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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2022 Linaro Ltd.
5 */
6
7/* DOC: IPA Interrupts
8 *
9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
10 * code. Whereas GSI interrupts are generally related to channel events (like
11 * transfer completions), IPA interrupts are related to other events related
12 * to the IPA. Some of the IPA interrupts come from a microcontroller
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
14 * acknowledged independent of the others.
15 *
16 * Two of the IPA interrupts are initiated by the microcontroller. A third
17 * can be generated to signal the need for a wakeup/resume when an IPA
18 * endpoint has been suspended. There are other IPA events, but at this
19 * time only these three are supported.
20 */
21
22#include <linux/types.h>
23#include <linux/interrupt.h>
24#include <linux/pm_runtime.h>
25#include <linux/pm_wakeirq.h>
26
27#include "ipa.h"
28#include "ipa_reg.h"
29#include "ipa_endpoint.h"
30#include "ipa_power.h"
31#include "ipa_uc.h"
32#include "ipa_interrupt.h"
33
34/**
35 * struct ipa_interrupt - IPA interrupt information
36 * @ipa: IPA pointer
37 * @irq: Linux IRQ number used for IPA interrupts
38 * @enabled: Mask indicating which interrupts are enabled
39 */
40struct ipa_interrupt {
41 struct ipa *ipa;
42 u32 irq;
43 u32 enabled;
44};
45
46/* Process a particular interrupt type that has been received */
47static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id)
48{
49 struct ipa *ipa = interrupt->ipa;
50 const struct reg *reg;
51 u32 mask = BIT(irq_id);
52 u32 offset;
53
54 reg = ipa_reg(ipa, IPA_IRQ_CLR);
55 offset = reg_offset(reg);
56
57 switch (irq_id) {
58 case IPA_IRQ_UC_0:
59 case IPA_IRQ_UC_1:
60 /* For microcontroller interrupts, clear the interrupt right
61 * away, "to avoid clearing unhandled interrupts."
62 */
63 iowrite32(mask, ipa->reg_virt + offset);
64 ipa_uc_interrupt_handler(ipa, irq_id);
65 break;
66
67 case IPA_IRQ_TX_SUSPEND:
68 /* Clearing the SUSPEND_TX interrupt also clears the
69 * register that tells us which suspended endpoint(s)
70 * caused the interrupt, so defer clearing until after
71 * the handler has been called.
72 */
73 ipa_power_suspend_handler(ipa, irq_id);
74 fallthrough;
75
76 default: /* Silently ignore (and clear) any other condition */
77 iowrite32(mask, ipa->reg_virt + offset);
78 break;
79 }
80}
81
82/* IPA IRQ handler is threaded */
83static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
84{
85 struct ipa_interrupt *interrupt = dev_id;
86 struct ipa *ipa = interrupt->ipa;
87 u32 enabled = interrupt->enabled;
88 const struct reg *reg;
89 struct device *dev;
90 u32 pending;
91 u32 offset;
92 u32 mask;
93 int ret;
94
95 dev = &ipa->pdev->dev;
96 ret = pm_runtime_get_sync(dev);
97 if (WARN_ON(ret < 0))
98 goto out_power_put;
99
100 /* The status register indicates which conditions are present,
101 * including conditions whose interrupt is not enabled. Handle
102 * only the enabled ones.
103 */
104 reg = ipa_reg(ipa, IPA_IRQ_STTS);
105 offset = reg_offset(reg);
106 pending = ioread32(ipa->reg_virt + offset);
107 while ((mask = pending & enabled)) {
108 do {
109 u32 irq_id = __ffs(mask);
110
111 mask ^= BIT(irq_id);
112
113 ipa_interrupt_process(interrupt, irq_id);
114 } while (mask);
115 pending = ioread32(ipa->reg_virt + offset);
116 }
117
118 /* If any disabled interrupts are pending, clear them */
119 if (pending) {
120 dev_dbg(dev, "clearing disabled IPA interrupts 0x%08x\n",
121 pending);
122 reg = ipa_reg(ipa, IPA_IRQ_CLR);
123 iowrite32(pending, ipa->reg_virt + reg_offset(reg));
124 }
125out_power_put:
126 pm_runtime_mark_last_busy(dev);
127 (void)pm_runtime_put_autosuspend(dev);
128
129 return IRQ_HANDLED;
130}
131
132static void ipa_interrupt_enabled_update(struct ipa *ipa)
133{
134 const struct reg *reg = ipa_reg(ipa, IPA_IRQ_EN);
135
136 iowrite32(ipa->interrupt->enabled, ipa->reg_virt + reg_offset(reg));
137}
138
139/* Enable an IPA interrupt type */
140void ipa_interrupt_enable(struct ipa *ipa, enum ipa_irq_id ipa_irq)
141{
142 /* Update the IPA interrupt mask to enable it */
143 ipa->interrupt->enabled |= BIT(ipa_irq);
144 ipa_interrupt_enabled_update(ipa);
145}
146
147/* Disable an IPA interrupt type */
148void ipa_interrupt_disable(struct ipa *ipa, enum ipa_irq_id ipa_irq)
149{
150 /* Update the IPA interrupt mask to disable it */
151 ipa->interrupt->enabled &= ~BIT(ipa_irq);
152 ipa_interrupt_enabled_update(ipa);
153}
154
155void ipa_interrupt_irq_disable(struct ipa *ipa)
156{
157 disable_irq(ipa->interrupt->irq);
158}
159
160void ipa_interrupt_irq_enable(struct ipa *ipa)
161{
162 enable_irq(ipa->interrupt->irq);
163}
164
165/* Common function used to enable/disable TX_SUSPEND for an endpoint */
166static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
167 u32 endpoint_id, bool enable)
168{
169 struct ipa *ipa = interrupt->ipa;
170 u32 mask = BIT(endpoint_id % 32);
171 u32 unit = endpoint_id / 32;
172 const struct reg *reg;
173 u32 offset;
174 u32 val;
175
176 WARN_ON(!test_bit(endpoint_id, ipa->available));
177
178 /* IPA version 3.0 does not support TX_SUSPEND interrupt control */
179 if (ipa->version == IPA_VERSION_3_0)
180 return;
181
182 reg = ipa_reg(ipa, IRQ_SUSPEND_EN);
183 offset = reg_n_offset(reg, unit);
184 val = ioread32(ipa->reg_virt + offset);
185
186 if (enable)
187 val |= mask;
188 else
189 val &= ~mask;
190
191 iowrite32(val, ipa->reg_virt + offset);
192}
193
194/* Enable TX_SUSPEND for an endpoint */
195void
196ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt, u32 endpoint_id)
197{
198 ipa_interrupt_suspend_control(interrupt, endpoint_id, true);
199}
200
201/* Disable TX_SUSPEND for an endpoint */
202void
203ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt, u32 endpoint_id)
204{
205 ipa_interrupt_suspend_control(interrupt, endpoint_id, false);
206}
207
208/* Clear the suspend interrupt for all endpoints that signaled it */
209void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt)
210{
211 struct ipa *ipa = interrupt->ipa;
212 u32 unit_count;
213 u32 unit;
214
215 unit_count = DIV_ROUND_UP(ipa->endpoint_count, 32);
216 for (unit = 0; unit < unit_count; unit++) {
217 const struct reg *reg;
218 u32 val;
219
220 reg = ipa_reg(ipa, IRQ_SUSPEND_INFO);
221 val = ioread32(ipa->reg_virt + reg_n_offset(reg, unit));
222
223 /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */
224 if (ipa->version == IPA_VERSION_3_0)
225 continue;
226
227 reg = ipa_reg(ipa, IRQ_SUSPEND_CLR);
228 iowrite32(val, ipa->reg_virt + reg_n_offset(reg, unit));
229 }
230}
231
232/* Simulate arrival of an IPA TX_SUSPEND interrupt */
233void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt)
234{
235 ipa_interrupt_process(interrupt, IPA_IRQ_TX_SUSPEND);
236}
237
238/* Configure the IPA interrupt framework */
239struct ipa_interrupt *ipa_interrupt_config(struct ipa *ipa)
240{
241 struct device *dev = &ipa->pdev->dev;
242 struct ipa_interrupt *interrupt;
243 const struct reg *reg;
244 unsigned int irq;
245 int ret;
246
247 ret = platform_get_irq_byname(ipa->pdev, "ipa");
248 if (ret <= 0) {
249 dev_err(dev, "DT error %d getting \"ipa\" IRQ property\n",
250 ret);
251 return ERR_PTR(ret ? : -EINVAL);
252 }
253 irq = ret;
254
255 interrupt = kzalloc(sizeof(*interrupt), GFP_KERNEL);
256 if (!interrupt)
257 return ERR_PTR(-ENOMEM);
258 interrupt->ipa = ipa;
259 interrupt->irq = irq;
260
261 /* Start with all IPA interrupts disabled */
262 reg = ipa_reg(ipa, IPA_IRQ_EN);
263 iowrite32(0, ipa->reg_virt + reg_offset(reg));
264
265 ret = request_threaded_irq(irq, NULL, ipa_isr_thread, IRQF_ONESHOT,
266 "ipa", interrupt);
267 if (ret) {
268 dev_err(dev, "error %d requesting \"ipa\" IRQ\n", ret);
269 goto err_kfree;
270 }
271
272 ret = dev_pm_set_wake_irq(dev, irq);
273 if (ret) {
274 dev_err(dev, "error %d registering \"ipa\" IRQ as wakeirq\n", ret);
275 goto err_free_irq;
276 }
277
278 return interrupt;
279
280err_free_irq:
281 free_irq(interrupt->irq, interrupt);
282err_kfree:
283 kfree(interrupt);
284
285 return ERR_PTR(ret);
286}
287
288/* Inverse of ipa_interrupt_config() */
289void ipa_interrupt_deconfig(struct ipa_interrupt *interrupt)
290{
291 struct device *dev = &interrupt->ipa->pdev->dev;
292
293 dev_pm_clear_wake_irq(dev);
294 free_irq(interrupt->irq, interrupt);
295 kfree(interrupt);
296}
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
4 * Copyright (C) 2018-2020 Linaro Ltd.
5 */
6
7/* DOC: IPA Interrupts
8 *
9 * The IPA has an interrupt line distinct from the interrupt used by the GSI
10 * code. Whereas GSI interrupts are generally related to channel events (like
11 * transfer completions), IPA interrupts are related to other events related
12 * to the IPA. Some of the IPA interrupts come from a microcontroller
13 * embedded in the IPA. Each IPA interrupt type can be both masked and
14 * acknowledged independent of the others.
15 *
16 * Two of the IPA interrupts are initiated by the microcontroller. A third
17 * can be generated to signal the need for a wakeup/resume when an IPA
18 * endpoint has been suspended. There are other IPA events, but at this
19 * time only these three are supported.
20 */
21
22#include <linux/types.h>
23#include <linux/interrupt.h>
24
25#include "ipa.h"
26#include "ipa_clock.h"
27#include "ipa_reg.h"
28#include "ipa_endpoint.h"
29#include "ipa_interrupt.h"
30
31/**
32 * struct ipa_interrupt - IPA interrupt information
33 * @ipa: IPA pointer
34 * @irq: Linux IRQ number used for IPA interrupts
35 * @enabled: Mask indicating which interrupts are enabled
36 * @handler: Array of handlers indexed by IPA interrupt ID
37 */
38struct ipa_interrupt {
39 struct ipa *ipa;
40 u32 irq;
41 u32 enabled;
42 ipa_irq_handler_t handler[IPA_IRQ_COUNT];
43};
44
45/* Returns true if the interrupt type is associated with the microcontroller */
46static bool ipa_interrupt_uc(struct ipa_interrupt *interrupt, u32 irq_id)
47{
48 return irq_id == IPA_IRQ_UC_0 || irq_id == IPA_IRQ_UC_1;
49}
50
51/* Process a particular interrupt type that has been received */
52static void ipa_interrupt_process(struct ipa_interrupt *interrupt, u32 irq_id)
53{
54 bool uc_irq = ipa_interrupt_uc(interrupt, irq_id);
55 struct ipa *ipa = interrupt->ipa;
56 u32 mask = BIT(irq_id);
57 u32 offset;
58
59 /* For microcontroller interrupts, clear the interrupt right away,
60 * "to avoid clearing unhandled interrupts."
61 */
62 offset = ipa_reg_irq_clr_offset(ipa->version);
63 if (uc_irq)
64 iowrite32(mask, ipa->reg_virt + offset);
65
66 if (irq_id < IPA_IRQ_COUNT && interrupt->handler[irq_id])
67 interrupt->handler[irq_id](interrupt->ipa, irq_id);
68
69 /* Clearing the SUSPEND_TX interrupt also clears the register
70 * that tells us which suspended endpoint(s) caused the interrupt,
71 * so defer clearing until after the handler has been called.
72 */
73 if (!uc_irq)
74 iowrite32(mask, ipa->reg_virt + offset);
75}
76
77/* Process all IPA interrupt types that have been signaled */
78static void ipa_interrupt_process_all(struct ipa_interrupt *interrupt)
79{
80 struct ipa *ipa = interrupt->ipa;
81 u32 enabled = interrupt->enabled;
82 u32 offset;
83 u32 mask;
84
85 /* The status register indicates which conditions are present,
86 * including conditions whose interrupt is not enabled. Handle
87 * only the enabled ones.
88 */
89 offset = ipa_reg_irq_stts_offset(ipa->version);
90 mask = ioread32(ipa->reg_virt + offset);
91 while ((mask &= enabled)) {
92 do {
93 u32 irq_id = __ffs(mask);
94
95 mask ^= BIT(irq_id);
96
97 ipa_interrupt_process(interrupt, irq_id);
98 } while (mask);
99 mask = ioread32(ipa->reg_virt + offset);
100 }
101}
102
103/* Threaded part of the IPA IRQ handler */
104static irqreturn_t ipa_isr_thread(int irq, void *dev_id)
105{
106 struct ipa_interrupt *interrupt = dev_id;
107
108 ipa_clock_get(interrupt->ipa);
109
110 ipa_interrupt_process_all(interrupt);
111
112 ipa_clock_put(interrupt->ipa);
113
114 return IRQ_HANDLED;
115}
116
117/* Hard part (i.e., "real" IRQ handler) of the IRQ handler */
118static irqreturn_t ipa_isr(int irq, void *dev_id)
119{
120 struct ipa_interrupt *interrupt = dev_id;
121 struct ipa *ipa = interrupt->ipa;
122 u32 offset;
123 u32 mask;
124
125 offset = ipa_reg_irq_stts_offset(ipa->version);
126 mask = ioread32(ipa->reg_virt + offset);
127 if (mask & interrupt->enabled)
128 return IRQ_WAKE_THREAD;
129
130 /* Nothing in the mask was supposed to cause an interrupt */
131 offset = ipa_reg_irq_clr_offset(ipa->version);
132 iowrite32(mask, ipa->reg_virt + offset);
133
134 dev_err(&ipa->pdev->dev, "%s: unexpected interrupt, mask 0x%08x\n",
135 __func__, mask);
136
137 return IRQ_HANDLED;
138}
139
140/* Common function used to enable/disable TX_SUSPEND for an endpoint */
141static void ipa_interrupt_suspend_control(struct ipa_interrupt *interrupt,
142 u32 endpoint_id, bool enable)
143{
144 struct ipa *ipa = interrupt->ipa;
145 u32 mask = BIT(endpoint_id);
146 u32 offset;
147 u32 val;
148
149 /* assert(mask & ipa->available); */
150
151 /* IPA version 3.0 does not support TX_SUSPEND interrupt control */
152 if (ipa->version == IPA_VERSION_3_0)
153 return;
154
155 offset = ipa_reg_irq_suspend_en_offset(ipa->version);
156 val = ioread32(ipa->reg_virt + offset);
157 if (enable)
158 val |= mask;
159 else
160 val &= ~mask;
161 iowrite32(val, ipa->reg_virt + offset);
162}
163
164/* Enable TX_SUSPEND for an endpoint */
165void
166ipa_interrupt_suspend_enable(struct ipa_interrupt *interrupt, u32 endpoint_id)
167{
168 ipa_interrupt_suspend_control(interrupt, endpoint_id, true);
169}
170
171/* Disable TX_SUSPEND for an endpoint */
172void
173ipa_interrupt_suspend_disable(struct ipa_interrupt *interrupt, u32 endpoint_id)
174{
175 ipa_interrupt_suspend_control(interrupt, endpoint_id, false);
176}
177
178/* Clear the suspend interrupt for all endpoints that signaled it */
179void ipa_interrupt_suspend_clear_all(struct ipa_interrupt *interrupt)
180{
181 struct ipa *ipa = interrupt->ipa;
182 u32 offset;
183 u32 val;
184
185 offset = ipa_reg_irq_suspend_info_offset(ipa->version);
186 val = ioread32(ipa->reg_virt + offset);
187
188 /* SUSPEND interrupt status isn't cleared on IPA version 3.0 */
189 if (ipa->version == IPA_VERSION_3_0)
190 return;
191
192 offset = ipa_reg_irq_suspend_clr_offset(ipa->version);
193 iowrite32(val, ipa->reg_virt + offset);
194}
195
196/* Simulate arrival of an IPA TX_SUSPEND interrupt */
197void ipa_interrupt_simulate_suspend(struct ipa_interrupt *interrupt)
198{
199 ipa_interrupt_process(interrupt, IPA_IRQ_TX_SUSPEND);
200}
201
202/* Add a handler for an IPA interrupt */
203void ipa_interrupt_add(struct ipa_interrupt *interrupt,
204 enum ipa_irq_id ipa_irq, ipa_irq_handler_t handler)
205{
206 struct ipa *ipa = interrupt->ipa;
207 u32 offset;
208
209 /* assert(ipa_irq < IPA_IRQ_COUNT); */
210 interrupt->handler[ipa_irq] = handler;
211
212 /* Update the IPA interrupt mask to enable it */
213 interrupt->enabled |= BIT(ipa_irq);
214 offset = ipa_reg_irq_en_offset(ipa->version);
215 iowrite32(interrupt->enabled, ipa->reg_virt + offset);
216}
217
218/* Remove the handler for an IPA interrupt type */
219void
220ipa_interrupt_remove(struct ipa_interrupt *interrupt, enum ipa_irq_id ipa_irq)
221{
222 struct ipa *ipa = interrupt->ipa;
223 u32 offset;
224
225 /* assert(ipa_irq < IPA_IRQ_COUNT); */
226 /* Update the IPA interrupt mask to disable it */
227 interrupt->enabled &= ~BIT(ipa_irq);
228 offset = ipa_reg_irq_en_offset(ipa->version);
229 iowrite32(interrupt->enabled, ipa->reg_virt + offset);
230
231 interrupt->handler[ipa_irq] = NULL;
232}
233
234/* Set up the IPA interrupt framework */
235struct ipa_interrupt *ipa_interrupt_setup(struct ipa *ipa)
236{
237 struct device *dev = &ipa->pdev->dev;
238 struct ipa_interrupt *interrupt;
239 unsigned int irq;
240 u32 offset;
241 int ret;
242
243 ret = platform_get_irq_byname(ipa->pdev, "ipa");
244 if (ret <= 0) {
245 dev_err(dev, "DT error %d getting \"ipa\" IRQ property\n",
246 ret);
247 return ERR_PTR(ret ? : -EINVAL);
248 }
249 irq = ret;
250
251 interrupt = kzalloc(sizeof(*interrupt), GFP_KERNEL);
252 if (!interrupt)
253 return ERR_PTR(-ENOMEM);
254 interrupt->ipa = ipa;
255 interrupt->irq = irq;
256
257 /* Start with all IPA interrupts disabled */
258 offset = ipa_reg_irq_en_offset(ipa->version);
259 iowrite32(0, ipa->reg_virt + offset);
260
261 ret = request_threaded_irq(irq, ipa_isr, ipa_isr_thread, IRQF_ONESHOT,
262 "ipa", interrupt);
263 if (ret) {
264 dev_err(dev, "error %d requesting \"ipa\" IRQ\n", ret);
265 goto err_kfree;
266 }
267
268 ret = enable_irq_wake(irq);
269 if (ret) {
270 dev_err(dev, "error %d enabling wakeup for \"ipa\" IRQ\n", ret);
271 goto err_free_irq;
272 }
273
274 return interrupt;
275
276err_free_irq:
277 free_irq(interrupt->irq, interrupt);
278err_kfree:
279 kfree(interrupt);
280
281 return ERR_PTR(ret);
282}
283
284/* Tear down the IPA interrupt framework */
285void ipa_interrupt_teardown(struct ipa_interrupt *interrupt)
286{
287 struct device *dev = &interrupt->ipa->pdev->dev;
288 int ret;
289
290 ret = disable_irq_wake(interrupt->irq);
291 if (ret)
292 dev_err(dev, "error %d disabling \"ipa\" IRQ wakeup\n", ret);
293 free_irq(interrupt->irq, interrupt);
294 kfree(interrupt);
295}