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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
3 *
4 * Inspired by dwc3-of-simple.c
5 */
6
7#include <linux/acpi.h>
8#include <linux/io.h>
9#include <linux/of.h>
10#include <linux/clk.h>
11#include <linux/irq.h>
12#include <linux/of_clk.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/extcon.h>
16#include <linux/interconnect.h>
17#include <linux/of_platform.h>
18#include <linux/platform_device.h>
19#include <linux/phy/phy.h>
20#include <linux/usb/of.h>
21#include <linux/reset.h>
22#include <linux/iopoll.h>
23#include <linux/usb/hcd.h>
24#include <linux/usb.h>
25#include "core.h"
26
27/* USB QSCRATCH Hardware registers */
28#define QSCRATCH_HS_PHY_CTRL 0x10
29#define UTMI_OTG_VBUS_VALID BIT(20)
30#define SW_SESSVLD_SEL BIT(28)
31
32#define QSCRATCH_SS_PHY_CTRL 0x30
33#define LANE0_PWR_PRESENT BIT(24)
34
35#define QSCRATCH_GENERAL_CFG 0x08
36#define PIPE_UTMI_CLK_SEL BIT(0)
37#define PIPE3_PHYSTATUS_SW BIT(3)
38#define PIPE_UTMI_CLK_DIS BIT(8)
39
40#define PWR_EVNT_IRQ_STAT_REG 0x58
41#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
42#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
43
44#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
45#define SDM845_QSCRATCH_SIZE 0x400
46#define SDM845_DWC3_CORE_SIZE 0xcd00
47
48/* Interconnect path bandwidths in MBps */
49#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
50#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
51#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
52#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
53#define APPS_USB_AVG_BW 0
54#define APPS_USB_PEAK_BW MBps_to_icc(40)
55
56struct dwc3_acpi_pdata {
57 u32 qscratch_base_offset;
58 u32 qscratch_base_size;
59 u32 dwc3_core_base_size;
60 int qusb2_phy_irq_index;
61 int dp_hs_phy_irq_index;
62 int dm_hs_phy_irq_index;
63 int ss_phy_irq_index;
64 bool is_urs;
65};
66
67struct dwc3_qcom {
68 struct device *dev;
69 void __iomem *qscratch_base;
70 struct platform_device *dwc3;
71 struct platform_device *urs_usb;
72 struct clk **clks;
73 int num_clocks;
74 struct reset_control *resets;
75
76 int qusb2_phy_irq;
77 int dp_hs_phy_irq;
78 int dm_hs_phy_irq;
79 int ss_phy_irq;
80 enum usb_device_speed usb2_speed;
81
82 struct extcon_dev *edev;
83 struct extcon_dev *host_edev;
84 struct notifier_block vbus_nb;
85 struct notifier_block host_nb;
86
87 const struct dwc3_acpi_pdata *acpi_pdata;
88
89 enum usb_dr_mode mode;
90 bool is_suspended;
91 bool pm_suspended;
92 struct icc_path *icc_path_ddr;
93 struct icc_path *icc_path_apps;
94};
95
96static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
97{
98 u32 reg;
99
100 reg = readl(base + offset);
101 reg |= val;
102 writel(reg, base + offset);
103
104 /* ensure that above write is through */
105 readl(base + offset);
106}
107
108static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
109{
110 u32 reg;
111
112 reg = readl(base + offset);
113 reg &= ~val;
114 writel(reg, base + offset);
115
116 /* ensure that above write is through */
117 readl(base + offset);
118}
119
120static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
121{
122 if (enable) {
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
124 LANE0_PWR_PRESENT);
125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
126 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
127 } else {
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
129 LANE0_PWR_PRESENT);
130 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
131 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
132 }
133}
134
135static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
136 unsigned long event, void *ptr)
137{
138 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
139
140 /* enable vbus override for device mode */
141 dwc3_qcom_vbus_override_enable(qcom, event);
142 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
143
144 return NOTIFY_DONE;
145}
146
147static int dwc3_qcom_host_notifier(struct notifier_block *nb,
148 unsigned long event, void *ptr)
149{
150 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
151
152 /* disable vbus override in host mode */
153 dwc3_qcom_vbus_override_enable(qcom, !event);
154 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
155
156 return NOTIFY_DONE;
157}
158
159static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
160{
161 struct device *dev = qcom->dev;
162 struct extcon_dev *host_edev;
163 int ret;
164
165 if (!of_property_read_bool(dev->of_node, "extcon"))
166 return 0;
167
168 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
169 if (IS_ERR(qcom->edev))
170 return dev_err_probe(dev, PTR_ERR(qcom->edev),
171 "Failed to get extcon\n");
172
173 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
174
175 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
176 if (IS_ERR(qcom->host_edev))
177 qcom->host_edev = NULL;
178
179 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
180 &qcom->vbus_nb);
181 if (ret < 0) {
182 dev_err(dev, "VBUS notifier register failed\n");
183 return ret;
184 }
185
186 if (qcom->host_edev)
187 host_edev = qcom->host_edev;
188 else
189 host_edev = qcom->edev;
190
191 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
192 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
193 &qcom->host_nb);
194 if (ret < 0) {
195 dev_err(dev, "Host notifier register failed\n");
196 return ret;
197 }
198
199 /* Update initial VBUS override based on extcon state */
200 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
201 !extcon_get_state(host_edev, EXTCON_USB_HOST))
202 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
203 else
204 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
205
206 return 0;
207}
208
209static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
210{
211 int ret;
212
213 ret = icc_enable(qcom->icc_path_ddr);
214 if (ret)
215 return ret;
216
217 ret = icc_enable(qcom->icc_path_apps);
218 if (ret)
219 icc_disable(qcom->icc_path_ddr);
220
221 return ret;
222}
223
224static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
225{
226 int ret;
227
228 ret = icc_disable(qcom->icc_path_ddr);
229 if (ret)
230 return ret;
231
232 ret = icc_disable(qcom->icc_path_apps);
233 if (ret)
234 icc_enable(qcom->icc_path_ddr);
235
236 return ret;
237}
238
239/**
240 * dwc3_qcom_interconnect_init() - Get interconnect path handles
241 * and set bandwidth.
242 * @qcom: Pointer to the concerned usb core.
243 *
244 */
245static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
246{
247 enum usb_device_speed max_speed;
248 struct device *dev = qcom->dev;
249 int ret;
250
251 if (has_acpi_companion(dev))
252 return 0;
253
254 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
255 if (IS_ERR(qcom->icc_path_ddr)) {
256 return dev_err_probe(dev, PTR_ERR(qcom->icc_path_ddr),
257 "failed to get usb-ddr path\n");
258 }
259
260 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
261 if (IS_ERR(qcom->icc_path_apps)) {
262 ret = dev_err_probe(dev, PTR_ERR(qcom->icc_path_apps),
263 "failed to get apps-usb path\n");
264 goto put_path_ddr;
265 }
266
267 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev);
268 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) {
269 ret = icc_set_bw(qcom->icc_path_ddr,
270 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
271 } else {
272 ret = icc_set_bw(qcom->icc_path_ddr,
273 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
274 }
275 if (ret) {
276 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
277 goto put_path_apps;
278 }
279
280 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
281 if (ret) {
282 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
283 goto put_path_apps;
284 }
285
286 return 0;
287
288put_path_apps:
289 icc_put(qcom->icc_path_apps);
290put_path_ddr:
291 icc_put(qcom->icc_path_ddr);
292 return ret;
293}
294
295/**
296 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
297 * @qcom: Pointer to the concerned usb core.
298 *
299 * This function is used to release interconnect path handle.
300 */
301static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
302{
303 icc_put(qcom->icc_path_ddr);
304 icc_put(qcom->icc_path_apps);
305}
306
307/* Only usable in contexts where the role can not change. */
308static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
309{
310 struct dwc3 *dwc;
311
312 /*
313 * FIXME: Fix this layering violation.
314 */
315 dwc = platform_get_drvdata(qcom->dwc3);
316
317 /* Core driver may not have probed yet. */
318 if (!dwc)
319 return false;
320
321 return dwc->xhci;
322}
323
324static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
325{
326 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
327 struct usb_device *udev;
328 struct usb_hcd __maybe_unused *hcd;
329
330 /*
331 * FIXME: Fix this layering violation.
332 */
333 hcd = platform_get_drvdata(dwc->xhci);
334
335 /*
336 * It is possible to query the speed of all children of
337 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
338 * currently supports only 1 port per controller. So
339 * this is sufficient.
340 */
341#ifdef CONFIG_USB
342 udev = usb_hub_find_child(hcd->self.root_hub, 1);
343#else
344 udev = NULL;
345#endif
346 if (!udev)
347 return USB_SPEED_UNKNOWN;
348
349 return udev->speed;
350}
351
352static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity)
353{
354 if (!irq)
355 return;
356
357 if (polarity)
358 irq_set_irq_type(irq, polarity);
359
360 enable_irq(irq);
361 enable_irq_wake(irq);
362}
363
364static void dwc3_qcom_disable_wakeup_irq(int irq)
365{
366 if (!irq)
367 return;
368
369 disable_irq_wake(irq);
370 disable_irq_nosync(irq);
371}
372
373static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
374{
375 dwc3_qcom_disable_wakeup_irq(qcom->qusb2_phy_irq);
376
377 if (qcom->usb2_speed == USB_SPEED_LOW) {
378 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
379 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
380 (qcom->usb2_speed == USB_SPEED_FULL)) {
381 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
382 } else {
383 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
384 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
385 }
386
387 dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
388}
389
390static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
391{
392 dwc3_qcom_enable_wakeup_irq(qcom->qusb2_phy_irq, 0);
393
394 /*
395 * Configure DP/DM line interrupts based on the USB2 device attached to
396 * the root hub port. When HS/FS device is connected, configure the DP line
397 * as falling edge to detect both disconnect and remote wakeup scenarios. When
398 * LS device is connected, configure DM line as falling edge to detect both
399 * disconnect and remote wakeup. When no device is connected, configure both
400 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
401 */
402
403 if (qcom->usb2_speed == USB_SPEED_LOW) {
404 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
405 IRQ_TYPE_EDGE_FALLING);
406 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
407 (qcom->usb2_speed == USB_SPEED_FULL)) {
408 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
409 IRQ_TYPE_EDGE_FALLING);
410 } else {
411 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
412 IRQ_TYPE_EDGE_RISING);
413 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
414 IRQ_TYPE_EDGE_RISING);
415 }
416
417 dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
418}
419
420static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
421{
422 u32 val;
423 int i, ret;
424
425 if (qcom->is_suspended)
426 return 0;
427
428 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
429 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
430 dev_err(qcom->dev, "HS-PHY not in L2\n");
431
432 for (i = qcom->num_clocks - 1; i >= 0; i--)
433 clk_disable_unprepare(qcom->clks[i]);
434
435 ret = dwc3_qcom_interconnect_disable(qcom);
436 if (ret)
437 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
438
439 /*
440 * The role is stable during suspend as role switching is done from a
441 * freezable workqueue.
442 */
443 if (dwc3_qcom_is_host(qcom) && wakeup) {
444 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
445 dwc3_qcom_enable_interrupts(qcom);
446 }
447
448 qcom->is_suspended = true;
449
450 return 0;
451}
452
453static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
454{
455 int ret;
456 int i;
457
458 if (!qcom->is_suspended)
459 return 0;
460
461 if (dwc3_qcom_is_host(qcom) && wakeup)
462 dwc3_qcom_disable_interrupts(qcom);
463
464 for (i = 0; i < qcom->num_clocks; i++) {
465 ret = clk_prepare_enable(qcom->clks[i]);
466 if (ret < 0) {
467 while (--i >= 0)
468 clk_disable_unprepare(qcom->clks[i]);
469 return ret;
470 }
471 }
472
473 ret = dwc3_qcom_interconnect_enable(qcom);
474 if (ret)
475 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
476
477 /* Clear existing events from PHY related to L2 in/out */
478 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
479 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
480
481 qcom->is_suspended = false;
482
483 return 0;
484}
485
486static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
487{
488 struct dwc3_qcom *qcom = data;
489 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
490
491 /* If pm_suspended then let pm_resume take care of resuming h/w */
492 if (qcom->pm_suspended)
493 return IRQ_HANDLED;
494
495 /*
496 * This is safe as role switching is done from a freezable workqueue
497 * and the wakeup interrupts are disabled as part of resume.
498 */
499 if (dwc3_qcom_is_host(qcom))
500 pm_runtime_resume(&dwc->xhci->dev);
501
502 return IRQ_HANDLED;
503}
504
505static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
506{
507 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
508 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
509 PIPE_UTMI_CLK_DIS);
510
511 usleep_range(100, 1000);
512
513 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
514 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
515
516 usleep_range(100, 1000);
517
518 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
519 PIPE_UTMI_CLK_DIS);
520}
521
522static int dwc3_qcom_get_irq(struct platform_device *pdev,
523 const char *name, int num)
524{
525 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
526 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
527 struct device_node *np = pdev->dev.of_node;
528 int ret;
529
530 if (np)
531 ret = platform_get_irq_byname_optional(pdev_irq, name);
532 else
533 ret = platform_get_irq_optional(pdev_irq, num);
534
535 return ret;
536}
537
538static int dwc3_qcom_setup_irq(struct platform_device *pdev)
539{
540 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
541 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
542 int irq;
543 int ret;
544
545 irq = dwc3_qcom_get_irq(pdev, "qusb2_phy",
546 pdata ? pdata->qusb2_phy_irq_index : -1);
547 if (irq > 0) {
548 /* Keep wakeup interrupts disabled until suspend */
549 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
550 qcom_dwc3_resume_irq,
551 IRQF_ONESHOT | IRQF_NO_AUTOEN,
552 "qcom_dwc3 QUSB2", qcom);
553 if (ret) {
554 dev_err(qcom->dev, "qusb2_phy_irq failed: %d\n", ret);
555 return ret;
556 }
557 qcom->qusb2_phy_irq = irq;
558 }
559
560 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
561 pdata ? pdata->dp_hs_phy_irq_index : -1);
562 if (irq > 0) {
563 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
564 qcom_dwc3_resume_irq,
565 IRQF_ONESHOT | IRQF_NO_AUTOEN,
566 "qcom_dwc3 DP_HS", qcom);
567 if (ret) {
568 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
569 return ret;
570 }
571 qcom->dp_hs_phy_irq = irq;
572 }
573
574 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
575 pdata ? pdata->dm_hs_phy_irq_index : -1);
576 if (irq > 0) {
577 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
578 qcom_dwc3_resume_irq,
579 IRQF_ONESHOT | IRQF_NO_AUTOEN,
580 "qcom_dwc3 DM_HS", qcom);
581 if (ret) {
582 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
583 return ret;
584 }
585 qcom->dm_hs_phy_irq = irq;
586 }
587
588 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
589 pdata ? pdata->ss_phy_irq_index : -1);
590 if (irq > 0) {
591 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
592 qcom_dwc3_resume_irq,
593 IRQF_ONESHOT | IRQF_NO_AUTOEN,
594 "qcom_dwc3 SS", qcom);
595 if (ret) {
596 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
597 return ret;
598 }
599 qcom->ss_phy_irq = irq;
600 }
601
602 return 0;
603}
604
605static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
606{
607 struct device *dev = qcom->dev;
608 struct device_node *np = dev->of_node;
609 int i;
610
611 if (!np || !count)
612 return 0;
613
614 if (count < 0)
615 return count;
616
617 qcom->num_clocks = count;
618
619 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
620 sizeof(struct clk *), GFP_KERNEL);
621 if (!qcom->clks)
622 return -ENOMEM;
623
624 for (i = 0; i < qcom->num_clocks; i++) {
625 struct clk *clk;
626 int ret;
627
628 clk = of_clk_get(np, i);
629 if (IS_ERR(clk)) {
630 while (--i >= 0)
631 clk_put(qcom->clks[i]);
632 return PTR_ERR(clk);
633 }
634
635 ret = clk_prepare_enable(clk);
636 if (ret < 0) {
637 while (--i >= 0) {
638 clk_disable_unprepare(qcom->clks[i]);
639 clk_put(qcom->clks[i]);
640 }
641 clk_put(clk);
642
643 return ret;
644 }
645
646 qcom->clks[i] = clk;
647 }
648
649 return 0;
650}
651
652static const struct property_entry dwc3_qcom_acpi_properties[] = {
653 PROPERTY_ENTRY_STRING("dr_mode", "host"),
654 {}
655};
656
657static const struct software_node dwc3_qcom_swnode = {
658 .properties = dwc3_qcom_acpi_properties,
659};
660
661static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
662{
663 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
664 struct device *dev = &pdev->dev;
665 struct resource *res, *child_res = NULL;
666 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
667 pdev;
668 int irq;
669 int ret;
670
671 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
672 if (!qcom->dwc3)
673 return -ENOMEM;
674
675 qcom->dwc3->dev.parent = dev;
676 qcom->dwc3->dev.type = dev->type;
677 qcom->dwc3->dev.dma_mask = dev->dma_mask;
678 qcom->dwc3->dev.dma_parms = dev->dma_parms;
679 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
680
681 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
682 if (!child_res) {
683 platform_device_put(qcom->dwc3);
684 return -ENOMEM;
685 }
686
687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
688 if (!res) {
689 dev_err(&pdev->dev, "failed to get memory resource\n");
690 ret = -ENODEV;
691 goto out;
692 }
693
694 child_res[0].flags = res->flags;
695 child_res[0].start = res->start;
696 child_res[0].end = child_res[0].start +
697 qcom->acpi_pdata->dwc3_core_base_size;
698
699 irq = platform_get_irq(pdev_irq, 0);
700 if (irq < 0) {
701 ret = irq;
702 goto out;
703 }
704 child_res[1].flags = IORESOURCE_IRQ;
705 child_res[1].start = child_res[1].end = irq;
706
707 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
708 if (ret) {
709 dev_err(&pdev->dev, "failed to add resources\n");
710 goto out;
711 }
712
713 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
714 if (ret < 0) {
715 dev_err(&pdev->dev, "failed to add properties\n");
716 goto out;
717 }
718
719 ret = platform_device_add(qcom->dwc3);
720 if (ret) {
721 dev_err(&pdev->dev, "failed to add device\n");
722 device_remove_software_node(&qcom->dwc3->dev);
723 goto out;
724 }
725 kfree(child_res);
726 return 0;
727
728out:
729 platform_device_put(qcom->dwc3);
730 kfree(child_res);
731 return ret;
732}
733
734static int dwc3_qcom_of_register_core(struct platform_device *pdev)
735{
736 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
737 struct device_node *np = pdev->dev.of_node, *dwc3_np;
738 struct device *dev = &pdev->dev;
739 int ret;
740
741 dwc3_np = of_get_compatible_child(np, "snps,dwc3");
742 if (!dwc3_np) {
743 dev_err(dev, "failed to find dwc3 core child\n");
744 return -ENODEV;
745 }
746
747 ret = of_platform_populate(np, NULL, NULL, dev);
748 if (ret) {
749 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
750 goto node_put;
751 }
752
753 qcom->dwc3 = of_find_device_by_node(dwc3_np);
754 if (!qcom->dwc3) {
755 ret = -ENODEV;
756 dev_err(dev, "failed to get dwc3 platform device\n");
757 of_platform_depopulate(dev);
758 }
759
760node_put:
761 of_node_put(dwc3_np);
762
763 return ret;
764}
765
766static struct platform_device *dwc3_qcom_create_urs_usb_platdev(struct device *dev)
767{
768 struct platform_device *urs_usb = NULL;
769 struct fwnode_handle *fwh;
770 struct acpi_device *adev;
771 char name[8];
772 int ret;
773 int id;
774
775 /* Figure out device id */
776 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
777 if (!ret)
778 return NULL;
779
780 /* Find the child using name */
781 snprintf(name, sizeof(name), "USB%d", id);
782 fwh = fwnode_get_named_child_node(dev->fwnode, name);
783 if (!fwh)
784 return NULL;
785
786 adev = to_acpi_device_node(fwh);
787 if (!adev)
788 goto err_put_handle;
789
790 urs_usb = acpi_create_platform_device(adev, NULL);
791 if (IS_ERR_OR_NULL(urs_usb))
792 goto err_put_handle;
793
794 return urs_usb;
795
796err_put_handle:
797 fwnode_handle_put(fwh);
798
799 return urs_usb;
800}
801
802static void dwc3_qcom_destroy_urs_usb_platdev(struct platform_device *urs_usb)
803{
804 struct fwnode_handle *fwh = urs_usb->dev.fwnode;
805
806 platform_device_unregister(urs_usb);
807 fwnode_handle_put(fwh);
808}
809
810static int dwc3_qcom_probe(struct platform_device *pdev)
811{
812 struct device_node *np = pdev->dev.of_node;
813 struct device *dev = &pdev->dev;
814 struct dwc3_qcom *qcom;
815 struct resource *res, *parent_res = NULL;
816 struct resource local_res;
817 int ret, i;
818 bool ignore_pipe_clk;
819 bool wakeup_source;
820
821 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
822 if (!qcom)
823 return -ENOMEM;
824
825 platform_set_drvdata(pdev, qcom);
826 qcom->dev = &pdev->dev;
827
828 if (has_acpi_companion(dev)) {
829 qcom->acpi_pdata = acpi_device_get_match_data(dev);
830 if (!qcom->acpi_pdata) {
831 dev_err(&pdev->dev, "no supporting ACPI device data\n");
832 return -EINVAL;
833 }
834 }
835
836 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
837 if (IS_ERR(qcom->resets)) {
838 return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
839 "failed to get resets\n");
840 }
841
842 ret = reset_control_assert(qcom->resets);
843 if (ret) {
844 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
845 return ret;
846 }
847
848 usleep_range(10, 1000);
849
850 ret = reset_control_deassert(qcom->resets);
851 if (ret) {
852 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
853 goto reset_assert;
854 }
855
856 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
857 if (ret) {
858 dev_err_probe(dev, ret, "failed to get clocks\n");
859 goto reset_assert;
860 }
861
862 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
863
864 if (np) {
865 parent_res = res;
866 } else {
867 memcpy(&local_res, res, sizeof(struct resource));
868 parent_res = &local_res;
869
870 parent_res->start = res->start +
871 qcom->acpi_pdata->qscratch_base_offset;
872 parent_res->end = parent_res->start +
873 qcom->acpi_pdata->qscratch_base_size;
874
875 if (qcom->acpi_pdata->is_urs) {
876 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
877 if (IS_ERR_OR_NULL(qcom->urs_usb)) {
878 dev_err(dev, "failed to create URS USB platdev\n");
879 if (!qcom->urs_usb)
880 ret = -ENODEV;
881 else
882 ret = PTR_ERR(qcom->urs_usb);
883 goto clk_disable;
884 }
885 }
886 }
887
888 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
889 if (IS_ERR(qcom->qscratch_base)) {
890 ret = PTR_ERR(qcom->qscratch_base);
891 goto free_urs;
892 }
893
894 ret = dwc3_qcom_setup_irq(pdev);
895 if (ret) {
896 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
897 goto free_urs;
898 }
899
900 /*
901 * Disable pipe_clk requirement if specified. Used when dwc3
902 * operates without SSPHY and only HS/FS/LS modes are supported.
903 */
904 ignore_pipe_clk = device_property_read_bool(dev,
905 "qcom,select-utmi-as-pipe-clk");
906 if (ignore_pipe_clk)
907 dwc3_qcom_select_utmi_clk(qcom);
908
909 if (np)
910 ret = dwc3_qcom_of_register_core(pdev);
911 else
912 ret = dwc3_qcom_acpi_register_core(pdev);
913
914 if (ret) {
915 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
916 goto free_urs;
917 }
918
919 ret = dwc3_qcom_interconnect_init(qcom);
920 if (ret)
921 goto depopulate;
922
923 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
924
925 /* enable vbus override for device mode */
926 if (qcom->mode != USB_DR_MODE_HOST)
927 dwc3_qcom_vbus_override_enable(qcom, true);
928
929 /* register extcon to override sw_vbus on Vbus change later */
930 ret = dwc3_qcom_register_extcon(qcom);
931 if (ret)
932 goto interconnect_exit;
933
934 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source");
935 device_init_wakeup(&pdev->dev, wakeup_source);
936 device_init_wakeup(&qcom->dwc3->dev, wakeup_source);
937
938 qcom->is_suspended = false;
939 pm_runtime_set_active(dev);
940 pm_runtime_enable(dev);
941 pm_runtime_forbid(dev);
942
943 return 0;
944
945interconnect_exit:
946 dwc3_qcom_interconnect_exit(qcom);
947depopulate:
948 if (np) {
949 of_platform_depopulate(&pdev->dev);
950 } else {
951 device_remove_software_node(&qcom->dwc3->dev);
952 platform_device_del(qcom->dwc3);
953 }
954 platform_device_put(qcom->dwc3);
955free_urs:
956 if (qcom->urs_usb)
957 dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb);
958clk_disable:
959 for (i = qcom->num_clocks - 1; i >= 0; i--) {
960 clk_disable_unprepare(qcom->clks[i]);
961 clk_put(qcom->clks[i]);
962 }
963reset_assert:
964 reset_control_assert(qcom->resets);
965
966 return ret;
967}
968
969static void dwc3_qcom_remove(struct platform_device *pdev)
970{
971 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
972 struct device_node *np = pdev->dev.of_node;
973 struct device *dev = &pdev->dev;
974 int i;
975
976 if (np) {
977 of_platform_depopulate(&pdev->dev);
978 } else {
979 device_remove_software_node(&qcom->dwc3->dev);
980 platform_device_del(qcom->dwc3);
981 }
982 platform_device_put(qcom->dwc3);
983
984 if (qcom->urs_usb)
985 dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb);
986
987 for (i = qcom->num_clocks - 1; i >= 0; i--) {
988 clk_disable_unprepare(qcom->clks[i]);
989 clk_put(qcom->clks[i]);
990 }
991 qcom->num_clocks = 0;
992
993 dwc3_qcom_interconnect_exit(qcom);
994 reset_control_assert(qcom->resets);
995
996 pm_runtime_allow(dev);
997 pm_runtime_disable(dev);
998}
999
1000static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
1001{
1002 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1003 bool wakeup = device_may_wakeup(dev);
1004 int ret;
1005
1006 ret = dwc3_qcom_suspend(qcom, wakeup);
1007 if (ret)
1008 return ret;
1009
1010 qcom->pm_suspended = true;
1011
1012 return 0;
1013}
1014
1015static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
1016{
1017 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1018 bool wakeup = device_may_wakeup(dev);
1019 int ret;
1020
1021 ret = dwc3_qcom_resume(qcom, wakeup);
1022 if (ret)
1023 return ret;
1024
1025 qcom->pm_suspended = false;
1026
1027 return 0;
1028}
1029
1030static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
1031{
1032 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1033
1034 return dwc3_qcom_suspend(qcom, true);
1035}
1036
1037static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
1038{
1039 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1040
1041 return dwc3_qcom_resume(qcom, true);
1042}
1043
1044static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
1045 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
1046 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
1047 NULL)
1048};
1049
1050static const struct of_device_id dwc3_qcom_of_match[] = {
1051 { .compatible = "qcom,dwc3" },
1052 { }
1053};
1054MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
1055
1056#ifdef CONFIG_ACPI
1057static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
1058 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1059 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1060 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1061 .qusb2_phy_irq_index = 1,
1062 .dp_hs_phy_irq_index = 4,
1063 .dm_hs_phy_irq_index = 3,
1064 .ss_phy_irq_index = 2
1065};
1066
1067static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
1068 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1069 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1070 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1071 .qusb2_phy_irq_index = 1,
1072 .dp_hs_phy_irq_index = 4,
1073 .dm_hs_phy_irq_index = 3,
1074 .ss_phy_irq_index = 2,
1075 .is_urs = true,
1076};
1077
1078static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
1079 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
1080 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
1081 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
1082 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
1083 { },
1084};
1085MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
1086#endif
1087
1088static struct platform_driver dwc3_qcom_driver = {
1089 .probe = dwc3_qcom_probe,
1090 .remove_new = dwc3_qcom_remove,
1091 .driver = {
1092 .name = "dwc3-qcom",
1093 .pm = &dwc3_qcom_dev_pm_ops,
1094 .of_match_table = dwc3_qcom_of_match,
1095 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
1096 },
1097};
1098
1099module_platform_driver(dwc3_qcom_driver);
1100
1101MODULE_LICENSE("GPL v2");
1102MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
3 *
4 * Inspired by dwc3-of-simple.c
5 */
6
7#include <linux/cleanup.h>
8#include <linux/io.h>
9#include <linux/of.h>
10#include <linux/clk.h>
11#include <linux/irq.h>
12#include <linux/of_clk.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/extcon.h>
16#include <linux/interconnect.h>
17#include <linux/of_platform.h>
18#include <linux/platform_device.h>
19#include <linux/phy/phy.h>
20#include <linux/usb/of.h>
21#include <linux/reset.h>
22#include <linux/iopoll.h>
23#include <linux/usb/hcd.h>
24#include <linux/usb.h>
25#include "core.h"
26
27/* USB QSCRATCH Hardware registers */
28#define QSCRATCH_HS_PHY_CTRL 0x10
29#define UTMI_OTG_VBUS_VALID BIT(20)
30#define SW_SESSVLD_SEL BIT(28)
31
32#define QSCRATCH_SS_PHY_CTRL 0x30
33#define LANE0_PWR_PRESENT BIT(24)
34
35#define QSCRATCH_GENERAL_CFG 0x08
36#define PIPE_UTMI_CLK_SEL BIT(0)
37#define PIPE3_PHYSTATUS_SW BIT(3)
38#define PIPE_UTMI_CLK_DIS BIT(8)
39
40#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
41#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
42
43#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
44#define SDM845_QSCRATCH_SIZE 0x400
45#define SDM845_DWC3_CORE_SIZE 0xcd00
46
47/* Interconnect path bandwidths in MBps */
48#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
49#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
50#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
51#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
52#define APPS_USB_AVG_BW 0
53#define APPS_USB_PEAK_BW MBps_to_icc(40)
54
55/* Qualcomm SoCs with multiport support has up to 4 ports */
56#define DWC3_QCOM_MAX_PORTS 4
57
58static const u32 pwr_evnt_irq_stat_reg[DWC3_QCOM_MAX_PORTS] = {
59 0x58,
60 0x1dc,
61 0x228,
62 0x238,
63};
64
65struct dwc3_qcom_port {
66 int qusb2_phy_irq;
67 int dp_hs_phy_irq;
68 int dm_hs_phy_irq;
69 int ss_phy_irq;
70 enum usb_device_speed usb2_speed;
71};
72
73struct dwc3_qcom {
74 struct device *dev;
75 void __iomem *qscratch_base;
76 struct platform_device *dwc3;
77 struct clk **clks;
78 int num_clocks;
79 struct reset_control *resets;
80 struct dwc3_qcom_port ports[DWC3_QCOM_MAX_PORTS];
81 u8 num_ports;
82
83 struct extcon_dev *edev;
84 struct extcon_dev *host_edev;
85 struct notifier_block vbus_nb;
86 struct notifier_block host_nb;
87
88 enum usb_dr_mode mode;
89 bool is_suspended;
90 bool pm_suspended;
91 struct icc_path *icc_path_ddr;
92 struct icc_path *icc_path_apps;
93};
94
95static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
96{
97 u32 reg;
98
99 reg = readl(base + offset);
100 reg |= val;
101 writel(reg, base + offset);
102
103 /* ensure that above write is through */
104 readl(base + offset);
105}
106
107static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
108{
109 u32 reg;
110
111 reg = readl(base + offset);
112 reg &= ~val;
113 writel(reg, base + offset);
114
115 /* ensure that above write is through */
116 readl(base + offset);
117}
118
119static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
120{
121 if (enable) {
122 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
123 LANE0_PWR_PRESENT);
124 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
125 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
126 } else {
127 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
128 LANE0_PWR_PRESENT);
129 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
130 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
131 }
132}
133
134static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
135 unsigned long event, void *ptr)
136{
137 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
138
139 /* enable vbus override for device mode */
140 dwc3_qcom_vbus_override_enable(qcom, event);
141 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
142
143 return NOTIFY_DONE;
144}
145
146static int dwc3_qcom_host_notifier(struct notifier_block *nb,
147 unsigned long event, void *ptr)
148{
149 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
150
151 /* disable vbus override in host mode */
152 dwc3_qcom_vbus_override_enable(qcom, !event);
153 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
154
155 return NOTIFY_DONE;
156}
157
158static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
159{
160 struct device *dev = qcom->dev;
161 struct extcon_dev *host_edev;
162 int ret;
163
164 if (!of_property_present(dev->of_node, "extcon"))
165 return 0;
166
167 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
168 if (IS_ERR(qcom->edev))
169 return dev_err_probe(dev, PTR_ERR(qcom->edev),
170 "Failed to get extcon\n");
171
172 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
173
174 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
175 if (IS_ERR(qcom->host_edev))
176 qcom->host_edev = NULL;
177
178 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
179 &qcom->vbus_nb);
180 if (ret < 0) {
181 dev_err(dev, "VBUS notifier register failed\n");
182 return ret;
183 }
184
185 if (qcom->host_edev)
186 host_edev = qcom->host_edev;
187 else
188 host_edev = qcom->edev;
189
190 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
191 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
192 &qcom->host_nb);
193 if (ret < 0) {
194 dev_err(dev, "Host notifier register failed\n");
195 return ret;
196 }
197
198 /* Update initial VBUS override based on extcon state */
199 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
200 !extcon_get_state(host_edev, EXTCON_USB_HOST))
201 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
202 else
203 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
204
205 return 0;
206}
207
208static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
209{
210 int ret;
211
212 ret = icc_enable(qcom->icc_path_ddr);
213 if (ret)
214 return ret;
215
216 ret = icc_enable(qcom->icc_path_apps);
217 if (ret)
218 icc_disable(qcom->icc_path_ddr);
219
220 return ret;
221}
222
223static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
224{
225 int ret;
226
227 ret = icc_disable(qcom->icc_path_ddr);
228 if (ret)
229 return ret;
230
231 ret = icc_disable(qcom->icc_path_apps);
232 if (ret)
233 icc_enable(qcom->icc_path_ddr);
234
235 return ret;
236}
237
238/**
239 * dwc3_qcom_interconnect_init() - Get interconnect path handles
240 * and set bandwidth.
241 * @qcom: Pointer to the concerned usb core.
242 *
243 */
244static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
245{
246 enum usb_device_speed max_speed;
247 struct device *dev = qcom->dev;
248 int ret;
249
250 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
251 if (IS_ERR(qcom->icc_path_ddr)) {
252 return dev_err_probe(dev, PTR_ERR(qcom->icc_path_ddr),
253 "failed to get usb-ddr path\n");
254 }
255
256 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
257 if (IS_ERR(qcom->icc_path_apps)) {
258 ret = dev_err_probe(dev, PTR_ERR(qcom->icc_path_apps),
259 "failed to get apps-usb path\n");
260 goto put_path_ddr;
261 }
262
263 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev);
264 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) {
265 ret = icc_set_bw(qcom->icc_path_ddr,
266 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
267 } else {
268 ret = icc_set_bw(qcom->icc_path_ddr,
269 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
270 }
271 if (ret) {
272 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
273 goto put_path_apps;
274 }
275
276 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
277 if (ret) {
278 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
279 goto put_path_apps;
280 }
281
282 return 0;
283
284put_path_apps:
285 icc_put(qcom->icc_path_apps);
286put_path_ddr:
287 icc_put(qcom->icc_path_ddr);
288 return ret;
289}
290
291/**
292 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
293 * @qcom: Pointer to the concerned usb core.
294 *
295 * This function is used to release interconnect path handle.
296 */
297static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
298{
299 icc_put(qcom->icc_path_ddr);
300 icc_put(qcom->icc_path_apps);
301}
302
303/* Only usable in contexts where the role can not change. */
304static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
305{
306 struct dwc3 *dwc;
307
308 /*
309 * FIXME: Fix this layering violation.
310 */
311 dwc = platform_get_drvdata(qcom->dwc3);
312
313 /* Core driver may not have probed yet. */
314 if (!dwc)
315 return false;
316
317 return dwc->xhci;
318}
319
320static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom, int port_index)
321{
322 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
323 struct usb_device *udev;
324 struct usb_hcd __maybe_unused *hcd;
325
326 /*
327 * FIXME: Fix this layering violation.
328 */
329 hcd = platform_get_drvdata(dwc->xhci);
330
331#ifdef CONFIG_USB
332 udev = usb_hub_find_child(hcd->self.root_hub, port_index + 1);
333#else
334 udev = NULL;
335#endif
336 if (!udev)
337 return USB_SPEED_UNKNOWN;
338
339 return udev->speed;
340}
341
342static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity)
343{
344 if (!irq)
345 return;
346
347 if (polarity)
348 irq_set_irq_type(irq, polarity);
349
350 enable_irq(irq);
351 enable_irq_wake(irq);
352}
353
354static void dwc3_qcom_disable_wakeup_irq(int irq)
355{
356 if (!irq)
357 return;
358
359 disable_irq_wake(irq);
360 disable_irq_nosync(irq);
361}
362
363static void dwc3_qcom_disable_port_interrupts(struct dwc3_qcom_port *port)
364{
365 dwc3_qcom_disable_wakeup_irq(port->qusb2_phy_irq);
366
367 if (port->usb2_speed == USB_SPEED_LOW) {
368 dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq);
369 } else if ((port->usb2_speed == USB_SPEED_HIGH) ||
370 (port->usb2_speed == USB_SPEED_FULL)) {
371 dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq);
372 } else {
373 dwc3_qcom_disable_wakeup_irq(port->dp_hs_phy_irq);
374 dwc3_qcom_disable_wakeup_irq(port->dm_hs_phy_irq);
375 }
376
377 dwc3_qcom_disable_wakeup_irq(port->ss_phy_irq);
378}
379
380static void dwc3_qcom_enable_port_interrupts(struct dwc3_qcom_port *port)
381{
382 dwc3_qcom_enable_wakeup_irq(port->qusb2_phy_irq, 0);
383
384 /*
385 * Configure DP/DM line interrupts based on the USB2 device attached to
386 * the root hub port. When HS/FS device is connected, configure the DP line
387 * as falling edge to detect both disconnect and remote wakeup scenarios. When
388 * LS device is connected, configure DM line as falling edge to detect both
389 * disconnect and remote wakeup. When no device is connected, configure both
390 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
391 */
392
393 if (port->usb2_speed == USB_SPEED_LOW) {
394 dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq,
395 IRQ_TYPE_EDGE_FALLING);
396 } else if ((port->usb2_speed == USB_SPEED_HIGH) ||
397 (port->usb2_speed == USB_SPEED_FULL)) {
398 dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq,
399 IRQ_TYPE_EDGE_FALLING);
400 } else {
401 dwc3_qcom_enable_wakeup_irq(port->dp_hs_phy_irq,
402 IRQ_TYPE_EDGE_RISING);
403 dwc3_qcom_enable_wakeup_irq(port->dm_hs_phy_irq,
404 IRQ_TYPE_EDGE_RISING);
405 }
406
407 dwc3_qcom_enable_wakeup_irq(port->ss_phy_irq, 0);
408}
409
410static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
411{
412 int i;
413
414 for (i = 0; i < qcom->num_ports; i++)
415 dwc3_qcom_disable_port_interrupts(&qcom->ports[i]);
416}
417
418static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
419{
420 int i;
421
422 for (i = 0; i < qcom->num_ports; i++)
423 dwc3_qcom_enable_port_interrupts(&qcom->ports[i]);
424}
425
426static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
427{
428 u32 val;
429 int i, ret;
430
431 if (qcom->is_suspended)
432 return 0;
433
434 for (i = 0; i < qcom->num_ports; i++) {
435 val = readl(qcom->qscratch_base + pwr_evnt_irq_stat_reg[i]);
436 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
437 dev_err(qcom->dev, "port-%d HS-PHY not in L2\n", i + 1);
438 }
439
440 for (i = qcom->num_clocks - 1; i >= 0; i--)
441 clk_disable_unprepare(qcom->clks[i]);
442
443 ret = dwc3_qcom_interconnect_disable(qcom);
444 if (ret)
445 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
446
447 /*
448 * The role is stable during suspend as role switching is done from a
449 * freezable workqueue.
450 */
451 if (dwc3_qcom_is_host(qcom) && wakeup) {
452 for (i = 0; i < qcom->num_ports; i++)
453 qcom->ports[i].usb2_speed = dwc3_qcom_read_usb2_speed(qcom, i);
454 dwc3_qcom_enable_interrupts(qcom);
455 }
456
457 qcom->is_suspended = true;
458
459 return 0;
460}
461
462static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
463{
464 int ret;
465 int i;
466
467 if (!qcom->is_suspended)
468 return 0;
469
470 if (dwc3_qcom_is_host(qcom) && wakeup)
471 dwc3_qcom_disable_interrupts(qcom);
472
473 for (i = 0; i < qcom->num_clocks; i++) {
474 ret = clk_prepare_enable(qcom->clks[i]);
475 if (ret < 0) {
476 while (--i >= 0)
477 clk_disable_unprepare(qcom->clks[i]);
478 return ret;
479 }
480 }
481
482 ret = dwc3_qcom_interconnect_enable(qcom);
483 if (ret)
484 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
485
486 /* Clear existing events from PHY related to L2 in/out */
487 for (i = 0; i < qcom->num_ports; i++) {
488 dwc3_qcom_setbits(qcom->qscratch_base,
489 pwr_evnt_irq_stat_reg[i],
490 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
491 }
492
493 qcom->is_suspended = false;
494
495 return 0;
496}
497
498static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
499{
500 struct dwc3_qcom *qcom = data;
501 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
502
503 /* If pm_suspended then let pm_resume take care of resuming h/w */
504 if (qcom->pm_suspended)
505 return IRQ_HANDLED;
506
507 /*
508 * This is safe as role switching is done from a freezable workqueue
509 * and the wakeup interrupts are disabled as part of resume.
510 */
511 if (dwc3_qcom_is_host(qcom))
512 pm_runtime_resume(&dwc->xhci->dev);
513
514 return IRQ_HANDLED;
515}
516
517static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
518{
519 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
520 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
521 PIPE_UTMI_CLK_DIS);
522
523 usleep_range(100, 1000);
524
525 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
526 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
527
528 usleep_range(100, 1000);
529
530 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
531 PIPE_UTMI_CLK_DIS);
532}
533
534static int dwc3_qcom_request_irq(struct dwc3_qcom *qcom, int irq,
535 const char *name)
536{
537 int ret;
538
539 /* Keep wakeup interrupts disabled until suspend */
540 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
541 qcom_dwc3_resume_irq,
542 IRQF_ONESHOT | IRQF_NO_AUTOEN,
543 name, qcom);
544 if (ret)
545 dev_err(qcom->dev, "failed to request irq %s: %d\n", name, ret);
546
547 return ret;
548}
549
550static int dwc3_qcom_setup_port_irq(struct platform_device *pdev, int port_index, bool is_multiport)
551{
552 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
553 const char *irq_name;
554 int irq;
555 int ret;
556
557 if (is_multiport)
558 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_%d", port_index + 1);
559 else
560 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dp_hs_phy_irq");
561 if (!irq_name)
562 return -ENOMEM;
563
564 irq = platform_get_irq_byname_optional(pdev, irq_name);
565 if (irq > 0) {
566 ret = dwc3_qcom_request_irq(qcom, irq, irq_name);
567 if (ret)
568 return ret;
569 qcom->ports[port_index].dp_hs_phy_irq = irq;
570 }
571
572 if (is_multiport)
573 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_%d", port_index + 1);
574 else
575 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "dm_hs_phy_irq");
576 if (!irq_name)
577 return -ENOMEM;
578
579 irq = platform_get_irq_byname_optional(pdev, irq_name);
580 if (irq > 0) {
581 ret = dwc3_qcom_request_irq(qcom, irq, irq_name);
582 if (ret)
583 return ret;
584 qcom->ports[port_index].dm_hs_phy_irq = irq;
585 }
586
587 if (is_multiport)
588 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_%d", port_index + 1);
589 else
590 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ss_phy_irq");
591 if (!irq_name)
592 return -ENOMEM;
593
594 irq = platform_get_irq_byname_optional(pdev, irq_name);
595 if (irq > 0) {
596 ret = dwc3_qcom_request_irq(qcom, irq, irq_name);
597 if (ret)
598 return ret;
599 qcom->ports[port_index].ss_phy_irq = irq;
600 }
601
602 if (is_multiport)
603 return 0;
604
605 irq = platform_get_irq_byname_optional(pdev, "qusb2_phy");
606 if (irq > 0) {
607 ret = dwc3_qcom_request_irq(qcom, irq, "qusb2_phy");
608 if (ret)
609 return ret;
610 qcom->ports[port_index].qusb2_phy_irq = irq;
611 }
612
613 return 0;
614}
615
616static int dwc3_qcom_find_num_ports(struct platform_device *pdev)
617{
618 char irq_name[14];
619 int port_num;
620 int irq;
621
622 irq = platform_get_irq_byname_optional(pdev, "dp_hs_phy_1");
623 if (irq <= 0)
624 return 1;
625
626 for (port_num = 2; port_num <= DWC3_QCOM_MAX_PORTS; port_num++) {
627 sprintf(irq_name, "dp_hs_phy_%d", port_num);
628
629 irq = platform_get_irq_byname_optional(pdev, irq_name);
630 if (irq <= 0)
631 return port_num - 1;
632 }
633
634 return DWC3_QCOM_MAX_PORTS;
635}
636
637static int dwc3_qcom_setup_irq(struct platform_device *pdev)
638{
639 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
640 bool is_multiport;
641 int ret;
642 int i;
643
644 qcom->num_ports = dwc3_qcom_find_num_ports(pdev);
645 is_multiport = (qcom->num_ports > 1);
646
647 for (i = 0; i < qcom->num_ports; i++) {
648 ret = dwc3_qcom_setup_port_irq(pdev, i, is_multiport);
649 if (ret)
650 return ret;
651 }
652
653 return 0;
654}
655
656static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
657{
658 struct device *dev = qcom->dev;
659 struct device_node *np = dev->of_node;
660 int i;
661
662 if (!np || !count)
663 return 0;
664
665 if (count < 0)
666 return count;
667
668 qcom->num_clocks = count;
669
670 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
671 sizeof(struct clk *), GFP_KERNEL);
672 if (!qcom->clks)
673 return -ENOMEM;
674
675 for (i = 0; i < qcom->num_clocks; i++) {
676 struct clk *clk;
677 int ret;
678
679 clk = of_clk_get(np, i);
680 if (IS_ERR(clk)) {
681 while (--i >= 0)
682 clk_put(qcom->clks[i]);
683 return PTR_ERR(clk);
684 }
685
686 ret = clk_prepare_enable(clk);
687 if (ret < 0) {
688 while (--i >= 0) {
689 clk_disable_unprepare(qcom->clks[i]);
690 clk_put(qcom->clks[i]);
691 }
692 clk_put(clk);
693
694 return ret;
695 }
696
697 qcom->clks[i] = clk;
698 }
699
700 return 0;
701}
702
703static int dwc3_qcom_of_register_core(struct platform_device *pdev)
704{
705 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
706 struct device_node *np = pdev->dev.of_node;
707 struct device *dev = &pdev->dev;
708 int ret;
709
710 struct device_node *dwc3_np __free(device_node) = of_get_compatible_child(np,
711 "snps,dwc3");
712 if (!dwc3_np) {
713 dev_err(dev, "failed to find dwc3 core child\n");
714 return -ENODEV;
715 }
716
717 ret = of_platform_populate(np, NULL, NULL, dev);
718 if (ret) {
719 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
720 return ret;
721 }
722
723 qcom->dwc3 = of_find_device_by_node(dwc3_np);
724 if (!qcom->dwc3) {
725 ret = -ENODEV;
726 dev_err(dev, "failed to get dwc3 platform device\n");
727 of_platform_depopulate(dev);
728 }
729
730 return ret;
731}
732
733static int dwc3_qcom_probe(struct platform_device *pdev)
734{
735 struct device_node *np = pdev->dev.of_node;
736 struct device *dev = &pdev->dev;
737 struct dwc3_qcom *qcom;
738 int ret, i;
739 bool ignore_pipe_clk;
740 bool wakeup_source;
741
742 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
743 if (!qcom)
744 return -ENOMEM;
745
746 platform_set_drvdata(pdev, qcom);
747 qcom->dev = &pdev->dev;
748
749 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
750 if (IS_ERR(qcom->resets)) {
751 return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
752 "failed to get resets\n");
753 }
754
755 ret = reset_control_assert(qcom->resets);
756 if (ret) {
757 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
758 return ret;
759 }
760
761 usleep_range(10, 1000);
762
763 ret = reset_control_deassert(qcom->resets);
764 if (ret) {
765 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
766 goto reset_assert;
767 }
768
769 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
770 if (ret) {
771 dev_err_probe(dev, ret, "failed to get clocks\n");
772 goto reset_assert;
773 }
774
775 qcom->qscratch_base = devm_platform_ioremap_resource(pdev, 0);
776 if (IS_ERR(qcom->qscratch_base)) {
777 ret = PTR_ERR(qcom->qscratch_base);
778 goto clk_disable;
779 }
780
781 ret = dwc3_qcom_setup_irq(pdev);
782 if (ret) {
783 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
784 goto clk_disable;
785 }
786
787 /*
788 * Disable pipe_clk requirement if specified. Used when dwc3
789 * operates without SSPHY and only HS/FS/LS modes are supported.
790 */
791 ignore_pipe_clk = device_property_read_bool(dev,
792 "qcom,select-utmi-as-pipe-clk");
793 if (ignore_pipe_clk)
794 dwc3_qcom_select_utmi_clk(qcom);
795
796 ret = dwc3_qcom_of_register_core(pdev);
797 if (ret) {
798 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
799 goto clk_disable;
800 }
801
802 ret = dwc3_qcom_interconnect_init(qcom);
803 if (ret)
804 goto depopulate;
805
806 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
807
808 /* enable vbus override for device mode */
809 if (qcom->mode != USB_DR_MODE_HOST)
810 dwc3_qcom_vbus_override_enable(qcom, true);
811
812 /* register extcon to override sw_vbus on Vbus change later */
813 ret = dwc3_qcom_register_extcon(qcom);
814 if (ret)
815 goto interconnect_exit;
816
817 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source");
818 device_init_wakeup(&pdev->dev, wakeup_source);
819 device_init_wakeup(&qcom->dwc3->dev, wakeup_source);
820
821 qcom->is_suspended = false;
822 pm_runtime_set_active(dev);
823 pm_runtime_enable(dev);
824 pm_runtime_forbid(dev);
825
826 return 0;
827
828interconnect_exit:
829 dwc3_qcom_interconnect_exit(qcom);
830depopulate:
831 of_platform_depopulate(&pdev->dev);
832 platform_device_put(qcom->dwc3);
833clk_disable:
834 for (i = qcom->num_clocks - 1; i >= 0; i--) {
835 clk_disable_unprepare(qcom->clks[i]);
836 clk_put(qcom->clks[i]);
837 }
838reset_assert:
839 reset_control_assert(qcom->resets);
840
841 return ret;
842}
843
844static void dwc3_qcom_remove(struct platform_device *pdev)
845{
846 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
847 struct device *dev = &pdev->dev;
848 int i;
849
850 of_platform_depopulate(&pdev->dev);
851 platform_device_put(qcom->dwc3);
852
853 for (i = qcom->num_clocks - 1; i >= 0; i--) {
854 clk_disable_unprepare(qcom->clks[i]);
855 clk_put(qcom->clks[i]);
856 }
857 qcom->num_clocks = 0;
858
859 dwc3_qcom_interconnect_exit(qcom);
860 reset_control_assert(qcom->resets);
861
862 pm_runtime_allow(dev);
863 pm_runtime_disable(dev);
864}
865
866static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
867{
868 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
869 bool wakeup = device_may_wakeup(dev);
870 int ret;
871
872 ret = dwc3_qcom_suspend(qcom, wakeup);
873 if (ret)
874 return ret;
875
876 qcom->pm_suspended = true;
877
878 return 0;
879}
880
881static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
882{
883 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
884 bool wakeup = device_may_wakeup(dev);
885 int ret;
886
887 ret = dwc3_qcom_resume(qcom, wakeup);
888 if (ret)
889 return ret;
890
891 qcom->pm_suspended = false;
892
893 return 0;
894}
895
896static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
897{
898 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
899
900 return dwc3_qcom_suspend(qcom, true);
901}
902
903static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
904{
905 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
906
907 return dwc3_qcom_resume(qcom, true);
908}
909
910static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
911 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
912 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
913 NULL)
914};
915
916static const struct of_device_id dwc3_qcom_of_match[] = {
917 { .compatible = "qcom,dwc3" },
918 { }
919};
920MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
921
922static struct platform_driver dwc3_qcom_driver = {
923 .probe = dwc3_qcom_probe,
924 .remove = dwc3_qcom_remove,
925 .driver = {
926 .name = "dwc3-qcom",
927 .pm = &dwc3_qcom_dev_pm_ops,
928 .of_match_table = dwc3_qcom_of_match,
929 },
930};
931
932module_platform_driver(dwc3_qcom_driver);
933
934MODULE_LICENSE("GPL v2");
935MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");