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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
3 *
4 * Inspired by dwc3-of-simple.c
5 */
6
7#include <linux/acpi.h>
8#include <linux/io.h>
9#include <linux/of.h>
10#include <linux/clk.h>
11#include <linux/irq.h>
12#include <linux/of_clk.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/extcon.h>
16#include <linux/interconnect.h>
17#include <linux/of_platform.h>
18#include <linux/platform_device.h>
19#include <linux/phy/phy.h>
20#include <linux/usb/of.h>
21#include <linux/reset.h>
22#include <linux/iopoll.h>
23#include <linux/usb/hcd.h>
24#include <linux/usb.h>
25#include "core.h"
26
27/* USB QSCRATCH Hardware registers */
28#define QSCRATCH_HS_PHY_CTRL 0x10
29#define UTMI_OTG_VBUS_VALID BIT(20)
30#define SW_SESSVLD_SEL BIT(28)
31
32#define QSCRATCH_SS_PHY_CTRL 0x30
33#define LANE0_PWR_PRESENT BIT(24)
34
35#define QSCRATCH_GENERAL_CFG 0x08
36#define PIPE_UTMI_CLK_SEL BIT(0)
37#define PIPE3_PHYSTATUS_SW BIT(3)
38#define PIPE_UTMI_CLK_DIS BIT(8)
39
40#define PWR_EVNT_IRQ_STAT_REG 0x58
41#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
42#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
43
44#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
45#define SDM845_QSCRATCH_SIZE 0x400
46#define SDM845_DWC3_CORE_SIZE 0xcd00
47
48/* Interconnect path bandwidths in MBps */
49#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
50#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
51#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
52#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
53#define APPS_USB_AVG_BW 0
54#define APPS_USB_PEAK_BW MBps_to_icc(40)
55
56struct dwc3_acpi_pdata {
57 u32 qscratch_base_offset;
58 u32 qscratch_base_size;
59 u32 dwc3_core_base_size;
60 int qusb2_phy_irq_index;
61 int dp_hs_phy_irq_index;
62 int dm_hs_phy_irq_index;
63 int ss_phy_irq_index;
64 bool is_urs;
65};
66
67struct dwc3_qcom {
68 struct device *dev;
69 void __iomem *qscratch_base;
70 struct platform_device *dwc3;
71 struct platform_device *urs_usb;
72 struct clk **clks;
73 int num_clocks;
74 struct reset_control *resets;
75
76 int qusb2_phy_irq;
77 int dp_hs_phy_irq;
78 int dm_hs_phy_irq;
79 int ss_phy_irq;
80 enum usb_device_speed usb2_speed;
81
82 struct extcon_dev *edev;
83 struct extcon_dev *host_edev;
84 struct notifier_block vbus_nb;
85 struct notifier_block host_nb;
86
87 const struct dwc3_acpi_pdata *acpi_pdata;
88
89 enum usb_dr_mode mode;
90 bool is_suspended;
91 bool pm_suspended;
92 struct icc_path *icc_path_ddr;
93 struct icc_path *icc_path_apps;
94};
95
96static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
97{
98 u32 reg;
99
100 reg = readl(base + offset);
101 reg |= val;
102 writel(reg, base + offset);
103
104 /* ensure that above write is through */
105 readl(base + offset);
106}
107
108static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
109{
110 u32 reg;
111
112 reg = readl(base + offset);
113 reg &= ~val;
114 writel(reg, base + offset);
115
116 /* ensure that above write is through */
117 readl(base + offset);
118}
119
120static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
121{
122 if (enable) {
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
124 LANE0_PWR_PRESENT);
125 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
126 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
127 } else {
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
129 LANE0_PWR_PRESENT);
130 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
131 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
132 }
133}
134
135static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
136 unsigned long event, void *ptr)
137{
138 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
139
140 /* enable vbus override for device mode */
141 dwc3_qcom_vbus_override_enable(qcom, event);
142 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
143
144 return NOTIFY_DONE;
145}
146
147static int dwc3_qcom_host_notifier(struct notifier_block *nb,
148 unsigned long event, void *ptr)
149{
150 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
151
152 /* disable vbus override in host mode */
153 dwc3_qcom_vbus_override_enable(qcom, !event);
154 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
155
156 return NOTIFY_DONE;
157}
158
159static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
160{
161 struct device *dev = qcom->dev;
162 struct extcon_dev *host_edev;
163 int ret;
164
165 if (!of_property_read_bool(dev->of_node, "extcon"))
166 return 0;
167
168 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
169 if (IS_ERR(qcom->edev))
170 return dev_err_probe(dev, PTR_ERR(qcom->edev),
171 "Failed to get extcon\n");
172
173 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
174
175 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
176 if (IS_ERR(qcom->host_edev))
177 qcom->host_edev = NULL;
178
179 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
180 &qcom->vbus_nb);
181 if (ret < 0) {
182 dev_err(dev, "VBUS notifier register failed\n");
183 return ret;
184 }
185
186 if (qcom->host_edev)
187 host_edev = qcom->host_edev;
188 else
189 host_edev = qcom->edev;
190
191 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
192 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
193 &qcom->host_nb);
194 if (ret < 0) {
195 dev_err(dev, "Host notifier register failed\n");
196 return ret;
197 }
198
199 /* Update initial VBUS override based on extcon state */
200 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
201 !extcon_get_state(host_edev, EXTCON_USB_HOST))
202 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
203 else
204 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
205
206 return 0;
207}
208
209static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
210{
211 int ret;
212
213 ret = icc_enable(qcom->icc_path_ddr);
214 if (ret)
215 return ret;
216
217 ret = icc_enable(qcom->icc_path_apps);
218 if (ret)
219 icc_disable(qcom->icc_path_ddr);
220
221 return ret;
222}
223
224static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
225{
226 int ret;
227
228 ret = icc_disable(qcom->icc_path_ddr);
229 if (ret)
230 return ret;
231
232 ret = icc_disable(qcom->icc_path_apps);
233 if (ret)
234 icc_enable(qcom->icc_path_ddr);
235
236 return ret;
237}
238
239/**
240 * dwc3_qcom_interconnect_init() - Get interconnect path handles
241 * and set bandwidth.
242 * @qcom: Pointer to the concerned usb core.
243 *
244 */
245static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
246{
247 enum usb_device_speed max_speed;
248 struct device *dev = qcom->dev;
249 int ret;
250
251 if (has_acpi_companion(dev))
252 return 0;
253
254 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
255 if (IS_ERR(qcom->icc_path_ddr)) {
256 return dev_err_probe(dev, PTR_ERR(qcom->icc_path_ddr),
257 "failed to get usb-ddr path\n");
258 }
259
260 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
261 if (IS_ERR(qcom->icc_path_apps)) {
262 ret = dev_err_probe(dev, PTR_ERR(qcom->icc_path_apps),
263 "failed to get apps-usb path\n");
264 goto put_path_ddr;
265 }
266
267 max_speed = usb_get_maximum_speed(&qcom->dwc3->dev);
268 if (max_speed >= USB_SPEED_SUPER || max_speed == USB_SPEED_UNKNOWN) {
269 ret = icc_set_bw(qcom->icc_path_ddr,
270 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
271 } else {
272 ret = icc_set_bw(qcom->icc_path_ddr,
273 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
274 }
275 if (ret) {
276 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
277 goto put_path_apps;
278 }
279
280 ret = icc_set_bw(qcom->icc_path_apps, APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
281 if (ret) {
282 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
283 goto put_path_apps;
284 }
285
286 return 0;
287
288put_path_apps:
289 icc_put(qcom->icc_path_apps);
290put_path_ddr:
291 icc_put(qcom->icc_path_ddr);
292 return ret;
293}
294
295/**
296 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
297 * @qcom: Pointer to the concerned usb core.
298 *
299 * This function is used to release interconnect path handle.
300 */
301static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
302{
303 icc_put(qcom->icc_path_ddr);
304 icc_put(qcom->icc_path_apps);
305}
306
307/* Only usable in contexts where the role can not change. */
308static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
309{
310 struct dwc3 *dwc;
311
312 /*
313 * FIXME: Fix this layering violation.
314 */
315 dwc = platform_get_drvdata(qcom->dwc3);
316
317 /* Core driver may not have probed yet. */
318 if (!dwc)
319 return false;
320
321 return dwc->xhci;
322}
323
324static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
325{
326 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
327 struct usb_device *udev;
328 struct usb_hcd __maybe_unused *hcd;
329
330 /*
331 * FIXME: Fix this layering violation.
332 */
333 hcd = platform_get_drvdata(dwc->xhci);
334
335 /*
336 * It is possible to query the speed of all children of
337 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
338 * currently supports only 1 port per controller. So
339 * this is sufficient.
340 */
341#ifdef CONFIG_USB
342 udev = usb_hub_find_child(hcd->self.root_hub, 1);
343#else
344 udev = NULL;
345#endif
346 if (!udev)
347 return USB_SPEED_UNKNOWN;
348
349 return udev->speed;
350}
351
352static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity)
353{
354 if (!irq)
355 return;
356
357 if (polarity)
358 irq_set_irq_type(irq, polarity);
359
360 enable_irq(irq);
361 enable_irq_wake(irq);
362}
363
364static void dwc3_qcom_disable_wakeup_irq(int irq)
365{
366 if (!irq)
367 return;
368
369 disable_irq_wake(irq);
370 disable_irq_nosync(irq);
371}
372
373static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
374{
375 dwc3_qcom_disable_wakeup_irq(qcom->qusb2_phy_irq);
376
377 if (qcom->usb2_speed == USB_SPEED_LOW) {
378 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
379 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
380 (qcom->usb2_speed == USB_SPEED_FULL)) {
381 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
382 } else {
383 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
384 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
385 }
386
387 dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
388}
389
390static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
391{
392 dwc3_qcom_enable_wakeup_irq(qcom->qusb2_phy_irq, 0);
393
394 /*
395 * Configure DP/DM line interrupts based on the USB2 device attached to
396 * the root hub port. When HS/FS device is connected, configure the DP line
397 * as falling edge to detect both disconnect and remote wakeup scenarios. When
398 * LS device is connected, configure DM line as falling edge to detect both
399 * disconnect and remote wakeup. When no device is connected, configure both
400 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
401 */
402
403 if (qcom->usb2_speed == USB_SPEED_LOW) {
404 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
405 IRQ_TYPE_EDGE_FALLING);
406 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
407 (qcom->usb2_speed == USB_SPEED_FULL)) {
408 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
409 IRQ_TYPE_EDGE_FALLING);
410 } else {
411 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
412 IRQ_TYPE_EDGE_RISING);
413 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
414 IRQ_TYPE_EDGE_RISING);
415 }
416
417 dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
418}
419
420static int dwc3_qcom_suspend(struct dwc3_qcom *qcom, bool wakeup)
421{
422 u32 val;
423 int i, ret;
424
425 if (qcom->is_suspended)
426 return 0;
427
428 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
429 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
430 dev_err(qcom->dev, "HS-PHY not in L2\n");
431
432 for (i = qcom->num_clocks - 1; i >= 0; i--)
433 clk_disable_unprepare(qcom->clks[i]);
434
435 ret = dwc3_qcom_interconnect_disable(qcom);
436 if (ret)
437 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
438
439 /*
440 * The role is stable during suspend as role switching is done from a
441 * freezable workqueue.
442 */
443 if (dwc3_qcom_is_host(qcom) && wakeup) {
444 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
445 dwc3_qcom_enable_interrupts(qcom);
446 }
447
448 qcom->is_suspended = true;
449
450 return 0;
451}
452
453static int dwc3_qcom_resume(struct dwc3_qcom *qcom, bool wakeup)
454{
455 int ret;
456 int i;
457
458 if (!qcom->is_suspended)
459 return 0;
460
461 if (dwc3_qcom_is_host(qcom) && wakeup)
462 dwc3_qcom_disable_interrupts(qcom);
463
464 for (i = 0; i < qcom->num_clocks; i++) {
465 ret = clk_prepare_enable(qcom->clks[i]);
466 if (ret < 0) {
467 while (--i >= 0)
468 clk_disable_unprepare(qcom->clks[i]);
469 return ret;
470 }
471 }
472
473 ret = dwc3_qcom_interconnect_enable(qcom);
474 if (ret)
475 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
476
477 /* Clear existing events from PHY related to L2 in/out */
478 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
479 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
480
481 qcom->is_suspended = false;
482
483 return 0;
484}
485
486static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
487{
488 struct dwc3_qcom *qcom = data;
489 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
490
491 /* If pm_suspended then let pm_resume take care of resuming h/w */
492 if (qcom->pm_suspended)
493 return IRQ_HANDLED;
494
495 /*
496 * This is safe as role switching is done from a freezable workqueue
497 * and the wakeup interrupts are disabled as part of resume.
498 */
499 if (dwc3_qcom_is_host(qcom))
500 pm_runtime_resume(&dwc->xhci->dev);
501
502 return IRQ_HANDLED;
503}
504
505static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
506{
507 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
508 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
509 PIPE_UTMI_CLK_DIS);
510
511 usleep_range(100, 1000);
512
513 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
514 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
515
516 usleep_range(100, 1000);
517
518 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
519 PIPE_UTMI_CLK_DIS);
520}
521
522static int dwc3_qcom_get_irq(struct platform_device *pdev,
523 const char *name, int num)
524{
525 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
526 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
527 struct device_node *np = pdev->dev.of_node;
528 int ret;
529
530 if (np)
531 ret = platform_get_irq_byname_optional(pdev_irq, name);
532 else
533 ret = platform_get_irq_optional(pdev_irq, num);
534
535 return ret;
536}
537
538static int dwc3_qcom_setup_irq(struct platform_device *pdev)
539{
540 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
541 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
542 int irq;
543 int ret;
544
545 irq = dwc3_qcom_get_irq(pdev, "qusb2_phy",
546 pdata ? pdata->qusb2_phy_irq_index : -1);
547 if (irq > 0) {
548 /* Keep wakeup interrupts disabled until suspend */
549 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
550 qcom_dwc3_resume_irq,
551 IRQF_ONESHOT | IRQF_NO_AUTOEN,
552 "qcom_dwc3 QUSB2", qcom);
553 if (ret) {
554 dev_err(qcom->dev, "qusb2_phy_irq failed: %d\n", ret);
555 return ret;
556 }
557 qcom->qusb2_phy_irq = irq;
558 }
559
560 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
561 pdata ? pdata->dp_hs_phy_irq_index : -1);
562 if (irq > 0) {
563 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
564 qcom_dwc3_resume_irq,
565 IRQF_ONESHOT | IRQF_NO_AUTOEN,
566 "qcom_dwc3 DP_HS", qcom);
567 if (ret) {
568 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
569 return ret;
570 }
571 qcom->dp_hs_phy_irq = irq;
572 }
573
574 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
575 pdata ? pdata->dm_hs_phy_irq_index : -1);
576 if (irq > 0) {
577 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
578 qcom_dwc3_resume_irq,
579 IRQF_ONESHOT | IRQF_NO_AUTOEN,
580 "qcom_dwc3 DM_HS", qcom);
581 if (ret) {
582 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
583 return ret;
584 }
585 qcom->dm_hs_phy_irq = irq;
586 }
587
588 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
589 pdata ? pdata->ss_phy_irq_index : -1);
590 if (irq > 0) {
591 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
592 qcom_dwc3_resume_irq,
593 IRQF_ONESHOT | IRQF_NO_AUTOEN,
594 "qcom_dwc3 SS", qcom);
595 if (ret) {
596 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
597 return ret;
598 }
599 qcom->ss_phy_irq = irq;
600 }
601
602 return 0;
603}
604
605static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
606{
607 struct device *dev = qcom->dev;
608 struct device_node *np = dev->of_node;
609 int i;
610
611 if (!np || !count)
612 return 0;
613
614 if (count < 0)
615 return count;
616
617 qcom->num_clocks = count;
618
619 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
620 sizeof(struct clk *), GFP_KERNEL);
621 if (!qcom->clks)
622 return -ENOMEM;
623
624 for (i = 0; i < qcom->num_clocks; i++) {
625 struct clk *clk;
626 int ret;
627
628 clk = of_clk_get(np, i);
629 if (IS_ERR(clk)) {
630 while (--i >= 0)
631 clk_put(qcom->clks[i]);
632 return PTR_ERR(clk);
633 }
634
635 ret = clk_prepare_enable(clk);
636 if (ret < 0) {
637 while (--i >= 0) {
638 clk_disable_unprepare(qcom->clks[i]);
639 clk_put(qcom->clks[i]);
640 }
641 clk_put(clk);
642
643 return ret;
644 }
645
646 qcom->clks[i] = clk;
647 }
648
649 return 0;
650}
651
652static const struct property_entry dwc3_qcom_acpi_properties[] = {
653 PROPERTY_ENTRY_STRING("dr_mode", "host"),
654 {}
655};
656
657static const struct software_node dwc3_qcom_swnode = {
658 .properties = dwc3_qcom_acpi_properties,
659};
660
661static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
662{
663 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
664 struct device *dev = &pdev->dev;
665 struct resource *res, *child_res = NULL;
666 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
667 pdev;
668 int irq;
669 int ret;
670
671 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
672 if (!qcom->dwc3)
673 return -ENOMEM;
674
675 qcom->dwc3->dev.parent = dev;
676 qcom->dwc3->dev.type = dev->type;
677 qcom->dwc3->dev.dma_mask = dev->dma_mask;
678 qcom->dwc3->dev.dma_parms = dev->dma_parms;
679 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
680
681 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
682 if (!child_res) {
683 platform_device_put(qcom->dwc3);
684 return -ENOMEM;
685 }
686
687 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
688 if (!res) {
689 dev_err(&pdev->dev, "failed to get memory resource\n");
690 ret = -ENODEV;
691 goto out;
692 }
693
694 child_res[0].flags = res->flags;
695 child_res[0].start = res->start;
696 child_res[0].end = child_res[0].start +
697 qcom->acpi_pdata->dwc3_core_base_size;
698
699 irq = platform_get_irq(pdev_irq, 0);
700 if (irq < 0) {
701 ret = irq;
702 goto out;
703 }
704 child_res[1].flags = IORESOURCE_IRQ;
705 child_res[1].start = child_res[1].end = irq;
706
707 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
708 if (ret) {
709 dev_err(&pdev->dev, "failed to add resources\n");
710 goto out;
711 }
712
713 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
714 if (ret < 0) {
715 dev_err(&pdev->dev, "failed to add properties\n");
716 goto out;
717 }
718
719 ret = platform_device_add(qcom->dwc3);
720 if (ret) {
721 dev_err(&pdev->dev, "failed to add device\n");
722 device_remove_software_node(&qcom->dwc3->dev);
723 goto out;
724 }
725 kfree(child_res);
726 return 0;
727
728out:
729 platform_device_put(qcom->dwc3);
730 kfree(child_res);
731 return ret;
732}
733
734static int dwc3_qcom_of_register_core(struct platform_device *pdev)
735{
736 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
737 struct device_node *np = pdev->dev.of_node, *dwc3_np;
738 struct device *dev = &pdev->dev;
739 int ret;
740
741 dwc3_np = of_get_compatible_child(np, "snps,dwc3");
742 if (!dwc3_np) {
743 dev_err(dev, "failed to find dwc3 core child\n");
744 return -ENODEV;
745 }
746
747 ret = of_platform_populate(np, NULL, NULL, dev);
748 if (ret) {
749 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
750 goto node_put;
751 }
752
753 qcom->dwc3 = of_find_device_by_node(dwc3_np);
754 if (!qcom->dwc3) {
755 ret = -ENODEV;
756 dev_err(dev, "failed to get dwc3 platform device\n");
757 of_platform_depopulate(dev);
758 }
759
760node_put:
761 of_node_put(dwc3_np);
762
763 return ret;
764}
765
766static struct platform_device *dwc3_qcom_create_urs_usb_platdev(struct device *dev)
767{
768 struct platform_device *urs_usb = NULL;
769 struct fwnode_handle *fwh;
770 struct acpi_device *adev;
771 char name[8];
772 int ret;
773 int id;
774
775 /* Figure out device id */
776 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
777 if (!ret)
778 return NULL;
779
780 /* Find the child using name */
781 snprintf(name, sizeof(name), "USB%d", id);
782 fwh = fwnode_get_named_child_node(dev->fwnode, name);
783 if (!fwh)
784 return NULL;
785
786 adev = to_acpi_device_node(fwh);
787 if (!adev)
788 goto err_put_handle;
789
790 urs_usb = acpi_create_platform_device(adev, NULL);
791 if (IS_ERR_OR_NULL(urs_usb))
792 goto err_put_handle;
793
794 return urs_usb;
795
796err_put_handle:
797 fwnode_handle_put(fwh);
798
799 return urs_usb;
800}
801
802static void dwc3_qcom_destroy_urs_usb_platdev(struct platform_device *urs_usb)
803{
804 struct fwnode_handle *fwh = urs_usb->dev.fwnode;
805
806 platform_device_unregister(urs_usb);
807 fwnode_handle_put(fwh);
808}
809
810static int dwc3_qcom_probe(struct platform_device *pdev)
811{
812 struct device_node *np = pdev->dev.of_node;
813 struct device *dev = &pdev->dev;
814 struct dwc3_qcom *qcom;
815 struct resource *res, *parent_res = NULL;
816 struct resource local_res;
817 int ret, i;
818 bool ignore_pipe_clk;
819 bool wakeup_source;
820
821 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
822 if (!qcom)
823 return -ENOMEM;
824
825 platform_set_drvdata(pdev, qcom);
826 qcom->dev = &pdev->dev;
827
828 if (has_acpi_companion(dev)) {
829 qcom->acpi_pdata = acpi_device_get_match_data(dev);
830 if (!qcom->acpi_pdata) {
831 dev_err(&pdev->dev, "no supporting ACPI device data\n");
832 return -EINVAL;
833 }
834 }
835
836 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
837 if (IS_ERR(qcom->resets)) {
838 return dev_err_probe(&pdev->dev, PTR_ERR(qcom->resets),
839 "failed to get resets\n");
840 }
841
842 ret = reset_control_assert(qcom->resets);
843 if (ret) {
844 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
845 return ret;
846 }
847
848 usleep_range(10, 1000);
849
850 ret = reset_control_deassert(qcom->resets);
851 if (ret) {
852 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
853 goto reset_assert;
854 }
855
856 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
857 if (ret) {
858 dev_err_probe(dev, ret, "failed to get clocks\n");
859 goto reset_assert;
860 }
861
862 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
863
864 if (np) {
865 parent_res = res;
866 } else {
867 memcpy(&local_res, res, sizeof(struct resource));
868 parent_res = &local_res;
869
870 parent_res->start = res->start +
871 qcom->acpi_pdata->qscratch_base_offset;
872 parent_res->end = parent_res->start +
873 qcom->acpi_pdata->qscratch_base_size;
874
875 if (qcom->acpi_pdata->is_urs) {
876 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
877 if (IS_ERR_OR_NULL(qcom->urs_usb)) {
878 dev_err(dev, "failed to create URS USB platdev\n");
879 if (!qcom->urs_usb)
880 ret = -ENODEV;
881 else
882 ret = PTR_ERR(qcom->urs_usb);
883 goto clk_disable;
884 }
885 }
886 }
887
888 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
889 if (IS_ERR(qcom->qscratch_base)) {
890 ret = PTR_ERR(qcom->qscratch_base);
891 goto free_urs;
892 }
893
894 ret = dwc3_qcom_setup_irq(pdev);
895 if (ret) {
896 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
897 goto free_urs;
898 }
899
900 /*
901 * Disable pipe_clk requirement if specified. Used when dwc3
902 * operates without SSPHY and only HS/FS/LS modes are supported.
903 */
904 ignore_pipe_clk = device_property_read_bool(dev,
905 "qcom,select-utmi-as-pipe-clk");
906 if (ignore_pipe_clk)
907 dwc3_qcom_select_utmi_clk(qcom);
908
909 if (np)
910 ret = dwc3_qcom_of_register_core(pdev);
911 else
912 ret = dwc3_qcom_acpi_register_core(pdev);
913
914 if (ret) {
915 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
916 goto free_urs;
917 }
918
919 ret = dwc3_qcom_interconnect_init(qcom);
920 if (ret)
921 goto depopulate;
922
923 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
924
925 /* enable vbus override for device mode */
926 if (qcom->mode != USB_DR_MODE_HOST)
927 dwc3_qcom_vbus_override_enable(qcom, true);
928
929 /* register extcon to override sw_vbus on Vbus change later */
930 ret = dwc3_qcom_register_extcon(qcom);
931 if (ret)
932 goto interconnect_exit;
933
934 wakeup_source = of_property_read_bool(dev->of_node, "wakeup-source");
935 device_init_wakeup(&pdev->dev, wakeup_source);
936 device_init_wakeup(&qcom->dwc3->dev, wakeup_source);
937
938 qcom->is_suspended = false;
939 pm_runtime_set_active(dev);
940 pm_runtime_enable(dev);
941 pm_runtime_forbid(dev);
942
943 return 0;
944
945interconnect_exit:
946 dwc3_qcom_interconnect_exit(qcom);
947depopulate:
948 if (np) {
949 of_platform_depopulate(&pdev->dev);
950 } else {
951 device_remove_software_node(&qcom->dwc3->dev);
952 platform_device_del(qcom->dwc3);
953 }
954 platform_device_put(qcom->dwc3);
955free_urs:
956 if (qcom->urs_usb)
957 dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb);
958clk_disable:
959 for (i = qcom->num_clocks - 1; i >= 0; i--) {
960 clk_disable_unprepare(qcom->clks[i]);
961 clk_put(qcom->clks[i]);
962 }
963reset_assert:
964 reset_control_assert(qcom->resets);
965
966 return ret;
967}
968
969static void dwc3_qcom_remove(struct platform_device *pdev)
970{
971 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
972 struct device_node *np = pdev->dev.of_node;
973 struct device *dev = &pdev->dev;
974 int i;
975
976 if (np) {
977 of_platform_depopulate(&pdev->dev);
978 } else {
979 device_remove_software_node(&qcom->dwc3->dev);
980 platform_device_del(qcom->dwc3);
981 }
982 platform_device_put(qcom->dwc3);
983
984 if (qcom->urs_usb)
985 dwc3_qcom_destroy_urs_usb_platdev(qcom->urs_usb);
986
987 for (i = qcom->num_clocks - 1; i >= 0; i--) {
988 clk_disable_unprepare(qcom->clks[i]);
989 clk_put(qcom->clks[i]);
990 }
991 qcom->num_clocks = 0;
992
993 dwc3_qcom_interconnect_exit(qcom);
994 reset_control_assert(qcom->resets);
995
996 pm_runtime_allow(dev);
997 pm_runtime_disable(dev);
998}
999
1000static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
1001{
1002 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1003 bool wakeup = device_may_wakeup(dev);
1004 int ret;
1005
1006 ret = dwc3_qcom_suspend(qcom, wakeup);
1007 if (ret)
1008 return ret;
1009
1010 qcom->pm_suspended = true;
1011
1012 return 0;
1013}
1014
1015static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
1016{
1017 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1018 bool wakeup = device_may_wakeup(dev);
1019 int ret;
1020
1021 ret = dwc3_qcom_resume(qcom, wakeup);
1022 if (ret)
1023 return ret;
1024
1025 qcom->pm_suspended = false;
1026
1027 return 0;
1028}
1029
1030static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
1031{
1032 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1033
1034 return dwc3_qcom_suspend(qcom, true);
1035}
1036
1037static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
1038{
1039 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
1040
1041 return dwc3_qcom_resume(qcom, true);
1042}
1043
1044static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
1045 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
1046 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
1047 NULL)
1048};
1049
1050static const struct of_device_id dwc3_qcom_of_match[] = {
1051 { .compatible = "qcom,dwc3" },
1052 { }
1053};
1054MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
1055
1056#ifdef CONFIG_ACPI
1057static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
1058 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1059 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1060 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1061 .qusb2_phy_irq_index = 1,
1062 .dp_hs_phy_irq_index = 4,
1063 .dm_hs_phy_irq_index = 3,
1064 .ss_phy_irq_index = 2
1065};
1066
1067static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
1068 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1069 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1070 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1071 .qusb2_phy_irq_index = 1,
1072 .dp_hs_phy_irq_index = 4,
1073 .dm_hs_phy_irq_index = 3,
1074 .ss_phy_irq_index = 2,
1075 .is_urs = true,
1076};
1077
1078static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
1079 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
1080 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
1081 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
1082 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
1083 { },
1084};
1085MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
1086#endif
1087
1088static struct platform_driver dwc3_qcom_driver = {
1089 .probe = dwc3_qcom_probe,
1090 .remove_new = dwc3_qcom_remove,
1091 .driver = {
1092 .name = "dwc3-qcom",
1093 .pm = &dwc3_qcom_dev_pm_ops,
1094 .of_match_table = dwc3_qcom_of_match,
1095 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
1096 },
1097};
1098
1099module_platform_driver(dwc3_qcom_driver);
1100
1101MODULE_LICENSE("GPL v2");
1102MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
3 *
4 * Inspired by dwc3-of-simple.c
5 */
6
7#include <linux/acpi.h>
8#include <linux/io.h>
9#include <linux/of.h>
10#include <linux/clk.h>
11#include <linux/irq.h>
12#include <linux/of_clk.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/extcon.h>
16#include <linux/interconnect.h>
17#include <linux/of_platform.h>
18#include <linux/platform_device.h>
19#include <linux/phy/phy.h>
20#include <linux/usb/of.h>
21#include <linux/reset.h>
22#include <linux/iopoll.h>
23
24#include "core.h"
25
26/* USB QSCRATCH Hardware registers */
27#define QSCRATCH_HS_PHY_CTRL 0x10
28#define UTMI_OTG_VBUS_VALID BIT(20)
29#define SW_SESSVLD_SEL BIT(28)
30
31#define QSCRATCH_SS_PHY_CTRL 0x30
32#define LANE0_PWR_PRESENT BIT(24)
33
34#define QSCRATCH_GENERAL_CFG 0x08
35#define PIPE_UTMI_CLK_SEL BIT(0)
36#define PIPE3_PHYSTATUS_SW BIT(3)
37#define PIPE_UTMI_CLK_DIS BIT(8)
38
39#define PWR_EVNT_IRQ_STAT_REG 0x58
40#define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
41#define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
42
43#define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
44#define SDM845_QSCRATCH_SIZE 0x400
45#define SDM845_DWC3_CORE_SIZE 0xcd00
46
47/* Interconnect path bandwidths in MBps */
48#define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
49#define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
50#define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
51#define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
52#define APPS_USB_AVG_BW 0
53#define APPS_USB_PEAK_BW MBps_to_icc(40)
54
55struct dwc3_acpi_pdata {
56 u32 qscratch_base_offset;
57 u32 qscratch_base_size;
58 u32 dwc3_core_base_size;
59 int hs_phy_irq_index;
60 int dp_hs_phy_irq_index;
61 int dm_hs_phy_irq_index;
62 int ss_phy_irq_index;
63 bool is_urs;
64};
65
66struct dwc3_qcom {
67 struct device *dev;
68 void __iomem *qscratch_base;
69 struct platform_device *dwc3;
70 struct platform_device *urs_usb;
71 struct clk **clks;
72 int num_clocks;
73 struct reset_control *resets;
74
75 int hs_phy_irq;
76 int dp_hs_phy_irq;
77 int dm_hs_phy_irq;
78 int ss_phy_irq;
79
80 struct extcon_dev *edev;
81 struct extcon_dev *host_edev;
82 struct notifier_block vbus_nb;
83 struct notifier_block host_nb;
84
85 const struct dwc3_acpi_pdata *acpi_pdata;
86
87 enum usb_dr_mode mode;
88 bool is_suspended;
89 bool pm_suspended;
90 struct icc_path *icc_path_ddr;
91 struct icc_path *icc_path_apps;
92};
93
94static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
95{
96 u32 reg;
97
98 reg = readl(base + offset);
99 reg |= val;
100 writel(reg, base + offset);
101
102 /* ensure that above write is through */
103 readl(base + offset);
104}
105
106static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
107{
108 u32 reg;
109
110 reg = readl(base + offset);
111 reg &= ~val;
112 writel(reg, base + offset);
113
114 /* ensure that above write is through */
115 readl(base + offset);
116}
117
118static void dwc3_qcom_vbus_overrride_enable(struct dwc3_qcom *qcom, bool enable)
119{
120 if (enable) {
121 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
122 LANE0_PWR_PRESENT);
123 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
124 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
125 } else {
126 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
127 LANE0_PWR_PRESENT);
128 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
129 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
130 }
131}
132
133static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
134 unsigned long event, void *ptr)
135{
136 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
137
138 /* enable vbus override for device mode */
139 dwc3_qcom_vbus_overrride_enable(qcom, event);
140 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
141
142 return NOTIFY_DONE;
143}
144
145static int dwc3_qcom_host_notifier(struct notifier_block *nb,
146 unsigned long event, void *ptr)
147{
148 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
149
150 /* disable vbus override in host mode */
151 dwc3_qcom_vbus_overrride_enable(qcom, !event);
152 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
153
154 return NOTIFY_DONE;
155}
156
157static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
158{
159 struct device *dev = qcom->dev;
160 struct extcon_dev *host_edev;
161 int ret;
162
163 if (!of_property_read_bool(dev->of_node, "extcon"))
164 return 0;
165
166 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
167 if (IS_ERR(qcom->edev))
168 return PTR_ERR(qcom->edev);
169
170 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
171
172 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
173 if (IS_ERR(qcom->host_edev))
174 qcom->host_edev = NULL;
175
176 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
177 &qcom->vbus_nb);
178 if (ret < 0) {
179 dev_err(dev, "VBUS notifier register failed\n");
180 return ret;
181 }
182
183 if (qcom->host_edev)
184 host_edev = qcom->host_edev;
185 else
186 host_edev = qcom->edev;
187
188 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
189 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
190 &qcom->host_nb);
191 if (ret < 0) {
192 dev_err(dev, "Host notifier register failed\n");
193 return ret;
194 }
195
196 /* Update initial VBUS override based on extcon state */
197 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
198 !extcon_get_state(host_edev, EXTCON_USB_HOST))
199 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
200 else
201 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
202
203 return 0;
204}
205
206static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
207{
208 int ret;
209
210 ret = icc_enable(qcom->icc_path_ddr);
211 if (ret)
212 return ret;
213
214 ret = icc_enable(qcom->icc_path_apps);
215 if (ret)
216 icc_disable(qcom->icc_path_ddr);
217
218 return ret;
219}
220
221static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
222{
223 int ret;
224
225 ret = icc_disable(qcom->icc_path_ddr);
226 if (ret)
227 return ret;
228
229 ret = icc_disable(qcom->icc_path_apps);
230 if (ret)
231 icc_enable(qcom->icc_path_ddr);
232
233 return ret;
234}
235
236/**
237 * dwc3_qcom_interconnect_init() - Get interconnect path handles
238 * and set bandwidth.
239 * @qcom: Pointer to the concerned usb core.
240 *
241 */
242static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
243{
244 struct device *dev = qcom->dev;
245 int ret;
246
247 if (has_acpi_companion(dev))
248 return 0;
249
250 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
251 if (IS_ERR(qcom->icc_path_ddr)) {
252 dev_err(dev, "failed to get usb-ddr path: %ld\n",
253 PTR_ERR(qcom->icc_path_ddr));
254 return PTR_ERR(qcom->icc_path_ddr);
255 }
256
257 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
258 if (IS_ERR(qcom->icc_path_apps)) {
259 dev_err(dev, "failed to get apps-usb path: %ld\n",
260 PTR_ERR(qcom->icc_path_apps));
261 return PTR_ERR(qcom->icc_path_apps);
262 }
263
264 if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
265 usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
266 ret = icc_set_bw(qcom->icc_path_ddr,
267 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
268 else
269 ret = icc_set_bw(qcom->icc_path_ddr,
270 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
271
272 if (ret) {
273 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
274 return ret;
275 }
276
277 ret = icc_set_bw(qcom->icc_path_apps,
278 APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
279 if (ret) {
280 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
281 return ret;
282 }
283
284 return 0;
285}
286
287/**
288 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
289 * @qcom: Pointer to the concerned usb core.
290 *
291 * This function is used to release interconnect path handle.
292 */
293static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
294{
295 icc_put(qcom->icc_path_ddr);
296 icc_put(qcom->icc_path_apps);
297}
298
299static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
300{
301 if (qcom->hs_phy_irq) {
302 disable_irq_wake(qcom->hs_phy_irq);
303 disable_irq_nosync(qcom->hs_phy_irq);
304 }
305
306 if (qcom->dp_hs_phy_irq) {
307 disable_irq_wake(qcom->dp_hs_phy_irq);
308 disable_irq_nosync(qcom->dp_hs_phy_irq);
309 }
310
311 if (qcom->dm_hs_phy_irq) {
312 disable_irq_wake(qcom->dm_hs_phy_irq);
313 disable_irq_nosync(qcom->dm_hs_phy_irq);
314 }
315
316 if (qcom->ss_phy_irq) {
317 disable_irq_wake(qcom->ss_phy_irq);
318 disable_irq_nosync(qcom->ss_phy_irq);
319 }
320}
321
322static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
323{
324 if (qcom->hs_phy_irq) {
325 enable_irq(qcom->hs_phy_irq);
326 enable_irq_wake(qcom->hs_phy_irq);
327 }
328
329 if (qcom->dp_hs_phy_irq) {
330 enable_irq(qcom->dp_hs_phy_irq);
331 enable_irq_wake(qcom->dp_hs_phy_irq);
332 }
333
334 if (qcom->dm_hs_phy_irq) {
335 enable_irq(qcom->dm_hs_phy_irq);
336 enable_irq_wake(qcom->dm_hs_phy_irq);
337 }
338
339 if (qcom->ss_phy_irq) {
340 enable_irq(qcom->ss_phy_irq);
341 enable_irq_wake(qcom->ss_phy_irq);
342 }
343}
344
345static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
346{
347 u32 val;
348 int i, ret;
349
350 if (qcom->is_suspended)
351 return 0;
352
353 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
354 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
355 dev_err(qcom->dev, "HS-PHY not in L2\n");
356
357 for (i = qcom->num_clocks - 1; i >= 0; i--)
358 clk_disable_unprepare(qcom->clks[i]);
359
360 ret = dwc3_qcom_interconnect_disable(qcom);
361 if (ret)
362 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
363
364 if (device_may_wakeup(qcom->dev))
365 dwc3_qcom_enable_interrupts(qcom);
366
367 qcom->is_suspended = true;
368
369 return 0;
370}
371
372static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
373{
374 int ret;
375 int i;
376
377 if (!qcom->is_suspended)
378 return 0;
379
380 if (device_may_wakeup(qcom->dev))
381 dwc3_qcom_disable_interrupts(qcom);
382
383 for (i = 0; i < qcom->num_clocks; i++) {
384 ret = clk_prepare_enable(qcom->clks[i]);
385 if (ret < 0) {
386 while (--i >= 0)
387 clk_disable_unprepare(qcom->clks[i]);
388 return ret;
389 }
390 }
391
392 ret = dwc3_qcom_interconnect_enable(qcom);
393 if (ret)
394 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
395
396 /* Clear existing events from PHY related to L2 in/out */
397 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
398 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
399
400 qcom->is_suspended = false;
401
402 return 0;
403}
404
405static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
406{
407 struct dwc3_qcom *qcom = data;
408 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
409
410 /* If pm_suspended then let pm_resume take care of resuming h/w */
411 if (qcom->pm_suspended)
412 return IRQ_HANDLED;
413
414 if (dwc->xhci)
415 pm_runtime_resume(&dwc->xhci->dev);
416
417 return IRQ_HANDLED;
418}
419
420static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
421{
422 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
423 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
424 PIPE_UTMI_CLK_DIS);
425
426 usleep_range(100, 1000);
427
428 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
429 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
430
431 usleep_range(100, 1000);
432
433 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
434 PIPE_UTMI_CLK_DIS);
435}
436
437static int dwc3_qcom_get_irq(struct platform_device *pdev,
438 const char *name, int num)
439{
440 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
441 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
442 struct device_node *np = pdev->dev.of_node;
443 int ret;
444
445 if (np)
446 ret = platform_get_irq_byname(pdev_irq, name);
447 else
448 ret = platform_get_irq(pdev_irq, num);
449
450 return ret;
451}
452
453static int dwc3_qcom_setup_irq(struct platform_device *pdev)
454{
455 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
456 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
457 int irq;
458 int ret;
459
460 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
461 pdata ? pdata->hs_phy_irq_index : -1);
462 if (irq > 0) {
463 /* Keep wakeup interrupts disabled until suspend */
464 irq_set_status_flags(irq, IRQ_NOAUTOEN);
465 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
466 qcom_dwc3_resume_irq,
467 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
468 "qcom_dwc3 HS", qcom);
469 if (ret) {
470 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
471 return ret;
472 }
473 qcom->hs_phy_irq = irq;
474 }
475
476 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
477 pdata ? pdata->dp_hs_phy_irq_index : -1);
478 if (irq > 0) {
479 irq_set_status_flags(irq, IRQ_NOAUTOEN);
480 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
481 qcom_dwc3_resume_irq,
482 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
483 "qcom_dwc3 DP_HS", qcom);
484 if (ret) {
485 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
486 return ret;
487 }
488 qcom->dp_hs_phy_irq = irq;
489 }
490
491 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
492 pdata ? pdata->dm_hs_phy_irq_index : -1);
493 if (irq > 0) {
494 irq_set_status_flags(irq, IRQ_NOAUTOEN);
495 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
496 qcom_dwc3_resume_irq,
497 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
498 "qcom_dwc3 DM_HS", qcom);
499 if (ret) {
500 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
501 return ret;
502 }
503 qcom->dm_hs_phy_irq = irq;
504 }
505
506 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
507 pdata ? pdata->ss_phy_irq_index : -1);
508 if (irq > 0) {
509 irq_set_status_flags(irq, IRQ_NOAUTOEN);
510 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
511 qcom_dwc3_resume_irq,
512 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
513 "qcom_dwc3 SS", qcom);
514 if (ret) {
515 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
516 return ret;
517 }
518 qcom->ss_phy_irq = irq;
519 }
520
521 return 0;
522}
523
524static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
525{
526 struct device *dev = qcom->dev;
527 struct device_node *np = dev->of_node;
528 int i;
529
530 if (!np || !count)
531 return 0;
532
533 if (count < 0)
534 return count;
535
536 qcom->num_clocks = count;
537
538 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
539 sizeof(struct clk *), GFP_KERNEL);
540 if (!qcom->clks)
541 return -ENOMEM;
542
543 for (i = 0; i < qcom->num_clocks; i++) {
544 struct clk *clk;
545 int ret;
546
547 clk = of_clk_get(np, i);
548 if (IS_ERR(clk)) {
549 while (--i >= 0)
550 clk_put(qcom->clks[i]);
551 return PTR_ERR(clk);
552 }
553
554 ret = clk_prepare_enable(clk);
555 if (ret < 0) {
556 while (--i >= 0) {
557 clk_disable_unprepare(qcom->clks[i]);
558 clk_put(qcom->clks[i]);
559 }
560 clk_put(clk);
561
562 return ret;
563 }
564
565 qcom->clks[i] = clk;
566 }
567
568 return 0;
569}
570
571static const struct property_entry dwc3_qcom_acpi_properties[] = {
572 PROPERTY_ENTRY_STRING("dr_mode", "host"),
573 {}
574};
575
576static const struct software_node dwc3_qcom_swnode = {
577 .properties = dwc3_qcom_acpi_properties,
578};
579
580static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
581{
582 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
583 struct device *dev = &pdev->dev;
584 struct resource *res, *child_res = NULL;
585 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
586 pdev;
587 int irq;
588 int ret;
589
590 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
591 if (!qcom->dwc3)
592 return -ENOMEM;
593
594 qcom->dwc3->dev.parent = dev;
595 qcom->dwc3->dev.type = dev->type;
596 qcom->dwc3->dev.dma_mask = dev->dma_mask;
597 qcom->dwc3->dev.dma_parms = dev->dma_parms;
598 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
599
600 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
601 if (!child_res)
602 return -ENOMEM;
603
604 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
605 if (!res) {
606 dev_err(&pdev->dev, "failed to get memory resource\n");
607 ret = -ENODEV;
608 goto out;
609 }
610
611 child_res[0].flags = res->flags;
612 child_res[0].start = res->start;
613 child_res[0].end = child_res[0].start +
614 qcom->acpi_pdata->dwc3_core_base_size;
615
616 irq = platform_get_irq(pdev_irq, 0);
617 if (irq < 0) {
618 ret = irq;
619 goto out;
620 }
621 child_res[1].flags = IORESOURCE_IRQ;
622 child_res[1].start = child_res[1].end = irq;
623
624 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
625 if (ret) {
626 dev_err(&pdev->dev, "failed to add resources\n");
627 goto out;
628 }
629
630 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
631 if (ret < 0) {
632 dev_err(&pdev->dev, "failed to add properties\n");
633 goto out;
634 }
635
636 ret = platform_device_add(qcom->dwc3);
637 if (ret) {
638 dev_err(&pdev->dev, "failed to add device\n");
639 device_remove_software_node(&qcom->dwc3->dev);
640 }
641
642out:
643 kfree(child_res);
644 return ret;
645}
646
647static int dwc3_qcom_of_register_core(struct platform_device *pdev)
648{
649 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
650 struct device_node *np = pdev->dev.of_node, *dwc3_np;
651 struct device *dev = &pdev->dev;
652 int ret;
653
654 dwc3_np = of_get_compatible_child(np, "snps,dwc3");
655 if (!dwc3_np) {
656 dev_err(dev, "failed to find dwc3 core child\n");
657 return -ENODEV;
658 }
659
660 ret = of_platform_populate(np, NULL, NULL, dev);
661 if (ret) {
662 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
663 goto node_put;
664 }
665
666 qcom->dwc3 = of_find_device_by_node(dwc3_np);
667 if (!qcom->dwc3) {
668 ret = -ENODEV;
669 dev_err(dev, "failed to get dwc3 platform device\n");
670 }
671
672node_put:
673 of_node_put(dwc3_np);
674
675 return ret;
676}
677
678static struct platform_device *
679dwc3_qcom_create_urs_usb_platdev(struct device *dev)
680{
681 struct fwnode_handle *fwh;
682 struct acpi_device *adev;
683 char name[8];
684 int ret;
685 int id;
686
687 /* Figure out device id */
688 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
689 if (!ret)
690 return NULL;
691
692 /* Find the child using name */
693 snprintf(name, sizeof(name), "USB%d", id);
694 fwh = fwnode_get_named_child_node(dev->fwnode, name);
695 if (!fwh)
696 return NULL;
697
698 adev = to_acpi_device_node(fwh);
699 if (!adev)
700 return NULL;
701
702 return acpi_create_platform_device(adev, NULL);
703}
704
705static int dwc3_qcom_probe(struct platform_device *pdev)
706{
707 struct device_node *np = pdev->dev.of_node;
708 struct device *dev = &pdev->dev;
709 struct dwc3_qcom *qcom;
710 struct resource *res, *parent_res = NULL;
711 int ret, i;
712 bool ignore_pipe_clk;
713
714 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
715 if (!qcom)
716 return -ENOMEM;
717
718 platform_set_drvdata(pdev, qcom);
719 qcom->dev = &pdev->dev;
720
721 if (has_acpi_companion(dev)) {
722 qcom->acpi_pdata = acpi_device_get_match_data(dev);
723 if (!qcom->acpi_pdata) {
724 dev_err(&pdev->dev, "no supporting ACPI device data\n");
725 return -EINVAL;
726 }
727 }
728
729 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
730 if (IS_ERR(qcom->resets)) {
731 ret = PTR_ERR(qcom->resets);
732 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
733 return ret;
734 }
735
736 ret = reset_control_assert(qcom->resets);
737 if (ret) {
738 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
739 return ret;
740 }
741
742 usleep_range(10, 1000);
743
744 ret = reset_control_deassert(qcom->resets);
745 if (ret) {
746 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
747 goto reset_assert;
748 }
749
750 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
751 if (ret) {
752 dev_err(dev, "failed to get clocks\n");
753 goto reset_assert;
754 }
755
756 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
757
758 if (np) {
759 parent_res = res;
760 } else {
761 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
762 if (!parent_res)
763 return -ENOMEM;
764
765 parent_res->start = res->start +
766 qcom->acpi_pdata->qscratch_base_offset;
767 parent_res->end = parent_res->start +
768 qcom->acpi_pdata->qscratch_base_size;
769
770 if (qcom->acpi_pdata->is_urs) {
771 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
772 if (!qcom->urs_usb) {
773 dev_err(dev, "failed to create URS USB platdev\n");
774 return -ENODEV;
775 }
776 }
777 }
778
779 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
780 if (IS_ERR(qcom->qscratch_base)) {
781 ret = PTR_ERR(qcom->qscratch_base);
782 goto clk_disable;
783 }
784
785 ret = dwc3_qcom_setup_irq(pdev);
786 if (ret) {
787 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
788 goto clk_disable;
789 }
790
791 /*
792 * Disable pipe_clk requirement if specified. Used when dwc3
793 * operates without SSPHY and only HS/FS/LS modes are supported.
794 */
795 ignore_pipe_clk = device_property_read_bool(dev,
796 "qcom,select-utmi-as-pipe-clk");
797 if (ignore_pipe_clk)
798 dwc3_qcom_select_utmi_clk(qcom);
799
800 if (np)
801 ret = dwc3_qcom_of_register_core(pdev);
802 else
803 ret = dwc3_qcom_acpi_register_core(pdev);
804
805 if (ret) {
806 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
807 goto depopulate;
808 }
809
810 ret = dwc3_qcom_interconnect_init(qcom);
811 if (ret)
812 goto depopulate;
813
814 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
815
816 /* enable vbus override for device mode */
817 if (qcom->mode == USB_DR_MODE_PERIPHERAL)
818 dwc3_qcom_vbus_overrride_enable(qcom, true);
819
820 /* register extcon to override sw_vbus on Vbus change later */
821 ret = dwc3_qcom_register_extcon(qcom);
822 if (ret)
823 goto interconnect_exit;
824
825 device_init_wakeup(&pdev->dev, 1);
826 qcom->is_suspended = false;
827 pm_runtime_set_active(dev);
828 pm_runtime_enable(dev);
829 pm_runtime_forbid(dev);
830
831 return 0;
832
833interconnect_exit:
834 dwc3_qcom_interconnect_exit(qcom);
835depopulate:
836 if (np)
837 of_platform_depopulate(&pdev->dev);
838 else
839 platform_device_put(pdev);
840clk_disable:
841 for (i = qcom->num_clocks - 1; i >= 0; i--) {
842 clk_disable_unprepare(qcom->clks[i]);
843 clk_put(qcom->clks[i]);
844 }
845reset_assert:
846 reset_control_assert(qcom->resets);
847
848 return ret;
849}
850
851static int dwc3_qcom_remove(struct platform_device *pdev)
852{
853 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
854 struct device *dev = &pdev->dev;
855 int i;
856
857 device_remove_software_node(&qcom->dwc3->dev);
858 of_platform_depopulate(dev);
859
860 for (i = qcom->num_clocks - 1; i >= 0; i--) {
861 clk_disable_unprepare(qcom->clks[i]);
862 clk_put(qcom->clks[i]);
863 }
864 qcom->num_clocks = 0;
865
866 dwc3_qcom_interconnect_exit(qcom);
867 reset_control_assert(qcom->resets);
868
869 pm_runtime_allow(dev);
870 pm_runtime_disable(dev);
871
872 return 0;
873}
874
875static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
876{
877 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
878 int ret = 0;
879
880 ret = dwc3_qcom_suspend(qcom);
881 if (!ret)
882 qcom->pm_suspended = true;
883
884 return ret;
885}
886
887static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
888{
889 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
890 int ret;
891
892 ret = dwc3_qcom_resume(qcom);
893 if (!ret)
894 qcom->pm_suspended = false;
895
896 return ret;
897}
898
899static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
900{
901 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
902
903 return dwc3_qcom_suspend(qcom);
904}
905
906static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
907{
908 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
909
910 return dwc3_qcom_resume(qcom);
911}
912
913static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
914 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
915 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
916 NULL)
917};
918
919static const struct of_device_id dwc3_qcom_of_match[] = {
920 { .compatible = "qcom,dwc3" },
921 { .compatible = "qcom,msm8996-dwc3" },
922 { .compatible = "qcom,msm8998-dwc3" },
923 { .compatible = "qcom,sdm845-dwc3" },
924 { }
925};
926MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
927
928#ifdef CONFIG_ACPI
929static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
930 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
931 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
932 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
933 .hs_phy_irq_index = 1,
934 .dp_hs_phy_irq_index = 4,
935 .dm_hs_phy_irq_index = 3,
936 .ss_phy_irq_index = 2
937};
938
939static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
940 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
941 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
942 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
943 .hs_phy_irq_index = 1,
944 .dp_hs_phy_irq_index = 4,
945 .dm_hs_phy_irq_index = 3,
946 .ss_phy_irq_index = 2,
947 .is_urs = true,
948};
949
950static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
951 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
952 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
953 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
954 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
955 { },
956};
957MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
958#endif
959
960static struct platform_driver dwc3_qcom_driver = {
961 .probe = dwc3_qcom_probe,
962 .remove = dwc3_qcom_remove,
963 .driver = {
964 .name = "dwc3-qcom",
965 .pm = &dwc3_qcom_dev_pm_ops,
966 .of_match_table = dwc3_qcom_of_match,
967 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
968 },
969};
970
971module_platform_driver(dwc3_qcom_driver);
972
973MODULE_LICENSE("GPL v2");
974MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");