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1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023 Linaro Ltd. */
4
5#include <linux/types.h>
6
7#include "../gsi.h"
8#include "../reg.h"
9#include "../gsi_reg.h"
10
11REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
12 0x0000c020 + 0x1000 * GSI_EE_AP);
13
14REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
15 0x0000c024 + 0x1000 * GSI_EE_AP);
16
17static const u32 reg_ch_c_cntxt_0_fmask[] = {
18 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
19 [CHTYPE_DIR] = BIT(3),
20 [CH_EE] = GENMASK(7, 4),
21 [CHID] = GENMASK(12, 8),
22 [CHTYPE_PROTOCOL_MSB] = BIT(13),
23 [ERINDEX] = GENMASK(18, 14),
24 /* Bit 19 reserved */
25 [CHSTATE] = GENMASK(23, 20),
26 [ELEMENT_SIZE] = GENMASK(31, 24),
27};
28
29REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
30 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
31
32static const u32 reg_ch_c_cntxt_1_fmask[] = {
33 [CH_R_LENGTH] = GENMASK(19, 0),
34 /* Bits 20-31 reserved */
35};
36
37REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
38 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
39
40REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
41
42REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
43
44static const u32 reg_ch_c_qos_fmask[] = {
45 [WRR_WEIGHT] = GENMASK(3, 0),
46 /* Bits 4-7 reserved */
47 [MAX_PREFETCH] = BIT(8),
48 [USE_DB_ENG] = BIT(9),
49 [PREFETCH_MODE] = GENMASK(13, 10),
50 /* Bits 14-15 reserved */
51 [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
52 [DB_IN_BYTES] = BIT(24),
53 /* Bits 25-31 reserved */
54};
55
56REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
57
58static const u32 reg_error_log_fmask[] = {
59 [ERR_ARG3] = GENMASK(3, 0),
60 [ERR_ARG2] = GENMASK(7, 4),
61 [ERR_ARG1] = GENMASK(11, 8),
62 [ERR_CODE] = GENMASK(15, 12),
63 /* Bits 16-18 reserved */
64 [ERR_VIRT_IDX] = GENMASK(23, 19),
65 [ERR_TYPE] = GENMASK(27, 24),
66 [ERR_EE] = GENMASK(31, 28),
67};
68
69REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
70 0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
71
72REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
73 0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
74
75REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
76 0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
77
78REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
79 0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
80
81static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
82 [EV_CHTYPE] = GENMASK(3, 0),
83 [EV_EE] = GENMASK(7, 4),
84 [EV_EVCHID] = GENMASK(15, 8),
85 [EV_INTYPE] = BIT(16),
86 /* Bits 17-19 reserved */
87 [EV_CHSTATE] = GENMASK(23, 20),
88 [EV_ELEMENT_SIZE] = GENMASK(31, 24),
89};
90
91REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
92 0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
93
94static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
95 [R_LENGTH] = GENMASK(19, 0),
96};
97
98REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
99 0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
100
101REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
102 0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
103
104REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
105 0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
106
107REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
108 0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
109
110static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
111 [EV_MODT] = GENMASK(15, 0),
112 [EV_MODC] = GENMASK(23, 16),
113 [EV_MOD_CNT] = GENMASK(31, 24),
114};
115
116REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
117 0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
118
119REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
120 0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
121
122REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
123 0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
124
125REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
126 0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
127
128REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
129 0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
130
131REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
132 0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
133
134REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
135 0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
136
137REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
138 0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
139
140REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
141 0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
142
143REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
144 0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
145
146static const u32 reg_gsi_status_fmask[] = {
147 [ENABLED] = BIT(0),
148 /* Bits 1-31 reserved */
149};
150
151REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
152
153static const u32 reg_ch_cmd_fmask[] = {
154 [CH_CHID] = GENMASK(7, 0),
155 /* Bits 8-23 reserved */
156 [CH_OPCODE] = GENMASK(31, 24),
157};
158
159REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
160
161static const u32 reg_ev_ch_cmd_fmask[] = {
162 [EV_CHID] = GENMASK(7, 0),
163 /* Bits 8-23 reserved */
164 [EV_OPCODE] = GENMASK(31, 24),
165};
166
167REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
168
169static const u32 reg_generic_cmd_fmask[] = {
170 [GENERIC_OPCODE] = GENMASK(4, 0),
171 [GENERIC_CHID] = GENMASK(9, 5),
172 [GENERIC_EE] = GENMASK(13, 10),
173 /* Bits 14-23 reserved */
174 [GENERIC_PARAMS] = GENMASK(31, 24),
175};
176
177REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
178
179static const u32 reg_hw_param_2_fmask[] = {
180 [IRAM_SIZE] = GENMASK(2, 0),
181 [NUM_CH_PER_EE] = GENMASK(7, 3),
182 [NUM_EV_PER_EE] = GENMASK(12, 8),
183 [GSI_CH_PEND_TRANSLATE] = BIT(13),
184 [GSI_CH_FULL_LOGIC] = BIT(14),
185 [GSI_USE_SDMA] = BIT(15),
186 [GSI_SDMA_N_INT] = GENMASK(18, 16),
187 [GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
188 [GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
189 [GSI_USE_RD_WR_ENG] = BIT(30),
190 [GSI_USE_INTER_EE] = BIT(31),
191};
192
193REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
194
195REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
196
197REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
198
199REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
200
201REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
202
203REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
204 0x00012098 + 0x4000 * GSI_EE_AP);
205
206REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
207 0x0001209c + 0x4000 * GSI_EE_AP);
208
209REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
210 0x000120a0 + 0x4000 * GSI_EE_AP);
211
212REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
213 0x000120a4 + 0x4000 * GSI_EE_AP);
214
215REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
216
217REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
218 0x000120b8 + 0x4000 * GSI_EE_AP);
219
220REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
221 0x000120c0 + 0x4000 * GSI_EE_AP);
222
223REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
224
225REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
226
227REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
228
229REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
230
231REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
232
233REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
234
235static const u32 reg_cntxt_intset_fmask[] = {
236 [INTYPE] = BIT(0)
237 /* Bits 1-31 reserved */
238};
239
240REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
241
242REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
243
244REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
245
246static const u32 reg_cntxt_scratch_0_fmask[] = {
247 [INTER_EE_RESULT] = GENMASK(2, 0),
248 /* Bits 3-4 reserved */
249 [GENERIC_EE_RESULT] = GENMASK(7, 5),
250 /* Bits 8-31 reserved */
251};
252
253REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
254
255static const struct reg *reg_array[] = {
256 [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk,
257 [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk,
258 [CH_C_CNTXT_0] = ®_ch_c_cntxt_0,
259 [CH_C_CNTXT_1] = ®_ch_c_cntxt_1,
260 [CH_C_CNTXT_2] = ®_ch_c_cntxt_2,
261 [CH_C_CNTXT_3] = ®_ch_c_cntxt_3,
262 [CH_C_QOS] = ®_ch_c_qos,
263 [CH_C_SCRATCH_0] = ®_ch_c_scratch_0,
264 [CH_C_SCRATCH_1] = ®_ch_c_scratch_1,
265 [CH_C_SCRATCH_2] = ®_ch_c_scratch_2,
266 [CH_C_SCRATCH_3] = ®_ch_c_scratch_3,
267 [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0,
268 [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1,
269 [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2,
270 [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3,
271 [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4,
272 [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8,
273 [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9,
274 [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10,
275 [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11,
276 [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12,
277 [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13,
278 [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0,
279 [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1,
280 [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0,
281 [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0,
282 [GSI_STATUS] = ®_gsi_status,
283 [CH_CMD] = ®_ch_cmd,
284 [EV_CH_CMD] = ®_ev_ch_cmd,
285 [GENERIC_CMD] = ®_generic_cmd,
286 [HW_PARAM_2] = ®_hw_param_2,
287 [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq,
288 [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk,
289 [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq,
290 [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq,
291 [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk,
292 [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk,
293 [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr,
294 [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr,
295 [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq,
296 [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk,
297 [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr,
298 [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts,
299 [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en,
300 [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr,
301 [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts,
302 [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en,
303 [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr,
304 [CNTXT_INTSET] = ®_cntxt_intset,
305 [ERROR_LOG] = ®_error_log,
306 [ERROR_LOG_CLR] = ®_error_log_clr,
307 [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0,
308};
309
310const struct regs gsi_regs_v4_11 = {
311 .reg_count = ARRAY_SIZE(reg_array),
312 .reg = reg_array,
313};
1// SPDX-License-Identifier: GPL-2.0
2
3/* Copyright (C) 2023-2024 Linaro Ltd. */
4
5#include <linux/array_size.h>
6#include <linux/bits.h>
7#include <linux/types.h>
8
9#include "../gsi_reg.h"
10#include "../ipa_version.h"
11#include "../reg.h"
12
13REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
14 0x0000c020 + 0x1000 * GSI_EE_AP);
15
16REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
17 0x0000c024 + 0x1000 * GSI_EE_AP);
18
19static const u32 reg_ch_c_cntxt_0_fmask[] = {
20 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
21 [CHTYPE_DIR] = BIT(3),
22 [CH_EE] = GENMASK(7, 4),
23 [CHID] = GENMASK(12, 8),
24 [CHTYPE_PROTOCOL_MSB] = BIT(13),
25 [ERINDEX] = GENMASK(18, 14),
26 /* Bit 19 reserved */
27 [CHSTATE] = GENMASK(23, 20),
28 [ELEMENT_SIZE] = GENMASK(31, 24),
29};
30
31REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
32 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
33
34static const u32 reg_ch_c_cntxt_1_fmask[] = {
35 [CH_R_LENGTH] = GENMASK(19, 0),
36 /* Bits 20-31 reserved */
37};
38
39REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
40 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
41
42REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
43
44REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
45
46static const u32 reg_ch_c_qos_fmask[] = {
47 [WRR_WEIGHT] = GENMASK(3, 0),
48 /* Bits 4-7 reserved */
49 [MAX_PREFETCH] = BIT(8),
50 [USE_DB_ENG] = BIT(9),
51 [PREFETCH_MODE] = GENMASK(13, 10),
52 /* Bits 14-15 reserved */
53 [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
54 [DB_IN_BYTES] = BIT(24),
55 /* Bits 25-31 reserved */
56};
57
58REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
59
60static const u32 reg_error_log_fmask[] = {
61 [ERR_ARG3] = GENMASK(3, 0),
62 [ERR_ARG2] = GENMASK(7, 4),
63 [ERR_ARG1] = GENMASK(11, 8),
64 [ERR_CODE] = GENMASK(15, 12),
65 /* Bits 16-18 reserved */
66 [ERR_VIRT_IDX] = GENMASK(23, 19),
67 [ERR_TYPE] = GENMASK(27, 24),
68 [ERR_EE] = GENMASK(31, 28),
69};
70
71REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
72 0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
73
74REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
75 0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
76
77REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
78 0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
79
80REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
81 0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
82
83static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
84 [EV_CHTYPE] = GENMASK(3, 0),
85 [EV_EE] = GENMASK(7, 4),
86 [EV_EVCHID] = GENMASK(15, 8),
87 [EV_INTYPE] = BIT(16),
88 /* Bits 17-19 reserved */
89 [EV_CHSTATE] = GENMASK(23, 20),
90 [EV_ELEMENT_SIZE] = GENMASK(31, 24),
91};
92
93REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
94 0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
95
96static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
97 [R_LENGTH] = GENMASK(19, 0),
98};
99
100REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
101 0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
102
103REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
104 0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
105
106REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
107 0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
108
109REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
110 0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
111
112static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
113 [EV_MODT] = GENMASK(15, 0),
114 [EV_MODC] = GENMASK(23, 16),
115 [EV_MOD_CNT] = GENMASK(31, 24),
116};
117
118REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
119 0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
120
121REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
122 0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
123
124REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
125 0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
126
127REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
128 0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
129
130REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
131 0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
132
133REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
134 0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
135
136REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
137 0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
138
139REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
140 0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
141
142REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
143 0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
144
145REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
146 0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
147
148static const u32 reg_gsi_status_fmask[] = {
149 [ENABLED] = BIT(0),
150 /* Bits 1-31 reserved */
151};
152
153REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
154
155static const u32 reg_ch_cmd_fmask[] = {
156 [CH_CHID] = GENMASK(7, 0),
157 /* Bits 8-23 reserved */
158 [CH_OPCODE] = GENMASK(31, 24),
159};
160
161REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
162
163static const u32 reg_ev_ch_cmd_fmask[] = {
164 [EV_CHID] = GENMASK(7, 0),
165 /* Bits 8-23 reserved */
166 [EV_OPCODE] = GENMASK(31, 24),
167};
168
169REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
170
171static const u32 reg_generic_cmd_fmask[] = {
172 [GENERIC_OPCODE] = GENMASK(4, 0),
173 [GENERIC_CHID] = GENMASK(9, 5),
174 [GENERIC_EE] = GENMASK(13, 10),
175 /* Bits 14-23 reserved */
176 [GENERIC_PARAMS] = GENMASK(31, 24),
177};
178
179REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
180
181static const u32 reg_hw_param_2_fmask[] = {
182 [IRAM_SIZE] = GENMASK(2, 0),
183 [NUM_CH_PER_EE] = GENMASK(7, 3),
184 [NUM_EV_PER_EE] = GENMASK(12, 8),
185 [GSI_CH_PEND_TRANSLATE] = BIT(13),
186 [GSI_CH_FULL_LOGIC] = BIT(14),
187 [GSI_USE_SDMA] = BIT(15),
188 [GSI_SDMA_N_INT] = GENMASK(18, 16),
189 [GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
190 [GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
191 [GSI_USE_RD_WR_ENG] = BIT(30),
192 [GSI_USE_INTER_EE] = BIT(31),
193};
194
195REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
196
197REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
198
199REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
200
201REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
202
203REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
204
205REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
206 0x00012098 + 0x4000 * GSI_EE_AP);
207
208REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
209 0x0001209c + 0x4000 * GSI_EE_AP);
210
211REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
212 0x000120a0 + 0x4000 * GSI_EE_AP);
213
214REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
215 0x000120a4 + 0x4000 * GSI_EE_AP);
216
217REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
218
219REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
220 0x000120b8 + 0x4000 * GSI_EE_AP);
221
222REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
223 0x000120c0 + 0x4000 * GSI_EE_AP);
224
225REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
226
227REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
228
229REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
230
231REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
232
233REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
234
235REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
236
237static const u32 reg_cntxt_intset_fmask[] = {
238 [INTYPE] = BIT(0)
239 /* Bits 1-31 reserved */
240};
241
242REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
243
244REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
245
246REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
247
248static const u32 reg_cntxt_scratch_0_fmask[] = {
249 [INTER_EE_RESULT] = GENMASK(2, 0),
250 /* Bits 3-4 reserved */
251 [GENERIC_EE_RESULT] = GENMASK(7, 5),
252 /* Bits 8-31 reserved */
253};
254
255REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
256
257static const struct reg *reg_array[] = {
258 [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk,
259 [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk,
260 [CH_C_CNTXT_0] = ®_ch_c_cntxt_0,
261 [CH_C_CNTXT_1] = ®_ch_c_cntxt_1,
262 [CH_C_CNTXT_2] = ®_ch_c_cntxt_2,
263 [CH_C_CNTXT_3] = ®_ch_c_cntxt_3,
264 [CH_C_QOS] = ®_ch_c_qos,
265 [CH_C_SCRATCH_0] = ®_ch_c_scratch_0,
266 [CH_C_SCRATCH_1] = ®_ch_c_scratch_1,
267 [CH_C_SCRATCH_2] = ®_ch_c_scratch_2,
268 [CH_C_SCRATCH_3] = ®_ch_c_scratch_3,
269 [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0,
270 [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1,
271 [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2,
272 [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3,
273 [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4,
274 [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8,
275 [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9,
276 [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10,
277 [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11,
278 [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12,
279 [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13,
280 [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0,
281 [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1,
282 [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0,
283 [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0,
284 [GSI_STATUS] = ®_gsi_status,
285 [CH_CMD] = ®_ch_cmd,
286 [EV_CH_CMD] = ®_ev_ch_cmd,
287 [GENERIC_CMD] = ®_generic_cmd,
288 [HW_PARAM_2] = ®_hw_param_2,
289 [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq,
290 [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk,
291 [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq,
292 [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq,
293 [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk,
294 [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk,
295 [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr,
296 [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr,
297 [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq,
298 [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk,
299 [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr,
300 [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts,
301 [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en,
302 [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr,
303 [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts,
304 [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en,
305 [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr,
306 [CNTXT_INTSET] = ®_cntxt_intset,
307 [ERROR_LOG] = ®_error_log,
308 [ERROR_LOG_CLR] = ®_error_log_clr,
309 [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0,
310};
311
312const struct regs gsi_regs_v4_11 = {
313 .reg_count = ARRAY_SIZE(reg_array),
314 .reg = reg_array,
315};