1# SPDX-License-Identifier: MIT
 
 
 2menu "Display Engine Configuration"
 3	depends on DRM && DRM_AMDGPU
 4
 5config DRM_AMD_DC
 6	bool "AMD DC - Enable new display engine"
 7	default y
 8	depends on BROKEN || !CC_IS_CLANG || ARM64 || RISCV || SPARC64 || X86_64
 9	select SND_HDA_COMPONENT if SND_HDA_CORE
10	# !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752
11	select DRM_AMD_DC_FP if (X86 || LOONGARCH || (PPC64 && ALTIVEC) || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG))
12	help
13	  Choose this option if you want to use the new display engine
14	  support for AMDGPU. This adds required support for Vega and
15	  Raven ASICs.
16
17	  calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 || ARM64)
18	  architectures built with Clang (all released versions), whereby the stack
19	  frame gets blown up to well over 5k.  This would cause an immediate kernel
20	  panic on most architectures.  We'll revert this when the following bug report
21	  has been resolved: https://github.com/llvm/llvm-project/issues/41896.
 
22
23config DRM_AMD_DC_FP
24	def_bool n
25	help
26	  Floating point support, required for DCN-based SoCs
27
28config DRM_AMD_DC_SI
29	bool "AMD DC support for Southern Islands ASICs"
30	depends on DRM_AMDGPU_SI
31	depends on DRM_AMD_DC
32	help
33	  Choose this option to enable new AMD DC support for SI asics
34	  by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.
35	  Hainan is not supported by AMD DC and it has no physical DCE6.
36
37config DEBUG_KERNEL_DC
38	bool "Enable kgdb break in DC"
39	depends on DRM_AMD_DC
40	depends on KGDB
41	help
42	  Choose this option if you want to hit kdgb_break in assert.
43
44config DRM_AMD_SECURE_DISPLAY
45	bool "Enable secure display support"
46	depends on DEBUG_FS
47	depends on DRM_AMD_DC_FP
48	help
49	  Choose this option if you want to support secure display
50
51	  This option enables the calculation of crc of specific region via
52	  debugfs. Cooperate with specific DMCU FW.
53
54endmenu

 1# SPDX-License-Identifier: MIT
 2# Copyright © 2019-2024 Advanced Micro Devices, Inc. All rights reserved.
 3
 4menu "Display Engine Configuration"
 5	depends on DRM && DRM_AMDGPU
 6
 7config DRM_AMD_DC
 8	bool "AMD DC - Enable new display engine"
 9	default y
10	depends on BROKEN || !CC_IS_CLANG || ARM64 || LOONGARCH || RISCV || SPARC64 || X86_64
11	select SND_HDA_COMPONENT if SND_HDA_CORE
12	# !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752
13	select DRM_AMD_DC_FP if ARCH_HAS_KERNEL_FPU_SUPPORT && !(CC_IS_CLANG && (ARM64 || LOONGARCH || RISCV))
14	help
15	  Choose this option if you want to use the new display engine
16	  support for AMDGPU. This adds required support for Vega and
17	  Raven ASICs.
18
19	  calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 ||
20	  ARM64 || LOONGARCH || RISCV) architectures built with Clang (all released
21	  versions), whereby the stack frame gets blown up to well over 5k.  This
22	  would cause an immediate kernel panic on most architectures.  We'll revert
23	  this when the following bug report has been resolved:
24	  https://github.com/llvm/llvm-project/issues/41896.
25
26config DRM_AMD_DC_FP
27	def_bool n
28	help
29	  Floating point support, required for DCN-based SoCs
30
31config DRM_AMD_DC_SI
32	bool "AMD DC support for Southern Islands ASICs"
33	depends on DRM_AMDGPU_SI
34	depends on DRM_AMD_DC
35	help
36	  Choose this option to enable new AMD DC support for SI asics
37	  by default. This includes Tahiti, Pitcairn, Cape Verde, Oland.
38	  Hainan is not supported by AMD DC and it has no physical DCE6.
39
40config DEBUG_KERNEL_DC
41	bool "Enable kgdb break in DC"
42	depends on DRM_AMD_DC
43	depends on KGDB
44	help
45	  Choose this option if you want to hit kdgb_break in assert.
46
47config DRM_AMD_SECURE_DISPLAY
48	bool "Enable secure display support"
49	depends on DEBUG_FS
50	depends on DRM_AMD_DC_FP
51	help
52	  Choose this option if you want to support secure display
53
54	  This option enables the calculation of crc of specific region via
55	  debugfs. Cooperate with specific DMCU FW.
56
57endmenu