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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
24
25#ifndef AMDGPU_AMDKFD_H_INCLUDED
26#define AMDGPU_AMDKFD_H_INCLUDED
27
28#include <linux/list.h>
29#include <linux/types.h>
30#include <linux/mm.h>
31#include <linux/kthread.h>
32#include <linux/workqueue.h>
33#include <linux/mmu_notifier.h>
34#include <linux/memremap.h>
35#include <kgd_kfd_interface.h>
36#include <drm/drm_client.h>
37#include "amdgpu_sync.h"
38#include "amdgpu_vm.h"
39#include "amdgpu_xcp.h"
40
41extern uint64_t amdgpu_amdkfd_total_mem_size;
42
43enum TLB_FLUSH_TYPE {
44 TLB_FLUSH_LEGACY = 0,
45 TLB_FLUSH_LIGHTWEIGHT,
46 TLB_FLUSH_HEAVYWEIGHT
47};
48
49struct amdgpu_device;
50
51enum kfd_mem_attachment_type {
52 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
53 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */
54 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */
55 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */
56};
57
58struct kfd_mem_attachment {
59 struct list_head list;
60 enum kfd_mem_attachment_type type;
61 bool is_mapped;
62 struct amdgpu_bo_va *bo_va;
63 struct amdgpu_device *adev;
64 uint64_t va;
65 uint64_t pte_flags;
66};
67
68struct kgd_mem {
69 struct mutex lock;
70 struct amdgpu_bo *bo;
71 struct dma_buf *dmabuf;
72 struct hmm_range *range;
73 struct list_head attachments;
74 /* protected by amdkfd_process_info.lock */
75 struct list_head validate_list;
76 uint32_t domain;
77 unsigned int mapped_to_gpu_memory;
78 uint64_t va;
79
80 uint32_t alloc_flags;
81
82 uint32_t invalid;
83 struct amdkfd_process_info *process_info;
84
85 struct amdgpu_sync sync;
86
87 uint32_t gem_handle;
88 bool aql_queue;
89 bool is_imported;
90};
91
92/* KFD Memory Eviction */
93struct amdgpu_amdkfd_fence {
94 struct dma_fence base;
95 struct mm_struct *mm;
96 spinlock_t lock;
97 char timeline_name[TASK_COMM_LEN];
98 struct svm_range_bo *svm_bo;
99};
100
101struct amdgpu_kfd_dev {
102 struct kfd_dev *dev;
103 int64_t vram_used[MAX_XCP];
104 uint64_t vram_used_aligned[MAX_XCP];
105 bool init_complete;
106 struct work_struct reset_work;
107
108 /* HMM page migration MEMORY_DEVICE_PRIVATE mapping */
109 struct dev_pagemap pgmap;
110
111 /* Client for KFD BO GEM handle allocations */
112 struct drm_client_dev client;
113};
114
115enum kgd_engine_type {
116 KGD_ENGINE_PFP = 1,
117 KGD_ENGINE_ME,
118 KGD_ENGINE_CE,
119 KGD_ENGINE_MEC1,
120 KGD_ENGINE_MEC2,
121 KGD_ENGINE_RLC,
122 KGD_ENGINE_SDMA1,
123 KGD_ENGINE_SDMA2,
124 KGD_ENGINE_MAX
125};
126
127
128struct amdkfd_process_info {
129 /* List head of all VMs that belong to a KFD process */
130 struct list_head vm_list_head;
131 /* List head for all KFD BOs that belong to a KFD process. */
132 struct list_head kfd_bo_list;
133 /* List of userptr BOs that are valid or invalid */
134 struct list_head userptr_valid_list;
135 struct list_head userptr_inval_list;
136 /* Lock to protect kfd_bo_list */
137 struct mutex lock;
138
139 /* Number of VMs */
140 unsigned int n_vms;
141 /* Eviction Fence */
142 struct amdgpu_amdkfd_fence *eviction_fence;
143
144 /* MMU-notifier related fields */
145 struct mutex notifier_lock;
146 uint32_t evicted_bos;
147 struct delayed_work restore_userptr_work;
148 struct pid *pid;
149 bool block_mmu_notifications;
150};
151
152int amdgpu_amdkfd_init(void);
153void amdgpu_amdkfd_fini(void);
154
155void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
156int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
157void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
158 const void *ih_ring_entry);
159void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
160void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
161void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
162int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev);
163void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev);
164int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
165 enum kgd_engine_type engine,
166 uint32_t vmid, uint64_t gpu_addr,
167 uint32_t *ib_cmd, uint32_t ib_len);
168void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
169bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);
170
171bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
172
173int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
174
175int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
176
177void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev);
178
179int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
180 int queue_bit);
181
182struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
183 struct mm_struct *mm,
184 struct svm_range_bo *svm_bo);
185
186int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev);
187#if defined(CONFIG_DEBUG_FS)
188int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data);
189#endif
190#if IS_ENABLED(CONFIG_HSA_AMD)
191bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
192struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
193int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
194int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
195 unsigned long cur_seq, struct kgd_mem *mem);
196#else
197static inline
198bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
199{
200 return false;
201}
202
203static inline
204struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
205{
206 return NULL;
207}
208
209static inline
210int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
211{
212 return 0;
213}
214
215static inline
216int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
217 unsigned long cur_seq, struct kgd_mem *mem)
218{
219 return 0;
220}
221#endif
222/* Shared API */
223int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
224 void **mem_obj, uint64_t *gpu_addr,
225 void **cpu_ptr, bool mqd_gfx9);
226void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj);
227int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
228 void **mem_obj);
229void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj);
230int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
231int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
232uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
233 enum kgd_engine_type type);
234void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
235 struct kfd_local_mem_info *mem_info,
236 struct amdgpu_xcp *xcp);
237uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);
238
239uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);
240int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
241 struct amdgpu_device **dmabuf_adev,
242 uint64_t *bo_size, void *metadata_buffer,
243 size_t buffer_size, uint32_t *metadata_size,
244 uint32_t *flags, int8_t *xcp_id);
245uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
246 struct amdgpu_device *src);
247int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
248 struct amdgpu_device *src,
249 bool is_min);
250int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);
251int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
252 uint32_t *payload);
253int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
254 u32 inst);
255
256/* Read user wptr from a specified user address space with page fault
257 * disabled. The memory must be pinned and mapped to the hardware when
258 * this is called in hqd_load functions, so it should never fault in
259 * the first place. This resolves a circular lock dependency involving
260 * four locks, including the DQM lock and mmap_lock.
261 */
262#define read_user_wptr(mmptr, wptr, dst) \
263 ({ \
264 bool valid = false; \
265 if ((mmptr) && (wptr)) { \
266 pagefault_disable(); \
267 if ((mmptr) == current->mm) { \
268 valid = !get_user((dst), (wptr)); \
269 } else if (current->flags & PF_KTHREAD) { \
270 kthread_use_mm(mmptr); \
271 valid = !get_user((dst), (wptr)); \
272 kthread_unuse_mm(mmptr); \
273 } \
274 pagefault_enable(); \
275 } \
276 valid; \
277 })
278
279/* GPUVM API */
280#define drm_priv_to_vm(drm_priv) \
281 (&((struct amdgpu_fpriv *) \
282 ((struct drm_file *)(drm_priv))->driver_priv)->vm)
283
284int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
285 struct amdgpu_vm *avm, u32 pasid);
286int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
287 struct amdgpu_vm *avm,
288 void **process_info,
289 struct dma_fence **ef);
290void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
291 void *drm_priv);
292uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
293size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
294 uint8_t xcp_id);
295int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
296 struct amdgpu_device *adev, uint64_t va, uint64_t size,
297 void *drm_priv, struct kgd_mem **mem,
298 uint64_t *offset, uint32_t flags, bool criu_resume);
299int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
300 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
301 uint64_t *size);
302int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev,
303 struct kgd_mem *mem, void *drm_priv);
304int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
305 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv);
306int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv);
307int amdgpu_amdkfd_gpuvm_sync_memory(
308 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
309int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
310 void **kptr, uint64_t *size);
311void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
312
313int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo);
314
315int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
316 struct dma_fence __rcu **ef);
317int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
318 struct kfd_vm_fault_info *info);
319int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
320 uint64_t va, void *drm_priv,
321 struct kgd_mem **mem, uint64_t *size,
322 uint64_t *mmap_offset);
323int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
324 struct dma_buf **dmabuf);
325void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev);
326int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
327 struct tile_config *config);
328void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
329 bool reset);
330bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem);
331void amdgpu_amdkfd_block_mmu_notifications(void *p);
332int amdgpu_amdkfd_criu_resume(void *p);
333bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);
334int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
335 uint64_t size, u32 alloc_flag, int8_t xcp_id);
336void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
337 uint64_t size, u32 alloc_flag, int8_t xcp_id);
338
339u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id);
340
341#define KFD_XCP_MEM_ID(adev, xcp_id) \
342 ((adev)->xcp_mgr && (xcp_id) >= 0 ?\
343 (adev)->xcp_mgr->xcp[(xcp_id)].mem_id : -1)
344
345#define KFD_XCP_MEMORY_SIZE(adev, xcp_id) amdgpu_amdkfd_xcp_memory_size((adev), (xcp_id))
346
347
348#if IS_ENABLED(CONFIG_HSA_AMD)
349void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
350void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
351 struct amdgpu_vm *vm);
352
353/**
354 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released
355 *
356 * Allows KFD to release its resources associated with the GEM object.
357 */
358void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
359void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
360#else
361static inline
362void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
363{
364}
365
366static inline
367void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
368 struct amdgpu_vm *vm)
369{
370}
371
372static inline
373void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
374{
375}
376#endif
377
378#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
379int kgd2kfd_init_zone_device(struct amdgpu_device *adev);
380#else
381static inline
382int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
383{
384 return 0;
385}
386#endif
387
388/* KGD2KFD callbacks */
389int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
390int kgd2kfd_resume_mm(struct mm_struct *mm);
391int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
392 struct dma_fence *fence);
393#if IS_ENABLED(CONFIG_HSA_AMD)
394int kgd2kfd_init(void);
395void kgd2kfd_exit(void);
396struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);
397bool kgd2kfd_device_init(struct kfd_dev *kfd,
398 const struct kgd2kfd_shared_resources *gpu_resources);
399void kgd2kfd_device_exit(struct kfd_dev *kfd);
400void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
401int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
402int kgd2kfd_pre_reset(struct kfd_dev *kfd);
403int kgd2kfd_post_reset(struct kfd_dev *kfd);
404void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
405void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
406void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);
407int kgd2kfd_check_and_lock_kfd(void);
408void kgd2kfd_unlock_kfd(void);
409#else
410static inline int kgd2kfd_init(void)
411{
412 return -ENOENT;
413}
414
415static inline void kgd2kfd_exit(void)
416{
417}
418
419static inline
420struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
421{
422 return NULL;
423}
424
425static inline
426bool kgd2kfd_device_init(struct kfd_dev *kfd,
427 const struct kgd2kfd_shared_resources *gpu_resources)
428{
429 return false;
430}
431
432static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
433{
434}
435
436static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
437{
438}
439
440static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
441{
442 return 0;
443}
444
445static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
446{
447 return 0;
448}
449
450static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
451{
452 return 0;
453}
454
455static inline
456void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
457{
458}
459
460static inline
461void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
462{
463}
464
465static inline
466void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
467{
468}
469
470static inline int kgd2kfd_check_and_lock_kfd(void)
471{
472 return 0;
473}
474
475static inline void kgd2kfd_unlock_kfd(void)
476{
477}
478#endif
479#endif /* AMDGPU_AMDKFD_H_INCLUDED */
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
24
25#ifndef AMDGPU_AMDKFD_H_INCLUDED
26#define AMDGPU_AMDKFD_H_INCLUDED
27
28#include <linux/list.h>
29#include <linux/types.h>
30#include <linux/mm.h>
31#include <linux/kthread.h>
32#include <linux/workqueue.h>
33#include <linux/mmu_notifier.h>
34#include <linux/memremap.h>
35#include <kgd_kfd_interface.h>
36#include <drm/drm_client.h>
37#include "amdgpu_sync.h"
38#include "amdgpu_vm.h"
39#include "amdgpu_xcp.h"
40
41extern uint64_t amdgpu_amdkfd_total_mem_size;
42
43enum TLB_FLUSH_TYPE {
44 TLB_FLUSH_LEGACY = 0,
45 TLB_FLUSH_LIGHTWEIGHT,
46 TLB_FLUSH_HEAVYWEIGHT
47};
48
49struct amdgpu_device;
50struct amdgpu_reset_context;
51
52enum kfd_mem_attachment_type {
53 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
54 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */
55 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */
56 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */
57};
58
59struct kfd_mem_attachment {
60 struct list_head list;
61 enum kfd_mem_attachment_type type;
62 bool is_mapped;
63 struct amdgpu_bo_va *bo_va;
64 struct amdgpu_device *adev;
65 uint64_t va;
66 uint64_t pte_flags;
67};
68
69struct kgd_mem {
70 struct mutex lock;
71 struct amdgpu_bo *bo;
72 struct dma_buf *dmabuf;
73 struct hmm_range *range;
74 struct list_head attachments;
75 /* protected by amdkfd_process_info.lock */
76 struct list_head validate_list;
77 uint32_t domain;
78 unsigned int mapped_to_gpu_memory;
79 uint64_t va;
80
81 uint32_t alloc_flags;
82
83 uint32_t invalid;
84 struct amdkfd_process_info *process_info;
85
86 struct amdgpu_sync sync;
87
88 uint32_t gem_handle;
89 bool aql_queue;
90 bool is_imported;
91};
92
93/* KFD Memory Eviction */
94struct amdgpu_amdkfd_fence {
95 struct dma_fence base;
96 struct mm_struct *mm;
97 spinlock_t lock;
98 char timeline_name[TASK_COMM_LEN];
99 struct svm_range_bo *svm_bo;
100};
101
102struct amdgpu_kfd_dev {
103 struct kfd_dev *dev;
104 int64_t vram_used[MAX_XCP];
105 uint64_t vram_used_aligned[MAX_XCP];
106 bool init_complete;
107 struct work_struct reset_work;
108
109 /* HMM page migration MEMORY_DEVICE_PRIVATE mapping */
110 struct dev_pagemap pgmap;
111
112 /* Client for KFD BO GEM handle allocations */
113 struct drm_client_dev client;
114};
115
116enum kgd_engine_type {
117 KGD_ENGINE_PFP = 1,
118 KGD_ENGINE_ME,
119 KGD_ENGINE_CE,
120 KGD_ENGINE_MEC1,
121 KGD_ENGINE_MEC2,
122 KGD_ENGINE_RLC,
123 KGD_ENGINE_SDMA1,
124 KGD_ENGINE_SDMA2,
125 KGD_ENGINE_MAX
126};
127
128
129struct amdkfd_process_info {
130 /* List head of all VMs that belong to a KFD process */
131 struct list_head vm_list_head;
132 /* List head for all KFD BOs that belong to a KFD process. */
133 struct list_head kfd_bo_list;
134 /* List of userptr BOs that are valid or invalid */
135 struct list_head userptr_valid_list;
136 struct list_head userptr_inval_list;
137 /* Lock to protect kfd_bo_list */
138 struct mutex lock;
139
140 /* Number of VMs */
141 unsigned int n_vms;
142 /* Eviction Fence */
143 struct amdgpu_amdkfd_fence *eviction_fence;
144
145 /* MMU-notifier related fields */
146 struct mutex notifier_lock;
147 uint32_t evicted_bos;
148 struct delayed_work restore_userptr_work;
149 struct pid *pid;
150 bool block_mmu_notifications;
151};
152
153int amdgpu_amdkfd_init(void);
154void amdgpu_amdkfd_fini(void);
155
156void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
157int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
158void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
159 const void *ih_ring_entry);
160void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
161void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
162void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
163int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev);
164void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev);
165int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
166 enum kgd_engine_type engine,
167 uint32_t vmid, uint64_t gpu_addr,
168 uint32_t *ib_cmd, uint32_t ib_len);
169void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
170bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);
171
172bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
173
174int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev,
175 struct amdgpu_reset_context *reset_context);
176
177int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
178
179void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev);
180
181int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
182 int queue_bit);
183
184struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
185 struct mm_struct *mm,
186 struct svm_range_bo *svm_bo);
187
188int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev);
189#if defined(CONFIG_DEBUG_FS)
190int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data);
191#endif
192#if IS_ENABLED(CONFIG_HSA_AMD)
193bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
194struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
195int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
196int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
197 unsigned long cur_seq, struct kgd_mem *mem);
198int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
199 uint32_t domain,
200 struct dma_fence *fence);
201#else
202static inline
203bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
204{
205 return false;
206}
207
208static inline
209struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
210{
211 return NULL;
212}
213
214static inline
215int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
216{
217 return 0;
218}
219
220static inline
221int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
222 unsigned long cur_seq, struct kgd_mem *mem)
223{
224 return 0;
225}
226static inline
227int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo,
228 uint32_t domain,
229 struct dma_fence *fence)
230{
231 return 0;
232}
233#endif
234/* Shared API */
235int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
236 void **mem_obj, uint64_t *gpu_addr,
237 void **cpu_ptr, bool mqd_gfx9);
238void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj);
239int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
240 void **mem_obj);
241void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj);
242int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
243int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
244uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
245 enum kgd_engine_type type);
246void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
247 struct kfd_local_mem_info *mem_info,
248 struct amdgpu_xcp *xcp);
249uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);
250
251uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);
252int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
253 struct amdgpu_device **dmabuf_adev,
254 uint64_t *bo_size, void *metadata_buffer,
255 size_t buffer_size, uint32_t *metadata_size,
256 uint32_t *flags, int8_t *xcp_id);
257uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
258 struct amdgpu_device *src);
259int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
260 struct amdgpu_device *src,
261 bool is_min);
262int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);
263int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
264 uint32_t *payload);
265int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
266 u32 inst);
267int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id);
268int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id);
269int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id,
270 bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable);
271bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id);
272
273
274/* Read user wptr from a specified user address space with page fault
275 * disabled. The memory must be pinned and mapped to the hardware when
276 * this is called in hqd_load functions, so it should never fault in
277 * the first place. This resolves a circular lock dependency involving
278 * four locks, including the DQM lock and mmap_lock.
279 */
280#define read_user_wptr(mmptr, wptr, dst) \
281 ({ \
282 bool valid = false; \
283 if ((mmptr) && (wptr)) { \
284 pagefault_disable(); \
285 if ((mmptr) == current->mm) { \
286 valid = !get_user((dst), (wptr)); \
287 } else if (current->flags & PF_KTHREAD) { \
288 kthread_use_mm(mmptr); \
289 valid = !get_user((dst), (wptr)); \
290 kthread_unuse_mm(mmptr); \
291 } \
292 pagefault_enable(); \
293 } \
294 valid; \
295 })
296
297/* GPUVM API */
298#define drm_priv_to_vm(drm_priv) \
299 (&((struct amdgpu_fpriv *) \
300 ((struct drm_file *)(drm_priv))->driver_priv)->vm)
301
302int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
303 struct amdgpu_vm *avm, u32 pasid);
304int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
305 struct amdgpu_vm *avm,
306 void **process_info,
307 struct dma_fence **ef);
308void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
309 void *drm_priv);
310uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
311size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
312 uint8_t xcp_id);
313int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
314 struct amdgpu_device *adev, uint64_t va, uint64_t size,
315 void *drm_priv, struct kgd_mem **mem,
316 uint64_t *offset, uint32_t flags, bool criu_resume);
317int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
318 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
319 uint64_t *size);
320int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev,
321 struct kgd_mem *mem, void *drm_priv);
322int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
323 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv);
324int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv);
325int amdgpu_amdkfd_gpuvm_sync_memory(
326 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
327int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
328 void **kptr, uint64_t *size);
329void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
330
331int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart);
332
333int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
334 struct dma_fence __rcu **ef);
335int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
336 struct kfd_vm_fault_info *info);
337int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
338 uint64_t va, void *drm_priv,
339 struct kgd_mem **mem, uint64_t *size,
340 uint64_t *mmap_offset);
341int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
342 struct dma_buf **dmabuf);
343void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev);
344int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
345 struct tile_config *config);
346void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
347 enum amdgpu_ras_block block, uint32_t reset);
348
349void amdgpu_amdkfd_ras_pasid_poison_consumption_handler(struct amdgpu_device *adev,
350 enum amdgpu_ras_block block, uint16_t pasid,
351 pasid_notify pasid_fn, void *data, uint32_t reset);
352
353bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev);
354bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem);
355void amdgpu_amdkfd_block_mmu_notifications(void *p);
356int amdgpu_amdkfd_criu_resume(void *p);
357int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
358 uint64_t size, u32 alloc_flag, int8_t xcp_id);
359void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
360 uint64_t size, u32 alloc_flag, int8_t xcp_id);
361
362u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id);
363
364#define KFD_XCP_MEM_ID(adev, xcp_id) \
365 ((adev)->xcp_mgr && (xcp_id) >= 0 ?\
366 (adev)->xcp_mgr->xcp[(xcp_id)].mem_id : -1)
367
368#define KFD_XCP_MEMORY_SIZE(adev, xcp_id) amdgpu_amdkfd_xcp_memory_size((adev), (xcp_id))
369
370
371#if IS_ENABLED(CONFIG_HSA_AMD)
372void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
373void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
374 struct amdgpu_vm *vm);
375
376/**
377 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released
378 *
379 * Allows KFD to release its resources associated with the GEM object.
380 */
381void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
382void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
383#else
384static inline
385void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
386{
387}
388
389static inline
390void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
391 struct amdgpu_vm *vm)
392{
393}
394
395static inline
396void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
397{
398}
399#endif
400
401#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
402int kgd2kfd_init_zone_device(struct amdgpu_device *adev);
403#else
404static inline
405int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
406{
407 return 0;
408}
409#endif
410
411/* KGD2KFD callbacks */
412int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
413int kgd2kfd_resume_mm(struct mm_struct *mm);
414int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
415 struct dma_fence *fence);
416#if IS_ENABLED(CONFIG_HSA_AMD)
417int kgd2kfd_init(void);
418void kgd2kfd_exit(void);
419struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);
420bool kgd2kfd_device_init(struct kfd_dev *kfd,
421 const struct kgd2kfd_shared_resources *gpu_resources);
422void kgd2kfd_device_exit(struct kfd_dev *kfd);
423void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
424int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
425int kgd2kfd_pre_reset(struct kfd_dev *kfd,
426 struct amdgpu_reset_context *reset_context);
427int kgd2kfd_post_reset(struct kfd_dev *kfd);
428void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
429void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
430void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);
431int kgd2kfd_check_and_lock_kfd(void);
432void kgd2kfd_unlock_kfd(void);
433int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id);
434int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id);
435bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id);
436#else
437static inline int kgd2kfd_init(void)
438{
439 return -ENOENT;
440}
441
442static inline void kgd2kfd_exit(void)
443{
444}
445
446static inline
447struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
448{
449 return NULL;
450}
451
452static inline
453bool kgd2kfd_device_init(struct kfd_dev *kfd,
454 const struct kgd2kfd_shared_resources *gpu_resources)
455{
456 return false;
457}
458
459static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
460{
461}
462
463static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
464{
465}
466
467static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
468{
469 return 0;
470}
471
472static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd,
473 struct amdgpu_reset_context *reset_context)
474{
475 return 0;
476}
477
478static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
479{
480 return 0;
481}
482
483static inline
484void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
485{
486}
487
488static inline
489void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
490{
491}
492
493static inline
494void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
495{
496}
497
498static inline int kgd2kfd_check_and_lock_kfd(void)
499{
500 return 0;
501}
502
503static inline void kgd2kfd_unlock_kfd(void)
504{
505}
506
507static inline int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id)
508{
509 return 0;
510}
511
512static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id)
513{
514 return 0;
515}
516
517static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id)
518{
519 return false;
520}
521#endif
522#endif /* AMDGPU_AMDKFD_H_INCLUDED */