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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#undef DEBUG
19
20#include <linux/clk.h>
21#include <linux/console.h>
22#include <linux/ctype.h>
23#include <linux/cpufreq.h>
24#include <linux/delay.h>
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
27#include <linux/err.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/ioport.h>
32#include <linux/ktime.h>
33#include <linux/major.h>
34#include <linux/minmax.h>
35#include <linux/module.h>
36#include <linux/mm.h>
37#include <linux/of.h>
38#include <linux/platform_device.h>
39#include <linux/pm_runtime.h>
40#include <linux/reset.h>
41#include <linux/scatterlist.h>
42#include <linux/serial.h>
43#include <linux/serial_sci.h>
44#include <linux/sh_dma.h>
45#include <linux/slab.h>
46#include <linux/string.h>
47#include <linux/sysrq.h>
48#include <linux/timer.h>
49#include <linux/tty.h>
50#include <linux/tty_flip.h>
51
52#ifdef CONFIG_SUPERH
53#include <asm/sh_bios.h>
54#include <asm/platform_early.h>
55#endif
56
57#include "serial_mctrl_gpio.h"
58#include "sh-sci.h"
59
60/* Offsets into the sci_port->irqs array */
61enum {
62 SCIx_ERI_IRQ,
63 SCIx_RXI_IRQ,
64 SCIx_TXI_IRQ,
65 SCIx_BRI_IRQ,
66 SCIx_DRI_IRQ,
67 SCIx_TEI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85};
86
87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103struct plat_sci_reg {
104 u8 offset, size;
105};
106
107struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
115};
116
117struct sci_port {
118 struct uart_port port;
119
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
126
127 /* Clocks */
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
130
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
133
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136
137#ifdef CONFIG_SERIAL_SH_SCI_DMA
138 struct dma_chan *chan_tx_saved;
139 struct dma_chan *chan_rx_saved;
140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
145 struct scatterlist sg_rx[2];
146 void *rx_buf[2];
147 size_t buf_len_rx;
148 struct work_struct work_tx;
149 struct hrtimer rx_timer;
150 unsigned int rx_timeout; /* microseconds */
151#endif
152 unsigned int rx_frame;
153 int rx_trigger;
154 struct timer_list rx_fifo_timer;
155 int rx_fifo_timeout;
156 u16 hscif_tot;
157
158 bool has_rtscts;
159 bool autorts;
160};
161
162#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
163
164static struct sci_port sci_ports[SCI_NPORTS];
165static unsigned long sci_ports_in_use;
166static struct uart_driver sci_uart_driver;
167
168static inline struct sci_port *
169to_sci_port(struct uart_port *uart)
170{
171 return container_of(uart, struct sci_port, port);
172}
173
174static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
175 /*
176 * Common SCI definitions, dependent on the port's regshift
177 * value.
178 */
179 [SCIx_SCI_REGTYPE] = {
180 .regs = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
187 },
188 .fifosize = 1,
189 .overrun_reg = SCxSR,
190 .overrun_mask = SCI_ORER,
191 .sampling_rate_mask = SCI_SR(32),
192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
194 },
195
196 /*
197 * Common definitions for legacy IrDA ports.
198 */
199 [SCIx_IRDA_REGTYPE] = {
200 .regs = {
201 [SCSMR] = { 0x00, 8 },
202 [SCBRR] = { 0x02, 8 },
203 [SCSCR] = { 0x04, 8 },
204 [SCxTDR] = { 0x06, 8 },
205 [SCxSR] = { 0x08, 16 },
206 [SCxRDR] = { 0x0a, 8 },
207 [SCFCR] = { 0x0c, 8 },
208 [SCFDR] = { 0x0e, 16 },
209 },
210 .fifosize = 1,
211 .overrun_reg = SCxSR,
212 .overrun_mask = SCI_ORER,
213 .sampling_rate_mask = SCI_SR(32),
214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
216 },
217
218 /*
219 * Common SCIFA definitions.
220 */
221 [SCIx_SCIFA_REGTYPE] = {
222 .regs = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x20, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x24, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = { 0x1c, 16 },
231 [SCPCR] = { 0x30, 16 },
232 [SCPDR] = { 0x34, 16 },
233 },
234 .fifosize = 64,
235 .overrun_reg = SCxSR,
236 .overrun_mask = SCIFA_ORER,
237 .sampling_rate_mask = SCI_SR_SCIFAB,
238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
240 },
241
242 /*
243 * Common SCIFB definitions.
244 */
245 [SCIx_SCIFB_REGTYPE] = {
246 .regs = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x40, 8 },
251 [SCxSR] = { 0x14, 16 },
252 [SCxRDR] = { 0x60, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCTFDR] = { 0x38, 16 },
255 [SCRFDR] = { 0x3c, 16 },
256 [SCPCR] = { 0x30, 16 },
257 [SCPDR] = { 0x34, 16 },
258 },
259 .fifosize = 256,
260 .overrun_reg = SCxSR,
261 .overrun_mask = SCIFA_ORER,
262 .sampling_rate_mask = SCI_SR_SCIFAB,
263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
265 },
266
267 /*
268 * Common SH-2(A) SCIF definitions for ports with FIFO data
269 * count registers.
270 */
271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
272 .regs = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCSPTR] = { 0x20, 16 },
282 [SCLSR] = { 0x24, 16 },
283 },
284 .fifosize = 16,
285 .overrun_reg = SCLSR,
286 .overrun_mask = SCLSR_ORER,
287 .sampling_rate_mask = SCI_SR(32),
288 .error_mask = SCIF_DEFAULT_ERROR_MASK,
289 .error_clear = SCIF_ERROR_CLEAR,
290 },
291
292 /*
293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
294 * It looks like a normal SCIF with FIFO data, but with a
295 * compressed address space. Also, the break out of interrupts
296 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
297 */
298 [SCIx_RZ_SCIFA_REGTYPE] = {
299 .regs = {
300 [SCSMR] = { 0x00, 16 },
301 [SCBRR] = { 0x02, 8 },
302 [SCSCR] = { 0x04, 16 },
303 [SCxTDR] = { 0x06, 8 },
304 [SCxSR] = { 0x08, 16 },
305 [SCxRDR] = { 0x0A, 8 },
306 [SCFCR] = { 0x0C, 16 },
307 [SCFDR] = { 0x0E, 16 },
308 [SCSPTR] = { 0x10, 16 },
309 [SCLSR] = { 0x12, 16 },
310 [SEMR] = { 0x14, 8 },
311 },
312 .fifosize = 16,
313 .overrun_reg = SCLSR,
314 .overrun_mask = SCLSR_ORER,
315 .sampling_rate_mask = SCI_SR(32),
316 .error_mask = SCIF_DEFAULT_ERROR_MASK,
317 .error_clear = SCIF_ERROR_CLEAR,
318 },
319
320 /*
321 * Common SH-3 SCIF definitions.
322 */
323 [SCIx_SH3_SCIF_REGTYPE] = {
324 .regs = {
325 [SCSMR] = { 0x00, 8 },
326 [SCBRR] = { 0x02, 8 },
327 [SCSCR] = { 0x04, 8 },
328 [SCxTDR] = { 0x06, 8 },
329 [SCxSR] = { 0x08, 16 },
330 [SCxRDR] = { 0x0a, 8 },
331 [SCFCR] = { 0x0c, 8 },
332 [SCFDR] = { 0x0e, 16 },
333 },
334 .fifosize = 16,
335 .overrun_reg = SCLSR,
336 .overrun_mask = SCLSR_ORER,
337 .sampling_rate_mask = SCI_SR(32),
338 .error_mask = SCIF_DEFAULT_ERROR_MASK,
339 .error_clear = SCIF_ERROR_CLEAR,
340 },
341
342 /*
343 * Common SH-4(A) SCIF(B) definitions.
344 */
345 [SCIx_SH4_SCIF_REGTYPE] = {
346 .regs = {
347 [SCSMR] = { 0x00, 16 },
348 [SCBRR] = { 0x04, 8 },
349 [SCSCR] = { 0x08, 16 },
350 [SCxTDR] = { 0x0c, 8 },
351 [SCxSR] = { 0x10, 16 },
352 [SCxRDR] = { 0x14, 8 },
353 [SCFCR] = { 0x18, 16 },
354 [SCFDR] = { 0x1c, 16 },
355 [SCSPTR] = { 0x20, 16 },
356 [SCLSR] = { 0x24, 16 },
357 },
358 .fifosize = 16,
359 .overrun_reg = SCLSR,
360 .overrun_mask = SCLSR_ORER,
361 .sampling_rate_mask = SCI_SR(32),
362 .error_mask = SCIF_DEFAULT_ERROR_MASK,
363 .error_clear = SCIF_ERROR_CLEAR,
364 },
365
366 /*
367 * Common SCIF definitions for ports with a Baud Rate Generator for
368 * External Clock (BRG).
369 */
370 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
371 .regs = {
372 [SCSMR] = { 0x00, 16 },
373 [SCBRR] = { 0x04, 8 },
374 [SCSCR] = { 0x08, 16 },
375 [SCxTDR] = { 0x0c, 8 },
376 [SCxSR] = { 0x10, 16 },
377 [SCxRDR] = { 0x14, 8 },
378 [SCFCR] = { 0x18, 16 },
379 [SCFDR] = { 0x1c, 16 },
380 [SCSPTR] = { 0x20, 16 },
381 [SCLSR] = { 0x24, 16 },
382 [SCDL] = { 0x30, 16 },
383 [SCCKS] = { 0x34, 16 },
384 },
385 .fifosize = 16,
386 .overrun_reg = SCLSR,
387 .overrun_mask = SCLSR_ORER,
388 .sampling_rate_mask = SCI_SR(32),
389 .error_mask = SCIF_DEFAULT_ERROR_MASK,
390 .error_clear = SCIF_ERROR_CLEAR,
391 },
392
393 /*
394 * Common HSCIF definitions.
395 */
396 [SCIx_HSCIF_REGTYPE] = {
397 .regs = {
398 [SCSMR] = { 0x00, 16 },
399 [SCBRR] = { 0x04, 8 },
400 [SCSCR] = { 0x08, 16 },
401 [SCxTDR] = { 0x0c, 8 },
402 [SCxSR] = { 0x10, 16 },
403 [SCxRDR] = { 0x14, 8 },
404 [SCFCR] = { 0x18, 16 },
405 [SCFDR] = { 0x1c, 16 },
406 [SCSPTR] = { 0x20, 16 },
407 [SCLSR] = { 0x24, 16 },
408 [HSSRR] = { 0x40, 16 },
409 [SCDL] = { 0x30, 16 },
410 [SCCKS] = { 0x34, 16 },
411 [HSRTRGR] = { 0x54, 16 },
412 [HSTTRGR] = { 0x58, 16 },
413 },
414 .fifosize = 128,
415 .overrun_reg = SCLSR,
416 .overrun_mask = SCLSR_ORER,
417 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
418 .error_mask = SCIF_DEFAULT_ERROR_MASK,
419 .error_clear = SCIF_ERROR_CLEAR,
420 },
421
422 /*
423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
424 * register.
425 */
426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
427 .regs = {
428 [SCSMR] = { 0x00, 16 },
429 [SCBRR] = { 0x04, 8 },
430 [SCSCR] = { 0x08, 16 },
431 [SCxTDR] = { 0x0c, 8 },
432 [SCxSR] = { 0x10, 16 },
433 [SCxRDR] = { 0x14, 8 },
434 [SCFCR] = { 0x18, 16 },
435 [SCFDR] = { 0x1c, 16 },
436 [SCLSR] = { 0x24, 16 },
437 },
438 .fifosize = 16,
439 .overrun_reg = SCLSR,
440 .overrun_mask = SCLSR_ORER,
441 .sampling_rate_mask = SCI_SR(32),
442 .error_mask = SCIF_DEFAULT_ERROR_MASK,
443 .error_clear = SCIF_ERROR_CLEAR,
444 },
445
446 /*
447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
448 * count registers.
449 */
450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
451 .regs = {
452 [SCSMR] = { 0x00, 16 },
453 [SCBRR] = { 0x04, 8 },
454 [SCSCR] = { 0x08, 16 },
455 [SCxTDR] = { 0x0c, 8 },
456 [SCxSR] = { 0x10, 16 },
457 [SCxRDR] = { 0x14, 8 },
458 [SCFCR] = { 0x18, 16 },
459 [SCFDR] = { 0x1c, 16 },
460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
461 [SCRFDR] = { 0x20, 16 },
462 [SCSPTR] = { 0x24, 16 },
463 [SCLSR] = { 0x28, 16 },
464 },
465 .fifosize = 16,
466 .overrun_reg = SCLSR,
467 .overrun_mask = SCLSR_ORER,
468 .sampling_rate_mask = SCI_SR(32),
469 .error_mask = SCIF_DEFAULT_ERROR_MASK,
470 .error_clear = SCIF_ERROR_CLEAR,
471 },
472
473 /*
474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
475 * registers.
476 */
477 [SCIx_SH7705_SCIF_REGTYPE] = {
478 .regs = {
479 [SCSMR] = { 0x00, 16 },
480 [SCBRR] = { 0x04, 8 },
481 [SCSCR] = { 0x08, 16 },
482 [SCxTDR] = { 0x20, 8 },
483 [SCxSR] = { 0x14, 16 },
484 [SCxRDR] = { 0x24, 8 },
485 [SCFCR] = { 0x18, 16 },
486 [SCFDR] = { 0x1c, 16 },
487 },
488 .fifosize = 64,
489 .overrun_reg = SCxSR,
490 .overrun_mask = SCIFA_ORER,
491 .sampling_rate_mask = SCI_SR(16),
492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
494 },
495};
496
497#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
498
499/*
500 * The "offset" here is rather misleading, in that it refers to an enum
501 * value relative to the port mapping rather than the fixed offset
502 * itself, which needs to be manually retrieved from the platform's
503 * register map for the given port.
504 */
505static unsigned int sci_serial_in(struct uart_port *p, int offset)
506{
507 const struct plat_sci_reg *reg = sci_getreg(p, offset);
508
509 if (reg->size == 8)
510 return ioread8(p->membase + (reg->offset << p->regshift));
511 else if (reg->size == 16)
512 return ioread16(p->membase + (reg->offset << p->regshift));
513 else
514 WARN(1, "Invalid register access\n");
515
516 return 0;
517}
518
519static void sci_serial_out(struct uart_port *p, int offset, int value)
520{
521 const struct plat_sci_reg *reg = sci_getreg(p, offset);
522
523 if (reg->size == 8)
524 iowrite8(value, p->membase + (reg->offset << p->regshift));
525 else if (reg->size == 16)
526 iowrite16(value, p->membase + (reg->offset << p->regshift));
527 else
528 WARN(1, "Invalid register access\n");
529}
530
531static void sci_port_enable(struct sci_port *sci_port)
532{
533 unsigned int i;
534
535 if (!sci_port->port.dev)
536 return;
537
538 pm_runtime_get_sync(sci_port->port.dev);
539
540 for (i = 0; i < SCI_NUM_CLKS; i++) {
541 clk_prepare_enable(sci_port->clks[i]);
542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
543 }
544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
545}
546
547static void sci_port_disable(struct sci_port *sci_port)
548{
549 unsigned int i;
550
551 if (!sci_port->port.dev)
552 return;
553
554 for (i = SCI_NUM_CLKS; i-- > 0; )
555 clk_disable_unprepare(sci_port->clks[i]);
556
557 pm_runtime_put_sync(sci_port->port.dev);
558}
559
560static inline unsigned long port_rx_irq_mask(struct uart_port *port)
561{
562 /*
563 * Not all ports (such as SCIFA) will support REIE. Rather than
564 * special-casing the port type, we check the port initialization
565 * IRQ enable mask to see whether the IRQ is desired at all. If
566 * it's unset, it's logically inferred that there's no point in
567 * testing for it.
568 */
569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
570}
571
572static void sci_start_tx(struct uart_port *port)
573{
574 struct sci_port *s = to_sci_port(port);
575 unsigned short ctrl;
576
577#ifdef CONFIG_SERIAL_SH_SCI_DMA
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
579 u16 new, scr = serial_port_in(port, SCSCR);
580 if (s->chan_tx)
581 new = scr | SCSCR_TDRQE;
582 else
583 new = scr & ~SCSCR_TDRQE;
584 if (new != scr)
585 serial_port_out(port, SCSCR, new);
586 }
587
588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
589 dma_submit_error(s->cookie_tx)) {
590 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
591 /* Switch irq from SCIF to DMA */
592 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
593
594 s->cookie_tx = 0;
595 schedule_work(&s->work_tx);
596 }
597#endif
598
599 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
600 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
601 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
602 ctrl = serial_port_in(port, SCSCR);
603
604 /*
605 * For SCI, TE (transmit enable) must be set after setting TIE
606 * (transmit interrupt enable) or in the same instruction to start
607 * the transmit process.
608 */
609 if (port->type == PORT_SCI)
610 ctrl |= SCSCR_TE;
611
612 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
613 }
614}
615
616static void sci_stop_tx(struct uart_port *port)
617{
618 unsigned short ctrl;
619
620 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
621 ctrl = serial_port_in(port, SCSCR);
622
623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
624 ctrl &= ~SCSCR_TDRQE;
625
626 ctrl &= ~SCSCR_TIE;
627
628 serial_port_out(port, SCSCR, ctrl);
629
630#ifdef CONFIG_SERIAL_SH_SCI_DMA
631 if (to_sci_port(port)->chan_tx &&
632 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
633 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
634 to_sci_port(port)->cookie_tx = -EINVAL;
635 }
636#endif
637}
638
639static void sci_start_rx(struct uart_port *port)
640{
641 unsigned short ctrl;
642
643 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
644
645 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
646 ctrl &= ~SCSCR_RDRQE;
647
648 serial_port_out(port, SCSCR, ctrl);
649}
650
651static void sci_stop_rx(struct uart_port *port)
652{
653 unsigned short ctrl;
654
655 ctrl = serial_port_in(port, SCSCR);
656
657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
658 ctrl &= ~SCSCR_RDRQE;
659
660 ctrl &= ~port_rx_irq_mask(port);
661
662 serial_port_out(port, SCSCR, ctrl);
663}
664
665static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
666{
667 if (port->type == PORT_SCI) {
668 /* Just store the mask */
669 serial_port_out(port, SCxSR, mask);
670 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
671 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
672 /* Only clear the status bits we want to clear */
673 serial_port_out(port, SCxSR,
674 serial_port_in(port, SCxSR) & mask);
675 } else {
676 /* Store the mask, clear parity/framing errors */
677 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
678 }
679}
680
681#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
682 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
683
684#ifdef CONFIG_CONSOLE_POLL
685static int sci_poll_get_char(struct uart_port *port)
686{
687 unsigned short status;
688 int c;
689
690 do {
691 status = serial_port_in(port, SCxSR);
692 if (status & SCxSR_ERRORS(port)) {
693 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
694 continue;
695 }
696 break;
697 } while (1);
698
699 if (!(status & SCxSR_RDxF(port)))
700 return NO_POLL_CHAR;
701
702 c = serial_port_in(port, SCxRDR);
703
704 /* Dummy read */
705 serial_port_in(port, SCxSR);
706 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
707
708 return c;
709}
710#endif
711
712static void sci_poll_put_char(struct uart_port *port, unsigned char c)
713{
714 unsigned short status;
715
716 do {
717 status = serial_port_in(port, SCxSR);
718 } while (!(status & SCxSR_TDxE(port)));
719
720 serial_port_out(port, SCxTDR, c);
721 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
722}
723#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
724 CONFIG_SERIAL_SH_SCI_EARLYCON */
725
726static void sci_init_pins(struct uart_port *port, unsigned int cflag)
727{
728 struct sci_port *s = to_sci_port(port);
729
730 /*
731 * Use port-specific handler if provided.
732 */
733 if (s->cfg->ops && s->cfg->ops->init_pins) {
734 s->cfg->ops->init_pins(port, cflag);
735 return;
736 }
737
738 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
739 u16 data = serial_port_in(port, SCPDR);
740 u16 ctrl = serial_port_in(port, SCPCR);
741
742 /* Enable RXD and TXD pin functions */
743 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
744 if (to_sci_port(port)->has_rtscts) {
745 /* RTS# is output, active low, unless autorts */
746 if (!(port->mctrl & TIOCM_RTS)) {
747 ctrl |= SCPCR_RTSC;
748 data |= SCPDR_RTSD;
749 } else if (!s->autorts) {
750 ctrl |= SCPCR_RTSC;
751 data &= ~SCPDR_RTSD;
752 } else {
753 /* Enable RTS# pin function */
754 ctrl &= ~SCPCR_RTSC;
755 }
756 /* Enable CTS# pin function */
757 ctrl &= ~SCPCR_CTSC;
758 }
759 serial_port_out(port, SCPDR, data);
760 serial_port_out(port, SCPCR, ctrl);
761 } else if (sci_getreg(port, SCSPTR)->size) {
762 u16 status = serial_port_in(port, SCSPTR);
763
764 /* RTS# is always output; and active low, unless autorts */
765 status |= SCSPTR_RTSIO;
766 if (!(port->mctrl & TIOCM_RTS))
767 status |= SCSPTR_RTSDT;
768 else if (!s->autorts)
769 status &= ~SCSPTR_RTSDT;
770 /* CTS# and SCK are inputs */
771 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
772 serial_port_out(port, SCSPTR, status);
773 }
774}
775
776static int sci_txfill(struct uart_port *port)
777{
778 struct sci_port *s = to_sci_port(port);
779 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
780 const struct plat_sci_reg *reg;
781
782 reg = sci_getreg(port, SCTFDR);
783 if (reg->size)
784 return serial_port_in(port, SCTFDR) & fifo_mask;
785
786 reg = sci_getreg(port, SCFDR);
787 if (reg->size)
788 return serial_port_in(port, SCFDR) >> 8;
789
790 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
791}
792
793static int sci_txroom(struct uart_port *port)
794{
795 return port->fifosize - sci_txfill(port);
796}
797
798static int sci_rxfill(struct uart_port *port)
799{
800 struct sci_port *s = to_sci_port(port);
801 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
802 const struct plat_sci_reg *reg;
803
804 reg = sci_getreg(port, SCRFDR);
805 if (reg->size)
806 return serial_port_in(port, SCRFDR) & fifo_mask;
807
808 reg = sci_getreg(port, SCFDR);
809 if (reg->size)
810 return serial_port_in(port, SCFDR) & fifo_mask;
811
812 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
813}
814
815/* ********************************************************************** *
816 * the interrupt related routines *
817 * ********************************************************************** */
818
819static void sci_transmit_chars(struct uart_port *port)
820{
821 struct circ_buf *xmit = &port->state->xmit;
822 unsigned int stopped = uart_tx_stopped(port);
823 unsigned short status;
824 unsigned short ctrl;
825 int count;
826
827 status = serial_port_in(port, SCxSR);
828 if (!(status & SCxSR_TDxE(port))) {
829 ctrl = serial_port_in(port, SCSCR);
830 if (uart_circ_empty(xmit))
831 ctrl &= ~SCSCR_TIE;
832 else
833 ctrl |= SCSCR_TIE;
834 serial_port_out(port, SCSCR, ctrl);
835 return;
836 }
837
838 count = sci_txroom(port);
839
840 do {
841 unsigned char c;
842
843 if (port->x_char) {
844 c = port->x_char;
845 port->x_char = 0;
846 } else if (!uart_circ_empty(xmit) && !stopped) {
847 c = xmit->buf[xmit->tail];
848 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
849 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) {
850 ctrl = serial_port_in(port, SCSCR);
851 ctrl &= ~SCSCR_TE;
852 serial_port_out(port, SCSCR, ctrl);
853 return;
854 } else {
855 break;
856 }
857
858 serial_port_out(port, SCxTDR, c);
859
860 port->icount.tx++;
861 } while (--count > 0);
862
863 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
864
865 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
866 uart_write_wakeup(port);
867 if (uart_circ_empty(xmit)) {
868 if (port->type == PORT_SCI) {
869 ctrl = serial_port_in(port, SCSCR);
870 ctrl &= ~SCSCR_TIE;
871 ctrl |= SCSCR_TEIE;
872 serial_port_out(port, SCSCR, ctrl);
873 }
874
875 sci_stop_tx(port);
876 }
877}
878
879static void sci_receive_chars(struct uart_port *port)
880{
881 struct tty_port *tport = &port->state->port;
882 int i, count, copied = 0;
883 unsigned short status;
884 unsigned char flag;
885
886 status = serial_port_in(port, SCxSR);
887 if (!(status & SCxSR_RDxF(port)))
888 return;
889
890 while (1) {
891 /* Don't copy more bytes than there is room for in the buffer */
892 count = tty_buffer_request_room(tport, sci_rxfill(port));
893
894 /* If for any reason we can't copy more data, we're done! */
895 if (count == 0)
896 break;
897
898 if (port->type == PORT_SCI) {
899 char c = serial_port_in(port, SCxRDR);
900 if (uart_handle_sysrq_char(port, c))
901 count = 0;
902 else
903 tty_insert_flip_char(tport, c, TTY_NORMAL);
904 } else {
905 for (i = 0; i < count; i++) {
906 char c;
907
908 if (port->type == PORT_SCIF ||
909 port->type == PORT_HSCIF) {
910 status = serial_port_in(port, SCxSR);
911 c = serial_port_in(port, SCxRDR);
912 } else {
913 c = serial_port_in(port, SCxRDR);
914 status = serial_port_in(port, SCxSR);
915 }
916 if (uart_handle_sysrq_char(port, c)) {
917 count--; i--;
918 continue;
919 }
920
921 /* Store data and status */
922 if (status & SCxSR_FER(port)) {
923 flag = TTY_FRAME;
924 port->icount.frame++;
925 } else if (status & SCxSR_PER(port)) {
926 flag = TTY_PARITY;
927 port->icount.parity++;
928 } else
929 flag = TTY_NORMAL;
930
931 tty_insert_flip_char(tport, c, flag);
932 }
933 }
934
935 serial_port_in(port, SCxSR); /* dummy read */
936 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
937
938 copied += count;
939 port->icount.rx += count;
940 }
941
942 if (copied) {
943 /* Tell the rest of the system the news. New characters! */
944 tty_flip_buffer_push(tport);
945 } else {
946 /* TTY buffers full; read from RX reg to prevent lockup */
947 serial_port_in(port, SCxRDR);
948 serial_port_in(port, SCxSR); /* dummy read */
949 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
950 }
951}
952
953static int sci_handle_errors(struct uart_port *port)
954{
955 int copied = 0;
956 unsigned short status = serial_port_in(port, SCxSR);
957 struct tty_port *tport = &port->state->port;
958 struct sci_port *s = to_sci_port(port);
959
960 /* Handle overruns */
961 if (status & s->params->overrun_mask) {
962 port->icount.overrun++;
963
964 /* overrun error */
965 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
966 copied++;
967 }
968
969 if (status & SCxSR_FER(port)) {
970 /* frame error */
971 port->icount.frame++;
972
973 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
974 copied++;
975 }
976
977 if (status & SCxSR_PER(port)) {
978 /* parity error */
979 port->icount.parity++;
980
981 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
982 copied++;
983 }
984
985 if (copied)
986 tty_flip_buffer_push(tport);
987
988 return copied;
989}
990
991static int sci_handle_fifo_overrun(struct uart_port *port)
992{
993 struct tty_port *tport = &port->state->port;
994 struct sci_port *s = to_sci_port(port);
995 const struct plat_sci_reg *reg;
996 int copied = 0;
997 u16 status;
998
999 reg = sci_getreg(port, s->params->overrun_reg);
1000 if (!reg->size)
1001 return 0;
1002
1003 status = serial_port_in(port, s->params->overrun_reg);
1004 if (status & s->params->overrun_mask) {
1005 status &= ~s->params->overrun_mask;
1006 serial_port_out(port, s->params->overrun_reg, status);
1007
1008 port->icount.overrun++;
1009
1010 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1011 tty_flip_buffer_push(tport);
1012 copied++;
1013 }
1014
1015 return copied;
1016}
1017
1018static int sci_handle_breaks(struct uart_port *port)
1019{
1020 int copied = 0;
1021 unsigned short status = serial_port_in(port, SCxSR);
1022 struct tty_port *tport = &port->state->port;
1023
1024 if (uart_handle_break(port))
1025 return 0;
1026
1027 if (status & SCxSR_BRK(port)) {
1028 port->icount.brk++;
1029
1030 /* Notify of BREAK */
1031 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1032 copied++;
1033 }
1034
1035 if (copied)
1036 tty_flip_buffer_push(tport);
1037
1038 copied += sci_handle_fifo_overrun(port);
1039
1040 return copied;
1041}
1042
1043static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1044{
1045 unsigned int bits;
1046
1047 if (rx_trig >= port->fifosize)
1048 rx_trig = port->fifosize - 1;
1049 if (rx_trig < 1)
1050 rx_trig = 1;
1051
1052 /* HSCIF can be set to an arbitrary level. */
1053 if (sci_getreg(port, HSRTRGR)->size) {
1054 serial_port_out(port, HSRTRGR, rx_trig);
1055 return rx_trig;
1056 }
1057
1058 switch (port->type) {
1059 case PORT_SCIF:
1060 if (rx_trig < 4) {
1061 bits = 0;
1062 rx_trig = 1;
1063 } else if (rx_trig < 8) {
1064 bits = SCFCR_RTRG0;
1065 rx_trig = 4;
1066 } else if (rx_trig < 14) {
1067 bits = SCFCR_RTRG1;
1068 rx_trig = 8;
1069 } else {
1070 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1071 rx_trig = 14;
1072 }
1073 break;
1074 case PORT_SCIFA:
1075 case PORT_SCIFB:
1076 if (rx_trig < 16) {
1077 bits = 0;
1078 rx_trig = 1;
1079 } else if (rx_trig < 32) {
1080 bits = SCFCR_RTRG0;
1081 rx_trig = 16;
1082 } else if (rx_trig < 48) {
1083 bits = SCFCR_RTRG1;
1084 rx_trig = 32;
1085 } else {
1086 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1087 rx_trig = 48;
1088 }
1089 break;
1090 default:
1091 WARN(1, "unknown FIFO configuration");
1092 return 1;
1093 }
1094
1095 serial_port_out(port, SCFCR,
1096 (serial_port_in(port, SCFCR) &
1097 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1098
1099 return rx_trig;
1100}
1101
1102static int scif_rtrg_enabled(struct uart_port *port)
1103{
1104 if (sci_getreg(port, HSRTRGR)->size)
1105 return serial_port_in(port, HSRTRGR) != 0;
1106 else
1107 return (serial_port_in(port, SCFCR) &
1108 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1109}
1110
1111static void rx_fifo_timer_fn(struct timer_list *t)
1112{
1113 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1114 struct uart_port *port = &s->port;
1115
1116 dev_dbg(port->dev, "Rx timed out\n");
1117 scif_set_rtrg(port, 1);
1118}
1119
1120static ssize_t rx_fifo_trigger_show(struct device *dev,
1121 struct device_attribute *attr, char *buf)
1122{
1123 struct uart_port *port = dev_get_drvdata(dev);
1124 struct sci_port *sci = to_sci_port(port);
1125
1126 return sprintf(buf, "%d\n", sci->rx_trigger);
1127}
1128
1129static ssize_t rx_fifo_trigger_store(struct device *dev,
1130 struct device_attribute *attr,
1131 const char *buf, size_t count)
1132{
1133 struct uart_port *port = dev_get_drvdata(dev);
1134 struct sci_port *sci = to_sci_port(port);
1135 int ret;
1136 long r;
1137
1138 ret = kstrtol(buf, 0, &r);
1139 if (ret)
1140 return ret;
1141
1142 sci->rx_trigger = scif_set_rtrg(port, r);
1143 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1144 scif_set_rtrg(port, 1);
1145
1146 return count;
1147}
1148
1149static DEVICE_ATTR_RW(rx_fifo_trigger);
1150
1151static ssize_t rx_fifo_timeout_show(struct device *dev,
1152 struct device_attribute *attr,
1153 char *buf)
1154{
1155 struct uart_port *port = dev_get_drvdata(dev);
1156 struct sci_port *sci = to_sci_port(port);
1157 int v;
1158
1159 if (port->type == PORT_HSCIF)
1160 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1161 else
1162 v = sci->rx_fifo_timeout;
1163
1164 return sprintf(buf, "%d\n", v);
1165}
1166
1167static ssize_t rx_fifo_timeout_store(struct device *dev,
1168 struct device_attribute *attr,
1169 const char *buf,
1170 size_t count)
1171{
1172 struct uart_port *port = dev_get_drvdata(dev);
1173 struct sci_port *sci = to_sci_port(port);
1174 int ret;
1175 long r;
1176
1177 ret = kstrtol(buf, 0, &r);
1178 if (ret)
1179 return ret;
1180
1181 if (port->type == PORT_HSCIF) {
1182 if (r < 0 || r > 3)
1183 return -EINVAL;
1184 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1185 } else {
1186 sci->rx_fifo_timeout = r;
1187 scif_set_rtrg(port, 1);
1188 if (r > 0)
1189 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1190 }
1191
1192 return count;
1193}
1194
1195static DEVICE_ATTR_RW(rx_fifo_timeout);
1196
1197
1198#ifdef CONFIG_SERIAL_SH_SCI_DMA
1199static void sci_dma_tx_complete(void *arg)
1200{
1201 struct sci_port *s = arg;
1202 struct uart_port *port = &s->port;
1203 struct circ_buf *xmit = &port->state->xmit;
1204 unsigned long flags;
1205
1206 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1207
1208 uart_port_lock_irqsave(port, &flags);
1209
1210 uart_xmit_advance(port, s->tx_dma_len);
1211
1212 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1213 uart_write_wakeup(port);
1214
1215 if (!uart_circ_empty(xmit)) {
1216 s->cookie_tx = 0;
1217 schedule_work(&s->work_tx);
1218 } else {
1219 s->cookie_tx = -EINVAL;
1220 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1221 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1222 u16 ctrl = serial_port_in(port, SCSCR);
1223 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1224 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1225 /* Switch irq from DMA to SCIF */
1226 dmaengine_pause(s->chan_tx_saved);
1227 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1228 }
1229 }
1230 }
1231
1232 uart_port_unlock_irqrestore(port, flags);
1233}
1234
1235/* Locking: called with port lock held */
1236static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1237{
1238 struct uart_port *port = &s->port;
1239 struct tty_port *tport = &port->state->port;
1240 int copied;
1241
1242 copied = tty_insert_flip_string(tport, buf, count);
1243 if (copied < count)
1244 port->icount.buf_overrun++;
1245
1246 port->icount.rx += copied;
1247
1248 return copied;
1249}
1250
1251static int sci_dma_rx_find_active(struct sci_port *s)
1252{
1253 unsigned int i;
1254
1255 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1256 if (s->active_rx == s->cookie_rx[i])
1257 return i;
1258
1259 return -1;
1260}
1261
1262static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1263{
1264 unsigned int i;
1265
1266 s->chan_rx = NULL;
1267 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1268 s->cookie_rx[i] = -EINVAL;
1269 s->active_rx = 0;
1270}
1271
1272static void sci_dma_rx_release(struct sci_port *s)
1273{
1274 struct dma_chan *chan = s->chan_rx_saved;
1275
1276 s->chan_rx_saved = NULL;
1277 sci_dma_rx_chan_invalidate(s);
1278 dmaengine_terminate_sync(chan);
1279 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1280 sg_dma_address(&s->sg_rx[0]));
1281 dma_release_channel(chan);
1282}
1283
1284static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1285{
1286 long sec = usec / 1000000;
1287 long nsec = (usec % 1000000) * 1000;
1288 ktime_t t = ktime_set(sec, nsec);
1289
1290 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1291}
1292
1293static void sci_dma_rx_reenable_irq(struct sci_port *s)
1294{
1295 struct uart_port *port = &s->port;
1296 u16 scr;
1297
1298 /* Direct new serial port interrupts back to CPU */
1299 scr = serial_port_in(port, SCSCR);
1300 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1301 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1302 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1303 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1304 scif_set_rtrg(port, s->rx_trigger);
1305 else
1306 scr &= ~SCSCR_RDRQE;
1307 }
1308 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1309}
1310
1311static void sci_dma_rx_complete(void *arg)
1312{
1313 struct sci_port *s = arg;
1314 struct dma_chan *chan = s->chan_rx;
1315 struct uart_port *port = &s->port;
1316 struct dma_async_tx_descriptor *desc;
1317 unsigned long flags;
1318 int active, count = 0;
1319
1320 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1321 s->active_rx);
1322
1323 uart_port_lock_irqsave(port, &flags);
1324
1325 active = sci_dma_rx_find_active(s);
1326 if (active >= 0)
1327 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1328
1329 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1330
1331 if (count)
1332 tty_flip_buffer_push(&port->state->port);
1333
1334 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1335 DMA_DEV_TO_MEM,
1336 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1337 if (!desc)
1338 goto fail;
1339
1340 desc->callback = sci_dma_rx_complete;
1341 desc->callback_param = s;
1342 s->cookie_rx[active] = dmaengine_submit(desc);
1343 if (dma_submit_error(s->cookie_rx[active]))
1344 goto fail;
1345
1346 s->active_rx = s->cookie_rx[!active];
1347
1348 dma_async_issue_pending(chan);
1349
1350 uart_port_unlock_irqrestore(port, flags);
1351 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1352 __func__, s->cookie_rx[active], active, s->active_rx);
1353 return;
1354
1355fail:
1356 uart_port_unlock_irqrestore(port, flags);
1357 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1358 /* Switch to PIO */
1359 uart_port_lock_irqsave(port, &flags);
1360 dmaengine_terminate_async(chan);
1361 sci_dma_rx_chan_invalidate(s);
1362 sci_dma_rx_reenable_irq(s);
1363 uart_port_unlock_irqrestore(port, flags);
1364}
1365
1366static void sci_dma_tx_release(struct sci_port *s)
1367{
1368 struct dma_chan *chan = s->chan_tx_saved;
1369
1370 cancel_work_sync(&s->work_tx);
1371 s->chan_tx_saved = s->chan_tx = NULL;
1372 s->cookie_tx = -EINVAL;
1373 dmaengine_terminate_sync(chan);
1374 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1375 DMA_TO_DEVICE);
1376 dma_release_channel(chan);
1377}
1378
1379static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1380{
1381 struct dma_chan *chan = s->chan_rx;
1382 struct uart_port *port = &s->port;
1383 unsigned long flags;
1384 int i;
1385
1386 for (i = 0; i < 2; i++) {
1387 struct scatterlist *sg = &s->sg_rx[i];
1388 struct dma_async_tx_descriptor *desc;
1389
1390 desc = dmaengine_prep_slave_sg(chan,
1391 sg, 1, DMA_DEV_TO_MEM,
1392 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1393 if (!desc)
1394 goto fail;
1395
1396 desc->callback = sci_dma_rx_complete;
1397 desc->callback_param = s;
1398 s->cookie_rx[i] = dmaengine_submit(desc);
1399 if (dma_submit_error(s->cookie_rx[i]))
1400 goto fail;
1401
1402 }
1403
1404 s->active_rx = s->cookie_rx[0];
1405
1406 dma_async_issue_pending(chan);
1407 return 0;
1408
1409fail:
1410 /* Switch to PIO */
1411 if (!port_lock_held)
1412 uart_port_lock_irqsave(port, &flags);
1413 if (i)
1414 dmaengine_terminate_async(chan);
1415 sci_dma_rx_chan_invalidate(s);
1416 sci_start_rx(port);
1417 if (!port_lock_held)
1418 uart_port_unlock_irqrestore(port, flags);
1419 return -EAGAIN;
1420}
1421
1422static void sci_dma_tx_work_fn(struct work_struct *work)
1423{
1424 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1425 struct dma_async_tx_descriptor *desc;
1426 struct dma_chan *chan = s->chan_tx;
1427 struct uart_port *port = &s->port;
1428 struct circ_buf *xmit = &port->state->xmit;
1429 unsigned long flags;
1430 dma_addr_t buf;
1431 int head, tail;
1432
1433 /*
1434 * DMA is idle now.
1435 * Port xmit buffer is already mapped, and it is one page... Just adjust
1436 * offsets and lengths. Since it is a circular buffer, we have to
1437 * transmit till the end, and then the rest. Take the port lock to get a
1438 * consistent xmit buffer state.
1439 */
1440 uart_port_lock_irq(port);
1441 head = xmit->head;
1442 tail = xmit->tail;
1443 buf = s->tx_dma_addr + tail;
1444 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE);
1445 if (!s->tx_dma_len) {
1446 /* Transmit buffer has been flushed */
1447 uart_port_unlock_irq(port);
1448 return;
1449 }
1450
1451 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1452 DMA_MEM_TO_DEV,
1453 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1454 if (!desc) {
1455 uart_port_unlock_irq(port);
1456 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1457 goto switch_to_pio;
1458 }
1459
1460 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1461 DMA_TO_DEVICE);
1462
1463 desc->callback = sci_dma_tx_complete;
1464 desc->callback_param = s;
1465 s->cookie_tx = dmaengine_submit(desc);
1466 if (dma_submit_error(s->cookie_tx)) {
1467 uart_port_unlock_irq(port);
1468 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1469 goto switch_to_pio;
1470 }
1471
1472 uart_port_unlock_irq(port);
1473 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1474 __func__, xmit->buf, tail, head, s->cookie_tx);
1475
1476 dma_async_issue_pending(chan);
1477 return;
1478
1479switch_to_pio:
1480 uart_port_lock_irqsave(port, &flags);
1481 s->chan_tx = NULL;
1482 sci_start_tx(port);
1483 uart_port_unlock_irqrestore(port, flags);
1484 return;
1485}
1486
1487static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1488{
1489 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1490 struct dma_chan *chan = s->chan_rx;
1491 struct uart_port *port = &s->port;
1492 struct dma_tx_state state;
1493 enum dma_status status;
1494 unsigned long flags;
1495 unsigned int read;
1496 int active, count;
1497
1498 dev_dbg(port->dev, "DMA Rx timed out\n");
1499
1500 uart_port_lock_irqsave(port, &flags);
1501
1502 active = sci_dma_rx_find_active(s);
1503 if (active < 0) {
1504 uart_port_unlock_irqrestore(port, flags);
1505 return HRTIMER_NORESTART;
1506 }
1507
1508 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1509 if (status == DMA_COMPLETE) {
1510 uart_port_unlock_irqrestore(port, flags);
1511 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1512 s->active_rx, active);
1513
1514 /* Let packet complete handler take care of the packet */
1515 return HRTIMER_NORESTART;
1516 }
1517
1518 dmaengine_pause(chan);
1519
1520 /*
1521 * sometimes DMA transfer doesn't stop even if it is stopped and
1522 * data keeps on coming until transaction is complete so check
1523 * for DMA_COMPLETE again
1524 * Let packet complete handler take care of the packet
1525 */
1526 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1527 if (status == DMA_COMPLETE) {
1528 uart_port_unlock_irqrestore(port, flags);
1529 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1530 return HRTIMER_NORESTART;
1531 }
1532
1533 /* Handle incomplete DMA receive */
1534 dmaengine_terminate_async(s->chan_rx);
1535 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1536
1537 if (read) {
1538 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1539 if (count)
1540 tty_flip_buffer_push(&port->state->port);
1541 }
1542
1543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1544 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1545 sci_dma_rx_submit(s, true);
1546
1547 sci_dma_rx_reenable_irq(s);
1548
1549 uart_port_unlock_irqrestore(port, flags);
1550
1551 return HRTIMER_NORESTART;
1552}
1553
1554static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1555 enum dma_transfer_direction dir)
1556{
1557 struct dma_chan *chan;
1558 struct dma_slave_config cfg;
1559 int ret;
1560
1561 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1562 if (IS_ERR(chan)) {
1563 dev_dbg(port->dev, "dma_request_chan failed\n");
1564 return NULL;
1565 }
1566
1567 memset(&cfg, 0, sizeof(cfg));
1568 cfg.direction = dir;
1569 cfg.dst_addr = port->mapbase +
1570 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1571 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1572 cfg.src_addr = port->mapbase +
1573 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1574 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1575
1576 ret = dmaengine_slave_config(chan, &cfg);
1577 if (ret) {
1578 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1579 dma_release_channel(chan);
1580 return NULL;
1581 }
1582
1583 return chan;
1584}
1585
1586static void sci_request_dma(struct uart_port *port)
1587{
1588 struct sci_port *s = to_sci_port(port);
1589 struct dma_chan *chan;
1590
1591 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1592
1593 /*
1594 * DMA on console may interfere with Kernel log messages which use
1595 * plain putchar(). So, simply don't use it with a console.
1596 */
1597 if (uart_console(port))
1598 return;
1599
1600 if (!port->dev->of_node)
1601 return;
1602
1603 s->cookie_tx = -EINVAL;
1604
1605 /*
1606 * Don't request a dma channel if no channel was specified
1607 * in the device tree.
1608 */
1609 if (!of_property_present(port->dev->of_node, "dmas"))
1610 return;
1611
1612 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1613 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1614 if (chan) {
1615 /* UART circular tx buffer is an aligned page. */
1616 s->tx_dma_addr = dma_map_single(chan->device->dev,
1617 port->state->xmit.buf,
1618 UART_XMIT_SIZE,
1619 DMA_TO_DEVICE);
1620 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1621 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1622 dma_release_channel(chan);
1623 } else {
1624 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1625 __func__, UART_XMIT_SIZE,
1626 port->state->xmit.buf, &s->tx_dma_addr);
1627
1628 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1629 s->chan_tx_saved = s->chan_tx = chan;
1630 }
1631 }
1632
1633 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1634 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1635 if (chan) {
1636 unsigned int i;
1637 dma_addr_t dma;
1638 void *buf;
1639
1640 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1641 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1642 &dma, GFP_KERNEL);
1643 if (!buf) {
1644 dev_warn(port->dev,
1645 "Failed to allocate Rx dma buffer, using PIO\n");
1646 dma_release_channel(chan);
1647 return;
1648 }
1649
1650 for (i = 0; i < 2; i++) {
1651 struct scatterlist *sg = &s->sg_rx[i];
1652
1653 sg_init_table(sg, 1);
1654 s->rx_buf[i] = buf;
1655 sg_dma_address(sg) = dma;
1656 sg_dma_len(sg) = s->buf_len_rx;
1657
1658 buf += s->buf_len_rx;
1659 dma += s->buf_len_rx;
1660 }
1661
1662 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1663 s->rx_timer.function = sci_dma_rx_timer_fn;
1664
1665 s->chan_rx_saved = s->chan_rx = chan;
1666
1667 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1668 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1669 sci_dma_rx_submit(s, false);
1670 }
1671}
1672
1673static void sci_free_dma(struct uart_port *port)
1674{
1675 struct sci_port *s = to_sci_port(port);
1676
1677 if (s->chan_tx_saved)
1678 sci_dma_tx_release(s);
1679 if (s->chan_rx_saved)
1680 sci_dma_rx_release(s);
1681}
1682
1683static void sci_flush_buffer(struct uart_port *port)
1684{
1685 struct sci_port *s = to_sci_port(port);
1686
1687 /*
1688 * In uart_flush_buffer(), the xmit circular buffer has just been
1689 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1690 * pending transfers
1691 */
1692 s->tx_dma_len = 0;
1693 if (s->chan_tx) {
1694 dmaengine_terminate_async(s->chan_tx);
1695 s->cookie_tx = -EINVAL;
1696 }
1697}
1698#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1699static inline void sci_request_dma(struct uart_port *port)
1700{
1701}
1702
1703static inline void sci_free_dma(struct uart_port *port)
1704{
1705}
1706
1707#define sci_flush_buffer NULL
1708#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1709
1710static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1711{
1712 struct uart_port *port = ptr;
1713 struct sci_port *s = to_sci_port(port);
1714
1715#ifdef CONFIG_SERIAL_SH_SCI_DMA
1716 if (s->chan_rx) {
1717 u16 scr = serial_port_in(port, SCSCR);
1718 u16 ssr = serial_port_in(port, SCxSR);
1719
1720 /* Disable future Rx interrupts */
1721 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1722 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1723 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1724 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1725 scif_set_rtrg(port, 1);
1726 scr |= SCSCR_RIE;
1727 } else {
1728 scr |= SCSCR_RDRQE;
1729 }
1730 } else {
1731 if (sci_dma_rx_submit(s, false) < 0)
1732 goto handle_pio;
1733
1734 scr &= ~SCSCR_RIE;
1735 }
1736 serial_port_out(port, SCSCR, scr);
1737 /* Clear current interrupt */
1738 serial_port_out(port, SCxSR,
1739 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1740 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1741 jiffies, s->rx_timeout);
1742 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1743
1744 return IRQ_HANDLED;
1745 }
1746
1747handle_pio:
1748#endif
1749
1750 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1751 if (!scif_rtrg_enabled(port))
1752 scif_set_rtrg(port, s->rx_trigger);
1753
1754 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1755 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1756 }
1757
1758 /* I think sci_receive_chars has to be called irrespective
1759 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1760 * to be disabled?
1761 */
1762 sci_receive_chars(port);
1763
1764 return IRQ_HANDLED;
1765}
1766
1767static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1768{
1769 struct uart_port *port = ptr;
1770 unsigned long flags;
1771
1772 uart_port_lock_irqsave(port, &flags);
1773 sci_transmit_chars(port);
1774 uart_port_unlock_irqrestore(port, flags);
1775
1776 return IRQ_HANDLED;
1777}
1778
1779static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1780{
1781 struct uart_port *port = ptr;
1782 unsigned long flags;
1783 unsigned short ctrl;
1784
1785 if (port->type != PORT_SCI)
1786 return sci_tx_interrupt(irq, ptr);
1787
1788 uart_port_lock_irqsave(port, &flags);
1789 ctrl = serial_port_in(port, SCSCR);
1790 ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
1791 serial_port_out(port, SCSCR, ctrl);
1792 uart_port_unlock_irqrestore(port, flags);
1793
1794 return IRQ_HANDLED;
1795}
1796
1797static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1798{
1799 struct uart_port *port = ptr;
1800
1801 /* Handle BREAKs */
1802 sci_handle_breaks(port);
1803
1804 /* drop invalid character received before break was detected */
1805 serial_port_in(port, SCxRDR);
1806
1807 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1808
1809 return IRQ_HANDLED;
1810}
1811
1812static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1813{
1814 struct uart_port *port = ptr;
1815 struct sci_port *s = to_sci_port(port);
1816
1817 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1818 /* Break and Error interrupts are muxed */
1819 unsigned short ssr_status = serial_port_in(port, SCxSR);
1820
1821 /* Break Interrupt */
1822 if (ssr_status & SCxSR_BRK(port))
1823 sci_br_interrupt(irq, ptr);
1824
1825 /* Break only? */
1826 if (!(ssr_status & SCxSR_ERRORS(port)))
1827 return IRQ_HANDLED;
1828 }
1829
1830 /* Handle errors */
1831 if (port->type == PORT_SCI) {
1832 if (sci_handle_errors(port)) {
1833 /* discard character in rx buffer */
1834 serial_port_in(port, SCxSR);
1835 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1836 }
1837 } else {
1838 sci_handle_fifo_overrun(port);
1839 if (!s->chan_rx)
1840 sci_receive_chars(port);
1841 }
1842
1843 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1844
1845 /* Kick the transmission */
1846 if (!s->chan_tx)
1847 sci_tx_interrupt(irq, ptr);
1848
1849 return IRQ_HANDLED;
1850}
1851
1852static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1853{
1854 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1855 struct uart_port *port = ptr;
1856 struct sci_port *s = to_sci_port(port);
1857 irqreturn_t ret = IRQ_NONE;
1858
1859 ssr_status = serial_port_in(port, SCxSR);
1860 scr_status = serial_port_in(port, SCSCR);
1861 if (s->params->overrun_reg == SCxSR)
1862 orer_status = ssr_status;
1863 else if (sci_getreg(port, s->params->overrun_reg)->size)
1864 orer_status = serial_port_in(port, s->params->overrun_reg);
1865
1866 err_enabled = scr_status & port_rx_irq_mask(port);
1867
1868 /* Tx Interrupt */
1869 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1870 !s->chan_tx)
1871 ret = sci_tx_interrupt(irq, ptr);
1872
1873 /*
1874 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1875 * DR flags
1876 */
1877 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1878 (scr_status & SCSCR_RIE))
1879 ret = sci_rx_interrupt(irq, ptr);
1880
1881 /* Error Interrupt */
1882 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1883 ret = sci_er_interrupt(irq, ptr);
1884
1885 /* Break Interrupt */
1886 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1887 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1888 ret = sci_br_interrupt(irq, ptr);
1889
1890 /* Overrun Interrupt */
1891 if (orer_status & s->params->overrun_mask) {
1892 sci_handle_fifo_overrun(port);
1893 ret = IRQ_HANDLED;
1894 }
1895
1896 return ret;
1897}
1898
1899static const struct sci_irq_desc {
1900 const char *desc;
1901 irq_handler_t handler;
1902} sci_irq_desc[] = {
1903 /*
1904 * Split out handlers, the default case.
1905 */
1906 [SCIx_ERI_IRQ] = {
1907 .desc = "rx err",
1908 .handler = sci_er_interrupt,
1909 },
1910
1911 [SCIx_RXI_IRQ] = {
1912 .desc = "rx full",
1913 .handler = sci_rx_interrupt,
1914 },
1915
1916 [SCIx_TXI_IRQ] = {
1917 .desc = "tx empty",
1918 .handler = sci_tx_interrupt,
1919 },
1920
1921 [SCIx_BRI_IRQ] = {
1922 .desc = "break",
1923 .handler = sci_br_interrupt,
1924 },
1925
1926 [SCIx_DRI_IRQ] = {
1927 .desc = "rx ready",
1928 .handler = sci_rx_interrupt,
1929 },
1930
1931 [SCIx_TEI_IRQ] = {
1932 .desc = "tx end",
1933 .handler = sci_tx_end_interrupt,
1934 },
1935
1936 /*
1937 * Special muxed handler.
1938 */
1939 [SCIx_MUX_IRQ] = {
1940 .desc = "mux",
1941 .handler = sci_mpxed_interrupt,
1942 },
1943};
1944
1945static int sci_request_irq(struct sci_port *port)
1946{
1947 struct uart_port *up = &port->port;
1948 int i, j, w, ret = 0;
1949
1950 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1951 const struct sci_irq_desc *desc;
1952 int irq;
1953
1954 /* Check if already registered (muxed) */
1955 for (w = 0; w < i; w++)
1956 if (port->irqs[w] == port->irqs[i])
1957 w = i + 1;
1958 if (w > i)
1959 continue;
1960
1961 if (SCIx_IRQ_IS_MUXED(port)) {
1962 i = SCIx_MUX_IRQ;
1963 irq = up->irq;
1964 } else {
1965 irq = port->irqs[i];
1966
1967 /*
1968 * Certain port types won't support all of the
1969 * available interrupt sources.
1970 */
1971 if (unlikely(irq < 0))
1972 continue;
1973 }
1974
1975 desc = sci_irq_desc + i;
1976 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1977 dev_name(up->dev), desc->desc);
1978 if (!port->irqstr[j]) {
1979 ret = -ENOMEM;
1980 goto out_nomem;
1981 }
1982
1983 ret = request_irq(irq, desc->handler, up->irqflags,
1984 port->irqstr[j], port);
1985 if (unlikely(ret)) {
1986 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1987 goto out_noirq;
1988 }
1989 }
1990
1991 return 0;
1992
1993out_noirq:
1994 while (--i >= 0)
1995 free_irq(port->irqs[i], port);
1996
1997out_nomem:
1998 while (--j >= 0)
1999 kfree(port->irqstr[j]);
2000
2001 return ret;
2002}
2003
2004static void sci_free_irq(struct sci_port *port)
2005{
2006 int i, j;
2007
2008 /*
2009 * Intentionally in reverse order so we iterate over the muxed
2010 * IRQ first.
2011 */
2012 for (i = 0; i < SCIx_NR_IRQS; i++) {
2013 int irq = port->irqs[i];
2014
2015 /*
2016 * Certain port types won't support all of the available
2017 * interrupt sources.
2018 */
2019 if (unlikely(irq < 0))
2020 continue;
2021
2022 /* Check if already freed (irq was muxed) */
2023 for (j = 0; j < i; j++)
2024 if (port->irqs[j] == irq)
2025 j = i + 1;
2026 if (j > i)
2027 continue;
2028
2029 free_irq(port->irqs[i], port);
2030 kfree(port->irqstr[i]);
2031
2032 if (SCIx_IRQ_IS_MUXED(port)) {
2033 /* If there's only one IRQ, we're done. */
2034 return;
2035 }
2036 }
2037}
2038
2039static unsigned int sci_tx_empty(struct uart_port *port)
2040{
2041 unsigned short status = serial_port_in(port, SCxSR);
2042 unsigned short in_tx_fifo = sci_txfill(port);
2043
2044 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2045}
2046
2047static void sci_set_rts(struct uart_port *port, bool state)
2048{
2049 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2050 u16 data = serial_port_in(port, SCPDR);
2051
2052 /* Active low */
2053 if (state)
2054 data &= ~SCPDR_RTSD;
2055 else
2056 data |= SCPDR_RTSD;
2057 serial_port_out(port, SCPDR, data);
2058
2059 /* RTS# is output */
2060 serial_port_out(port, SCPCR,
2061 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2062 } else if (sci_getreg(port, SCSPTR)->size) {
2063 u16 ctrl = serial_port_in(port, SCSPTR);
2064
2065 /* Active low */
2066 if (state)
2067 ctrl &= ~SCSPTR_RTSDT;
2068 else
2069 ctrl |= SCSPTR_RTSDT;
2070 serial_port_out(port, SCSPTR, ctrl);
2071 }
2072}
2073
2074static bool sci_get_cts(struct uart_port *port)
2075{
2076 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2077 /* Active low */
2078 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2079 } else if (sci_getreg(port, SCSPTR)->size) {
2080 /* Active low */
2081 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2082 }
2083
2084 return true;
2085}
2086
2087/*
2088 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2089 * CTS/RTS is supported in hardware by at least one port and controlled
2090 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2091 * handled via the ->init_pins() op, which is a bit of a one-way street,
2092 * lacking any ability to defer pin control -- this will later be
2093 * converted over to the GPIO framework).
2094 *
2095 * Other modes (such as loopback) are supported generically on certain
2096 * port types, but not others. For these it's sufficient to test for the
2097 * existence of the support register and simply ignore the port type.
2098 */
2099static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2100{
2101 struct sci_port *s = to_sci_port(port);
2102
2103 if (mctrl & TIOCM_LOOP) {
2104 const struct plat_sci_reg *reg;
2105
2106 /*
2107 * Standard loopback mode for SCFCR ports.
2108 */
2109 reg = sci_getreg(port, SCFCR);
2110 if (reg->size)
2111 serial_port_out(port, SCFCR,
2112 serial_port_in(port, SCFCR) |
2113 SCFCR_LOOP);
2114 }
2115
2116 mctrl_gpio_set(s->gpios, mctrl);
2117
2118 if (!s->has_rtscts)
2119 return;
2120
2121 if (!(mctrl & TIOCM_RTS)) {
2122 /* Disable Auto RTS */
2123 serial_port_out(port, SCFCR,
2124 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2125
2126 /* Clear RTS */
2127 sci_set_rts(port, 0);
2128 } else if (s->autorts) {
2129 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2130 /* Enable RTS# pin function */
2131 serial_port_out(port, SCPCR,
2132 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2133 }
2134
2135 /* Enable Auto RTS */
2136 serial_port_out(port, SCFCR,
2137 serial_port_in(port, SCFCR) | SCFCR_MCE);
2138 } else {
2139 /* Set RTS */
2140 sci_set_rts(port, 1);
2141 }
2142}
2143
2144static unsigned int sci_get_mctrl(struct uart_port *port)
2145{
2146 struct sci_port *s = to_sci_port(port);
2147 struct mctrl_gpios *gpios = s->gpios;
2148 unsigned int mctrl = 0;
2149
2150 mctrl_gpio_get(gpios, &mctrl);
2151
2152 /*
2153 * CTS/RTS is handled in hardware when supported, while nothing
2154 * else is wired up.
2155 */
2156 if (s->autorts) {
2157 if (sci_get_cts(port))
2158 mctrl |= TIOCM_CTS;
2159 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2160 mctrl |= TIOCM_CTS;
2161 }
2162 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2163 mctrl |= TIOCM_DSR;
2164 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2165 mctrl |= TIOCM_CAR;
2166
2167 return mctrl;
2168}
2169
2170static void sci_enable_ms(struct uart_port *port)
2171{
2172 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2173}
2174
2175static void sci_break_ctl(struct uart_port *port, int break_state)
2176{
2177 unsigned short scscr, scsptr;
2178 unsigned long flags;
2179
2180 /* check whether the port has SCSPTR */
2181 if (!sci_getreg(port, SCSPTR)->size) {
2182 /*
2183 * Not supported by hardware. Most parts couple break and rx
2184 * interrupts together, with break detection always enabled.
2185 */
2186 return;
2187 }
2188
2189 uart_port_lock_irqsave(port, &flags);
2190 scsptr = serial_port_in(port, SCSPTR);
2191 scscr = serial_port_in(port, SCSCR);
2192
2193 if (break_state == -1) {
2194 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2195 scscr &= ~SCSCR_TE;
2196 } else {
2197 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2198 scscr |= SCSCR_TE;
2199 }
2200
2201 serial_port_out(port, SCSPTR, scsptr);
2202 serial_port_out(port, SCSCR, scscr);
2203 uart_port_unlock_irqrestore(port, flags);
2204}
2205
2206static int sci_startup(struct uart_port *port)
2207{
2208 struct sci_port *s = to_sci_port(port);
2209 int ret;
2210
2211 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2212
2213 sci_request_dma(port);
2214
2215 ret = sci_request_irq(s);
2216 if (unlikely(ret < 0)) {
2217 sci_free_dma(port);
2218 return ret;
2219 }
2220
2221 return 0;
2222}
2223
2224static void sci_shutdown(struct uart_port *port)
2225{
2226 struct sci_port *s = to_sci_port(port);
2227 unsigned long flags;
2228 u16 scr;
2229
2230 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2231
2232 s->autorts = false;
2233 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2234
2235 uart_port_lock_irqsave(port, &flags);
2236 sci_stop_rx(port);
2237 sci_stop_tx(port);
2238 /*
2239 * Stop RX and TX, disable related interrupts, keep clock source
2240 * and HSCIF TOT bits
2241 */
2242 scr = serial_port_in(port, SCSCR);
2243 serial_port_out(port, SCSCR, scr &
2244 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2245 uart_port_unlock_irqrestore(port, flags);
2246
2247#ifdef CONFIG_SERIAL_SH_SCI_DMA
2248 if (s->chan_rx_saved) {
2249 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2250 port->line);
2251 hrtimer_cancel(&s->rx_timer);
2252 }
2253#endif
2254
2255 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2256 del_timer_sync(&s->rx_fifo_timer);
2257 sci_free_irq(s);
2258 sci_free_dma(port);
2259}
2260
2261static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2262 unsigned int *srr)
2263{
2264 unsigned long freq = s->clk_rates[SCI_SCK];
2265 int err, min_err = INT_MAX;
2266 unsigned int sr;
2267
2268 if (s->port.type != PORT_HSCIF)
2269 freq *= 2;
2270
2271 for_each_sr(sr, s) {
2272 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2273 if (abs(err) >= abs(min_err))
2274 continue;
2275
2276 min_err = err;
2277 *srr = sr - 1;
2278
2279 if (!err)
2280 break;
2281 }
2282
2283 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2284 *srr + 1);
2285 return min_err;
2286}
2287
2288static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2289 unsigned long freq, unsigned int *dlr,
2290 unsigned int *srr)
2291{
2292 int err, min_err = INT_MAX;
2293 unsigned int sr, dl;
2294
2295 if (s->port.type != PORT_HSCIF)
2296 freq *= 2;
2297
2298 for_each_sr(sr, s) {
2299 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2300 dl = clamp(dl, 1U, 65535U);
2301
2302 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2303 if (abs(err) >= abs(min_err))
2304 continue;
2305
2306 min_err = err;
2307 *dlr = dl;
2308 *srr = sr - 1;
2309
2310 if (!err)
2311 break;
2312 }
2313
2314 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2315 min_err, *dlr, *srr + 1);
2316 return min_err;
2317}
2318
2319/* calculate sample rate, BRR, and clock select */
2320static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2321 unsigned int *brr, unsigned int *srr,
2322 unsigned int *cks)
2323{
2324 unsigned long freq = s->clk_rates[SCI_FCK];
2325 unsigned int sr, br, prediv, scrate, c;
2326 int err, min_err = INT_MAX;
2327
2328 if (s->port.type != PORT_HSCIF)
2329 freq *= 2;
2330
2331 /*
2332 * Find the combination of sample rate and clock select with the
2333 * smallest deviation from the desired baud rate.
2334 * Prefer high sample rates to maximise the receive margin.
2335 *
2336 * M: Receive margin (%)
2337 * N: Ratio of bit rate to clock (N = sampling rate)
2338 * D: Clock duty (D = 0 to 1.0)
2339 * L: Frame length (L = 9 to 12)
2340 * F: Absolute value of clock frequency deviation
2341 *
2342 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2343 * (|D - 0.5| / N * (1 + F))|
2344 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2345 */
2346 for_each_sr(sr, s) {
2347 for (c = 0; c <= 3; c++) {
2348 /* integerized formulas from HSCIF documentation */
2349 prediv = sr << (2 * c + 1);
2350
2351 /*
2352 * We need to calculate:
2353 *
2354 * br = freq / (prediv * bps) clamped to [1..256]
2355 * err = freq / (br * prediv) - bps
2356 *
2357 * Watch out for overflow when calculating the desired
2358 * sampling clock rate!
2359 */
2360 if (bps > UINT_MAX / prediv)
2361 break;
2362
2363 scrate = prediv * bps;
2364 br = DIV_ROUND_CLOSEST(freq, scrate);
2365 br = clamp(br, 1U, 256U);
2366
2367 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2368 if (abs(err) >= abs(min_err))
2369 continue;
2370
2371 min_err = err;
2372 *brr = br - 1;
2373 *srr = sr - 1;
2374 *cks = c;
2375
2376 if (!err)
2377 goto found;
2378 }
2379 }
2380
2381found:
2382 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2383 min_err, *brr, *srr + 1, *cks);
2384 return min_err;
2385}
2386
2387static void sci_reset(struct uart_port *port)
2388{
2389 const struct plat_sci_reg *reg;
2390 unsigned int status;
2391 struct sci_port *s = to_sci_port(port);
2392
2393 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2394
2395 reg = sci_getreg(port, SCFCR);
2396 if (reg->size)
2397 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2398
2399 sci_clear_SCxSR(port,
2400 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2401 SCxSR_BREAK_CLEAR(port));
2402 if (sci_getreg(port, SCLSR)->size) {
2403 status = serial_port_in(port, SCLSR);
2404 status &= ~(SCLSR_TO | SCLSR_ORER);
2405 serial_port_out(port, SCLSR, status);
2406 }
2407
2408 if (s->rx_trigger > 1) {
2409 if (s->rx_fifo_timeout) {
2410 scif_set_rtrg(port, 1);
2411 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2412 } else {
2413 if (port->type == PORT_SCIFA ||
2414 port->type == PORT_SCIFB)
2415 scif_set_rtrg(port, 1);
2416 else
2417 scif_set_rtrg(port, s->rx_trigger);
2418 }
2419 }
2420}
2421
2422static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2423 const struct ktermios *old)
2424{
2425 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2426 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2427 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2428 struct sci_port *s = to_sci_port(port);
2429 const struct plat_sci_reg *reg;
2430 int min_err = INT_MAX, err;
2431 unsigned long max_freq = 0;
2432 int best_clk = -1;
2433 unsigned long flags;
2434
2435 if ((termios->c_cflag & CSIZE) == CS7) {
2436 smr_val |= SCSMR_CHR;
2437 } else {
2438 termios->c_cflag &= ~CSIZE;
2439 termios->c_cflag |= CS8;
2440 }
2441 if (termios->c_cflag & PARENB)
2442 smr_val |= SCSMR_PE;
2443 if (termios->c_cflag & PARODD)
2444 smr_val |= SCSMR_PE | SCSMR_ODD;
2445 if (termios->c_cflag & CSTOPB)
2446 smr_val |= SCSMR_STOP;
2447
2448 /*
2449 * earlyprintk comes here early on with port->uartclk set to zero.
2450 * the clock framework is not up and running at this point so here
2451 * we assume that 115200 is the maximum baud rate. please note that
2452 * the baud rate is not programmed during earlyprintk - it is assumed
2453 * that the previous boot loader has enabled required clocks and
2454 * setup the baud rate generator hardware for us already.
2455 */
2456 if (!port->uartclk) {
2457 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2458 goto done;
2459 }
2460
2461 for (i = 0; i < SCI_NUM_CLKS; i++)
2462 max_freq = max(max_freq, s->clk_rates[i]);
2463
2464 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2465 if (!baud)
2466 goto done;
2467
2468 /*
2469 * There can be multiple sources for the sampling clock. Find the one
2470 * that gives us the smallest deviation from the desired baud rate.
2471 */
2472
2473 /* Optional Undivided External Clock */
2474 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2475 port->type != PORT_SCIFB) {
2476 err = sci_sck_calc(s, baud, &srr1);
2477 if (abs(err) < abs(min_err)) {
2478 best_clk = SCI_SCK;
2479 scr_val = SCSCR_CKE1;
2480 sccks = SCCKS_CKS;
2481 min_err = err;
2482 srr = srr1;
2483 if (!err)
2484 goto done;
2485 }
2486 }
2487
2488 /* Optional BRG Frequency Divided External Clock */
2489 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2490 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2491 &srr1);
2492 if (abs(err) < abs(min_err)) {
2493 best_clk = SCI_SCIF_CLK;
2494 scr_val = SCSCR_CKE1;
2495 sccks = 0;
2496 min_err = err;
2497 dl = dl1;
2498 srr = srr1;
2499 if (!err)
2500 goto done;
2501 }
2502 }
2503
2504 /* Optional BRG Frequency Divided Internal Clock */
2505 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2506 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2507 &srr1);
2508 if (abs(err) < abs(min_err)) {
2509 best_clk = SCI_BRG_INT;
2510 scr_val = SCSCR_CKE1;
2511 sccks = SCCKS_XIN;
2512 min_err = err;
2513 dl = dl1;
2514 srr = srr1;
2515 if (!min_err)
2516 goto done;
2517 }
2518 }
2519
2520 /* Divided Functional Clock using standard Bit Rate Register */
2521 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2522 if (abs(err) < abs(min_err)) {
2523 best_clk = SCI_FCK;
2524 scr_val = 0;
2525 min_err = err;
2526 brr = brr1;
2527 srr = srr1;
2528 cks = cks1;
2529 }
2530
2531done:
2532 if (best_clk >= 0)
2533 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2534 s->clks[best_clk], baud, min_err);
2535
2536 sci_port_enable(s);
2537
2538 /*
2539 * Program the optional External Baud Rate Generator (BRG) first.
2540 * It controls the mux to select (H)SCK or frequency divided clock.
2541 */
2542 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2543 serial_port_out(port, SCDL, dl);
2544 serial_port_out(port, SCCKS, sccks);
2545 }
2546
2547 uart_port_lock_irqsave(port, &flags);
2548
2549 sci_reset(port);
2550
2551 uart_update_timeout(port, termios->c_cflag, baud);
2552
2553 /* byte size and parity */
2554 bits = tty_get_frame_size(termios->c_cflag);
2555
2556 if (sci_getreg(port, SEMR)->size)
2557 serial_port_out(port, SEMR, 0);
2558
2559 if (best_clk >= 0) {
2560 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2561 switch (srr + 1) {
2562 case 5: smr_val |= SCSMR_SRC_5; break;
2563 case 7: smr_val |= SCSMR_SRC_7; break;
2564 case 11: smr_val |= SCSMR_SRC_11; break;
2565 case 13: smr_val |= SCSMR_SRC_13; break;
2566 case 16: smr_val |= SCSMR_SRC_16; break;
2567 case 17: smr_val |= SCSMR_SRC_17; break;
2568 case 19: smr_val |= SCSMR_SRC_19; break;
2569 case 27: smr_val |= SCSMR_SRC_27; break;
2570 }
2571 smr_val |= cks;
2572 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2573 serial_port_out(port, SCSMR, smr_val);
2574 serial_port_out(port, SCBRR, brr);
2575 if (sci_getreg(port, HSSRR)->size) {
2576 unsigned int hssrr = srr | HSCIF_SRE;
2577 /* Calculate deviation from intended rate at the
2578 * center of the last stop bit in sampling clocks.
2579 */
2580 int last_stop = bits * 2 - 1;
2581 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2582 (int)(srr + 1),
2583 2 * (int)baud);
2584
2585 if (abs(deviation) >= 2) {
2586 /* At least two sampling clocks off at the
2587 * last stop bit; we can increase the error
2588 * margin by shifting the sampling point.
2589 */
2590 int shift = clamp(deviation / 2, -8, 7);
2591
2592 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2593 HSCIF_SRHP_MASK;
2594 hssrr |= HSCIF_SRDE;
2595 }
2596 serial_port_out(port, HSSRR, hssrr);
2597 }
2598
2599 /* Wait one bit interval */
2600 udelay((1000000 + (baud - 1)) / baud);
2601 } else {
2602 /* Don't touch the bit rate configuration */
2603 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2604 smr_val |= serial_port_in(port, SCSMR) &
2605 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2606 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2607 serial_port_out(port, SCSMR, smr_val);
2608 }
2609
2610 sci_init_pins(port, termios->c_cflag);
2611
2612 port->status &= ~UPSTAT_AUTOCTS;
2613 s->autorts = false;
2614 reg = sci_getreg(port, SCFCR);
2615 if (reg->size) {
2616 unsigned short ctrl = serial_port_in(port, SCFCR);
2617
2618 if ((port->flags & UPF_HARD_FLOW) &&
2619 (termios->c_cflag & CRTSCTS)) {
2620 /* There is no CTS interrupt to restart the hardware */
2621 port->status |= UPSTAT_AUTOCTS;
2622 /* MCE is enabled when RTS is raised */
2623 s->autorts = true;
2624 }
2625
2626 /*
2627 * As we've done a sci_reset() above, ensure we don't
2628 * interfere with the FIFOs while toggling MCE. As the
2629 * reset values could still be set, simply mask them out.
2630 */
2631 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2632
2633 serial_port_out(port, SCFCR, ctrl);
2634 }
2635 if (port->flags & UPF_HARD_FLOW) {
2636 /* Refresh (Auto) RTS */
2637 sci_set_mctrl(port, port->mctrl);
2638 }
2639
2640 /*
2641 * For SCI, TE (transmit enable) must be set after setting TIE
2642 * (transmit interrupt enable) or in the same instruction to
2643 * start the transmitting process. So skip setting TE here for SCI.
2644 */
2645 if (port->type != PORT_SCI)
2646 scr_val |= SCSCR_TE;
2647 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2648 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2649 if ((srr + 1 == 5) &&
2650 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2651 /*
2652 * In asynchronous mode, when the sampling rate is 1/5, first
2653 * received data may become invalid on some SCIFA and SCIFB.
2654 * To avoid this problem wait more than 1 serial data time (1
2655 * bit time x serial data number) after setting SCSCR.RE = 1.
2656 */
2657 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2658 }
2659
2660 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2661 s->rx_frame = (10000 * bits) / (baud / 100);
2662#ifdef CONFIG_SERIAL_SH_SCI_DMA
2663 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2664#endif
2665
2666 if ((termios->c_cflag & CREAD) != 0)
2667 sci_start_rx(port);
2668
2669 uart_port_unlock_irqrestore(port, flags);
2670
2671 sci_port_disable(s);
2672
2673 if (UART_ENABLE_MS(port, termios->c_cflag))
2674 sci_enable_ms(port);
2675}
2676
2677static void sci_pm(struct uart_port *port, unsigned int state,
2678 unsigned int oldstate)
2679{
2680 struct sci_port *sci_port = to_sci_port(port);
2681
2682 switch (state) {
2683 case UART_PM_STATE_OFF:
2684 sci_port_disable(sci_port);
2685 break;
2686 default:
2687 sci_port_enable(sci_port);
2688 break;
2689 }
2690}
2691
2692static const char *sci_type(struct uart_port *port)
2693{
2694 switch (port->type) {
2695 case PORT_IRDA:
2696 return "irda";
2697 case PORT_SCI:
2698 return "sci";
2699 case PORT_SCIF:
2700 return "scif";
2701 case PORT_SCIFA:
2702 return "scifa";
2703 case PORT_SCIFB:
2704 return "scifb";
2705 case PORT_HSCIF:
2706 return "hscif";
2707 }
2708
2709 return NULL;
2710}
2711
2712static int sci_remap_port(struct uart_port *port)
2713{
2714 struct sci_port *sport = to_sci_port(port);
2715
2716 /*
2717 * Nothing to do if there's already an established membase.
2718 */
2719 if (port->membase)
2720 return 0;
2721
2722 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2723 port->membase = ioremap(port->mapbase, sport->reg_size);
2724 if (unlikely(!port->membase)) {
2725 dev_err(port->dev, "can't remap port#%d\n", port->line);
2726 return -ENXIO;
2727 }
2728 } else {
2729 /*
2730 * For the simple (and majority of) cases where we don't
2731 * need to do any remapping, just cast the cookie
2732 * directly.
2733 */
2734 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2735 }
2736
2737 return 0;
2738}
2739
2740static void sci_release_port(struct uart_port *port)
2741{
2742 struct sci_port *sport = to_sci_port(port);
2743
2744 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2745 iounmap(port->membase);
2746 port->membase = NULL;
2747 }
2748
2749 release_mem_region(port->mapbase, sport->reg_size);
2750}
2751
2752static int sci_request_port(struct uart_port *port)
2753{
2754 struct resource *res;
2755 struct sci_port *sport = to_sci_port(port);
2756 int ret;
2757
2758 res = request_mem_region(port->mapbase, sport->reg_size,
2759 dev_name(port->dev));
2760 if (unlikely(res == NULL)) {
2761 dev_err(port->dev, "request_mem_region failed.");
2762 return -EBUSY;
2763 }
2764
2765 ret = sci_remap_port(port);
2766 if (unlikely(ret != 0)) {
2767 release_resource(res);
2768 return ret;
2769 }
2770
2771 return 0;
2772}
2773
2774static void sci_config_port(struct uart_port *port, int flags)
2775{
2776 if (flags & UART_CONFIG_TYPE) {
2777 struct sci_port *sport = to_sci_port(port);
2778
2779 port->type = sport->cfg->type;
2780 sci_request_port(port);
2781 }
2782}
2783
2784static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2785{
2786 if (ser->baud_base < 2400)
2787 /* No paper tape reader for Mitch.. */
2788 return -EINVAL;
2789
2790 return 0;
2791}
2792
2793static const struct uart_ops sci_uart_ops = {
2794 .tx_empty = sci_tx_empty,
2795 .set_mctrl = sci_set_mctrl,
2796 .get_mctrl = sci_get_mctrl,
2797 .start_tx = sci_start_tx,
2798 .stop_tx = sci_stop_tx,
2799 .stop_rx = sci_stop_rx,
2800 .enable_ms = sci_enable_ms,
2801 .break_ctl = sci_break_ctl,
2802 .startup = sci_startup,
2803 .shutdown = sci_shutdown,
2804 .flush_buffer = sci_flush_buffer,
2805 .set_termios = sci_set_termios,
2806 .pm = sci_pm,
2807 .type = sci_type,
2808 .release_port = sci_release_port,
2809 .request_port = sci_request_port,
2810 .config_port = sci_config_port,
2811 .verify_port = sci_verify_port,
2812#ifdef CONFIG_CONSOLE_POLL
2813 .poll_get_char = sci_poll_get_char,
2814 .poll_put_char = sci_poll_put_char,
2815#endif
2816};
2817
2818static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2819{
2820 const char *clk_names[] = {
2821 [SCI_FCK] = "fck",
2822 [SCI_SCK] = "sck",
2823 [SCI_BRG_INT] = "brg_int",
2824 [SCI_SCIF_CLK] = "scif_clk",
2825 };
2826 struct clk *clk;
2827 unsigned int i;
2828
2829 if (sci_port->cfg->type == PORT_HSCIF)
2830 clk_names[SCI_SCK] = "hsck";
2831
2832 for (i = 0; i < SCI_NUM_CLKS; i++) {
2833 clk = devm_clk_get_optional(dev, clk_names[i]);
2834 if (IS_ERR(clk))
2835 return PTR_ERR(clk);
2836
2837 if (!clk && i == SCI_FCK) {
2838 /*
2839 * Not all SH platforms declare a clock lookup entry
2840 * for SCI devices, in which case we need to get the
2841 * global "peripheral_clk" clock.
2842 */
2843 clk = devm_clk_get(dev, "peripheral_clk");
2844 if (IS_ERR(clk))
2845 return dev_err_probe(dev, PTR_ERR(clk),
2846 "failed to get %s\n",
2847 clk_names[i]);
2848 }
2849
2850 if (!clk)
2851 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2852 else
2853 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2854 clk, clk_get_rate(clk));
2855 sci_port->clks[i] = clk;
2856 }
2857 return 0;
2858}
2859
2860static const struct sci_port_params *
2861sci_probe_regmap(const struct plat_sci_port *cfg)
2862{
2863 unsigned int regtype;
2864
2865 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2866 return &sci_port_params[cfg->regtype];
2867
2868 switch (cfg->type) {
2869 case PORT_SCI:
2870 regtype = SCIx_SCI_REGTYPE;
2871 break;
2872 case PORT_IRDA:
2873 regtype = SCIx_IRDA_REGTYPE;
2874 break;
2875 case PORT_SCIFA:
2876 regtype = SCIx_SCIFA_REGTYPE;
2877 break;
2878 case PORT_SCIFB:
2879 regtype = SCIx_SCIFB_REGTYPE;
2880 break;
2881 case PORT_SCIF:
2882 /*
2883 * The SH-4 is a bit of a misnomer here, although that's
2884 * where this particular port layout originated. This
2885 * configuration (or some slight variation thereof)
2886 * remains the dominant model for all SCIFs.
2887 */
2888 regtype = SCIx_SH4_SCIF_REGTYPE;
2889 break;
2890 case PORT_HSCIF:
2891 regtype = SCIx_HSCIF_REGTYPE;
2892 break;
2893 default:
2894 pr_err("Can't probe register map for given port\n");
2895 return NULL;
2896 }
2897
2898 return &sci_port_params[regtype];
2899}
2900
2901static int sci_init_single(struct platform_device *dev,
2902 struct sci_port *sci_port, unsigned int index,
2903 const struct plat_sci_port *p, bool early)
2904{
2905 struct uart_port *port = &sci_port->port;
2906 const struct resource *res;
2907 unsigned int i;
2908 int ret;
2909
2910 sci_port->cfg = p;
2911
2912 port->ops = &sci_uart_ops;
2913 port->iotype = UPIO_MEM;
2914 port->line = index;
2915 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2916
2917 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2918 if (res == NULL)
2919 return -ENOMEM;
2920
2921 port->mapbase = res->start;
2922 sci_port->reg_size = resource_size(res);
2923
2924 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2925 if (i)
2926 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2927 else
2928 sci_port->irqs[i] = platform_get_irq(dev, i);
2929 }
2930
2931 /*
2932 * The fourth interrupt on SCI port is transmit end interrupt, so
2933 * shuffle the interrupts.
2934 */
2935 if (p->type == PORT_SCI)
2936 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
2937
2938 /* The SCI generates several interrupts. They can be muxed together or
2939 * connected to different interrupt lines. In the muxed case only one
2940 * interrupt resource is specified as there is only one interrupt ID.
2941 * In the non-muxed case, up to 6 interrupt signals might be generated
2942 * from the SCI, however those signals might have their own individual
2943 * interrupt ID numbers, or muxed together with another interrupt.
2944 */
2945 if (sci_port->irqs[0] < 0)
2946 return -ENXIO;
2947
2948 if (sci_port->irqs[1] < 0)
2949 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2950 sci_port->irqs[i] = sci_port->irqs[0];
2951
2952 sci_port->params = sci_probe_regmap(p);
2953 if (unlikely(sci_port->params == NULL))
2954 return -EINVAL;
2955
2956 switch (p->type) {
2957 case PORT_SCIFB:
2958 sci_port->rx_trigger = 48;
2959 break;
2960 case PORT_HSCIF:
2961 sci_port->rx_trigger = 64;
2962 break;
2963 case PORT_SCIFA:
2964 sci_port->rx_trigger = 32;
2965 break;
2966 case PORT_SCIF:
2967 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2968 /* RX triggering not implemented for this IP */
2969 sci_port->rx_trigger = 1;
2970 else
2971 sci_port->rx_trigger = 8;
2972 break;
2973 default:
2974 sci_port->rx_trigger = 1;
2975 break;
2976 }
2977
2978 sci_port->rx_fifo_timeout = 0;
2979 sci_port->hscif_tot = 0;
2980
2981 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2982 * match the SoC datasheet, this should be investigated. Let platform
2983 * data override the sampling rate for now.
2984 */
2985 sci_port->sampling_rate_mask = p->sampling_rate
2986 ? SCI_SR(p->sampling_rate)
2987 : sci_port->params->sampling_rate_mask;
2988
2989 if (!early) {
2990 ret = sci_init_clocks(sci_port, &dev->dev);
2991 if (ret < 0)
2992 return ret;
2993
2994 port->dev = &dev->dev;
2995
2996 pm_runtime_enable(&dev->dev);
2997 }
2998
2999 port->type = p->type;
3000 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3001 port->fifosize = sci_port->params->fifosize;
3002
3003 if (port->type == PORT_SCI && !dev->dev.of_node) {
3004 if (sci_port->reg_size >= 0x20)
3005 port->regshift = 2;
3006 else
3007 port->regshift = 1;
3008 }
3009
3010 /*
3011 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3012 * for the multi-IRQ ports, which is where we are primarily
3013 * concerned with the shutdown path synchronization.
3014 *
3015 * For the muxed case there's nothing more to do.
3016 */
3017 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3018 port->irqflags = 0;
3019
3020 port->serial_in = sci_serial_in;
3021 port->serial_out = sci_serial_out;
3022
3023 return 0;
3024}
3025
3026static void sci_cleanup_single(struct sci_port *port)
3027{
3028 pm_runtime_disable(port->port.dev);
3029}
3030
3031#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3032 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3033static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3034{
3035 sci_poll_put_char(port, ch);
3036}
3037
3038/*
3039 * Print a string to the serial port trying not to disturb
3040 * any possible real use of the port...
3041 */
3042static void serial_console_write(struct console *co, const char *s,
3043 unsigned count)
3044{
3045 struct sci_port *sci_port = &sci_ports[co->index];
3046 struct uart_port *port = &sci_port->port;
3047 unsigned short bits, ctrl, ctrl_temp;
3048 unsigned long flags;
3049 int locked = 1;
3050
3051 if (port->sysrq)
3052 locked = 0;
3053 else if (oops_in_progress)
3054 locked = uart_port_trylock_irqsave(port, &flags);
3055 else
3056 uart_port_lock_irqsave(port, &flags);
3057
3058 /* first save SCSCR then disable interrupts, keep clock source */
3059 ctrl = serial_port_in(port, SCSCR);
3060 ctrl_temp = SCSCR_RE | SCSCR_TE |
3061 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3062 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3063 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3064
3065 uart_console_write(port, s, count, serial_console_putchar);
3066
3067 /* wait until fifo is empty and last bit has been transmitted */
3068 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3069 while ((serial_port_in(port, SCxSR) & bits) != bits)
3070 cpu_relax();
3071
3072 /* restore the SCSCR */
3073 serial_port_out(port, SCSCR, ctrl);
3074
3075 if (locked)
3076 uart_port_unlock_irqrestore(port, flags);
3077}
3078
3079static int serial_console_setup(struct console *co, char *options)
3080{
3081 struct sci_port *sci_port;
3082 struct uart_port *port;
3083 int baud = 115200;
3084 int bits = 8;
3085 int parity = 'n';
3086 int flow = 'n';
3087 int ret;
3088
3089 /*
3090 * Refuse to handle any bogus ports.
3091 */
3092 if (co->index < 0 || co->index >= SCI_NPORTS)
3093 return -ENODEV;
3094
3095 sci_port = &sci_ports[co->index];
3096 port = &sci_port->port;
3097
3098 /*
3099 * Refuse to handle uninitialized ports.
3100 */
3101 if (!port->ops)
3102 return -ENODEV;
3103
3104 ret = sci_remap_port(port);
3105 if (unlikely(ret != 0))
3106 return ret;
3107
3108 if (options)
3109 uart_parse_options(options, &baud, &parity, &bits, &flow);
3110
3111 return uart_set_options(port, co, baud, parity, bits, flow);
3112}
3113
3114static struct console serial_console = {
3115 .name = "ttySC",
3116 .device = uart_console_device,
3117 .write = serial_console_write,
3118 .setup = serial_console_setup,
3119 .flags = CON_PRINTBUFFER,
3120 .index = -1,
3121 .data = &sci_uart_driver,
3122};
3123
3124#ifdef CONFIG_SUPERH
3125static char early_serial_buf[32];
3126
3127static int early_serial_console_setup(struct console *co, char *options)
3128{
3129 /*
3130 * This early console is always registered using the earlyprintk=
3131 * parameter, which does not call add_preferred_console(). Thus
3132 * @options is always NULL and the options for this early console
3133 * are passed using a custom buffer.
3134 */
3135 WARN_ON(options);
3136
3137 return serial_console_setup(co, early_serial_buf);
3138}
3139
3140static struct console early_serial_console = {
3141 .name = "early_ttySC",
3142 .write = serial_console_write,
3143 .setup = early_serial_console_setup,
3144 .flags = CON_PRINTBUFFER,
3145 .index = -1,
3146};
3147
3148static int sci_probe_earlyprintk(struct platform_device *pdev)
3149{
3150 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3151
3152 if (early_serial_console.data)
3153 return -EEXIST;
3154
3155 early_serial_console.index = pdev->id;
3156
3157 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3158
3159 if (!strstr(early_serial_buf, "keep"))
3160 early_serial_console.flags |= CON_BOOT;
3161
3162 register_console(&early_serial_console);
3163 return 0;
3164}
3165#endif
3166
3167#define SCI_CONSOLE (&serial_console)
3168
3169#else
3170static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3171{
3172 return -EINVAL;
3173}
3174
3175#define SCI_CONSOLE NULL
3176
3177#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3178
3179static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3180
3181static DEFINE_MUTEX(sci_uart_registration_lock);
3182static struct uart_driver sci_uart_driver = {
3183 .owner = THIS_MODULE,
3184 .driver_name = "sci",
3185 .dev_name = "ttySC",
3186 .major = SCI_MAJOR,
3187 .minor = SCI_MINOR_START,
3188 .nr = SCI_NPORTS,
3189 .cons = SCI_CONSOLE,
3190};
3191
3192static void sci_remove(struct platform_device *dev)
3193{
3194 struct sci_port *port = platform_get_drvdata(dev);
3195 unsigned int type = port->port.type; /* uart_remove_... clears it */
3196
3197 sci_ports_in_use &= ~BIT(port->port.line);
3198 uart_remove_one_port(&sci_uart_driver, &port->port);
3199
3200 sci_cleanup_single(port);
3201
3202 if (port->port.fifosize > 1)
3203 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3204 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3205 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3206}
3207
3208
3209#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3210#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3211#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3212
3213static const struct of_device_id of_sci_match[] __maybe_unused = {
3214 /* SoC-specific types */
3215 {
3216 .compatible = "renesas,scif-r7s72100",
3217 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3218 },
3219 {
3220 .compatible = "renesas,scif-r7s9210",
3221 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3222 },
3223 {
3224 .compatible = "renesas,scif-r9a07g044",
3225 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3226 },
3227 /* Family-specific types */
3228 {
3229 .compatible = "renesas,rcar-gen1-scif",
3230 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3231 }, {
3232 .compatible = "renesas,rcar-gen2-scif",
3233 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3234 }, {
3235 .compatible = "renesas,rcar-gen3-scif",
3236 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3237 }, {
3238 .compatible = "renesas,rcar-gen4-scif",
3239 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3240 },
3241 /* Generic types */
3242 {
3243 .compatible = "renesas,scif",
3244 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3245 }, {
3246 .compatible = "renesas,scifa",
3247 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3248 }, {
3249 .compatible = "renesas,scifb",
3250 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3251 }, {
3252 .compatible = "renesas,hscif",
3253 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3254 }, {
3255 .compatible = "renesas,sci",
3256 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3257 }, {
3258 /* Terminator */
3259 },
3260};
3261MODULE_DEVICE_TABLE(of, of_sci_match);
3262
3263static void sci_reset_control_assert(void *data)
3264{
3265 reset_control_assert(data);
3266}
3267
3268static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3269 unsigned int *dev_id)
3270{
3271 struct device_node *np = pdev->dev.of_node;
3272 struct reset_control *rstc;
3273 struct plat_sci_port *p;
3274 struct sci_port *sp;
3275 const void *data;
3276 int id, ret;
3277
3278 if (!IS_ENABLED(CONFIG_OF) || !np)
3279 return ERR_PTR(-EINVAL);
3280
3281 data = of_device_get_match_data(&pdev->dev);
3282
3283 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3284 if (IS_ERR(rstc))
3285 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3286 "failed to get reset ctrl\n"));
3287
3288 ret = reset_control_deassert(rstc);
3289 if (ret) {
3290 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3291 return ERR_PTR(ret);
3292 }
3293
3294 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3295 if (ret) {
3296 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3297 ret);
3298 return ERR_PTR(ret);
3299 }
3300
3301 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3302 if (!p)
3303 return ERR_PTR(-ENOMEM);
3304
3305 /* Get the line number from the aliases node. */
3306 id = of_alias_get_id(np, "serial");
3307 if (id < 0 && ~sci_ports_in_use)
3308 id = ffz(sci_ports_in_use);
3309 if (id < 0) {
3310 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3311 return ERR_PTR(-EINVAL);
3312 }
3313 if (id >= ARRAY_SIZE(sci_ports)) {
3314 dev_err(&pdev->dev, "serial%d out of range\n", id);
3315 return ERR_PTR(-EINVAL);
3316 }
3317
3318 sp = &sci_ports[id];
3319 *dev_id = id;
3320
3321 p->type = SCI_OF_TYPE(data);
3322 p->regtype = SCI_OF_REGTYPE(data);
3323
3324 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3325
3326 return p;
3327}
3328
3329static int sci_probe_single(struct platform_device *dev,
3330 unsigned int index,
3331 struct plat_sci_port *p,
3332 struct sci_port *sciport)
3333{
3334 int ret;
3335
3336 /* Sanity check */
3337 if (unlikely(index >= SCI_NPORTS)) {
3338 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3339 index+1, SCI_NPORTS);
3340 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3341 return -EINVAL;
3342 }
3343 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3344 if (sci_ports_in_use & BIT(index))
3345 return -EBUSY;
3346
3347 mutex_lock(&sci_uart_registration_lock);
3348 if (!sci_uart_driver.state) {
3349 ret = uart_register_driver(&sci_uart_driver);
3350 if (ret) {
3351 mutex_unlock(&sci_uart_registration_lock);
3352 return ret;
3353 }
3354 }
3355 mutex_unlock(&sci_uart_registration_lock);
3356
3357 ret = sci_init_single(dev, sciport, index, p, false);
3358 if (ret)
3359 return ret;
3360
3361 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3362 if (IS_ERR(sciport->gpios))
3363 return PTR_ERR(sciport->gpios);
3364
3365 if (sciport->has_rtscts) {
3366 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3367 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3368 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3369 return -EINVAL;
3370 }
3371 sciport->port.flags |= UPF_HARD_FLOW;
3372 }
3373
3374 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3375 if (ret) {
3376 sci_cleanup_single(sciport);
3377 return ret;
3378 }
3379
3380 return 0;
3381}
3382
3383static int sci_probe(struct platform_device *dev)
3384{
3385 struct plat_sci_port *p;
3386 struct sci_port *sp;
3387 unsigned int dev_id;
3388 int ret;
3389
3390 /*
3391 * If we've come here via earlyprintk initialization, head off to
3392 * the special early probe. We don't have sufficient device state
3393 * to make it beyond this yet.
3394 */
3395#ifdef CONFIG_SUPERH
3396 if (is_sh_early_platform_device(dev))
3397 return sci_probe_earlyprintk(dev);
3398#endif
3399
3400 if (dev->dev.of_node) {
3401 p = sci_parse_dt(dev, &dev_id);
3402 if (IS_ERR(p))
3403 return PTR_ERR(p);
3404 } else {
3405 p = dev->dev.platform_data;
3406 if (p == NULL) {
3407 dev_err(&dev->dev, "no platform data supplied\n");
3408 return -EINVAL;
3409 }
3410
3411 dev_id = dev->id;
3412 }
3413
3414 sp = &sci_ports[dev_id];
3415 platform_set_drvdata(dev, sp);
3416
3417 ret = sci_probe_single(dev, dev_id, p, sp);
3418 if (ret)
3419 return ret;
3420
3421 if (sp->port.fifosize > 1) {
3422 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3423 if (ret)
3424 return ret;
3425 }
3426 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3427 sp->port.type == PORT_HSCIF) {
3428 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3429 if (ret) {
3430 if (sp->port.fifosize > 1) {
3431 device_remove_file(&dev->dev,
3432 &dev_attr_rx_fifo_trigger);
3433 }
3434 return ret;
3435 }
3436 }
3437
3438#ifdef CONFIG_SH_STANDARD_BIOS
3439 sh_bios_gdb_detach();
3440#endif
3441
3442 sci_ports_in_use |= BIT(dev_id);
3443 return 0;
3444}
3445
3446static __maybe_unused int sci_suspend(struct device *dev)
3447{
3448 struct sci_port *sport = dev_get_drvdata(dev);
3449
3450 if (sport)
3451 uart_suspend_port(&sci_uart_driver, &sport->port);
3452
3453 return 0;
3454}
3455
3456static __maybe_unused int sci_resume(struct device *dev)
3457{
3458 struct sci_port *sport = dev_get_drvdata(dev);
3459
3460 if (sport)
3461 uart_resume_port(&sci_uart_driver, &sport->port);
3462
3463 return 0;
3464}
3465
3466static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3467
3468static struct platform_driver sci_driver = {
3469 .probe = sci_probe,
3470 .remove_new = sci_remove,
3471 .driver = {
3472 .name = "sh-sci",
3473 .pm = &sci_dev_pm_ops,
3474 .of_match_table = of_match_ptr(of_sci_match),
3475 },
3476};
3477
3478static int __init sci_init(void)
3479{
3480 pr_info("%s\n", banner);
3481
3482 return platform_driver_register(&sci_driver);
3483}
3484
3485static void __exit sci_exit(void)
3486{
3487 platform_driver_unregister(&sci_driver);
3488
3489 if (sci_uart_driver.state)
3490 uart_unregister_driver(&sci_uart_driver);
3491}
3492
3493#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3494sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3495 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3496#endif
3497#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3498static struct plat_sci_port port_cfg __initdata;
3499
3500static int __init early_console_setup(struct earlycon_device *device,
3501 int type)
3502{
3503 if (!device->port.membase)
3504 return -ENODEV;
3505
3506 device->port.serial_in = sci_serial_in;
3507 device->port.serial_out = sci_serial_out;
3508 device->port.type = type;
3509 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3510 port_cfg.type = type;
3511 sci_ports[0].cfg = &port_cfg;
3512 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3513 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3514 sci_serial_out(&sci_ports[0].port, SCSCR,
3515 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3516
3517 device->con->write = serial_console_write;
3518 return 0;
3519}
3520static int __init sci_early_console_setup(struct earlycon_device *device,
3521 const char *opt)
3522{
3523 return early_console_setup(device, PORT_SCI);
3524}
3525static int __init scif_early_console_setup(struct earlycon_device *device,
3526 const char *opt)
3527{
3528 return early_console_setup(device, PORT_SCIF);
3529}
3530static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3531 const char *opt)
3532{
3533 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3534 return early_console_setup(device, PORT_SCIF);
3535}
3536
3537static int __init scifa_early_console_setup(struct earlycon_device *device,
3538 const char *opt)
3539{
3540 return early_console_setup(device, PORT_SCIFA);
3541}
3542static int __init scifb_early_console_setup(struct earlycon_device *device,
3543 const char *opt)
3544{
3545 return early_console_setup(device, PORT_SCIFB);
3546}
3547static int __init hscif_early_console_setup(struct earlycon_device *device,
3548 const char *opt)
3549{
3550 return early_console_setup(device, PORT_HSCIF);
3551}
3552
3553OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3554OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3555OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3556OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3557OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3558OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3559OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3560#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3561
3562module_init(sci_init);
3563module_exit(sci_exit);
3564
3565MODULE_LICENSE("GPL");
3566MODULE_ALIAS("platform:sh-sci");
3567MODULE_AUTHOR("Paul Mundt");
3568MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#undef DEBUG
19
20#include <linux/clk.h>
21#include <linux/console.h>
22#include <linux/ctype.h>
23#include <linux/cpufreq.h>
24#include <linux/delay.h>
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
27#include <linux/err.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/ioport.h>
32#include <linux/ktime.h>
33#include <linux/major.h>
34#include <linux/minmax.h>
35#include <linux/module.h>
36#include <linux/mm.h>
37#include <linux/of.h>
38#include <linux/platform_device.h>
39#include <linux/pm_runtime.h>
40#include <linux/reset.h>
41#include <linux/scatterlist.h>
42#include <linux/serial.h>
43#include <linux/serial_sci.h>
44#include <linux/sh_dma.h>
45#include <linux/slab.h>
46#include <linux/string.h>
47#include <linux/sysrq.h>
48#include <linux/timer.h>
49#include <linux/tty.h>
50#include <linux/tty_flip.h>
51
52#ifdef CONFIG_SUPERH
53#include <asm/sh_bios.h>
54#include <asm/platform_early.h>
55#endif
56
57#include "serial_mctrl_gpio.h"
58#include "sh-sci.h"
59
60/* Offsets into the sci_port->irqs array */
61enum {
62 SCIx_ERI_IRQ,
63 SCIx_RXI_IRQ,
64 SCIx_TXI_IRQ,
65 SCIx_BRI_IRQ,
66 SCIx_DRI_IRQ,
67 SCIx_TEI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85};
86
87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103struct plat_sci_reg {
104 u8 offset, size;
105};
106
107struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
115};
116
117struct sci_port {
118 struct uart_port port;
119
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
126
127 /* Clocks */
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
130
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
133
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136
137#ifdef CONFIG_SERIAL_SH_SCI_DMA
138 struct dma_chan *chan_tx_saved;
139 struct dma_chan *chan_rx_saved;
140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
145 struct scatterlist sg_rx[2];
146 void *rx_buf[2];
147 size_t buf_len_rx;
148 struct work_struct work_tx;
149 struct hrtimer rx_timer;
150 unsigned int rx_timeout; /* microseconds */
151#endif
152 unsigned int rx_frame;
153 int rx_trigger;
154 struct timer_list rx_fifo_timer;
155 int rx_fifo_timeout;
156 u16 hscif_tot;
157
158 bool has_rtscts;
159 bool autorts;
160 bool tx_occurred;
161};
162
163#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
164
165static struct sci_port sci_ports[SCI_NPORTS];
166static unsigned long sci_ports_in_use;
167static struct uart_driver sci_uart_driver;
168static bool sci_uart_earlycon;
169static bool sci_uart_earlycon_dev_probing;
170
171static inline struct sci_port *
172to_sci_port(struct uart_port *uart)
173{
174 return container_of(uart, struct sci_port, port);
175}
176
177static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
178 /*
179 * Common SCI definitions, dependent on the port's regshift
180 * value.
181 */
182 [SCIx_SCI_REGTYPE] = {
183 .regs = {
184 [SCSMR] = { 0x00, 8 },
185 [SCBRR] = { 0x01, 8 },
186 [SCSCR] = { 0x02, 8 },
187 [SCxTDR] = { 0x03, 8 },
188 [SCxSR] = { 0x04, 8 },
189 [SCxRDR] = { 0x05, 8 },
190 },
191 .fifosize = 1,
192 .overrun_reg = SCxSR,
193 .overrun_mask = SCI_ORER,
194 .sampling_rate_mask = SCI_SR(32),
195 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
196 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
197 },
198
199 /*
200 * Common definitions for legacy IrDA ports.
201 */
202 [SCIx_IRDA_REGTYPE] = {
203 .regs = {
204 [SCSMR] = { 0x00, 8 },
205 [SCBRR] = { 0x02, 8 },
206 [SCSCR] = { 0x04, 8 },
207 [SCxTDR] = { 0x06, 8 },
208 [SCxSR] = { 0x08, 16 },
209 [SCxRDR] = { 0x0a, 8 },
210 [SCFCR] = { 0x0c, 8 },
211 [SCFDR] = { 0x0e, 16 },
212 },
213 .fifosize = 1,
214 .overrun_reg = SCxSR,
215 .overrun_mask = SCI_ORER,
216 .sampling_rate_mask = SCI_SR(32),
217 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
218 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
219 },
220
221 /*
222 * Common SCIFA definitions.
223 */
224 [SCIx_SCIFA_REGTYPE] = {
225 .regs = {
226 [SCSMR] = { 0x00, 16 },
227 [SCBRR] = { 0x04, 8 },
228 [SCSCR] = { 0x08, 16 },
229 [SCxTDR] = { 0x20, 8 },
230 [SCxSR] = { 0x14, 16 },
231 [SCxRDR] = { 0x24, 8 },
232 [SCFCR] = { 0x18, 16 },
233 [SCFDR] = { 0x1c, 16 },
234 [SCPCR] = { 0x30, 16 },
235 [SCPDR] = { 0x34, 16 },
236 },
237 .fifosize = 64,
238 .overrun_reg = SCxSR,
239 .overrun_mask = SCIFA_ORER,
240 .sampling_rate_mask = SCI_SR_SCIFAB,
241 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
242 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
243 },
244
245 /*
246 * Common SCIFB definitions.
247 */
248 [SCIx_SCIFB_REGTYPE] = {
249 .regs = {
250 [SCSMR] = { 0x00, 16 },
251 [SCBRR] = { 0x04, 8 },
252 [SCSCR] = { 0x08, 16 },
253 [SCxTDR] = { 0x40, 8 },
254 [SCxSR] = { 0x14, 16 },
255 [SCxRDR] = { 0x60, 8 },
256 [SCFCR] = { 0x18, 16 },
257 [SCTFDR] = { 0x38, 16 },
258 [SCRFDR] = { 0x3c, 16 },
259 [SCPCR] = { 0x30, 16 },
260 [SCPDR] = { 0x34, 16 },
261 },
262 .fifosize = 256,
263 .overrun_reg = SCxSR,
264 .overrun_mask = SCIFA_ORER,
265 .sampling_rate_mask = SCI_SR_SCIFAB,
266 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
267 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
268 },
269
270 /*
271 * Common SH-2(A) SCIF definitions for ports with FIFO data
272 * count registers.
273 */
274 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
275 .regs = {
276 [SCSMR] = { 0x00, 16 },
277 [SCBRR] = { 0x04, 8 },
278 [SCSCR] = { 0x08, 16 },
279 [SCxTDR] = { 0x0c, 8 },
280 [SCxSR] = { 0x10, 16 },
281 [SCxRDR] = { 0x14, 8 },
282 [SCFCR] = { 0x18, 16 },
283 [SCFDR] = { 0x1c, 16 },
284 [SCSPTR] = { 0x20, 16 },
285 [SCLSR] = { 0x24, 16 },
286 },
287 .fifosize = 16,
288 .overrun_reg = SCLSR,
289 .overrun_mask = SCLSR_ORER,
290 .sampling_rate_mask = SCI_SR(32),
291 .error_mask = SCIF_DEFAULT_ERROR_MASK,
292 .error_clear = SCIF_ERROR_CLEAR,
293 },
294
295 /*
296 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
297 * It looks like a normal SCIF with FIFO data, but with a
298 * compressed address space. Also, the break out of interrupts
299 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
300 */
301 [SCIx_RZ_SCIFA_REGTYPE] = {
302 .regs = {
303 [SCSMR] = { 0x00, 16 },
304 [SCBRR] = { 0x02, 8 },
305 [SCSCR] = { 0x04, 16 },
306 [SCxTDR] = { 0x06, 8 },
307 [SCxSR] = { 0x08, 16 },
308 [SCxRDR] = { 0x0A, 8 },
309 [SCFCR] = { 0x0C, 16 },
310 [SCFDR] = { 0x0E, 16 },
311 [SCSPTR] = { 0x10, 16 },
312 [SCLSR] = { 0x12, 16 },
313 [SEMR] = { 0x14, 8 },
314 },
315 .fifosize = 16,
316 .overrun_reg = SCLSR,
317 .overrun_mask = SCLSR_ORER,
318 .sampling_rate_mask = SCI_SR(32),
319 .error_mask = SCIF_DEFAULT_ERROR_MASK,
320 .error_clear = SCIF_ERROR_CLEAR,
321 },
322
323 /*
324 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC
325 * with below differences,
326 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
327 * TEI-DRI, RXI-EDGE and TXI-EDGE.
328 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
329 * - SCFCR register does not have SCFCR_MCE bit.
330 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
331 */
332 [SCIx_RZV2H_SCIF_REGTYPE] = {
333 .regs = {
334 [SCSMR] = { 0x00, 16 },
335 [SCBRR] = { 0x02, 8 },
336 [SCSCR] = { 0x04, 16 },
337 [SCxTDR] = { 0x06, 8 },
338 [SCxSR] = { 0x08, 16 },
339 [SCxRDR] = { 0x0a, 8 },
340 [SCFCR] = { 0x0c, 16 },
341 [SCFDR] = { 0x0e, 16 },
342 [SCSPTR] = { 0x10, 16 },
343 [SCLSR] = { 0x12, 16 },
344 [SEMR] = { 0x14, 8 },
345 },
346 .fifosize = 16,
347 .overrun_reg = SCLSR,
348 .overrun_mask = SCLSR_ORER,
349 .sampling_rate_mask = SCI_SR(32),
350 .error_mask = SCIF_DEFAULT_ERROR_MASK,
351 .error_clear = SCIF_ERROR_CLEAR,
352 },
353
354 /*
355 * Common SH-3 SCIF definitions.
356 */
357 [SCIx_SH3_SCIF_REGTYPE] = {
358 .regs = {
359 [SCSMR] = { 0x00, 8 },
360 [SCBRR] = { 0x02, 8 },
361 [SCSCR] = { 0x04, 8 },
362 [SCxTDR] = { 0x06, 8 },
363 [SCxSR] = { 0x08, 16 },
364 [SCxRDR] = { 0x0a, 8 },
365 [SCFCR] = { 0x0c, 8 },
366 [SCFDR] = { 0x0e, 16 },
367 },
368 .fifosize = 16,
369 .overrun_reg = SCLSR,
370 .overrun_mask = SCLSR_ORER,
371 .sampling_rate_mask = SCI_SR(32),
372 .error_mask = SCIF_DEFAULT_ERROR_MASK,
373 .error_clear = SCIF_ERROR_CLEAR,
374 },
375
376 /*
377 * Common SH-4(A) SCIF(B) definitions.
378 */
379 [SCIx_SH4_SCIF_REGTYPE] = {
380 .regs = {
381 [SCSMR] = { 0x00, 16 },
382 [SCBRR] = { 0x04, 8 },
383 [SCSCR] = { 0x08, 16 },
384 [SCxTDR] = { 0x0c, 8 },
385 [SCxSR] = { 0x10, 16 },
386 [SCxRDR] = { 0x14, 8 },
387 [SCFCR] = { 0x18, 16 },
388 [SCFDR] = { 0x1c, 16 },
389 [SCSPTR] = { 0x20, 16 },
390 [SCLSR] = { 0x24, 16 },
391 },
392 .fifosize = 16,
393 .overrun_reg = SCLSR,
394 .overrun_mask = SCLSR_ORER,
395 .sampling_rate_mask = SCI_SR(32),
396 .error_mask = SCIF_DEFAULT_ERROR_MASK,
397 .error_clear = SCIF_ERROR_CLEAR,
398 },
399
400 /*
401 * Common SCIF definitions for ports with a Baud Rate Generator for
402 * External Clock (BRG).
403 */
404 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
405 .regs = {
406 [SCSMR] = { 0x00, 16 },
407 [SCBRR] = { 0x04, 8 },
408 [SCSCR] = { 0x08, 16 },
409 [SCxTDR] = { 0x0c, 8 },
410 [SCxSR] = { 0x10, 16 },
411 [SCxRDR] = { 0x14, 8 },
412 [SCFCR] = { 0x18, 16 },
413 [SCFDR] = { 0x1c, 16 },
414 [SCSPTR] = { 0x20, 16 },
415 [SCLSR] = { 0x24, 16 },
416 [SCDL] = { 0x30, 16 },
417 [SCCKS] = { 0x34, 16 },
418 },
419 .fifosize = 16,
420 .overrun_reg = SCLSR,
421 .overrun_mask = SCLSR_ORER,
422 .sampling_rate_mask = SCI_SR(32),
423 .error_mask = SCIF_DEFAULT_ERROR_MASK,
424 .error_clear = SCIF_ERROR_CLEAR,
425 },
426
427 /*
428 * Common HSCIF definitions.
429 */
430 [SCIx_HSCIF_REGTYPE] = {
431 .regs = {
432 [SCSMR] = { 0x00, 16 },
433 [SCBRR] = { 0x04, 8 },
434 [SCSCR] = { 0x08, 16 },
435 [SCxTDR] = { 0x0c, 8 },
436 [SCxSR] = { 0x10, 16 },
437 [SCxRDR] = { 0x14, 8 },
438 [SCFCR] = { 0x18, 16 },
439 [SCFDR] = { 0x1c, 16 },
440 [SCSPTR] = { 0x20, 16 },
441 [SCLSR] = { 0x24, 16 },
442 [HSSRR] = { 0x40, 16 },
443 [SCDL] = { 0x30, 16 },
444 [SCCKS] = { 0x34, 16 },
445 [HSRTRGR] = { 0x54, 16 },
446 [HSTTRGR] = { 0x58, 16 },
447 },
448 .fifosize = 128,
449 .overrun_reg = SCLSR,
450 .overrun_mask = SCLSR_ORER,
451 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
452 .error_mask = SCIF_DEFAULT_ERROR_MASK,
453 .error_clear = SCIF_ERROR_CLEAR,
454 },
455
456 /*
457 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
458 * register.
459 */
460 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
461 .regs = {
462 [SCSMR] = { 0x00, 16 },
463 [SCBRR] = { 0x04, 8 },
464 [SCSCR] = { 0x08, 16 },
465 [SCxTDR] = { 0x0c, 8 },
466 [SCxSR] = { 0x10, 16 },
467 [SCxRDR] = { 0x14, 8 },
468 [SCFCR] = { 0x18, 16 },
469 [SCFDR] = { 0x1c, 16 },
470 [SCLSR] = { 0x24, 16 },
471 },
472 .fifosize = 16,
473 .overrun_reg = SCLSR,
474 .overrun_mask = SCLSR_ORER,
475 .sampling_rate_mask = SCI_SR(32),
476 .error_mask = SCIF_DEFAULT_ERROR_MASK,
477 .error_clear = SCIF_ERROR_CLEAR,
478 },
479
480 /*
481 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
482 * count registers.
483 */
484 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
485 .regs = {
486 [SCSMR] = { 0x00, 16 },
487 [SCBRR] = { 0x04, 8 },
488 [SCSCR] = { 0x08, 16 },
489 [SCxTDR] = { 0x0c, 8 },
490 [SCxSR] = { 0x10, 16 },
491 [SCxRDR] = { 0x14, 8 },
492 [SCFCR] = { 0x18, 16 },
493 [SCFDR] = { 0x1c, 16 },
494 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
495 [SCRFDR] = { 0x20, 16 },
496 [SCSPTR] = { 0x24, 16 },
497 [SCLSR] = { 0x28, 16 },
498 },
499 .fifosize = 16,
500 .overrun_reg = SCLSR,
501 .overrun_mask = SCLSR_ORER,
502 .sampling_rate_mask = SCI_SR(32),
503 .error_mask = SCIF_DEFAULT_ERROR_MASK,
504 .error_clear = SCIF_ERROR_CLEAR,
505 },
506
507 /*
508 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
509 * registers.
510 */
511 [SCIx_SH7705_SCIF_REGTYPE] = {
512 .regs = {
513 [SCSMR] = { 0x00, 16 },
514 [SCBRR] = { 0x04, 8 },
515 [SCSCR] = { 0x08, 16 },
516 [SCxTDR] = { 0x20, 8 },
517 [SCxSR] = { 0x14, 16 },
518 [SCxRDR] = { 0x24, 8 },
519 [SCFCR] = { 0x18, 16 },
520 [SCFDR] = { 0x1c, 16 },
521 },
522 .fifosize = 64,
523 .overrun_reg = SCxSR,
524 .overrun_mask = SCIFA_ORER,
525 .sampling_rate_mask = SCI_SR(16),
526 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
527 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
528 },
529};
530
531#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
532
533/*
534 * The "offset" here is rather misleading, in that it refers to an enum
535 * value relative to the port mapping rather than the fixed offset
536 * itself, which needs to be manually retrieved from the platform's
537 * register map for the given port.
538 */
539static unsigned int sci_serial_in(struct uart_port *p, int offset)
540{
541 const struct plat_sci_reg *reg = sci_getreg(p, offset);
542
543 if (reg->size == 8)
544 return ioread8(p->membase + (reg->offset << p->regshift));
545 else if (reg->size == 16)
546 return ioread16(p->membase + (reg->offset << p->regshift));
547 else
548 WARN(1, "Invalid register access\n");
549
550 return 0;
551}
552
553static void sci_serial_out(struct uart_port *p, int offset, int value)
554{
555 const struct plat_sci_reg *reg = sci_getreg(p, offset);
556
557 if (reg->size == 8)
558 iowrite8(value, p->membase + (reg->offset << p->regshift));
559 else if (reg->size == 16)
560 iowrite16(value, p->membase + (reg->offset << p->regshift));
561 else
562 WARN(1, "Invalid register access\n");
563}
564
565static void sci_port_enable(struct sci_port *sci_port)
566{
567 unsigned int i;
568
569 if (!sci_port->port.dev)
570 return;
571
572 pm_runtime_get_sync(sci_port->port.dev);
573
574 for (i = 0; i < SCI_NUM_CLKS; i++) {
575 clk_prepare_enable(sci_port->clks[i]);
576 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
577 }
578 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
579}
580
581static void sci_port_disable(struct sci_port *sci_port)
582{
583 unsigned int i;
584
585 if (!sci_port->port.dev)
586 return;
587
588 for (i = SCI_NUM_CLKS; i-- > 0; )
589 clk_disable_unprepare(sci_port->clks[i]);
590
591 pm_runtime_put_sync(sci_port->port.dev);
592}
593
594static inline unsigned long port_rx_irq_mask(struct uart_port *port)
595{
596 /*
597 * Not all ports (such as SCIFA) will support REIE. Rather than
598 * special-casing the port type, we check the port initialization
599 * IRQ enable mask to see whether the IRQ is desired at all. If
600 * it's unset, it's logically inferred that there's no point in
601 * testing for it.
602 */
603 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
604}
605
606static void sci_start_tx(struct uart_port *port)
607{
608 struct sci_port *s = to_sci_port(port);
609 unsigned short ctrl;
610
611#ifdef CONFIG_SERIAL_SH_SCI_DMA
612 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
613 u16 new, scr = sci_serial_in(port, SCSCR);
614 if (s->chan_tx)
615 new = scr | SCSCR_TDRQE;
616 else
617 new = scr & ~SCSCR_TDRQE;
618 if (new != scr)
619 sci_serial_out(port, SCSCR, new);
620 }
621
622 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
623 dma_submit_error(s->cookie_tx)) {
624 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
625 /* Switch irq from SCIF to DMA */
626 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
627
628 s->cookie_tx = 0;
629 schedule_work(&s->work_tx);
630 }
631#endif
632
633 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
634 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
635 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
636 ctrl = sci_serial_in(port, SCSCR);
637
638 /*
639 * For SCI, TE (transmit enable) must be set after setting TIE
640 * (transmit interrupt enable) or in the same instruction to start
641 * the transmit process.
642 */
643 if (port->type == PORT_SCI)
644 ctrl |= SCSCR_TE;
645
646 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
647 }
648}
649
650static void sci_stop_tx(struct uart_port *port)
651{
652 unsigned short ctrl;
653
654 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
655 ctrl = sci_serial_in(port, SCSCR);
656
657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
658 ctrl &= ~SCSCR_TDRQE;
659
660 ctrl &= ~SCSCR_TIE;
661
662 sci_serial_out(port, SCSCR, ctrl);
663
664#ifdef CONFIG_SERIAL_SH_SCI_DMA
665 if (to_sci_port(port)->chan_tx &&
666 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
667 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
668 to_sci_port(port)->cookie_tx = -EINVAL;
669 }
670#endif
671}
672
673static void sci_start_rx(struct uart_port *port)
674{
675 unsigned short ctrl;
676
677 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
678
679 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
680 ctrl &= ~SCSCR_RDRQE;
681
682 sci_serial_out(port, SCSCR, ctrl);
683}
684
685static void sci_stop_rx(struct uart_port *port)
686{
687 unsigned short ctrl;
688
689 ctrl = sci_serial_in(port, SCSCR);
690
691 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
692 ctrl &= ~SCSCR_RDRQE;
693
694 ctrl &= ~port_rx_irq_mask(port);
695
696 sci_serial_out(port, SCSCR, ctrl);
697}
698
699static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
700{
701 if (port->type == PORT_SCI) {
702 /* Just store the mask */
703 sci_serial_out(port, SCxSR, mask);
704 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
705 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
706 /* Only clear the status bits we want to clear */
707 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
708 } else {
709 /* Store the mask, clear parity/framing errors */
710 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
711 }
712}
713
714#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
715 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
716
717#ifdef CONFIG_CONSOLE_POLL
718static int sci_poll_get_char(struct uart_port *port)
719{
720 unsigned short status;
721 int c;
722
723 do {
724 status = sci_serial_in(port, SCxSR);
725 if (status & SCxSR_ERRORS(port)) {
726 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
727 continue;
728 }
729 break;
730 } while (1);
731
732 if (!(status & SCxSR_RDxF(port)))
733 return NO_POLL_CHAR;
734
735 c = sci_serial_in(port, SCxRDR);
736
737 /* Dummy read */
738 sci_serial_in(port, SCxSR);
739 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
740
741 return c;
742}
743#endif
744
745static void sci_poll_put_char(struct uart_port *port, unsigned char c)
746{
747 unsigned short status;
748
749 do {
750 status = sci_serial_in(port, SCxSR);
751 } while (!(status & SCxSR_TDxE(port)));
752
753 sci_serial_out(port, SCxTDR, c);
754 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
755}
756#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
757 CONFIG_SERIAL_SH_SCI_EARLYCON */
758
759static void sci_init_pins(struct uart_port *port, unsigned int cflag)
760{
761 struct sci_port *s = to_sci_port(port);
762
763 /*
764 * Use port-specific handler if provided.
765 */
766 if (s->cfg->ops && s->cfg->ops->init_pins) {
767 s->cfg->ops->init_pins(port, cflag);
768 return;
769 }
770
771 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
772 u16 data = sci_serial_in(port, SCPDR);
773 u16 ctrl = sci_serial_in(port, SCPCR);
774
775 /* Enable RXD and TXD pin functions */
776 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
777 if (to_sci_port(port)->has_rtscts) {
778 /* RTS# is output, active low, unless autorts */
779 if (!(port->mctrl & TIOCM_RTS)) {
780 ctrl |= SCPCR_RTSC;
781 data |= SCPDR_RTSD;
782 } else if (!s->autorts) {
783 ctrl |= SCPCR_RTSC;
784 data &= ~SCPDR_RTSD;
785 } else {
786 /* Enable RTS# pin function */
787 ctrl &= ~SCPCR_RTSC;
788 }
789 /* Enable CTS# pin function */
790 ctrl &= ~SCPCR_CTSC;
791 }
792 sci_serial_out(port, SCPDR, data);
793 sci_serial_out(port, SCPCR, ctrl);
794 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
795 u16 status = sci_serial_in(port, SCSPTR);
796
797 /* RTS# is always output; and active low, unless autorts */
798 status |= SCSPTR_RTSIO;
799 if (!(port->mctrl & TIOCM_RTS))
800 status |= SCSPTR_RTSDT;
801 else if (!s->autorts)
802 status &= ~SCSPTR_RTSDT;
803 /* CTS# and SCK are inputs */
804 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
805 sci_serial_out(port, SCSPTR, status);
806 }
807}
808
809static int sci_txfill(struct uart_port *port)
810{
811 struct sci_port *s = to_sci_port(port);
812 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
813 const struct plat_sci_reg *reg;
814
815 reg = sci_getreg(port, SCTFDR);
816 if (reg->size)
817 return sci_serial_in(port, SCTFDR) & fifo_mask;
818
819 reg = sci_getreg(port, SCFDR);
820 if (reg->size)
821 return sci_serial_in(port, SCFDR) >> 8;
822
823 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
824}
825
826static int sci_txroom(struct uart_port *port)
827{
828 return port->fifosize - sci_txfill(port);
829}
830
831static int sci_rxfill(struct uart_port *port)
832{
833 struct sci_port *s = to_sci_port(port);
834 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
835 const struct plat_sci_reg *reg;
836
837 reg = sci_getreg(port, SCRFDR);
838 if (reg->size)
839 return sci_serial_in(port, SCRFDR) & fifo_mask;
840
841 reg = sci_getreg(port, SCFDR);
842 if (reg->size)
843 return sci_serial_in(port, SCFDR) & fifo_mask;
844
845 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
846}
847
848/* ********************************************************************** *
849 * the interrupt related routines *
850 * ********************************************************************** */
851
852static void sci_transmit_chars(struct uart_port *port)
853{
854 struct tty_port *tport = &port->state->port;
855 unsigned int stopped = uart_tx_stopped(port);
856 struct sci_port *s = to_sci_port(port);
857 unsigned short status;
858 unsigned short ctrl;
859 int count;
860
861 status = sci_serial_in(port, SCxSR);
862 if (!(status & SCxSR_TDxE(port))) {
863 ctrl = sci_serial_in(port, SCSCR);
864 if (kfifo_is_empty(&tport->xmit_fifo))
865 ctrl &= ~SCSCR_TIE;
866 else
867 ctrl |= SCSCR_TIE;
868 sci_serial_out(port, SCSCR, ctrl);
869 return;
870 }
871
872 count = sci_txroom(port);
873
874 do {
875 unsigned char c;
876
877 if (port->x_char) {
878 c = port->x_char;
879 port->x_char = 0;
880 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
881 if (port->type == PORT_SCI &&
882 kfifo_is_empty(&tport->xmit_fifo)) {
883 ctrl = sci_serial_in(port, SCSCR);
884 ctrl &= ~SCSCR_TE;
885 sci_serial_out(port, SCSCR, ctrl);
886 return;
887 }
888 break;
889 }
890
891 sci_serial_out(port, SCxTDR, c);
892 s->tx_occurred = true;
893
894 port->icount.tx++;
895 } while (--count > 0);
896
897 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
898
899 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
900 uart_write_wakeup(port);
901 if (kfifo_is_empty(&tport->xmit_fifo)) {
902 if (port->type == PORT_SCI) {
903 ctrl = sci_serial_in(port, SCSCR);
904 ctrl &= ~SCSCR_TIE;
905 ctrl |= SCSCR_TEIE;
906 sci_serial_out(port, SCSCR, ctrl);
907 }
908
909 sci_stop_tx(port);
910 }
911}
912
913static void sci_receive_chars(struct uart_port *port)
914{
915 struct tty_port *tport = &port->state->port;
916 int i, count, copied = 0;
917 unsigned short status;
918 unsigned char flag;
919
920 status = sci_serial_in(port, SCxSR);
921 if (!(status & SCxSR_RDxF(port)))
922 return;
923
924 while (1) {
925 /* Don't copy more bytes than there is room for in the buffer */
926 count = tty_buffer_request_room(tport, sci_rxfill(port));
927
928 /* If for any reason we can't copy more data, we're done! */
929 if (count == 0)
930 break;
931
932 if (port->type == PORT_SCI) {
933 char c = sci_serial_in(port, SCxRDR);
934 if (uart_handle_sysrq_char(port, c))
935 count = 0;
936 else
937 tty_insert_flip_char(tport, c, TTY_NORMAL);
938 } else {
939 for (i = 0; i < count; i++) {
940 char c;
941
942 if (port->type == PORT_SCIF ||
943 port->type == PORT_HSCIF) {
944 status = sci_serial_in(port, SCxSR);
945 c = sci_serial_in(port, SCxRDR);
946 } else {
947 c = sci_serial_in(port, SCxRDR);
948 status = sci_serial_in(port, SCxSR);
949 }
950 if (uart_handle_sysrq_char(port, c)) {
951 count--; i--;
952 continue;
953 }
954
955 /* Store data and status */
956 if (status & SCxSR_FER(port)) {
957 flag = TTY_FRAME;
958 port->icount.frame++;
959 } else if (status & SCxSR_PER(port)) {
960 flag = TTY_PARITY;
961 port->icount.parity++;
962 } else
963 flag = TTY_NORMAL;
964
965 tty_insert_flip_char(tport, c, flag);
966 }
967 }
968
969 sci_serial_in(port, SCxSR); /* dummy read */
970 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
971
972 copied += count;
973 port->icount.rx += count;
974 }
975
976 if (copied) {
977 /* Tell the rest of the system the news. New characters! */
978 tty_flip_buffer_push(tport);
979 } else {
980 /* TTY buffers full; read from RX reg to prevent lockup */
981 sci_serial_in(port, SCxRDR);
982 sci_serial_in(port, SCxSR); /* dummy read */
983 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
984 }
985}
986
987static int sci_handle_errors(struct uart_port *port)
988{
989 int copied = 0;
990 unsigned short status = sci_serial_in(port, SCxSR);
991 struct tty_port *tport = &port->state->port;
992 struct sci_port *s = to_sci_port(port);
993
994 /* Handle overruns */
995 if (status & s->params->overrun_mask) {
996 port->icount.overrun++;
997
998 /* overrun error */
999 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
1000 copied++;
1001 }
1002
1003 if (status & SCxSR_FER(port)) {
1004 /* frame error */
1005 port->icount.frame++;
1006
1007 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1008 copied++;
1009 }
1010
1011 if (status & SCxSR_PER(port)) {
1012 /* parity error */
1013 port->icount.parity++;
1014
1015 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1016 copied++;
1017 }
1018
1019 if (copied)
1020 tty_flip_buffer_push(tport);
1021
1022 return copied;
1023}
1024
1025static int sci_handle_fifo_overrun(struct uart_port *port)
1026{
1027 struct tty_port *tport = &port->state->port;
1028 struct sci_port *s = to_sci_port(port);
1029 const struct plat_sci_reg *reg;
1030 int copied = 0;
1031 u16 status;
1032
1033 reg = sci_getreg(port, s->params->overrun_reg);
1034 if (!reg->size)
1035 return 0;
1036
1037 status = sci_serial_in(port, s->params->overrun_reg);
1038 if (status & s->params->overrun_mask) {
1039 status &= ~s->params->overrun_mask;
1040 sci_serial_out(port, s->params->overrun_reg, status);
1041
1042 port->icount.overrun++;
1043
1044 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1045 tty_flip_buffer_push(tport);
1046 copied++;
1047 }
1048
1049 return copied;
1050}
1051
1052static int sci_handle_breaks(struct uart_port *port)
1053{
1054 int copied = 0;
1055 unsigned short status = sci_serial_in(port, SCxSR);
1056 struct tty_port *tport = &port->state->port;
1057
1058 if (uart_handle_break(port))
1059 return 0;
1060
1061 if (status & SCxSR_BRK(port)) {
1062 port->icount.brk++;
1063
1064 /* Notify of BREAK */
1065 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1066 copied++;
1067 }
1068
1069 if (copied)
1070 tty_flip_buffer_push(tport);
1071
1072 copied += sci_handle_fifo_overrun(port);
1073
1074 return copied;
1075}
1076
1077static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1078{
1079 unsigned int bits;
1080
1081 if (rx_trig >= port->fifosize)
1082 rx_trig = port->fifosize - 1;
1083 if (rx_trig < 1)
1084 rx_trig = 1;
1085
1086 /* HSCIF can be set to an arbitrary level. */
1087 if (sci_getreg(port, HSRTRGR)->size) {
1088 sci_serial_out(port, HSRTRGR, rx_trig);
1089 return rx_trig;
1090 }
1091
1092 switch (port->type) {
1093 case PORT_SCIF:
1094 if (rx_trig < 4) {
1095 bits = 0;
1096 rx_trig = 1;
1097 } else if (rx_trig < 8) {
1098 bits = SCFCR_RTRG0;
1099 rx_trig = 4;
1100 } else if (rx_trig < 14) {
1101 bits = SCFCR_RTRG1;
1102 rx_trig = 8;
1103 } else {
1104 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1105 rx_trig = 14;
1106 }
1107 break;
1108 case PORT_SCIFA:
1109 case PORT_SCIFB:
1110 if (rx_trig < 16) {
1111 bits = 0;
1112 rx_trig = 1;
1113 } else if (rx_trig < 32) {
1114 bits = SCFCR_RTRG0;
1115 rx_trig = 16;
1116 } else if (rx_trig < 48) {
1117 bits = SCFCR_RTRG1;
1118 rx_trig = 32;
1119 } else {
1120 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1121 rx_trig = 48;
1122 }
1123 break;
1124 default:
1125 WARN(1, "unknown FIFO configuration");
1126 return 1;
1127 }
1128
1129 sci_serial_out(port, SCFCR,
1130 (sci_serial_in(port, SCFCR) &
1131 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1132
1133 return rx_trig;
1134}
1135
1136static int scif_rtrg_enabled(struct uart_port *port)
1137{
1138 if (sci_getreg(port, HSRTRGR)->size)
1139 return sci_serial_in(port, HSRTRGR) != 0;
1140 else
1141 return (sci_serial_in(port, SCFCR) &
1142 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1143}
1144
1145static void rx_fifo_timer_fn(struct timer_list *t)
1146{
1147 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1148 struct uart_port *port = &s->port;
1149
1150 dev_dbg(port->dev, "Rx timed out\n");
1151 scif_set_rtrg(port, 1);
1152}
1153
1154static ssize_t rx_fifo_trigger_show(struct device *dev,
1155 struct device_attribute *attr, char *buf)
1156{
1157 struct uart_port *port = dev_get_drvdata(dev);
1158 struct sci_port *sci = to_sci_port(port);
1159
1160 return sprintf(buf, "%d\n", sci->rx_trigger);
1161}
1162
1163static ssize_t rx_fifo_trigger_store(struct device *dev,
1164 struct device_attribute *attr,
1165 const char *buf, size_t count)
1166{
1167 struct uart_port *port = dev_get_drvdata(dev);
1168 struct sci_port *sci = to_sci_port(port);
1169 int ret;
1170 long r;
1171
1172 ret = kstrtol(buf, 0, &r);
1173 if (ret)
1174 return ret;
1175
1176 sci->rx_trigger = scif_set_rtrg(port, r);
1177 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1178 scif_set_rtrg(port, 1);
1179
1180 return count;
1181}
1182
1183static DEVICE_ATTR_RW(rx_fifo_trigger);
1184
1185static ssize_t rx_fifo_timeout_show(struct device *dev,
1186 struct device_attribute *attr,
1187 char *buf)
1188{
1189 struct uart_port *port = dev_get_drvdata(dev);
1190 struct sci_port *sci = to_sci_port(port);
1191 int v;
1192
1193 if (port->type == PORT_HSCIF)
1194 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1195 else
1196 v = sci->rx_fifo_timeout;
1197
1198 return sprintf(buf, "%d\n", v);
1199}
1200
1201static ssize_t rx_fifo_timeout_store(struct device *dev,
1202 struct device_attribute *attr,
1203 const char *buf,
1204 size_t count)
1205{
1206 struct uart_port *port = dev_get_drvdata(dev);
1207 struct sci_port *sci = to_sci_port(port);
1208 int ret;
1209 long r;
1210
1211 ret = kstrtol(buf, 0, &r);
1212 if (ret)
1213 return ret;
1214
1215 if (port->type == PORT_HSCIF) {
1216 if (r < 0 || r > 3)
1217 return -EINVAL;
1218 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1219 } else {
1220 sci->rx_fifo_timeout = r;
1221 scif_set_rtrg(port, 1);
1222 if (r > 0)
1223 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1224 }
1225
1226 return count;
1227}
1228
1229static DEVICE_ATTR_RW(rx_fifo_timeout);
1230
1231
1232#ifdef CONFIG_SERIAL_SH_SCI_DMA
1233static void sci_dma_tx_complete(void *arg)
1234{
1235 struct sci_port *s = arg;
1236 struct uart_port *port = &s->port;
1237 struct tty_port *tport = &port->state->port;
1238 unsigned long flags;
1239
1240 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1241
1242 uart_port_lock_irqsave(port, &flags);
1243
1244 uart_xmit_advance(port, s->tx_dma_len);
1245
1246 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1247 uart_write_wakeup(port);
1248
1249 s->tx_occurred = true;
1250
1251 if (!kfifo_is_empty(&tport->xmit_fifo)) {
1252 s->cookie_tx = 0;
1253 schedule_work(&s->work_tx);
1254 } else {
1255 s->cookie_tx = -EINVAL;
1256 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1257 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1258 u16 ctrl = sci_serial_in(port, SCSCR);
1259 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1260 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1261 /* Switch irq from DMA to SCIF */
1262 dmaengine_pause(s->chan_tx_saved);
1263 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1264 }
1265 }
1266 }
1267
1268 uart_port_unlock_irqrestore(port, flags);
1269}
1270
1271/* Locking: called with port lock held */
1272static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1273{
1274 struct uart_port *port = &s->port;
1275 struct tty_port *tport = &port->state->port;
1276 int copied;
1277
1278 copied = tty_insert_flip_string(tport, buf, count);
1279 if (copied < count)
1280 port->icount.buf_overrun++;
1281
1282 port->icount.rx += copied;
1283
1284 return copied;
1285}
1286
1287static int sci_dma_rx_find_active(struct sci_port *s)
1288{
1289 unsigned int i;
1290
1291 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1292 if (s->active_rx == s->cookie_rx[i])
1293 return i;
1294
1295 return -1;
1296}
1297
1298/* Must only be called with uart_port_lock taken */
1299static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1300{
1301 unsigned int i;
1302
1303 s->chan_rx = NULL;
1304 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1305 s->cookie_rx[i] = -EINVAL;
1306 s->active_rx = 0;
1307}
1308
1309static void sci_dma_rx_release(struct sci_port *s)
1310{
1311 struct dma_chan *chan = s->chan_rx_saved;
1312 struct uart_port *port = &s->port;
1313 unsigned long flags;
1314
1315 uart_port_lock_irqsave(port, &flags);
1316 s->chan_rx_saved = NULL;
1317 sci_dma_rx_chan_invalidate(s);
1318 uart_port_unlock_irqrestore(port, flags);
1319
1320 dmaengine_terminate_sync(chan);
1321 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1322 sg_dma_address(&s->sg_rx[0]));
1323 dma_release_channel(chan);
1324}
1325
1326static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1327{
1328 long sec = usec / 1000000;
1329 long nsec = (usec % 1000000) * 1000;
1330 ktime_t t = ktime_set(sec, nsec);
1331
1332 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1333}
1334
1335static void sci_dma_rx_reenable_irq(struct sci_port *s)
1336{
1337 struct uart_port *port = &s->port;
1338 u16 scr;
1339
1340 /* Direct new serial port interrupts back to CPU */
1341 scr = sci_serial_in(port, SCSCR);
1342 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1343 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1344 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1345 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1346 scif_set_rtrg(port, s->rx_trigger);
1347 else
1348 scr &= ~SCSCR_RDRQE;
1349 }
1350 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1351}
1352
1353static void sci_dma_rx_complete(void *arg)
1354{
1355 struct sci_port *s = arg;
1356 struct dma_chan *chan = s->chan_rx;
1357 struct uart_port *port = &s->port;
1358 struct dma_async_tx_descriptor *desc;
1359 unsigned long flags;
1360 int active, count = 0;
1361
1362 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1363 s->active_rx);
1364
1365 hrtimer_cancel(&s->rx_timer);
1366
1367 uart_port_lock_irqsave(port, &flags);
1368
1369 active = sci_dma_rx_find_active(s);
1370 if (active >= 0)
1371 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1372
1373 if (count)
1374 tty_flip_buffer_push(&port->state->port);
1375
1376 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1377 DMA_DEV_TO_MEM,
1378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1379 if (!desc)
1380 goto fail;
1381
1382 desc->callback = sci_dma_rx_complete;
1383 desc->callback_param = s;
1384 s->cookie_rx[active] = dmaengine_submit(desc);
1385 if (dma_submit_error(s->cookie_rx[active]))
1386 goto fail;
1387
1388 s->active_rx = s->cookie_rx[!active];
1389
1390 dma_async_issue_pending(chan);
1391
1392 uart_port_unlock_irqrestore(port, flags);
1393 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1394 __func__, s->cookie_rx[active], active, s->active_rx);
1395
1396 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1397
1398 return;
1399
1400fail:
1401 /* Switch to PIO */
1402 dmaengine_terminate_async(chan);
1403 sci_dma_rx_chan_invalidate(s);
1404 sci_dma_rx_reenable_irq(s);
1405 uart_port_unlock_irqrestore(port, flags);
1406 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1407}
1408
1409static void sci_dma_tx_release(struct sci_port *s)
1410{
1411 struct dma_chan *chan = s->chan_tx_saved;
1412
1413 cancel_work_sync(&s->work_tx);
1414 s->chan_tx_saved = s->chan_tx = NULL;
1415 s->cookie_tx = -EINVAL;
1416 dmaengine_terminate_sync(chan);
1417 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1418 DMA_TO_DEVICE);
1419 dma_release_channel(chan);
1420}
1421
1422static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1423{
1424 struct dma_chan *chan = s->chan_rx;
1425 struct uart_port *port = &s->port;
1426 unsigned long flags;
1427 int i;
1428
1429 for (i = 0; i < 2; i++) {
1430 struct scatterlist *sg = &s->sg_rx[i];
1431 struct dma_async_tx_descriptor *desc;
1432
1433 desc = dmaengine_prep_slave_sg(chan,
1434 sg, 1, DMA_DEV_TO_MEM,
1435 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1436 if (!desc)
1437 goto fail;
1438
1439 desc->callback = sci_dma_rx_complete;
1440 desc->callback_param = s;
1441 s->cookie_rx[i] = dmaengine_submit(desc);
1442 if (dma_submit_error(s->cookie_rx[i]))
1443 goto fail;
1444
1445 }
1446
1447 s->active_rx = s->cookie_rx[0];
1448
1449 dma_async_issue_pending(chan);
1450 return 0;
1451
1452fail:
1453 /* Switch to PIO */
1454 if (!port_lock_held)
1455 uart_port_lock_irqsave(port, &flags);
1456 if (i)
1457 dmaengine_terminate_async(chan);
1458 sci_dma_rx_chan_invalidate(s);
1459 sci_start_rx(port);
1460 if (!port_lock_held)
1461 uart_port_unlock_irqrestore(port, flags);
1462 return -EAGAIN;
1463}
1464
1465static void sci_dma_tx_work_fn(struct work_struct *work)
1466{
1467 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1468 struct dma_async_tx_descriptor *desc;
1469 struct dma_chan *chan = s->chan_tx;
1470 struct uart_port *port = &s->port;
1471 struct tty_port *tport = &port->state->port;
1472 unsigned long flags;
1473 unsigned int tail;
1474 dma_addr_t buf;
1475
1476 /*
1477 * DMA is idle now.
1478 * Port xmit buffer is already mapped, and it is one page... Just adjust
1479 * offsets and lengths. Since it is a circular buffer, we have to
1480 * transmit till the end, and then the rest. Take the port lock to get a
1481 * consistent xmit buffer state.
1482 */
1483 uart_port_lock_irq(port);
1484 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
1485 UART_XMIT_SIZE);
1486 buf = s->tx_dma_addr + tail;
1487 if (!s->tx_dma_len) {
1488 /* Transmit buffer has been flushed */
1489 uart_port_unlock_irq(port);
1490 return;
1491 }
1492
1493 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1494 DMA_MEM_TO_DEV,
1495 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1496 if (!desc) {
1497 uart_port_unlock_irq(port);
1498 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1499 goto switch_to_pio;
1500 }
1501
1502 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1503 DMA_TO_DEVICE);
1504
1505 desc->callback = sci_dma_tx_complete;
1506 desc->callback_param = s;
1507 s->cookie_tx = dmaengine_submit(desc);
1508 if (dma_submit_error(s->cookie_tx)) {
1509 uart_port_unlock_irq(port);
1510 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1511 goto switch_to_pio;
1512 }
1513
1514 uart_port_unlock_irq(port);
1515 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n",
1516 __func__, tport->xmit_buf, tail, s->cookie_tx);
1517
1518 dma_async_issue_pending(chan);
1519 return;
1520
1521switch_to_pio:
1522 uart_port_lock_irqsave(port, &flags);
1523 s->chan_tx = NULL;
1524 sci_start_tx(port);
1525 uart_port_unlock_irqrestore(port, flags);
1526 return;
1527}
1528
1529static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1530{
1531 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1532 struct dma_chan *chan = s->chan_rx;
1533 struct uart_port *port = &s->port;
1534 struct dma_tx_state state;
1535 enum dma_status status;
1536 unsigned long flags;
1537 unsigned int read;
1538 int active, count;
1539
1540 dev_dbg(port->dev, "DMA Rx timed out\n");
1541
1542 uart_port_lock_irqsave(port, &flags);
1543
1544 active = sci_dma_rx_find_active(s);
1545 if (active < 0) {
1546 uart_port_unlock_irqrestore(port, flags);
1547 return HRTIMER_NORESTART;
1548 }
1549
1550 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1551 if (status == DMA_COMPLETE) {
1552 uart_port_unlock_irqrestore(port, flags);
1553 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1554 s->active_rx, active);
1555
1556 /* Let packet complete handler take care of the packet */
1557 return HRTIMER_NORESTART;
1558 }
1559
1560 dmaengine_pause(chan);
1561
1562 /*
1563 * sometimes DMA transfer doesn't stop even if it is stopped and
1564 * data keeps on coming until transaction is complete so check
1565 * for DMA_COMPLETE again
1566 * Let packet complete handler take care of the packet
1567 */
1568 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1569 if (status == DMA_COMPLETE) {
1570 uart_port_unlock_irqrestore(port, flags);
1571 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1572 return HRTIMER_NORESTART;
1573 }
1574
1575 /* Handle incomplete DMA receive */
1576 dmaengine_terminate_async(s->chan_rx);
1577 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1578
1579 if (read) {
1580 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1581 if (count)
1582 tty_flip_buffer_push(&port->state->port);
1583 }
1584
1585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1586 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1587 sci_dma_rx_submit(s, true);
1588
1589 sci_dma_rx_reenable_irq(s);
1590
1591 uart_port_unlock_irqrestore(port, flags);
1592
1593 return HRTIMER_NORESTART;
1594}
1595
1596static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1597 enum dma_transfer_direction dir)
1598{
1599 struct dma_chan *chan;
1600 struct dma_slave_config cfg;
1601 int ret;
1602
1603 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1604 if (IS_ERR(chan)) {
1605 dev_dbg(port->dev, "dma_request_chan failed\n");
1606 return NULL;
1607 }
1608
1609 memset(&cfg, 0, sizeof(cfg));
1610 cfg.direction = dir;
1611 cfg.dst_addr = port->mapbase +
1612 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1613 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1614 cfg.src_addr = port->mapbase +
1615 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1616 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1617
1618 ret = dmaengine_slave_config(chan, &cfg);
1619 if (ret) {
1620 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1621 dma_release_channel(chan);
1622 return NULL;
1623 }
1624
1625 return chan;
1626}
1627
1628static void sci_request_dma(struct uart_port *port)
1629{
1630 struct sci_port *s = to_sci_port(port);
1631 struct tty_port *tport = &port->state->port;
1632 struct dma_chan *chan;
1633
1634 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1635
1636 /*
1637 * DMA on console may interfere with Kernel log messages which use
1638 * plain putchar(). So, simply don't use it with a console.
1639 */
1640 if (uart_console(port))
1641 return;
1642
1643 if (!port->dev->of_node)
1644 return;
1645
1646 s->cookie_tx = -EINVAL;
1647
1648 /*
1649 * Don't request a dma channel if no channel was specified
1650 * in the device tree.
1651 */
1652 if (!of_property_present(port->dev->of_node, "dmas"))
1653 return;
1654
1655 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1656 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1657 if (chan) {
1658 /* UART circular tx buffer is an aligned page. */
1659 s->tx_dma_addr = dma_map_single(chan->device->dev,
1660 tport->xmit_buf,
1661 UART_XMIT_SIZE,
1662 DMA_TO_DEVICE);
1663 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1664 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1665 dma_release_channel(chan);
1666 } else {
1667 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1668 __func__, UART_XMIT_SIZE,
1669 tport->xmit_buf, &s->tx_dma_addr);
1670
1671 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1672 s->chan_tx_saved = s->chan_tx = chan;
1673 }
1674 }
1675
1676 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1677 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1678 if (chan) {
1679 unsigned int i;
1680 dma_addr_t dma;
1681 void *buf;
1682
1683 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1684 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1685 &dma, GFP_KERNEL);
1686 if (!buf) {
1687 dev_warn(port->dev,
1688 "Failed to allocate Rx dma buffer, using PIO\n");
1689 dma_release_channel(chan);
1690 return;
1691 }
1692
1693 for (i = 0; i < 2; i++) {
1694 struct scatterlist *sg = &s->sg_rx[i];
1695
1696 sg_init_table(sg, 1);
1697 s->rx_buf[i] = buf;
1698 sg_dma_address(sg) = dma;
1699 sg_dma_len(sg) = s->buf_len_rx;
1700
1701 buf += s->buf_len_rx;
1702 dma += s->buf_len_rx;
1703 }
1704
1705 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1706 s->rx_timer.function = sci_dma_rx_timer_fn;
1707
1708 s->chan_rx_saved = s->chan_rx = chan;
1709
1710 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1711 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1712 sci_dma_rx_submit(s, false);
1713 }
1714}
1715
1716static void sci_free_dma(struct uart_port *port)
1717{
1718 struct sci_port *s = to_sci_port(port);
1719
1720 if (s->chan_tx_saved)
1721 sci_dma_tx_release(s);
1722 if (s->chan_rx_saved)
1723 sci_dma_rx_release(s);
1724}
1725
1726static void sci_flush_buffer(struct uart_port *port)
1727{
1728 struct sci_port *s = to_sci_port(port);
1729
1730 /*
1731 * In uart_flush_buffer(), the xmit circular buffer has just been
1732 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1733 * pending transfers
1734 */
1735 s->tx_dma_len = 0;
1736 if (s->chan_tx) {
1737 dmaengine_terminate_async(s->chan_tx);
1738 s->cookie_tx = -EINVAL;
1739 }
1740}
1741
1742static void sci_dma_check_tx_occurred(struct sci_port *s)
1743{
1744 struct dma_tx_state state;
1745 enum dma_status status;
1746
1747 if (!s->chan_tx)
1748 return;
1749
1750 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
1751 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
1752 s->tx_occurred = true;
1753}
1754#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1755static inline void sci_request_dma(struct uart_port *port)
1756{
1757}
1758
1759static inline void sci_free_dma(struct uart_port *port)
1760{
1761}
1762
1763static void sci_dma_check_tx_occurred(struct sci_port *s)
1764{
1765}
1766
1767#define sci_flush_buffer NULL
1768#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1769
1770static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1771{
1772 struct uart_port *port = ptr;
1773 struct sci_port *s = to_sci_port(port);
1774
1775#ifdef CONFIG_SERIAL_SH_SCI_DMA
1776 if (s->chan_rx) {
1777 u16 scr = sci_serial_in(port, SCSCR);
1778 u16 ssr = sci_serial_in(port, SCxSR);
1779
1780 /* Disable future Rx interrupts */
1781 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1782 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1783 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1784 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1785 scif_set_rtrg(port, 1);
1786 scr |= SCSCR_RIE;
1787 } else {
1788 scr |= SCSCR_RDRQE;
1789 }
1790 } else {
1791 if (sci_dma_rx_submit(s, false) < 0)
1792 goto handle_pio;
1793
1794 scr &= ~SCSCR_RIE;
1795 }
1796 sci_serial_out(port, SCSCR, scr);
1797 /* Clear current interrupt */
1798 sci_serial_out(port, SCxSR,
1799 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1800 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1801 jiffies, s->rx_timeout);
1802 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1803
1804 return IRQ_HANDLED;
1805 }
1806
1807handle_pio:
1808#endif
1809
1810 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1811 if (!scif_rtrg_enabled(port))
1812 scif_set_rtrg(port, s->rx_trigger);
1813
1814 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1815 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1816 }
1817
1818 /* I think sci_receive_chars has to be called irrespective
1819 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1820 * to be disabled?
1821 */
1822 sci_receive_chars(port);
1823
1824 return IRQ_HANDLED;
1825}
1826
1827static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1828{
1829 struct uart_port *port = ptr;
1830 unsigned long flags;
1831
1832 uart_port_lock_irqsave(port, &flags);
1833 sci_transmit_chars(port);
1834 uart_port_unlock_irqrestore(port, flags);
1835
1836 return IRQ_HANDLED;
1837}
1838
1839static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1840{
1841 struct uart_port *port = ptr;
1842 unsigned long flags;
1843 unsigned short ctrl;
1844
1845 if (port->type != PORT_SCI)
1846 return sci_tx_interrupt(irq, ptr);
1847
1848 uart_port_lock_irqsave(port, &flags);
1849 ctrl = sci_serial_in(port, SCSCR);
1850 ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
1851 sci_serial_out(port, SCSCR, ctrl);
1852 uart_port_unlock_irqrestore(port, flags);
1853
1854 return IRQ_HANDLED;
1855}
1856
1857static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1858{
1859 struct uart_port *port = ptr;
1860
1861 /* Handle BREAKs */
1862 sci_handle_breaks(port);
1863
1864 /* drop invalid character received before break was detected */
1865 sci_serial_in(port, SCxRDR);
1866
1867 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1868
1869 return IRQ_HANDLED;
1870}
1871
1872static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1873{
1874 struct uart_port *port = ptr;
1875 struct sci_port *s = to_sci_port(port);
1876
1877 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1878 /* Break and Error interrupts are muxed */
1879 unsigned short ssr_status = sci_serial_in(port, SCxSR);
1880
1881 /* Break Interrupt */
1882 if (ssr_status & SCxSR_BRK(port))
1883 sci_br_interrupt(irq, ptr);
1884
1885 /* Break only? */
1886 if (!(ssr_status & SCxSR_ERRORS(port)))
1887 return IRQ_HANDLED;
1888 }
1889
1890 /* Handle errors */
1891 if (port->type == PORT_SCI) {
1892 if (sci_handle_errors(port)) {
1893 /* discard character in rx buffer */
1894 sci_serial_in(port, SCxSR);
1895 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1896 }
1897 } else {
1898 sci_handle_fifo_overrun(port);
1899 if (!s->chan_rx)
1900 sci_receive_chars(port);
1901 }
1902
1903 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1904
1905 /* Kick the transmission */
1906 if (!s->chan_tx)
1907 sci_tx_interrupt(irq, ptr);
1908
1909 return IRQ_HANDLED;
1910}
1911
1912static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1913{
1914 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1915 struct uart_port *port = ptr;
1916 struct sci_port *s = to_sci_port(port);
1917 irqreturn_t ret = IRQ_NONE;
1918
1919 ssr_status = sci_serial_in(port, SCxSR);
1920 scr_status = sci_serial_in(port, SCSCR);
1921 if (s->params->overrun_reg == SCxSR)
1922 orer_status = ssr_status;
1923 else if (sci_getreg(port, s->params->overrun_reg)->size)
1924 orer_status = sci_serial_in(port, s->params->overrun_reg);
1925
1926 err_enabled = scr_status & port_rx_irq_mask(port);
1927
1928 /* Tx Interrupt */
1929 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1930 !s->chan_tx)
1931 ret = sci_tx_interrupt(irq, ptr);
1932
1933 /*
1934 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1935 * DR flags
1936 */
1937 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1938 (scr_status & SCSCR_RIE))
1939 ret = sci_rx_interrupt(irq, ptr);
1940
1941 /* Error Interrupt */
1942 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1943 ret = sci_er_interrupt(irq, ptr);
1944
1945 /* Break Interrupt */
1946 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1947 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1948 ret = sci_br_interrupt(irq, ptr);
1949
1950 /* Overrun Interrupt */
1951 if (orer_status & s->params->overrun_mask) {
1952 sci_handle_fifo_overrun(port);
1953 ret = IRQ_HANDLED;
1954 }
1955
1956 return ret;
1957}
1958
1959static const struct sci_irq_desc {
1960 const char *desc;
1961 irq_handler_t handler;
1962} sci_irq_desc[] = {
1963 /*
1964 * Split out handlers, the default case.
1965 */
1966 [SCIx_ERI_IRQ] = {
1967 .desc = "rx err",
1968 .handler = sci_er_interrupt,
1969 },
1970
1971 [SCIx_RXI_IRQ] = {
1972 .desc = "rx full",
1973 .handler = sci_rx_interrupt,
1974 },
1975
1976 [SCIx_TXI_IRQ] = {
1977 .desc = "tx empty",
1978 .handler = sci_tx_interrupt,
1979 },
1980
1981 [SCIx_BRI_IRQ] = {
1982 .desc = "break",
1983 .handler = sci_br_interrupt,
1984 },
1985
1986 [SCIx_DRI_IRQ] = {
1987 .desc = "rx ready",
1988 .handler = sci_rx_interrupt,
1989 },
1990
1991 [SCIx_TEI_IRQ] = {
1992 .desc = "tx end",
1993 .handler = sci_tx_end_interrupt,
1994 },
1995
1996 /*
1997 * Special muxed handler.
1998 */
1999 [SCIx_MUX_IRQ] = {
2000 .desc = "mux",
2001 .handler = sci_mpxed_interrupt,
2002 },
2003};
2004
2005static int sci_request_irq(struct sci_port *port)
2006{
2007 struct uart_port *up = &port->port;
2008 int i, j, w, ret = 0;
2009
2010 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
2011 const struct sci_irq_desc *desc;
2012 int irq;
2013
2014 /* Check if already registered (muxed) */
2015 for (w = 0; w < i; w++)
2016 if (port->irqs[w] == port->irqs[i])
2017 w = i + 1;
2018 if (w > i)
2019 continue;
2020
2021 if (SCIx_IRQ_IS_MUXED(port)) {
2022 i = SCIx_MUX_IRQ;
2023 irq = up->irq;
2024 } else {
2025 irq = port->irqs[i];
2026
2027 /*
2028 * Certain port types won't support all of the
2029 * available interrupt sources.
2030 */
2031 if (unlikely(irq < 0))
2032 continue;
2033 }
2034
2035 desc = sci_irq_desc + i;
2036 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
2037 dev_name(up->dev), desc->desc);
2038 if (!port->irqstr[j]) {
2039 ret = -ENOMEM;
2040 goto out_nomem;
2041 }
2042
2043 ret = request_irq(irq, desc->handler, up->irqflags,
2044 port->irqstr[j], port);
2045 if (unlikely(ret)) {
2046 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
2047 goto out_noirq;
2048 }
2049 }
2050
2051 return 0;
2052
2053out_noirq:
2054 while (--i >= 0)
2055 free_irq(port->irqs[i], port);
2056
2057out_nomem:
2058 while (--j >= 0)
2059 kfree(port->irqstr[j]);
2060
2061 return ret;
2062}
2063
2064static void sci_free_irq(struct sci_port *port)
2065{
2066 int i, j;
2067
2068 /*
2069 * Intentionally in reverse order so we iterate over the muxed
2070 * IRQ first.
2071 */
2072 for (i = 0; i < SCIx_NR_IRQS; i++) {
2073 int irq = port->irqs[i];
2074
2075 /*
2076 * Certain port types won't support all of the available
2077 * interrupt sources.
2078 */
2079 if (unlikely(irq < 0))
2080 continue;
2081
2082 /* Check if already freed (irq was muxed) */
2083 for (j = 0; j < i; j++)
2084 if (port->irqs[j] == irq)
2085 j = i + 1;
2086 if (j > i)
2087 continue;
2088
2089 free_irq(port->irqs[i], port);
2090 kfree(port->irqstr[i]);
2091
2092 if (SCIx_IRQ_IS_MUXED(port)) {
2093 /* If there's only one IRQ, we're done. */
2094 return;
2095 }
2096 }
2097}
2098
2099static unsigned int sci_tx_empty(struct uart_port *port)
2100{
2101 unsigned short status = sci_serial_in(port, SCxSR);
2102 unsigned short in_tx_fifo = sci_txfill(port);
2103 struct sci_port *s = to_sci_port(port);
2104
2105 sci_dma_check_tx_occurred(s);
2106
2107 if (!s->tx_occurred)
2108 return TIOCSER_TEMT;
2109
2110 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2111}
2112
2113static void sci_set_rts(struct uart_port *port, bool state)
2114{
2115 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2116 u16 data = sci_serial_in(port, SCPDR);
2117
2118 /* Active low */
2119 if (state)
2120 data &= ~SCPDR_RTSD;
2121 else
2122 data |= SCPDR_RTSD;
2123 sci_serial_out(port, SCPDR, data);
2124
2125 /* RTS# is output */
2126 sci_serial_out(port, SCPCR,
2127 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2128 } else if (sci_getreg(port, SCSPTR)->size) {
2129 u16 ctrl = sci_serial_in(port, SCSPTR);
2130
2131 /* Active low */
2132 if (state)
2133 ctrl &= ~SCSPTR_RTSDT;
2134 else
2135 ctrl |= SCSPTR_RTSDT;
2136 sci_serial_out(port, SCSPTR, ctrl);
2137 }
2138}
2139
2140static bool sci_get_cts(struct uart_port *port)
2141{
2142 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2143 /* Active low */
2144 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2145 } else if (sci_getreg(port, SCSPTR)->size) {
2146 /* Active low */
2147 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2148 }
2149
2150 return true;
2151}
2152
2153/*
2154 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2155 * CTS/RTS is supported in hardware by at least one port and controlled
2156 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2157 * handled via the ->init_pins() op, which is a bit of a one-way street,
2158 * lacking any ability to defer pin control -- this will later be
2159 * converted over to the GPIO framework).
2160 *
2161 * Other modes (such as loopback) are supported generically on certain
2162 * port types, but not others. For these it's sufficient to test for the
2163 * existence of the support register and simply ignore the port type.
2164 */
2165static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2166{
2167 struct sci_port *s = to_sci_port(port);
2168
2169 if (mctrl & TIOCM_LOOP) {
2170 const struct plat_sci_reg *reg;
2171
2172 /*
2173 * Standard loopback mode for SCFCR ports.
2174 */
2175 reg = sci_getreg(port, SCFCR);
2176 if (reg->size)
2177 sci_serial_out(port, SCFCR,
2178 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2179 }
2180
2181 mctrl_gpio_set(s->gpios, mctrl);
2182
2183 if (!s->has_rtscts)
2184 return;
2185
2186 if (!(mctrl & TIOCM_RTS)) {
2187 /* Disable Auto RTS */
2188 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2189 sci_serial_out(port, SCFCR,
2190 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2191
2192 /* Clear RTS */
2193 sci_set_rts(port, 0);
2194 } else if (s->autorts) {
2195 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2196 /* Enable RTS# pin function */
2197 sci_serial_out(port, SCPCR,
2198 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2199 }
2200
2201 /* Enable Auto RTS */
2202 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2203 sci_serial_out(port, SCFCR,
2204 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2205 } else {
2206 /* Set RTS */
2207 sci_set_rts(port, 1);
2208 }
2209}
2210
2211static unsigned int sci_get_mctrl(struct uart_port *port)
2212{
2213 struct sci_port *s = to_sci_port(port);
2214 struct mctrl_gpios *gpios = s->gpios;
2215 unsigned int mctrl = 0;
2216
2217 mctrl_gpio_get(gpios, &mctrl);
2218
2219 /*
2220 * CTS/RTS is handled in hardware when supported, while nothing
2221 * else is wired up.
2222 */
2223 if (s->autorts) {
2224 if (sci_get_cts(port))
2225 mctrl |= TIOCM_CTS;
2226 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2227 mctrl |= TIOCM_CTS;
2228 }
2229 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2230 mctrl |= TIOCM_DSR;
2231 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2232 mctrl |= TIOCM_CAR;
2233
2234 return mctrl;
2235}
2236
2237static void sci_enable_ms(struct uart_port *port)
2238{
2239 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2240}
2241
2242static void sci_break_ctl(struct uart_port *port, int break_state)
2243{
2244 unsigned short scscr, scsptr;
2245 unsigned long flags;
2246
2247 /* check whether the port has SCSPTR */
2248 if (!sci_getreg(port, SCSPTR)->size) {
2249 /*
2250 * Not supported by hardware. Most parts couple break and rx
2251 * interrupts together, with break detection always enabled.
2252 */
2253 return;
2254 }
2255
2256 uart_port_lock_irqsave(port, &flags);
2257 scsptr = sci_serial_in(port, SCSPTR);
2258 scscr = sci_serial_in(port, SCSCR);
2259
2260 if (break_state == -1) {
2261 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2262 scscr &= ~SCSCR_TE;
2263 } else {
2264 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2265 scscr |= SCSCR_TE;
2266 }
2267
2268 sci_serial_out(port, SCSPTR, scsptr);
2269 sci_serial_out(port, SCSCR, scscr);
2270 uart_port_unlock_irqrestore(port, flags);
2271}
2272
2273static int sci_startup(struct uart_port *port)
2274{
2275 struct sci_port *s = to_sci_port(port);
2276 int ret;
2277
2278 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2279
2280 s->tx_occurred = false;
2281 sci_request_dma(port);
2282
2283 ret = sci_request_irq(s);
2284 if (unlikely(ret < 0)) {
2285 sci_free_dma(port);
2286 return ret;
2287 }
2288
2289 return 0;
2290}
2291
2292static void sci_shutdown(struct uart_port *port)
2293{
2294 struct sci_port *s = to_sci_port(port);
2295 unsigned long flags;
2296 u16 scr;
2297
2298 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2299
2300 s->autorts = false;
2301 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2302
2303 uart_port_lock_irqsave(port, &flags);
2304 sci_stop_rx(port);
2305 sci_stop_tx(port);
2306 /*
2307 * Stop RX and TX, disable related interrupts, keep clock source
2308 * and HSCIF TOT bits
2309 */
2310 scr = sci_serial_in(port, SCSCR);
2311 sci_serial_out(port, SCSCR,
2312 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2313 uart_port_unlock_irqrestore(port, flags);
2314
2315#ifdef CONFIG_SERIAL_SH_SCI_DMA
2316 if (s->chan_rx_saved) {
2317 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2318 port->line);
2319 hrtimer_cancel(&s->rx_timer);
2320 }
2321#endif
2322
2323 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2324 del_timer_sync(&s->rx_fifo_timer);
2325 sci_free_irq(s);
2326 sci_free_dma(port);
2327}
2328
2329static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2330 unsigned int *srr)
2331{
2332 unsigned long freq = s->clk_rates[SCI_SCK];
2333 int err, min_err = INT_MAX;
2334 unsigned int sr;
2335
2336 if (s->port.type != PORT_HSCIF)
2337 freq *= 2;
2338
2339 for_each_sr(sr, s) {
2340 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2341 if (abs(err) >= abs(min_err))
2342 continue;
2343
2344 min_err = err;
2345 *srr = sr - 1;
2346
2347 if (!err)
2348 break;
2349 }
2350
2351 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2352 *srr + 1);
2353 return min_err;
2354}
2355
2356static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2357 unsigned long freq, unsigned int *dlr,
2358 unsigned int *srr)
2359{
2360 int err, min_err = INT_MAX;
2361 unsigned int sr, dl;
2362
2363 if (s->port.type != PORT_HSCIF)
2364 freq *= 2;
2365
2366 for_each_sr(sr, s) {
2367 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2368 dl = clamp(dl, 1U, 65535U);
2369
2370 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2371 if (abs(err) >= abs(min_err))
2372 continue;
2373
2374 min_err = err;
2375 *dlr = dl;
2376 *srr = sr - 1;
2377
2378 if (!err)
2379 break;
2380 }
2381
2382 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2383 min_err, *dlr, *srr + 1);
2384 return min_err;
2385}
2386
2387/* calculate sample rate, BRR, and clock select */
2388static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2389 unsigned int *brr, unsigned int *srr,
2390 unsigned int *cks)
2391{
2392 unsigned long freq = s->clk_rates[SCI_FCK];
2393 unsigned int sr, br, prediv, scrate, c;
2394 int err, min_err = INT_MAX;
2395
2396 if (s->port.type != PORT_HSCIF)
2397 freq *= 2;
2398
2399 /*
2400 * Find the combination of sample rate and clock select with the
2401 * smallest deviation from the desired baud rate.
2402 * Prefer high sample rates to maximise the receive margin.
2403 *
2404 * M: Receive margin (%)
2405 * N: Ratio of bit rate to clock (N = sampling rate)
2406 * D: Clock duty (D = 0 to 1.0)
2407 * L: Frame length (L = 9 to 12)
2408 * F: Absolute value of clock frequency deviation
2409 *
2410 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2411 * (|D - 0.5| / N * (1 + F))|
2412 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2413 */
2414 for_each_sr(sr, s) {
2415 for (c = 0; c <= 3; c++) {
2416 /* integerized formulas from HSCIF documentation */
2417 prediv = sr << (2 * c + 1);
2418
2419 /*
2420 * We need to calculate:
2421 *
2422 * br = freq / (prediv * bps) clamped to [1..256]
2423 * err = freq / (br * prediv) - bps
2424 *
2425 * Watch out for overflow when calculating the desired
2426 * sampling clock rate!
2427 */
2428 if (bps > UINT_MAX / prediv)
2429 break;
2430
2431 scrate = prediv * bps;
2432 br = DIV_ROUND_CLOSEST(freq, scrate);
2433 br = clamp(br, 1U, 256U);
2434
2435 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2436 if (abs(err) >= abs(min_err))
2437 continue;
2438
2439 min_err = err;
2440 *brr = br - 1;
2441 *srr = sr - 1;
2442 *cks = c;
2443
2444 if (!err)
2445 goto found;
2446 }
2447 }
2448
2449found:
2450 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2451 min_err, *brr, *srr + 1, *cks);
2452 return min_err;
2453}
2454
2455static void sci_reset(struct uart_port *port)
2456{
2457 const struct plat_sci_reg *reg;
2458 unsigned int status;
2459 struct sci_port *s = to_sci_port(port);
2460
2461 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2462
2463 reg = sci_getreg(port, SCFCR);
2464 if (reg->size)
2465 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2466
2467 sci_clear_SCxSR(port,
2468 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2469 SCxSR_BREAK_CLEAR(port));
2470 if (sci_getreg(port, SCLSR)->size) {
2471 status = sci_serial_in(port, SCLSR);
2472 status &= ~(SCLSR_TO | SCLSR_ORER);
2473 sci_serial_out(port, SCLSR, status);
2474 }
2475
2476 if (s->rx_trigger > 1) {
2477 if (s->rx_fifo_timeout) {
2478 scif_set_rtrg(port, 1);
2479 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2480 } else {
2481 if (port->type == PORT_SCIFA ||
2482 port->type == PORT_SCIFB)
2483 scif_set_rtrg(port, 1);
2484 else
2485 scif_set_rtrg(port, s->rx_trigger);
2486 }
2487 }
2488}
2489
2490static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2491 const struct ktermios *old)
2492{
2493 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2494 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2495 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2496 struct sci_port *s = to_sci_port(port);
2497 const struct plat_sci_reg *reg;
2498 int min_err = INT_MAX, err;
2499 unsigned long max_freq = 0;
2500 int best_clk = -1;
2501 unsigned long flags;
2502
2503 if ((termios->c_cflag & CSIZE) == CS7) {
2504 smr_val |= SCSMR_CHR;
2505 } else {
2506 termios->c_cflag &= ~CSIZE;
2507 termios->c_cflag |= CS8;
2508 }
2509 if (termios->c_cflag & PARENB)
2510 smr_val |= SCSMR_PE;
2511 if (termios->c_cflag & PARODD)
2512 smr_val |= SCSMR_PE | SCSMR_ODD;
2513 if (termios->c_cflag & CSTOPB)
2514 smr_val |= SCSMR_STOP;
2515
2516 /*
2517 * earlyprintk comes here early on with port->uartclk set to zero.
2518 * the clock framework is not up and running at this point so here
2519 * we assume that 115200 is the maximum baud rate. please note that
2520 * the baud rate is not programmed during earlyprintk - it is assumed
2521 * that the previous boot loader has enabled required clocks and
2522 * setup the baud rate generator hardware for us already.
2523 */
2524 if (!port->uartclk) {
2525 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2526 goto done;
2527 }
2528
2529 for (i = 0; i < SCI_NUM_CLKS; i++)
2530 max_freq = max(max_freq, s->clk_rates[i]);
2531
2532 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2533 if (!baud)
2534 goto done;
2535
2536 /*
2537 * There can be multiple sources for the sampling clock. Find the one
2538 * that gives us the smallest deviation from the desired baud rate.
2539 */
2540
2541 /* Optional Undivided External Clock */
2542 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2543 port->type != PORT_SCIFB) {
2544 err = sci_sck_calc(s, baud, &srr1);
2545 if (abs(err) < abs(min_err)) {
2546 best_clk = SCI_SCK;
2547 scr_val = SCSCR_CKE1;
2548 sccks = SCCKS_CKS;
2549 min_err = err;
2550 srr = srr1;
2551 if (!err)
2552 goto done;
2553 }
2554 }
2555
2556 /* Optional BRG Frequency Divided External Clock */
2557 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2558 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2559 &srr1);
2560 if (abs(err) < abs(min_err)) {
2561 best_clk = SCI_SCIF_CLK;
2562 scr_val = SCSCR_CKE1;
2563 sccks = 0;
2564 min_err = err;
2565 dl = dl1;
2566 srr = srr1;
2567 if (!err)
2568 goto done;
2569 }
2570 }
2571
2572 /* Optional BRG Frequency Divided Internal Clock */
2573 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2574 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2575 &srr1);
2576 if (abs(err) < abs(min_err)) {
2577 best_clk = SCI_BRG_INT;
2578 scr_val = SCSCR_CKE1;
2579 sccks = SCCKS_XIN;
2580 min_err = err;
2581 dl = dl1;
2582 srr = srr1;
2583 if (!min_err)
2584 goto done;
2585 }
2586 }
2587
2588 /* Divided Functional Clock using standard Bit Rate Register */
2589 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2590 if (abs(err) < abs(min_err)) {
2591 best_clk = SCI_FCK;
2592 scr_val = 0;
2593 min_err = err;
2594 brr = brr1;
2595 srr = srr1;
2596 cks = cks1;
2597 }
2598
2599done:
2600 if (best_clk >= 0)
2601 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2602 s->clks[best_clk], baud, min_err);
2603
2604 sci_port_enable(s);
2605
2606 /*
2607 * Program the optional External Baud Rate Generator (BRG) first.
2608 * It controls the mux to select (H)SCK or frequency divided clock.
2609 */
2610 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2611 sci_serial_out(port, SCDL, dl);
2612 sci_serial_out(port, SCCKS, sccks);
2613 }
2614
2615 uart_port_lock_irqsave(port, &flags);
2616
2617 sci_reset(port);
2618
2619 uart_update_timeout(port, termios->c_cflag, baud);
2620
2621 /* byte size and parity */
2622 bits = tty_get_frame_size(termios->c_cflag);
2623
2624 if (sci_getreg(port, SEMR)->size)
2625 sci_serial_out(port, SEMR, 0);
2626
2627 if (best_clk >= 0) {
2628 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2629 switch (srr + 1) {
2630 case 5: smr_val |= SCSMR_SRC_5; break;
2631 case 7: smr_val |= SCSMR_SRC_7; break;
2632 case 11: smr_val |= SCSMR_SRC_11; break;
2633 case 13: smr_val |= SCSMR_SRC_13; break;
2634 case 16: smr_val |= SCSMR_SRC_16; break;
2635 case 17: smr_val |= SCSMR_SRC_17; break;
2636 case 19: smr_val |= SCSMR_SRC_19; break;
2637 case 27: smr_val |= SCSMR_SRC_27; break;
2638 }
2639 smr_val |= cks;
2640 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2641 sci_serial_out(port, SCSMR, smr_val);
2642 sci_serial_out(port, SCBRR, brr);
2643 if (sci_getreg(port, HSSRR)->size) {
2644 unsigned int hssrr = srr | HSCIF_SRE;
2645 /* Calculate deviation from intended rate at the
2646 * center of the last stop bit in sampling clocks.
2647 */
2648 int last_stop = bits * 2 - 1;
2649 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2650 (int)(srr + 1),
2651 2 * (int)baud);
2652
2653 if (abs(deviation) >= 2) {
2654 /* At least two sampling clocks off at the
2655 * last stop bit; we can increase the error
2656 * margin by shifting the sampling point.
2657 */
2658 int shift = clamp(deviation / 2, -8, 7);
2659
2660 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2661 HSCIF_SRHP_MASK;
2662 hssrr |= HSCIF_SRDE;
2663 }
2664 sci_serial_out(port, HSSRR, hssrr);
2665 }
2666
2667 /* Wait one bit interval */
2668 udelay((1000000 + (baud - 1)) / baud);
2669 } else {
2670 /* Don't touch the bit rate configuration */
2671 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2672 smr_val |= sci_serial_in(port, SCSMR) &
2673 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2674 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2675 sci_serial_out(port, SCSMR, smr_val);
2676 }
2677
2678 sci_init_pins(port, termios->c_cflag);
2679
2680 port->status &= ~UPSTAT_AUTOCTS;
2681 s->autorts = false;
2682 reg = sci_getreg(port, SCFCR);
2683 if (reg->size) {
2684 unsigned short ctrl = sci_serial_in(port, SCFCR);
2685
2686 if ((port->flags & UPF_HARD_FLOW) &&
2687 (termios->c_cflag & CRTSCTS)) {
2688 /* There is no CTS interrupt to restart the hardware */
2689 port->status |= UPSTAT_AUTOCTS;
2690 /* MCE is enabled when RTS is raised */
2691 s->autorts = true;
2692 }
2693
2694 /*
2695 * As we've done a sci_reset() above, ensure we don't
2696 * interfere with the FIFOs while toggling MCE. As the
2697 * reset values could still be set, simply mask them out.
2698 */
2699 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2700
2701 sci_serial_out(port, SCFCR, ctrl);
2702 }
2703 if (port->flags & UPF_HARD_FLOW) {
2704 /* Refresh (Auto) RTS */
2705 sci_set_mctrl(port, port->mctrl);
2706 }
2707
2708 /*
2709 * For SCI, TE (transmit enable) must be set after setting TIE
2710 * (transmit interrupt enable) or in the same instruction to
2711 * start the transmitting process. So skip setting TE here for SCI.
2712 */
2713 if (port->type != PORT_SCI)
2714 scr_val |= SCSCR_TE;
2715 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2716 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2717 if ((srr + 1 == 5) &&
2718 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2719 /*
2720 * In asynchronous mode, when the sampling rate is 1/5, first
2721 * received data may become invalid on some SCIFA and SCIFB.
2722 * To avoid this problem wait more than 1 serial data time (1
2723 * bit time x serial data number) after setting SCSCR.RE = 1.
2724 */
2725 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2726 }
2727
2728 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2729 s->rx_frame = (10000 * bits) / (baud / 100);
2730#ifdef CONFIG_SERIAL_SH_SCI_DMA
2731 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2732#endif
2733
2734 if ((termios->c_cflag & CREAD) != 0)
2735 sci_start_rx(port);
2736
2737 uart_port_unlock_irqrestore(port, flags);
2738
2739 sci_port_disable(s);
2740
2741 if (UART_ENABLE_MS(port, termios->c_cflag))
2742 sci_enable_ms(port);
2743}
2744
2745static void sci_pm(struct uart_port *port, unsigned int state,
2746 unsigned int oldstate)
2747{
2748 struct sci_port *sci_port = to_sci_port(port);
2749
2750 switch (state) {
2751 case UART_PM_STATE_OFF:
2752 sci_port_disable(sci_port);
2753 break;
2754 default:
2755 sci_port_enable(sci_port);
2756 break;
2757 }
2758}
2759
2760static const char *sci_type(struct uart_port *port)
2761{
2762 switch (port->type) {
2763 case PORT_IRDA:
2764 return "irda";
2765 case PORT_SCI:
2766 return "sci";
2767 case PORT_SCIF:
2768 return "scif";
2769 case PORT_SCIFA:
2770 return "scifa";
2771 case PORT_SCIFB:
2772 return "scifb";
2773 case PORT_HSCIF:
2774 return "hscif";
2775 }
2776
2777 return NULL;
2778}
2779
2780static int sci_remap_port(struct uart_port *port)
2781{
2782 struct sci_port *sport = to_sci_port(port);
2783
2784 /*
2785 * Nothing to do if there's already an established membase.
2786 */
2787 if (port->membase)
2788 return 0;
2789
2790 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2791 port->membase = ioremap(port->mapbase, sport->reg_size);
2792 if (unlikely(!port->membase)) {
2793 dev_err(port->dev, "can't remap port#%d\n", port->line);
2794 return -ENXIO;
2795 }
2796 } else {
2797 /*
2798 * For the simple (and majority of) cases where we don't
2799 * need to do any remapping, just cast the cookie
2800 * directly.
2801 */
2802 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2803 }
2804
2805 return 0;
2806}
2807
2808static void sci_release_port(struct uart_port *port)
2809{
2810 struct sci_port *sport = to_sci_port(port);
2811
2812 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2813 iounmap(port->membase);
2814 port->membase = NULL;
2815 }
2816
2817 release_mem_region(port->mapbase, sport->reg_size);
2818}
2819
2820static int sci_request_port(struct uart_port *port)
2821{
2822 struct resource *res;
2823 struct sci_port *sport = to_sci_port(port);
2824 int ret;
2825
2826 res = request_mem_region(port->mapbase, sport->reg_size,
2827 dev_name(port->dev));
2828 if (unlikely(res == NULL)) {
2829 dev_err(port->dev, "request_mem_region failed.");
2830 return -EBUSY;
2831 }
2832
2833 ret = sci_remap_port(port);
2834 if (unlikely(ret != 0)) {
2835 release_resource(res);
2836 return ret;
2837 }
2838
2839 return 0;
2840}
2841
2842static void sci_config_port(struct uart_port *port, int flags)
2843{
2844 if (flags & UART_CONFIG_TYPE) {
2845 struct sci_port *sport = to_sci_port(port);
2846
2847 port->type = sport->cfg->type;
2848 sci_request_port(port);
2849 }
2850}
2851
2852static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2853{
2854 if (ser->baud_base < 2400)
2855 /* No paper tape reader for Mitch.. */
2856 return -EINVAL;
2857
2858 return 0;
2859}
2860
2861static const struct uart_ops sci_uart_ops = {
2862 .tx_empty = sci_tx_empty,
2863 .set_mctrl = sci_set_mctrl,
2864 .get_mctrl = sci_get_mctrl,
2865 .start_tx = sci_start_tx,
2866 .stop_tx = sci_stop_tx,
2867 .stop_rx = sci_stop_rx,
2868 .enable_ms = sci_enable_ms,
2869 .break_ctl = sci_break_ctl,
2870 .startup = sci_startup,
2871 .shutdown = sci_shutdown,
2872 .flush_buffer = sci_flush_buffer,
2873 .set_termios = sci_set_termios,
2874 .pm = sci_pm,
2875 .type = sci_type,
2876 .release_port = sci_release_port,
2877 .request_port = sci_request_port,
2878 .config_port = sci_config_port,
2879 .verify_port = sci_verify_port,
2880#ifdef CONFIG_CONSOLE_POLL
2881 .poll_get_char = sci_poll_get_char,
2882 .poll_put_char = sci_poll_put_char,
2883#endif
2884};
2885
2886static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2887{
2888 const char *clk_names[] = {
2889 [SCI_FCK] = "fck",
2890 [SCI_SCK] = "sck",
2891 [SCI_BRG_INT] = "brg_int",
2892 [SCI_SCIF_CLK] = "scif_clk",
2893 };
2894 struct clk *clk;
2895 unsigned int i;
2896
2897 if (sci_port->cfg->type == PORT_HSCIF)
2898 clk_names[SCI_SCK] = "hsck";
2899
2900 for (i = 0; i < SCI_NUM_CLKS; i++) {
2901 clk = devm_clk_get_optional(dev, clk_names[i]);
2902 if (IS_ERR(clk))
2903 return PTR_ERR(clk);
2904
2905 if (!clk && i == SCI_FCK) {
2906 /*
2907 * Not all SH platforms declare a clock lookup entry
2908 * for SCI devices, in which case we need to get the
2909 * global "peripheral_clk" clock.
2910 */
2911 clk = devm_clk_get(dev, "peripheral_clk");
2912 if (IS_ERR(clk))
2913 return dev_err_probe(dev, PTR_ERR(clk),
2914 "failed to get %s\n",
2915 clk_names[i]);
2916 }
2917
2918 if (!clk)
2919 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2920 else
2921 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2922 clk, clk_get_rate(clk));
2923 sci_port->clks[i] = clk;
2924 }
2925 return 0;
2926}
2927
2928static const struct sci_port_params *
2929sci_probe_regmap(const struct plat_sci_port *cfg)
2930{
2931 unsigned int regtype;
2932
2933 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2934 return &sci_port_params[cfg->regtype];
2935
2936 switch (cfg->type) {
2937 case PORT_SCI:
2938 regtype = SCIx_SCI_REGTYPE;
2939 break;
2940 case PORT_IRDA:
2941 regtype = SCIx_IRDA_REGTYPE;
2942 break;
2943 case PORT_SCIFA:
2944 regtype = SCIx_SCIFA_REGTYPE;
2945 break;
2946 case PORT_SCIFB:
2947 regtype = SCIx_SCIFB_REGTYPE;
2948 break;
2949 case PORT_SCIF:
2950 /*
2951 * The SH-4 is a bit of a misnomer here, although that's
2952 * where this particular port layout originated. This
2953 * configuration (or some slight variation thereof)
2954 * remains the dominant model for all SCIFs.
2955 */
2956 regtype = SCIx_SH4_SCIF_REGTYPE;
2957 break;
2958 case PORT_HSCIF:
2959 regtype = SCIx_HSCIF_REGTYPE;
2960 break;
2961 default:
2962 pr_err("Can't probe register map for given port\n");
2963 return NULL;
2964 }
2965
2966 return &sci_port_params[regtype];
2967}
2968
2969static int sci_init_single(struct platform_device *dev,
2970 struct sci_port *sci_port, unsigned int index,
2971 const struct plat_sci_port *p, bool early)
2972{
2973 struct uart_port *port = &sci_port->port;
2974 const struct resource *res;
2975 unsigned int i;
2976 int ret;
2977
2978 sci_port->cfg = p;
2979
2980 port->ops = &sci_uart_ops;
2981 port->iotype = UPIO_MEM;
2982 port->line = index;
2983 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2984
2985 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2986 if (res == NULL)
2987 return -ENOMEM;
2988
2989 port->mapbase = res->start;
2990 sci_port->reg_size = resource_size(res);
2991
2992 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2993 if (i)
2994 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2995 else
2996 sci_port->irqs[i] = platform_get_irq(dev, i);
2997 }
2998
2999 /*
3000 * The fourth interrupt on SCI port is transmit end interrupt, so
3001 * shuffle the interrupts.
3002 */
3003 if (p->type == PORT_SCI)
3004 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
3005
3006 /* The SCI generates several interrupts. They can be muxed together or
3007 * connected to different interrupt lines. In the muxed case only one
3008 * interrupt resource is specified as there is only one interrupt ID.
3009 * In the non-muxed case, up to 6 interrupt signals might be generated
3010 * from the SCI, however those signals might have their own individual
3011 * interrupt ID numbers, or muxed together with another interrupt.
3012 */
3013 if (sci_port->irqs[0] < 0)
3014 return -ENXIO;
3015
3016 if (sci_port->irqs[1] < 0)
3017 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
3018 sci_port->irqs[i] = sci_port->irqs[0];
3019
3020 sci_port->params = sci_probe_regmap(p);
3021 if (unlikely(sci_port->params == NULL))
3022 return -EINVAL;
3023
3024 switch (p->type) {
3025 case PORT_SCIFB:
3026 sci_port->rx_trigger = 48;
3027 break;
3028 case PORT_HSCIF:
3029 sci_port->rx_trigger = 64;
3030 break;
3031 case PORT_SCIFA:
3032 sci_port->rx_trigger = 32;
3033 break;
3034 case PORT_SCIF:
3035 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
3036 /* RX triggering not implemented for this IP */
3037 sci_port->rx_trigger = 1;
3038 else
3039 sci_port->rx_trigger = 8;
3040 break;
3041 default:
3042 sci_port->rx_trigger = 1;
3043 break;
3044 }
3045
3046 sci_port->rx_fifo_timeout = 0;
3047 sci_port->hscif_tot = 0;
3048
3049 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
3050 * match the SoC datasheet, this should be investigated. Let platform
3051 * data override the sampling rate for now.
3052 */
3053 sci_port->sampling_rate_mask = p->sampling_rate
3054 ? SCI_SR(p->sampling_rate)
3055 : sci_port->params->sampling_rate_mask;
3056
3057 if (!early) {
3058 ret = sci_init_clocks(sci_port, &dev->dev);
3059 if (ret < 0)
3060 return ret;
3061 }
3062
3063 port->type = p->type;
3064 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3065 port->fifosize = sci_port->params->fifosize;
3066
3067 if (port->type == PORT_SCI && !dev->dev.of_node) {
3068 if (sci_port->reg_size >= 0x20)
3069 port->regshift = 2;
3070 else
3071 port->regshift = 1;
3072 }
3073
3074 /*
3075 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3076 * for the multi-IRQ ports, which is where we are primarily
3077 * concerned with the shutdown path synchronization.
3078 *
3079 * For the muxed case there's nothing more to do.
3080 */
3081 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3082 port->irqflags = 0;
3083
3084 return 0;
3085}
3086
3087#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3088 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3089static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3090{
3091 sci_poll_put_char(port, ch);
3092}
3093
3094/*
3095 * Print a string to the serial port trying not to disturb
3096 * any possible real use of the port...
3097 */
3098static void serial_console_write(struct console *co, const char *s,
3099 unsigned count)
3100{
3101 struct sci_port *sci_port = &sci_ports[co->index];
3102 struct uart_port *port = &sci_port->port;
3103 unsigned short bits, ctrl, ctrl_temp;
3104 unsigned long flags;
3105 int locked = 1;
3106
3107 if (port->sysrq)
3108 locked = 0;
3109 else if (oops_in_progress)
3110 locked = uart_port_trylock_irqsave(port, &flags);
3111 else
3112 uart_port_lock_irqsave(port, &flags);
3113
3114 /* first save SCSCR then disable interrupts, keep clock source */
3115 ctrl = sci_serial_in(port, SCSCR);
3116 ctrl_temp = SCSCR_RE | SCSCR_TE |
3117 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3118 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3119 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3120
3121 uart_console_write(port, s, count, serial_console_putchar);
3122
3123 /* wait until fifo is empty and last bit has been transmitted */
3124 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3125 while ((sci_serial_in(port, SCxSR) & bits) != bits)
3126 cpu_relax();
3127
3128 /* restore the SCSCR */
3129 sci_serial_out(port, SCSCR, ctrl);
3130
3131 if (locked)
3132 uart_port_unlock_irqrestore(port, flags);
3133}
3134
3135static int serial_console_setup(struct console *co, char *options)
3136{
3137 struct sci_port *sci_port;
3138 struct uart_port *port;
3139 int baud = 115200;
3140 int bits = 8;
3141 int parity = 'n';
3142 int flow = 'n';
3143 int ret;
3144
3145 /*
3146 * Refuse to handle any bogus ports.
3147 */
3148 if (co->index < 0 || co->index >= SCI_NPORTS)
3149 return -ENODEV;
3150
3151 sci_port = &sci_ports[co->index];
3152 port = &sci_port->port;
3153
3154 /*
3155 * Refuse to handle uninitialized ports.
3156 */
3157 if (!port->ops)
3158 return -ENODEV;
3159
3160 ret = sci_remap_port(port);
3161 if (unlikely(ret != 0))
3162 return ret;
3163
3164 if (options)
3165 uart_parse_options(options, &baud, &parity, &bits, &flow);
3166
3167 return uart_set_options(port, co, baud, parity, bits, flow);
3168}
3169
3170static struct console serial_console = {
3171 .name = "ttySC",
3172 .device = uart_console_device,
3173 .write = serial_console_write,
3174 .setup = serial_console_setup,
3175 .flags = CON_PRINTBUFFER,
3176 .index = -1,
3177 .data = &sci_uart_driver,
3178};
3179
3180#ifdef CONFIG_SUPERH
3181static char early_serial_buf[32];
3182
3183static int early_serial_console_setup(struct console *co, char *options)
3184{
3185 /*
3186 * This early console is always registered using the earlyprintk=
3187 * parameter, which does not call add_preferred_console(). Thus
3188 * @options is always NULL and the options for this early console
3189 * are passed using a custom buffer.
3190 */
3191 WARN_ON(options);
3192
3193 return serial_console_setup(co, early_serial_buf);
3194}
3195
3196static struct console early_serial_console = {
3197 .name = "early_ttySC",
3198 .write = serial_console_write,
3199 .setup = early_serial_console_setup,
3200 .flags = CON_PRINTBUFFER,
3201 .index = -1,
3202};
3203
3204static int sci_probe_earlyprintk(struct platform_device *pdev)
3205{
3206 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3207
3208 if (early_serial_console.data)
3209 return -EEXIST;
3210
3211 early_serial_console.index = pdev->id;
3212
3213 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3214
3215 if (!strstr(early_serial_buf, "keep"))
3216 early_serial_console.flags |= CON_BOOT;
3217
3218 register_console(&early_serial_console);
3219 return 0;
3220}
3221#endif
3222
3223#define SCI_CONSOLE (&serial_console)
3224
3225#else
3226static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3227{
3228 return -EINVAL;
3229}
3230
3231#define SCI_CONSOLE NULL
3232
3233#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3234
3235static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3236
3237static DEFINE_MUTEX(sci_uart_registration_lock);
3238static struct uart_driver sci_uart_driver = {
3239 .owner = THIS_MODULE,
3240 .driver_name = "sci",
3241 .dev_name = "ttySC",
3242 .major = SCI_MAJOR,
3243 .minor = SCI_MINOR_START,
3244 .nr = SCI_NPORTS,
3245 .cons = SCI_CONSOLE,
3246};
3247
3248static void sci_remove(struct platform_device *dev)
3249{
3250 struct sci_port *port = platform_get_drvdata(dev);
3251 unsigned int type = port->port.type; /* uart_remove_... clears it */
3252
3253 sci_ports_in_use &= ~BIT(port->port.line);
3254 uart_remove_one_port(&sci_uart_driver, &port->port);
3255
3256 if (port->port.fifosize > 1)
3257 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3258 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3259 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3260}
3261
3262
3263#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3264#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3265#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3266
3267static const struct of_device_id of_sci_match[] __maybe_unused = {
3268 /* SoC-specific types */
3269 {
3270 .compatible = "renesas,scif-r7s72100",
3271 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3272 },
3273 {
3274 .compatible = "renesas,scif-r7s9210",
3275 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3276 },
3277 {
3278 .compatible = "renesas,scif-r9a07g044",
3279 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3280 },
3281 {
3282 .compatible = "renesas,scif-r9a09g057",
3283 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE),
3284 },
3285 /* Family-specific types */
3286 {
3287 .compatible = "renesas,rcar-gen1-scif",
3288 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3289 }, {
3290 .compatible = "renesas,rcar-gen2-scif",
3291 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3292 }, {
3293 .compatible = "renesas,rcar-gen3-scif",
3294 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3295 }, {
3296 .compatible = "renesas,rcar-gen4-scif",
3297 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3298 },
3299 /* Generic types */
3300 {
3301 .compatible = "renesas,scif",
3302 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3303 }, {
3304 .compatible = "renesas,scifa",
3305 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3306 }, {
3307 .compatible = "renesas,scifb",
3308 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3309 }, {
3310 .compatible = "renesas,hscif",
3311 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3312 }, {
3313 .compatible = "renesas,sci",
3314 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3315 }, {
3316 /* Terminator */
3317 },
3318};
3319MODULE_DEVICE_TABLE(of, of_sci_match);
3320
3321static void sci_reset_control_assert(void *data)
3322{
3323 reset_control_assert(data);
3324}
3325
3326static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3327 unsigned int *dev_id)
3328{
3329 struct device_node *np = pdev->dev.of_node;
3330 struct reset_control *rstc;
3331 struct plat_sci_port *p;
3332 struct sci_port *sp;
3333 const void *data;
3334 int id, ret;
3335
3336 if (!IS_ENABLED(CONFIG_OF) || !np)
3337 return ERR_PTR(-EINVAL);
3338
3339 data = of_device_get_match_data(&pdev->dev);
3340
3341 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3342 if (IS_ERR(rstc))
3343 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3344 "failed to get reset ctrl\n"));
3345
3346 ret = reset_control_deassert(rstc);
3347 if (ret) {
3348 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3349 return ERR_PTR(ret);
3350 }
3351
3352 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3353 if (ret) {
3354 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3355 ret);
3356 return ERR_PTR(ret);
3357 }
3358
3359 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3360 if (!p)
3361 return ERR_PTR(-ENOMEM);
3362
3363 /* Get the line number from the aliases node. */
3364 id = of_alias_get_id(np, "serial");
3365 if (id < 0 && ~sci_ports_in_use)
3366 id = ffz(sci_ports_in_use);
3367 if (id < 0) {
3368 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3369 return ERR_PTR(-EINVAL);
3370 }
3371 if (id >= ARRAY_SIZE(sci_ports)) {
3372 dev_err(&pdev->dev, "serial%d out of range\n", id);
3373 return ERR_PTR(-EINVAL);
3374 }
3375
3376 sp = &sci_ports[id];
3377 *dev_id = id;
3378
3379 p->type = SCI_OF_TYPE(data);
3380 p->regtype = SCI_OF_REGTYPE(data);
3381
3382 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3383
3384 return p;
3385}
3386
3387static int sci_probe_single(struct platform_device *dev,
3388 unsigned int index,
3389 struct plat_sci_port *p,
3390 struct sci_port *sciport,
3391 struct resource *sci_res)
3392{
3393 int ret;
3394
3395 /* Sanity check */
3396 if (unlikely(index >= SCI_NPORTS)) {
3397 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3398 index+1, SCI_NPORTS);
3399 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3400 return -EINVAL;
3401 }
3402 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3403 if (sci_ports_in_use & BIT(index))
3404 return -EBUSY;
3405
3406 mutex_lock(&sci_uart_registration_lock);
3407 if (!sci_uart_driver.state) {
3408 ret = uart_register_driver(&sci_uart_driver);
3409 if (ret) {
3410 mutex_unlock(&sci_uart_registration_lock);
3411 return ret;
3412 }
3413 }
3414 mutex_unlock(&sci_uart_registration_lock);
3415
3416 ret = sci_init_single(dev, sciport, index, p, false);
3417 if (ret)
3418 return ret;
3419
3420 sciport->port.dev = &dev->dev;
3421 ret = devm_pm_runtime_enable(&dev->dev);
3422 if (ret)
3423 return ret;
3424
3425 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3426 if (IS_ERR(sciport->gpios))
3427 return PTR_ERR(sciport->gpios);
3428
3429 if (sciport->has_rtscts) {
3430 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3431 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3432 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3433 return -EINVAL;
3434 }
3435 sciport->port.flags |= UPF_HARD_FLOW;
3436 }
3437
3438 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
3439 /*
3440 * In case:
3441 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and
3442 * - it now maps to an alias other than zero and
3443 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is
3444 * available in bootargs)
3445 *
3446 * we need to avoid disabling clocks and PM domains through the runtime
3447 * PM APIs called in __device_attach(). For this, increment the runtime
3448 * PM reference counter (the clocks and PM domains were already enabled
3449 * by the bootloader). Otherwise the earlycon may access the HW when it
3450 * has no clocks enabled leading to failures (infinite loop in
3451 * sci_poll_put_char()).
3452 */
3453 pm_runtime_get_noresume(&dev->dev);
3454
3455 /*
3456 * Skip cleanup the sci_port[0] in early_console_exit(), this
3457 * port is the same as the earlycon one.
3458 */
3459 sci_uart_earlycon_dev_probing = true;
3460 }
3461
3462 return uart_add_one_port(&sci_uart_driver, &sciport->port);
3463}
3464
3465static int sci_probe(struct platform_device *dev)
3466{
3467 struct plat_sci_port *p;
3468 struct resource *res;
3469 struct sci_port *sp;
3470 unsigned int dev_id;
3471 int ret;
3472
3473 /*
3474 * If we've come here via earlyprintk initialization, head off to
3475 * the special early probe. We don't have sufficient device state
3476 * to make it beyond this yet.
3477 */
3478#ifdef CONFIG_SUPERH
3479 if (is_sh_early_platform_device(dev))
3480 return sci_probe_earlyprintk(dev);
3481#endif
3482
3483 if (dev->dev.of_node) {
3484 p = sci_parse_dt(dev, &dev_id);
3485 if (IS_ERR(p))
3486 return PTR_ERR(p);
3487 } else {
3488 p = dev->dev.platform_data;
3489 if (p == NULL) {
3490 dev_err(&dev->dev, "no platform data supplied\n");
3491 return -EINVAL;
3492 }
3493
3494 dev_id = dev->id;
3495 }
3496
3497 sp = &sci_ports[dev_id];
3498
3499 /*
3500 * In case:
3501 * - the probed port alias is zero (as the one used by earlycon), and
3502 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in
3503 * bootargs)
3504 *
3505 * defer the probe of this serial. This is a debug scenario and the user
3506 * must be aware of it.
3507 *
3508 * Except when the probed port is the same as the earlycon port.
3509 */
3510
3511 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3512 if (!res)
3513 return -ENODEV;
3514
3515 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)
3516 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
3517
3518 platform_set_drvdata(dev, sp);
3519
3520 ret = sci_probe_single(dev, dev_id, p, sp, res);
3521 if (ret)
3522 return ret;
3523
3524 if (sp->port.fifosize > 1) {
3525 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3526 if (ret)
3527 return ret;
3528 }
3529 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3530 sp->port.type == PORT_HSCIF) {
3531 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3532 if (ret) {
3533 if (sp->port.fifosize > 1) {
3534 device_remove_file(&dev->dev,
3535 &dev_attr_rx_fifo_trigger);
3536 }
3537 return ret;
3538 }
3539 }
3540
3541#ifdef CONFIG_SH_STANDARD_BIOS
3542 sh_bios_gdb_detach();
3543#endif
3544
3545 sci_ports_in_use |= BIT(dev_id);
3546 return 0;
3547}
3548
3549static __maybe_unused int sci_suspend(struct device *dev)
3550{
3551 struct sci_port *sport = dev_get_drvdata(dev);
3552
3553 if (sport)
3554 uart_suspend_port(&sci_uart_driver, &sport->port);
3555
3556 return 0;
3557}
3558
3559static __maybe_unused int sci_resume(struct device *dev)
3560{
3561 struct sci_port *sport = dev_get_drvdata(dev);
3562
3563 if (sport)
3564 uart_resume_port(&sci_uart_driver, &sport->port);
3565
3566 return 0;
3567}
3568
3569static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3570
3571static struct platform_driver sci_driver = {
3572 .probe = sci_probe,
3573 .remove = sci_remove,
3574 .driver = {
3575 .name = "sh-sci",
3576 .pm = &sci_dev_pm_ops,
3577 .of_match_table = of_match_ptr(of_sci_match),
3578 },
3579};
3580
3581static int __init sci_init(void)
3582{
3583 pr_info("%s\n", banner);
3584
3585 return platform_driver_register(&sci_driver);
3586}
3587
3588static void __exit sci_exit(void)
3589{
3590 platform_driver_unregister(&sci_driver);
3591
3592 if (sci_uart_driver.state)
3593 uart_unregister_driver(&sci_uart_driver);
3594}
3595
3596#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3597sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3598 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3599#endif
3600#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3601static struct plat_sci_port port_cfg;
3602
3603static int early_console_exit(struct console *co)
3604{
3605 struct sci_port *sci_port = &sci_ports[0];
3606
3607 /*
3608 * Clean the slot used by earlycon. A new SCI device might
3609 * map to this slot.
3610 */
3611 if (!sci_uart_earlycon_dev_probing) {
3612 memset(sci_port, 0, sizeof(*sci_port));
3613 sci_uart_earlycon = false;
3614 }
3615
3616 return 0;
3617}
3618
3619static int __init early_console_setup(struct earlycon_device *device,
3620 int type)
3621{
3622 if (!device->port.membase)
3623 return -ENODEV;
3624
3625 device->port.type = type;
3626 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3627 port_cfg.type = type;
3628 sci_ports[0].cfg = &port_cfg;
3629 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3630 sci_uart_earlycon = true;
3631 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3632 sci_serial_out(&sci_ports[0].port, SCSCR,
3633 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3634
3635 device->con->write = serial_console_write;
3636 device->con->exit = early_console_exit;
3637
3638 return 0;
3639}
3640static int __init sci_early_console_setup(struct earlycon_device *device,
3641 const char *opt)
3642{
3643 return early_console_setup(device, PORT_SCI);
3644}
3645static int __init scif_early_console_setup(struct earlycon_device *device,
3646 const char *opt)
3647{
3648 return early_console_setup(device, PORT_SCIF);
3649}
3650static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3651 const char *opt)
3652{
3653 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3654 return early_console_setup(device, PORT_SCIF);
3655}
3656
3657static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
3658 const char *opt)
3659{
3660 port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE;
3661 return early_console_setup(device, PORT_SCIF);
3662}
3663
3664static int __init scifa_early_console_setup(struct earlycon_device *device,
3665 const char *opt)
3666{
3667 return early_console_setup(device, PORT_SCIFA);
3668}
3669static int __init scifb_early_console_setup(struct earlycon_device *device,
3670 const char *opt)
3671{
3672 return early_console_setup(device, PORT_SCIFB);
3673}
3674static int __init hscif_early_console_setup(struct earlycon_device *device,
3675 const char *opt)
3676{
3677 return early_console_setup(device, PORT_HSCIF);
3678}
3679
3680OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3681OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3682OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3683OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3684OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3685OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3686OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3687OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3688#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3689
3690module_init(sci_init);
3691module_exit(sci_exit);
3692
3693MODULE_LICENSE("GPL");
3694MODULE_ALIAS("platform:sh-sci");
3695MODULE_AUTHOR("Paul Mundt");
3696MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");