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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#undef DEBUG
19
20#include <linux/clk.h>
21#include <linux/console.h>
22#include <linux/ctype.h>
23#include <linux/cpufreq.h>
24#include <linux/delay.h>
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
27#include <linux/err.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/ioport.h>
32#include <linux/ktime.h>
33#include <linux/major.h>
34#include <linux/minmax.h>
35#include <linux/module.h>
36#include <linux/mm.h>
37#include <linux/of.h>
38#include <linux/platform_device.h>
39#include <linux/pm_runtime.h>
40#include <linux/reset.h>
41#include <linux/scatterlist.h>
42#include <linux/serial.h>
43#include <linux/serial_sci.h>
44#include <linux/sh_dma.h>
45#include <linux/slab.h>
46#include <linux/string.h>
47#include <linux/sysrq.h>
48#include <linux/timer.h>
49#include <linux/tty.h>
50#include <linux/tty_flip.h>
51
52#ifdef CONFIG_SUPERH
53#include <asm/sh_bios.h>
54#include <asm/platform_early.h>
55#endif
56
57#include "serial_mctrl_gpio.h"
58#include "sh-sci.h"
59
60/* Offsets into the sci_port->irqs array */
61enum {
62 SCIx_ERI_IRQ,
63 SCIx_RXI_IRQ,
64 SCIx_TXI_IRQ,
65 SCIx_BRI_IRQ,
66 SCIx_DRI_IRQ,
67 SCIx_TEI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85};
86
87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103struct plat_sci_reg {
104 u8 offset, size;
105};
106
107struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
115};
116
117struct sci_port {
118 struct uart_port port;
119
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
126
127 /* Clocks */
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
130
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
133
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136
137#ifdef CONFIG_SERIAL_SH_SCI_DMA
138 struct dma_chan *chan_tx_saved;
139 struct dma_chan *chan_rx_saved;
140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
145 struct scatterlist sg_rx[2];
146 void *rx_buf[2];
147 size_t buf_len_rx;
148 struct work_struct work_tx;
149 struct hrtimer rx_timer;
150 unsigned int rx_timeout; /* microseconds */
151#endif
152 unsigned int rx_frame;
153 int rx_trigger;
154 struct timer_list rx_fifo_timer;
155 int rx_fifo_timeout;
156 u16 hscif_tot;
157
158 bool has_rtscts;
159 bool autorts;
160};
161
162#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
163
164static struct sci_port sci_ports[SCI_NPORTS];
165static unsigned long sci_ports_in_use;
166static struct uart_driver sci_uart_driver;
167
168static inline struct sci_port *
169to_sci_port(struct uart_port *uart)
170{
171 return container_of(uart, struct sci_port, port);
172}
173
174static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
175 /*
176 * Common SCI definitions, dependent on the port's regshift
177 * value.
178 */
179 [SCIx_SCI_REGTYPE] = {
180 .regs = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
187 },
188 .fifosize = 1,
189 .overrun_reg = SCxSR,
190 .overrun_mask = SCI_ORER,
191 .sampling_rate_mask = SCI_SR(32),
192 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
193 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
194 },
195
196 /*
197 * Common definitions for legacy IrDA ports.
198 */
199 [SCIx_IRDA_REGTYPE] = {
200 .regs = {
201 [SCSMR] = { 0x00, 8 },
202 [SCBRR] = { 0x02, 8 },
203 [SCSCR] = { 0x04, 8 },
204 [SCxTDR] = { 0x06, 8 },
205 [SCxSR] = { 0x08, 16 },
206 [SCxRDR] = { 0x0a, 8 },
207 [SCFCR] = { 0x0c, 8 },
208 [SCFDR] = { 0x0e, 16 },
209 },
210 .fifosize = 1,
211 .overrun_reg = SCxSR,
212 .overrun_mask = SCI_ORER,
213 .sampling_rate_mask = SCI_SR(32),
214 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
215 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
216 },
217
218 /*
219 * Common SCIFA definitions.
220 */
221 [SCIx_SCIFA_REGTYPE] = {
222 .regs = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x20, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x24, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = { 0x1c, 16 },
231 [SCPCR] = { 0x30, 16 },
232 [SCPDR] = { 0x34, 16 },
233 },
234 .fifosize = 64,
235 .overrun_reg = SCxSR,
236 .overrun_mask = SCIFA_ORER,
237 .sampling_rate_mask = SCI_SR_SCIFAB,
238 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
239 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
240 },
241
242 /*
243 * Common SCIFB definitions.
244 */
245 [SCIx_SCIFB_REGTYPE] = {
246 .regs = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x40, 8 },
251 [SCxSR] = { 0x14, 16 },
252 [SCxRDR] = { 0x60, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCTFDR] = { 0x38, 16 },
255 [SCRFDR] = { 0x3c, 16 },
256 [SCPCR] = { 0x30, 16 },
257 [SCPDR] = { 0x34, 16 },
258 },
259 .fifosize = 256,
260 .overrun_reg = SCxSR,
261 .overrun_mask = SCIFA_ORER,
262 .sampling_rate_mask = SCI_SR_SCIFAB,
263 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
264 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
265 },
266
267 /*
268 * Common SH-2(A) SCIF definitions for ports with FIFO data
269 * count registers.
270 */
271 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
272 .regs = {
273 [SCSMR] = { 0x00, 16 },
274 [SCBRR] = { 0x04, 8 },
275 [SCSCR] = { 0x08, 16 },
276 [SCxTDR] = { 0x0c, 8 },
277 [SCxSR] = { 0x10, 16 },
278 [SCxRDR] = { 0x14, 8 },
279 [SCFCR] = { 0x18, 16 },
280 [SCFDR] = { 0x1c, 16 },
281 [SCSPTR] = { 0x20, 16 },
282 [SCLSR] = { 0x24, 16 },
283 },
284 .fifosize = 16,
285 .overrun_reg = SCLSR,
286 .overrun_mask = SCLSR_ORER,
287 .sampling_rate_mask = SCI_SR(32),
288 .error_mask = SCIF_DEFAULT_ERROR_MASK,
289 .error_clear = SCIF_ERROR_CLEAR,
290 },
291
292 /*
293 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
294 * It looks like a normal SCIF with FIFO data, but with a
295 * compressed address space. Also, the break out of interrupts
296 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
297 */
298 [SCIx_RZ_SCIFA_REGTYPE] = {
299 .regs = {
300 [SCSMR] = { 0x00, 16 },
301 [SCBRR] = { 0x02, 8 },
302 [SCSCR] = { 0x04, 16 },
303 [SCxTDR] = { 0x06, 8 },
304 [SCxSR] = { 0x08, 16 },
305 [SCxRDR] = { 0x0A, 8 },
306 [SCFCR] = { 0x0C, 16 },
307 [SCFDR] = { 0x0E, 16 },
308 [SCSPTR] = { 0x10, 16 },
309 [SCLSR] = { 0x12, 16 },
310 [SEMR] = { 0x14, 8 },
311 },
312 .fifosize = 16,
313 .overrun_reg = SCLSR,
314 .overrun_mask = SCLSR_ORER,
315 .sampling_rate_mask = SCI_SR(32),
316 .error_mask = SCIF_DEFAULT_ERROR_MASK,
317 .error_clear = SCIF_ERROR_CLEAR,
318 },
319
320 /*
321 * Common SH-3 SCIF definitions.
322 */
323 [SCIx_SH3_SCIF_REGTYPE] = {
324 .regs = {
325 [SCSMR] = { 0x00, 8 },
326 [SCBRR] = { 0x02, 8 },
327 [SCSCR] = { 0x04, 8 },
328 [SCxTDR] = { 0x06, 8 },
329 [SCxSR] = { 0x08, 16 },
330 [SCxRDR] = { 0x0a, 8 },
331 [SCFCR] = { 0x0c, 8 },
332 [SCFDR] = { 0x0e, 16 },
333 },
334 .fifosize = 16,
335 .overrun_reg = SCLSR,
336 .overrun_mask = SCLSR_ORER,
337 .sampling_rate_mask = SCI_SR(32),
338 .error_mask = SCIF_DEFAULT_ERROR_MASK,
339 .error_clear = SCIF_ERROR_CLEAR,
340 },
341
342 /*
343 * Common SH-4(A) SCIF(B) definitions.
344 */
345 [SCIx_SH4_SCIF_REGTYPE] = {
346 .regs = {
347 [SCSMR] = { 0x00, 16 },
348 [SCBRR] = { 0x04, 8 },
349 [SCSCR] = { 0x08, 16 },
350 [SCxTDR] = { 0x0c, 8 },
351 [SCxSR] = { 0x10, 16 },
352 [SCxRDR] = { 0x14, 8 },
353 [SCFCR] = { 0x18, 16 },
354 [SCFDR] = { 0x1c, 16 },
355 [SCSPTR] = { 0x20, 16 },
356 [SCLSR] = { 0x24, 16 },
357 },
358 .fifosize = 16,
359 .overrun_reg = SCLSR,
360 .overrun_mask = SCLSR_ORER,
361 .sampling_rate_mask = SCI_SR(32),
362 .error_mask = SCIF_DEFAULT_ERROR_MASK,
363 .error_clear = SCIF_ERROR_CLEAR,
364 },
365
366 /*
367 * Common SCIF definitions for ports with a Baud Rate Generator for
368 * External Clock (BRG).
369 */
370 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
371 .regs = {
372 [SCSMR] = { 0x00, 16 },
373 [SCBRR] = { 0x04, 8 },
374 [SCSCR] = { 0x08, 16 },
375 [SCxTDR] = { 0x0c, 8 },
376 [SCxSR] = { 0x10, 16 },
377 [SCxRDR] = { 0x14, 8 },
378 [SCFCR] = { 0x18, 16 },
379 [SCFDR] = { 0x1c, 16 },
380 [SCSPTR] = { 0x20, 16 },
381 [SCLSR] = { 0x24, 16 },
382 [SCDL] = { 0x30, 16 },
383 [SCCKS] = { 0x34, 16 },
384 },
385 .fifosize = 16,
386 .overrun_reg = SCLSR,
387 .overrun_mask = SCLSR_ORER,
388 .sampling_rate_mask = SCI_SR(32),
389 .error_mask = SCIF_DEFAULT_ERROR_MASK,
390 .error_clear = SCIF_ERROR_CLEAR,
391 },
392
393 /*
394 * Common HSCIF definitions.
395 */
396 [SCIx_HSCIF_REGTYPE] = {
397 .regs = {
398 [SCSMR] = { 0x00, 16 },
399 [SCBRR] = { 0x04, 8 },
400 [SCSCR] = { 0x08, 16 },
401 [SCxTDR] = { 0x0c, 8 },
402 [SCxSR] = { 0x10, 16 },
403 [SCxRDR] = { 0x14, 8 },
404 [SCFCR] = { 0x18, 16 },
405 [SCFDR] = { 0x1c, 16 },
406 [SCSPTR] = { 0x20, 16 },
407 [SCLSR] = { 0x24, 16 },
408 [HSSRR] = { 0x40, 16 },
409 [SCDL] = { 0x30, 16 },
410 [SCCKS] = { 0x34, 16 },
411 [HSRTRGR] = { 0x54, 16 },
412 [HSTTRGR] = { 0x58, 16 },
413 },
414 .fifosize = 128,
415 .overrun_reg = SCLSR,
416 .overrun_mask = SCLSR_ORER,
417 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
418 .error_mask = SCIF_DEFAULT_ERROR_MASK,
419 .error_clear = SCIF_ERROR_CLEAR,
420 },
421
422 /*
423 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
424 * register.
425 */
426 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
427 .regs = {
428 [SCSMR] = { 0x00, 16 },
429 [SCBRR] = { 0x04, 8 },
430 [SCSCR] = { 0x08, 16 },
431 [SCxTDR] = { 0x0c, 8 },
432 [SCxSR] = { 0x10, 16 },
433 [SCxRDR] = { 0x14, 8 },
434 [SCFCR] = { 0x18, 16 },
435 [SCFDR] = { 0x1c, 16 },
436 [SCLSR] = { 0x24, 16 },
437 },
438 .fifosize = 16,
439 .overrun_reg = SCLSR,
440 .overrun_mask = SCLSR_ORER,
441 .sampling_rate_mask = SCI_SR(32),
442 .error_mask = SCIF_DEFAULT_ERROR_MASK,
443 .error_clear = SCIF_ERROR_CLEAR,
444 },
445
446 /*
447 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
448 * count registers.
449 */
450 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
451 .regs = {
452 [SCSMR] = { 0x00, 16 },
453 [SCBRR] = { 0x04, 8 },
454 [SCSCR] = { 0x08, 16 },
455 [SCxTDR] = { 0x0c, 8 },
456 [SCxSR] = { 0x10, 16 },
457 [SCxRDR] = { 0x14, 8 },
458 [SCFCR] = { 0x18, 16 },
459 [SCFDR] = { 0x1c, 16 },
460 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
461 [SCRFDR] = { 0x20, 16 },
462 [SCSPTR] = { 0x24, 16 },
463 [SCLSR] = { 0x28, 16 },
464 },
465 .fifosize = 16,
466 .overrun_reg = SCLSR,
467 .overrun_mask = SCLSR_ORER,
468 .sampling_rate_mask = SCI_SR(32),
469 .error_mask = SCIF_DEFAULT_ERROR_MASK,
470 .error_clear = SCIF_ERROR_CLEAR,
471 },
472
473 /*
474 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
475 * registers.
476 */
477 [SCIx_SH7705_SCIF_REGTYPE] = {
478 .regs = {
479 [SCSMR] = { 0x00, 16 },
480 [SCBRR] = { 0x04, 8 },
481 [SCSCR] = { 0x08, 16 },
482 [SCxTDR] = { 0x20, 8 },
483 [SCxSR] = { 0x14, 16 },
484 [SCxRDR] = { 0x24, 8 },
485 [SCFCR] = { 0x18, 16 },
486 [SCFDR] = { 0x1c, 16 },
487 },
488 .fifosize = 64,
489 .overrun_reg = SCxSR,
490 .overrun_mask = SCIFA_ORER,
491 .sampling_rate_mask = SCI_SR(16),
492 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
493 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
494 },
495};
496
497#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
498
499/*
500 * The "offset" here is rather misleading, in that it refers to an enum
501 * value relative to the port mapping rather than the fixed offset
502 * itself, which needs to be manually retrieved from the platform's
503 * register map for the given port.
504 */
505static unsigned int sci_serial_in(struct uart_port *p, int offset)
506{
507 const struct plat_sci_reg *reg = sci_getreg(p, offset);
508
509 if (reg->size == 8)
510 return ioread8(p->membase + (reg->offset << p->regshift));
511 else if (reg->size == 16)
512 return ioread16(p->membase + (reg->offset << p->regshift));
513 else
514 WARN(1, "Invalid register access\n");
515
516 return 0;
517}
518
519static void sci_serial_out(struct uart_port *p, int offset, int value)
520{
521 const struct plat_sci_reg *reg = sci_getreg(p, offset);
522
523 if (reg->size == 8)
524 iowrite8(value, p->membase + (reg->offset << p->regshift));
525 else if (reg->size == 16)
526 iowrite16(value, p->membase + (reg->offset << p->regshift));
527 else
528 WARN(1, "Invalid register access\n");
529}
530
531static void sci_port_enable(struct sci_port *sci_port)
532{
533 unsigned int i;
534
535 if (!sci_port->port.dev)
536 return;
537
538 pm_runtime_get_sync(sci_port->port.dev);
539
540 for (i = 0; i < SCI_NUM_CLKS; i++) {
541 clk_prepare_enable(sci_port->clks[i]);
542 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
543 }
544 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
545}
546
547static void sci_port_disable(struct sci_port *sci_port)
548{
549 unsigned int i;
550
551 if (!sci_port->port.dev)
552 return;
553
554 for (i = SCI_NUM_CLKS; i-- > 0; )
555 clk_disable_unprepare(sci_port->clks[i]);
556
557 pm_runtime_put_sync(sci_port->port.dev);
558}
559
560static inline unsigned long port_rx_irq_mask(struct uart_port *port)
561{
562 /*
563 * Not all ports (such as SCIFA) will support REIE. Rather than
564 * special-casing the port type, we check the port initialization
565 * IRQ enable mask to see whether the IRQ is desired at all. If
566 * it's unset, it's logically inferred that there's no point in
567 * testing for it.
568 */
569 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
570}
571
572static void sci_start_tx(struct uart_port *port)
573{
574 struct sci_port *s = to_sci_port(port);
575 unsigned short ctrl;
576
577#ifdef CONFIG_SERIAL_SH_SCI_DMA
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
579 u16 new, scr = serial_port_in(port, SCSCR);
580 if (s->chan_tx)
581 new = scr | SCSCR_TDRQE;
582 else
583 new = scr & ~SCSCR_TDRQE;
584 if (new != scr)
585 serial_port_out(port, SCSCR, new);
586 }
587
588 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
589 dma_submit_error(s->cookie_tx)) {
590 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
591 /* Switch irq from SCIF to DMA */
592 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
593
594 s->cookie_tx = 0;
595 schedule_work(&s->work_tx);
596 }
597#endif
598
599 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
600 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
601 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
602 ctrl = serial_port_in(port, SCSCR);
603
604 /*
605 * For SCI, TE (transmit enable) must be set after setting TIE
606 * (transmit interrupt enable) or in the same instruction to start
607 * the transmit process.
608 */
609 if (port->type == PORT_SCI)
610 ctrl |= SCSCR_TE;
611
612 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
613 }
614}
615
616static void sci_stop_tx(struct uart_port *port)
617{
618 unsigned short ctrl;
619
620 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
621 ctrl = serial_port_in(port, SCSCR);
622
623 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
624 ctrl &= ~SCSCR_TDRQE;
625
626 ctrl &= ~SCSCR_TIE;
627
628 serial_port_out(port, SCSCR, ctrl);
629
630#ifdef CONFIG_SERIAL_SH_SCI_DMA
631 if (to_sci_port(port)->chan_tx &&
632 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
633 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
634 to_sci_port(port)->cookie_tx = -EINVAL;
635 }
636#endif
637}
638
639static void sci_start_rx(struct uart_port *port)
640{
641 unsigned short ctrl;
642
643 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
644
645 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
646 ctrl &= ~SCSCR_RDRQE;
647
648 serial_port_out(port, SCSCR, ctrl);
649}
650
651static void sci_stop_rx(struct uart_port *port)
652{
653 unsigned short ctrl;
654
655 ctrl = serial_port_in(port, SCSCR);
656
657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
658 ctrl &= ~SCSCR_RDRQE;
659
660 ctrl &= ~port_rx_irq_mask(port);
661
662 serial_port_out(port, SCSCR, ctrl);
663}
664
665static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
666{
667 if (port->type == PORT_SCI) {
668 /* Just store the mask */
669 serial_port_out(port, SCxSR, mask);
670 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
671 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
672 /* Only clear the status bits we want to clear */
673 serial_port_out(port, SCxSR,
674 serial_port_in(port, SCxSR) & mask);
675 } else {
676 /* Store the mask, clear parity/framing errors */
677 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
678 }
679}
680
681#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
682 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
683
684#ifdef CONFIG_CONSOLE_POLL
685static int sci_poll_get_char(struct uart_port *port)
686{
687 unsigned short status;
688 int c;
689
690 do {
691 status = serial_port_in(port, SCxSR);
692 if (status & SCxSR_ERRORS(port)) {
693 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
694 continue;
695 }
696 break;
697 } while (1);
698
699 if (!(status & SCxSR_RDxF(port)))
700 return NO_POLL_CHAR;
701
702 c = serial_port_in(port, SCxRDR);
703
704 /* Dummy read */
705 serial_port_in(port, SCxSR);
706 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
707
708 return c;
709}
710#endif
711
712static void sci_poll_put_char(struct uart_port *port, unsigned char c)
713{
714 unsigned short status;
715
716 do {
717 status = serial_port_in(port, SCxSR);
718 } while (!(status & SCxSR_TDxE(port)));
719
720 serial_port_out(port, SCxTDR, c);
721 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
722}
723#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
724 CONFIG_SERIAL_SH_SCI_EARLYCON */
725
726static void sci_init_pins(struct uart_port *port, unsigned int cflag)
727{
728 struct sci_port *s = to_sci_port(port);
729
730 /*
731 * Use port-specific handler if provided.
732 */
733 if (s->cfg->ops && s->cfg->ops->init_pins) {
734 s->cfg->ops->init_pins(port, cflag);
735 return;
736 }
737
738 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
739 u16 data = serial_port_in(port, SCPDR);
740 u16 ctrl = serial_port_in(port, SCPCR);
741
742 /* Enable RXD and TXD pin functions */
743 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
744 if (to_sci_port(port)->has_rtscts) {
745 /* RTS# is output, active low, unless autorts */
746 if (!(port->mctrl & TIOCM_RTS)) {
747 ctrl |= SCPCR_RTSC;
748 data |= SCPDR_RTSD;
749 } else if (!s->autorts) {
750 ctrl |= SCPCR_RTSC;
751 data &= ~SCPDR_RTSD;
752 } else {
753 /* Enable RTS# pin function */
754 ctrl &= ~SCPCR_RTSC;
755 }
756 /* Enable CTS# pin function */
757 ctrl &= ~SCPCR_CTSC;
758 }
759 serial_port_out(port, SCPDR, data);
760 serial_port_out(port, SCPCR, ctrl);
761 } else if (sci_getreg(port, SCSPTR)->size) {
762 u16 status = serial_port_in(port, SCSPTR);
763
764 /* RTS# is always output; and active low, unless autorts */
765 status |= SCSPTR_RTSIO;
766 if (!(port->mctrl & TIOCM_RTS))
767 status |= SCSPTR_RTSDT;
768 else if (!s->autorts)
769 status &= ~SCSPTR_RTSDT;
770 /* CTS# and SCK are inputs */
771 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
772 serial_port_out(port, SCSPTR, status);
773 }
774}
775
776static int sci_txfill(struct uart_port *port)
777{
778 struct sci_port *s = to_sci_port(port);
779 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
780 const struct plat_sci_reg *reg;
781
782 reg = sci_getreg(port, SCTFDR);
783 if (reg->size)
784 return serial_port_in(port, SCTFDR) & fifo_mask;
785
786 reg = sci_getreg(port, SCFDR);
787 if (reg->size)
788 return serial_port_in(port, SCFDR) >> 8;
789
790 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
791}
792
793static int sci_txroom(struct uart_port *port)
794{
795 return port->fifosize - sci_txfill(port);
796}
797
798static int sci_rxfill(struct uart_port *port)
799{
800 struct sci_port *s = to_sci_port(port);
801 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
802 const struct plat_sci_reg *reg;
803
804 reg = sci_getreg(port, SCRFDR);
805 if (reg->size)
806 return serial_port_in(port, SCRFDR) & fifo_mask;
807
808 reg = sci_getreg(port, SCFDR);
809 if (reg->size)
810 return serial_port_in(port, SCFDR) & fifo_mask;
811
812 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
813}
814
815/* ********************************************************************** *
816 * the interrupt related routines *
817 * ********************************************************************** */
818
819static void sci_transmit_chars(struct uart_port *port)
820{
821 struct circ_buf *xmit = &port->state->xmit;
822 unsigned int stopped = uart_tx_stopped(port);
823 unsigned short status;
824 unsigned short ctrl;
825 int count;
826
827 status = serial_port_in(port, SCxSR);
828 if (!(status & SCxSR_TDxE(port))) {
829 ctrl = serial_port_in(port, SCSCR);
830 if (uart_circ_empty(xmit))
831 ctrl &= ~SCSCR_TIE;
832 else
833 ctrl |= SCSCR_TIE;
834 serial_port_out(port, SCSCR, ctrl);
835 return;
836 }
837
838 count = sci_txroom(port);
839
840 do {
841 unsigned char c;
842
843 if (port->x_char) {
844 c = port->x_char;
845 port->x_char = 0;
846 } else if (!uart_circ_empty(xmit) && !stopped) {
847 c = xmit->buf[xmit->tail];
848 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
849 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) {
850 ctrl = serial_port_in(port, SCSCR);
851 ctrl &= ~SCSCR_TE;
852 serial_port_out(port, SCSCR, ctrl);
853 return;
854 } else {
855 break;
856 }
857
858 serial_port_out(port, SCxTDR, c);
859
860 port->icount.tx++;
861 } while (--count > 0);
862
863 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
864
865 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
866 uart_write_wakeup(port);
867 if (uart_circ_empty(xmit)) {
868 if (port->type == PORT_SCI) {
869 ctrl = serial_port_in(port, SCSCR);
870 ctrl &= ~SCSCR_TIE;
871 ctrl |= SCSCR_TEIE;
872 serial_port_out(port, SCSCR, ctrl);
873 }
874
875 sci_stop_tx(port);
876 }
877}
878
879static void sci_receive_chars(struct uart_port *port)
880{
881 struct tty_port *tport = &port->state->port;
882 int i, count, copied = 0;
883 unsigned short status;
884 unsigned char flag;
885
886 status = serial_port_in(port, SCxSR);
887 if (!(status & SCxSR_RDxF(port)))
888 return;
889
890 while (1) {
891 /* Don't copy more bytes than there is room for in the buffer */
892 count = tty_buffer_request_room(tport, sci_rxfill(port));
893
894 /* If for any reason we can't copy more data, we're done! */
895 if (count == 0)
896 break;
897
898 if (port->type == PORT_SCI) {
899 char c = serial_port_in(port, SCxRDR);
900 if (uart_handle_sysrq_char(port, c))
901 count = 0;
902 else
903 tty_insert_flip_char(tport, c, TTY_NORMAL);
904 } else {
905 for (i = 0; i < count; i++) {
906 char c;
907
908 if (port->type == PORT_SCIF ||
909 port->type == PORT_HSCIF) {
910 status = serial_port_in(port, SCxSR);
911 c = serial_port_in(port, SCxRDR);
912 } else {
913 c = serial_port_in(port, SCxRDR);
914 status = serial_port_in(port, SCxSR);
915 }
916 if (uart_handle_sysrq_char(port, c)) {
917 count--; i--;
918 continue;
919 }
920
921 /* Store data and status */
922 if (status & SCxSR_FER(port)) {
923 flag = TTY_FRAME;
924 port->icount.frame++;
925 } else if (status & SCxSR_PER(port)) {
926 flag = TTY_PARITY;
927 port->icount.parity++;
928 } else
929 flag = TTY_NORMAL;
930
931 tty_insert_flip_char(tport, c, flag);
932 }
933 }
934
935 serial_port_in(port, SCxSR); /* dummy read */
936 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
937
938 copied += count;
939 port->icount.rx += count;
940 }
941
942 if (copied) {
943 /* Tell the rest of the system the news. New characters! */
944 tty_flip_buffer_push(tport);
945 } else {
946 /* TTY buffers full; read from RX reg to prevent lockup */
947 serial_port_in(port, SCxRDR);
948 serial_port_in(port, SCxSR); /* dummy read */
949 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
950 }
951}
952
953static int sci_handle_errors(struct uart_port *port)
954{
955 int copied = 0;
956 unsigned short status = serial_port_in(port, SCxSR);
957 struct tty_port *tport = &port->state->port;
958 struct sci_port *s = to_sci_port(port);
959
960 /* Handle overruns */
961 if (status & s->params->overrun_mask) {
962 port->icount.overrun++;
963
964 /* overrun error */
965 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
966 copied++;
967 }
968
969 if (status & SCxSR_FER(port)) {
970 /* frame error */
971 port->icount.frame++;
972
973 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
974 copied++;
975 }
976
977 if (status & SCxSR_PER(port)) {
978 /* parity error */
979 port->icount.parity++;
980
981 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
982 copied++;
983 }
984
985 if (copied)
986 tty_flip_buffer_push(tport);
987
988 return copied;
989}
990
991static int sci_handle_fifo_overrun(struct uart_port *port)
992{
993 struct tty_port *tport = &port->state->port;
994 struct sci_port *s = to_sci_port(port);
995 const struct plat_sci_reg *reg;
996 int copied = 0;
997 u16 status;
998
999 reg = sci_getreg(port, s->params->overrun_reg);
1000 if (!reg->size)
1001 return 0;
1002
1003 status = serial_port_in(port, s->params->overrun_reg);
1004 if (status & s->params->overrun_mask) {
1005 status &= ~s->params->overrun_mask;
1006 serial_port_out(port, s->params->overrun_reg, status);
1007
1008 port->icount.overrun++;
1009
1010 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1011 tty_flip_buffer_push(tport);
1012 copied++;
1013 }
1014
1015 return copied;
1016}
1017
1018static int sci_handle_breaks(struct uart_port *port)
1019{
1020 int copied = 0;
1021 unsigned short status = serial_port_in(port, SCxSR);
1022 struct tty_port *tport = &port->state->port;
1023
1024 if (uart_handle_break(port))
1025 return 0;
1026
1027 if (status & SCxSR_BRK(port)) {
1028 port->icount.brk++;
1029
1030 /* Notify of BREAK */
1031 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1032 copied++;
1033 }
1034
1035 if (copied)
1036 tty_flip_buffer_push(tport);
1037
1038 copied += sci_handle_fifo_overrun(port);
1039
1040 return copied;
1041}
1042
1043static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1044{
1045 unsigned int bits;
1046
1047 if (rx_trig >= port->fifosize)
1048 rx_trig = port->fifosize - 1;
1049 if (rx_trig < 1)
1050 rx_trig = 1;
1051
1052 /* HSCIF can be set to an arbitrary level. */
1053 if (sci_getreg(port, HSRTRGR)->size) {
1054 serial_port_out(port, HSRTRGR, rx_trig);
1055 return rx_trig;
1056 }
1057
1058 switch (port->type) {
1059 case PORT_SCIF:
1060 if (rx_trig < 4) {
1061 bits = 0;
1062 rx_trig = 1;
1063 } else if (rx_trig < 8) {
1064 bits = SCFCR_RTRG0;
1065 rx_trig = 4;
1066 } else if (rx_trig < 14) {
1067 bits = SCFCR_RTRG1;
1068 rx_trig = 8;
1069 } else {
1070 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1071 rx_trig = 14;
1072 }
1073 break;
1074 case PORT_SCIFA:
1075 case PORT_SCIFB:
1076 if (rx_trig < 16) {
1077 bits = 0;
1078 rx_trig = 1;
1079 } else if (rx_trig < 32) {
1080 bits = SCFCR_RTRG0;
1081 rx_trig = 16;
1082 } else if (rx_trig < 48) {
1083 bits = SCFCR_RTRG1;
1084 rx_trig = 32;
1085 } else {
1086 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1087 rx_trig = 48;
1088 }
1089 break;
1090 default:
1091 WARN(1, "unknown FIFO configuration");
1092 return 1;
1093 }
1094
1095 serial_port_out(port, SCFCR,
1096 (serial_port_in(port, SCFCR) &
1097 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1098
1099 return rx_trig;
1100}
1101
1102static int scif_rtrg_enabled(struct uart_port *port)
1103{
1104 if (sci_getreg(port, HSRTRGR)->size)
1105 return serial_port_in(port, HSRTRGR) != 0;
1106 else
1107 return (serial_port_in(port, SCFCR) &
1108 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1109}
1110
1111static void rx_fifo_timer_fn(struct timer_list *t)
1112{
1113 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1114 struct uart_port *port = &s->port;
1115
1116 dev_dbg(port->dev, "Rx timed out\n");
1117 scif_set_rtrg(port, 1);
1118}
1119
1120static ssize_t rx_fifo_trigger_show(struct device *dev,
1121 struct device_attribute *attr, char *buf)
1122{
1123 struct uart_port *port = dev_get_drvdata(dev);
1124 struct sci_port *sci = to_sci_port(port);
1125
1126 return sprintf(buf, "%d\n", sci->rx_trigger);
1127}
1128
1129static ssize_t rx_fifo_trigger_store(struct device *dev,
1130 struct device_attribute *attr,
1131 const char *buf, size_t count)
1132{
1133 struct uart_port *port = dev_get_drvdata(dev);
1134 struct sci_port *sci = to_sci_port(port);
1135 int ret;
1136 long r;
1137
1138 ret = kstrtol(buf, 0, &r);
1139 if (ret)
1140 return ret;
1141
1142 sci->rx_trigger = scif_set_rtrg(port, r);
1143 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1144 scif_set_rtrg(port, 1);
1145
1146 return count;
1147}
1148
1149static DEVICE_ATTR_RW(rx_fifo_trigger);
1150
1151static ssize_t rx_fifo_timeout_show(struct device *dev,
1152 struct device_attribute *attr,
1153 char *buf)
1154{
1155 struct uart_port *port = dev_get_drvdata(dev);
1156 struct sci_port *sci = to_sci_port(port);
1157 int v;
1158
1159 if (port->type == PORT_HSCIF)
1160 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1161 else
1162 v = sci->rx_fifo_timeout;
1163
1164 return sprintf(buf, "%d\n", v);
1165}
1166
1167static ssize_t rx_fifo_timeout_store(struct device *dev,
1168 struct device_attribute *attr,
1169 const char *buf,
1170 size_t count)
1171{
1172 struct uart_port *port = dev_get_drvdata(dev);
1173 struct sci_port *sci = to_sci_port(port);
1174 int ret;
1175 long r;
1176
1177 ret = kstrtol(buf, 0, &r);
1178 if (ret)
1179 return ret;
1180
1181 if (port->type == PORT_HSCIF) {
1182 if (r < 0 || r > 3)
1183 return -EINVAL;
1184 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1185 } else {
1186 sci->rx_fifo_timeout = r;
1187 scif_set_rtrg(port, 1);
1188 if (r > 0)
1189 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1190 }
1191
1192 return count;
1193}
1194
1195static DEVICE_ATTR_RW(rx_fifo_timeout);
1196
1197
1198#ifdef CONFIG_SERIAL_SH_SCI_DMA
1199static void sci_dma_tx_complete(void *arg)
1200{
1201 struct sci_port *s = arg;
1202 struct uart_port *port = &s->port;
1203 struct circ_buf *xmit = &port->state->xmit;
1204 unsigned long flags;
1205
1206 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1207
1208 uart_port_lock_irqsave(port, &flags);
1209
1210 uart_xmit_advance(port, s->tx_dma_len);
1211
1212 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1213 uart_write_wakeup(port);
1214
1215 if (!uart_circ_empty(xmit)) {
1216 s->cookie_tx = 0;
1217 schedule_work(&s->work_tx);
1218 } else {
1219 s->cookie_tx = -EINVAL;
1220 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1221 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1222 u16 ctrl = serial_port_in(port, SCSCR);
1223 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1224 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1225 /* Switch irq from DMA to SCIF */
1226 dmaengine_pause(s->chan_tx_saved);
1227 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1228 }
1229 }
1230 }
1231
1232 uart_port_unlock_irqrestore(port, flags);
1233}
1234
1235/* Locking: called with port lock held */
1236static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1237{
1238 struct uart_port *port = &s->port;
1239 struct tty_port *tport = &port->state->port;
1240 int copied;
1241
1242 copied = tty_insert_flip_string(tport, buf, count);
1243 if (copied < count)
1244 port->icount.buf_overrun++;
1245
1246 port->icount.rx += copied;
1247
1248 return copied;
1249}
1250
1251static int sci_dma_rx_find_active(struct sci_port *s)
1252{
1253 unsigned int i;
1254
1255 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1256 if (s->active_rx == s->cookie_rx[i])
1257 return i;
1258
1259 return -1;
1260}
1261
1262static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1263{
1264 unsigned int i;
1265
1266 s->chan_rx = NULL;
1267 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1268 s->cookie_rx[i] = -EINVAL;
1269 s->active_rx = 0;
1270}
1271
1272static void sci_dma_rx_release(struct sci_port *s)
1273{
1274 struct dma_chan *chan = s->chan_rx_saved;
1275
1276 s->chan_rx_saved = NULL;
1277 sci_dma_rx_chan_invalidate(s);
1278 dmaengine_terminate_sync(chan);
1279 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1280 sg_dma_address(&s->sg_rx[0]));
1281 dma_release_channel(chan);
1282}
1283
1284static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1285{
1286 long sec = usec / 1000000;
1287 long nsec = (usec % 1000000) * 1000;
1288 ktime_t t = ktime_set(sec, nsec);
1289
1290 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1291}
1292
1293static void sci_dma_rx_reenable_irq(struct sci_port *s)
1294{
1295 struct uart_port *port = &s->port;
1296 u16 scr;
1297
1298 /* Direct new serial port interrupts back to CPU */
1299 scr = serial_port_in(port, SCSCR);
1300 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1301 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1302 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1303 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1304 scif_set_rtrg(port, s->rx_trigger);
1305 else
1306 scr &= ~SCSCR_RDRQE;
1307 }
1308 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1309}
1310
1311static void sci_dma_rx_complete(void *arg)
1312{
1313 struct sci_port *s = arg;
1314 struct dma_chan *chan = s->chan_rx;
1315 struct uart_port *port = &s->port;
1316 struct dma_async_tx_descriptor *desc;
1317 unsigned long flags;
1318 int active, count = 0;
1319
1320 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1321 s->active_rx);
1322
1323 uart_port_lock_irqsave(port, &flags);
1324
1325 active = sci_dma_rx_find_active(s);
1326 if (active >= 0)
1327 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1328
1329 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1330
1331 if (count)
1332 tty_flip_buffer_push(&port->state->port);
1333
1334 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1335 DMA_DEV_TO_MEM,
1336 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1337 if (!desc)
1338 goto fail;
1339
1340 desc->callback = sci_dma_rx_complete;
1341 desc->callback_param = s;
1342 s->cookie_rx[active] = dmaengine_submit(desc);
1343 if (dma_submit_error(s->cookie_rx[active]))
1344 goto fail;
1345
1346 s->active_rx = s->cookie_rx[!active];
1347
1348 dma_async_issue_pending(chan);
1349
1350 uart_port_unlock_irqrestore(port, flags);
1351 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1352 __func__, s->cookie_rx[active], active, s->active_rx);
1353 return;
1354
1355fail:
1356 uart_port_unlock_irqrestore(port, flags);
1357 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1358 /* Switch to PIO */
1359 uart_port_lock_irqsave(port, &flags);
1360 dmaengine_terminate_async(chan);
1361 sci_dma_rx_chan_invalidate(s);
1362 sci_dma_rx_reenable_irq(s);
1363 uart_port_unlock_irqrestore(port, flags);
1364}
1365
1366static void sci_dma_tx_release(struct sci_port *s)
1367{
1368 struct dma_chan *chan = s->chan_tx_saved;
1369
1370 cancel_work_sync(&s->work_tx);
1371 s->chan_tx_saved = s->chan_tx = NULL;
1372 s->cookie_tx = -EINVAL;
1373 dmaengine_terminate_sync(chan);
1374 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1375 DMA_TO_DEVICE);
1376 dma_release_channel(chan);
1377}
1378
1379static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1380{
1381 struct dma_chan *chan = s->chan_rx;
1382 struct uart_port *port = &s->port;
1383 unsigned long flags;
1384 int i;
1385
1386 for (i = 0; i < 2; i++) {
1387 struct scatterlist *sg = &s->sg_rx[i];
1388 struct dma_async_tx_descriptor *desc;
1389
1390 desc = dmaengine_prep_slave_sg(chan,
1391 sg, 1, DMA_DEV_TO_MEM,
1392 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1393 if (!desc)
1394 goto fail;
1395
1396 desc->callback = sci_dma_rx_complete;
1397 desc->callback_param = s;
1398 s->cookie_rx[i] = dmaengine_submit(desc);
1399 if (dma_submit_error(s->cookie_rx[i]))
1400 goto fail;
1401
1402 }
1403
1404 s->active_rx = s->cookie_rx[0];
1405
1406 dma_async_issue_pending(chan);
1407 return 0;
1408
1409fail:
1410 /* Switch to PIO */
1411 if (!port_lock_held)
1412 uart_port_lock_irqsave(port, &flags);
1413 if (i)
1414 dmaengine_terminate_async(chan);
1415 sci_dma_rx_chan_invalidate(s);
1416 sci_start_rx(port);
1417 if (!port_lock_held)
1418 uart_port_unlock_irqrestore(port, flags);
1419 return -EAGAIN;
1420}
1421
1422static void sci_dma_tx_work_fn(struct work_struct *work)
1423{
1424 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1425 struct dma_async_tx_descriptor *desc;
1426 struct dma_chan *chan = s->chan_tx;
1427 struct uart_port *port = &s->port;
1428 struct circ_buf *xmit = &port->state->xmit;
1429 unsigned long flags;
1430 dma_addr_t buf;
1431 int head, tail;
1432
1433 /*
1434 * DMA is idle now.
1435 * Port xmit buffer is already mapped, and it is one page... Just adjust
1436 * offsets and lengths. Since it is a circular buffer, we have to
1437 * transmit till the end, and then the rest. Take the port lock to get a
1438 * consistent xmit buffer state.
1439 */
1440 uart_port_lock_irq(port);
1441 head = xmit->head;
1442 tail = xmit->tail;
1443 buf = s->tx_dma_addr + tail;
1444 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE);
1445 if (!s->tx_dma_len) {
1446 /* Transmit buffer has been flushed */
1447 uart_port_unlock_irq(port);
1448 return;
1449 }
1450
1451 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1452 DMA_MEM_TO_DEV,
1453 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1454 if (!desc) {
1455 uart_port_unlock_irq(port);
1456 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1457 goto switch_to_pio;
1458 }
1459
1460 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1461 DMA_TO_DEVICE);
1462
1463 desc->callback = sci_dma_tx_complete;
1464 desc->callback_param = s;
1465 s->cookie_tx = dmaengine_submit(desc);
1466 if (dma_submit_error(s->cookie_tx)) {
1467 uart_port_unlock_irq(port);
1468 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1469 goto switch_to_pio;
1470 }
1471
1472 uart_port_unlock_irq(port);
1473 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1474 __func__, xmit->buf, tail, head, s->cookie_tx);
1475
1476 dma_async_issue_pending(chan);
1477 return;
1478
1479switch_to_pio:
1480 uart_port_lock_irqsave(port, &flags);
1481 s->chan_tx = NULL;
1482 sci_start_tx(port);
1483 uart_port_unlock_irqrestore(port, flags);
1484 return;
1485}
1486
1487static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1488{
1489 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1490 struct dma_chan *chan = s->chan_rx;
1491 struct uart_port *port = &s->port;
1492 struct dma_tx_state state;
1493 enum dma_status status;
1494 unsigned long flags;
1495 unsigned int read;
1496 int active, count;
1497
1498 dev_dbg(port->dev, "DMA Rx timed out\n");
1499
1500 uart_port_lock_irqsave(port, &flags);
1501
1502 active = sci_dma_rx_find_active(s);
1503 if (active < 0) {
1504 uart_port_unlock_irqrestore(port, flags);
1505 return HRTIMER_NORESTART;
1506 }
1507
1508 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1509 if (status == DMA_COMPLETE) {
1510 uart_port_unlock_irqrestore(port, flags);
1511 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1512 s->active_rx, active);
1513
1514 /* Let packet complete handler take care of the packet */
1515 return HRTIMER_NORESTART;
1516 }
1517
1518 dmaengine_pause(chan);
1519
1520 /*
1521 * sometimes DMA transfer doesn't stop even if it is stopped and
1522 * data keeps on coming until transaction is complete so check
1523 * for DMA_COMPLETE again
1524 * Let packet complete handler take care of the packet
1525 */
1526 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1527 if (status == DMA_COMPLETE) {
1528 uart_port_unlock_irqrestore(port, flags);
1529 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1530 return HRTIMER_NORESTART;
1531 }
1532
1533 /* Handle incomplete DMA receive */
1534 dmaengine_terminate_async(s->chan_rx);
1535 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1536
1537 if (read) {
1538 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1539 if (count)
1540 tty_flip_buffer_push(&port->state->port);
1541 }
1542
1543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1544 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1545 sci_dma_rx_submit(s, true);
1546
1547 sci_dma_rx_reenable_irq(s);
1548
1549 uart_port_unlock_irqrestore(port, flags);
1550
1551 return HRTIMER_NORESTART;
1552}
1553
1554static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1555 enum dma_transfer_direction dir)
1556{
1557 struct dma_chan *chan;
1558 struct dma_slave_config cfg;
1559 int ret;
1560
1561 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1562 if (IS_ERR(chan)) {
1563 dev_dbg(port->dev, "dma_request_chan failed\n");
1564 return NULL;
1565 }
1566
1567 memset(&cfg, 0, sizeof(cfg));
1568 cfg.direction = dir;
1569 cfg.dst_addr = port->mapbase +
1570 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1571 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1572 cfg.src_addr = port->mapbase +
1573 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1574 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1575
1576 ret = dmaengine_slave_config(chan, &cfg);
1577 if (ret) {
1578 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1579 dma_release_channel(chan);
1580 return NULL;
1581 }
1582
1583 return chan;
1584}
1585
1586static void sci_request_dma(struct uart_port *port)
1587{
1588 struct sci_port *s = to_sci_port(port);
1589 struct dma_chan *chan;
1590
1591 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1592
1593 /*
1594 * DMA on console may interfere with Kernel log messages which use
1595 * plain putchar(). So, simply don't use it with a console.
1596 */
1597 if (uart_console(port))
1598 return;
1599
1600 if (!port->dev->of_node)
1601 return;
1602
1603 s->cookie_tx = -EINVAL;
1604
1605 /*
1606 * Don't request a dma channel if no channel was specified
1607 * in the device tree.
1608 */
1609 if (!of_property_present(port->dev->of_node, "dmas"))
1610 return;
1611
1612 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1613 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1614 if (chan) {
1615 /* UART circular tx buffer is an aligned page. */
1616 s->tx_dma_addr = dma_map_single(chan->device->dev,
1617 port->state->xmit.buf,
1618 UART_XMIT_SIZE,
1619 DMA_TO_DEVICE);
1620 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1621 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1622 dma_release_channel(chan);
1623 } else {
1624 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1625 __func__, UART_XMIT_SIZE,
1626 port->state->xmit.buf, &s->tx_dma_addr);
1627
1628 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1629 s->chan_tx_saved = s->chan_tx = chan;
1630 }
1631 }
1632
1633 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1634 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1635 if (chan) {
1636 unsigned int i;
1637 dma_addr_t dma;
1638 void *buf;
1639
1640 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1641 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1642 &dma, GFP_KERNEL);
1643 if (!buf) {
1644 dev_warn(port->dev,
1645 "Failed to allocate Rx dma buffer, using PIO\n");
1646 dma_release_channel(chan);
1647 return;
1648 }
1649
1650 for (i = 0; i < 2; i++) {
1651 struct scatterlist *sg = &s->sg_rx[i];
1652
1653 sg_init_table(sg, 1);
1654 s->rx_buf[i] = buf;
1655 sg_dma_address(sg) = dma;
1656 sg_dma_len(sg) = s->buf_len_rx;
1657
1658 buf += s->buf_len_rx;
1659 dma += s->buf_len_rx;
1660 }
1661
1662 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1663 s->rx_timer.function = sci_dma_rx_timer_fn;
1664
1665 s->chan_rx_saved = s->chan_rx = chan;
1666
1667 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1668 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1669 sci_dma_rx_submit(s, false);
1670 }
1671}
1672
1673static void sci_free_dma(struct uart_port *port)
1674{
1675 struct sci_port *s = to_sci_port(port);
1676
1677 if (s->chan_tx_saved)
1678 sci_dma_tx_release(s);
1679 if (s->chan_rx_saved)
1680 sci_dma_rx_release(s);
1681}
1682
1683static void sci_flush_buffer(struct uart_port *port)
1684{
1685 struct sci_port *s = to_sci_port(port);
1686
1687 /*
1688 * In uart_flush_buffer(), the xmit circular buffer has just been
1689 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1690 * pending transfers
1691 */
1692 s->tx_dma_len = 0;
1693 if (s->chan_tx) {
1694 dmaengine_terminate_async(s->chan_tx);
1695 s->cookie_tx = -EINVAL;
1696 }
1697}
1698#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1699static inline void sci_request_dma(struct uart_port *port)
1700{
1701}
1702
1703static inline void sci_free_dma(struct uart_port *port)
1704{
1705}
1706
1707#define sci_flush_buffer NULL
1708#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1709
1710static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1711{
1712 struct uart_port *port = ptr;
1713 struct sci_port *s = to_sci_port(port);
1714
1715#ifdef CONFIG_SERIAL_SH_SCI_DMA
1716 if (s->chan_rx) {
1717 u16 scr = serial_port_in(port, SCSCR);
1718 u16 ssr = serial_port_in(port, SCxSR);
1719
1720 /* Disable future Rx interrupts */
1721 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1722 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1723 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1724 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1725 scif_set_rtrg(port, 1);
1726 scr |= SCSCR_RIE;
1727 } else {
1728 scr |= SCSCR_RDRQE;
1729 }
1730 } else {
1731 if (sci_dma_rx_submit(s, false) < 0)
1732 goto handle_pio;
1733
1734 scr &= ~SCSCR_RIE;
1735 }
1736 serial_port_out(port, SCSCR, scr);
1737 /* Clear current interrupt */
1738 serial_port_out(port, SCxSR,
1739 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1740 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1741 jiffies, s->rx_timeout);
1742 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1743
1744 return IRQ_HANDLED;
1745 }
1746
1747handle_pio:
1748#endif
1749
1750 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1751 if (!scif_rtrg_enabled(port))
1752 scif_set_rtrg(port, s->rx_trigger);
1753
1754 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1755 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1756 }
1757
1758 /* I think sci_receive_chars has to be called irrespective
1759 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1760 * to be disabled?
1761 */
1762 sci_receive_chars(port);
1763
1764 return IRQ_HANDLED;
1765}
1766
1767static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1768{
1769 struct uart_port *port = ptr;
1770 unsigned long flags;
1771
1772 uart_port_lock_irqsave(port, &flags);
1773 sci_transmit_chars(port);
1774 uart_port_unlock_irqrestore(port, flags);
1775
1776 return IRQ_HANDLED;
1777}
1778
1779static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1780{
1781 struct uart_port *port = ptr;
1782 unsigned long flags;
1783 unsigned short ctrl;
1784
1785 if (port->type != PORT_SCI)
1786 return sci_tx_interrupt(irq, ptr);
1787
1788 uart_port_lock_irqsave(port, &flags);
1789 ctrl = serial_port_in(port, SCSCR);
1790 ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
1791 serial_port_out(port, SCSCR, ctrl);
1792 uart_port_unlock_irqrestore(port, flags);
1793
1794 return IRQ_HANDLED;
1795}
1796
1797static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1798{
1799 struct uart_port *port = ptr;
1800
1801 /* Handle BREAKs */
1802 sci_handle_breaks(port);
1803
1804 /* drop invalid character received before break was detected */
1805 serial_port_in(port, SCxRDR);
1806
1807 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1808
1809 return IRQ_HANDLED;
1810}
1811
1812static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1813{
1814 struct uart_port *port = ptr;
1815 struct sci_port *s = to_sci_port(port);
1816
1817 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1818 /* Break and Error interrupts are muxed */
1819 unsigned short ssr_status = serial_port_in(port, SCxSR);
1820
1821 /* Break Interrupt */
1822 if (ssr_status & SCxSR_BRK(port))
1823 sci_br_interrupt(irq, ptr);
1824
1825 /* Break only? */
1826 if (!(ssr_status & SCxSR_ERRORS(port)))
1827 return IRQ_HANDLED;
1828 }
1829
1830 /* Handle errors */
1831 if (port->type == PORT_SCI) {
1832 if (sci_handle_errors(port)) {
1833 /* discard character in rx buffer */
1834 serial_port_in(port, SCxSR);
1835 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1836 }
1837 } else {
1838 sci_handle_fifo_overrun(port);
1839 if (!s->chan_rx)
1840 sci_receive_chars(port);
1841 }
1842
1843 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1844
1845 /* Kick the transmission */
1846 if (!s->chan_tx)
1847 sci_tx_interrupt(irq, ptr);
1848
1849 return IRQ_HANDLED;
1850}
1851
1852static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1853{
1854 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1855 struct uart_port *port = ptr;
1856 struct sci_port *s = to_sci_port(port);
1857 irqreturn_t ret = IRQ_NONE;
1858
1859 ssr_status = serial_port_in(port, SCxSR);
1860 scr_status = serial_port_in(port, SCSCR);
1861 if (s->params->overrun_reg == SCxSR)
1862 orer_status = ssr_status;
1863 else if (sci_getreg(port, s->params->overrun_reg)->size)
1864 orer_status = serial_port_in(port, s->params->overrun_reg);
1865
1866 err_enabled = scr_status & port_rx_irq_mask(port);
1867
1868 /* Tx Interrupt */
1869 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1870 !s->chan_tx)
1871 ret = sci_tx_interrupt(irq, ptr);
1872
1873 /*
1874 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1875 * DR flags
1876 */
1877 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1878 (scr_status & SCSCR_RIE))
1879 ret = sci_rx_interrupt(irq, ptr);
1880
1881 /* Error Interrupt */
1882 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1883 ret = sci_er_interrupt(irq, ptr);
1884
1885 /* Break Interrupt */
1886 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1887 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1888 ret = sci_br_interrupt(irq, ptr);
1889
1890 /* Overrun Interrupt */
1891 if (orer_status & s->params->overrun_mask) {
1892 sci_handle_fifo_overrun(port);
1893 ret = IRQ_HANDLED;
1894 }
1895
1896 return ret;
1897}
1898
1899static const struct sci_irq_desc {
1900 const char *desc;
1901 irq_handler_t handler;
1902} sci_irq_desc[] = {
1903 /*
1904 * Split out handlers, the default case.
1905 */
1906 [SCIx_ERI_IRQ] = {
1907 .desc = "rx err",
1908 .handler = sci_er_interrupt,
1909 },
1910
1911 [SCIx_RXI_IRQ] = {
1912 .desc = "rx full",
1913 .handler = sci_rx_interrupt,
1914 },
1915
1916 [SCIx_TXI_IRQ] = {
1917 .desc = "tx empty",
1918 .handler = sci_tx_interrupt,
1919 },
1920
1921 [SCIx_BRI_IRQ] = {
1922 .desc = "break",
1923 .handler = sci_br_interrupt,
1924 },
1925
1926 [SCIx_DRI_IRQ] = {
1927 .desc = "rx ready",
1928 .handler = sci_rx_interrupt,
1929 },
1930
1931 [SCIx_TEI_IRQ] = {
1932 .desc = "tx end",
1933 .handler = sci_tx_end_interrupt,
1934 },
1935
1936 /*
1937 * Special muxed handler.
1938 */
1939 [SCIx_MUX_IRQ] = {
1940 .desc = "mux",
1941 .handler = sci_mpxed_interrupt,
1942 },
1943};
1944
1945static int sci_request_irq(struct sci_port *port)
1946{
1947 struct uart_port *up = &port->port;
1948 int i, j, w, ret = 0;
1949
1950 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1951 const struct sci_irq_desc *desc;
1952 int irq;
1953
1954 /* Check if already registered (muxed) */
1955 for (w = 0; w < i; w++)
1956 if (port->irqs[w] == port->irqs[i])
1957 w = i + 1;
1958 if (w > i)
1959 continue;
1960
1961 if (SCIx_IRQ_IS_MUXED(port)) {
1962 i = SCIx_MUX_IRQ;
1963 irq = up->irq;
1964 } else {
1965 irq = port->irqs[i];
1966
1967 /*
1968 * Certain port types won't support all of the
1969 * available interrupt sources.
1970 */
1971 if (unlikely(irq < 0))
1972 continue;
1973 }
1974
1975 desc = sci_irq_desc + i;
1976 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1977 dev_name(up->dev), desc->desc);
1978 if (!port->irqstr[j]) {
1979 ret = -ENOMEM;
1980 goto out_nomem;
1981 }
1982
1983 ret = request_irq(irq, desc->handler, up->irqflags,
1984 port->irqstr[j], port);
1985 if (unlikely(ret)) {
1986 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1987 goto out_noirq;
1988 }
1989 }
1990
1991 return 0;
1992
1993out_noirq:
1994 while (--i >= 0)
1995 free_irq(port->irqs[i], port);
1996
1997out_nomem:
1998 while (--j >= 0)
1999 kfree(port->irqstr[j]);
2000
2001 return ret;
2002}
2003
2004static void sci_free_irq(struct sci_port *port)
2005{
2006 int i, j;
2007
2008 /*
2009 * Intentionally in reverse order so we iterate over the muxed
2010 * IRQ first.
2011 */
2012 for (i = 0; i < SCIx_NR_IRQS; i++) {
2013 int irq = port->irqs[i];
2014
2015 /*
2016 * Certain port types won't support all of the available
2017 * interrupt sources.
2018 */
2019 if (unlikely(irq < 0))
2020 continue;
2021
2022 /* Check if already freed (irq was muxed) */
2023 for (j = 0; j < i; j++)
2024 if (port->irqs[j] == irq)
2025 j = i + 1;
2026 if (j > i)
2027 continue;
2028
2029 free_irq(port->irqs[i], port);
2030 kfree(port->irqstr[i]);
2031
2032 if (SCIx_IRQ_IS_MUXED(port)) {
2033 /* If there's only one IRQ, we're done. */
2034 return;
2035 }
2036 }
2037}
2038
2039static unsigned int sci_tx_empty(struct uart_port *port)
2040{
2041 unsigned short status = serial_port_in(port, SCxSR);
2042 unsigned short in_tx_fifo = sci_txfill(port);
2043
2044 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2045}
2046
2047static void sci_set_rts(struct uart_port *port, bool state)
2048{
2049 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2050 u16 data = serial_port_in(port, SCPDR);
2051
2052 /* Active low */
2053 if (state)
2054 data &= ~SCPDR_RTSD;
2055 else
2056 data |= SCPDR_RTSD;
2057 serial_port_out(port, SCPDR, data);
2058
2059 /* RTS# is output */
2060 serial_port_out(port, SCPCR,
2061 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2062 } else if (sci_getreg(port, SCSPTR)->size) {
2063 u16 ctrl = serial_port_in(port, SCSPTR);
2064
2065 /* Active low */
2066 if (state)
2067 ctrl &= ~SCSPTR_RTSDT;
2068 else
2069 ctrl |= SCSPTR_RTSDT;
2070 serial_port_out(port, SCSPTR, ctrl);
2071 }
2072}
2073
2074static bool sci_get_cts(struct uart_port *port)
2075{
2076 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2077 /* Active low */
2078 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2079 } else if (sci_getreg(port, SCSPTR)->size) {
2080 /* Active low */
2081 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2082 }
2083
2084 return true;
2085}
2086
2087/*
2088 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2089 * CTS/RTS is supported in hardware by at least one port and controlled
2090 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2091 * handled via the ->init_pins() op, which is a bit of a one-way street,
2092 * lacking any ability to defer pin control -- this will later be
2093 * converted over to the GPIO framework).
2094 *
2095 * Other modes (such as loopback) are supported generically on certain
2096 * port types, but not others. For these it's sufficient to test for the
2097 * existence of the support register and simply ignore the port type.
2098 */
2099static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2100{
2101 struct sci_port *s = to_sci_port(port);
2102
2103 if (mctrl & TIOCM_LOOP) {
2104 const struct plat_sci_reg *reg;
2105
2106 /*
2107 * Standard loopback mode for SCFCR ports.
2108 */
2109 reg = sci_getreg(port, SCFCR);
2110 if (reg->size)
2111 serial_port_out(port, SCFCR,
2112 serial_port_in(port, SCFCR) |
2113 SCFCR_LOOP);
2114 }
2115
2116 mctrl_gpio_set(s->gpios, mctrl);
2117
2118 if (!s->has_rtscts)
2119 return;
2120
2121 if (!(mctrl & TIOCM_RTS)) {
2122 /* Disable Auto RTS */
2123 serial_port_out(port, SCFCR,
2124 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2125
2126 /* Clear RTS */
2127 sci_set_rts(port, 0);
2128 } else if (s->autorts) {
2129 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2130 /* Enable RTS# pin function */
2131 serial_port_out(port, SCPCR,
2132 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2133 }
2134
2135 /* Enable Auto RTS */
2136 serial_port_out(port, SCFCR,
2137 serial_port_in(port, SCFCR) | SCFCR_MCE);
2138 } else {
2139 /* Set RTS */
2140 sci_set_rts(port, 1);
2141 }
2142}
2143
2144static unsigned int sci_get_mctrl(struct uart_port *port)
2145{
2146 struct sci_port *s = to_sci_port(port);
2147 struct mctrl_gpios *gpios = s->gpios;
2148 unsigned int mctrl = 0;
2149
2150 mctrl_gpio_get(gpios, &mctrl);
2151
2152 /*
2153 * CTS/RTS is handled in hardware when supported, while nothing
2154 * else is wired up.
2155 */
2156 if (s->autorts) {
2157 if (sci_get_cts(port))
2158 mctrl |= TIOCM_CTS;
2159 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2160 mctrl |= TIOCM_CTS;
2161 }
2162 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2163 mctrl |= TIOCM_DSR;
2164 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2165 mctrl |= TIOCM_CAR;
2166
2167 return mctrl;
2168}
2169
2170static void sci_enable_ms(struct uart_port *port)
2171{
2172 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2173}
2174
2175static void sci_break_ctl(struct uart_port *port, int break_state)
2176{
2177 unsigned short scscr, scsptr;
2178 unsigned long flags;
2179
2180 /* check whether the port has SCSPTR */
2181 if (!sci_getreg(port, SCSPTR)->size) {
2182 /*
2183 * Not supported by hardware. Most parts couple break and rx
2184 * interrupts together, with break detection always enabled.
2185 */
2186 return;
2187 }
2188
2189 uart_port_lock_irqsave(port, &flags);
2190 scsptr = serial_port_in(port, SCSPTR);
2191 scscr = serial_port_in(port, SCSCR);
2192
2193 if (break_state == -1) {
2194 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2195 scscr &= ~SCSCR_TE;
2196 } else {
2197 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2198 scscr |= SCSCR_TE;
2199 }
2200
2201 serial_port_out(port, SCSPTR, scsptr);
2202 serial_port_out(port, SCSCR, scscr);
2203 uart_port_unlock_irqrestore(port, flags);
2204}
2205
2206static int sci_startup(struct uart_port *port)
2207{
2208 struct sci_port *s = to_sci_port(port);
2209 int ret;
2210
2211 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2212
2213 sci_request_dma(port);
2214
2215 ret = sci_request_irq(s);
2216 if (unlikely(ret < 0)) {
2217 sci_free_dma(port);
2218 return ret;
2219 }
2220
2221 return 0;
2222}
2223
2224static void sci_shutdown(struct uart_port *port)
2225{
2226 struct sci_port *s = to_sci_port(port);
2227 unsigned long flags;
2228 u16 scr;
2229
2230 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2231
2232 s->autorts = false;
2233 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2234
2235 uart_port_lock_irqsave(port, &flags);
2236 sci_stop_rx(port);
2237 sci_stop_tx(port);
2238 /*
2239 * Stop RX and TX, disable related interrupts, keep clock source
2240 * and HSCIF TOT bits
2241 */
2242 scr = serial_port_in(port, SCSCR);
2243 serial_port_out(port, SCSCR, scr &
2244 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2245 uart_port_unlock_irqrestore(port, flags);
2246
2247#ifdef CONFIG_SERIAL_SH_SCI_DMA
2248 if (s->chan_rx_saved) {
2249 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2250 port->line);
2251 hrtimer_cancel(&s->rx_timer);
2252 }
2253#endif
2254
2255 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2256 del_timer_sync(&s->rx_fifo_timer);
2257 sci_free_irq(s);
2258 sci_free_dma(port);
2259}
2260
2261static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2262 unsigned int *srr)
2263{
2264 unsigned long freq = s->clk_rates[SCI_SCK];
2265 int err, min_err = INT_MAX;
2266 unsigned int sr;
2267
2268 if (s->port.type != PORT_HSCIF)
2269 freq *= 2;
2270
2271 for_each_sr(sr, s) {
2272 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2273 if (abs(err) >= abs(min_err))
2274 continue;
2275
2276 min_err = err;
2277 *srr = sr - 1;
2278
2279 if (!err)
2280 break;
2281 }
2282
2283 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2284 *srr + 1);
2285 return min_err;
2286}
2287
2288static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2289 unsigned long freq, unsigned int *dlr,
2290 unsigned int *srr)
2291{
2292 int err, min_err = INT_MAX;
2293 unsigned int sr, dl;
2294
2295 if (s->port.type != PORT_HSCIF)
2296 freq *= 2;
2297
2298 for_each_sr(sr, s) {
2299 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2300 dl = clamp(dl, 1U, 65535U);
2301
2302 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2303 if (abs(err) >= abs(min_err))
2304 continue;
2305
2306 min_err = err;
2307 *dlr = dl;
2308 *srr = sr - 1;
2309
2310 if (!err)
2311 break;
2312 }
2313
2314 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2315 min_err, *dlr, *srr + 1);
2316 return min_err;
2317}
2318
2319/* calculate sample rate, BRR, and clock select */
2320static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2321 unsigned int *brr, unsigned int *srr,
2322 unsigned int *cks)
2323{
2324 unsigned long freq = s->clk_rates[SCI_FCK];
2325 unsigned int sr, br, prediv, scrate, c;
2326 int err, min_err = INT_MAX;
2327
2328 if (s->port.type != PORT_HSCIF)
2329 freq *= 2;
2330
2331 /*
2332 * Find the combination of sample rate and clock select with the
2333 * smallest deviation from the desired baud rate.
2334 * Prefer high sample rates to maximise the receive margin.
2335 *
2336 * M: Receive margin (%)
2337 * N: Ratio of bit rate to clock (N = sampling rate)
2338 * D: Clock duty (D = 0 to 1.0)
2339 * L: Frame length (L = 9 to 12)
2340 * F: Absolute value of clock frequency deviation
2341 *
2342 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2343 * (|D - 0.5| / N * (1 + F))|
2344 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2345 */
2346 for_each_sr(sr, s) {
2347 for (c = 0; c <= 3; c++) {
2348 /* integerized formulas from HSCIF documentation */
2349 prediv = sr << (2 * c + 1);
2350
2351 /*
2352 * We need to calculate:
2353 *
2354 * br = freq / (prediv * bps) clamped to [1..256]
2355 * err = freq / (br * prediv) - bps
2356 *
2357 * Watch out for overflow when calculating the desired
2358 * sampling clock rate!
2359 */
2360 if (bps > UINT_MAX / prediv)
2361 break;
2362
2363 scrate = prediv * bps;
2364 br = DIV_ROUND_CLOSEST(freq, scrate);
2365 br = clamp(br, 1U, 256U);
2366
2367 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2368 if (abs(err) >= abs(min_err))
2369 continue;
2370
2371 min_err = err;
2372 *brr = br - 1;
2373 *srr = sr - 1;
2374 *cks = c;
2375
2376 if (!err)
2377 goto found;
2378 }
2379 }
2380
2381found:
2382 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2383 min_err, *brr, *srr + 1, *cks);
2384 return min_err;
2385}
2386
2387static void sci_reset(struct uart_port *port)
2388{
2389 const struct plat_sci_reg *reg;
2390 unsigned int status;
2391 struct sci_port *s = to_sci_port(port);
2392
2393 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2394
2395 reg = sci_getreg(port, SCFCR);
2396 if (reg->size)
2397 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2398
2399 sci_clear_SCxSR(port,
2400 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2401 SCxSR_BREAK_CLEAR(port));
2402 if (sci_getreg(port, SCLSR)->size) {
2403 status = serial_port_in(port, SCLSR);
2404 status &= ~(SCLSR_TO | SCLSR_ORER);
2405 serial_port_out(port, SCLSR, status);
2406 }
2407
2408 if (s->rx_trigger > 1) {
2409 if (s->rx_fifo_timeout) {
2410 scif_set_rtrg(port, 1);
2411 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2412 } else {
2413 if (port->type == PORT_SCIFA ||
2414 port->type == PORT_SCIFB)
2415 scif_set_rtrg(port, 1);
2416 else
2417 scif_set_rtrg(port, s->rx_trigger);
2418 }
2419 }
2420}
2421
2422static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2423 const struct ktermios *old)
2424{
2425 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2426 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2427 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2428 struct sci_port *s = to_sci_port(port);
2429 const struct plat_sci_reg *reg;
2430 int min_err = INT_MAX, err;
2431 unsigned long max_freq = 0;
2432 int best_clk = -1;
2433 unsigned long flags;
2434
2435 if ((termios->c_cflag & CSIZE) == CS7) {
2436 smr_val |= SCSMR_CHR;
2437 } else {
2438 termios->c_cflag &= ~CSIZE;
2439 termios->c_cflag |= CS8;
2440 }
2441 if (termios->c_cflag & PARENB)
2442 smr_val |= SCSMR_PE;
2443 if (termios->c_cflag & PARODD)
2444 smr_val |= SCSMR_PE | SCSMR_ODD;
2445 if (termios->c_cflag & CSTOPB)
2446 smr_val |= SCSMR_STOP;
2447
2448 /*
2449 * earlyprintk comes here early on with port->uartclk set to zero.
2450 * the clock framework is not up and running at this point so here
2451 * we assume that 115200 is the maximum baud rate. please note that
2452 * the baud rate is not programmed during earlyprintk - it is assumed
2453 * that the previous boot loader has enabled required clocks and
2454 * setup the baud rate generator hardware for us already.
2455 */
2456 if (!port->uartclk) {
2457 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2458 goto done;
2459 }
2460
2461 for (i = 0; i < SCI_NUM_CLKS; i++)
2462 max_freq = max(max_freq, s->clk_rates[i]);
2463
2464 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2465 if (!baud)
2466 goto done;
2467
2468 /*
2469 * There can be multiple sources for the sampling clock. Find the one
2470 * that gives us the smallest deviation from the desired baud rate.
2471 */
2472
2473 /* Optional Undivided External Clock */
2474 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2475 port->type != PORT_SCIFB) {
2476 err = sci_sck_calc(s, baud, &srr1);
2477 if (abs(err) < abs(min_err)) {
2478 best_clk = SCI_SCK;
2479 scr_val = SCSCR_CKE1;
2480 sccks = SCCKS_CKS;
2481 min_err = err;
2482 srr = srr1;
2483 if (!err)
2484 goto done;
2485 }
2486 }
2487
2488 /* Optional BRG Frequency Divided External Clock */
2489 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2490 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2491 &srr1);
2492 if (abs(err) < abs(min_err)) {
2493 best_clk = SCI_SCIF_CLK;
2494 scr_val = SCSCR_CKE1;
2495 sccks = 0;
2496 min_err = err;
2497 dl = dl1;
2498 srr = srr1;
2499 if (!err)
2500 goto done;
2501 }
2502 }
2503
2504 /* Optional BRG Frequency Divided Internal Clock */
2505 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2506 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2507 &srr1);
2508 if (abs(err) < abs(min_err)) {
2509 best_clk = SCI_BRG_INT;
2510 scr_val = SCSCR_CKE1;
2511 sccks = SCCKS_XIN;
2512 min_err = err;
2513 dl = dl1;
2514 srr = srr1;
2515 if (!min_err)
2516 goto done;
2517 }
2518 }
2519
2520 /* Divided Functional Clock using standard Bit Rate Register */
2521 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2522 if (abs(err) < abs(min_err)) {
2523 best_clk = SCI_FCK;
2524 scr_val = 0;
2525 min_err = err;
2526 brr = brr1;
2527 srr = srr1;
2528 cks = cks1;
2529 }
2530
2531done:
2532 if (best_clk >= 0)
2533 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2534 s->clks[best_clk], baud, min_err);
2535
2536 sci_port_enable(s);
2537
2538 /*
2539 * Program the optional External Baud Rate Generator (BRG) first.
2540 * It controls the mux to select (H)SCK or frequency divided clock.
2541 */
2542 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2543 serial_port_out(port, SCDL, dl);
2544 serial_port_out(port, SCCKS, sccks);
2545 }
2546
2547 uart_port_lock_irqsave(port, &flags);
2548
2549 sci_reset(port);
2550
2551 uart_update_timeout(port, termios->c_cflag, baud);
2552
2553 /* byte size and parity */
2554 bits = tty_get_frame_size(termios->c_cflag);
2555
2556 if (sci_getreg(port, SEMR)->size)
2557 serial_port_out(port, SEMR, 0);
2558
2559 if (best_clk >= 0) {
2560 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2561 switch (srr + 1) {
2562 case 5: smr_val |= SCSMR_SRC_5; break;
2563 case 7: smr_val |= SCSMR_SRC_7; break;
2564 case 11: smr_val |= SCSMR_SRC_11; break;
2565 case 13: smr_val |= SCSMR_SRC_13; break;
2566 case 16: smr_val |= SCSMR_SRC_16; break;
2567 case 17: smr_val |= SCSMR_SRC_17; break;
2568 case 19: smr_val |= SCSMR_SRC_19; break;
2569 case 27: smr_val |= SCSMR_SRC_27; break;
2570 }
2571 smr_val |= cks;
2572 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2573 serial_port_out(port, SCSMR, smr_val);
2574 serial_port_out(port, SCBRR, brr);
2575 if (sci_getreg(port, HSSRR)->size) {
2576 unsigned int hssrr = srr | HSCIF_SRE;
2577 /* Calculate deviation from intended rate at the
2578 * center of the last stop bit in sampling clocks.
2579 */
2580 int last_stop = bits * 2 - 1;
2581 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2582 (int)(srr + 1),
2583 2 * (int)baud);
2584
2585 if (abs(deviation) >= 2) {
2586 /* At least two sampling clocks off at the
2587 * last stop bit; we can increase the error
2588 * margin by shifting the sampling point.
2589 */
2590 int shift = clamp(deviation / 2, -8, 7);
2591
2592 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2593 HSCIF_SRHP_MASK;
2594 hssrr |= HSCIF_SRDE;
2595 }
2596 serial_port_out(port, HSSRR, hssrr);
2597 }
2598
2599 /* Wait one bit interval */
2600 udelay((1000000 + (baud - 1)) / baud);
2601 } else {
2602 /* Don't touch the bit rate configuration */
2603 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2604 smr_val |= serial_port_in(port, SCSMR) &
2605 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2606 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2607 serial_port_out(port, SCSMR, smr_val);
2608 }
2609
2610 sci_init_pins(port, termios->c_cflag);
2611
2612 port->status &= ~UPSTAT_AUTOCTS;
2613 s->autorts = false;
2614 reg = sci_getreg(port, SCFCR);
2615 if (reg->size) {
2616 unsigned short ctrl = serial_port_in(port, SCFCR);
2617
2618 if ((port->flags & UPF_HARD_FLOW) &&
2619 (termios->c_cflag & CRTSCTS)) {
2620 /* There is no CTS interrupt to restart the hardware */
2621 port->status |= UPSTAT_AUTOCTS;
2622 /* MCE is enabled when RTS is raised */
2623 s->autorts = true;
2624 }
2625
2626 /*
2627 * As we've done a sci_reset() above, ensure we don't
2628 * interfere with the FIFOs while toggling MCE. As the
2629 * reset values could still be set, simply mask them out.
2630 */
2631 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2632
2633 serial_port_out(port, SCFCR, ctrl);
2634 }
2635 if (port->flags & UPF_HARD_FLOW) {
2636 /* Refresh (Auto) RTS */
2637 sci_set_mctrl(port, port->mctrl);
2638 }
2639
2640 /*
2641 * For SCI, TE (transmit enable) must be set after setting TIE
2642 * (transmit interrupt enable) or in the same instruction to
2643 * start the transmitting process. So skip setting TE here for SCI.
2644 */
2645 if (port->type != PORT_SCI)
2646 scr_val |= SCSCR_TE;
2647 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2648 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2649 if ((srr + 1 == 5) &&
2650 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2651 /*
2652 * In asynchronous mode, when the sampling rate is 1/5, first
2653 * received data may become invalid on some SCIFA and SCIFB.
2654 * To avoid this problem wait more than 1 serial data time (1
2655 * bit time x serial data number) after setting SCSCR.RE = 1.
2656 */
2657 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2658 }
2659
2660 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2661 s->rx_frame = (10000 * bits) / (baud / 100);
2662#ifdef CONFIG_SERIAL_SH_SCI_DMA
2663 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2664#endif
2665
2666 if ((termios->c_cflag & CREAD) != 0)
2667 sci_start_rx(port);
2668
2669 uart_port_unlock_irqrestore(port, flags);
2670
2671 sci_port_disable(s);
2672
2673 if (UART_ENABLE_MS(port, termios->c_cflag))
2674 sci_enable_ms(port);
2675}
2676
2677static void sci_pm(struct uart_port *port, unsigned int state,
2678 unsigned int oldstate)
2679{
2680 struct sci_port *sci_port = to_sci_port(port);
2681
2682 switch (state) {
2683 case UART_PM_STATE_OFF:
2684 sci_port_disable(sci_port);
2685 break;
2686 default:
2687 sci_port_enable(sci_port);
2688 break;
2689 }
2690}
2691
2692static const char *sci_type(struct uart_port *port)
2693{
2694 switch (port->type) {
2695 case PORT_IRDA:
2696 return "irda";
2697 case PORT_SCI:
2698 return "sci";
2699 case PORT_SCIF:
2700 return "scif";
2701 case PORT_SCIFA:
2702 return "scifa";
2703 case PORT_SCIFB:
2704 return "scifb";
2705 case PORT_HSCIF:
2706 return "hscif";
2707 }
2708
2709 return NULL;
2710}
2711
2712static int sci_remap_port(struct uart_port *port)
2713{
2714 struct sci_port *sport = to_sci_port(port);
2715
2716 /*
2717 * Nothing to do if there's already an established membase.
2718 */
2719 if (port->membase)
2720 return 0;
2721
2722 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2723 port->membase = ioremap(port->mapbase, sport->reg_size);
2724 if (unlikely(!port->membase)) {
2725 dev_err(port->dev, "can't remap port#%d\n", port->line);
2726 return -ENXIO;
2727 }
2728 } else {
2729 /*
2730 * For the simple (and majority of) cases where we don't
2731 * need to do any remapping, just cast the cookie
2732 * directly.
2733 */
2734 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2735 }
2736
2737 return 0;
2738}
2739
2740static void sci_release_port(struct uart_port *port)
2741{
2742 struct sci_port *sport = to_sci_port(port);
2743
2744 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2745 iounmap(port->membase);
2746 port->membase = NULL;
2747 }
2748
2749 release_mem_region(port->mapbase, sport->reg_size);
2750}
2751
2752static int sci_request_port(struct uart_port *port)
2753{
2754 struct resource *res;
2755 struct sci_port *sport = to_sci_port(port);
2756 int ret;
2757
2758 res = request_mem_region(port->mapbase, sport->reg_size,
2759 dev_name(port->dev));
2760 if (unlikely(res == NULL)) {
2761 dev_err(port->dev, "request_mem_region failed.");
2762 return -EBUSY;
2763 }
2764
2765 ret = sci_remap_port(port);
2766 if (unlikely(ret != 0)) {
2767 release_resource(res);
2768 return ret;
2769 }
2770
2771 return 0;
2772}
2773
2774static void sci_config_port(struct uart_port *port, int flags)
2775{
2776 if (flags & UART_CONFIG_TYPE) {
2777 struct sci_port *sport = to_sci_port(port);
2778
2779 port->type = sport->cfg->type;
2780 sci_request_port(port);
2781 }
2782}
2783
2784static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2785{
2786 if (ser->baud_base < 2400)
2787 /* No paper tape reader for Mitch.. */
2788 return -EINVAL;
2789
2790 return 0;
2791}
2792
2793static const struct uart_ops sci_uart_ops = {
2794 .tx_empty = sci_tx_empty,
2795 .set_mctrl = sci_set_mctrl,
2796 .get_mctrl = sci_get_mctrl,
2797 .start_tx = sci_start_tx,
2798 .stop_tx = sci_stop_tx,
2799 .stop_rx = sci_stop_rx,
2800 .enable_ms = sci_enable_ms,
2801 .break_ctl = sci_break_ctl,
2802 .startup = sci_startup,
2803 .shutdown = sci_shutdown,
2804 .flush_buffer = sci_flush_buffer,
2805 .set_termios = sci_set_termios,
2806 .pm = sci_pm,
2807 .type = sci_type,
2808 .release_port = sci_release_port,
2809 .request_port = sci_request_port,
2810 .config_port = sci_config_port,
2811 .verify_port = sci_verify_port,
2812#ifdef CONFIG_CONSOLE_POLL
2813 .poll_get_char = sci_poll_get_char,
2814 .poll_put_char = sci_poll_put_char,
2815#endif
2816};
2817
2818static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2819{
2820 const char *clk_names[] = {
2821 [SCI_FCK] = "fck",
2822 [SCI_SCK] = "sck",
2823 [SCI_BRG_INT] = "brg_int",
2824 [SCI_SCIF_CLK] = "scif_clk",
2825 };
2826 struct clk *clk;
2827 unsigned int i;
2828
2829 if (sci_port->cfg->type == PORT_HSCIF)
2830 clk_names[SCI_SCK] = "hsck";
2831
2832 for (i = 0; i < SCI_NUM_CLKS; i++) {
2833 clk = devm_clk_get_optional(dev, clk_names[i]);
2834 if (IS_ERR(clk))
2835 return PTR_ERR(clk);
2836
2837 if (!clk && i == SCI_FCK) {
2838 /*
2839 * Not all SH platforms declare a clock lookup entry
2840 * for SCI devices, in which case we need to get the
2841 * global "peripheral_clk" clock.
2842 */
2843 clk = devm_clk_get(dev, "peripheral_clk");
2844 if (IS_ERR(clk))
2845 return dev_err_probe(dev, PTR_ERR(clk),
2846 "failed to get %s\n",
2847 clk_names[i]);
2848 }
2849
2850 if (!clk)
2851 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2852 else
2853 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2854 clk, clk_get_rate(clk));
2855 sci_port->clks[i] = clk;
2856 }
2857 return 0;
2858}
2859
2860static const struct sci_port_params *
2861sci_probe_regmap(const struct plat_sci_port *cfg)
2862{
2863 unsigned int regtype;
2864
2865 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2866 return &sci_port_params[cfg->regtype];
2867
2868 switch (cfg->type) {
2869 case PORT_SCI:
2870 regtype = SCIx_SCI_REGTYPE;
2871 break;
2872 case PORT_IRDA:
2873 regtype = SCIx_IRDA_REGTYPE;
2874 break;
2875 case PORT_SCIFA:
2876 regtype = SCIx_SCIFA_REGTYPE;
2877 break;
2878 case PORT_SCIFB:
2879 regtype = SCIx_SCIFB_REGTYPE;
2880 break;
2881 case PORT_SCIF:
2882 /*
2883 * The SH-4 is a bit of a misnomer here, although that's
2884 * where this particular port layout originated. This
2885 * configuration (or some slight variation thereof)
2886 * remains the dominant model for all SCIFs.
2887 */
2888 regtype = SCIx_SH4_SCIF_REGTYPE;
2889 break;
2890 case PORT_HSCIF:
2891 regtype = SCIx_HSCIF_REGTYPE;
2892 break;
2893 default:
2894 pr_err("Can't probe register map for given port\n");
2895 return NULL;
2896 }
2897
2898 return &sci_port_params[regtype];
2899}
2900
2901static int sci_init_single(struct platform_device *dev,
2902 struct sci_port *sci_port, unsigned int index,
2903 const struct plat_sci_port *p, bool early)
2904{
2905 struct uart_port *port = &sci_port->port;
2906 const struct resource *res;
2907 unsigned int i;
2908 int ret;
2909
2910 sci_port->cfg = p;
2911
2912 port->ops = &sci_uart_ops;
2913 port->iotype = UPIO_MEM;
2914 port->line = index;
2915 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2916
2917 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2918 if (res == NULL)
2919 return -ENOMEM;
2920
2921 port->mapbase = res->start;
2922 sci_port->reg_size = resource_size(res);
2923
2924 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2925 if (i)
2926 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2927 else
2928 sci_port->irqs[i] = platform_get_irq(dev, i);
2929 }
2930
2931 /*
2932 * The fourth interrupt on SCI port is transmit end interrupt, so
2933 * shuffle the interrupts.
2934 */
2935 if (p->type == PORT_SCI)
2936 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
2937
2938 /* The SCI generates several interrupts. They can be muxed together or
2939 * connected to different interrupt lines. In the muxed case only one
2940 * interrupt resource is specified as there is only one interrupt ID.
2941 * In the non-muxed case, up to 6 interrupt signals might be generated
2942 * from the SCI, however those signals might have their own individual
2943 * interrupt ID numbers, or muxed together with another interrupt.
2944 */
2945 if (sci_port->irqs[0] < 0)
2946 return -ENXIO;
2947
2948 if (sci_port->irqs[1] < 0)
2949 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2950 sci_port->irqs[i] = sci_port->irqs[0];
2951
2952 sci_port->params = sci_probe_regmap(p);
2953 if (unlikely(sci_port->params == NULL))
2954 return -EINVAL;
2955
2956 switch (p->type) {
2957 case PORT_SCIFB:
2958 sci_port->rx_trigger = 48;
2959 break;
2960 case PORT_HSCIF:
2961 sci_port->rx_trigger = 64;
2962 break;
2963 case PORT_SCIFA:
2964 sci_port->rx_trigger = 32;
2965 break;
2966 case PORT_SCIF:
2967 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2968 /* RX triggering not implemented for this IP */
2969 sci_port->rx_trigger = 1;
2970 else
2971 sci_port->rx_trigger = 8;
2972 break;
2973 default:
2974 sci_port->rx_trigger = 1;
2975 break;
2976 }
2977
2978 sci_port->rx_fifo_timeout = 0;
2979 sci_port->hscif_tot = 0;
2980
2981 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2982 * match the SoC datasheet, this should be investigated. Let platform
2983 * data override the sampling rate for now.
2984 */
2985 sci_port->sampling_rate_mask = p->sampling_rate
2986 ? SCI_SR(p->sampling_rate)
2987 : sci_port->params->sampling_rate_mask;
2988
2989 if (!early) {
2990 ret = sci_init_clocks(sci_port, &dev->dev);
2991 if (ret < 0)
2992 return ret;
2993
2994 port->dev = &dev->dev;
2995
2996 pm_runtime_enable(&dev->dev);
2997 }
2998
2999 port->type = p->type;
3000 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3001 port->fifosize = sci_port->params->fifosize;
3002
3003 if (port->type == PORT_SCI && !dev->dev.of_node) {
3004 if (sci_port->reg_size >= 0x20)
3005 port->regshift = 2;
3006 else
3007 port->regshift = 1;
3008 }
3009
3010 /*
3011 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3012 * for the multi-IRQ ports, which is where we are primarily
3013 * concerned with the shutdown path synchronization.
3014 *
3015 * For the muxed case there's nothing more to do.
3016 */
3017 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3018 port->irqflags = 0;
3019
3020 port->serial_in = sci_serial_in;
3021 port->serial_out = sci_serial_out;
3022
3023 return 0;
3024}
3025
3026static void sci_cleanup_single(struct sci_port *port)
3027{
3028 pm_runtime_disable(port->port.dev);
3029}
3030
3031#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3032 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3033static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3034{
3035 sci_poll_put_char(port, ch);
3036}
3037
3038/*
3039 * Print a string to the serial port trying not to disturb
3040 * any possible real use of the port...
3041 */
3042static void serial_console_write(struct console *co, const char *s,
3043 unsigned count)
3044{
3045 struct sci_port *sci_port = &sci_ports[co->index];
3046 struct uart_port *port = &sci_port->port;
3047 unsigned short bits, ctrl, ctrl_temp;
3048 unsigned long flags;
3049 int locked = 1;
3050
3051 if (port->sysrq)
3052 locked = 0;
3053 else if (oops_in_progress)
3054 locked = uart_port_trylock_irqsave(port, &flags);
3055 else
3056 uart_port_lock_irqsave(port, &flags);
3057
3058 /* first save SCSCR then disable interrupts, keep clock source */
3059 ctrl = serial_port_in(port, SCSCR);
3060 ctrl_temp = SCSCR_RE | SCSCR_TE |
3061 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3062 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3063 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3064
3065 uart_console_write(port, s, count, serial_console_putchar);
3066
3067 /* wait until fifo is empty and last bit has been transmitted */
3068 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3069 while ((serial_port_in(port, SCxSR) & bits) != bits)
3070 cpu_relax();
3071
3072 /* restore the SCSCR */
3073 serial_port_out(port, SCSCR, ctrl);
3074
3075 if (locked)
3076 uart_port_unlock_irqrestore(port, flags);
3077}
3078
3079static int serial_console_setup(struct console *co, char *options)
3080{
3081 struct sci_port *sci_port;
3082 struct uart_port *port;
3083 int baud = 115200;
3084 int bits = 8;
3085 int parity = 'n';
3086 int flow = 'n';
3087 int ret;
3088
3089 /*
3090 * Refuse to handle any bogus ports.
3091 */
3092 if (co->index < 0 || co->index >= SCI_NPORTS)
3093 return -ENODEV;
3094
3095 sci_port = &sci_ports[co->index];
3096 port = &sci_port->port;
3097
3098 /*
3099 * Refuse to handle uninitialized ports.
3100 */
3101 if (!port->ops)
3102 return -ENODEV;
3103
3104 ret = sci_remap_port(port);
3105 if (unlikely(ret != 0))
3106 return ret;
3107
3108 if (options)
3109 uart_parse_options(options, &baud, &parity, &bits, &flow);
3110
3111 return uart_set_options(port, co, baud, parity, bits, flow);
3112}
3113
3114static struct console serial_console = {
3115 .name = "ttySC",
3116 .device = uart_console_device,
3117 .write = serial_console_write,
3118 .setup = serial_console_setup,
3119 .flags = CON_PRINTBUFFER,
3120 .index = -1,
3121 .data = &sci_uart_driver,
3122};
3123
3124#ifdef CONFIG_SUPERH
3125static char early_serial_buf[32];
3126
3127static int early_serial_console_setup(struct console *co, char *options)
3128{
3129 /*
3130 * This early console is always registered using the earlyprintk=
3131 * parameter, which does not call add_preferred_console(). Thus
3132 * @options is always NULL and the options for this early console
3133 * are passed using a custom buffer.
3134 */
3135 WARN_ON(options);
3136
3137 return serial_console_setup(co, early_serial_buf);
3138}
3139
3140static struct console early_serial_console = {
3141 .name = "early_ttySC",
3142 .write = serial_console_write,
3143 .setup = early_serial_console_setup,
3144 .flags = CON_PRINTBUFFER,
3145 .index = -1,
3146};
3147
3148static int sci_probe_earlyprintk(struct platform_device *pdev)
3149{
3150 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3151
3152 if (early_serial_console.data)
3153 return -EEXIST;
3154
3155 early_serial_console.index = pdev->id;
3156
3157 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3158
3159 if (!strstr(early_serial_buf, "keep"))
3160 early_serial_console.flags |= CON_BOOT;
3161
3162 register_console(&early_serial_console);
3163 return 0;
3164}
3165#endif
3166
3167#define SCI_CONSOLE (&serial_console)
3168
3169#else
3170static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3171{
3172 return -EINVAL;
3173}
3174
3175#define SCI_CONSOLE NULL
3176
3177#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3178
3179static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3180
3181static DEFINE_MUTEX(sci_uart_registration_lock);
3182static struct uart_driver sci_uart_driver = {
3183 .owner = THIS_MODULE,
3184 .driver_name = "sci",
3185 .dev_name = "ttySC",
3186 .major = SCI_MAJOR,
3187 .minor = SCI_MINOR_START,
3188 .nr = SCI_NPORTS,
3189 .cons = SCI_CONSOLE,
3190};
3191
3192static void sci_remove(struct platform_device *dev)
3193{
3194 struct sci_port *port = platform_get_drvdata(dev);
3195 unsigned int type = port->port.type; /* uart_remove_... clears it */
3196
3197 sci_ports_in_use &= ~BIT(port->port.line);
3198 uart_remove_one_port(&sci_uart_driver, &port->port);
3199
3200 sci_cleanup_single(port);
3201
3202 if (port->port.fifosize > 1)
3203 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3204 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3205 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3206}
3207
3208
3209#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3210#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3211#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3212
3213static const struct of_device_id of_sci_match[] __maybe_unused = {
3214 /* SoC-specific types */
3215 {
3216 .compatible = "renesas,scif-r7s72100",
3217 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3218 },
3219 {
3220 .compatible = "renesas,scif-r7s9210",
3221 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3222 },
3223 {
3224 .compatible = "renesas,scif-r9a07g044",
3225 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3226 },
3227 /* Family-specific types */
3228 {
3229 .compatible = "renesas,rcar-gen1-scif",
3230 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3231 }, {
3232 .compatible = "renesas,rcar-gen2-scif",
3233 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3234 }, {
3235 .compatible = "renesas,rcar-gen3-scif",
3236 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3237 }, {
3238 .compatible = "renesas,rcar-gen4-scif",
3239 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3240 },
3241 /* Generic types */
3242 {
3243 .compatible = "renesas,scif",
3244 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3245 }, {
3246 .compatible = "renesas,scifa",
3247 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3248 }, {
3249 .compatible = "renesas,scifb",
3250 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3251 }, {
3252 .compatible = "renesas,hscif",
3253 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3254 }, {
3255 .compatible = "renesas,sci",
3256 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3257 }, {
3258 /* Terminator */
3259 },
3260};
3261MODULE_DEVICE_TABLE(of, of_sci_match);
3262
3263static void sci_reset_control_assert(void *data)
3264{
3265 reset_control_assert(data);
3266}
3267
3268static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3269 unsigned int *dev_id)
3270{
3271 struct device_node *np = pdev->dev.of_node;
3272 struct reset_control *rstc;
3273 struct plat_sci_port *p;
3274 struct sci_port *sp;
3275 const void *data;
3276 int id, ret;
3277
3278 if (!IS_ENABLED(CONFIG_OF) || !np)
3279 return ERR_PTR(-EINVAL);
3280
3281 data = of_device_get_match_data(&pdev->dev);
3282
3283 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3284 if (IS_ERR(rstc))
3285 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3286 "failed to get reset ctrl\n"));
3287
3288 ret = reset_control_deassert(rstc);
3289 if (ret) {
3290 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3291 return ERR_PTR(ret);
3292 }
3293
3294 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3295 if (ret) {
3296 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3297 ret);
3298 return ERR_PTR(ret);
3299 }
3300
3301 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3302 if (!p)
3303 return ERR_PTR(-ENOMEM);
3304
3305 /* Get the line number from the aliases node. */
3306 id = of_alias_get_id(np, "serial");
3307 if (id < 0 && ~sci_ports_in_use)
3308 id = ffz(sci_ports_in_use);
3309 if (id < 0) {
3310 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3311 return ERR_PTR(-EINVAL);
3312 }
3313 if (id >= ARRAY_SIZE(sci_ports)) {
3314 dev_err(&pdev->dev, "serial%d out of range\n", id);
3315 return ERR_PTR(-EINVAL);
3316 }
3317
3318 sp = &sci_ports[id];
3319 *dev_id = id;
3320
3321 p->type = SCI_OF_TYPE(data);
3322 p->regtype = SCI_OF_REGTYPE(data);
3323
3324 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3325
3326 return p;
3327}
3328
3329static int sci_probe_single(struct platform_device *dev,
3330 unsigned int index,
3331 struct plat_sci_port *p,
3332 struct sci_port *sciport)
3333{
3334 int ret;
3335
3336 /* Sanity check */
3337 if (unlikely(index >= SCI_NPORTS)) {
3338 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3339 index+1, SCI_NPORTS);
3340 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3341 return -EINVAL;
3342 }
3343 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3344 if (sci_ports_in_use & BIT(index))
3345 return -EBUSY;
3346
3347 mutex_lock(&sci_uart_registration_lock);
3348 if (!sci_uart_driver.state) {
3349 ret = uart_register_driver(&sci_uart_driver);
3350 if (ret) {
3351 mutex_unlock(&sci_uart_registration_lock);
3352 return ret;
3353 }
3354 }
3355 mutex_unlock(&sci_uart_registration_lock);
3356
3357 ret = sci_init_single(dev, sciport, index, p, false);
3358 if (ret)
3359 return ret;
3360
3361 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3362 if (IS_ERR(sciport->gpios))
3363 return PTR_ERR(sciport->gpios);
3364
3365 if (sciport->has_rtscts) {
3366 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3367 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3368 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3369 return -EINVAL;
3370 }
3371 sciport->port.flags |= UPF_HARD_FLOW;
3372 }
3373
3374 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3375 if (ret) {
3376 sci_cleanup_single(sciport);
3377 return ret;
3378 }
3379
3380 return 0;
3381}
3382
3383static int sci_probe(struct platform_device *dev)
3384{
3385 struct plat_sci_port *p;
3386 struct sci_port *sp;
3387 unsigned int dev_id;
3388 int ret;
3389
3390 /*
3391 * If we've come here via earlyprintk initialization, head off to
3392 * the special early probe. We don't have sufficient device state
3393 * to make it beyond this yet.
3394 */
3395#ifdef CONFIG_SUPERH
3396 if (is_sh_early_platform_device(dev))
3397 return sci_probe_earlyprintk(dev);
3398#endif
3399
3400 if (dev->dev.of_node) {
3401 p = sci_parse_dt(dev, &dev_id);
3402 if (IS_ERR(p))
3403 return PTR_ERR(p);
3404 } else {
3405 p = dev->dev.platform_data;
3406 if (p == NULL) {
3407 dev_err(&dev->dev, "no platform data supplied\n");
3408 return -EINVAL;
3409 }
3410
3411 dev_id = dev->id;
3412 }
3413
3414 sp = &sci_ports[dev_id];
3415 platform_set_drvdata(dev, sp);
3416
3417 ret = sci_probe_single(dev, dev_id, p, sp);
3418 if (ret)
3419 return ret;
3420
3421 if (sp->port.fifosize > 1) {
3422 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3423 if (ret)
3424 return ret;
3425 }
3426 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3427 sp->port.type == PORT_HSCIF) {
3428 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3429 if (ret) {
3430 if (sp->port.fifosize > 1) {
3431 device_remove_file(&dev->dev,
3432 &dev_attr_rx_fifo_trigger);
3433 }
3434 return ret;
3435 }
3436 }
3437
3438#ifdef CONFIG_SH_STANDARD_BIOS
3439 sh_bios_gdb_detach();
3440#endif
3441
3442 sci_ports_in_use |= BIT(dev_id);
3443 return 0;
3444}
3445
3446static __maybe_unused int sci_suspend(struct device *dev)
3447{
3448 struct sci_port *sport = dev_get_drvdata(dev);
3449
3450 if (sport)
3451 uart_suspend_port(&sci_uart_driver, &sport->port);
3452
3453 return 0;
3454}
3455
3456static __maybe_unused int sci_resume(struct device *dev)
3457{
3458 struct sci_port *sport = dev_get_drvdata(dev);
3459
3460 if (sport)
3461 uart_resume_port(&sci_uart_driver, &sport->port);
3462
3463 return 0;
3464}
3465
3466static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3467
3468static struct platform_driver sci_driver = {
3469 .probe = sci_probe,
3470 .remove_new = sci_remove,
3471 .driver = {
3472 .name = "sh-sci",
3473 .pm = &sci_dev_pm_ops,
3474 .of_match_table = of_match_ptr(of_sci_match),
3475 },
3476};
3477
3478static int __init sci_init(void)
3479{
3480 pr_info("%s\n", banner);
3481
3482 return platform_driver_register(&sci_driver);
3483}
3484
3485static void __exit sci_exit(void)
3486{
3487 platform_driver_unregister(&sci_driver);
3488
3489 if (sci_uart_driver.state)
3490 uart_unregister_driver(&sci_uart_driver);
3491}
3492
3493#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3494sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3495 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3496#endif
3497#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3498static struct plat_sci_port port_cfg __initdata;
3499
3500static int __init early_console_setup(struct earlycon_device *device,
3501 int type)
3502{
3503 if (!device->port.membase)
3504 return -ENODEV;
3505
3506 device->port.serial_in = sci_serial_in;
3507 device->port.serial_out = sci_serial_out;
3508 device->port.type = type;
3509 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3510 port_cfg.type = type;
3511 sci_ports[0].cfg = &port_cfg;
3512 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3513 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3514 sci_serial_out(&sci_ports[0].port, SCSCR,
3515 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3516
3517 device->con->write = serial_console_write;
3518 return 0;
3519}
3520static int __init sci_early_console_setup(struct earlycon_device *device,
3521 const char *opt)
3522{
3523 return early_console_setup(device, PORT_SCI);
3524}
3525static int __init scif_early_console_setup(struct earlycon_device *device,
3526 const char *opt)
3527{
3528 return early_console_setup(device, PORT_SCIF);
3529}
3530static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3531 const char *opt)
3532{
3533 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3534 return early_console_setup(device, PORT_SCIF);
3535}
3536
3537static int __init scifa_early_console_setup(struct earlycon_device *device,
3538 const char *opt)
3539{
3540 return early_console_setup(device, PORT_SCIFA);
3541}
3542static int __init scifb_early_console_setup(struct earlycon_device *device,
3543 const char *opt)
3544{
3545 return early_console_setup(device, PORT_SCIFB);
3546}
3547static int __init hscif_early_console_setup(struct earlycon_device *device,
3548 const char *opt)
3549{
3550 return early_console_setup(device, PORT_HSCIF);
3551}
3552
3553OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3554OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3555OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3556OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3557OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3558OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3559OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3560#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3561
3562module_init(sci_init);
3563module_exit(sci_exit);
3564
3565MODULE_LICENSE("GPL");
3566MODULE_ALIAS("platform:sh-sci");
3567MODULE_AUTHOR("Paul Mundt");
3568MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
22#undef DEBUG
23
24#include <linux/clk.h>
25#include <linux/console.h>
26#include <linux/ctype.h>
27#include <linux/cpufreq.h>
28#include <linux/delay.h>
29#include <linux/dmaengine.h>
30#include <linux/dma-mapping.h>
31#include <linux/err.h>
32#include <linux/errno.h>
33#include <linux/init.h>
34#include <linux/interrupt.h>
35#include <linux/ioport.h>
36#include <linux/ktime.h>
37#include <linux/major.h>
38#include <linux/module.h>
39#include <linux/mm.h>
40#include <linux/of.h>
41#include <linux/of_device.h>
42#include <linux/platform_device.h>
43#include <linux/pm_runtime.h>
44#include <linux/scatterlist.h>
45#include <linux/serial.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
48#include <linux/slab.h>
49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
54
55#ifdef CONFIG_SUPERH
56#include <asm/sh_bios.h>
57#endif
58
59#include "serial_mctrl_gpio.h"
60#include "sh-sci.h"
61
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85};
86
87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103struct plat_sci_reg {
104 u8 offset, size;
105};
106
107struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
115};
116
117struct sci_port {
118 struct uart_port port;
119
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
126
127 /* Clocks */
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
130
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
133
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136
137#ifdef CONFIG_SERIAL_SH_SCI_DMA
138 dma_cookie_t cookie_tx;
139 dma_cookie_t cookie_rx[2];
140 dma_cookie_t active_rx;
141 dma_addr_t tx_dma_addr;
142 unsigned int tx_dma_len;
143 struct scatterlist sg_rx[2];
144 void *rx_buf[2];
145 size_t buf_len_rx;
146 struct work_struct work_tx;
147 struct hrtimer rx_timer;
148 unsigned int rx_timeout; /* microseconds */
149#endif
150 unsigned int rx_frame;
151 int rx_trigger;
152 struct timer_list rx_fifo_timer;
153 int rx_fifo_timeout;
154 u16 hscif_tot;
155
156 bool has_rtscts;
157 bool autorts;
158};
159
160#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
161
162static struct sci_port sci_ports[SCI_NPORTS];
163static struct uart_driver sci_uart_driver;
164
165static inline struct sci_port *
166to_sci_port(struct uart_port *uart)
167{
168 return container_of(uart, struct sci_port, port);
169}
170
171static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
172 /*
173 * Common SCI definitions, dependent on the port's regshift
174 * value.
175 */
176 [SCIx_SCI_REGTYPE] = {
177 .regs = {
178 [SCSMR] = { 0x00, 8 },
179 [SCBRR] = { 0x01, 8 },
180 [SCSCR] = { 0x02, 8 },
181 [SCxTDR] = { 0x03, 8 },
182 [SCxSR] = { 0x04, 8 },
183 [SCxRDR] = { 0x05, 8 },
184 },
185 .fifosize = 1,
186 .overrun_reg = SCxSR,
187 .overrun_mask = SCI_ORER,
188 .sampling_rate_mask = SCI_SR(32),
189 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
190 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
191 },
192
193 /*
194 * Common definitions for legacy IrDA ports.
195 */
196 [SCIx_IRDA_REGTYPE] = {
197 .regs = {
198 [SCSMR] = { 0x00, 8 },
199 [SCBRR] = { 0x02, 8 },
200 [SCSCR] = { 0x04, 8 },
201 [SCxTDR] = { 0x06, 8 },
202 [SCxSR] = { 0x08, 16 },
203 [SCxRDR] = { 0x0a, 8 },
204 [SCFCR] = { 0x0c, 8 },
205 [SCFDR] = { 0x0e, 16 },
206 },
207 .fifosize = 1,
208 .overrun_reg = SCxSR,
209 .overrun_mask = SCI_ORER,
210 .sampling_rate_mask = SCI_SR(32),
211 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
212 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
213 },
214
215 /*
216 * Common SCIFA definitions.
217 */
218 [SCIx_SCIFA_REGTYPE] = {
219 .regs = {
220 [SCSMR] = { 0x00, 16 },
221 [SCBRR] = { 0x04, 8 },
222 [SCSCR] = { 0x08, 16 },
223 [SCxTDR] = { 0x20, 8 },
224 [SCxSR] = { 0x14, 16 },
225 [SCxRDR] = { 0x24, 8 },
226 [SCFCR] = { 0x18, 16 },
227 [SCFDR] = { 0x1c, 16 },
228 [SCPCR] = { 0x30, 16 },
229 [SCPDR] = { 0x34, 16 },
230 },
231 .fifosize = 64,
232 .overrun_reg = SCxSR,
233 .overrun_mask = SCIFA_ORER,
234 .sampling_rate_mask = SCI_SR_SCIFAB,
235 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
236 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
237 },
238
239 /*
240 * Common SCIFB definitions.
241 */
242 [SCIx_SCIFB_REGTYPE] = {
243 .regs = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x40, 8 },
248 [SCxSR] = { 0x14, 16 },
249 [SCxRDR] = { 0x60, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCTFDR] = { 0x38, 16 },
252 [SCRFDR] = { 0x3c, 16 },
253 [SCPCR] = { 0x30, 16 },
254 [SCPDR] = { 0x34, 16 },
255 },
256 .fifosize = 256,
257 .overrun_reg = SCxSR,
258 .overrun_mask = SCIFA_ORER,
259 .sampling_rate_mask = SCI_SR_SCIFAB,
260 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
261 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
262 },
263
264 /*
265 * Common SH-2(A) SCIF definitions for ports with FIFO data
266 * count registers.
267 */
268 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
269 .regs = {
270 [SCSMR] = { 0x00, 16 },
271 [SCBRR] = { 0x04, 8 },
272 [SCSCR] = { 0x08, 16 },
273 [SCxTDR] = { 0x0c, 8 },
274 [SCxSR] = { 0x10, 16 },
275 [SCxRDR] = { 0x14, 8 },
276 [SCFCR] = { 0x18, 16 },
277 [SCFDR] = { 0x1c, 16 },
278 [SCSPTR] = { 0x20, 16 },
279 [SCLSR] = { 0x24, 16 },
280 },
281 .fifosize = 16,
282 .overrun_reg = SCLSR,
283 .overrun_mask = SCLSR_ORER,
284 .sampling_rate_mask = SCI_SR(32),
285 .error_mask = SCIF_DEFAULT_ERROR_MASK,
286 .error_clear = SCIF_ERROR_CLEAR,
287 },
288
289 /*
290 * Common SH-3 SCIF definitions.
291 */
292 [SCIx_SH3_SCIF_REGTYPE] = {
293 .regs = {
294 [SCSMR] = { 0x00, 8 },
295 [SCBRR] = { 0x02, 8 },
296 [SCSCR] = { 0x04, 8 },
297 [SCxTDR] = { 0x06, 8 },
298 [SCxSR] = { 0x08, 16 },
299 [SCxRDR] = { 0x0a, 8 },
300 [SCFCR] = { 0x0c, 8 },
301 [SCFDR] = { 0x0e, 16 },
302 },
303 .fifosize = 16,
304 .overrun_reg = SCLSR,
305 .overrun_mask = SCLSR_ORER,
306 .sampling_rate_mask = SCI_SR(32),
307 .error_mask = SCIF_DEFAULT_ERROR_MASK,
308 .error_clear = SCIF_ERROR_CLEAR,
309 },
310
311 /*
312 * Common SH-4(A) SCIF(B) definitions.
313 */
314 [SCIx_SH4_SCIF_REGTYPE] = {
315 .regs = {
316 [SCSMR] = { 0x00, 16 },
317 [SCBRR] = { 0x04, 8 },
318 [SCSCR] = { 0x08, 16 },
319 [SCxTDR] = { 0x0c, 8 },
320 [SCxSR] = { 0x10, 16 },
321 [SCxRDR] = { 0x14, 8 },
322 [SCFCR] = { 0x18, 16 },
323 [SCFDR] = { 0x1c, 16 },
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
326 },
327 .fifosize = 16,
328 .overrun_reg = SCLSR,
329 .overrun_mask = SCLSR_ORER,
330 .sampling_rate_mask = SCI_SR(32),
331 .error_mask = SCIF_DEFAULT_ERROR_MASK,
332 .error_clear = SCIF_ERROR_CLEAR,
333 },
334
335 /*
336 * Common SCIF definitions for ports with a Baud Rate Generator for
337 * External Clock (BRG).
338 */
339 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
340 .regs = {
341 [SCSMR] = { 0x00, 16 },
342 [SCBRR] = { 0x04, 8 },
343 [SCSCR] = { 0x08, 16 },
344 [SCxTDR] = { 0x0c, 8 },
345 [SCxSR] = { 0x10, 16 },
346 [SCxRDR] = { 0x14, 8 },
347 [SCFCR] = { 0x18, 16 },
348 [SCFDR] = { 0x1c, 16 },
349 [SCSPTR] = { 0x20, 16 },
350 [SCLSR] = { 0x24, 16 },
351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
353 },
354 .fifosize = 16,
355 .overrun_reg = SCLSR,
356 .overrun_mask = SCLSR_ORER,
357 .sampling_rate_mask = SCI_SR(32),
358 .error_mask = SCIF_DEFAULT_ERROR_MASK,
359 .error_clear = SCIF_ERROR_CLEAR,
360 },
361
362 /*
363 * Common HSCIF definitions.
364 */
365 [SCIx_HSCIF_REGTYPE] = {
366 .regs = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCSPTR] = { 0x20, 16 },
376 [SCLSR] = { 0x24, 16 },
377 [HSSRR] = { 0x40, 16 },
378 [SCDL] = { 0x30, 16 },
379 [SCCKS] = { 0x34, 16 },
380 [HSRTRGR] = { 0x54, 16 },
381 [HSTTRGR] = { 0x58, 16 },
382 },
383 .fifosize = 128,
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
389 },
390
391 /*
392 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
393 * register.
394 */
395 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
396 .regs = {
397 [SCSMR] = { 0x00, 16 },
398 [SCBRR] = { 0x04, 8 },
399 [SCSCR] = { 0x08, 16 },
400 [SCxTDR] = { 0x0c, 8 },
401 [SCxSR] = { 0x10, 16 },
402 [SCxRDR] = { 0x14, 8 },
403 [SCFCR] = { 0x18, 16 },
404 [SCFDR] = { 0x1c, 16 },
405 [SCLSR] = { 0x24, 16 },
406 },
407 .fifosize = 16,
408 .overrun_reg = SCLSR,
409 .overrun_mask = SCLSR_ORER,
410 .sampling_rate_mask = SCI_SR(32),
411 .error_mask = SCIF_DEFAULT_ERROR_MASK,
412 .error_clear = SCIF_ERROR_CLEAR,
413 },
414
415 /*
416 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
417 * count registers.
418 */
419 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
420 .regs = {
421 [SCSMR] = { 0x00, 16 },
422 [SCBRR] = { 0x04, 8 },
423 [SCSCR] = { 0x08, 16 },
424 [SCxTDR] = { 0x0c, 8 },
425 [SCxSR] = { 0x10, 16 },
426 [SCxRDR] = { 0x14, 8 },
427 [SCFCR] = { 0x18, 16 },
428 [SCFDR] = { 0x1c, 16 },
429 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
430 [SCRFDR] = { 0x20, 16 },
431 [SCSPTR] = { 0x24, 16 },
432 [SCLSR] = { 0x28, 16 },
433 },
434 .fifosize = 16,
435 .overrun_reg = SCLSR,
436 .overrun_mask = SCLSR_ORER,
437 .sampling_rate_mask = SCI_SR(32),
438 .error_mask = SCIF_DEFAULT_ERROR_MASK,
439 .error_clear = SCIF_ERROR_CLEAR,
440 },
441
442 /*
443 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
444 * registers.
445 */
446 [SCIx_SH7705_SCIF_REGTYPE] = {
447 .regs = {
448 [SCSMR] = { 0x00, 16 },
449 [SCBRR] = { 0x04, 8 },
450 [SCSCR] = { 0x08, 16 },
451 [SCxTDR] = { 0x20, 8 },
452 [SCxSR] = { 0x14, 16 },
453 [SCxRDR] = { 0x24, 8 },
454 [SCFCR] = { 0x18, 16 },
455 [SCFDR] = { 0x1c, 16 },
456 },
457 .fifosize = 64,
458 .overrun_reg = SCxSR,
459 .overrun_mask = SCIFA_ORER,
460 .sampling_rate_mask = SCI_SR(16),
461 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
462 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
463 },
464};
465
466#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
467
468/*
469 * The "offset" here is rather misleading, in that it refers to an enum
470 * value relative to the port mapping rather than the fixed offset
471 * itself, which needs to be manually retrieved from the platform's
472 * register map for the given port.
473 */
474static unsigned int sci_serial_in(struct uart_port *p, int offset)
475{
476 const struct plat_sci_reg *reg = sci_getreg(p, offset);
477
478 if (reg->size == 8)
479 return ioread8(p->membase + (reg->offset << p->regshift));
480 else if (reg->size == 16)
481 return ioread16(p->membase + (reg->offset << p->regshift));
482 else
483 WARN(1, "Invalid register access\n");
484
485 return 0;
486}
487
488static void sci_serial_out(struct uart_port *p, int offset, int value)
489{
490 const struct plat_sci_reg *reg = sci_getreg(p, offset);
491
492 if (reg->size == 8)
493 iowrite8(value, p->membase + (reg->offset << p->regshift));
494 else if (reg->size == 16)
495 iowrite16(value, p->membase + (reg->offset << p->regshift));
496 else
497 WARN(1, "Invalid register access\n");
498}
499
500static void sci_port_enable(struct sci_port *sci_port)
501{
502 unsigned int i;
503
504 if (!sci_port->port.dev)
505 return;
506
507 pm_runtime_get_sync(sci_port->port.dev);
508
509 for (i = 0; i < SCI_NUM_CLKS; i++) {
510 clk_prepare_enable(sci_port->clks[i]);
511 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
512 }
513 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
514}
515
516static void sci_port_disable(struct sci_port *sci_port)
517{
518 unsigned int i;
519
520 if (!sci_port->port.dev)
521 return;
522
523 for (i = SCI_NUM_CLKS; i-- > 0; )
524 clk_disable_unprepare(sci_port->clks[i]);
525
526 pm_runtime_put_sync(sci_port->port.dev);
527}
528
529static inline unsigned long port_rx_irq_mask(struct uart_port *port)
530{
531 /*
532 * Not all ports (such as SCIFA) will support REIE. Rather than
533 * special-casing the port type, we check the port initialization
534 * IRQ enable mask to see whether the IRQ is desired at all. If
535 * it's unset, it's logically inferred that there's no point in
536 * testing for it.
537 */
538 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
539}
540
541static void sci_start_tx(struct uart_port *port)
542{
543 struct sci_port *s = to_sci_port(port);
544 unsigned short ctrl;
545
546#ifdef CONFIG_SERIAL_SH_SCI_DMA
547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
548 u16 new, scr = serial_port_in(port, SCSCR);
549 if (s->chan_tx)
550 new = scr | SCSCR_TDRQE;
551 else
552 new = scr & ~SCSCR_TDRQE;
553 if (new != scr)
554 serial_port_out(port, SCSCR, new);
555 }
556
557 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
558 dma_submit_error(s->cookie_tx)) {
559 s->cookie_tx = 0;
560 schedule_work(&s->work_tx);
561 }
562#endif
563
564 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
565 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
566 ctrl = serial_port_in(port, SCSCR);
567 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
568 }
569}
570
571static void sci_stop_tx(struct uart_port *port)
572{
573 unsigned short ctrl;
574
575 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
576 ctrl = serial_port_in(port, SCSCR);
577
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
579 ctrl &= ~SCSCR_TDRQE;
580
581 ctrl &= ~SCSCR_TIE;
582
583 serial_port_out(port, SCSCR, ctrl);
584}
585
586static void sci_start_rx(struct uart_port *port)
587{
588 unsigned short ctrl;
589
590 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
591
592 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
593 ctrl &= ~SCSCR_RDRQE;
594
595 serial_port_out(port, SCSCR, ctrl);
596}
597
598static void sci_stop_rx(struct uart_port *port)
599{
600 unsigned short ctrl;
601
602 ctrl = serial_port_in(port, SCSCR);
603
604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
605 ctrl &= ~SCSCR_RDRQE;
606
607 ctrl &= ~port_rx_irq_mask(port);
608
609 serial_port_out(port, SCSCR, ctrl);
610}
611
612static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
613{
614 if (port->type == PORT_SCI) {
615 /* Just store the mask */
616 serial_port_out(port, SCxSR, mask);
617 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
618 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
619 /* Only clear the status bits we want to clear */
620 serial_port_out(port, SCxSR,
621 serial_port_in(port, SCxSR) & mask);
622 } else {
623 /* Store the mask, clear parity/framing errors */
624 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
625 }
626}
627
628#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
629 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
630
631#ifdef CONFIG_CONSOLE_POLL
632static int sci_poll_get_char(struct uart_port *port)
633{
634 unsigned short status;
635 int c;
636
637 do {
638 status = serial_port_in(port, SCxSR);
639 if (status & SCxSR_ERRORS(port)) {
640 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
641 continue;
642 }
643 break;
644 } while (1);
645
646 if (!(status & SCxSR_RDxF(port)))
647 return NO_POLL_CHAR;
648
649 c = serial_port_in(port, SCxRDR);
650
651 /* Dummy read */
652 serial_port_in(port, SCxSR);
653 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
654
655 return c;
656}
657#endif
658
659static void sci_poll_put_char(struct uart_port *port, unsigned char c)
660{
661 unsigned short status;
662
663 do {
664 status = serial_port_in(port, SCxSR);
665 } while (!(status & SCxSR_TDxE(port)));
666
667 serial_port_out(port, SCxTDR, c);
668 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
669}
670#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
671 CONFIG_SERIAL_SH_SCI_EARLYCON */
672
673static void sci_init_pins(struct uart_port *port, unsigned int cflag)
674{
675 struct sci_port *s = to_sci_port(port);
676
677 /*
678 * Use port-specific handler if provided.
679 */
680 if (s->cfg->ops && s->cfg->ops->init_pins) {
681 s->cfg->ops->init_pins(port, cflag);
682 return;
683 }
684
685 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
686 u16 data = serial_port_in(port, SCPDR);
687 u16 ctrl = serial_port_in(port, SCPCR);
688
689 /* Enable RXD and TXD pin functions */
690 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
691 if (to_sci_port(port)->has_rtscts) {
692 /* RTS# is output, active low, unless autorts */
693 if (!(port->mctrl & TIOCM_RTS)) {
694 ctrl |= SCPCR_RTSC;
695 data |= SCPDR_RTSD;
696 } else if (!s->autorts) {
697 ctrl |= SCPCR_RTSC;
698 data &= ~SCPDR_RTSD;
699 } else {
700 /* Enable RTS# pin function */
701 ctrl &= ~SCPCR_RTSC;
702 }
703 /* Enable CTS# pin function */
704 ctrl &= ~SCPCR_CTSC;
705 }
706 serial_port_out(port, SCPDR, data);
707 serial_port_out(port, SCPCR, ctrl);
708 } else if (sci_getreg(port, SCSPTR)->size) {
709 u16 status = serial_port_in(port, SCSPTR);
710
711 /* RTS# is always output; and active low, unless autorts */
712 status |= SCSPTR_RTSIO;
713 if (!(port->mctrl & TIOCM_RTS))
714 status |= SCSPTR_RTSDT;
715 else if (!s->autorts)
716 status &= ~SCSPTR_RTSDT;
717 /* CTS# and SCK are inputs */
718 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
719 serial_port_out(port, SCSPTR, status);
720 }
721}
722
723static int sci_txfill(struct uart_port *port)
724{
725 struct sci_port *s = to_sci_port(port);
726 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
727 const struct plat_sci_reg *reg;
728
729 reg = sci_getreg(port, SCTFDR);
730 if (reg->size)
731 return serial_port_in(port, SCTFDR) & fifo_mask;
732
733 reg = sci_getreg(port, SCFDR);
734 if (reg->size)
735 return serial_port_in(port, SCFDR) >> 8;
736
737 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
738}
739
740static int sci_txroom(struct uart_port *port)
741{
742 return port->fifosize - sci_txfill(port);
743}
744
745static int sci_rxfill(struct uart_port *port)
746{
747 struct sci_port *s = to_sci_port(port);
748 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
749 const struct plat_sci_reg *reg;
750
751 reg = sci_getreg(port, SCRFDR);
752 if (reg->size)
753 return serial_port_in(port, SCRFDR) & fifo_mask;
754
755 reg = sci_getreg(port, SCFDR);
756 if (reg->size)
757 return serial_port_in(port, SCFDR) & fifo_mask;
758
759 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
760}
761
762/* ********************************************************************** *
763 * the interrupt related routines *
764 * ********************************************************************** */
765
766static void sci_transmit_chars(struct uart_port *port)
767{
768 struct circ_buf *xmit = &port->state->xmit;
769 unsigned int stopped = uart_tx_stopped(port);
770 unsigned short status;
771 unsigned short ctrl;
772 int count;
773
774 status = serial_port_in(port, SCxSR);
775 if (!(status & SCxSR_TDxE(port))) {
776 ctrl = serial_port_in(port, SCSCR);
777 if (uart_circ_empty(xmit))
778 ctrl &= ~SCSCR_TIE;
779 else
780 ctrl |= SCSCR_TIE;
781 serial_port_out(port, SCSCR, ctrl);
782 return;
783 }
784
785 count = sci_txroom(port);
786
787 do {
788 unsigned char c;
789
790 if (port->x_char) {
791 c = port->x_char;
792 port->x_char = 0;
793 } else if (!uart_circ_empty(xmit) && !stopped) {
794 c = xmit->buf[xmit->tail];
795 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
796 } else {
797 break;
798 }
799
800 serial_port_out(port, SCxTDR, c);
801
802 port->icount.tx++;
803 } while (--count > 0);
804
805 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
806
807 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
808 uart_write_wakeup(port);
809 if (uart_circ_empty(xmit)) {
810 sci_stop_tx(port);
811 } else {
812 ctrl = serial_port_in(port, SCSCR);
813
814 if (port->type != PORT_SCI) {
815 serial_port_in(port, SCxSR); /* Dummy read */
816 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
817 }
818
819 ctrl |= SCSCR_TIE;
820 serial_port_out(port, SCSCR, ctrl);
821 }
822}
823
824/* On SH3, SCIF may read end-of-break as a space->mark char */
825#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
826
827static void sci_receive_chars(struct uart_port *port)
828{
829 struct tty_port *tport = &port->state->port;
830 int i, count, copied = 0;
831 unsigned short status;
832 unsigned char flag;
833
834 status = serial_port_in(port, SCxSR);
835 if (!(status & SCxSR_RDxF(port)))
836 return;
837
838 while (1) {
839 /* Don't copy more bytes than there is room for in the buffer */
840 count = tty_buffer_request_room(tport, sci_rxfill(port));
841
842 /* If for any reason we can't copy more data, we're done! */
843 if (count == 0)
844 break;
845
846 if (port->type == PORT_SCI) {
847 char c = serial_port_in(port, SCxRDR);
848 if (uart_handle_sysrq_char(port, c))
849 count = 0;
850 else
851 tty_insert_flip_char(tport, c, TTY_NORMAL);
852 } else {
853 for (i = 0; i < count; i++) {
854 char c = serial_port_in(port, SCxRDR);
855
856 status = serial_port_in(port, SCxSR);
857 if (uart_handle_sysrq_char(port, c)) {
858 count--; i--;
859 continue;
860 }
861
862 /* Store data and status */
863 if (status & SCxSR_FER(port)) {
864 flag = TTY_FRAME;
865 port->icount.frame++;
866 dev_notice(port->dev, "frame error\n");
867 } else if (status & SCxSR_PER(port)) {
868 flag = TTY_PARITY;
869 port->icount.parity++;
870 dev_notice(port->dev, "parity error\n");
871 } else
872 flag = TTY_NORMAL;
873
874 tty_insert_flip_char(tport, c, flag);
875 }
876 }
877
878 serial_port_in(port, SCxSR); /* dummy read */
879 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
880
881 copied += count;
882 port->icount.rx += count;
883 }
884
885 if (copied) {
886 /* Tell the rest of the system the news. New characters! */
887 tty_flip_buffer_push(tport);
888 } else {
889 /* TTY buffers full; read from RX reg to prevent lockup */
890 serial_port_in(port, SCxRDR);
891 serial_port_in(port, SCxSR); /* dummy read */
892 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
893 }
894}
895
896static int sci_handle_errors(struct uart_port *port)
897{
898 int copied = 0;
899 unsigned short status = serial_port_in(port, SCxSR);
900 struct tty_port *tport = &port->state->port;
901 struct sci_port *s = to_sci_port(port);
902
903 /* Handle overruns */
904 if (status & s->params->overrun_mask) {
905 port->icount.overrun++;
906
907 /* overrun error */
908 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
909 copied++;
910
911 dev_notice(port->dev, "overrun error\n");
912 }
913
914 if (status & SCxSR_FER(port)) {
915 /* frame error */
916 port->icount.frame++;
917
918 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
919 copied++;
920
921 dev_notice(port->dev, "frame error\n");
922 }
923
924 if (status & SCxSR_PER(port)) {
925 /* parity error */
926 port->icount.parity++;
927
928 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
929 copied++;
930
931 dev_notice(port->dev, "parity error\n");
932 }
933
934 if (copied)
935 tty_flip_buffer_push(tport);
936
937 return copied;
938}
939
940static int sci_handle_fifo_overrun(struct uart_port *port)
941{
942 struct tty_port *tport = &port->state->port;
943 struct sci_port *s = to_sci_port(port);
944 const struct plat_sci_reg *reg;
945 int copied = 0;
946 u16 status;
947
948 reg = sci_getreg(port, s->params->overrun_reg);
949 if (!reg->size)
950 return 0;
951
952 status = serial_port_in(port, s->params->overrun_reg);
953 if (status & s->params->overrun_mask) {
954 status &= ~s->params->overrun_mask;
955 serial_port_out(port, s->params->overrun_reg, status);
956
957 port->icount.overrun++;
958
959 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
960 tty_flip_buffer_push(tport);
961
962 dev_dbg(port->dev, "overrun error\n");
963 copied++;
964 }
965
966 return copied;
967}
968
969static int sci_handle_breaks(struct uart_port *port)
970{
971 int copied = 0;
972 unsigned short status = serial_port_in(port, SCxSR);
973 struct tty_port *tport = &port->state->port;
974
975 if (uart_handle_break(port))
976 return 0;
977
978 if (status & SCxSR_BRK(port)) {
979 port->icount.brk++;
980
981 /* Notify of BREAK */
982 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
983 copied++;
984
985 dev_dbg(port->dev, "BREAK detected\n");
986 }
987
988 if (copied)
989 tty_flip_buffer_push(tport);
990
991 copied += sci_handle_fifo_overrun(port);
992
993 return copied;
994}
995
996static int scif_set_rtrg(struct uart_port *port, int rx_trig)
997{
998 unsigned int bits;
999
1000 if (rx_trig < 1)
1001 rx_trig = 1;
1002 if (rx_trig >= port->fifosize)
1003 rx_trig = port->fifosize;
1004
1005 /* HSCIF can be set to an arbitrary level. */
1006 if (sci_getreg(port, HSRTRGR)->size) {
1007 serial_port_out(port, HSRTRGR, rx_trig);
1008 return rx_trig;
1009 }
1010
1011 switch (port->type) {
1012 case PORT_SCIF:
1013 if (rx_trig < 4) {
1014 bits = 0;
1015 rx_trig = 1;
1016 } else if (rx_trig < 8) {
1017 bits = SCFCR_RTRG0;
1018 rx_trig = 4;
1019 } else if (rx_trig < 14) {
1020 bits = SCFCR_RTRG1;
1021 rx_trig = 8;
1022 } else {
1023 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1024 rx_trig = 14;
1025 }
1026 break;
1027 case PORT_SCIFA:
1028 case PORT_SCIFB:
1029 if (rx_trig < 16) {
1030 bits = 0;
1031 rx_trig = 1;
1032 } else if (rx_trig < 32) {
1033 bits = SCFCR_RTRG0;
1034 rx_trig = 16;
1035 } else if (rx_trig < 48) {
1036 bits = SCFCR_RTRG1;
1037 rx_trig = 32;
1038 } else {
1039 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1040 rx_trig = 48;
1041 }
1042 break;
1043 default:
1044 WARN(1, "unknown FIFO configuration");
1045 return 1;
1046 }
1047
1048 serial_port_out(port, SCFCR,
1049 (serial_port_in(port, SCFCR) &
1050 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1051
1052 return rx_trig;
1053}
1054
1055static int scif_rtrg_enabled(struct uart_port *port)
1056{
1057 if (sci_getreg(port, HSRTRGR)->size)
1058 return serial_port_in(port, HSRTRGR) != 0;
1059 else
1060 return (serial_port_in(port, SCFCR) &
1061 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1062}
1063
1064static void rx_fifo_timer_fn(struct timer_list *t)
1065{
1066 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1067 struct uart_port *port = &s->port;
1068
1069 dev_dbg(port->dev, "Rx timed out\n");
1070 scif_set_rtrg(port, 1);
1071}
1072
1073static ssize_t rx_trigger_show(struct device *dev,
1074 struct device_attribute *attr,
1075 char *buf)
1076{
1077 struct uart_port *port = dev_get_drvdata(dev);
1078 struct sci_port *sci = to_sci_port(port);
1079
1080 return sprintf(buf, "%d\n", sci->rx_trigger);
1081}
1082
1083static ssize_t rx_trigger_store(struct device *dev,
1084 struct device_attribute *attr,
1085 const char *buf,
1086 size_t count)
1087{
1088 struct uart_port *port = dev_get_drvdata(dev);
1089 struct sci_port *sci = to_sci_port(port);
1090 int ret;
1091 long r;
1092
1093 ret = kstrtol(buf, 0, &r);
1094 if (ret)
1095 return ret;
1096
1097 sci->rx_trigger = scif_set_rtrg(port, r);
1098 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1099 scif_set_rtrg(port, 1);
1100
1101 return count;
1102}
1103
1104static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1105
1106static ssize_t rx_fifo_timeout_show(struct device *dev,
1107 struct device_attribute *attr,
1108 char *buf)
1109{
1110 struct uart_port *port = dev_get_drvdata(dev);
1111 struct sci_port *sci = to_sci_port(port);
1112 int v;
1113
1114 if (port->type == PORT_HSCIF)
1115 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1116 else
1117 v = sci->rx_fifo_timeout;
1118
1119 return sprintf(buf, "%d\n", v);
1120}
1121
1122static ssize_t rx_fifo_timeout_store(struct device *dev,
1123 struct device_attribute *attr,
1124 const char *buf,
1125 size_t count)
1126{
1127 struct uart_port *port = dev_get_drvdata(dev);
1128 struct sci_port *sci = to_sci_port(port);
1129 int ret;
1130 long r;
1131
1132 ret = kstrtol(buf, 0, &r);
1133 if (ret)
1134 return ret;
1135
1136 if (port->type == PORT_HSCIF) {
1137 if (r < 0 || r > 3)
1138 return -EINVAL;
1139 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1140 } else {
1141 sci->rx_fifo_timeout = r;
1142 scif_set_rtrg(port, 1);
1143 if (r > 0)
1144 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1145 }
1146
1147 return count;
1148}
1149
1150static DEVICE_ATTR_RW(rx_fifo_timeout);
1151
1152
1153#ifdef CONFIG_SERIAL_SH_SCI_DMA
1154static void sci_dma_tx_complete(void *arg)
1155{
1156 struct sci_port *s = arg;
1157 struct uart_port *port = &s->port;
1158 struct circ_buf *xmit = &port->state->xmit;
1159 unsigned long flags;
1160
1161 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1162
1163 spin_lock_irqsave(&port->lock, flags);
1164
1165 xmit->tail += s->tx_dma_len;
1166 xmit->tail &= UART_XMIT_SIZE - 1;
1167
1168 port->icount.tx += s->tx_dma_len;
1169
1170 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1171 uart_write_wakeup(port);
1172
1173 if (!uart_circ_empty(xmit)) {
1174 s->cookie_tx = 0;
1175 schedule_work(&s->work_tx);
1176 } else {
1177 s->cookie_tx = -EINVAL;
1178 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1179 u16 ctrl = serial_port_in(port, SCSCR);
1180 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1181 }
1182 }
1183
1184 spin_unlock_irqrestore(&port->lock, flags);
1185}
1186
1187/* Locking: called with port lock held */
1188static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1189{
1190 struct uart_port *port = &s->port;
1191 struct tty_port *tport = &port->state->port;
1192 int copied;
1193
1194 copied = tty_insert_flip_string(tport, buf, count);
1195 if (copied < count)
1196 port->icount.buf_overrun++;
1197
1198 port->icount.rx += copied;
1199
1200 return copied;
1201}
1202
1203static int sci_dma_rx_find_active(struct sci_port *s)
1204{
1205 unsigned int i;
1206
1207 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1208 if (s->active_rx == s->cookie_rx[i])
1209 return i;
1210
1211 return -1;
1212}
1213
1214static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1215{
1216 struct dma_chan *chan = s->chan_rx;
1217 struct uart_port *port = &s->port;
1218 unsigned long flags;
1219
1220 spin_lock_irqsave(&port->lock, flags);
1221 s->chan_rx = NULL;
1222 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1223 spin_unlock_irqrestore(&port->lock, flags);
1224 dmaengine_terminate_all(chan);
1225 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1226 sg_dma_address(&s->sg_rx[0]));
1227 dma_release_channel(chan);
1228 if (enable_pio) {
1229 spin_lock_irqsave(&port->lock, flags);
1230 sci_start_rx(port);
1231 spin_unlock_irqrestore(&port->lock, flags);
1232 }
1233}
1234
1235static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1236{
1237 long sec = usec / 1000000;
1238 long nsec = (usec % 1000000) * 1000;
1239 ktime_t t = ktime_set(sec, nsec);
1240
1241 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1242}
1243
1244static void sci_dma_rx_complete(void *arg)
1245{
1246 struct sci_port *s = arg;
1247 struct dma_chan *chan = s->chan_rx;
1248 struct uart_port *port = &s->port;
1249 struct dma_async_tx_descriptor *desc;
1250 unsigned long flags;
1251 int active, count = 0;
1252
1253 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1254 s->active_rx);
1255
1256 spin_lock_irqsave(&port->lock, flags);
1257
1258 active = sci_dma_rx_find_active(s);
1259 if (active >= 0)
1260 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1261
1262 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1263
1264 if (count)
1265 tty_flip_buffer_push(&port->state->port);
1266
1267 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1268 DMA_DEV_TO_MEM,
1269 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1270 if (!desc)
1271 goto fail;
1272
1273 desc->callback = sci_dma_rx_complete;
1274 desc->callback_param = s;
1275 s->cookie_rx[active] = dmaengine_submit(desc);
1276 if (dma_submit_error(s->cookie_rx[active]))
1277 goto fail;
1278
1279 s->active_rx = s->cookie_rx[!active];
1280
1281 dma_async_issue_pending(chan);
1282
1283 spin_unlock_irqrestore(&port->lock, flags);
1284 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1285 __func__, s->cookie_rx[active], active, s->active_rx);
1286 return;
1287
1288fail:
1289 spin_unlock_irqrestore(&port->lock, flags);
1290 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1291 sci_rx_dma_release(s, true);
1292}
1293
1294static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1295{
1296 struct dma_chan *chan = s->chan_tx;
1297 struct uart_port *port = &s->port;
1298 unsigned long flags;
1299
1300 spin_lock_irqsave(&port->lock, flags);
1301 s->chan_tx = NULL;
1302 s->cookie_tx = -EINVAL;
1303 spin_unlock_irqrestore(&port->lock, flags);
1304 dmaengine_terminate_all(chan);
1305 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1306 DMA_TO_DEVICE);
1307 dma_release_channel(chan);
1308 if (enable_pio) {
1309 spin_lock_irqsave(&port->lock, flags);
1310 sci_start_tx(port);
1311 spin_unlock_irqrestore(&port->lock, flags);
1312 }
1313}
1314
1315static void sci_submit_rx(struct sci_port *s)
1316{
1317 struct dma_chan *chan = s->chan_rx;
1318 int i;
1319
1320 for (i = 0; i < 2; i++) {
1321 struct scatterlist *sg = &s->sg_rx[i];
1322 struct dma_async_tx_descriptor *desc;
1323
1324 desc = dmaengine_prep_slave_sg(chan,
1325 sg, 1, DMA_DEV_TO_MEM,
1326 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1327 if (!desc)
1328 goto fail;
1329
1330 desc->callback = sci_dma_rx_complete;
1331 desc->callback_param = s;
1332 s->cookie_rx[i] = dmaengine_submit(desc);
1333 if (dma_submit_error(s->cookie_rx[i]))
1334 goto fail;
1335
1336 }
1337
1338 s->active_rx = s->cookie_rx[0];
1339
1340 dma_async_issue_pending(chan);
1341 return;
1342
1343fail:
1344 if (i)
1345 dmaengine_terminate_all(chan);
1346 for (i = 0; i < 2; i++)
1347 s->cookie_rx[i] = -EINVAL;
1348 s->active_rx = -EINVAL;
1349 sci_rx_dma_release(s, true);
1350}
1351
1352static void work_fn_tx(struct work_struct *work)
1353{
1354 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1355 struct dma_async_tx_descriptor *desc;
1356 struct dma_chan *chan = s->chan_tx;
1357 struct uart_port *port = &s->port;
1358 struct circ_buf *xmit = &port->state->xmit;
1359 dma_addr_t buf;
1360
1361 /*
1362 * DMA is idle now.
1363 * Port xmit buffer is already mapped, and it is one page... Just adjust
1364 * offsets and lengths. Since it is a circular buffer, we have to
1365 * transmit till the end, and then the rest. Take the port lock to get a
1366 * consistent xmit buffer state.
1367 */
1368 spin_lock_irq(&port->lock);
1369 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1370 s->tx_dma_len = min_t(unsigned int,
1371 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1372 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1373 spin_unlock_irq(&port->lock);
1374
1375 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1376 DMA_MEM_TO_DEV,
1377 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1378 if (!desc) {
1379 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1380 /* switch to PIO */
1381 sci_tx_dma_release(s, true);
1382 return;
1383 }
1384
1385 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1386 DMA_TO_DEVICE);
1387
1388 spin_lock_irq(&port->lock);
1389 desc->callback = sci_dma_tx_complete;
1390 desc->callback_param = s;
1391 spin_unlock_irq(&port->lock);
1392 s->cookie_tx = dmaengine_submit(desc);
1393 if (dma_submit_error(s->cookie_tx)) {
1394 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1395 /* switch to PIO */
1396 sci_tx_dma_release(s, true);
1397 return;
1398 }
1399
1400 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1401 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1402
1403 dma_async_issue_pending(chan);
1404}
1405
1406static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
1407{
1408 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1409 struct dma_chan *chan = s->chan_rx;
1410 struct uart_port *port = &s->port;
1411 struct dma_tx_state state;
1412 enum dma_status status;
1413 unsigned long flags;
1414 unsigned int read;
1415 int active, count;
1416 u16 scr;
1417
1418 dev_dbg(port->dev, "DMA Rx timed out\n");
1419
1420 spin_lock_irqsave(&port->lock, flags);
1421
1422 active = sci_dma_rx_find_active(s);
1423 if (active < 0) {
1424 spin_unlock_irqrestore(&port->lock, flags);
1425 return HRTIMER_NORESTART;
1426 }
1427
1428 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1429 if (status == DMA_COMPLETE) {
1430 spin_unlock_irqrestore(&port->lock, flags);
1431 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1432 s->active_rx, active);
1433
1434 /* Let packet complete handler take care of the packet */
1435 return HRTIMER_NORESTART;
1436 }
1437
1438 dmaengine_pause(chan);
1439
1440 /*
1441 * sometimes DMA transfer doesn't stop even if it is stopped and
1442 * data keeps on coming until transaction is complete so check
1443 * for DMA_COMPLETE again
1444 * Let packet complete handler take care of the packet
1445 */
1446 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1447 if (status == DMA_COMPLETE) {
1448 spin_unlock_irqrestore(&port->lock, flags);
1449 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1450 return HRTIMER_NORESTART;
1451 }
1452
1453 /* Handle incomplete DMA receive */
1454 dmaengine_terminate_all(s->chan_rx);
1455 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1456
1457 if (read) {
1458 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1459 if (count)
1460 tty_flip_buffer_push(&port->state->port);
1461 }
1462
1463 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1464 sci_submit_rx(s);
1465
1466 /* Direct new serial port interrupts back to CPU */
1467 scr = serial_port_in(port, SCSCR);
1468 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1469 scr &= ~SCSCR_RDRQE;
1470 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1471 }
1472 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1473
1474 spin_unlock_irqrestore(&port->lock, flags);
1475
1476 return HRTIMER_NORESTART;
1477}
1478
1479static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1480 enum dma_transfer_direction dir)
1481{
1482 struct dma_chan *chan;
1483 struct dma_slave_config cfg;
1484 int ret;
1485
1486 chan = dma_request_slave_channel(port->dev,
1487 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1488 if (!chan) {
1489 dev_warn(port->dev, "dma_request_slave_channel failed\n");
1490 return NULL;
1491 }
1492
1493 memset(&cfg, 0, sizeof(cfg));
1494 cfg.direction = dir;
1495 if (dir == DMA_MEM_TO_DEV) {
1496 cfg.dst_addr = port->mapbase +
1497 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1498 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1499 } else {
1500 cfg.src_addr = port->mapbase +
1501 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1502 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1503 }
1504
1505 ret = dmaengine_slave_config(chan, &cfg);
1506 if (ret) {
1507 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1508 dma_release_channel(chan);
1509 return NULL;
1510 }
1511
1512 return chan;
1513}
1514
1515static void sci_request_dma(struct uart_port *port)
1516{
1517 struct sci_port *s = to_sci_port(port);
1518 struct dma_chan *chan;
1519
1520 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1521
1522 if (!port->dev->of_node)
1523 return;
1524
1525 s->cookie_tx = -EINVAL;
1526
1527 /*
1528 * Don't request a dma channel if no channel was specified
1529 * in the device tree.
1530 */
1531 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1532 return;
1533
1534 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1535 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1536 if (chan) {
1537 s->chan_tx = chan;
1538 /* UART circular tx buffer is an aligned page. */
1539 s->tx_dma_addr = dma_map_single(chan->device->dev,
1540 port->state->xmit.buf,
1541 UART_XMIT_SIZE,
1542 DMA_TO_DEVICE);
1543 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1544 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1545 dma_release_channel(chan);
1546 s->chan_tx = NULL;
1547 } else {
1548 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1549 __func__, UART_XMIT_SIZE,
1550 port->state->xmit.buf, &s->tx_dma_addr);
1551 }
1552
1553 INIT_WORK(&s->work_tx, work_fn_tx);
1554 }
1555
1556 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1557 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1558 if (chan) {
1559 unsigned int i;
1560 dma_addr_t dma;
1561 void *buf;
1562
1563 s->chan_rx = chan;
1564
1565 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1566 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1567 &dma, GFP_KERNEL);
1568 if (!buf) {
1569 dev_warn(port->dev,
1570 "Failed to allocate Rx dma buffer, using PIO\n");
1571 dma_release_channel(chan);
1572 s->chan_rx = NULL;
1573 return;
1574 }
1575
1576 for (i = 0; i < 2; i++) {
1577 struct scatterlist *sg = &s->sg_rx[i];
1578
1579 sg_init_table(sg, 1);
1580 s->rx_buf[i] = buf;
1581 sg_dma_address(sg) = dma;
1582 sg_dma_len(sg) = s->buf_len_rx;
1583
1584 buf += s->buf_len_rx;
1585 dma += s->buf_len_rx;
1586 }
1587
1588 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1589 s->rx_timer.function = rx_timer_fn;
1590
1591 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1592 sci_submit_rx(s);
1593 }
1594}
1595
1596static void sci_free_dma(struct uart_port *port)
1597{
1598 struct sci_port *s = to_sci_port(port);
1599
1600 if (s->chan_tx)
1601 sci_tx_dma_release(s, false);
1602 if (s->chan_rx)
1603 sci_rx_dma_release(s, false);
1604}
1605
1606static void sci_flush_buffer(struct uart_port *port)
1607{
1608 /*
1609 * In uart_flush_buffer(), the xmit circular buffer has just been
1610 * cleared, so we have to reset tx_dma_len accordingly.
1611 */
1612 to_sci_port(port)->tx_dma_len = 0;
1613}
1614#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1615static inline void sci_request_dma(struct uart_port *port)
1616{
1617}
1618
1619static inline void sci_free_dma(struct uart_port *port)
1620{
1621}
1622
1623#define sci_flush_buffer NULL
1624#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1625
1626static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1627{
1628 struct uart_port *port = ptr;
1629 struct sci_port *s = to_sci_port(port);
1630
1631#ifdef CONFIG_SERIAL_SH_SCI_DMA
1632 if (s->chan_rx) {
1633 u16 scr = serial_port_in(port, SCSCR);
1634 u16 ssr = serial_port_in(port, SCxSR);
1635
1636 /* Disable future Rx interrupts */
1637 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1638 disable_irq_nosync(irq);
1639 scr |= SCSCR_RDRQE;
1640 } else {
1641 scr &= ~SCSCR_RIE;
1642 sci_submit_rx(s);
1643 }
1644 serial_port_out(port, SCSCR, scr);
1645 /* Clear current interrupt */
1646 serial_port_out(port, SCxSR,
1647 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1648 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1649 jiffies, s->rx_timeout);
1650 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1651
1652 return IRQ_HANDLED;
1653 }
1654#endif
1655
1656 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1657 if (!scif_rtrg_enabled(port))
1658 scif_set_rtrg(port, s->rx_trigger);
1659
1660 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1661 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1662 }
1663
1664 /* I think sci_receive_chars has to be called irrespective
1665 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1666 * to be disabled?
1667 */
1668 sci_receive_chars(ptr);
1669
1670 return IRQ_HANDLED;
1671}
1672
1673static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1674{
1675 struct uart_port *port = ptr;
1676 unsigned long flags;
1677
1678 spin_lock_irqsave(&port->lock, flags);
1679 sci_transmit_chars(port);
1680 spin_unlock_irqrestore(&port->lock, flags);
1681
1682 return IRQ_HANDLED;
1683}
1684
1685static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1686{
1687 struct uart_port *port = ptr;
1688 struct sci_port *s = to_sci_port(port);
1689
1690 /* Handle errors */
1691 if (port->type == PORT_SCI) {
1692 if (sci_handle_errors(port)) {
1693 /* discard character in rx buffer */
1694 serial_port_in(port, SCxSR);
1695 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1696 }
1697 } else {
1698 sci_handle_fifo_overrun(port);
1699 if (!s->chan_rx)
1700 sci_receive_chars(ptr);
1701 }
1702
1703 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1704
1705 /* Kick the transmission */
1706 if (!s->chan_tx)
1707 sci_tx_interrupt(irq, ptr);
1708
1709 return IRQ_HANDLED;
1710}
1711
1712static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1713{
1714 struct uart_port *port = ptr;
1715
1716 /* Handle BREAKs */
1717 sci_handle_breaks(port);
1718 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1719
1720 return IRQ_HANDLED;
1721}
1722
1723static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1724{
1725 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1726 struct uart_port *port = ptr;
1727 struct sci_port *s = to_sci_port(port);
1728 irqreturn_t ret = IRQ_NONE;
1729
1730 ssr_status = serial_port_in(port, SCxSR);
1731 scr_status = serial_port_in(port, SCSCR);
1732 if (s->params->overrun_reg == SCxSR)
1733 orer_status = ssr_status;
1734 else if (sci_getreg(port, s->params->overrun_reg)->size)
1735 orer_status = serial_port_in(port, s->params->overrun_reg);
1736
1737 err_enabled = scr_status & port_rx_irq_mask(port);
1738
1739 /* Tx Interrupt */
1740 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1741 !s->chan_tx)
1742 ret = sci_tx_interrupt(irq, ptr);
1743
1744 /*
1745 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1746 * DR flags
1747 */
1748 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1749 (scr_status & SCSCR_RIE))
1750 ret = sci_rx_interrupt(irq, ptr);
1751
1752 /* Error Interrupt */
1753 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1754 ret = sci_er_interrupt(irq, ptr);
1755
1756 /* Break Interrupt */
1757 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1758 ret = sci_br_interrupt(irq, ptr);
1759
1760 /* Overrun Interrupt */
1761 if (orer_status & s->params->overrun_mask) {
1762 sci_handle_fifo_overrun(port);
1763 ret = IRQ_HANDLED;
1764 }
1765
1766 return ret;
1767}
1768
1769static const struct sci_irq_desc {
1770 const char *desc;
1771 irq_handler_t handler;
1772} sci_irq_desc[] = {
1773 /*
1774 * Split out handlers, the default case.
1775 */
1776 [SCIx_ERI_IRQ] = {
1777 .desc = "rx err",
1778 .handler = sci_er_interrupt,
1779 },
1780
1781 [SCIx_RXI_IRQ] = {
1782 .desc = "rx full",
1783 .handler = sci_rx_interrupt,
1784 },
1785
1786 [SCIx_TXI_IRQ] = {
1787 .desc = "tx empty",
1788 .handler = sci_tx_interrupt,
1789 },
1790
1791 [SCIx_BRI_IRQ] = {
1792 .desc = "break",
1793 .handler = sci_br_interrupt,
1794 },
1795
1796 /*
1797 * Special muxed handler.
1798 */
1799 [SCIx_MUX_IRQ] = {
1800 .desc = "mux",
1801 .handler = sci_mpxed_interrupt,
1802 },
1803};
1804
1805static int sci_request_irq(struct sci_port *port)
1806{
1807 struct uart_port *up = &port->port;
1808 int i, j, ret = 0;
1809
1810 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1811 const struct sci_irq_desc *desc;
1812 int irq;
1813
1814 if (SCIx_IRQ_IS_MUXED(port)) {
1815 i = SCIx_MUX_IRQ;
1816 irq = up->irq;
1817 } else {
1818 irq = port->irqs[i];
1819
1820 /*
1821 * Certain port types won't support all of the
1822 * available interrupt sources.
1823 */
1824 if (unlikely(irq < 0))
1825 continue;
1826 }
1827
1828 desc = sci_irq_desc + i;
1829 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1830 dev_name(up->dev), desc->desc);
1831 if (!port->irqstr[j]) {
1832 ret = -ENOMEM;
1833 goto out_nomem;
1834 }
1835
1836 ret = request_irq(irq, desc->handler, up->irqflags,
1837 port->irqstr[j], port);
1838 if (unlikely(ret)) {
1839 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1840 goto out_noirq;
1841 }
1842 }
1843
1844 return 0;
1845
1846out_noirq:
1847 while (--i >= 0)
1848 free_irq(port->irqs[i], port);
1849
1850out_nomem:
1851 while (--j >= 0)
1852 kfree(port->irqstr[j]);
1853
1854 return ret;
1855}
1856
1857static void sci_free_irq(struct sci_port *port)
1858{
1859 int i;
1860
1861 /*
1862 * Intentionally in reverse order so we iterate over the muxed
1863 * IRQ first.
1864 */
1865 for (i = 0; i < SCIx_NR_IRQS; i++) {
1866 int irq = port->irqs[i];
1867
1868 /*
1869 * Certain port types won't support all of the available
1870 * interrupt sources.
1871 */
1872 if (unlikely(irq < 0))
1873 continue;
1874
1875 free_irq(port->irqs[i], port);
1876 kfree(port->irqstr[i]);
1877
1878 if (SCIx_IRQ_IS_MUXED(port)) {
1879 /* If there's only one IRQ, we're done. */
1880 return;
1881 }
1882 }
1883}
1884
1885static unsigned int sci_tx_empty(struct uart_port *port)
1886{
1887 unsigned short status = serial_port_in(port, SCxSR);
1888 unsigned short in_tx_fifo = sci_txfill(port);
1889
1890 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1891}
1892
1893static void sci_set_rts(struct uart_port *port, bool state)
1894{
1895 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1896 u16 data = serial_port_in(port, SCPDR);
1897
1898 /* Active low */
1899 if (state)
1900 data &= ~SCPDR_RTSD;
1901 else
1902 data |= SCPDR_RTSD;
1903 serial_port_out(port, SCPDR, data);
1904
1905 /* RTS# is output */
1906 serial_port_out(port, SCPCR,
1907 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1908 } else if (sci_getreg(port, SCSPTR)->size) {
1909 u16 ctrl = serial_port_in(port, SCSPTR);
1910
1911 /* Active low */
1912 if (state)
1913 ctrl &= ~SCSPTR_RTSDT;
1914 else
1915 ctrl |= SCSPTR_RTSDT;
1916 serial_port_out(port, SCSPTR, ctrl);
1917 }
1918}
1919
1920static bool sci_get_cts(struct uart_port *port)
1921{
1922 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1923 /* Active low */
1924 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1925 } else if (sci_getreg(port, SCSPTR)->size) {
1926 /* Active low */
1927 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1928 }
1929
1930 return true;
1931}
1932
1933/*
1934 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1935 * CTS/RTS is supported in hardware by at least one port and controlled
1936 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1937 * handled via the ->init_pins() op, which is a bit of a one-way street,
1938 * lacking any ability to defer pin control -- this will later be
1939 * converted over to the GPIO framework).
1940 *
1941 * Other modes (such as loopback) are supported generically on certain
1942 * port types, but not others. For these it's sufficient to test for the
1943 * existence of the support register and simply ignore the port type.
1944 */
1945static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1946{
1947 struct sci_port *s = to_sci_port(port);
1948
1949 if (mctrl & TIOCM_LOOP) {
1950 const struct plat_sci_reg *reg;
1951
1952 /*
1953 * Standard loopback mode for SCFCR ports.
1954 */
1955 reg = sci_getreg(port, SCFCR);
1956 if (reg->size)
1957 serial_port_out(port, SCFCR,
1958 serial_port_in(port, SCFCR) |
1959 SCFCR_LOOP);
1960 }
1961
1962 mctrl_gpio_set(s->gpios, mctrl);
1963
1964 if (!s->has_rtscts)
1965 return;
1966
1967 if (!(mctrl & TIOCM_RTS)) {
1968 /* Disable Auto RTS */
1969 serial_port_out(port, SCFCR,
1970 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1971
1972 /* Clear RTS */
1973 sci_set_rts(port, 0);
1974 } else if (s->autorts) {
1975 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1976 /* Enable RTS# pin function */
1977 serial_port_out(port, SCPCR,
1978 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1979 }
1980
1981 /* Enable Auto RTS */
1982 serial_port_out(port, SCFCR,
1983 serial_port_in(port, SCFCR) | SCFCR_MCE);
1984 } else {
1985 /* Set RTS */
1986 sci_set_rts(port, 1);
1987 }
1988}
1989
1990static unsigned int sci_get_mctrl(struct uart_port *port)
1991{
1992 struct sci_port *s = to_sci_port(port);
1993 struct mctrl_gpios *gpios = s->gpios;
1994 unsigned int mctrl = 0;
1995
1996 mctrl_gpio_get(gpios, &mctrl);
1997
1998 /*
1999 * CTS/RTS is handled in hardware when supported, while nothing
2000 * else is wired up.
2001 */
2002 if (s->autorts) {
2003 if (sci_get_cts(port))
2004 mctrl |= TIOCM_CTS;
2005 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2006 mctrl |= TIOCM_CTS;
2007 }
2008 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2009 mctrl |= TIOCM_DSR;
2010 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2011 mctrl |= TIOCM_CAR;
2012
2013 return mctrl;
2014}
2015
2016static void sci_enable_ms(struct uart_port *port)
2017{
2018 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2019}
2020
2021static void sci_break_ctl(struct uart_port *port, int break_state)
2022{
2023 unsigned short scscr, scsptr;
2024 unsigned long flags;
2025
2026 /* check wheter the port has SCSPTR */
2027 if (!sci_getreg(port, SCSPTR)->size) {
2028 /*
2029 * Not supported by hardware. Most parts couple break and rx
2030 * interrupts together, with break detection always enabled.
2031 */
2032 return;
2033 }
2034
2035 spin_lock_irqsave(&port->lock, flags);
2036 scsptr = serial_port_in(port, SCSPTR);
2037 scscr = serial_port_in(port, SCSCR);
2038
2039 if (break_state == -1) {
2040 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2041 scscr &= ~SCSCR_TE;
2042 } else {
2043 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2044 scscr |= SCSCR_TE;
2045 }
2046
2047 serial_port_out(port, SCSPTR, scsptr);
2048 serial_port_out(port, SCSCR, scscr);
2049 spin_unlock_irqrestore(&port->lock, flags);
2050}
2051
2052static int sci_startup(struct uart_port *port)
2053{
2054 struct sci_port *s = to_sci_port(port);
2055 int ret;
2056
2057 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2058
2059 sci_request_dma(port);
2060
2061 ret = sci_request_irq(s);
2062 if (unlikely(ret < 0)) {
2063 sci_free_dma(port);
2064 return ret;
2065 }
2066
2067 return 0;
2068}
2069
2070static void sci_shutdown(struct uart_port *port)
2071{
2072 struct sci_port *s = to_sci_port(port);
2073 unsigned long flags;
2074 u16 scr;
2075
2076 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2077
2078 s->autorts = false;
2079 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2080
2081 spin_lock_irqsave(&port->lock, flags);
2082 sci_stop_rx(port);
2083 sci_stop_tx(port);
2084 /*
2085 * Stop RX and TX, disable related interrupts, keep clock source
2086 * and HSCIF TOT bits
2087 */
2088 scr = serial_port_in(port, SCSCR);
2089 serial_port_out(port, SCSCR, scr &
2090 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2091 spin_unlock_irqrestore(&port->lock, flags);
2092
2093#ifdef CONFIG_SERIAL_SH_SCI_DMA
2094 if (s->chan_rx) {
2095 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2096 port->line);
2097 hrtimer_cancel(&s->rx_timer);
2098 }
2099#endif
2100
2101 sci_free_irq(s);
2102 sci_free_dma(port);
2103}
2104
2105static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2106 unsigned int *srr)
2107{
2108 unsigned long freq = s->clk_rates[SCI_SCK];
2109 int err, min_err = INT_MAX;
2110 unsigned int sr;
2111
2112 if (s->port.type != PORT_HSCIF)
2113 freq *= 2;
2114
2115 for_each_sr(sr, s) {
2116 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2117 if (abs(err) >= abs(min_err))
2118 continue;
2119
2120 min_err = err;
2121 *srr = sr - 1;
2122
2123 if (!err)
2124 break;
2125 }
2126
2127 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2128 *srr + 1);
2129 return min_err;
2130}
2131
2132static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2133 unsigned long freq, unsigned int *dlr,
2134 unsigned int *srr)
2135{
2136 int err, min_err = INT_MAX;
2137 unsigned int sr, dl;
2138
2139 if (s->port.type != PORT_HSCIF)
2140 freq *= 2;
2141
2142 for_each_sr(sr, s) {
2143 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2144 dl = clamp(dl, 1U, 65535U);
2145
2146 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2147 if (abs(err) >= abs(min_err))
2148 continue;
2149
2150 min_err = err;
2151 *dlr = dl;
2152 *srr = sr - 1;
2153
2154 if (!err)
2155 break;
2156 }
2157
2158 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2159 min_err, *dlr, *srr + 1);
2160 return min_err;
2161}
2162
2163/* calculate sample rate, BRR, and clock select */
2164static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2165 unsigned int *brr, unsigned int *srr,
2166 unsigned int *cks)
2167{
2168 unsigned long freq = s->clk_rates[SCI_FCK];
2169 unsigned int sr, br, prediv, scrate, c;
2170 int err, min_err = INT_MAX;
2171
2172 if (s->port.type != PORT_HSCIF)
2173 freq *= 2;
2174
2175 /*
2176 * Find the combination of sample rate and clock select with the
2177 * smallest deviation from the desired baud rate.
2178 * Prefer high sample rates to maximise the receive margin.
2179 *
2180 * M: Receive margin (%)
2181 * N: Ratio of bit rate to clock (N = sampling rate)
2182 * D: Clock duty (D = 0 to 1.0)
2183 * L: Frame length (L = 9 to 12)
2184 * F: Absolute value of clock frequency deviation
2185 *
2186 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2187 * (|D - 0.5| / N * (1 + F))|
2188 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2189 */
2190 for_each_sr(sr, s) {
2191 for (c = 0; c <= 3; c++) {
2192 /* integerized formulas from HSCIF documentation */
2193 prediv = sr * (1 << (2 * c + 1));
2194
2195 /*
2196 * We need to calculate:
2197 *
2198 * br = freq / (prediv * bps) clamped to [1..256]
2199 * err = freq / (br * prediv) - bps
2200 *
2201 * Watch out for overflow when calculating the desired
2202 * sampling clock rate!
2203 */
2204 if (bps > UINT_MAX / prediv)
2205 break;
2206
2207 scrate = prediv * bps;
2208 br = DIV_ROUND_CLOSEST(freq, scrate);
2209 br = clamp(br, 1U, 256U);
2210
2211 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2212 if (abs(err) >= abs(min_err))
2213 continue;
2214
2215 min_err = err;
2216 *brr = br - 1;
2217 *srr = sr - 1;
2218 *cks = c;
2219
2220 if (!err)
2221 goto found;
2222 }
2223 }
2224
2225found:
2226 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2227 min_err, *brr, *srr + 1, *cks);
2228 return min_err;
2229}
2230
2231static void sci_reset(struct uart_port *port)
2232{
2233 const struct plat_sci_reg *reg;
2234 unsigned int status;
2235 struct sci_port *s = to_sci_port(port);
2236
2237 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2238
2239 reg = sci_getreg(port, SCFCR);
2240 if (reg->size)
2241 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2242
2243 sci_clear_SCxSR(port,
2244 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2245 SCxSR_BREAK_CLEAR(port));
2246 if (sci_getreg(port, SCLSR)->size) {
2247 status = serial_port_in(port, SCLSR);
2248 status &= ~(SCLSR_TO | SCLSR_ORER);
2249 serial_port_out(port, SCLSR, status);
2250 }
2251
2252 if (s->rx_trigger > 1) {
2253 if (s->rx_fifo_timeout) {
2254 scif_set_rtrg(port, 1);
2255 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2256 } else {
2257 if (port->type == PORT_SCIFA ||
2258 port->type == PORT_SCIFB)
2259 scif_set_rtrg(port, 1);
2260 else
2261 scif_set_rtrg(port, s->rx_trigger);
2262 }
2263 }
2264}
2265
2266static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2267 struct ktermios *old)
2268{
2269 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2270 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2271 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2272 struct sci_port *s = to_sci_port(port);
2273 const struct plat_sci_reg *reg;
2274 int min_err = INT_MAX, err;
2275 unsigned long max_freq = 0;
2276 int best_clk = -1;
2277 unsigned long flags;
2278
2279 if ((termios->c_cflag & CSIZE) == CS7)
2280 smr_val |= SCSMR_CHR;
2281 if (termios->c_cflag & PARENB)
2282 smr_val |= SCSMR_PE;
2283 if (termios->c_cflag & PARODD)
2284 smr_val |= SCSMR_PE | SCSMR_ODD;
2285 if (termios->c_cflag & CSTOPB)
2286 smr_val |= SCSMR_STOP;
2287
2288 /*
2289 * earlyprintk comes here early on with port->uartclk set to zero.
2290 * the clock framework is not up and running at this point so here
2291 * we assume that 115200 is the maximum baud rate. please note that
2292 * the baud rate is not programmed during earlyprintk - it is assumed
2293 * that the previous boot loader has enabled required clocks and
2294 * setup the baud rate generator hardware for us already.
2295 */
2296 if (!port->uartclk) {
2297 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2298 goto done;
2299 }
2300
2301 for (i = 0; i < SCI_NUM_CLKS; i++)
2302 max_freq = max(max_freq, s->clk_rates[i]);
2303
2304 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2305 if (!baud)
2306 goto done;
2307
2308 /*
2309 * There can be multiple sources for the sampling clock. Find the one
2310 * that gives us the smallest deviation from the desired baud rate.
2311 */
2312
2313 /* Optional Undivided External Clock */
2314 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2315 port->type != PORT_SCIFB) {
2316 err = sci_sck_calc(s, baud, &srr1);
2317 if (abs(err) < abs(min_err)) {
2318 best_clk = SCI_SCK;
2319 scr_val = SCSCR_CKE1;
2320 sccks = SCCKS_CKS;
2321 min_err = err;
2322 srr = srr1;
2323 if (!err)
2324 goto done;
2325 }
2326 }
2327
2328 /* Optional BRG Frequency Divided External Clock */
2329 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2330 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2331 &srr1);
2332 if (abs(err) < abs(min_err)) {
2333 best_clk = SCI_SCIF_CLK;
2334 scr_val = SCSCR_CKE1;
2335 sccks = 0;
2336 min_err = err;
2337 dl = dl1;
2338 srr = srr1;
2339 if (!err)
2340 goto done;
2341 }
2342 }
2343
2344 /* Optional BRG Frequency Divided Internal Clock */
2345 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2346 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2347 &srr1);
2348 if (abs(err) < abs(min_err)) {
2349 best_clk = SCI_BRG_INT;
2350 scr_val = SCSCR_CKE1;
2351 sccks = SCCKS_XIN;
2352 min_err = err;
2353 dl = dl1;
2354 srr = srr1;
2355 if (!min_err)
2356 goto done;
2357 }
2358 }
2359
2360 /* Divided Functional Clock using standard Bit Rate Register */
2361 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2362 if (abs(err) < abs(min_err)) {
2363 best_clk = SCI_FCK;
2364 scr_val = 0;
2365 min_err = err;
2366 brr = brr1;
2367 srr = srr1;
2368 cks = cks1;
2369 }
2370
2371done:
2372 if (best_clk >= 0)
2373 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2374 s->clks[best_clk], baud, min_err);
2375
2376 sci_port_enable(s);
2377
2378 /*
2379 * Program the optional External Baud Rate Generator (BRG) first.
2380 * It controls the mux to select (H)SCK or frequency divided clock.
2381 */
2382 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2383 serial_port_out(port, SCDL, dl);
2384 serial_port_out(port, SCCKS, sccks);
2385 }
2386
2387 spin_lock_irqsave(&port->lock, flags);
2388
2389 sci_reset(port);
2390
2391 uart_update_timeout(port, termios->c_cflag, baud);
2392
2393 if (best_clk >= 0) {
2394 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2395 switch (srr + 1) {
2396 case 5: smr_val |= SCSMR_SRC_5; break;
2397 case 7: smr_val |= SCSMR_SRC_7; break;
2398 case 11: smr_val |= SCSMR_SRC_11; break;
2399 case 13: smr_val |= SCSMR_SRC_13; break;
2400 case 16: smr_val |= SCSMR_SRC_16; break;
2401 case 17: smr_val |= SCSMR_SRC_17; break;
2402 case 19: smr_val |= SCSMR_SRC_19; break;
2403 case 27: smr_val |= SCSMR_SRC_27; break;
2404 }
2405 smr_val |= cks;
2406 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2407 serial_port_out(port, SCSMR, smr_val);
2408 serial_port_out(port, SCBRR, brr);
2409 if (sci_getreg(port, HSSRR)->size)
2410 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2411
2412 /* Wait one bit interval */
2413 udelay((1000000 + (baud - 1)) / baud);
2414 } else {
2415 /* Don't touch the bit rate configuration */
2416 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2417 smr_val |= serial_port_in(port, SCSMR) &
2418 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2419 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2420 serial_port_out(port, SCSMR, smr_val);
2421 }
2422
2423 sci_init_pins(port, termios->c_cflag);
2424
2425 port->status &= ~UPSTAT_AUTOCTS;
2426 s->autorts = false;
2427 reg = sci_getreg(port, SCFCR);
2428 if (reg->size) {
2429 unsigned short ctrl = serial_port_in(port, SCFCR);
2430
2431 if ((port->flags & UPF_HARD_FLOW) &&
2432 (termios->c_cflag & CRTSCTS)) {
2433 /* There is no CTS interrupt to restart the hardware */
2434 port->status |= UPSTAT_AUTOCTS;
2435 /* MCE is enabled when RTS is raised */
2436 s->autorts = true;
2437 }
2438
2439 /*
2440 * As we've done a sci_reset() above, ensure we don't
2441 * interfere with the FIFOs while toggling MCE. As the
2442 * reset values could still be set, simply mask them out.
2443 */
2444 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2445
2446 serial_port_out(port, SCFCR, ctrl);
2447 }
2448 if (port->flags & UPF_HARD_FLOW) {
2449 /* Refresh (Auto) RTS */
2450 sci_set_mctrl(port, port->mctrl);
2451 }
2452
2453 scr_val |= SCSCR_RE | SCSCR_TE |
2454 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2455 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2456 if ((srr + 1 == 5) &&
2457 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2458 /*
2459 * In asynchronous mode, when the sampling rate is 1/5, first
2460 * received data may become invalid on some SCIFA and SCIFB.
2461 * To avoid this problem wait more than 1 serial data time (1
2462 * bit time x serial data number) after setting SCSCR.RE = 1.
2463 */
2464 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2465 }
2466
2467 /*
2468 * Calculate delay for 2 DMA buffers (4 FIFO).
2469 * See serial_core.c::uart_update_timeout().
2470 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2471 * function calculates 1 jiffie for the data plus 5 jiffies for the
2472 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2473 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2474 * value obtained by this formula is too small. Therefore, if the value
2475 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2476 */
2477 /* byte size and parity */
2478 switch (termios->c_cflag & CSIZE) {
2479 case CS5:
2480 bits = 7;
2481 break;
2482 case CS6:
2483 bits = 8;
2484 break;
2485 case CS7:
2486 bits = 9;
2487 break;
2488 default:
2489 bits = 10;
2490 break;
2491 }
2492
2493 if (termios->c_cflag & CSTOPB)
2494 bits++;
2495 if (termios->c_cflag & PARENB)
2496 bits++;
2497
2498 s->rx_frame = (10000 * bits) / (baud / 100);
2499#ifdef CONFIG_SERIAL_SH_SCI_DMA
2500 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2501 if (s->rx_timeout < 20)
2502 s->rx_timeout = 20;
2503#endif
2504
2505 if ((termios->c_cflag & CREAD) != 0)
2506 sci_start_rx(port);
2507
2508 spin_unlock_irqrestore(&port->lock, flags);
2509
2510 sci_port_disable(s);
2511
2512 if (UART_ENABLE_MS(port, termios->c_cflag))
2513 sci_enable_ms(port);
2514}
2515
2516static void sci_pm(struct uart_port *port, unsigned int state,
2517 unsigned int oldstate)
2518{
2519 struct sci_port *sci_port = to_sci_port(port);
2520
2521 switch (state) {
2522 case UART_PM_STATE_OFF:
2523 sci_port_disable(sci_port);
2524 break;
2525 default:
2526 sci_port_enable(sci_port);
2527 break;
2528 }
2529}
2530
2531static const char *sci_type(struct uart_port *port)
2532{
2533 switch (port->type) {
2534 case PORT_IRDA:
2535 return "irda";
2536 case PORT_SCI:
2537 return "sci";
2538 case PORT_SCIF:
2539 return "scif";
2540 case PORT_SCIFA:
2541 return "scifa";
2542 case PORT_SCIFB:
2543 return "scifb";
2544 case PORT_HSCIF:
2545 return "hscif";
2546 }
2547
2548 return NULL;
2549}
2550
2551static int sci_remap_port(struct uart_port *port)
2552{
2553 struct sci_port *sport = to_sci_port(port);
2554
2555 /*
2556 * Nothing to do if there's already an established membase.
2557 */
2558 if (port->membase)
2559 return 0;
2560
2561 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2562 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2563 if (unlikely(!port->membase)) {
2564 dev_err(port->dev, "can't remap port#%d\n", port->line);
2565 return -ENXIO;
2566 }
2567 } else {
2568 /*
2569 * For the simple (and majority of) cases where we don't
2570 * need to do any remapping, just cast the cookie
2571 * directly.
2572 */
2573 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2574 }
2575
2576 return 0;
2577}
2578
2579static void sci_release_port(struct uart_port *port)
2580{
2581 struct sci_port *sport = to_sci_port(port);
2582
2583 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2584 iounmap(port->membase);
2585 port->membase = NULL;
2586 }
2587
2588 release_mem_region(port->mapbase, sport->reg_size);
2589}
2590
2591static int sci_request_port(struct uart_port *port)
2592{
2593 struct resource *res;
2594 struct sci_port *sport = to_sci_port(port);
2595 int ret;
2596
2597 res = request_mem_region(port->mapbase, sport->reg_size,
2598 dev_name(port->dev));
2599 if (unlikely(res == NULL)) {
2600 dev_err(port->dev, "request_mem_region failed.");
2601 return -EBUSY;
2602 }
2603
2604 ret = sci_remap_port(port);
2605 if (unlikely(ret != 0)) {
2606 release_resource(res);
2607 return ret;
2608 }
2609
2610 return 0;
2611}
2612
2613static void sci_config_port(struct uart_port *port, int flags)
2614{
2615 if (flags & UART_CONFIG_TYPE) {
2616 struct sci_port *sport = to_sci_port(port);
2617
2618 port->type = sport->cfg->type;
2619 sci_request_port(port);
2620 }
2621}
2622
2623static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2624{
2625 if (ser->baud_base < 2400)
2626 /* No paper tape reader for Mitch.. */
2627 return -EINVAL;
2628
2629 return 0;
2630}
2631
2632static const struct uart_ops sci_uart_ops = {
2633 .tx_empty = sci_tx_empty,
2634 .set_mctrl = sci_set_mctrl,
2635 .get_mctrl = sci_get_mctrl,
2636 .start_tx = sci_start_tx,
2637 .stop_tx = sci_stop_tx,
2638 .stop_rx = sci_stop_rx,
2639 .enable_ms = sci_enable_ms,
2640 .break_ctl = sci_break_ctl,
2641 .startup = sci_startup,
2642 .shutdown = sci_shutdown,
2643 .flush_buffer = sci_flush_buffer,
2644 .set_termios = sci_set_termios,
2645 .pm = sci_pm,
2646 .type = sci_type,
2647 .release_port = sci_release_port,
2648 .request_port = sci_request_port,
2649 .config_port = sci_config_port,
2650 .verify_port = sci_verify_port,
2651#ifdef CONFIG_CONSOLE_POLL
2652 .poll_get_char = sci_poll_get_char,
2653 .poll_put_char = sci_poll_put_char,
2654#endif
2655};
2656
2657static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2658{
2659 const char *clk_names[] = {
2660 [SCI_FCK] = "fck",
2661 [SCI_SCK] = "sck",
2662 [SCI_BRG_INT] = "brg_int",
2663 [SCI_SCIF_CLK] = "scif_clk",
2664 };
2665 struct clk *clk;
2666 unsigned int i;
2667
2668 if (sci_port->cfg->type == PORT_HSCIF)
2669 clk_names[SCI_SCK] = "hsck";
2670
2671 for (i = 0; i < SCI_NUM_CLKS; i++) {
2672 clk = devm_clk_get(dev, clk_names[i]);
2673 if (PTR_ERR(clk) == -EPROBE_DEFER)
2674 return -EPROBE_DEFER;
2675
2676 if (IS_ERR(clk) && i == SCI_FCK) {
2677 /*
2678 * "fck" used to be called "sci_ick", and we need to
2679 * maintain DT backward compatibility.
2680 */
2681 clk = devm_clk_get(dev, "sci_ick");
2682 if (PTR_ERR(clk) == -EPROBE_DEFER)
2683 return -EPROBE_DEFER;
2684
2685 if (!IS_ERR(clk))
2686 goto found;
2687
2688 /*
2689 * Not all SH platforms declare a clock lookup entry
2690 * for SCI devices, in which case we need to get the
2691 * global "peripheral_clk" clock.
2692 */
2693 clk = devm_clk_get(dev, "peripheral_clk");
2694 if (!IS_ERR(clk))
2695 goto found;
2696
2697 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2698 PTR_ERR(clk));
2699 return PTR_ERR(clk);
2700 }
2701
2702found:
2703 if (IS_ERR(clk))
2704 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2705 PTR_ERR(clk));
2706 else
2707 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2708 clk, clk);
2709 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2710 }
2711 return 0;
2712}
2713
2714static const struct sci_port_params *
2715sci_probe_regmap(const struct plat_sci_port *cfg)
2716{
2717 unsigned int regtype;
2718
2719 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2720 return &sci_port_params[cfg->regtype];
2721
2722 switch (cfg->type) {
2723 case PORT_SCI:
2724 regtype = SCIx_SCI_REGTYPE;
2725 break;
2726 case PORT_IRDA:
2727 regtype = SCIx_IRDA_REGTYPE;
2728 break;
2729 case PORT_SCIFA:
2730 regtype = SCIx_SCIFA_REGTYPE;
2731 break;
2732 case PORT_SCIFB:
2733 regtype = SCIx_SCIFB_REGTYPE;
2734 break;
2735 case PORT_SCIF:
2736 /*
2737 * The SH-4 is a bit of a misnomer here, although that's
2738 * where this particular port layout originated. This
2739 * configuration (or some slight variation thereof)
2740 * remains the dominant model for all SCIFs.
2741 */
2742 regtype = SCIx_SH4_SCIF_REGTYPE;
2743 break;
2744 case PORT_HSCIF:
2745 regtype = SCIx_HSCIF_REGTYPE;
2746 break;
2747 default:
2748 pr_err("Can't probe register map for given port\n");
2749 return NULL;
2750 }
2751
2752 return &sci_port_params[regtype];
2753}
2754
2755static int sci_init_single(struct platform_device *dev,
2756 struct sci_port *sci_port, unsigned int index,
2757 const struct plat_sci_port *p, bool early)
2758{
2759 struct uart_port *port = &sci_port->port;
2760 const struct resource *res;
2761 unsigned int i;
2762 int ret;
2763
2764 sci_port->cfg = p;
2765
2766 port->ops = &sci_uart_ops;
2767 port->iotype = UPIO_MEM;
2768 port->line = index;
2769
2770 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2771 if (res == NULL)
2772 return -ENOMEM;
2773
2774 port->mapbase = res->start;
2775 sci_port->reg_size = resource_size(res);
2776
2777 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2778 sci_port->irqs[i] = platform_get_irq(dev, i);
2779
2780 /* The SCI generates several interrupts. They can be muxed together or
2781 * connected to different interrupt lines. In the muxed case only one
2782 * interrupt resource is specified. In the non-muxed case three or four
2783 * interrupt resources are specified, as the BRI interrupt is optional.
2784 */
2785 if (sci_port->irqs[0] < 0)
2786 return -ENXIO;
2787
2788 if (sci_port->irqs[1] < 0) {
2789 sci_port->irqs[1] = sci_port->irqs[0];
2790 sci_port->irqs[2] = sci_port->irqs[0];
2791 sci_port->irqs[3] = sci_port->irqs[0];
2792 }
2793
2794 sci_port->params = sci_probe_regmap(p);
2795 if (unlikely(sci_port->params == NULL))
2796 return -EINVAL;
2797
2798 switch (p->type) {
2799 case PORT_SCIFB:
2800 sci_port->rx_trigger = 48;
2801 break;
2802 case PORT_HSCIF:
2803 sci_port->rx_trigger = 64;
2804 break;
2805 case PORT_SCIFA:
2806 sci_port->rx_trigger = 32;
2807 break;
2808 case PORT_SCIF:
2809 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2810 /* RX triggering not implemented for this IP */
2811 sci_port->rx_trigger = 1;
2812 else
2813 sci_port->rx_trigger = 8;
2814 break;
2815 default:
2816 sci_port->rx_trigger = 1;
2817 break;
2818 }
2819
2820 sci_port->rx_fifo_timeout = 0;
2821 sci_port->hscif_tot = 0;
2822
2823 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2824 * match the SoC datasheet, this should be investigated. Let platform
2825 * data override the sampling rate for now.
2826 */
2827 sci_port->sampling_rate_mask = p->sampling_rate
2828 ? SCI_SR(p->sampling_rate)
2829 : sci_port->params->sampling_rate_mask;
2830
2831 if (!early) {
2832 ret = sci_init_clocks(sci_port, &dev->dev);
2833 if (ret < 0)
2834 return ret;
2835
2836 port->dev = &dev->dev;
2837
2838 pm_runtime_enable(&dev->dev);
2839 }
2840
2841 port->type = p->type;
2842 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2843 port->fifosize = sci_port->params->fifosize;
2844
2845 if (port->type == PORT_SCI) {
2846 if (sci_port->reg_size >= 0x20)
2847 port->regshift = 2;
2848 else
2849 port->regshift = 1;
2850 }
2851
2852 /*
2853 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2854 * for the multi-IRQ ports, which is where we are primarily
2855 * concerned with the shutdown path synchronization.
2856 *
2857 * For the muxed case there's nothing more to do.
2858 */
2859 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2860 port->irqflags = 0;
2861
2862 port->serial_in = sci_serial_in;
2863 port->serial_out = sci_serial_out;
2864
2865 return 0;
2866}
2867
2868static void sci_cleanup_single(struct sci_port *port)
2869{
2870 pm_runtime_disable(port->port.dev);
2871}
2872
2873#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2874 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2875static void serial_console_putchar(struct uart_port *port, int ch)
2876{
2877 sci_poll_put_char(port, ch);
2878}
2879
2880/*
2881 * Print a string to the serial port trying not to disturb
2882 * any possible real use of the port...
2883 */
2884static void serial_console_write(struct console *co, const char *s,
2885 unsigned count)
2886{
2887 struct sci_port *sci_port = &sci_ports[co->index];
2888 struct uart_port *port = &sci_port->port;
2889 unsigned short bits, ctrl, ctrl_temp;
2890 unsigned long flags;
2891 int locked = 1;
2892
2893 local_irq_save(flags);
2894#if defined(SUPPORT_SYSRQ)
2895 if (port->sysrq)
2896 locked = 0;
2897 else
2898#endif
2899 if (oops_in_progress)
2900 locked = spin_trylock(&port->lock);
2901 else
2902 spin_lock(&port->lock);
2903
2904 /* first save SCSCR then disable interrupts, keep clock source */
2905 ctrl = serial_port_in(port, SCSCR);
2906 ctrl_temp = SCSCR_RE | SCSCR_TE |
2907 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2908 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2909 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
2910
2911 uart_console_write(port, s, count, serial_console_putchar);
2912
2913 /* wait until fifo is empty and last bit has been transmitted */
2914 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2915 while ((serial_port_in(port, SCxSR) & bits) != bits)
2916 cpu_relax();
2917
2918 /* restore the SCSCR */
2919 serial_port_out(port, SCSCR, ctrl);
2920
2921 if (locked)
2922 spin_unlock(&port->lock);
2923 local_irq_restore(flags);
2924}
2925
2926static int serial_console_setup(struct console *co, char *options)
2927{
2928 struct sci_port *sci_port;
2929 struct uart_port *port;
2930 int baud = 115200;
2931 int bits = 8;
2932 int parity = 'n';
2933 int flow = 'n';
2934 int ret;
2935
2936 /*
2937 * Refuse to handle any bogus ports.
2938 */
2939 if (co->index < 0 || co->index >= SCI_NPORTS)
2940 return -ENODEV;
2941
2942 sci_port = &sci_ports[co->index];
2943 port = &sci_port->port;
2944
2945 /*
2946 * Refuse to handle uninitialized ports.
2947 */
2948 if (!port->ops)
2949 return -ENODEV;
2950
2951 ret = sci_remap_port(port);
2952 if (unlikely(ret != 0))
2953 return ret;
2954
2955 if (options)
2956 uart_parse_options(options, &baud, &parity, &bits, &flow);
2957
2958 return uart_set_options(port, co, baud, parity, bits, flow);
2959}
2960
2961static struct console serial_console = {
2962 .name = "ttySC",
2963 .device = uart_console_device,
2964 .write = serial_console_write,
2965 .setup = serial_console_setup,
2966 .flags = CON_PRINTBUFFER,
2967 .index = -1,
2968 .data = &sci_uart_driver,
2969};
2970
2971static struct console early_serial_console = {
2972 .name = "early_ttySC",
2973 .write = serial_console_write,
2974 .flags = CON_PRINTBUFFER,
2975 .index = -1,
2976};
2977
2978static char early_serial_buf[32];
2979
2980static int sci_probe_earlyprintk(struct platform_device *pdev)
2981{
2982 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2983
2984 if (early_serial_console.data)
2985 return -EEXIST;
2986
2987 early_serial_console.index = pdev->id;
2988
2989 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2990
2991 serial_console_setup(&early_serial_console, early_serial_buf);
2992
2993 if (!strstr(early_serial_buf, "keep"))
2994 early_serial_console.flags |= CON_BOOT;
2995
2996 register_console(&early_serial_console);
2997 return 0;
2998}
2999
3000#define SCI_CONSOLE (&serial_console)
3001
3002#else
3003static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3004{
3005 return -EINVAL;
3006}
3007
3008#define SCI_CONSOLE NULL
3009
3010#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3011
3012static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3013
3014static DEFINE_MUTEX(sci_uart_registration_lock);
3015static struct uart_driver sci_uart_driver = {
3016 .owner = THIS_MODULE,
3017 .driver_name = "sci",
3018 .dev_name = "ttySC",
3019 .major = SCI_MAJOR,
3020 .minor = SCI_MINOR_START,
3021 .nr = SCI_NPORTS,
3022 .cons = SCI_CONSOLE,
3023};
3024
3025static int sci_remove(struct platform_device *dev)
3026{
3027 struct sci_port *port = platform_get_drvdata(dev);
3028
3029 uart_remove_one_port(&sci_uart_driver, &port->port);
3030
3031 sci_cleanup_single(port);
3032
3033 if (port->port.fifosize > 1) {
3034 sysfs_remove_file(&dev->dev.kobj,
3035 &dev_attr_rx_fifo_trigger.attr);
3036 }
3037 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3038 port->port.type == PORT_HSCIF) {
3039 sysfs_remove_file(&dev->dev.kobj,
3040 &dev_attr_rx_fifo_timeout.attr);
3041 }
3042
3043 return 0;
3044}
3045
3046
3047#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3048#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3049#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3050
3051static const struct of_device_id of_sci_match[] = {
3052 /* SoC-specific types */
3053 {
3054 .compatible = "renesas,scif-r7s72100",
3055 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3056 },
3057 /* Family-specific types */
3058 {
3059 .compatible = "renesas,rcar-gen1-scif",
3060 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3061 }, {
3062 .compatible = "renesas,rcar-gen2-scif",
3063 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3064 }, {
3065 .compatible = "renesas,rcar-gen3-scif",
3066 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3067 },
3068 /* Generic types */
3069 {
3070 .compatible = "renesas,scif",
3071 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3072 }, {
3073 .compatible = "renesas,scifa",
3074 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3075 }, {
3076 .compatible = "renesas,scifb",
3077 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3078 }, {
3079 .compatible = "renesas,hscif",
3080 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3081 }, {
3082 .compatible = "renesas,sci",
3083 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3084 }, {
3085 /* Terminator */
3086 },
3087};
3088MODULE_DEVICE_TABLE(of, of_sci_match);
3089
3090static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3091 unsigned int *dev_id)
3092{
3093 struct device_node *np = pdev->dev.of_node;
3094 struct plat_sci_port *p;
3095 struct sci_port *sp;
3096 const void *data;
3097 int id;
3098
3099 if (!IS_ENABLED(CONFIG_OF) || !np)
3100 return NULL;
3101
3102 data = of_device_get_match_data(&pdev->dev);
3103
3104 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3105 if (!p)
3106 return NULL;
3107
3108 /* Get the line number from the aliases node. */
3109 id = of_alias_get_id(np, "serial");
3110 if (id < 0) {
3111 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3112 return NULL;
3113 }
3114 if (id >= ARRAY_SIZE(sci_ports)) {
3115 dev_err(&pdev->dev, "serial%d out of range\n", id);
3116 return NULL;
3117 }
3118
3119 sp = &sci_ports[id];
3120 *dev_id = id;
3121
3122 p->type = SCI_OF_TYPE(data);
3123 p->regtype = SCI_OF_REGTYPE(data);
3124
3125 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3126
3127 return p;
3128}
3129
3130static int sci_probe_single(struct platform_device *dev,
3131 unsigned int index,
3132 struct plat_sci_port *p,
3133 struct sci_port *sciport)
3134{
3135 int ret;
3136
3137 /* Sanity check */
3138 if (unlikely(index >= SCI_NPORTS)) {
3139 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3140 index+1, SCI_NPORTS);
3141 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3142 return -EINVAL;
3143 }
3144
3145 mutex_lock(&sci_uart_registration_lock);
3146 if (!sci_uart_driver.state) {
3147 ret = uart_register_driver(&sci_uart_driver);
3148 if (ret) {
3149 mutex_unlock(&sci_uart_registration_lock);
3150 return ret;
3151 }
3152 }
3153 mutex_unlock(&sci_uart_registration_lock);
3154
3155 ret = sci_init_single(dev, sciport, index, p, false);
3156 if (ret)
3157 return ret;
3158
3159 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3160 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3161 return PTR_ERR(sciport->gpios);
3162
3163 if (sciport->has_rtscts) {
3164 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3165 UART_GPIO_CTS)) ||
3166 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3167 UART_GPIO_RTS))) {
3168 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3169 return -EINVAL;
3170 }
3171 sciport->port.flags |= UPF_HARD_FLOW;
3172 }
3173
3174 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3175 if (ret) {
3176 sci_cleanup_single(sciport);
3177 return ret;
3178 }
3179
3180 return 0;
3181}
3182
3183static int sci_probe(struct platform_device *dev)
3184{
3185 struct plat_sci_port *p;
3186 struct sci_port *sp;
3187 unsigned int dev_id;
3188 int ret;
3189
3190 /*
3191 * If we've come here via earlyprintk initialization, head off to
3192 * the special early probe. We don't have sufficient device state
3193 * to make it beyond this yet.
3194 */
3195 if (is_early_platform_device(dev))
3196 return sci_probe_earlyprintk(dev);
3197
3198 if (dev->dev.of_node) {
3199 p = sci_parse_dt(dev, &dev_id);
3200 if (p == NULL)
3201 return -EINVAL;
3202 } else {
3203 p = dev->dev.platform_data;
3204 if (p == NULL) {
3205 dev_err(&dev->dev, "no platform data supplied\n");
3206 return -EINVAL;
3207 }
3208
3209 dev_id = dev->id;
3210 }
3211
3212 sp = &sci_ports[dev_id];
3213 platform_set_drvdata(dev, sp);
3214
3215 ret = sci_probe_single(dev, dev_id, p, sp);
3216 if (ret)
3217 return ret;
3218
3219 if (sp->port.fifosize > 1) {
3220 ret = sysfs_create_file(&dev->dev.kobj,
3221 &dev_attr_rx_fifo_trigger.attr);
3222 if (ret)
3223 return ret;
3224 }
3225 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3226 sp->port.type == PORT_HSCIF) {
3227 ret = sysfs_create_file(&dev->dev.kobj,
3228 &dev_attr_rx_fifo_timeout.attr);
3229 if (ret) {
3230 if (sp->port.fifosize > 1) {
3231 sysfs_remove_file(&dev->dev.kobj,
3232 &dev_attr_rx_fifo_trigger.attr);
3233 }
3234 return ret;
3235 }
3236 }
3237
3238#ifdef CONFIG_SH_STANDARD_BIOS
3239 sh_bios_gdb_detach();
3240#endif
3241
3242 return 0;
3243}
3244
3245static __maybe_unused int sci_suspend(struct device *dev)
3246{
3247 struct sci_port *sport = dev_get_drvdata(dev);
3248
3249 if (sport)
3250 uart_suspend_port(&sci_uart_driver, &sport->port);
3251
3252 return 0;
3253}
3254
3255static __maybe_unused int sci_resume(struct device *dev)
3256{
3257 struct sci_port *sport = dev_get_drvdata(dev);
3258
3259 if (sport)
3260 uart_resume_port(&sci_uart_driver, &sport->port);
3261
3262 return 0;
3263}
3264
3265static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3266
3267static struct platform_driver sci_driver = {
3268 .probe = sci_probe,
3269 .remove = sci_remove,
3270 .driver = {
3271 .name = "sh-sci",
3272 .pm = &sci_dev_pm_ops,
3273 .of_match_table = of_match_ptr(of_sci_match),
3274 },
3275};
3276
3277static int __init sci_init(void)
3278{
3279 pr_info("%s\n", banner);
3280
3281 return platform_driver_register(&sci_driver);
3282}
3283
3284static void __exit sci_exit(void)
3285{
3286 platform_driver_unregister(&sci_driver);
3287
3288 if (sci_uart_driver.state)
3289 uart_unregister_driver(&sci_uart_driver);
3290}
3291
3292#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3293early_platform_init_buffer("earlyprintk", &sci_driver,
3294 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3295#endif
3296#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3297static struct plat_sci_port port_cfg __initdata;
3298
3299static int __init early_console_setup(struct earlycon_device *device,
3300 int type)
3301{
3302 if (!device->port.membase)
3303 return -ENODEV;
3304
3305 device->port.serial_in = sci_serial_in;
3306 device->port.serial_out = sci_serial_out;
3307 device->port.type = type;
3308 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3309 port_cfg.type = type;
3310 sci_ports[0].cfg = &port_cfg;
3311 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3312 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3313 sci_serial_out(&sci_ports[0].port, SCSCR,
3314 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3315
3316 device->con->write = serial_console_write;
3317 return 0;
3318}
3319static int __init sci_early_console_setup(struct earlycon_device *device,
3320 const char *opt)
3321{
3322 return early_console_setup(device, PORT_SCI);
3323}
3324static int __init scif_early_console_setup(struct earlycon_device *device,
3325 const char *opt)
3326{
3327 return early_console_setup(device, PORT_SCIF);
3328}
3329static int __init scifa_early_console_setup(struct earlycon_device *device,
3330 const char *opt)
3331{
3332 return early_console_setup(device, PORT_SCIFA);
3333}
3334static int __init scifb_early_console_setup(struct earlycon_device *device,
3335 const char *opt)
3336{
3337 return early_console_setup(device, PORT_SCIFB);
3338}
3339static int __init hscif_early_console_setup(struct earlycon_device *device,
3340 const char *opt)
3341{
3342 return early_console_setup(device, PORT_HSCIF);
3343}
3344
3345OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3346OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3347OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3348OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3349OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3350#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3351
3352module_init(sci_init);
3353module_exit(sci_exit);
3354
3355MODULE_LICENSE("GPL");
3356MODULE_ALIAS("platform:sh-sci");
3357MODULE_AUTHOR("Paul Mundt");
3358MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");