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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Atmel Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2013 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
7 *
8 * Links to reference manuals for the supported PWM chips can be found in
9 * Documentation/arch/arm/microchip.rst.
10 *
11 * Limitations:
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
14 *
15 * Software bugs/possible improvements:
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
19 * functionality could be used.
20 */
21
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/pwm.h>
30#include <linux/slab.h>
31
32/* The following is global registers for PWM controller */
33#define PWM_ENA 0x04
34#define PWM_DIS 0x08
35#define PWM_SR 0x0C
36#define PWM_ISR 0x1C
37/* Bit field in SR */
38#define PWM_SR_ALL_CH_MASK 0x0F
39
40/* The following register is PWM channel related registers */
41#define PWM_CH_REG_OFFSET 0x200
42#define PWM_CH_REG_SIZE 0x20
43
44#define PWM_CMR 0x0
45/* Bit field in CMR */
46#define PWM_CMR_CPOL (1 << 9)
47#define PWM_CMR_UPD_CDTY (1 << 10)
48#define PWM_CMR_CPRE_MSK 0xF
49
50/* The following registers for PWM v1 */
51#define PWMV1_CDTY 0x04
52#define PWMV1_CPRD 0x08
53#define PWMV1_CUPD 0x10
54
55/* The following registers for PWM v2 */
56#define PWMV2_CDTY 0x04
57#define PWMV2_CDTYUPD 0x08
58#define PWMV2_CPRD 0x0C
59#define PWMV2_CPRDUPD 0x10
60
61#define PWM_MAX_PRES 10
62
63struct atmel_pwm_registers {
64 u8 period;
65 u8 period_upd;
66 u8 duty;
67 u8 duty_upd;
68};
69
70struct atmel_pwm_config {
71 u32 period_bits;
72};
73
74struct atmel_pwm_data {
75 struct atmel_pwm_registers regs;
76 struct atmel_pwm_config cfg;
77};
78
79struct atmel_pwm_chip {
80 struct pwm_chip chip;
81 struct clk *clk;
82 void __iomem *base;
83 const struct atmel_pwm_data *data;
84
85 /*
86 * The hardware supports a mechanism to update a channel's duty cycle at
87 * the end of the currently running period. When such an update is
88 * pending we delay disabling the PWM until the new configuration is
89 * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
90 * might not result in an inactive output.
91 * This bitmask tracks for which channels an update is pending in
92 * hardware.
93 */
94 u32 update_pending;
95
96 /* Protects .update_pending */
97 spinlock_t lock;
98};
99
100static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
101{
102 return container_of(chip, struct atmel_pwm_chip, chip);
103}
104
105static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
106 unsigned long offset)
107{
108 return readl_relaxed(chip->base + offset);
109}
110
111static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
112 unsigned long offset, unsigned long val)
113{
114 writel_relaxed(val, chip->base + offset);
115}
116
117static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
118 unsigned int ch, unsigned long offset)
119{
120 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
121
122 return atmel_pwm_readl(chip, base + offset);
123}
124
125static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
126 unsigned int ch, unsigned long offset,
127 unsigned long val)
128{
129 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
130
131 atmel_pwm_writel(chip, base + offset, val);
132}
133
134static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
135{
136 /*
137 * Each channel that has its bit in ISR set started a new period since
138 * ISR was cleared and so there is no more update pending. Note that
139 * reading ISR clears it, so this needs to handle all channels to not
140 * loose information.
141 */
142 u32 isr = atmel_pwm_readl(chip, PWM_ISR);
143
144 chip->update_pending &= ~isr;
145}
146
147static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
148{
149 spin_lock(&chip->lock);
150
151 /*
152 * Clear pending flags in hardware because otherwise there might still
153 * be a stale flag in ISR.
154 */
155 atmel_pwm_update_pending(chip);
156
157 chip->update_pending |= (1 << ch);
158
159 spin_unlock(&chip->lock);
160}
161
162static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
163{
164 int ret = 0;
165
166 spin_lock(&chip->lock);
167
168 if (chip->update_pending & (1 << ch)) {
169 atmel_pwm_update_pending(chip);
170
171 if (chip->update_pending & (1 << ch))
172 ret = 1;
173 }
174
175 spin_unlock(&chip->lock);
176
177 return ret;
178}
179
180static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
181{
182 unsigned long timeout = jiffies + 2 * HZ;
183 int ret;
184
185 while ((ret = atmel_pwm_test_pending(chip, ch)) &&
186 time_before(jiffies, timeout))
187 usleep_range(10, 100);
188
189 return ret ? -ETIMEDOUT : 0;
190}
191
192static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
193 unsigned long clkrate,
194 const struct pwm_state *state,
195 unsigned long *cprd, u32 *pres)
196{
197 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
198 unsigned long long cycles = state->period;
199 int shift;
200
201 /* Calculate the period cycles and prescale value */
202 cycles *= clkrate;
203 do_div(cycles, NSEC_PER_SEC);
204
205 /*
206 * The register for the period length is cfg.period_bits bits wide.
207 * So for each bit the number of clock cycles is wider divide the input
208 * clock frequency by two using pres and shift cprd accordingly.
209 */
210 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
211
212 if (shift > PWM_MAX_PRES) {
213 dev_err(chip->dev, "pres exceeds the maximum value\n");
214 return -EINVAL;
215 } else if (shift > 0) {
216 *pres = shift;
217 cycles >>= *pres;
218 } else {
219 *pres = 0;
220 }
221
222 *cprd = cycles;
223
224 return 0;
225}
226
227static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
228 unsigned long clkrate, unsigned long cprd,
229 u32 pres, unsigned long *cdty)
230{
231 unsigned long long cycles = state->duty_cycle;
232
233 cycles *= clkrate;
234 do_div(cycles, NSEC_PER_SEC);
235 cycles >>= pres;
236 *cdty = cprd - cycles;
237}
238
239static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
240 unsigned long cdty)
241{
242 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
243 u32 val;
244
245 if (atmel_pwm->data->regs.duty_upd ==
246 atmel_pwm->data->regs.period_upd) {
247 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
248 val &= ~PWM_CMR_UPD_CDTY;
249 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
250 }
251
252 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
253 atmel_pwm->data->regs.duty_upd, cdty);
254 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
255}
256
257static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
258 struct pwm_device *pwm,
259 unsigned long cprd, unsigned long cdty)
260{
261 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
262
263 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
264 atmel_pwm->data->regs.duty, cdty);
265 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
266 atmel_pwm->data->regs.period, cprd);
267}
268
269static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
270 bool disable_clk)
271{
272 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
273 unsigned long timeout;
274
275 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
276
277 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
278
279 /*
280 * Wait for the PWM channel disable operation to be effective before
281 * stopping the clock.
282 */
283 timeout = jiffies + 2 * HZ;
284
285 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
286 time_before(jiffies, timeout))
287 usleep_range(10, 100);
288
289 if (disable_clk)
290 clk_disable(atmel_pwm->clk);
291}
292
293static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
294 const struct pwm_state *state)
295{
296 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
297 struct pwm_state cstate;
298 unsigned long cprd, cdty;
299 u32 pres, val;
300 int ret;
301
302 pwm_get_state(pwm, &cstate);
303
304 if (state->enabled) {
305 unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
306
307 if (cstate.enabled &&
308 cstate.polarity == state->polarity &&
309 cstate.period == state->period) {
310 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
311
312 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
313 atmel_pwm->data->regs.period);
314 pres = cmr & PWM_CMR_CPRE_MSK;
315
316 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
317 atmel_pwm_update_cdty(chip, pwm, cdty);
318 return 0;
319 }
320
321 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
322 &pres);
323 if (ret) {
324 dev_err(chip->dev,
325 "failed to calculate cprd and prescaler\n");
326 return ret;
327 }
328
329 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
330
331 if (cstate.enabled) {
332 atmel_pwm_disable(chip, pwm, false);
333 } else {
334 ret = clk_enable(atmel_pwm->clk);
335 if (ret) {
336 dev_err(chip->dev, "failed to enable clock\n");
337 return ret;
338 }
339 }
340
341 /* It is necessary to preserve CPOL, inside CMR */
342 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
343 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
344 if (state->polarity == PWM_POLARITY_NORMAL)
345 val &= ~PWM_CMR_CPOL;
346 else
347 val |= PWM_CMR_CPOL;
348 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
349 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
350 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
351 } else if (cstate.enabled) {
352 atmel_pwm_disable(chip, pwm, true);
353 }
354
355 return 0;
356}
357
358static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
359 struct pwm_state *state)
360{
361 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
362 u32 sr, cmr;
363
364 sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
365 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
366
367 if (sr & (1 << pwm->hwpwm)) {
368 unsigned long rate = clk_get_rate(atmel_pwm->clk);
369 u32 cdty, cprd, pres;
370 u64 tmp;
371
372 pres = cmr & PWM_CMR_CPRE_MSK;
373
374 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
375 atmel_pwm->data->regs.period);
376 tmp = (u64)cprd * NSEC_PER_SEC;
377 tmp <<= pres;
378 state->period = DIV64_U64_ROUND_UP(tmp, rate);
379
380 /* Wait for an updated duty_cycle queued in hardware */
381 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
382
383 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
384 atmel_pwm->data->regs.duty);
385 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
386 tmp <<= pres;
387 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
388
389 state->enabled = true;
390 } else {
391 state->enabled = false;
392 }
393
394 if (cmr & PWM_CMR_CPOL)
395 state->polarity = PWM_POLARITY_INVERSED;
396 else
397 state->polarity = PWM_POLARITY_NORMAL;
398
399 return 0;
400}
401
402static const struct pwm_ops atmel_pwm_ops = {
403 .apply = atmel_pwm_apply,
404 .get_state = atmel_pwm_get_state,
405};
406
407static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
408 .regs = {
409 .period = PWMV1_CPRD,
410 .period_upd = PWMV1_CUPD,
411 .duty = PWMV1_CDTY,
412 .duty_upd = PWMV1_CUPD,
413 },
414 .cfg = {
415 /* 16 bits to keep period and duty. */
416 .period_bits = 16,
417 },
418};
419
420static const struct atmel_pwm_data atmel_sama5_pwm_data = {
421 .regs = {
422 .period = PWMV2_CPRD,
423 .period_upd = PWMV2_CPRDUPD,
424 .duty = PWMV2_CDTY,
425 .duty_upd = PWMV2_CDTYUPD,
426 },
427 .cfg = {
428 /* 16 bits to keep period and duty. */
429 .period_bits = 16,
430 },
431};
432
433static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
434 .regs = {
435 .period = PWMV1_CPRD,
436 .period_upd = PWMV1_CUPD,
437 .duty = PWMV1_CDTY,
438 .duty_upd = PWMV1_CUPD,
439 },
440 .cfg = {
441 /* 32 bits to keep period and duty. */
442 .period_bits = 32,
443 },
444};
445
446static const struct of_device_id atmel_pwm_dt_ids[] = {
447 {
448 .compatible = "atmel,at91sam9rl-pwm",
449 .data = &atmel_sam9rl_pwm_data,
450 }, {
451 .compatible = "atmel,sama5d3-pwm",
452 .data = &atmel_sama5_pwm_data,
453 }, {
454 .compatible = "atmel,sama5d2-pwm",
455 .data = &atmel_sama5_pwm_data,
456 }, {
457 .compatible = "microchip,sam9x60-pwm",
458 .data = &mchp_sam9x60_pwm_data,
459 }, {
460 /* sentinel */
461 },
462};
463MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
464
465static int atmel_pwm_enable_clk_if_on(struct atmel_pwm_chip *atmel_pwm, bool on)
466{
467 unsigned int i, cnt = 0;
468 unsigned long sr;
469 int ret = 0;
470
471 sr = atmel_pwm_readl(atmel_pwm, PWM_SR) & PWM_SR_ALL_CH_MASK;
472 if (!sr)
473 return 0;
474
475 cnt = bitmap_weight(&sr, atmel_pwm->chip.npwm);
476
477 if (!on)
478 goto disable_clk;
479
480 for (i = 0; i < cnt; i++) {
481 ret = clk_enable(atmel_pwm->clk);
482 if (ret) {
483 dev_err(atmel_pwm->chip.dev,
484 "failed to enable clock for pwm %pe\n",
485 ERR_PTR(ret));
486
487 cnt = i;
488 goto disable_clk;
489 }
490 }
491
492 return 0;
493
494disable_clk:
495 while (cnt--)
496 clk_disable(atmel_pwm->clk);
497
498 return ret;
499}
500
501static int atmel_pwm_probe(struct platform_device *pdev)
502{
503 struct atmel_pwm_chip *atmel_pwm;
504 int ret;
505
506 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
507 if (!atmel_pwm)
508 return -ENOMEM;
509
510 atmel_pwm->data = of_device_get_match_data(&pdev->dev);
511
512 atmel_pwm->update_pending = 0;
513 spin_lock_init(&atmel_pwm->lock);
514
515 atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
516 if (IS_ERR(atmel_pwm->base))
517 return PTR_ERR(atmel_pwm->base);
518
519 atmel_pwm->clk = devm_clk_get_prepared(&pdev->dev, NULL);
520 if (IS_ERR(atmel_pwm->clk))
521 return dev_err_probe(&pdev->dev, PTR_ERR(atmel_pwm->clk),
522 "failed to get prepared PWM clock\n");
523
524 atmel_pwm->chip.dev = &pdev->dev;
525 atmel_pwm->chip.ops = &atmel_pwm_ops;
526 atmel_pwm->chip.npwm = 4;
527
528 ret = atmel_pwm_enable_clk_if_on(atmel_pwm, true);
529 if (ret < 0)
530 return ret;
531
532 ret = devm_pwmchip_add(&pdev->dev, &atmel_pwm->chip);
533 if (ret < 0) {
534 dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
535 goto disable_clk;
536 }
537
538 return 0;
539
540disable_clk:
541 atmel_pwm_enable_clk_if_on(atmel_pwm, false);
542
543 return ret;
544}
545
546static struct platform_driver atmel_pwm_driver = {
547 .driver = {
548 .name = "atmel-pwm",
549 .of_match_table = atmel_pwm_dt_ids,
550 },
551 .probe = atmel_pwm_probe,
552};
553module_platform_driver(atmel_pwm_driver);
554
555MODULE_ALIAS("platform:atmel-pwm");
556MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
557MODULE_DESCRIPTION("Atmel PWM driver");
558MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Atmel Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2013 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
7 *
8 * Links to reference manuals for the supported PWM chips can be found in
9 * Documentation/arch/arm/microchip.rst.
10 *
11 * Limitations:
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
14 *
15 * Software bugs/possible improvements:
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
19 * functionality could be used.
20 */
21
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/pwm.h>
30#include <linux/slab.h>
31
32/* The following is global registers for PWM controller */
33#define PWM_ENA 0x04
34#define PWM_DIS 0x08
35#define PWM_SR 0x0C
36#define PWM_ISR 0x1C
37/* Bit field in SR */
38#define PWM_SR_ALL_CH_MASK 0x0F
39
40/* The following register is PWM channel related registers */
41#define PWM_CH_REG_OFFSET 0x200
42#define PWM_CH_REG_SIZE 0x20
43
44#define PWM_CMR 0x0
45/* Bit field in CMR */
46#define PWM_CMR_CPOL (1 << 9)
47#define PWM_CMR_UPD_CDTY (1 << 10)
48#define PWM_CMR_CPRE_MSK 0xF
49
50/* The following registers for PWM v1 */
51#define PWMV1_CDTY 0x04
52#define PWMV1_CPRD 0x08
53#define PWMV1_CUPD 0x10
54
55/* The following registers for PWM v2 */
56#define PWMV2_CDTY 0x04
57#define PWMV2_CDTYUPD 0x08
58#define PWMV2_CPRD 0x0C
59#define PWMV2_CPRDUPD 0x10
60
61#define PWM_MAX_PRES 10
62
63struct atmel_pwm_registers {
64 u8 period;
65 u8 period_upd;
66 u8 duty;
67 u8 duty_upd;
68};
69
70struct atmel_pwm_config {
71 u32 period_bits;
72};
73
74struct atmel_pwm_data {
75 struct atmel_pwm_registers regs;
76 struct atmel_pwm_config cfg;
77};
78
79struct atmel_pwm_chip {
80 struct clk *clk;
81 void __iomem *base;
82 const struct atmel_pwm_data *data;
83
84 /*
85 * The hardware supports a mechanism to update a channel's duty cycle at
86 * the end of the currently running period. When such an update is
87 * pending we delay disabling the PWM until the new configuration is
88 * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
89 * might not result in an inactive output.
90 * This bitmask tracks for which channels an update is pending in
91 * hardware.
92 */
93 u32 update_pending;
94
95 /* Protects .update_pending */
96 spinlock_t lock;
97};
98
99static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
100{
101 return pwmchip_get_drvdata(chip);
102}
103
104static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
105 unsigned long offset)
106{
107 return readl_relaxed(chip->base + offset);
108}
109
110static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
111 unsigned long offset, unsigned long val)
112{
113 writel_relaxed(val, chip->base + offset);
114}
115
116static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
117 unsigned int ch, unsigned long offset)
118{
119 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
120
121 return atmel_pwm_readl(chip, base + offset);
122}
123
124static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
125 unsigned int ch, unsigned long offset,
126 unsigned long val)
127{
128 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
129
130 atmel_pwm_writel(chip, base + offset, val);
131}
132
133static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
134{
135 /*
136 * Each channel that has its bit in ISR set started a new period since
137 * ISR was cleared and so there is no more update pending. Note that
138 * reading ISR clears it, so this needs to handle all channels to not
139 * loose information.
140 */
141 u32 isr = atmel_pwm_readl(chip, PWM_ISR);
142
143 chip->update_pending &= ~isr;
144}
145
146static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
147{
148 spin_lock(&chip->lock);
149
150 /*
151 * Clear pending flags in hardware because otherwise there might still
152 * be a stale flag in ISR.
153 */
154 atmel_pwm_update_pending(chip);
155
156 chip->update_pending |= (1 << ch);
157
158 spin_unlock(&chip->lock);
159}
160
161static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
162{
163 int ret = 0;
164
165 spin_lock(&chip->lock);
166
167 if (chip->update_pending & (1 << ch)) {
168 atmel_pwm_update_pending(chip);
169
170 if (chip->update_pending & (1 << ch))
171 ret = 1;
172 }
173
174 spin_unlock(&chip->lock);
175
176 return ret;
177}
178
179static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
180{
181 unsigned long timeout = jiffies + 2 * HZ;
182 int ret;
183
184 while ((ret = atmel_pwm_test_pending(chip, ch)) &&
185 time_before(jiffies, timeout))
186 usleep_range(10, 100);
187
188 return ret ? -ETIMEDOUT : 0;
189}
190
191static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
192 unsigned long clkrate,
193 const struct pwm_state *state,
194 unsigned long *cprd, u32 *pres)
195{
196 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
197 unsigned long long cycles = state->period;
198 int shift;
199
200 /* Calculate the period cycles and prescale value */
201 cycles *= clkrate;
202 do_div(cycles, NSEC_PER_SEC);
203
204 /*
205 * The register for the period length is cfg.period_bits bits wide.
206 * So for each bit the number of clock cycles is wider divide the input
207 * clock frequency by two using pres and shift cprd accordingly.
208 */
209 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
210
211 if (shift > PWM_MAX_PRES) {
212 dev_err(pwmchip_parent(chip), "pres exceeds the maximum value\n");
213 return -EINVAL;
214 } else if (shift > 0) {
215 *pres = shift;
216 cycles >>= *pres;
217 } else {
218 *pres = 0;
219 }
220
221 *cprd = cycles;
222
223 return 0;
224}
225
226static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
227 unsigned long clkrate, unsigned long cprd,
228 u32 pres, unsigned long *cdty)
229{
230 unsigned long long cycles = state->duty_cycle;
231
232 cycles *= clkrate;
233 do_div(cycles, NSEC_PER_SEC);
234 cycles >>= pres;
235 *cdty = cprd - cycles;
236}
237
238static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
239 unsigned long cdty)
240{
241 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
242 u32 val;
243
244 if (atmel_pwm->data->regs.duty_upd ==
245 atmel_pwm->data->regs.period_upd) {
246 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
247 val &= ~PWM_CMR_UPD_CDTY;
248 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
249 }
250
251 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
252 atmel_pwm->data->regs.duty_upd, cdty);
253 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
254}
255
256static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
257 struct pwm_device *pwm,
258 unsigned long cprd, unsigned long cdty)
259{
260 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
261
262 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
263 atmel_pwm->data->regs.duty, cdty);
264 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
265 atmel_pwm->data->regs.period, cprd);
266}
267
268static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
269 bool disable_clk)
270{
271 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
272 unsigned long timeout;
273
274 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
275
276 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
277
278 /*
279 * Wait for the PWM channel disable operation to be effective before
280 * stopping the clock.
281 */
282 timeout = jiffies + 2 * HZ;
283
284 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
285 time_before(jiffies, timeout))
286 usleep_range(10, 100);
287
288 if (disable_clk)
289 clk_disable(atmel_pwm->clk);
290}
291
292static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
293 const struct pwm_state *state)
294{
295 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
296 unsigned long cprd, cdty;
297 u32 pres, val;
298 int ret;
299
300 if (state->enabled) {
301 unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
302
303 if (pwm->state.enabled &&
304 pwm->state.polarity == state->polarity &&
305 pwm->state.period == state->period) {
306 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
307
308 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
309 atmel_pwm->data->regs.period);
310 pres = cmr & PWM_CMR_CPRE_MSK;
311
312 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
313 atmel_pwm_update_cdty(chip, pwm, cdty);
314 return 0;
315 }
316
317 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
318 &pres);
319 if (ret) {
320 dev_err(pwmchip_parent(chip),
321 "failed to calculate cprd and prescaler\n");
322 return ret;
323 }
324
325 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
326
327 if (pwm->state.enabled) {
328 atmel_pwm_disable(chip, pwm, false);
329 } else {
330 ret = clk_enable(atmel_pwm->clk);
331 if (ret) {
332 dev_err(pwmchip_parent(chip), "failed to enable clock\n");
333 return ret;
334 }
335 }
336
337 /* It is necessary to preserve CPOL, inside CMR */
338 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
339 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
340 if (state->polarity == PWM_POLARITY_NORMAL)
341 val &= ~PWM_CMR_CPOL;
342 else
343 val |= PWM_CMR_CPOL;
344 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
345 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
346 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
347 } else if (pwm->state.enabled) {
348 atmel_pwm_disable(chip, pwm, true);
349 }
350
351 return 0;
352}
353
354static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
355 struct pwm_state *state)
356{
357 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
358 u32 sr, cmr;
359
360 sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
361 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
362
363 if (sr & (1 << pwm->hwpwm)) {
364 unsigned long rate = clk_get_rate(atmel_pwm->clk);
365 u32 cdty, cprd, pres;
366 u64 tmp;
367
368 pres = cmr & PWM_CMR_CPRE_MSK;
369
370 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
371 atmel_pwm->data->regs.period);
372 tmp = (u64)cprd * NSEC_PER_SEC;
373 tmp <<= pres;
374 state->period = DIV64_U64_ROUND_UP(tmp, rate);
375
376 /* Wait for an updated duty_cycle queued in hardware */
377 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
378
379 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
380 atmel_pwm->data->regs.duty);
381 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
382 tmp <<= pres;
383 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
384
385 state->enabled = true;
386 } else {
387 state->enabled = false;
388 }
389
390 if (cmr & PWM_CMR_CPOL)
391 state->polarity = PWM_POLARITY_INVERSED;
392 else
393 state->polarity = PWM_POLARITY_NORMAL;
394
395 return 0;
396}
397
398static const struct pwm_ops atmel_pwm_ops = {
399 .apply = atmel_pwm_apply,
400 .get_state = atmel_pwm_get_state,
401};
402
403static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
404 .regs = {
405 .period = PWMV1_CPRD,
406 .period_upd = PWMV1_CUPD,
407 .duty = PWMV1_CDTY,
408 .duty_upd = PWMV1_CUPD,
409 },
410 .cfg = {
411 /* 16 bits to keep period and duty. */
412 .period_bits = 16,
413 },
414};
415
416static const struct atmel_pwm_data atmel_sama5_pwm_data = {
417 .regs = {
418 .period = PWMV2_CPRD,
419 .period_upd = PWMV2_CPRDUPD,
420 .duty = PWMV2_CDTY,
421 .duty_upd = PWMV2_CDTYUPD,
422 },
423 .cfg = {
424 /* 16 bits to keep period and duty. */
425 .period_bits = 16,
426 },
427};
428
429static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
430 .regs = {
431 .period = PWMV1_CPRD,
432 .period_upd = PWMV1_CUPD,
433 .duty = PWMV1_CDTY,
434 .duty_upd = PWMV1_CUPD,
435 },
436 .cfg = {
437 /* 32 bits to keep period and duty. */
438 .period_bits = 32,
439 },
440};
441
442static const struct of_device_id atmel_pwm_dt_ids[] = {
443 {
444 .compatible = "atmel,at91sam9rl-pwm",
445 .data = &atmel_sam9rl_pwm_data,
446 }, {
447 .compatible = "atmel,sama5d3-pwm",
448 .data = &atmel_sama5_pwm_data,
449 }, {
450 .compatible = "atmel,sama5d2-pwm",
451 .data = &atmel_sama5_pwm_data,
452 }, {
453 .compatible = "microchip,sam9x60-pwm",
454 .data = &mchp_sam9x60_pwm_data,
455 }, {
456 /* sentinel */
457 },
458};
459MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
460
461static int atmel_pwm_enable_clk_if_on(struct pwm_chip *chip, bool on)
462{
463 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
464 unsigned int i, cnt = 0;
465 unsigned long sr;
466 int ret = 0;
467
468 sr = atmel_pwm_readl(atmel_pwm, PWM_SR) & PWM_SR_ALL_CH_MASK;
469 if (!sr)
470 return 0;
471
472 cnt = bitmap_weight(&sr, chip->npwm);
473
474 if (!on)
475 goto disable_clk;
476
477 for (i = 0; i < cnt; i++) {
478 ret = clk_enable(atmel_pwm->clk);
479 if (ret) {
480 dev_err(pwmchip_parent(chip),
481 "failed to enable clock for pwm %pe\n",
482 ERR_PTR(ret));
483
484 cnt = i;
485 goto disable_clk;
486 }
487 }
488
489 return 0;
490
491disable_clk:
492 while (cnt--)
493 clk_disable(atmel_pwm->clk);
494
495 return ret;
496}
497
498static int atmel_pwm_probe(struct platform_device *pdev)
499{
500 struct atmel_pwm_chip *atmel_pwm;
501 struct pwm_chip *chip;
502 int ret;
503
504 chip = devm_pwmchip_alloc(&pdev->dev, 4, sizeof(*atmel_pwm));
505 if (IS_ERR(chip))
506 return PTR_ERR(chip);
507
508 atmel_pwm = to_atmel_pwm_chip(chip);
509 atmel_pwm->data = of_device_get_match_data(&pdev->dev);
510
511 atmel_pwm->update_pending = 0;
512 spin_lock_init(&atmel_pwm->lock);
513
514 atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
515 if (IS_ERR(atmel_pwm->base))
516 return PTR_ERR(atmel_pwm->base);
517
518 atmel_pwm->clk = devm_clk_get_prepared(&pdev->dev, NULL);
519 if (IS_ERR(atmel_pwm->clk))
520 return dev_err_probe(&pdev->dev, PTR_ERR(atmel_pwm->clk),
521 "failed to get prepared PWM clock\n");
522
523 chip->ops = &atmel_pwm_ops;
524
525 ret = atmel_pwm_enable_clk_if_on(chip, true);
526 if (ret < 0)
527 return ret;
528
529 ret = devm_pwmchip_add(&pdev->dev, chip);
530 if (ret < 0) {
531 dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
532 goto disable_clk;
533 }
534
535 return 0;
536
537disable_clk:
538 atmel_pwm_enable_clk_if_on(chip, false);
539
540 return ret;
541}
542
543static struct platform_driver atmel_pwm_driver = {
544 .driver = {
545 .name = "atmel-pwm",
546 .of_match_table = atmel_pwm_dt_ids,
547 },
548 .probe = atmel_pwm_probe,
549};
550module_platform_driver(atmel_pwm_driver);
551
552MODULE_ALIAS("platform:atmel-pwm");
553MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
554MODULE_DESCRIPTION("Atmel PWM driver");
555MODULE_LICENSE("GPL v2");