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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Atmel Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2013 Atmel Corporation
6 * Bo Shen <voice.shen@atmel.com>
7 *
8 * Links to reference manuals for the supported PWM chips can be found in
9 * Documentation/arch/arm/microchip.rst.
10 *
11 * Limitations:
12 * - Periods start with the inactive level.
13 * - Hardware has to be stopped in general to update settings.
14 *
15 * Software bugs/possible improvements:
16 * - When atmel_pwm_apply() is called with state->enabled=false a change in
17 * state->polarity isn't honored.
18 * - Instead of sleeping to wait for a completed period, the interrupt
19 * functionality could be used.
20 */
21
22#include <linux/clk.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/io.h>
26#include <linux/module.h>
27#include <linux/of.h>
28#include <linux/platform_device.h>
29#include <linux/pwm.h>
30#include <linux/slab.h>
31
32/* The following is global registers for PWM controller */
33#define PWM_ENA 0x04
34#define PWM_DIS 0x08
35#define PWM_SR 0x0C
36#define PWM_ISR 0x1C
37/* Bit field in SR */
38#define PWM_SR_ALL_CH_MASK 0x0F
39
40/* The following register is PWM channel related registers */
41#define PWM_CH_REG_OFFSET 0x200
42#define PWM_CH_REG_SIZE 0x20
43
44#define PWM_CMR 0x0
45/* Bit field in CMR */
46#define PWM_CMR_CPOL (1 << 9)
47#define PWM_CMR_UPD_CDTY (1 << 10)
48#define PWM_CMR_CPRE_MSK 0xF
49
50/* The following registers for PWM v1 */
51#define PWMV1_CDTY 0x04
52#define PWMV1_CPRD 0x08
53#define PWMV1_CUPD 0x10
54
55/* The following registers for PWM v2 */
56#define PWMV2_CDTY 0x04
57#define PWMV2_CDTYUPD 0x08
58#define PWMV2_CPRD 0x0C
59#define PWMV2_CPRDUPD 0x10
60
61#define PWM_MAX_PRES 10
62
63struct atmel_pwm_registers {
64 u8 period;
65 u8 period_upd;
66 u8 duty;
67 u8 duty_upd;
68};
69
70struct atmel_pwm_config {
71 u32 period_bits;
72};
73
74struct atmel_pwm_data {
75 struct atmel_pwm_registers regs;
76 struct atmel_pwm_config cfg;
77};
78
79struct atmel_pwm_chip {
80 struct pwm_chip chip;
81 struct clk *clk;
82 void __iomem *base;
83 const struct atmel_pwm_data *data;
84
85 /*
86 * The hardware supports a mechanism to update a channel's duty cycle at
87 * the end of the currently running period. When such an update is
88 * pending we delay disabling the PWM until the new configuration is
89 * active because otherwise pmw_config(duty_cycle=0); pwm_disable();
90 * might not result in an inactive output.
91 * This bitmask tracks for which channels an update is pending in
92 * hardware.
93 */
94 u32 update_pending;
95
96 /* Protects .update_pending */
97 spinlock_t lock;
98};
99
100static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
101{
102 return container_of(chip, struct atmel_pwm_chip, chip);
103}
104
105static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
106 unsigned long offset)
107{
108 return readl_relaxed(chip->base + offset);
109}
110
111static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
112 unsigned long offset, unsigned long val)
113{
114 writel_relaxed(val, chip->base + offset);
115}
116
117static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
118 unsigned int ch, unsigned long offset)
119{
120 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
121
122 return atmel_pwm_readl(chip, base + offset);
123}
124
125static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
126 unsigned int ch, unsigned long offset,
127 unsigned long val)
128{
129 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
130
131 atmel_pwm_writel(chip, base + offset, val);
132}
133
134static void atmel_pwm_update_pending(struct atmel_pwm_chip *chip)
135{
136 /*
137 * Each channel that has its bit in ISR set started a new period since
138 * ISR was cleared and so there is no more update pending. Note that
139 * reading ISR clears it, so this needs to handle all channels to not
140 * loose information.
141 */
142 u32 isr = atmel_pwm_readl(chip, PWM_ISR);
143
144 chip->update_pending &= ~isr;
145}
146
147static void atmel_pwm_set_pending(struct atmel_pwm_chip *chip, unsigned int ch)
148{
149 spin_lock(&chip->lock);
150
151 /*
152 * Clear pending flags in hardware because otherwise there might still
153 * be a stale flag in ISR.
154 */
155 atmel_pwm_update_pending(chip);
156
157 chip->update_pending |= (1 << ch);
158
159 spin_unlock(&chip->lock);
160}
161
162static int atmel_pwm_test_pending(struct atmel_pwm_chip *chip, unsigned int ch)
163{
164 int ret = 0;
165
166 spin_lock(&chip->lock);
167
168 if (chip->update_pending & (1 << ch)) {
169 atmel_pwm_update_pending(chip);
170
171 if (chip->update_pending & (1 << ch))
172 ret = 1;
173 }
174
175 spin_unlock(&chip->lock);
176
177 return ret;
178}
179
180static int atmel_pwm_wait_nonpending(struct atmel_pwm_chip *chip, unsigned int ch)
181{
182 unsigned long timeout = jiffies + 2 * HZ;
183 int ret;
184
185 while ((ret = atmel_pwm_test_pending(chip, ch)) &&
186 time_before(jiffies, timeout))
187 usleep_range(10, 100);
188
189 return ret ? -ETIMEDOUT : 0;
190}
191
192static int atmel_pwm_calculate_cprd_and_pres(struct pwm_chip *chip,
193 unsigned long clkrate,
194 const struct pwm_state *state,
195 unsigned long *cprd, u32 *pres)
196{
197 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
198 unsigned long long cycles = state->period;
199 int shift;
200
201 /* Calculate the period cycles and prescale value */
202 cycles *= clkrate;
203 do_div(cycles, NSEC_PER_SEC);
204
205 /*
206 * The register for the period length is cfg.period_bits bits wide.
207 * So for each bit the number of clock cycles is wider divide the input
208 * clock frequency by two using pres and shift cprd accordingly.
209 */
210 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits;
211
212 if (shift > PWM_MAX_PRES) {
213 dev_err(chip->dev, "pres exceeds the maximum value\n");
214 return -EINVAL;
215 } else if (shift > 0) {
216 *pres = shift;
217 cycles >>= *pres;
218 } else {
219 *pres = 0;
220 }
221
222 *cprd = cycles;
223
224 return 0;
225}
226
227static void atmel_pwm_calculate_cdty(const struct pwm_state *state,
228 unsigned long clkrate, unsigned long cprd,
229 u32 pres, unsigned long *cdty)
230{
231 unsigned long long cycles = state->duty_cycle;
232
233 cycles *= clkrate;
234 do_div(cycles, NSEC_PER_SEC);
235 cycles >>= pres;
236 *cdty = cprd - cycles;
237}
238
239static void atmel_pwm_update_cdty(struct pwm_chip *chip, struct pwm_device *pwm,
240 unsigned long cdty)
241{
242 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
243 u32 val;
244
245 if (atmel_pwm->data->regs.duty_upd ==
246 atmel_pwm->data->regs.period_upd) {
247 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
248 val &= ~PWM_CMR_UPD_CDTY;
249 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
250 }
251
252 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
253 atmel_pwm->data->regs.duty_upd, cdty);
254 atmel_pwm_set_pending(atmel_pwm, pwm->hwpwm);
255}
256
257static void atmel_pwm_set_cprd_cdty(struct pwm_chip *chip,
258 struct pwm_device *pwm,
259 unsigned long cprd, unsigned long cdty)
260{
261 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
262
263 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
264 atmel_pwm->data->regs.duty, cdty);
265 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm,
266 atmel_pwm->data->regs.period, cprd);
267}
268
269static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm,
270 bool disable_clk)
271{
272 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
273 unsigned long timeout;
274
275 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
276
277 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
278
279 /*
280 * Wait for the PWM channel disable operation to be effective before
281 * stopping the clock.
282 */
283 timeout = jiffies + 2 * HZ;
284
285 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
286 time_before(jiffies, timeout))
287 usleep_range(10, 100);
288
289 if (disable_clk)
290 clk_disable(atmel_pwm->clk);
291}
292
293static int atmel_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
294 const struct pwm_state *state)
295{
296 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
297 struct pwm_state cstate;
298 unsigned long cprd, cdty;
299 u32 pres, val;
300 int ret;
301
302 pwm_get_state(pwm, &cstate);
303
304 if (state->enabled) {
305 unsigned long clkrate = clk_get_rate(atmel_pwm->clk);
306
307 if (cstate.enabled &&
308 cstate.polarity == state->polarity &&
309 cstate.period == state->period) {
310 u32 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
311
312 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
313 atmel_pwm->data->regs.period);
314 pres = cmr & PWM_CMR_CPRE_MSK;
315
316 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
317 atmel_pwm_update_cdty(chip, pwm, cdty);
318 return 0;
319 }
320
321 ret = atmel_pwm_calculate_cprd_and_pres(chip, clkrate, state, &cprd,
322 &pres);
323 if (ret) {
324 dev_err(chip->dev,
325 "failed to calculate cprd and prescaler\n");
326 return ret;
327 }
328
329 atmel_pwm_calculate_cdty(state, clkrate, cprd, pres, &cdty);
330
331 if (cstate.enabled) {
332 atmel_pwm_disable(chip, pwm, false);
333 } else {
334 ret = clk_enable(atmel_pwm->clk);
335 if (ret) {
336 dev_err(chip->dev, "failed to enable clock\n");
337 return ret;
338 }
339 }
340
341 /* It is necessary to preserve CPOL, inside CMR */
342 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
343 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
344 if (state->polarity == PWM_POLARITY_NORMAL)
345 val &= ~PWM_CMR_CPOL;
346 else
347 val |= PWM_CMR_CPOL;
348 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
349 atmel_pwm_set_cprd_cdty(chip, pwm, cprd, cdty);
350 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
351 } else if (cstate.enabled) {
352 atmel_pwm_disable(chip, pwm, true);
353 }
354
355 return 0;
356}
357
358static int atmel_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
359 struct pwm_state *state)
360{
361 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
362 u32 sr, cmr;
363
364 sr = atmel_pwm_readl(atmel_pwm, PWM_SR);
365 cmr = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
366
367 if (sr & (1 << pwm->hwpwm)) {
368 unsigned long rate = clk_get_rate(atmel_pwm->clk);
369 u32 cdty, cprd, pres;
370 u64 tmp;
371
372 pres = cmr & PWM_CMR_CPRE_MSK;
373
374 cprd = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
375 atmel_pwm->data->regs.period);
376 tmp = (u64)cprd * NSEC_PER_SEC;
377 tmp <<= pres;
378 state->period = DIV64_U64_ROUND_UP(tmp, rate);
379
380 /* Wait for an updated duty_cycle queued in hardware */
381 atmel_pwm_wait_nonpending(atmel_pwm, pwm->hwpwm);
382
383 cdty = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm,
384 atmel_pwm->data->regs.duty);
385 tmp = (u64)(cprd - cdty) * NSEC_PER_SEC;
386 tmp <<= pres;
387 state->duty_cycle = DIV64_U64_ROUND_UP(tmp, rate);
388
389 state->enabled = true;
390 } else {
391 state->enabled = false;
392 }
393
394 if (cmr & PWM_CMR_CPOL)
395 state->polarity = PWM_POLARITY_INVERSED;
396 else
397 state->polarity = PWM_POLARITY_NORMAL;
398
399 return 0;
400}
401
402static const struct pwm_ops atmel_pwm_ops = {
403 .apply = atmel_pwm_apply,
404 .get_state = atmel_pwm_get_state,
405};
406
407static const struct atmel_pwm_data atmel_sam9rl_pwm_data = {
408 .regs = {
409 .period = PWMV1_CPRD,
410 .period_upd = PWMV1_CUPD,
411 .duty = PWMV1_CDTY,
412 .duty_upd = PWMV1_CUPD,
413 },
414 .cfg = {
415 /* 16 bits to keep period and duty. */
416 .period_bits = 16,
417 },
418};
419
420static const struct atmel_pwm_data atmel_sama5_pwm_data = {
421 .regs = {
422 .period = PWMV2_CPRD,
423 .period_upd = PWMV2_CPRDUPD,
424 .duty = PWMV2_CDTY,
425 .duty_upd = PWMV2_CDTYUPD,
426 },
427 .cfg = {
428 /* 16 bits to keep period and duty. */
429 .period_bits = 16,
430 },
431};
432
433static const struct atmel_pwm_data mchp_sam9x60_pwm_data = {
434 .regs = {
435 .period = PWMV1_CPRD,
436 .period_upd = PWMV1_CUPD,
437 .duty = PWMV1_CDTY,
438 .duty_upd = PWMV1_CUPD,
439 },
440 .cfg = {
441 /* 32 bits to keep period and duty. */
442 .period_bits = 32,
443 },
444};
445
446static const struct of_device_id atmel_pwm_dt_ids[] = {
447 {
448 .compatible = "atmel,at91sam9rl-pwm",
449 .data = &atmel_sam9rl_pwm_data,
450 }, {
451 .compatible = "atmel,sama5d3-pwm",
452 .data = &atmel_sama5_pwm_data,
453 }, {
454 .compatible = "atmel,sama5d2-pwm",
455 .data = &atmel_sama5_pwm_data,
456 }, {
457 .compatible = "microchip,sam9x60-pwm",
458 .data = &mchp_sam9x60_pwm_data,
459 }, {
460 /* sentinel */
461 },
462};
463MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
464
465static int atmel_pwm_enable_clk_if_on(struct atmel_pwm_chip *atmel_pwm, bool on)
466{
467 unsigned int i, cnt = 0;
468 unsigned long sr;
469 int ret = 0;
470
471 sr = atmel_pwm_readl(atmel_pwm, PWM_SR) & PWM_SR_ALL_CH_MASK;
472 if (!sr)
473 return 0;
474
475 cnt = bitmap_weight(&sr, atmel_pwm->chip.npwm);
476
477 if (!on)
478 goto disable_clk;
479
480 for (i = 0; i < cnt; i++) {
481 ret = clk_enable(atmel_pwm->clk);
482 if (ret) {
483 dev_err(atmel_pwm->chip.dev,
484 "failed to enable clock for pwm %pe\n",
485 ERR_PTR(ret));
486
487 cnt = i;
488 goto disable_clk;
489 }
490 }
491
492 return 0;
493
494disable_clk:
495 while (cnt--)
496 clk_disable(atmel_pwm->clk);
497
498 return ret;
499}
500
501static int atmel_pwm_probe(struct platform_device *pdev)
502{
503 struct atmel_pwm_chip *atmel_pwm;
504 int ret;
505
506 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
507 if (!atmel_pwm)
508 return -ENOMEM;
509
510 atmel_pwm->data = of_device_get_match_data(&pdev->dev);
511
512 atmel_pwm->update_pending = 0;
513 spin_lock_init(&atmel_pwm->lock);
514
515 atmel_pwm->base = devm_platform_ioremap_resource(pdev, 0);
516 if (IS_ERR(atmel_pwm->base))
517 return PTR_ERR(atmel_pwm->base);
518
519 atmel_pwm->clk = devm_clk_get_prepared(&pdev->dev, NULL);
520 if (IS_ERR(atmel_pwm->clk))
521 return dev_err_probe(&pdev->dev, PTR_ERR(atmel_pwm->clk),
522 "failed to get prepared PWM clock\n");
523
524 atmel_pwm->chip.dev = &pdev->dev;
525 atmel_pwm->chip.ops = &atmel_pwm_ops;
526 atmel_pwm->chip.npwm = 4;
527
528 ret = atmel_pwm_enable_clk_if_on(atmel_pwm, true);
529 if (ret < 0)
530 return ret;
531
532 ret = devm_pwmchip_add(&pdev->dev, &atmel_pwm->chip);
533 if (ret < 0) {
534 dev_err_probe(&pdev->dev, ret, "failed to add PWM chip\n");
535 goto disable_clk;
536 }
537
538 return 0;
539
540disable_clk:
541 atmel_pwm_enable_clk_if_on(atmel_pwm, false);
542
543 return ret;
544}
545
546static struct platform_driver atmel_pwm_driver = {
547 .driver = {
548 .name = "atmel-pwm",
549 .of_match_table = atmel_pwm_dt_ids,
550 },
551 .probe = atmel_pwm_probe,
552};
553module_platform_driver(atmel_pwm_driver);
554
555MODULE_ALIAS("platform:atmel-pwm");
556MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
557MODULE_DESCRIPTION("Atmel PWM driver");
558MODULE_LICENSE("GPL v2");
1/*
2 * Driver for Atmel Pulse Width Modulation Controller
3 *
4 * Copyright (C) 2013 Atmel Corporation
5 * Bo Shen <voice.shen@atmel.com>
6 *
7 * Licensed under GPLv2.
8 */
9
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/mutex.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21
22/* The following is global registers for PWM controller */
23#define PWM_ENA 0x04
24#define PWM_DIS 0x08
25#define PWM_SR 0x0C
26#define PWM_ISR 0x1C
27/* Bit field in SR */
28#define PWM_SR_ALL_CH_ON 0x0F
29
30/* The following register is PWM channel related registers */
31#define PWM_CH_REG_OFFSET 0x200
32#define PWM_CH_REG_SIZE 0x20
33
34#define PWM_CMR 0x0
35/* Bit field in CMR */
36#define PWM_CMR_CPOL (1 << 9)
37#define PWM_CMR_UPD_CDTY (1 << 10)
38#define PWM_CMR_CPRE_MSK 0xF
39
40/* The following registers for PWM v1 */
41#define PWMV1_CDTY 0x04
42#define PWMV1_CPRD 0x08
43#define PWMV1_CUPD 0x10
44
45/* The following registers for PWM v2 */
46#define PWMV2_CDTY 0x04
47#define PWMV2_CDTYUPD 0x08
48#define PWMV2_CPRD 0x0C
49#define PWMV2_CPRDUPD 0x10
50
51/*
52 * Max value for duty and period
53 *
54 * Although the duty and period register is 32 bit,
55 * however only the LSB 16 bits are significant.
56 */
57#define PWM_MAX_DTY 0xFFFF
58#define PWM_MAX_PRD 0xFFFF
59#define PRD_MAX_PRES 10
60
61struct atmel_pwm_chip {
62 struct pwm_chip chip;
63 struct clk *clk;
64 void __iomem *base;
65
66 unsigned int updated_pwms;
67 /* ISR is cleared when read, ensure only one thread does that */
68 struct mutex isr_lock;
69
70 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
71 unsigned long dty, unsigned long prd);
72};
73
74static inline struct atmel_pwm_chip *to_atmel_pwm_chip(struct pwm_chip *chip)
75{
76 return container_of(chip, struct atmel_pwm_chip, chip);
77}
78
79static inline u32 atmel_pwm_readl(struct atmel_pwm_chip *chip,
80 unsigned long offset)
81{
82 return readl_relaxed(chip->base + offset);
83}
84
85static inline void atmel_pwm_writel(struct atmel_pwm_chip *chip,
86 unsigned long offset, unsigned long val)
87{
88 writel_relaxed(val, chip->base + offset);
89}
90
91static inline u32 atmel_pwm_ch_readl(struct atmel_pwm_chip *chip,
92 unsigned int ch, unsigned long offset)
93{
94 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
95
96 return readl_relaxed(chip->base + base + offset);
97}
98
99static inline void atmel_pwm_ch_writel(struct atmel_pwm_chip *chip,
100 unsigned int ch, unsigned long offset,
101 unsigned long val)
102{
103 unsigned long base = PWM_CH_REG_OFFSET + ch * PWM_CH_REG_SIZE;
104
105 writel_relaxed(val, chip->base + base + offset);
106}
107
108static int atmel_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
109 int duty_ns, int period_ns)
110{
111 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
112 unsigned long prd, dty;
113 unsigned long long div;
114 unsigned int pres = 0;
115 u32 val;
116 int ret;
117
118 if (pwm_is_enabled(pwm) && (period_ns != pwm_get_period(pwm))) {
119 dev_err(chip->dev, "cannot change PWM period while enabled\n");
120 return -EBUSY;
121 }
122
123 /* Calculate the period cycles and prescale value */
124 div = (unsigned long long)clk_get_rate(atmel_pwm->clk) * period_ns;
125 do_div(div, NSEC_PER_SEC);
126
127 while (div > PWM_MAX_PRD) {
128 div >>= 1;
129 pres++;
130 }
131
132 if (pres > PRD_MAX_PRES) {
133 dev_err(chip->dev, "pres exceeds the maximum value\n");
134 return -EINVAL;
135 }
136
137 /* Calculate the duty cycles */
138 prd = div;
139 div *= duty_ns;
140 do_div(div, period_ns);
141 dty = prd - div;
142
143 ret = clk_enable(atmel_pwm->clk);
144 if (ret) {
145 dev_err(chip->dev, "failed to enable PWM clock\n");
146 return ret;
147 }
148
149 /* It is necessary to preserve CPOL, inside CMR */
150 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
151 val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK);
152 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
153 atmel_pwm->config(chip, pwm, dty, prd);
154 mutex_lock(&atmel_pwm->isr_lock);
155 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
156 atmel_pwm->updated_pwms &= ~(1 << pwm->hwpwm);
157 mutex_unlock(&atmel_pwm->isr_lock);
158
159 clk_disable(atmel_pwm->clk);
160 return ret;
161}
162
163static void atmel_pwm_config_v1(struct pwm_chip *chip, struct pwm_device *pwm,
164 unsigned long dty, unsigned long prd)
165{
166 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
167 unsigned int val;
168
169
170 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CUPD, dty);
171
172 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
173 val &= ~PWM_CMR_UPD_CDTY;
174 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
175
176 /*
177 * If the PWM channel is enabled, only update CDTY by using the update
178 * register, it needs to set bit 10 of CMR to 0
179 */
180 if (pwm_is_enabled(pwm))
181 return;
182 /*
183 * If the PWM channel is disabled, write value to duty and period
184 * registers directly.
185 */
186 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CDTY, dty);
187 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV1_CPRD, prd);
188}
189
190static void atmel_pwm_config_v2(struct pwm_chip *chip, struct pwm_device *pwm,
191 unsigned long dty, unsigned long prd)
192{
193 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
194
195 if (pwm_is_enabled(pwm)) {
196 /*
197 * If the PWM channel is enabled, using the duty update register
198 * to update the value.
199 */
200 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTYUPD, dty);
201 } else {
202 /*
203 * If the PWM channel is disabled, write value to duty and
204 * period registers directly.
205 */
206 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CDTY, dty);
207 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWMV2_CPRD, prd);
208 }
209}
210
211static int atmel_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
212 enum pwm_polarity polarity)
213{
214 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
215 u32 val;
216 int ret;
217
218 val = atmel_pwm_ch_readl(atmel_pwm, pwm->hwpwm, PWM_CMR);
219
220 if (polarity == PWM_POLARITY_NORMAL)
221 val &= ~PWM_CMR_CPOL;
222 else
223 val |= PWM_CMR_CPOL;
224
225 ret = clk_enable(atmel_pwm->clk);
226 if (ret) {
227 dev_err(chip->dev, "failed to enable PWM clock\n");
228 return ret;
229 }
230
231 atmel_pwm_ch_writel(atmel_pwm, pwm->hwpwm, PWM_CMR, val);
232
233 clk_disable(atmel_pwm->clk);
234
235 return 0;
236}
237
238static int atmel_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
239{
240 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
241 int ret;
242
243 ret = clk_enable(atmel_pwm->clk);
244 if (ret) {
245 dev_err(chip->dev, "failed to enable PWM clock\n");
246 return ret;
247 }
248
249 atmel_pwm_writel(atmel_pwm, PWM_ENA, 1 << pwm->hwpwm);
250
251 return 0;
252}
253
254static void atmel_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
255{
256 struct atmel_pwm_chip *atmel_pwm = to_atmel_pwm_chip(chip);
257 unsigned long timeout = jiffies + 2 * HZ;
258
259 /*
260 * Wait for at least a complete period to have passed before disabling a
261 * channel to be sure that CDTY has been updated
262 */
263 mutex_lock(&atmel_pwm->isr_lock);
264 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
265
266 while (!(atmel_pwm->updated_pwms & (1 << pwm->hwpwm)) &&
267 time_before(jiffies, timeout)) {
268 usleep_range(10, 100);
269 atmel_pwm->updated_pwms |= atmel_pwm_readl(atmel_pwm, PWM_ISR);
270 }
271
272 mutex_unlock(&atmel_pwm->isr_lock);
273 atmel_pwm_writel(atmel_pwm, PWM_DIS, 1 << pwm->hwpwm);
274
275 /*
276 * Wait for the PWM channel disable operation to be effective before
277 * stopping the clock.
278 */
279 timeout = jiffies + 2 * HZ;
280
281 while ((atmel_pwm_readl(atmel_pwm, PWM_SR) & (1 << pwm->hwpwm)) &&
282 time_before(jiffies, timeout))
283 usleep_range(10, 100);
284
285 clk_disable(atmel_pwm->clk);
286}
287
288static const struct pwm_ops atmel_pwm_ops = {
289 .config = atmel_pwm_config,
290 .set_polarity = atmel_pwm_set_polarity,
291 .enable = atmel_pwm_enable,
292 .disable = atmel_pwm_disable,
293 .owner = THIS_MODULE,
294};
295
296struct atmel_pwm_data {
297 void (*config)(struct pwm_chip *chip, struct pwm_device *pwm,
298 unsigned long dty, unsigned long prd);
299};
300
301static const struct atmel_pwm_data atmel_pwm_data_v1 = {
302 .config = atmel_pwm_config_v1,
303};
304
305static const struct atmel_pwm_data atmel_pwm_data_v2 = {
306 .config = atmel_pwm_config_v2,
307};
308
309static const struct platform_device_id atmel_pwm_devtypes[] = {
310 {
311 .name = "at91sam9rl-pwm",
312 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v1,
313 }, {
314 .name = "sama5d3-pwm",
315 .driver_data = (kernel_ulong_t)&atmel_pwm_data_v2,
316 }, {
317 /* sentinel */
318 },
319};
320MODULE_DEVICE_TABLE(platform, atmel_pwm_devtypes);
321
322static const struct of_device_id atmel_pwm_dt_ids[] = {
323 {
324 .compatible = "atmel,at91sam9rl-pwm",
325 .data = &atmel_pwm_data_v1,
326 }, {
327 .compatible = "atmel,sama5d3-pwm",
328 .data = &atmel_pwm_data_v2,
329 }, {
330 /* sentinel */
331 },
332};
333MODULE_DEVICE_TABLE(of, atmel_pwm_dt_ids);
334
335static inline const struct atmel_pwm_data *
336atmel_pwm_get_driver_data(struct platform_device *pdev)
337{
338 const struct platform_device_id *id;
339
340 if (pdev->dev.of_node)
341 return of_device_get_match_data(&pdev->dev);
342
343 id = platform_get_device_id(pdev);
344
345 return (struct atmel_pwm_data *)id->driver_data;
346}
347
348static int atmel_pwm_probe(struct platform_device *pdev)
349{
350 const struct atmel_pwm_data *data;
351 struct atmel_pwm_chip *atmel_pwm;
352 struct resource *res;
353 int ret;
354
355 data = atmel_pwm_get_driver_data(pdev);
356 if (!data)
357 return -ENODEV;
358
359 atmel_pwm = devm_kzalloc(&pdev->dev, sizeof(*atmel_pwm), GFP_KERNEL);
360 if (!atmel_pwm)
361 return -ENOMEM;
362
363 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
364 atmel_pwm->base = devm_ioremap_resource(&pdev->dev, res);
365 if (IS_ERR(atmel_pwm->base))
366 return PTR_ERR(atmel_pwm->base);
367
368 atmel_pwm->clk = devm_clk_get(&pdev->dev, NULL);
369 if (IS_ERR(atmel_pwm->clk))
370 return PTR_ERR(atmel_pwm->clk);
371
372 ret = clk_prepare(atmel_pwm->clk);
373 if (ret) {
374 dev_err(&pdev->dev, "failed to prepare PWM clock\n");
375 return ret;
376 }
377
378 atmel_pwm->chip.dev = &pdev->dev;
379 atmel_pwm->chip.ops = &atmel_pwm_ops;
380
381 if (pdev->dev.of_node) {
382 atmel_pwm->chip.of_xlate = of_pwm_xlate_with_flags;
383 atmel_pwm->chip.of_pwm_n_cells = 3;
384 }
385
386 atmel_pwm->chip.base = -1;
387 atmel_pwm->chip.npwm = 4;
388 atmel_pwm->chip.can_sleep = true;
389 atmel_pwm->config = data->config;
390 atmel_pwm->updated_pwms = 0;
391 mutex_init(&atmel_pwm->isr_lock);
392
393 ret = pwmchip_add(&atmel_pwm->chip);
394 if (ret < 0) {
395 dev_err(&pdev->dev, "failed to add PWM chip %d\n", ret);
396 goto unprepare_clk;
397 }
398
399 platform_set_drvdata(pdev, atmel_pwm);
400
401 return ret;
402
403unprepare_clk:
404 clk_unprepare(atmel_pwm->clk);
405 return ret;
406}
407
408static int atmel_pwm_remove(struct platform_device *pdev)
409{
410 struct atmel_pwm_chip *atmel_pwm = platform_get_drvdata(pdev);
411
412 clk_unprepare(atmel_pwm->clk);
413 mutex_destroy(&atmel_pwm->isr_lock);
414
415 return pwmchip_remove(&atmel_pwm->chip);
416}
417
418static struct platform_driver atmel_pwm_driver = {
419 .driver = {
420 .name = "atmel-pwm",
421 .of_match_table = of_match_ptr(atmel_pwm_dt_ids),
422 },
423 .id_table = atmel_pwm_devtypes,
424 .probe = atmel_pwm_probe,
425 .remove = atmel_pwm_remove,
426};
427module_platform_driver(atmel_pwm_driver);
428
429MODULE_ALIAS("platform:atmel-pwm");
430MODULE_AUTHOR("Bo Shen <voice.shen@atmel.com>");
431MODULE_DESCRIPTION("Atmel PWM driver");
432MODULE_LICENSE("GPL v2");