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1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21/* Code sharing between pci-quirks and xhci hcd */
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25/* max buffer size for trace and debug messages */
26#define XHCI_MSG_MAX 500
27
28/* xHCI PCI Configuration Registers */
29#define XHCI_SBRN_OFFSET (0x60)
30
31/* Max number of USB devices for any host controller - limit in section 6.1 */
32#define MAX_HC_SLOTS 256
33/* Section 5.3.3 - MaxPorts */
34#define MAX_HC_PORTS 127
35
36/*
37 * xHCI register interface.
38 * This corresponds to the eXtensible Host Controller Interface (xHCI)
39 * Revision 0.95 specification
40 */
41
42/**
43 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
44 * @hc_capbase: length of the capabilities register and HC version number
45 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
46 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
47 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
48 * @hcc_params: HCCPARAMS - Capability Parameters
49 * @db_off: DBOFF - Doorbell array offset
50 * @run_regs_off: RTSOFF - Runtime register space offset
51 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
52 */
53struct xhci_cap_regs {
54 __le32 hc_capbase;
55 __le32 hcs_params1;
56 __le32 hcs_params2;
57 __le32 hcs_params3;
58 __le32 hcc_params;
59 __le32 db_off;
60 __le32 run_regs_off;
61 __le32 hcc_params2; /* xhci 1.1 */
62 /* Reserved up to (CAPLENGTH - 0x1C) */
63};
64
65/* hc_capbase bitmasks */
66/* bits 7:0 - how long is the Capabilities register */
67#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
68/* bits 31:16 */
69#define HC_VERSION(p) (((p) >> 16) & 0xffff)
70
71/* HCSPARAMS1 - hcs_params1 - bitmasks */
72/* bits 0:7, Max Device Slots */
73#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
74#define HCS_SLOTS_MASK 0xff
75/* bits 8:18, Max Interrupters */
76#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
77/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
78#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
79
80/* HCSPARAMS2 - hcs_params2 - bitmasks */
81/* bits 0:3, frames or uframes that SW needs to queue transactions
82 * ahead of the HW to meet periodic deadlines */
83#define HCS_IST(p) (((p) >> 0) & 0xf)
84/* bits 4:7, max number of Event Ring segments */
85#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
86/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
87/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
88/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
89#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
90
91/* HCSPARAMS3 - hcs_params3 - bitmasks */
92/* bits 0:7, Max U1 to U0 latency for the roothub ports */
93#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
94/* bits 16:31, Max U2 to U0 latency for the roothub ports */
95#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
96
97/* HCCPARAMS - hcc_params - bitmasks */
98/* true: HC can use 64-bit address pointers */
99#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
100/* true: HC can do bandwidth negotiation */
101#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
102/* true: HC uses 64-byte Device Context structures
103 * FIXME 64-byte context structures aren't supported yet.
104 */
105#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
106/* true: HC has port power switches */
107#define HCC_PPC(p) ((p) & (1 << 3))
108/* true: HC has port indicators */
109#define HCS_INDICATOR(p) ((p) & (1 << 4))
110/* true: HC has Light HC Reset Capability */
111#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
112/* true: HC supports latency tolerance messaging */
113#define HCC_LTC(p) ((p) & (1 << 6))
114/* true: no secondary Stream ID Support */
115#define HCC_NSS(p) ((p) & (1 << 7))
116/* true: HC supports Stopped - Short Packet */
117#define HCC_SPC(p) ((p) & (1 << 9))
118/* true: HC has Contiguous Frame ID Capability */
119#define HCC_CFC(p) ((p) & (1 << 11))
120/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
121#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122/* Extended Capabilities pointer from PCI base - section 5.3.6 */
123#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
126
127/* db_off bitmask - bits 0:1 reserved */
128#define DBOFF_MASK (~0x3)
129
130/* run_regs_off bitmask - bits 0:4 reserved */
131#define RTSOFF_MASK (~0x1f)
132
133/* HCCPARAMS2 - hcc_params2 - bitmasks */
134/* true: HC supports U3 entry Capability */
135#define HCC2_U3C(p) ((p) & (1 << 0))
136/* true: HC supports Configure endpoint command Max exit latency too large */
137#define HCC2_CMC(p) ((p) & (1 << 1))
138/* true: HC supports Force Save context Capability */
139#define HCC2_FSC(p) ((p) & (1 << 2))
140/* true: HC supports Compliance Transition Capability */
141#define HCC2_CTC(p) ((p) & (1 << 3))
142/* true: HC support Large ESIT payload Capability > 48k */
143#define HCC2_LEC(p) ((p) & (1 << 4))
144/* true: HC support Configuration Information Capability */
145#define HCC2_CIC(p) ((p) & (1 << 5))
146/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
147#define HCC2_ETC(p) ((p) & (1 << 6))
148
149/* Number of registers per port */
150#define NUM_PORT_REGS 4
151
152#define PORTSC 0
153#define PORTPMSC 1
154#define PORTLI 2
155#define PORTHLPMC 3
156
157/**
158 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
159 * @command: USBCMD - xHC command register
160 * @status: USBSTS - xHC status register
161 * @page_size: This indicates the page size that the host controller
162 * supports. If bit n is set, the HC supports a page size
163 * of 2^(n+12), up to a 128MB page size.
164 * 4K is the minimum page size.
165 * @cmd_ring: CRP - 64-bit Command Ring Pointer
166 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
167 * @config_reg: CONFIG - Configure Register
168 * @port_status_base: PORTSCn - base address for Port Status and Control
169 * Each port has a Port Status and Control register,
170 * followed by a Port Power Management Status and Control
171 * register, a Port Link Info register, and a reserved
172 * register.
173 * @port_power_base: PORTPMSCn - base address for
174 * Port Power Management Status and Control
175 * @port_link_base: PORTLIn - base address for Port Link Info (current
176 * Link PM state and control) for USB 2.1 and USB 3.0
177 * devices.
178 */
179struct xhci_op_regs {
180 __le32 command;
181 __le32 status;
182 __le32 page_size;
183 __le32 reserved1;
184 __le32 reserved2;
185 __le32 dev_notification;
186 __le64 cmd_ring;
187 /* rsvd: offset 0x20-2F */
188 __le32 reserved3[4];
189 __le64 dcbaa_ptr;
190 __le32 config_reg;
191 /* rsvd: offset 0x3C-3FF */
192 __le32 reserved4[241];
193 /* port 1 registers, which serve as a base address for other ports */
194 __le32 port_status_base;
195 __le32 port_power_base;
196 __le32 port_link_base;
197 __le32 reserved5;
198 /* registers for ports 2-255 */
199 __le32 reserved6[NUM_PORT_REGS*254];
200};
201
202/* USBCMD - USB command - command bitmasks */
203/* start/stop HC execution - do not write unless HC is halted*/
204#define CMD_RUN XHCI_CMD_RUN
205/* Reset HC - resets internal HC state machine and all registers (except
206 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
207 * The xHCI driver must reinitialize the xHC after setting this bit.
208 */
209#define CMD_RESET (1 << 1)
210/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
211#define CMD_EIE XHCI_CMD_EIE
212/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
213#define CMD_HSEIE XHCI_CMD_HSEIE
214/* bits 4:6 are reserved (and should be preserved on writes). */
215/* light reset (port status stays unchanged) - reset completed when this is 0 */
216#define CMD_LRESET (1 << 7)
217/* host controller save/restore state. */
218#define CMD_CSS (1 << 8)
219#define CMD_CRS (1 << 9)
220/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
221#define CMD_EWE XHCI_CMD_EWE
222/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
223 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
224 * '0' means the xHC can power it off if all ports are in the disconnect,
225 * disabled, or powered-off state.
226 */
227#define CMD_PM_INDEX (1 << 11)
228/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
229#define CMD_ETE (1 << 14)
230/* bits 15:31 are reserved (and should be preserved on writes). */
231
232#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
233#define XHCI_RESET_SHORT_USEC (250 * 1000)
234
235/* IMAN - Interrupt Management Register */
236#define IMAN_IE (1 << 1)
237#define IMAN_IP (1 << 0)
238
239/* USBSTS - USB status - status bitmasks */
240/* HC not running - set to 1 when run/stop bit is cleared. */
241#define STS_HALT XHCI_STS_HALT
242/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
243#define STS_FATAL (1 << 2)
244/* event interrupt - clear this prior to clearing any IP flags in IR set*/
245#define STS_EINT (1 << 3)
246/* port change detect */
247#define STS_PORT (1 << 4)
248/* bits 5:7 reserved and zeroed */
249/* save state status - '1' means xHC is saving state */
250#define STS_SAVE (1 << 8)
251/* restore state status - '1' means xHC is restoring state */
252#define STS_RESTORE (1 << 9)
253/* true: save or restore error */
254#define STS_SRE (1 << 10)
255/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
256#define STS_CNR XHCI_STS_CNR
257/* true: internal Host Controller Error - SW needs to reset and reinitialize */
258#define STS_HCE (1 << 12)
259/* bits 13:31 reserved and should be preserved */
260
261/*
262 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
263 * Generate a device notification event when the HC sees a transaction with a
264 * notification type that matches a bit set in this bit field.
265 */
266#define DEV_NOTE_MASK (0xffff)
267#define ENABLE_DEV_NOTE(x) (1 << (x))
268/* Most of the device notification types should only be used for debug.
269 * SW does need to pay attention to function wake notifications.
270 */
271#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
272
273/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
274/* bit 0 is the command ring cycle state */
275/* stop ring operation after completion of the currently executing command */
276#define CMD_RING_PAUSE (1 << 1)
277/* stop ring immediately - abort the currently executing command */
278#define CMD_RING_ABORT (1 << 2)
279/* true: command ring is running */
280#define CMD_RING_RUNNING (1 << 3)
281/* bits 4:5 reserved and should be preserved */
282/* Command Ring pointer - bit mask for the lower 32 bits. */
283#define CMD_RING_RSVD_BITS (0x3f)
284
285/* CONFIG - Configure Register - config_reg bitmasks */
286/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
287#define MAX_DEVS(p) ((p) & 0xff)
288/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
289#define CONFIG_U3E (1 << 8)
290/* bit 9: Configuration Information Enable, xhci 1.1 */
291#define CONFIG_CIE (1 << 9)
292/* bits 10:31 - reserved and should be preserved */
293
294/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
295/* true: device connected */
296#define PORT_CONNECT (1 << 0)
297/* true: port enabled */
298#define PORT_PE (1 << 1)
299/* bit 2 reserved and zeroed */
300/* true: port has an over-current condition */
301#define PORT_OC (1 << 3)
302/* true: port reset signaling asserted */
303#define PORT_RESET (1 << 4)
304/* Port Link State - bits 5:8
305 * A read gives the current link PM state of the port,
306 * a write with Link State Write Strobe set sets the link state.
307 */
308#define PORT_PLS_MASK (0xf << 5)
309#define XDEV_U0 (0x0 << 5)
310#define XDEV_U1 (0x1 << 5)
311#define XDEV_U2 (0x2 << 5)
312#define XDEV_U3 (0x3 << 5)
313#define XDEV_DISABLED (0x4 << 5)
314#define XDEV_RXDETECT (0x5 << 5)
315#define XDEV_INACTIVE (0x6 << 5)
316#define XDEV_POLLING (0x7 << 5)
317#define XDEV_RECOVERY (0x8 << 5)
318#define XDEV_HOT_RESET (0x9 << 5)
319#define XDEV_COMP_MODE (0xa << 5)
320#define XDEV_TEST_MODE (0xb << 5)
321#define XDEV_RESUME (0xf << 5)
322
323/* true: port has power (see HCC_PPC) */
324#define PORT_POWER (1 << 9)
325/* bits 10:13 indicate device speed:
326 * 0 - undefined speed - port hasn't be initialized by a reset yet
327 * 1 - full speed
328 * 2 - low speed
329 * 3 - high speed
330 * 4 - super speed
331 * 5-15 reserved
332 */
333#define DEV_SPEED_MASK (0xf << 10)
334#define XDEV_FS (0x1 << 10)
335#define XDEV_LS (0x2 << 10)
336#define XDEV_HS (0x3 << 10)
337#define XDEV_SS (0x4 << 10)
338#define XDEV_SSP (0x5 << 10)
339#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
340#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
341#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
342#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
343#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
344#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
345#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
346#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
347
348/* Bits 20:23 in the Slot Context are the speed for the device */
349#define SLOT_SPEED_FS (XDEV_FS << 10)
350#define SLOT_SPEED_LS (XDEV_LS << 10)
351#define SLOT_SPEED_HS (XDEV_HS << 10)
352#define SLOT_SPEED_SS (XDEV_SS << 10)
353#define SLOT_SPEED_SSP (XDEV_SSP << 10)
354/* Port Indicator Control */
355#define PORT_LED_OFF (0 << 14)
356#define PORT_LED_AMBER (1 << 14)
357#define PORT_LED_GREEN (2 << 14)
358#define PORT_LED_MASK (3 << 14)
359/* Port Link State Write Strobe - set this when changing link state */
360#define PORT_LINK_STROBE (1 << 16)
361/* true: connect status change */
362#define PORT_CSC (1 << 17)
363/* true: port enable change */
364#define PORT_PEC (1 << 18)
365/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
366 * into an enabled state, and the device into the default state. A "warm" reset
367 * also resets the link, forcing the device through the link training sequence.
368 * SW can also look at the Port Reset register to see when warm reset is done.
369 */
370#define PORT_WRC (1 << 19)
371/* true: over-current change */
372#define PORT_OCC (1 << 20)
373/* true: reset change - 1 to 0 transition of PORT_RESET */
374#define PORT_RC (1 << 21)
375/* port link status change - set on some port link state transitions:
376 * Transition Reason
377 * ------------------------------------------------------------------------------
378 * - U3 to Resume Wakeup signaling from a device
379 * - Resume to Recovery to U0 USB 3.0 device resume
380 * - Resume to U0 USB 2.0 device resume
381 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
382 * - U3 to U0 Software resume of USB 2.0 device complete
383 * - U2 to U0 L1 resume of USB 2.1 device complete
384 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
385 * - U0 to disabled L1 entry error with USB 2.1 device
386 * - Any state to inactive Error on USB 3.0 port
387 */
388#define PORT_PLC (1 << 22)
389/* port configure error change - port failed to configure its link partner */
390#define PORT_CEC (1 << 23)
391#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
392 PORT_RC | PORT_PLC | PORT_CEC)
393
394
395/* Cold Attach Status - xHC can set this bit to report device attached during
396 * Sx state. Warm port reset should be perfomed to clear this bit and move port
397 * to connected state.
398 */
399#define PORT_CAS (1 << 24)
400/* wake on connect (enable) */
401#define PORT_WKCONN_E (1 << 25)
402/* wake on disconnect (enable) */
403#define PORT_WKDISC_E (1 << 26)
404/* wake on over-current (enable) */
405#define PORT_WKOC_E (1 << 27)
406/* bits 28:29 reserved */
407/* true: device is non-removable - for USB 3.0 roothub emulation */
408#define PORT_DEV_REMOVE (1 << 30)
409/* Initiate a warm port reset - complete when PORT_WRC is '1' */
410#define PORT_WR (1 << 31)
411
412/* We mark duplicate entries with -1 */
413#define DUPLICATE_ENTRY ((u8)(-1))
414
415/* Port Power Management Status and Control - port_power_base bitmasks */
416/* Inactivity timer value for transitions into U1, in microseconds.
417 * Timeout can be up to 127us. 0xFF means an infinite timeout.
418 */
419#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
420#define PORT_U1_TIMEOUT_MASK 0xff
421/* Inactivity timer value for transitions into U2 */
422#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
423#define PORT_U2_TIMEOUT_MASK (0xff << 8)
424/* Bits 24:31 for port testing */
425
426/* USB2 Protocol PORTSPMSC */
427#define PORT_L1S_MASK 7
428#define PORT_L1S_SUCCESS 1
429#define PORT_RWE (1 << 3)
430#define PORT_HIRD(p) (((p) & 0xf) << 4)
431#define PORT_HIRD_MASK (0xf << 4)
432#define PORT_L1DS_MASK (0xff << 8)
433#define PORT_L1DS(p) (((p) & 0xff) << 8)
434#define PORT_HLE (1 << 16)
435#define PORT_TEST_MODE_SHIFT 28
436
437/* USB3 Protocol PORTLI Port Link Information */
438#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
439#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
440
441/* USB2 Protocol PORTHLPMC */
442#define PORT_HIRDM(p)((p) & 3)
443#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
444#define PORT_BESLD(p)(((p) & 0xf) << 10)
445
446/* use 512 microseconds as USB2 LPM L1 default timeout. */
447#define XHCI_L1_TIMEOUT 512
448
449/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
450 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
451 * by other operating systems.
452 *
453 * XHCI 1.0 errata 8/14/12 Table 13 notes:
454 * "Software should choose xHC BESL/BESLD field values that do not violate a
455 * device's resume latency requirements,
456 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
457 * or not program values < '4' if BLC = '0' and a BESL device is attached.
458 */
459#define XHCI_DEFAULT_BESL 4
460
461/*
462 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
463 * to complete link training. usually link trainig completes much faster
464 * so check status 10 times with 36ms sleep in places we need to wait for
465 * polling to complete.
466 */
467#define XHCI_PORT_POLLING_LFPS_TIME 36
468
469/**
470 * struct xhci_intr_reg - Interrupt Register Set
471 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
472 * interrupts and check for pending interrupts.
473 * @irq_control: IMOD - Interrupt Moderation Register.
474 * Used to throttle interrupts.
475 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
476 * @erst_base: ERST base address.
477 * @erst_dequeue: Event ring dequeue pointer.
478 *
479 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
480 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
481 * multiple segments of the same size. The HC places events on the ring and
482 * "updates the Cycle bit in the TRBs to indicate to software the current
483 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
484 * updates the dequeue pointer.
485 */
486struct xhci_intr_reg {
487 __le32 irq_pending;
488 __le32 irq_control;
489 __le32 erst_size;
490 __le32 rsvd;
491 __le64 erst_base;
492 __le64 erst_dequeue;
493};
494
495/* irq_pending bitmasks */
496#define ER_IRQ_PENDING(p) ((p) & 0x1)
497/* bits 2:31 need to be preserved */
498/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
499#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
500#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
501#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
502
503/* irq_control bitmasks */
504/* Minimum interval between interrupts (in 250ns intervals). The interval
505 * between interrupts will be longer if there are no events on the event ring.
506 * Default is 4000 (1 ms).
507 */
508#define ER_IRQ_INTERVAL_MASK (0xffff)
509/* Counter used to count down the time to the next interrupt - HW use only */
510#define ER_IRQ_COUNTER_MASK (0xffff << 16)
511
512/* erst_size bitmasks */
513/* Preserve bits 16:31 of erst_size */
514#define ERST_SIZE_MASK (0xffff << 16)
515
516/* erst_base bitmasks */
517#define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
518
519/* erst_dequeue bitmasks */
520/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
521 * where the current dequeue pointer lies. This is an optional HW hint.
522 */
523#define ERST_DESI_MASK (0x7)
524/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
525 * a work queue (or delayed service routine)?
526 */
527#define ERST_EHB (1 << 3)
528#define ERST_PTR_MASK (GENMASK_ULL(63, 4))
529
530/**
531 * struct xhci_run_regs
532 * @microframe_index:
533 * MFINDEX - current microframe number
534 *
535 * Section 5.5 Host Controller Runtime Registers:
536 * "Software should read and write these registers using only Dword (32 bit)
537 * or larger accesses"
538 */
539struct xhci_run_regs {
540 __le32 microframe_index;
541 __le32 rsvd[7];
542 struct xhci_intr_reg ir_set[128];
543};
544
545/**
546 * struct doorbell_array
547 *
548 * Bits 0 - 7: Endpoint target
549 * Bits 8 - 15: RsvdZ
550 * Bits 16 - 31: Stream ID
551 *
552 * Section 5.6
553 */
554struct xhci_doorbell_array {
555 __le32 doorbell[256];
556};
557
558#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
559#define DB_VALUE_HOST 0x00000000
560
561#define PLT_MASK (0x03 << 6)
562#define PLT_SYM (0x00 << 6)
563#define PLT_ASYM_RX (0x02 << 6)
564#define PLT_ASYM_TX (0x03 << 6)
565
566/**
567 * struct xhci_container_ctx
568 * @type: Type of context. Used to calculated offsets to contained contexts.
569 * @size: Size of the context data
570 * @bytes: The raw context data given to HW
571 * @dma: dma address of the bytes
572 *
573 * Represents either a Device or Input context. Holds a pointer to the raw
574 * memory used for the context (bytes) and dma address of it (dma).
575 */
576struct xhci_container_ctx {
577 unsigned type;
578#define XHCI_CTX_TYPE_DEVICE 0x1
579#define XHCI_CTX_TYPE_INPUT 0x2
580
581 int size;
582
583 u8 *bytes;
584 dma_addr_t dma;
585};
586
587/**
588 * struct xhci_slot_ctx
589 * @dev_info: Route string, device speed, hub info, and last valid endpoint
590 * @dev_info2: Max exit latency for device number, root hub port number
591 * @tt_info: tt_info is used to construct split transaction tokens
592 * @dev_state: slot state and device address
593 *
594 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
595 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
596 * reserved at the end of the slot context for HC internal use.
597 */
598struct xhci_slot_ctx {
599 __le32 dev_info;
600 __le32 dev_info2;
601 __le32 tt_info;
602 __le32 dev_state;
603 /* offset 0x10 to 0x1f reserved for HC internal use */
604 __le32 reserved[4];
605};
606
607/* dev_info bitmasks */
608/* Route String - 0:19 */
609#define ROUTE_STRING_MASK (0xfffff)
610/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
611#define DEV_SPEED (0xf << 20)
612#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
613/* bit 24 reserved */
614/* Is this LS/FS device connected through a HS hub? - bit 25 */
615#define DEV_MTT (0x1 << 25)
616/* Set if the device is a hub - bit 26 */
617#define DEV_HUB (0x1 << 26)
618/* Index of the last valid endpoint context in this device context - 27:31 */
619#define LAST_CTX_MASK (0x1f << 27)
620#define LAST_CTX(p) ((p) << 27)
621#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
622#define SLOT_FLAG (1 << 0)
623#define EP0_FLAG (1 << 1)
624
625/* dev_info2 bitmasks */
626/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
627#define MAX_EXIT (0xffff)
628/* Root hub port number that is needed to access the USB device */
629#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
630#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
631/* Maximum number of ports under a hub device */
632#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
633#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
634
635/* tt_info bitmasks */
636/*
637 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
638 * The Slot ID of the hub that isolates the high speed signaling from
639 * this low or full-speed device. '0' if attached to root hub port.
640 */
641#define TT_SLOT (0xff)
642/*
643 * The number of the downstream facing port of the high-speed hub
644 * '0' if the device is not low or full speed.
645 */
646#define TT_PORT (0xff << 8)
647#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
648#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
649
650/* dev_state bitmasks */
651/* USB device address - assigned by the HC */
652#define DEV_ADDR_MASK (0xff)
653/* bits 8:26 reserved */
654/* Slot state */
655#define SLOT_STATE (0x1f << 27)
656#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
657
658#define SLOT_STATE_DISABLED 0
659#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
660#define SLOT_STATE_DEFAULT 1
661#define SLOT_STATE_ADDRESSED 2
662#define SLOT_STATE_CONFIGURED 3
663
664/**
665 * struct xhci_ep_ctx
666 * @ep_info: endpoint state, streams, mult, and interval information.
667 * @ep_info2: information on endpoint type, max packet size, max burst size,
668 * error count, and whether the HC will force an event for all
669 * transactions.
670 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
671 * defines one stream, this points to the endpoint transfer ring.
672 * Otherwise, it points to a stream context array, which has a
673 * ring pointer for each flow.
674 * @tx_info:
675 * Average TRB lengths for the endpoint ring and
676 * max payload within an Endpoint Service Interval Time (ESIT).
677 *
678 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
679 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
680 * reserved at the end of the endpoint context for HC internal use.
681 */
682struct xhci_ep_ctx {
683 __le32 ep_info;
684 __le32 ep_info2;
685 __le64 deq;
686 __le32 tx_info;
687 /* offset 0x14 - 0x1f reserved for HC internal use */
688 __le32 reserved[3];
689};
690
691/* ep_info bitmasks */
692/*
693 * Endpoint State - bits 0:2
694 * 0 - disabled
695 * 1 - running
696 * 2 - halted due to halt condition - ok to manipulate endpoint ring
697 * 3 - stopped
698 * 4 - TRB error
699 * 5-7 - reserved
700 */
701#define EP_STATE_MASK (0x7)
702#define EP_STATE_DISABLED 0
703#define EP_STATE_RUNNING 1
704#define EP_STATE_HALTED 2
705#define EP_STATE_STOPPED 3
706#define EP_STATE_ERROR 4
707#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
708
709/* Mult - Max number of burtst within an interval, in EP companion desc. */
710#define EP_MULT(p) (((p) & 0x3) << 8)
711#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
712/* bits 10:14 are Max Primary Streams */
713/* bit 15 is Linear Stream Array */
714/* Interval - period between requests to an endpoint - 125u increments. */
715#define EP_INTERVAL(p) (((p) & 0xff) << 16)
716#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
717#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
718#define EP_MAXPSTREAMS_MASK (0x1f << 10)
719#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
720#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
721/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
722#define EP_HAS_LSA (1 << 15)
723/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
724#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
725
726/* ep_info2 bitmasks */
727/*
728 * Force Event - generate transfer events for all TRBs for this endpoint
729 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
730 */
731#define FORCE_EVENT (0x1)
732#define ERROR_COUNT(p) (((p) & 0x3) << 1)
733#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
734#define EP_TYPE(p) ((p) << 3)
735#define ISOC_OUT_EP 1
736#define BULK_OUT_EP 2
737#define INT_OUT_EP 3
738#define CTRL_EP 4
739#define ISOC_IN_EP 5
740#define BULK_IN_EP 6
741#define INT_IN_EP 7
742/* bit 6 reserved */
743/* bit 7 is Host Initiate Disable - for disabling stream selection */
744#define MAX_BURST(p) (((p)&0xff) << 8)
745#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
746#define MAX_PACKET(p) (((p)&0xffff) << 16)
747#define MAX_PACKET_MASK (0xffff << 16)
748#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
749
750/* tx_info bitmasks */
751#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
752#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
753#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
754#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
755
756/* deq bitmasks */
757#define EP_CTX_CYCLE_MASK (1 << 0)
758#define SCTX_DEQ_MASK (~0xfL)
759
760
761/**
762 * struct xhci_input_control_context
763 * Input control context; see section 6.2.5.
764 *
765 * @drop_context: set the bit of the endpoint context you want to disable
766 * @add_context: set the bit of the endpoint context you want to enable
767 */
768struct xhci_input_control_ctx {
769 __le32 drop_flags;
770 __le32 add_flags;
771 __le32 rsvd2[6];
772};
773
774#define EP_IS_ADDED(ctrl_ctx, i) \
775 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
776#define EP_IS_DROPPED(ctrl_ctx, i) \
777 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
778
779/* Represents everything that is needed to issue a command on the command ring.
780 * It's useful to pre-allocate these for commands that cannot fail due to
781 * out-of-memory errors, like freeing streams.
782 */
783struct xhci_command {
784 /* Input context for changing device state */
785 struct xhci_container_ctx *in_ctx;
786 u32 status;
787 int slot_id;
788 /* If completion is null, no one is waiting on this command
789 * and the structure can be freed after the command completes.
790 */
791 struct completion *completion;
792 union xhci_trb *command_trb;
793 struct list_head cmd_list;
794 /* xHCI command response timeout in milliseconds */
795 unsigned int timeout_ms;
796};
797
798/* drop context bitmasks */
799#define DROP_EP(x) (0x1 << x)
800/* add context bitmasks */
801#define ADD_EP(x) (0x1 << x)
802
803struct xhci_stream_ctx {
804 /* 64-bit stream ring address, cycle state, and stream type */
805 __le64 stream_ring;
806 /* offset 0x14 - 0x1f reserved for HC internal use */
807 __le32 reserved[2];
808};
809
810/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
811#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
812/* Secondary stream array type, dequeue pointer is to a transfer ring */
813#define SCT_SEC_TR 0
814/* Primary stream array type, dequeue pointer is to a transfer ring */
815#define SCT_PRI_TR 1
816/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
817#define SCT_SSA_8 2
818#define SCT_SSA_16 3
819#define SCT_SSA_32 4
820#define SCT_SSA_64 5
821#define SCT_SSA_128 6
822#define SCT_SSA_256 7
823
824/* Assume no secondary streams for now */
825struct xhci_stream_info {
826 struct xhci_ring **stream_rings;
827 /* Number of streams, including stream 0 (which drivers can't use) */
828 unsigned int num_streams;
829 /* The stream context array may be bigger than
830 * the number of streams the driver asked for
831 */
832 struct xhci_stream_ctx *stream_ctx_array;
833 unsigned int num_stream_ctxs;
834 dma_addr_t ctx_array_dma;
835 /* For mapping physical TRB addresses to segments in stream rings */
836 struct radix_tree_root trb_address_map;
837 struct xhci_command *free_streams_command;
838};
839
840#define SMALL_STREAM_ARRAY_SIZE 256
841#define MEDIUM_STREAM_ARRAY_SIZE 1024
842
843/* Some Intel xHCI host controllers need software to keep track of the bus
844 * bandwidth. Keep track of endpoint info here. Each root port is allocated
845 * the full bus bandwidth. We must also treat TTs (including each port under a
846 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
847 * (DMI) also limits the total bandwidth (across all domains) that can be used.
848 */
849struct xhci_bw_info {
850 /* ep_interval is zero-based */
851 unsigned int ep_interval;
852 /* mult and num_packets are one-based */
853 unsigned int mult;
854 unsigned int num_packets;
855 unsigned int max_packet_size;
856 unsigned int max_esit_payload;
857 unsigned int type;
858};
859
860/* "Block" sizes in bytes the hardware uses for different device speeds.
861 * The logic in this part of the hardware limits the number of bits the hardware
862 * can use, so must represent bandwidth in a less precise manner to mimic what
863 * the scheduler hardware computes.
864 */
865#define FS_BLOCK 1
866#define HS_BLOCK 4
867#define SS_BLOCK 16
868#define DMI_BLOCK 32
869
870/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
871 * with each byte transferred. SuperSpeed devices have an initial overhead to
872 * set up bursts. These are in blocks, see above. LS overhead has already been
873 * translated into FS blocks.
874 */
875#define DMI_OVERHEAD 8
876#define DMI_OVERHEAD_BURST 4
877#define SS_OVERHEAD 8
878#define SS_OVERHEAD_BURST 32
879#define HS_OVERHEAD 26
880#define FS_OVERHEAD 20
881#define LS_OVERHEAD 128
882/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
883 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
884 * of overhead associated with split transfers crossing microframe boundaries.
885 * 31 blocks is pure protocol overhead.
886 */
887#define TT_HS_OVERHEAD (31 + 94)
888#define TT_DMI_OVERHEAD (25 + 12)
889
890/* Bandwidth limits in blocks */
891#define FS_BW_LIMIT 1285
892#define TT_BW_LIMIT 1320
893#define HS_BW_LIMIT 1607
894#define SS_BW_LIMIT_IN 3906
895#define DMI_BW_LIMIT_IN 3906
896#define SS_BW_LIMIT_OUT 3906
897#define DMI_BW_LIMIT_OUT 3906
898
899/* Percentage of bus bandwidth reserved for non-periodic transfers */
900#define FS_BW_RESERVED 10
901#define HS_BW_RESERVED 20
902#define SS_BW_RESERVED 10
903
904struct xhci_virt_ep {
905 struct xhci_virt_device *vdev; /* parent */
906 unsigned int ep_index;
907 struct xhci_ring *ring;
908 /* Related to endpoints that are configured to use stream IDs only */
909 struct xhci_stream_info *stream_info;
910 /* Temporary storage in case the configure endpoint command fails and we
911 * have to restore the device state to the previous state
912 */
913 struct xhci_ring *new_ring;
914 unsigned int err_count;
915 unsigned int ep_state;
916#define SET_DEQ_PENDING (1 << 0)
917#define EP_HALTED (1 << 1) /* For stall handling */
918#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
919/* Transitioning the endpoint to using streams, don't enqueue URBs */
920#define EP_GETTING_STREAMS (1 << 3)
921#define EP_HAS_STREAMS (1 << 4)
922/* Transitioning the endpoint to not using streams, don't enqueue URBs */
923#define EP_GETTING_NO_STREAMS (1 << 5)
924#define EP_HARD_CLEAR_TOGGLE (1 << 6)
925#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
926/* usb_hub_clear_tt_buffer is in progress */
927#define EP_CLEARING_TT (1 << 8)
928 /* ---- Related to URB cancellation ---- */
929 struct list_head cancelled_td_list;
930 struct xhci_hcd *xhci;
931 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
932 * command. We'll need to update the ring's dequeue segment and dequeue
933 * pointer after the command completes.
934 */
935 struct xhci_segment *queued_deq_seg;
936 union xhci_trb *queued_deq_ptr;
937 /*
938 * Sometimes the xHC can not process isochronous endpoint ring quickly
939 * enough, and it will miss some isoc tds on the ring and generate
940 * a Missed Service Error Event.
941 * Set skip flag when receive a Missed Service Error Event and
942 * process the missed tds on the endpoint ring.
943 */
944 bool skip;
945 /* Bandwidth checking storage */
946 struct xhci_bw_info bw_info;
947 struct list_head bw_endpoint_list;
948 /* Isoch Frame ID checking storage */
949 int next_frame_id;
950 /* Use new Isoch TRB layout needed for extended TBC support */
951 bool use_extended_tbc;
952};
953
954enum xhci_overhead_type {
955 LS_OVERHEAD_TYPE = 0,
956 FS_OVERHEAD_TYPE,
957 HS_OVERHEAD_TYPE,
958};
959
960struct xhci_interval_bw {
961 unsigned int num_packets;
962 /* Sorted by max packet size.
963 * Head of the list is the greatest max packet size.
964 */
965 struct list_head endpoints;
966 /* How many endpoints of each speed are present. */
967 unsigned int overhead[3];
968};
969
970#define XHCI_MAX_INTERVAL 16
971
972struct xhci_interval_bw_table {
973 unsigned int interval0_esit_payload;
974 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
975 /* Includes reserved bandwidth for async endpoints */
976 unsigned int bw_used;
977 unsigned int ss_bw_in;
978 unsigned int ss_bw_out;
979};
980
981#define EP_CTX_PER_DEV 31
982
983struct xhci_virt_device {
984 int slot_id;
985 struct usb_device *udev;
986 /*
987 * Commands to the hardware are passed an "input context" that
988 * tells the hardware what to change in its data structures.
989 * The hardware will return changes in an "output context" that
990 * software must allocate for the hardware. We need to keep
991 * track of input and output contexts separately because
992 * these commands might fail and we don't trust the hardware.
993 */
994 struct xhci_container_ctx *out_ctx;
995 /* Used for addressing devices and configuration changes */
996 struct xhci_container_ctx *in_ctx;
997 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
998 u8 fake_port;
999 u8 real_port;
1000 struct xhci_interval_bw_table *bw_table;
1001 struct xhci_tt_bw_info *tt_info;
1002 /*
1003 * flags for state tracking based on events and issued commands.
1004 * Software can not rely on states from output contexts because of
1005 * latency between events and xHC updating output context values.
1006 * See xhci 1.1 section 4.8.3 for more details
1007 */
1008 unsigned long flags;
1009#define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1010
1011 /* The current max exit latency for the enabled USB3 link states. */
1012 u16 current_mel;
1013 /* Used for the debugfs interfaces. */
1014 void *debugfs_private;
1015};
1016
1017/*
1018 * For each roothub, keep track of the bandwidth information for each periodic
1019 * interval.
1020 *
1021 * If a high speed hub is attached to the roothub, each TT associated with that
1022 * hub is a separate bandwidth domain. The interval information for the
1023 * endpoints on the devices under that TT will appear in the TT structure.
1024 */
1025struct xhci_root_port_bw_info {
1026 struct list_head tts;
1027 unsigned int num_active_tts;
1028 struct xhci_interval_bw_table bw_table;
1029};
1030
1031struct xhci_tt_bw_info {
1032 struct list_head tt_list;
1033 int slot_id;
1034 int ttport;
1035 struct xhci_interval_bw_table bw_table;
1036 int active_eps;
1037};
1038
1039
1040/**
1041 * struct xhci_device_context_array
1042 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1043 */
1044struct xhci_device_context_array {
1045 /* 64-bit device addresses; we only write 32-bit addresses */
1046 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1047 /* private xHCD pointers */
1048 dma_addr_t dma;
1049};
1050/* TODO: write function to set the 64-bit device DMA address */
1051/*
1052 * TODO: change this to be dynamically sized at HC mem init time since the HC
1053 * might not be able to handle the maximum number of devices possible.
1054 */
1055
1056
1057struct xhci_transfer_event {
1058 /* 64-bit buffer address, or immediate data */
1059 __le64 buffer;
1060 __le32 transfer_len;
1061 /* This field is interpreted differently based on the type of TRB */
1062 __le32 flags;
1063};
1064
1065/* Transfer event TRB length bit mask */
1066/* bits 0:23 */
1067#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1068
1069/** Transfer Event bit fields **/
1070#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1071
1072/* Completion Code - only applicable for some types of TRBs */
1073#define COMP_CODE_MASK (0xff << 24)
1074#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1075#define COMP_INVALID 0
1076#define COMP_SUCCESS 1
1077#define COMP_DATA_BUFFER_ERROR 2
1078#define COMP_BABBLE_DETECTED_ERROR 3
1079#define COMP_USB_TRANSACTION_ERROR 4
1080#define COMP_TRB_ERROR 5
1081#define COMP_STALL_ERROR 6
1082#define COMP_RESOURCE_ERROR 7
1083#define COMP_BANDWIDTH_ERROR 8
1084#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1085#define COMP_INVALID_STREAM_TYPE_ERROR 10
1086#define COMP_SLOT_NOT_ENABLED_ERROR 11
1087#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1088#define COMP_SHORT_PACKET 13
1089#define COMP_RING_UNDERRUN 14
1090#define COMP_RING_OVERRUN 15
1091#define COMP_VF_EVENT_RING_FULL_ERROR 16
1092#define COMP_PARAMETER_ERROR 17
1093#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1094#define COMP_CONTEXT_STATE_ERROR 19
1095#define COMP_NO_PING_RESPONSE_ERROR 20
1096#define COMP_EVENT_RING_FULL_ERROR 21
1097#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1098#define COMP_MISSED_SERVICE_ERROR 23
1099#define COMP_COMMAND_RING_STOPPED 24
1100#define COMP_COMMAND_ABORTED 25
1101#define COMP_STOPPED 26
1102#define COMP_STOPPED_LENGTH_INVALID 27
1103#define COMP_STOPPED_SHORT_PACKET 28
1104#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1105#define COMP_ISOCH_BUFFER_OVERRUN 31
1106#define COMP_EVENT_LOST_ERROR 32
1107#define COMP_UNDEFINED_ERROR 33
1108#define COMP_INVALID_STREAM_ID_ERROR 34
1109#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1110#define COMP_SPLIT_TRANSACTION_ERROR 36
1111
1112static inline const char *xhci_trb_comp_code_string(u8 status)
1113{
1114 switch (status) {
1115 case COMP_INVALID:
1116 return "Invalid";
1117 case COMP_SUCCESS:
1118 return "Success";
1119 case COMP_DATA_BUFFER_ERROR:
1120 return "Data Buffer Error";
1121 case COMP_BABBLE_DETECTED_ERROR:
1122 return "Babble Detected";
1123 case COMP_USB_TRANSACTION_ERROR:
1124 return "USB Transaction Error";
1125 case COMP_TRB_ERROR:
1126 return "TRB Error";
1127 case COMP_STALL_ERROR:
1128 return "Stall Error";
1129 case COMP_RESOURCE_ERROR:
1130 return "Resource Error";
1131 case COMP_BANDWIDTH_ERROR:
1132 return "Bandwidth Error";
1133 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1134 return "No Slots Available Error";
1135 case COMP_INVALID_STREAM_TYPE_ERROR:
1136 return "Invalid Stream Type Error";
1137 case COMP_SLOT_NOT_ENABLED_ERROR:
1138 return "Slot Not Enabled Error";
1139 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1140 return "Endpoint Not Enabled Error";
1141 case COMP_SHORT_PACKET:
1142 return "Short Packet";
1143 case COMP_RING_UNDERRUN:
1144 return "Ring Underrun";
1145 case COMP_RING_OVERRUN:
1146 return "Ring Overrun";
1147 case COMP_VF_EVENT_RING_FULL_ERROR:
1148 return "VF Event Ring Full Error";
1149 case COMP_PARAMETER_ERROR:
1150 return "Parameter Error";
1151 case COMP_BANDWIDTH_OVERRUN_ERROR:
1152 return "Bandwidth Overrun Error";
1153 case COMP_CONTEXT_STATE_ERROR:
1154 return "Context State Error";
1155 case COMP_NO_PING_RESPONSE_ERROR:
1156 return "No Ping Response Error";
1157 case COMP_EVENT_RING_FULL_ERROR:
1158 return "Event Ring Full Error";
1159 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1160 return "Incompatible Device Error";
1161 case COMP_MISSED_SERVICE_ERROR:
1162 return "Missed Service Error";
1163 case COMP_COMMAND_RING_STOPPED:
1164 return "Command Ring Stopped";
1165 case COMP_COMMAND_ABORTED:
1166 return "Command Aborted";
1167 case COMP_STOPPED:
1168 return "Stopped";
1169 case COMP_STOPPED_LENGTH_INVALID:
1170 return "Stopped - Length Invalid";
1171 case COMP_STOPPED_SHORT_PACKET:
1172 return "Stopped - Short Packet";
1173 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1174 return "Max Exit Latency Too Large Error";
1175 case COMP_ISOCH_BUFFER_OVERRUN:
1176 return "Isoch Buffer Overrun";
1177 case COMP_EVENT_LOST_ERROR:
1178 return "Event Lost Error";
1179 case COMP_UNDEFINED_ERROR:
1180 return "Undefined Error";
1181 case COMP_INVALID_STREAM_ID_ERROR:
1182 return "Invalid Stream ID Error";
1183 case COMP_SECONDARY_BANDWIDTH_ERROR:
1184 return "Secondary Bandwidth Error";
1185 case COMP_SPLIT_TRANSACTION_ERROR:
1186 return "Split Transaction Error";
1187 default:
1188 return "Unknown!!";
1189 }
1190}
1191
1192struct xhci_link_trb {
1193 /* 64-bit segment pointer*/
1194 __le64 segment_ptr;
1195 __le32 intr_target;
1196 __le32 control;
1197};
1198
1199/* control bitfields */
1200#define LINK_TOGGLE (0x1<<1)
1201
1202/* Command completion event TRB */
1203struct xhci_event_cmd {
1204 /* Pointer to command TRB, or the value passed by the event data trb */
1205 __le64 cmd_trb;
1206 __le32 status;
1207 __le32 flags;
1208};
1209
1210/* flags bitmasks */
1211
1212/* Address device - disable SetAddress */
1213#define TRB_BSR (1<<9)
1214
1215/* Configure Endpoint - Deconfigure */
1216#define TRB_DC (1<<9)
1217
1218/* Stop Ring - Transfer State Preserve */
1219#define TRB_TSP (1<<9)
1220
1221enum xhci_ep_reset_type {
1222 EP_HARD_RESET,
1223 EP_SOFT_RESET,
1224};
1225
1226/* Force Event */
1227#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1228#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1229
1230/* Set Latency Tolerance Value */
1231#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1232
1233/* Get Port Bandwidth */
1234#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1235
1236/* Force Header */
1237#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1238#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1239
1240enum xhci_setup_dev {
1241 SETUP_CONTEXT_ONLY,
1242 SETUP_CONTEXT_ADDRESS,
1243};
1244
1245/* bits 16:23 are the virtual function ID */
1246/* bits 24:31 are the slot ID */
1247#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1248#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1249
1250/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1251#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1252#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1253
1254#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1255#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1256#define LAST_EP_INDEX 30
1257
1258/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1259#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1260#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1261#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1262
1263/* Link TRB specific fields */
1264#define TRB_TC (1<<1)
1265
1266/* Port Status Change Event TRB fields */
1267/* Port ID - bits 31:24 */
1268#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1269
1270#define EVENT_DATA (1 << 2)
1271
1272/* Normal TRB fields */
1273/* transfer_len bitmasks - bits 0:16 */
1274#define TRB_LEN(p) ((p) & 0x1ffff)
1275/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1276#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1277#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1278/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1279#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1280/* Interrupter Target - which MSI-X vector to target the completion event at */
1281#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1282#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1283/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1284#define TRB_TBC(p) (((p) & 0x3) << 7)
1285#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1286
1287/* Cycle bit - indicates TRB ownership by HC or HCD */
1288#define TRB_CYCLE (1<<0)
1289/*
1290 * Force next event data TRB to be evaluated before task switch.
1291 * Used to pass OS data back after a TD completes.
1292 */
1293#define TRB_ENT (1<<1)
1294/* Interrupt on short packet */
1295#define TRB_ISP (1<<2)
1296/* Set PCIe no snoop attribute */
1297#define TRB_NO_SNOOP (1<<3)
1298/* Chain multiple TRBs into a TD */
1299#define TRB_CHAIN (1<<4)
1300/* Interrupt on completion */
1301#define TRB_IOC (1<<5)
1302/* The buffer pointer contains immediate data */
1303#define TRB_IDT (1<<6)
1304/* TDs smaller than this might use IDT */
1305#define TRB_IDT_MAX_SIZE 8
1306
1307/* Block Event Interrupt */
1308#define TRB_BEI (1<<9)
1309
1310/* Control transfer TRB specific fields */
1311#define TRB_DIR_IN (1<<16)
1312#define TRB_TX_TYPE(p) ((p) << 16)
1313#define TRB_DATA_OUT 2
1314#define TRB_DATA_IN 3
1315
1316/* Isochronous TRB specific fields */
1317#define TRB_SIA (1<<31)
1318#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1319
1320/* TRB cache size for xHC with TRB cache */
1321#define TRB_CACHE_SIZE_HS 8
1322#define TRB_CACHE_SIZE_SS 16
1323
1324struct xhci_generic_trb {
1325 __le32 field[4];
1326};
1327
1328union xhci_trb {
1329 struct xhci_link_trb link;
1330 struct xhci_transfer_event trans_event;
1331 struct xhci_event_cmd event_cmd;
1332 struct xhci_generic_trb generic;
1333};
1334
1335/* TRB bit mask */
1336#define TRB_TYPE_BITMASK (0xfc00)
1337#define TRB_TYPE(p) ((p) << 10)
1338#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1339/* TRB type IDs */
1340/* bulk, interrupt, isoc scatter/gather, and control data stage */
1341#define TRB_NORMAL 1
1342/* setup stage for control transfers */
1343#define TRB_SETUP 2
1344/* data stage for control transfers */
1345#define TRB_DATA 3
1346/* status stage for control transfers */
1347#define TRB_STATUS 4
1348/* isoc transfers */
1349#define TRB_ISOC 5
1350/* TRB for linking ring segments */
1351#define TRB_LINK 6
1352#define TRB_EVENT_DATA 7
1353/* Transfer Ring No-op (not for the command ring) */
1354#define TRB_TR_NOOP 8
1355/* Command TRBs */
1356/* Enable Slot Command */
1357#define TRB_ENABLE_SLOT 9
1358/* Disable Slot Command */
1359#define TRB_DISABLE_SLOT 10
1360/* Address Device Command */
1361#define TRB_ADDR_DEV 11
1362/* Configure Endpoint Command */
1363#define TRB_CONFIG_EP 12
1364/* Evaluate Context Command */
1365#define TRB_EVAL_CONTEXT 13
1366/* Reset Endpoint Command */
1367#define TRB_RESET_EP 14
1368/* Stop Transfer Ring Command */
1369#define TRB_STOP_RING 15
1370/* Set Transfer Ring Dequeue Pointer Command */
1371#define TRB_SET_DEQ 16
1372/* Reset Device Command */
1373#define TRB_RESET_DEV 17
1374/* Force Event Command (opt) */
1375#define TRB_FORCE_EVENT 18
1376/* Negotiate Bandwidth Command (opt) */
1377#define TRB_NEG_BANDWIDTH 19
1378/* Set Latency Tolerance Value Command (opt) */
1379#define TRB_SET_LT 20
1380/* Get port bandwidth Command */
1381#define TRB_GET_BW 21
1382/* Force Header Command - generate a transaction or link management packet */
1383#define TRB_FORCE_HEADER 22
1384/* No-op Command - not for transfer rings */
1385#define TRB_CMD_NOOP 23
1386/* TRB IDs 24-31 reserved */
1387/* Event TRBS */
1388/* Transfer Event */
1389#define TRB_TRANSFER 32
1390/* Command Completion Event */
1391#define TRB_COMPLETION 33
1392/* Port Status Change Event */
1393#define TRB_PORT_STATUS 34
1394/* Bandwidth Request Event (opt) */
1395#define TRB_BANDWIDTH_EVENT 35
1396/* Doorbell Event (opt) */
1397#define TRB_DOORBELL 36
1398/* Host Controller Event */
1399#define TRB_HC_EVENT 37
1400/* Device Notification Event - device sent function wake notification */
1401#define TRB_DEV_NOTE 38
1402/* MFINDEX Wrap Event - microframe counter wrapped */
1403#define TRB_MFINDEX_WRAP 39
1404/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1405#define TRB_VENDOR_DEFINED_LOW 48
1406/* Nec vendor-specific command completion event. */
1407#define TRB_NEC_CMD_COMP 48
1408/* Get NEC firmware revision. */
1409#define TRB_NEC_GET_FW 49
1410
1411static inline const char *xhci_trb_type_string(u8 type)
1412{
1413 switch (type) {
1414 case TRB_NORMAL:
1415 return "Normal";
1416 case TRB_SETUP:
1417 return "Setup Stage";
1418 case TRB_DATA:
1419 return "Data Stage";
1420 case TRB_STATUS:
1421 return "Status Stage";
1422 case TRB_ISOC:
1423 return "Isoch";
1424 case TRB_LINK:
1425 return "Link";
1426 case TRB_EVENT_DATA:
1427 return "Event Data";
1428 case TRB_TR_NOOP:
1429 return "No-Op";
1430 case TRB_ENABLE_SLOT:
1431 return "Enable Slot Command";
1432 case TRB_DISABLE_SLOT:
1433 return "Disable Slot Command";
1434 case TRB_ADDR_DEV:
1435 return "Address Device Command";
1436 case TRB_CONFIG_EP:
1437 return "Configure Endpoint Command";
1438 case TRB_EVAL_CONTEXT:
1439 return "Evaluate Context Command";
1440 case TRB_RESET_EP:
1441 return "Reset Endpoint Command";
1442 case TRB_STOP_RING:
1443 return "Stop Ring Command";
1444 case TRB_SET_DEQ:
1445 return "Set TR Dequeue Pointer Command";
1446 case TRB_RESET_DEV:
1447 return "Reset Device Command";
1448 case TRB_FORCE_EVENT:
1449 return "Force Event Command";
1450 case TRB_NEG_BANDWIDTH:
1451 return "Negotiate Bandwidth Command";
1452 case TRB_SET_LT:
1453 return "Set Latency Tolerance Value Command";
1454 case TRB_GET_BW:
1455 return "Get Port Bandwidth Command";
1456 case TRB_FORCE_HEADER:
1457 return "Force Header Command";
1458 case TRB_CMD_NOOP:
1459 return "No-Op Command";
1460 case TRB_TRANSFER:
1461 return "Transfer Event";
1462 case TRB_COMPLETION:
1463 return "Command Completion Event";
1464 case TRB_PORT_STATUS:
1465 return "Port Status Change Event";
1466 case TRB_BANDWIDTH_EVENT:
1467 return "Bandwidth Request Event";
1468 case TRB_DOORBELL:
1469 return "Doorbell Event";
1470 case TRB_HC_EVENT:
1471 return "Host Controller Event";
1472 case TRB_DEV_NOTE:
1473 return "Device Notification Event";
1474 case TRB_MFINDEX_WRAP:
1475 return "MFINDEX Wrap Event";
1476 case TRB_NEC_CMD_COMP:
1477 return "NEC Command Completion Event";
1478 case TRB_NEC_GET_FW:
1479 return "NET Get Firmware Revision Command";
1480 default:
1481 return "UNKNOWN";
1482 }
1483}
1484
1485#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1486/* Above, but for __le32 types -- can avoid work by swapping constants: */
1487#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1488 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1489#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1490 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1491
1492#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1493#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1494
1495/*
1496 * TRBS_PER_SEGMENT must be a multiple of 4,
1497 * since the command ring is 64-byte aligned.
1498 * It must also be greater than 16.
1499 */
1500#define TRBS_PER_SEGMENT 256
1501/* Allow two commands + a link TRB, along with any reserved command TRBs */
1502#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1503#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1504#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1505/* TRB buffer pointers can't cross 64KB boundaries */
1506#define TRB_MAX_BUFF_SHIFT 16
1507#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1508/* How much data is left before the 64KB boundary? */
1509#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1510 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1511#define MAX_SOFT_RETRY 3
1512/*
1513 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1514 * XHCI_AVOID_BEI quirk is in use.
1515 */
1516#define AVOID_BEI_INTERVAL_MIN 8
1517#define AVOID_BEI_INTERVAL_MAX 32
1518
1519struct xhci_segment {
1520 union xhci_trb *trbs;
1521 /* private to HCD */
1522 struct xhci_segment *next;
1523 unsigned int num;
1524 dma_addr_t dma;
1525 /* Max packet sized bounce buffer for td-fragmant alignment */
1526 dma_addr_t bounce_dma;
1527 void *bounce_buf;
1528 unsigned int bounce_offs;
1529 unsigned int bounce_len;
1530};
1531
1532enum xhci_cancelled_td_status {
1533 TD_DIRTY = 0,
1534 TD_HALTED,
1535 TD_CLEARING_CACHE,
1536 TD_CLEARED,
1537};
1538
1539struct xhci_td {
1540 struct list_head td_list;
1541 struct list_head cancelled_td_list;
1542 int status;
1543 enum xhci_cancelled_td_status cancel_status;
1544 struct urb *urb;
1545 struct xhci_segment *start_seg;
1546 union xhci_trb *first_trb;
1547 union xhci_trb *last_trb;
1548 struct xhci_segment *last_trb_seg;
1549 struct xhci_segment *bounce_seg;
1550 /* actual_length of the URB has already been set */
1551 bool urb_length_set;
1552 bool error_mid_td;
1553 unsigned int num_trbs;
1554};
1555
1556/*
1557 * xHCI command default timeout value in milliseconds.
1558 * USB 3.2 spec, section 9.2.6.1
1559 */
1560#define XHCI_CMD_DEFAULT_TIMEOUT 5000
1561
1562/* command descriptor */
1563struct xhci_cd {
1564 struct xhci_command *command;
1565 union xhci_trb *cmd_trb;
1566};
1567
1568enum xhci_ring_type {
1569 TYPE_CTRL = 0,
1570 TYPE_ISOC,
1571 TYPE_BULK,
1572 TYPE_INTR,
1573 TYPE_STREAM,
1574 TYPE_COMMAND,
1575 TYPE_EVENT,
1576};
1577
1578static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1579{
1580 switch (type) {
1581 case TYPE_CTRL:
1582 return "CTRL";
1583 case TYPE_ISOC:
1584 return "ISOC";
1585 case TYPE_BULK:
1586 return "BULK";
1587 case TYPE_INTR:
1588 return "INTR";
1589 case TYPE_STREAM:
1590 return "STREAM";
1591 case TYPE_COMMAND:
1592 return "CMD";
1593 case TYPE_EVENT:
1594 return "EVENT";
1595 }
1596
1597 return "UNKNOWN";
1598}
1599
1600struct xhci_ring {
1601 struct xhci_segment *first_seg;
1602 struct xhci_segment *last_seg;
1603 union xhci_trb *enqueue;
1604 struct xhci_segment *enq_seg;
1605 union xhci_trb *dequeue;
1606 struct xhci_segment *deq_seg;
1607 struct list_head td_list;
1608 /*
1609 * Write the cycle state into the TRB cycle field to give ownership of
1610 * the TRB to the host controller (if we are the producer), or to check
1611 * if we own the TRB (if we are the consumer). See section 4.9.1.
1612 */
1613 u32 cycle_state;
1614 unsigned int stream_id;
1615 unsigned int num_segs;
1616 unsigned int num_trbs_free; /* used only by xhci DbC */
1617 unsigned int bounce_buf_len;
1618 enum xhci_ring_type type;
1619 bool last_td_was_short;
1620 struct radix_tree_root *trb_address_map;
1621};
1622
1623struct xhci_erst_entry {
1624 /* 64-bit event ring segment address */
1625 __le64 seg_addr;
1626 __le32 seg_size;
1627 /* Set to zero */
1628 __le32 rsvd;
1629};
1630
1631struct xhci_erst {
1632 struct xhci_erst_entry *entries;
1633 unsigned int num_entries;
1634 /* xhci->event_ring keeps track of segment dma addresses */
1635 dma_addr_t erst_dma_addr;
1636 /* Num entries the ERST can contain */
1637 unsigned int erst_size;
1638};
1639
1640struct xhci_scratchpad {
1641 u64 *sp_array;
1642 dma_addr_t sp_dma;
1643 void **sp_buffers;
1644};
1645
1646struct urb_priv {
1647 int num_tds;
1648 int num_tds_done;
1649 struct xhci_td td[] __counted_by(num_tds);
1650};
1651
1652/* Reasonable limit for number of Event Ring segments (spec allows 32k) */
1653#define ERST_MAX_SEGS 2
1654/* Poll every 60 seconds */
1655#define POLL_TIMEOUT 60
1656/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1657#define XHCI_STOP_EP_CMD_TIMEOUT 5
1658/* XXX: Make these module parameters */
1659
1660struct s3_save {
1661 u32 command;
1662 u32 dev_nt;
1663 u64 dcbaa_ptr;
1664 u32 config_reg;
1665};
1666
1667/* Use for lpm */
1668struct dev_info {
1669 u32 dev_id;
1670 struct list_head list;
1671};
1672
1673struct xhci_bus_state {
1674 unsigned long bus_suspended;
1675 unsigned long next_statechange;
1676
1677 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1678 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1679 u32 port_c_suspend;
1680 u32 suspended_ports;
1681 u32 port_remote_wakeup;
1682 /* which ports have started to resume */
1683 unsigned long resuming_ports;
1684};
1685
1686struct xhci_interrupter {
1687 struct xhci_ring *event_ring;
1688 struct xhci_erst erst;
1689 struct xhci_intr_reg __iomem *ir_set;
1690 unsigned int intr_num;
1691 /* For interrupter registers save and restore over suspend/resume */
1692 u32 s3_irq_pending;
1693 u32 s3_irq_control;
1694 u32 s3_erst_size;
1695 u64 s3_erst_base;
1696 u64 s3_erst_dequeue;
1697};
1698/*
1699 * It can take up to 20 ms to transition from RExit to U0 on the
1700 * Intel Lynx Point LP xHCI host.
1701 */
1702#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1703struct xhci_port_cap {
1704 u32 *psi; /* array of protocol speed ID entries */
1705 u8 psi_count;
1706 u8 psi_uid_count;
1707 u8 maj_rev;
1708 u8 min_rev;
1709};
1710
1711struct xhci_port {
1712 __le32 __iomem *addr;
1713 int hw_portnum;
1714 int hcd_portnum;
1715 struct xhci_hub *rhub;
1716 struct xhci_port_cap *port_cap;
1717 unsigned int lpm_incapable:1;
1718 unsigned long resume_timestamp;
1719 bool rexit_active;
1720 struct completion rexit_done;
1721 struct completion u3exit_done;
1722};
1723
1724struct xhci_hub {
1725 struct xhci_port **ports;
1726 unsigned int num_ports;
1727 struct usb_hcd *hcd;
1728 /* keep track of bus suspend info */
1729 struct xhci_bus_state bus_state;
1730 /* supported prococol extended capabiliy values */
1731 u8 maj_rev;
1732 u8 min_rev;
1733};
1734
1735/* There is one xhci_hcd structure per controller */
1736struct xhci_hcd {
1737 struct usb_hcd *main_hcd;
1738 struct usb_hcd *shared_hcd;
1739 /* glue to PCI and HCD framework */
1740 struct xhci_cap_regs __iomem *cap_regs;
1741 struct xhci_op_regs __iomem *op_regs;
1742 struct xhci_run_regs __iomem *run_regs;
1743 struct xhci_doorbell_array __iomem *dba;
1744
1745 /* Cached register copies of read-only HC data */
1746 __u32 hcs_params1;
1747 __u32 hcs_params2;
1748 __u32 hcs_params3;
1749 __u32 hcc_params;
1750 __u32 hcc_params2;
1751
1752 spinlock_t lock;
1753
1754 /* packed release number */
1755 u8 sbrn;
1756 u16 hci_version;
1757 u8 max_slots;
1758 u16 max_interrupters;
1759 u8 max_ports;
1760 u8 isoc_threshold;
1761 /* imod_interval in ns (I * 250ns) */
1762 u32 imod_interval;
1763 u32 isoc_bei_interval;
1764 int event_ring_max;
1765 /* 4KB min, 128MB max */
1766 int page_size;
1767 /* Valid values are 12 to 20, inclusive */
1768 int page_shift;
1769 /* MSI-X/MSI vectors */
1770 int nvecs;
1771 /* optional clocks */
1772 struct clk *clk;
1773 struct clk *reg_clk;
1774 /* optional reset controller */
1775 struct reset_control *reset;
1776 /* data structures */
1777 struct xhci_device_context_array *dcbaa;
1778 struct xhci_interrupter **interrupters;
1779 struct xhci_ring *cmd_ring;
1780 unsigned int cmd_ring_state;
1781#define CMD_RING_STATE_RUNNING (1 << 0)
1782#define CMD_RING_STATE_ABORTED (1 << 1)
1783#define CMD_RING_STATE_STOPPED (1 << 2)
1784 struct list_head cmd_list;
1785 unsigned int cmd_ring_reserved_trbs;
1786 struct delayed_work cmd_timer;
1787 struct completion cmd_ring_stop_completion;
1788 struct xhci_command *current_cmd;
1789
1790 /* Scratchpad */
1791 struct xhci_scratchpad *scratchpad;
1792
1793 /* slot enabling and address device helpers */
1794 /* these are not thread safe so use mutex */
1795 struct mutex mutex;
1796 /* Internal mirror of the HW's dcbaa */
1797 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1798 /* For keeping track of bandwidth domains per roothub. */
1799 struct xhci_root_port_bw_info *rh_bw;
1800
1801 /* DMA pools */
1802 struct dma_pool *device_pool;
1803 struct dma_pool *segment_pool;
1804 struct dma_pool *small_streams_pool;
1805 struct dma_pool *medium_streams_pool;
1806
1807 /* Host controller watchdog timer structures */
1808 unsigned int xhc_state;
1809 unsigned long run_graceperiod;
1810 struct s3_save s3;
1811/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1812 *
1813 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1814 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1815 * that sees this status (other than the timer that set it) should stop touching
1816 * hardware immediately. Interrupt handlers should return immediately when
1817 * they see this status (any time they drop and re-acquire xhci->lock).
1818 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1819 * putting the TD on the canceled list, etc.
1820 *
1821 * There are no reports of xHCI host controllers that display this issue.
1822 */
1823#define XHCI_STATE_DYING (1 << 0)
1824#define XHCI_STATE_HALTED (1 << 1)
1825#define XHCI_STATE_REMOVING (1 << 2)
1826 unsigned long long quirks;
1827#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1828#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1829#define XHCI_NEC_HOST BIT_ULL(2)
1830#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1831#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1832/*
1833 * Certain Intel host controllers have a limit to the number of endpoint
1834 * contexts they can handle. Ideally, they would signal that they can't handle
1835 * anymore endpoint contexts by returning a Resource Error for the Configure
1836 * Endpoint command, but they don't. Instead they expect software to keep track
1837 * of the number of active endpoints for them, across configure endpoint
1838 * commands, reset device commands, disable slot commands, and address device
1839 * commands.
1840 */
1841#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1842#define XHCI_BROKEN_MSI BIT_ULL(6)
1843#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1844#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1845#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1846#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1847#define XHCI_LPM_SUPPORT BIT_ULL(11)
1848#define XHCI_INTEL_HOST BIT_ULL(12)
1849#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1850#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1851#define XHCI_AVOID_BEI BIT_ULL(15)
1852#define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1853#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1854#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1855/* For controllers with a broken beyond repair streams implementation */
1856#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1857#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1858#define XHCI_MTK_HOST BIT_ULL(21)
1859#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1860#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1861#define XHCI_MISSING_CAS BIT_ULL(24)
1862/* For controller with a broken Port Disable implementation */
1863#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1864#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1865#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1866#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1867#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1868#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1869#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1870#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1871#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1872#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1873#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1874#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1875#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1876#define XHCI_DISABLE_SPARSE BIT_ULL(38)
1877#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1878#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1879#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1880#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1881#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1882#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1883#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
1884#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1885
1886 unsigned int num_active_eps;
1887 unsigned int limit_active_eps;
1888 struct xhci_port *hw_ports;
1889 struct xhci_hub usb2_rhub;
1890 struct xhci_hub usb3_rhub;
1891 /* support xHCI 1.0 spec USB2 hardware LPM */
1892 unsigned hw_lpm_support:1;
1893 /* Broken Suspend flag for SNPS Suspend resume issue */
1894 unsigned broken_suspend:1;
1895 /* Indicates that omitting hcd is supported if root hub has no ports */
1896 unsigned allow_single_roothub:1;
1897 /* cached usb2 extened protocol capabilites */
1898 u32 *ext_caps;
1899 unsigned int num_ext_caps;
1900 /* cached extended protocol port capabilities */
1901 struct xhci_port_cap *port_caps;
1902 unsigned int num_port_caps;
1903 /* Compliance Mode Recovery Data */
1904 struct timer_list comp_mode_recovery_timer;
1905 u32 port_status_u0;
1906 u16 test_mode;
1907/* Compliance Mode Timer Triggered every 2 seconds */
1908#define COMP_MODE_RCVRY_MSECS 2000
1909
1910 struct dentry *debugfs_root;
1911 struct dentry *debugfs_slots;
1912 struct list_head regset_list;
1913
1914 void *dbc;
1915 /* platform-specific data -- must come last */
1916 unsigned long priv[] __aligned(sizeof(s64));
1917};
1918
1919/* Platform specific overrides to generic XHCI hc_driver ops */
1920struct xhci_driver_overrides {
1921 size_t extra_priv_size;
1922 int (*reset)(struct usb_hcd *hcd);
1923 int (*start)(struct usb_hcd *hcd);
1924 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1925 struct usb_host_endpoint *ep);
1926 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1927 struct usb_host_endpoint *ep);
1928 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1929 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1930 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1931 struct usb_tt *tt, gfp_t mem_flags);
1932 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1933 u16 wIndex, char *buf, u16 wLength);
1934};
1935
1936#define XHCI_CFC_DELAY 10
1937
1938/* convert between an HCD pointer and the corresponding EHCI_HCD */
1939static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1940{
1941 struct usb_hcd *primary_hcd;
1942
1943 if (usb_hcd_is_primary_hcd(hcd))
1944 primary_hcd = hcd;
1945 else
1946 primary_hcd = hcd->primary_hcd;
1947
1948 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1949}
1950
1951static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1952{
1953 return xhci->main_hcd;
1954}
1955
1956static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1957{
1958 if (xhci->shared_hcd)
1959 return xhci->shared_hcd;
1960
1961 if (!xhci->usb2_rhub.num_ports)
1962 return xhci->main_hcd;
1963
1964 return NULL;
1965}
1966
1967static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1968{
1969 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1970
1971 return hcd == xhci_get_usb3_hcd(xhci);
1972}
1973
1974static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1975{
1976 return xhci->allow_single_roothub &&
1977 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1978}
1979
1980#define xhci_dbg(xhci, fmt, args...) \
1981 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1982#define xhci_err(xhci, fmt, args...) \
1983 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1984#define xhci_warn(xhci, fmt, args...) \
1985 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1986#define xhci_warn_ratelimited(xhci, fmt, args...) \
1987 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1988#define xhci_info(xhci, fmt, args...) \
1989 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1990
1991/*
1992 * Registers should always be accessed with double word or quad word accesses.
1993 *
1994 * Some xHCI implementations may support 64-bit address pointers. Registers
1995 * with 64-bit address pointers should be written to with dword accesses by
1996 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1997 * xHCI implementations that do not support 64-bit address pointers will ignore
1998 * the high dword, and write order is irrelevant.
1999 */
2000static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
2001 __le64 __iomem *regs)
2002{
2003 return lo_hi_readq(regs);
2004}
2005static inline void xhci_write_64(struct xhci_hcd *xhci,
2006 const u64 val, __le64 __iomem *regs)
2007{
2008 lo_hi_writeq(val, regs);
2009}
2010
2011static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
2012{
2013 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
2014}
2015
2016/* xHCI debugging */
2017char *xhci_get_slot_state(struct xhci_hcd *xhci,
2018 struct xhci_container_ctx *ctx);
2019void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
2020 const char *fmt, ...);
2021
2022/* xHCI memory management */
2023void xhci_mem_cleanup(struct xhci_hcd *xhci);
2024int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
2025void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
2026int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
2027int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2028void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
2029 struct usb_device *udev);
2030unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
2031unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
2032void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2033void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2034 struct xhci_virt_device *virt_dev,
2035 int old_active_eps);
2036void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2037void xhci_update_bw_info(struct xhci_hcd *xhci,
2038 struct xhci_container_ctx *in_ctx,
2039 struct xhci_input_control_ctx *ctrl_ctx,
2040 struct xhci_virt_device *virt_dev);
2041void xhci_endpoint_copy(struct xhci_hcd *xhci,
2042 struct xhci_container_ctx *in_ctx,
2043 struct xhci_container_ctx *out_ctx,
2044 unsigned int ep_index);
2045void xhci_slot_copy(struct xhci_hcd *xhci,
2046 struct xhci_container_ctx *in_ctx,
2047 struct xhci_container_ctx *out_ctx);
2048int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2049 struct usb_device *udev, struct usb_host_endpoint *ep,
2050 gfp_t mem_flags);
2051struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2052 unsigned int num_segs, unsigned int cycle_state,
2053 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2054void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2055int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2056 unsigned int num_trbs, gfp_t flags);
2057void xhci_initialize_ring_info(struct xhci_ring *ring,
2058 unsigned int cycle_state);
2059void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2060 struct xhci_virt_device *virt_dev,
2061 unsigned int ep_index);
2062struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2063 unsigned int num_stream_ctxs,
2064 unsigned int num_streams,
2065 unsigned int max_packet, gfp_t flags);
2066void xhci_free_stream_info(struct xhci_hcd *xhci,
2067 struct xhci_stream_info *stream_info);
2068void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2069 struct xhci_ep_ctx *ep_ctx,
2070 struct xhci_stream_info *stream_info);
2071void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2072 struct xhci_virt_ep *ep);
2073void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2074 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2075struct xhci_ring *xhci_dma_to_transfer_ring(
2076 struct xhci_virt_ep *ep,
2077 u64 address);
2078struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2079 bool allocate_completion, gfp_t mem_flags);
2080struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2081 bool allocate_completion, gfp_t mem_flags);
2082void xhci_urb_free_priv(struct urb_priv *urb_priv);
2083void xhci_free_command(struct xhci_hcd *xhci,
2084 struct xhci_command *command);
2085struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2086 int type, gfp_t flags);
2087void xhci_free_container_ctx(struct xhci_hcd *xhci,
2088 struct xhci_container_ctx *ctx);
2089struct xhci_interrupter *
2090xhci_create_secondary_interrupter(struct usb_hcd *hcd, int num_seg);
2091void xhci_remove_secondary_interrupter(struct usb_hcd
2092 *hcd, struct xhci_interrupter *ir);
2093
2094/* xHCI host controller glue */
2095typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2096int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
2097int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
2098 u32 mask, u32 done, int usec, unsigned int exit_state);
2099void xhci_quiesce(struct xhci_hcd *xhci);
2100int xhci_halt(struct xhci_hcd *xhci);
2101int xhci_start(struct xhci_hcd *xhci);
2102int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
2103int xhci_run(struct usb_hcd *hcd);
2104int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2105void xhci_shutdown(struct usb_hcd *hcd);
2106void xhci_stop(struct usb_hcd *hcd);
2107void xhci_init_driver(struct hc_driver *drv,
2108 const struct xhci_driver_overrides *over);
2109int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2110 struct usb_host_endpoint *ep);
2111int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2112 struct usb_host_endpoint *ep);
2113int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2114void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2115int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
2116 struct usb_tt *tt, gfp_t mem_flags);
2117int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2118int xhci_ext_cap_init(struct xhci_hcd *xhci);
2119
2120int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2121int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
2122
2123irqreturn_t xhci_irq(struct usb_hcd *hcd);
2124irqreturn_t xhci_msi_irq(int irq, void *hcd);
2125int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2126int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2127 struct xhci_virt_device *virt_dev,
2128 struct usb_device *hdev,
2129 struct usb_tt *tt, gfp_t mem_flags);
2130
2131/* xHCI ring, segment, TRB, and TD functions */
2132dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2133struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2134 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2135 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2136int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2137void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2138int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2139 u32 trb_type, u32 slot_id);
2140int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2141 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2142int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2143 u32 field1, u32 field2, u32 field3, u32 field4);
2144int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2145 int slot_id, unsigned int ep_index, int suspend);
2146int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2147 int slot_id, unsigned int ep_index);
2148int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2149 int slot_id, unsigned int ep_index);
2150int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2151 int slot_id, unsigned int ep_index);
2152int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2153 struct urb *urb, int slot_id, unsigned int ep_index);
2154int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2155 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2156 bool command_must_succeed);
2157int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2158 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2159int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2160 int slot_id, unsigned int ep_index,
2161 enum xhci_ep_reset_type reset_type);
2162int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2163 u32 slot_id);
2164void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2165 unsigned int ep_index, unsigned int stream_id,
2166 struct xhci_td *td);
2167void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2168void xhci_handle_command_timeout(struct work_struct *work);
2169
2170void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2171 unsigned int ep_index, unsigned int stream_id);
2172void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2173 unsigned int slot_id,
2174 unsigned int ep_index);
2175void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2176void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2177unsigned int count_trbs(u64 addr, u64 len);
2178
2179/* xHCI roothub code */
2180void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2181 u32 link_state);
2182void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2183 u32 port_bit);
2184int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2185 char *buf, u16 wLength);
2186int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2187int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2188struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2189
2190void xhci_hc_died(struct xhci_hcd *xhci);
2191
2192#ifdef CONFIG_PM
2193int xhci_bus_suspend(struct usb_hcd *hcd);
2194int xhci_bus_resume(struct usb_hcd *hcd);
2195unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2196#else
2197#define xhci_bus_suspend NULL
2198#define xhci_bus_resume NULL
2199#define xhci_get_resuming_ports NULL
2200#endif /* CONFIG_PM */
2201
2202u32 xhci_port_state_to_neutral(u32 state);
2203int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2204 u16 port);
2205void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2206
2207/* xHCI contexts */
2208struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2209struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2210struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2211
2212struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2213 unsigned int slot_id, unsigned int ep_index,
2214 unsigned int stream_id);
2215
2216static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2217 struct urb *urb)
2218{
2219 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2220 xhci_get_endpoint_index(&urb->ep->desc),
2221 urb->stream_id);
2222}
2223
2224/*
2225 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2226 * them anyways as we where unable to find a device that matches the
2227 * constraints.
2228 */
2229static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2230{
2231 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2232 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2233 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2234 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2235 !urb->num_sgs)
2236 return true;
2237
2238 return false;
2239}
2240
2241static inline char *xhci_slot_state_string(u32 state)
2242{
2243 switch (state) {
2244 case SLOT_STATE_ENABLED:
2245 return "enabled/disabled";
2246 case SLOT_STATE_DEFAULT:
2247 return "default";
2248 case SLOT_STATE_ADDRESSED:
2249 return "addressed";
2250 case SLOT_STATE_CONFIGURED:
2251 return "configured";
2252 default:
2253 return "reserved";
2254 }
2255}
2256
2257static inline const char *xhci_decode_trb(char *str, size_t size,
2258 u32 field0, u32 field1, u32 field2, u32 field3)
2259{
2260 int type = TRB_FIELD_TO_TYPE(field3);
2261
2262 switch (type) {
2263 case TRB_LINK:
2264 snprintf(str, size,
2265 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2266 field1, field0, GET_INTR_TARGET(field2),
2267 xhci_trb_type_string(type),
2268 field3 & TRB_IOC ? 'I' : 'i',
2269 field3 & TRB_CHAIN ? 'C' : 'c',
2270 field3 & TRB_TC ? 'T' : 't',
2271 field3 & TRB_CYCLE ? 'C' : 'c');
2272 break;
2273 case TRB_TRANSFER:
2274 case TRB_COMPLETION:
2275 case TRB_PORT_STATUS:
2276 case TRB_BANDWIDTH_EVENT:
2277 case TRB_DOORBELL:
2278 case TRB_HC_EVENT:
2279 case TRB_DEV_NOTE:
2280 case TRB_MFINDEX_WRAP:
2281 snprintf(str, size,
2282 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2283 field1, field0,
2284 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2285 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2286 /* Macro decrements 1, maybe it shouldn't?!? */
2287 TRB_TO_EP_INDEX(field3) + 1,
2288 xhci_trb_type_string(type),
2289 field3 & EVENT_DATA ? 'E' : 'e',
2290 field3 & TRB_CYCLE ? 'C' : 'c');
2291
2292 break;
2293 case TRB_SETUP:
2294 snprintf(str, size,
2295 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2296 field0 & 0xff,
2297 (field0 & 0xff00) >> 8,
2298 (field0 & 0xff000000) >> 24,
2299 (field0 & 0xff0000) >> 16,
2300 (field1 & 0xff00) >> 8,
2301 field1 & 0xff,
2302 (field1 & 0xff000000) >> 16 |
2303 (field1 & 0xff0000) >> 16,
2304 TRB_LEN(field2), GET_TD_SIZE(field2),
2305 GET_INTR_TARGET(field2),
2306 xhci_trb_type_string(type),
2307 field3 & TRB_IDT ? 'I' : 'i',
2308 field3 & TRB_IOC ? 'I' : 'i',
2309 field3 & TRB_CYCLE ? 'C' : 'c');
2310 break;
2311 case TRB_DATA:
2312 snprintf(str, size,
2313 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2314 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2315 GET_INTR_TARGET(field2),
2316 xhci_trb_type_string(type),
2317 field3 & TRB_IDT ? 'I' : 'i',
2318 field3 & TRB_IOC ? 'I' : 'i',
2319 field3 & TRB_CHAIN ? 'C' : 'c',
2320 field3 & TRB_NO_SNOOP ? 'S' : 's',
2321 field3 & TRB_ISP ? 'I' : 'i',
2322 field3 & TRB_ENT ? 'E' : 'e',
2323 field3 & TRB_CYCLE ? 'C' : 'c');
2324 break;
2325 case TRB_STATUS:
2326 snprintf(str, size,
2327 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2328 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2329 GET_INTR_TARGET(field2),
2330 xhci_trb_type_string(type),
2331 field3 & TRB_IOC ? 'I' : 'i',
2332 field3 & TRB_CHAIN ? 'C' : 'c',
2333 field3 & TRB_ENT ? 'E' : 'e',
2334 field3 & TRB_CYCLE ? 'C' : 'c');
2335 break;
2336 case TRB_NORMAL:
2337 case TRB_ISOC:
2338 case TRB_EVENT_DATA:
2339 case TRB_TR_NOOP:
2340 snprintf(str, size,
2341 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2342 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2343 GET_INTR_TARGET(field2),
2344 xhci_trb_type_string(type),
2345 field3 & TRB_BEI ? 'B' : 'b',
2346 field3 & TRB_IDT ? 'I' : 'i',
2347 field3 & TRB_IOC ? 'I' : 'i',
2348 field3 & TRB_CHAIN ? 'C' : 'c',
2349 field3 & TRB_NO_SNOOP ? 'S' : 's',
2350 field3 & TRB_ISP ? 'I' : 'i',
2351 field3 & TRB_ENT ? 'E' : 'e',
2352 field3 & TRB_CYCLE ? 'C' : 'c');
2353 break;
2354
2355 case TRB_CMD_NOOP:
2356 case TRB_ENABLE_SLOT:
2357 snprintf(str, size,
2358 "%s: flags %c",
2359 xhci_trb_type_string(type),
2360 field3 & TRB_CYCLE ? 'C' : 'c');
2361 break;
2362 case TRB_DISABLE_SLOT:
2363 case TRB_NEG_BANDWIDTH:
2364 snprintf(str, size,
2365 "%s: slot %d flags %c",
2366 xhci_trb_type_string(type),
2367 TRB_TO_SLOT_ID(field3),
2368 field3 & TRB_CYCLE ? 'C' : 'c');
2369 break;
2370 case TRB_ADDR_DEV:
2371 snprintf(str, size,
2372 "%s: ctx %08x%08x slot %d flags %c:%c",
2373 xhci_trb_type_string(type),
2374 field1, field0,
2375 TRB_TO_SLOT_ID(field3),
2376 field3 & TRB_BSR ? 'B' : 'b',
2377 field3 & TRB_CYCLE ? 'C' : 'c');
2378 break;
2379 case TRB_CONFIG_EP:
2380 snprintf(str, size,
2381 "%s: ctx %08x%08x slot %d flags %c:%c",
2382 xhci_trb_type_string(type),
2383 field1, field0,
2384 TRB_TO_SLOT_ID(field3),
2385 field3 & TRB_DC ? 'D' : 'd',
2386 field3 & TRB_CYCLE ? 'C' : 'c');
2387 break;
2388 case TRB_EVAL_CONTEXT:
2389 snprintf(str, size,
2390 "%s: ctx %08x%08x slot %d flags %c",
2391 xhci_trb_type_string(type),
2392 field1, field0,
2393 TRB_TO_SLOT_ID(field3),
2394 field3 & TRB_CYCLE ? 'C' : 'c');
2395 break;
2396 case TRB_RESET_EP:
2397 snprintf(str, size,
2398 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2399 xhci_trb_type_string(type),
2400 field1, field0,
2401 TRB_TO_SLOT_ID(field3),
2402 /* Macro decrements 1, maybe it shouldn't?!? */
2403 TRB_TO_EP_INDEX(field3) + 1,
2404 field3 & TRB_TSP ? 'T' : 't',
2405 field3 & TRB_CYCLE ? 'C' : 'c');
2406 break;
2407 case TRB_STOP_RING:
2408 snprintf(str, size,
2409 "%s: slot %d sp %d ep %d flags %c",
2410 xhci_trb_type_string(type),
2411 TRB_TO_SLOT_ID(field3),
2412 TRB_TO_SUSPEND_PORT(field3),
2413 /* Macro decrements 1, maybe it shouldn't?!? */
2414 TRB_TO_EP_INDEX(field3) + 1,
2415 field3 & TRB_CYCLE ? 'C' : 'c');
2416 break;
2417 case TRB_SET_DEQ:
2418 snprintf(str, size,
2419 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2420 xhci_trb_type_string(type),
2421 field1, field0,
2422 TRB_TO_STREAM_ID(field2),
2423 TRB_TO_SLOT_ID(field3),
2424 /* Macro decrements 1, maybe it shouldn't?!? */
2425 TRB_TO_EP_INDEX(field3) + 1,
2426 field3 & TRB_CYCLE ? 'C' : 'c');
2427 break;
2428 case TRB_RESET_DEV:
2429 snprintf(str, size,
2430 "%s: slot %d flags %c",
2431 xhci_trb_type_string(type),
2432 TRB_TO_SLOT_ID(field3),
2433 field3 & TRB_CYCLE ? 'C' : 'c');
2434 break;
2435 case TRB_FORCE_EVENT:
2436 snprintf(str, size,
2437 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2438 xhci_trb_type_string(type),
2439 field1, field0,
2440 TRB_TO_VF_INTR_TARGET(field2),
2441 TRB_TO_VF_ID(field3),
2442 field3 & TRB_CYCLE ? 'C' : 'c');
2443 break;
2444 case TRB_SET_LT:
2445 snprintf(str, size,
2446 "%s: belt %d flags %c",
2447 xhci_trb_type_string(type),
2448 TRB_TO_BELT(field3),
2449 field3 & TRB_CYCLE ? 'C' : 'c');
2450 break;
2451 case TRB_GET_BW:
2452 snprintf(str, size,
2453 "%s: ctx %08x%08x slot %d speed %d flags %c",
2454 xhci_trb_type_string(type),
2455 field1, field0,
2456 TRB_TO_SLOT_ID(field3),
2457 TRB_TO_DEV_SPEED(field3),
2458 field3 & TRB_CYCLE ? 'C' : 'c');
2459 break;
2460 case TRB_FORCE_HEADER:
2461 snprintf(str, size,
2462 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2463 xhci_trb_type_string(type),
2464 field2, field1, field0 & 0xffffffe0,
2465 TRB_TO_PACKET_TYPE(field0),
2466 TRB_TO_ROOTHUB_PORT(field3),
2467 field3 & TRB_CYCLE ? 'C' : 'c');
2468 break;
2469 default:
2470 snprintf(str, size,
2471 "type '%s' -> raw %08x %08x %08x %08x",
2472 xhci_trb_type_string(type),
2473 field0, field1, field2, field3);
2474 }
2475
2476 return str;
2477}
2478
2479static inline const char *xhci_decode_ctrl_ctx(char *str,
2480 unsigned long drop, unsigned long add)
2481{
2482 unsigned int bit;
2483 int ret = 0;
2484
2485 str[0] = '\0';
2486
2487 if (drop) {
2488 ret = sprintf(str, "Drop:");
2489 for_each_set_bit(bit, &drop, 32)
2490 ret += sprintf(str + ret, " %d%s",
2491 bit / 2,
2492 bit % 2 ? "in":"out");
2493 ret += sprintf(str + ret, ", ");
2494 }
2495
2496 if (add) {
2497 ret += sprintf(str + ret, "Add:%s%s",
2498 (add & SLOT_FLAG) ? " slot":"",
2499 (add & EP0_FLAG) ? " ep0":"");
2500 add &= ~(SLOT_FLAG | EP0_FLAG);
2501 for_each_set_bit(bit, &add, 32)
2502 ret += sprintf(str + ret, " %d%s",
2503 bit / 2,
2504 bit % 2 ? "in":"out");
2505 }
2506 return str;
2507}
2508
2509static inline const char *xhci_decode_slot_context(char *str,
2510 u32 info, u32 info2, u32 tt_info, u32 state)
2511{
2512 u32 speed;
2513 u32 hub;
2514 u32 mtt;
2515 int ret = 0;
2516
2517 speed = info & DEV_SPEED;
2518 hub = info & DEV_HUB;
2519 mtt = info & DEV_MTT;
2520
2521 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2522 info & ROUTE_STRING_MASK,
2523 ({ char *s;
2524 switch (speed) {
2525 case SLOT_SPEED_FS:
2526 s = "full-speed";
2527 break;
2528 case SLOT_SPEED_LS:
2529 s = "low-speed";
2530 break;
2531 case SLOT_SPEED_HS:
2532 s = "high-speed";
2533 break;
2534 case SLOT_SPEED_SS:
2535 s = "super-speed";
2536 break;
2537 case SLOT_SPEED_SSP:
2538 s = "super-speed plus";
2539 break;
2540 default:
2541 s = "UNKNOWN speed";
2542 } s; }),
2543 mtt ? " multi-TT" : "",
2544 hub ? " Hub" : "",
2545 (info & LAST_CTX_MASK) >> 27,
2546 info2 & MAX_EXIT,
2547 DEVINFO_TO_ROOT_HUB_PORT(info2),
2548 DEVINFO_TO_MAX_PORTS(info2));
2549
2550 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2551 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2552 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2553 state & DEV_ADDR_MASK,
2554 xhci_slot_state_string(GET_SLOT_STATE(state)));
2555
2556 return str;
2557}
2558
2559
2560static inline const char *xhci_portsc_link_state_string(u32 portsc)
2561{
2562 switch (portsc & PORT_PLS_MASK) {
2563 case XDEV_U0:
2564 return "U0";
2565 case XDEV_U1:
2566 return "U1";
2567 case XDEV_U2:
2568 return "U2";
2569 case XDEV_U3:
2570 return "U3";
2571 case XDEV_DISABLED:
2572 return "Disabled";
2573 case XDEV_RXDETECT:
2574 return "RxDetect";
2575 case XDEV_INACTIVE:
2576 return "Inactive";
2577 case XDEV_POLLING:
2578 return "Polling";
2579 case XDEV_RECOVERY:
2580 return "Recovery";
2581 case XDEV_HOT_RESET:
2582 return "Hot Reset";
2583 case XDEV_COMP_MODE:
2584 return "Compliance mode";
2585 case XDEV_TEST_MODE:
2586 return "Test mode";
2587 case XDEV_RESUME:
2588 return "Resume";
2589 default:
2590 break;
2591 }
2592 return "Unknown";
2593}
2594
2595static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2596{
2597 int ret;
2598
2599 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2600 portsc & PORT_POWER ? "Powered" : "Powered-off",
2601 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2602 portsc & PORT_PE ? "Enabled" : "Disabled",
2603 xhci_portsc_link_state_string(portsc),
2604 DEV_PORT_SPEED(portsc));
2605
2606 if (portsc & PORT_OC)
2607 ret += sprintf(str + ret, "OverCurrent ");
2608 if (portsc & PORT_RESET)
2609 ret += sprintf(str + ret, "In-Reset ");
2610
2611 ret += sprintf(str + ret, "Change: ");
2612 if (portsc & PORT_CSC)
2613 ret += sprintf(str + ret, "CSC ");
2614 if (portsc & PORT_PEC)
2615 ret += sprintf(str + ret, "PEC ");
2616 if (portsc & PORT_WRC)
2617 ret += sprintf(str + ret, "WRC ");
2618 if (portsc & PORT_OCC)
2619 ret += sprintf(str + ret, "OCC ");
2620 if (portsc & PORT_RC)
2621 ret += sprintf(str + ret, "PRC ");
2622 if (portsc & PORT_PLC)
2623 ret += sprintf(str + ret, "PLC ");
2624 if (portsc & PORT_CEC)
2625 ret += sprintf(str + ret, "CEC ");
2626 if (portsc & PORT_CAS)
2627 ret += sprintf(str + ret, "CAS ");
2628
2629 ret += sprintf(str + ret, "Wake: ");
2630 if (portsc & PORT_WKCONN_E)
2631 ret += sprintf(str + ret, "WCE ");
2632 if (portsc & PORT_WKDISC_E)
2633 ret += sprintf(str + ret, "WDE ");
2634 if (portsc & PORT_WKOC_E)
2635 ret += sprintf(str + ret, "WOE ");
2636
2637 return str;
2638}
2639
2640static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2641{
2642 int ret = 0;
2643
2644 ret = sprintf(str, " 0x%08x", usbsts);
2645
2646 if (usbsts == ~(u32)0)
2647 return str;
2648
2649 if (usbsts & STS_HALT)
2650 ret += sprintf(str + ret, " HCHalted");
2651 if (usbsts & STS_FATAL)
2652 ret += sprintf(str + ret, " HSE");
2653 if (usbsts & STS_EINT)
2654 ret += sprintf(str + ret, " EINT");
2655 if (usbsts & STS_PORT)
2656 ret += sprintf(str + ret, " PCD");
2657 if (usbsts & STS_SAVE)
2658 ret += sprintf(str + ret, " SSS");
2659 if (usbsts & STS_RESTORE)
2660 ret += sprintf(str + ret, " RSS");
2661 if (usbsts & STS_SRE)
2662 ret += sprintf(str + ret, " SRE");
2663 if (usbsts & STS_CNR)
2664 ret += sprintf(str + ret, " CNR");
2665 if (usbsts & STS_HCE)
2666 ret += sprintf(str + ret, " HCE");
2667
2668 return str;
2669}
2670
2671static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2672{
2673 u8 ep;
2674 u16 stream;
2675 int ret;
2676
2677 ep = (doorbell & 0xff);
2678 stream = doorbell >> 16;
2679
2680 if (slot == 0) {
2681 sprintf(str, "Command Ring %d", doorbell);
2682 return str;
2683 }
2684 ret = sprintf(str, "Slot %d ", slot);
2685 if (ep > 0 && ep < 32)
2686 ret = sprintf(str + ret, "ep%d%s",
2687 ep / 2,
2688 ep % 2 ? "in" : "out");
2689 else if (ep == 0 || ep < 248)
2690 ret = sprintf(str + ret, "Reserved %d", ep);
2691 else
2692 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2693 if (stream)
2694 ret = sprintf(str + ret, " Stream %d", stream);
2695
2696 return str;
2697}
2698
2699static inline const char *xhci_ep_state_string(u8 state)
2700{
2701 switch (state) {
2702 case EP_STATE_DISABLED:
2703 return "disabled";
2704 case EP_STATE_RUNNING:
2705 return "running";
2706 case EP_STATE_HALTED:
2707 return "halted";
2708 case EP_STATE_STOPPED:
2709 return "stopped";
2710 case EP_STATE_ERROR:
2711 return "error";
2712 default:
2713 return "INVALID";
2714 }
2715}
2716
2717static inline const char *xhci_ep_type_string(u8 type)
2718{
2719 switch (type) {
2720 case ISOC_OUT_EP:
2721 return "Isoc OUT";
2722 case BULK_OUT_EP:
2723 return "Bulk OUT";
2724 case INT_OUT_EP:
2725 return "Int OUT";
2726 case CTRL_EP:
2727 return "Ctrl";
2728 case ISOC_IN_EP:
2729 return "Isoc IN";
2730 case BULK_IN_EP:
2731 return "Bulk IN";
2732 case INT_IN_EP:
2733 return "Int IN";
2734 default:
2735 return "INVALID";
2736 }
2737}
2738
2739static inline const char *xhci_decode_ep_context(char *str, u32 info,
2740 u32 info2, u64 deq, u32 tx_info)
2741{
2742 int ret;
2743
2744 u32 esit;
2745 u16 maxp;
2746 u16 avg;
2747
2748 u8 max_pstr;
2749 u8 ep_state;
2750 u8 interval;
2751 u8 ep_type;
2752 u8 burst;
2753 u8 cerr;
2754 u8 mult;
2755
2756 bool lsa;
2757 bool hid;
2758
2759 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2760 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2761
2762 ep_state = info & EP_STATE_MASK;
2763 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2764 interval = CTX_TO_EP_INTERVAL(info);
2765 mult = CTX_TO_EP_MULT(info) + 1;
2766 lsa = !!(info & EP_HAS_LSA);
2767
2768 cerr = (info2 & (3 << 1)) >> 1;
2769 ep_type = CTX_TO_EP_TYPE(info2);
2770 hid = !!(info2 & (1 << 7));
2771 burst = CTX_TO_MAX_BURST(info2);
2772 maxp = MAX_PACKET_DECODED(info2);
2773
2774 avg = EP_AVG_TRB_LENGTH(tx_info);
2775
2776 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2777 xhci_ep_state_string(ep_state), mult,
2778 max_pstr, lsa ? "LSA " : "");
2779
2780 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2781 (1 << interval) * 125, esit, cerr);
2782
2783 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2784 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2785 burst, maxp, deq);
2786
2787 ret += sprintf(str + ret, "avg trb len %d", avg);
2788
2789 return str;
2790}
2791
2792#endif /* __LINUX_XHCI_HCD_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21/* Code sharing between pci-quirks and xhci hcd */
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25/* xHCI PCI Configuration Registers */
26#define XHCI_SBRN_OFFSET (0x60)
27
28/* Max number of USB devices for any host controller - limit in section 6.1 */
29#define MAX_HC_SLOTS 256
30/* Section 5.3.3 - MaxPorts */
31#define MAX_HC_PORTS 127
32
33/*
34 * xHCI register interface.
35 * This corresponds to the eXtensible Host Controller Interface (xHCI)
36 * Revision 0.95 specification
37 */
38
39/**
40 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
41 * @hc_capbase: length of the capabilities register and HC version number
42 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
43 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
44 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
45 * @hcc_params: HCCPARAMS - Capability Parameters
46 * @db_off: DBOFF - Doorbell array offset
47 * @run_regs_off: RTSOFF - Runtime register space offset
48 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
49 */
50struct xhci_cap_regs {
51 __le32 hc_capbase;
52 __le32 hcs_params1;
53 __le32 hcs_params2;
54 __le32 hcs_params3;
55 __le32 hcc_params;
56 __le32 db_off;
57 __le32 run_regs_off;
58 __le32 hcc_params2; /* xhci 1.1 */
59 /* Reserved up to (CAPLENGTH - 0x1C) */
60};
61
62/* hc_capbase bitmasks */
63/* bits 7:0 - how long is the Capabilities register */
64#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
65/* bits 31:16 */
66#define HC_VERSION(p) (((p) >> 16) & 0xffff)
67
68/* HCSPARAMS1 - hcs_params1 - bitmasks */
69/* bits 0:7, Max Device Slots */
70#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
71#define HCS_SLOTS_MASK 0xff
72/* bits 8:18, Max Interrupters */
73#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
74/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
75#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
76
77/* HCSPARAMS2 - hcs_params2 - bitmasks */
78/* bits 0:3, frames or uframes that SW needs to queue transactions
79 * ahead of the HW to meet periodic deadlines */
80#define HCS_IST(p) (((p) >> 0) & 0xf)
81/* bits 4:7, max number of Event Ring segments */
82#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
83/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
84/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
85/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
86#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
87
88/* HCSPARAMS3 - hcs_params3 - bitmasks */
89/* bits 0:7, Max U1 to U0 latency for the roothub ports */
90#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
91/* bits 16:31, Max U2 to U0 latency for the roothub ports */
92#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
93
94/* HCCPARAMS - hcc_params - bitmasks */
95/* true: HC can use 64-bit address pointers */
96#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
97/* true: HC can do bandwidth negotiation */
98#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
99/* true: HC uses 64-byte Device Context structures
100 * FIXME 64-byte context structures aren't supported yet.
101 */
102#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
103/* true: HC has port power switches */
104#define HCC_PPC(p) ((p) & (1 << 3))
105/* true: HC has port indicators */
106#define HCS_INDICATOR(p) ((p) & (1 << 4))
107/* true: HC has Light HC Reset Capability */
108#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
109/* true: HC supports latency tolerance messaging */
110#define HCC_LTC(p) ((p) & (1 << 6))
111/* true: no secondary Stream ID Support */
112#define HCC_NSS(p) ((p) & (1 << 7))
113/* true: HC supports Stopped - Short Packet */
114#define HCC_SPC(p) ((p) & (1 << 9))
115/* true: HC has Contiguous Frame ID Capability */
116#define HCC_CFC(p) ((p) & (1 << 11))
117/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
118#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
119/* Extended Capabilities pointer from PCI base - section 5.3.6 */
120#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
121
122#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
123
124/* db_off bitmask - bits 0:1 reserved */
125#define DBOFF_MASK (~0x3)
126
127/* run_regs_off bitmask - bits 0:4 reserved */
128#define RTSOFF_MASK (~0x1f)
129
130/* HCCPARAMS2 - hcc_params2 - bitmasks */
131/* true: HC supports U3 entry Capability */
132#define HCC2_U3C(p) ((p) & (1 << 0))
133/* true: HC supports Configure endpoint command Max exit latency too large */
134#define HCC2_CMC(p) ((p) & (1 << 1))
135/* true: HC supports Force Save context Capability */
136#define HCC2_FSC(p) ((p) & (1 << 2))
137/* true: HC supports Compliance Transition Capability */
138#define HCC2_CTC(p) ((p) & (1 << 3))
139/* true: HC support Large ESIT payload Capability > 48k */
140#define HCC2_LEC(p) ((p) & (1 << 4))
141/* true: HC support Configuration Information Capability */
142#define HCC2_CIC(p) ((p) & (1 << 5))
143/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
144#define HCC2_ETC(p) ((p) & (1 << 6))
145
146/* Number of registers per port */
147#define NUM_PORT_REGS 4
148
149#define PORTSC 0
150#define PORTPMSC 1
151#define PORTLI 2
152#define PORTHLPMC 3
153
154/**
155 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
156 * @command: USBCMD - xHC command register
157 * @status: USBSTS - xHC status register
158 * @page_size: This indicates the page size that the host controller
159 * supports. If bit n is set, the HC supports a page size
160 * of 2^(n+12), up to a 128MB page size.
161 * 4K is the minimum page size.
162 * @cmd_ring: CRP - 64-bit Command Ring Pointer
163 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
164 * @config_reg: CONFIG - Configure Register
165 * @port_status_base: PORTSCn - base address for Port Status and Control
166 * Each port has a Port Status and Control register,
167 * followed by a Port Power Management Status and Control
168 * register, a Port Link Info register, and a reserved
169 * register.
170 * @port_power_base: PORTPMSCn - base address for
171 * Port Power Management Status and Control
172 * @port_link_base: PORTLIn - base address for Port Link Info (current
173 * Link PM state and control) for USB 2.1 and USB 3.0
174 * devices.
175 */
176struct xhci_op_regs {
177 __le32 command;
178 __le32 status;
179 __le32 page_size;
180 __le32 reserved1;
181 __le32 reserved2;
182 __le32 dev_notification;
183 __le64 cmd_ring;
184 /* rsvd: offset 0x20-2F */
185 __le32 reserved3[4];
186 __le64 dcbaa_ptr;
187 __le32 config_reg;
188 /* rsvd: offset 0x3C-3FF */
189 __le32 reserved4[241];
190 /* port 1 registers, which serve as a base address for other ports */
191 __le32 port_status_base;
192 __le32 port_power_base;
193 __le32 port_link_base;
194 __le32 reserved5;
195 /* registers for ports 2-255 */
196 __le32 reserved6[NUM_PORT_REGS*254];
197};
198
199/* USBCMD - USB command - command bitmasks */
200/* start/stop HC execution - do not write unless HC is halted*/
201#define CMD_RUN XHCI_CMD_RUN
202/* Reset HC - resets internal HC state machine and all registers (except
203 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
204 * The xHCI driver must reinitialize the xHC after setting this bit.
205 */
206#define CMD_RESET (1 << 1)
207/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
208#define CMD_EIE XHCI_CMD_EIE
209/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
210#define CMD_HSEIE XHCI_CMD_HSEIE
211/* bits 4:6 are reserved (and should be preserved on writes). */
212/* light reset (port status stays unchanged) - reset completed when this is 0 */
213#define CMD_LRESET (1 << 7)
214/* host controller save/restore state. */
215#define CMD_CSS (1 << 8)
216#define CMD_CRS (1 << 9)
217/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
218#define CMD_EWE XHCI_CMD_EWE
219/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
220 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
221 * '0' means the xHC can power it off if all ports are in the disconnect,
222 * disabled, or powered-off state.
223 */
224#define CMD_PM_INDEX (1 << 11)
225/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
226#define CMD_ETE (1 << 14)
227/* bits 15:31 are reserved (and should be preserved on writes). */
228
229/* IMAN - Interrupt Management Register */
230#define IMAN_IE (1 << 1)
231#define IMAN_IP (1 << 0)
232
233/* USBSTS - USB status - status bitmasks */
234/* HC not running - set to 1 when run/stop bit is cleared. */
235#define STS_HALT XHCI_STS_HALT
236/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
237#define STS_FATAL (1 << 2)
238/* event interrupt - clear this prior to clearing any IP flags in IR set*/
239#define STS_EINT (1 << 3)
240/* port change detect */
241#define STS_PORT (1 << 4)
242/* bits 5:7 reserved and zeroed */
243/* save state status - '1' means xHC is saving state */
244#define STS_SAVE (1 << 8)
245/* restore state status - '1' means xHC is restoring state */
246#define STS_RESTORE (1 << 9)
247/* true: save or restore error */
248#define STS_SRE (1 << 10)
249/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
250#define STS_CNR XHCI_STS_CNR
251/* true: internal Host Controller Error - SW needs to reset and reinitialize */
252#define STS_HCE (1 << 12)
253/* bits 13:31 reserved and should be preserved */
254
255/*
256 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
257 * Generate a device notification event when the HC sees a transaction with a
258 * notification type that matches a bit set in this bit field.
259 */
260#define DEV_NOTE_MASK (0xffff)
261#define ENABLE_DEV_NOTE(x) (1 << (x))
262/* Most of the device notification types should only be used for debug.
263 * SW does need to pay attention to function wake notifications.
264 */
265#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
266
267/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
268/* bit 0 is the command ring cycle state */
269/* stop ring operation after completion of the currently executing command */
270#define CMD_RING_PAUSE (1 << 1)
271/* stop ring immediately - abort the currently executing command */
272#define CMD_RING_ABORT (1 << 2)
273/* true: command ring is running */
274#define CMD_RING_RUNNING (1 << 3)
275/* bits 4:5 reserved and should be preserved */
276/* Command Ring pointer - bit mask for the lower 32 bits. */
277#define CMD_RING_RSVD_BITS (0x3f)
278
279/* CONFIG - Configure Register - config_reg bitmasks */
280/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
281#define MAX_DEVS(p) ((p) & 0xff)
282/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
283#define CONFIG_U3E (1 << 8)
284/* bit 9: Configuration Information Enable, xhci 1.1 */
285#define CONFIG_CIE (1 << 9)
286/* bits 10:31 - reserved and should be preserved */
287
288/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
289/* true: device connected */
290#define PORT_CONNECT (1 << 0)
291/* true: port enabled */
292#define PORT_PE (1 << 1)
293/* bit 2 reserved and zeroed */
294/* true: port has an over-current condition */
295#define PORT_OC (1 << 3)
296/* true: port reset signaling asserted */
297#define PORT_RESET (1 << 4)
298/* Port Link State - bits 5:8
299 * A read gives the current link PM state of the port,
300 * a write with Link State Write Strobe set sets the link state.
301 */
302#define PORT_PLS_MASK (0xf << 5)
303#define XDEV_U0 (0x0 << 5)
304#define XDEV_U1 (0x1 << 5)
305#define XDEV_U2 (0x2 << 5)
306#define XDEV_U3 (0x3 << 5)
307#define XDEV_DISABLED (0x4 << 5)
308#define XDEV_RXDETECT (0x5 << 5)
309#define XDEV_INACTIVE (0x6 << 5)
310#define XDEV_POLLING (0x7 << 5)
311#define XDEV_RECOVERY (0x8 << 5)
312#define XDEV_HOT_RESET (0x9 << 5)
313#define XDEV_COMP_MODE (0xa << 5)
314#define XDEV_TEST_MODE (0xb << 5)
315#define XDEV_RESUME (0xf << 5)
316
317/* true: port has power (see HCC_PPC) */
318#define PORT_POWER (1 << 9)
319/* bits 10:13 indicate device speed:
320 * 0 - undefined speed - port hasn't be initialized by a reset yet
321 * 1 - full speed
322 * 2 - low speed
323 * 3 - high speed
324 * 4 - super speed
325 * 5-15 reserved
326 */
327#define DEV_SPEED_MASK (0xf << 10)
328#define XDEV_FS (0x1 << 10)
329#define XDEV_LS (0x2 << 10)
330#define XDEV_HS (0x3 << 10)
331#define XDEV_SS (0x4 << 10)
332#define XDEV_SSP (0x5 << 10)
333#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
334#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
335#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
336#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
337#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
338#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
339#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
340#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
341
342/* Bits 20:23 in the Slot Context are the speed for the device */
343#define SLOT_SPEED_FS (XDEV_FS << 10)
344#define SLOT_SPEED_LS (XDEV_LS << 10)
345#define SLOT_SPEED_HS (XDEV_HS << 10)
346#define SLOT_SPEED_SS (XDEV_SS << 10)
347#define SLOT_SPEED_SSP (XDEV_SSP << 10)
348/* Port Indicator Control */
349#define PORT_LED_OFF (0 << 14)
350#define PORT_LED_AMBER (1 << 14)
351#define PORT_LED_GREEN (2 << 14)
352#define PORT_LED_MASK (3 << 14)
353/* Port Link State Write Strobe - set this when changing link state */
354#define PORT_LINK_STROBE (1 << 16)
355/* true: connect status change */
356#define PORT_CSC (1 << 17)
357/* true: port enable change */
358#define PORT_PEC (1 << 18)
359/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
360 * into an enabled state, and the device into the default state. A "warm" reset
361 * also resets the link, forcing the device through the link training sequence.
362 * SW can also look at the Port Reset register to see when warm reset is done.
363 */
364#define PORT_WRC (1 << 19)
365/* true: over-current change */
366#define PORT_OCC (1 << 20)
367/* true: reset change - 1 to 0 transition of PORT_RESET */
368#define PORT_RC (1 << 21)
369/* port link status change - set on some port link state transitions:
370 * Transition Reason
371 * ------------------------------------------------------------------------------
372 * - U3 to Resume Wakeup signaling from a device
373 * - Resume to Recovery to U0 USB 3.0 device resume
374 * - Resume to U0 USB 2.0 device resume
375 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
376 * - U3 to U0 Software resume of USB 2.0 device complete
377 * - U2 to U0 L1 resume of USB 2.1 device complete
378 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
379 * - U0 to disabled L1 entry error with USB 2.1 device
380 * - Any state to inactive Error on USB 3.0 port
381 */
382#define PORT_PLC (1 << 22)
383/* port configure error change - port failed to configure its link partner */
384#define PORT_CEC (1 << 23)
385#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
386 PORT_RC | PORT_PLC | PORT_CEC)
387
388
389/* Cold Attach Status - xHC can set this bit to report device attached during
390 * Sx state. Warm port reset should be perfomed to clear this bit and move port
391 * to connected state.
392 */
393#define PORT_CAS (1 << 24)
394/* wake on connect (enable) */
395#define PORT_WKCONN_E (1 << 25)
396/* wake on disconnect (enable) */
397#define PORT_WKDISC_E (1 << 26)
398/* wake on over-current (enable) */
399#define PORT_WKOC_E (1 << 27)
400/* bits 28:29 reserved */
401/* true: device is non-removable - for USB 3.0 roothub emulation */
402#define PORT_DEV_REMOVE (1 << 30)
403/* Initiate a warm port reset - complete when PORT_WRC is '1' */
404#define PORT_WR (1 << 31)
405
406/* We mark duplicate entries with -1 */
407#define DUPLICATE_ENTRY ((u8)(-1))
408
409/* Port Power Management Status and Control - port_power_base bitmasks */
410/* Inactivity timer value for transitions into U1, in microseconds.
411 * Timeout can be up to 127us. 0xFF means an infinite timeout.
412 */
413#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
414#define PORT_U1_TIMEOUT_MASK 0xff
415/* Inactivity timer value for transitions into U2 */
416#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
417#define PORT_U2_TIMEOUT_MASK (0xff << 8)
418/* Bits 24:31 for port testing */
419
420/* USB2 Protocol PORTSPMSC */
421#define PORT_L1S_MASK 7
422#define PORT_L1S_SUCCESS 1
423#define PORT_RWE (1 << 3)
424#define PORT_HIRD(p) (((p) & 0xf) << 4)
425#define PORT_HIRD_MASK (0xf << 4)
426#define PORT_L1DS_MASK (0xff << 8)
427#define PORT_L1DS(p) (((p) & 0xff) << 8)
428#define PORT_HLE (1 << 16)
429#define PORT_TEST_MODE_SHIFT 28
430
431/* USB3 Protocol PORTLI Port Link Information */
432#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
433#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
434
435/* USB2 Protocol PORTHLPMC */
436#define PORT_HIRDM(p)((p) & 3)
437#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
438#define PORT_BESLD(p)(((p) & 0xf) << 10)
439
440/* use 512 microseconds as USB2 LPM L1 default timeout. */
441#define XHCI_L1_TIMEOUT 512
442
443/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
444 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
445 * by other operating systems.
446 *
447 * XHCI 1.0 errata 8/14/12 Table 13 notes:
448 * "Software should choose xHC BESL/BESLD field values that do not violate a
449 * device's resume latency requirements,
450 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
451 * or not program values < '4' if BLC = '0' and a BESL device is attached.
452 */
453#define XHCI_DEFAULT_BESL 4
454
455/*
456 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
457 * to complete link training. usually link trainig completes much faster
458 * so check status 10 times with 36ms sleep in places we need to wait for
459 * polling to complete.
460 */
461#define XHCI_PORT_POLLING_LFPS_TIME 36
462
463/**
464 * struct xhci_intr_reg - Interrupt Register Set
465 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
466 * interrupts and check for pending interrupts.
467 * @irq_control: IMOD - Interrupt Moderation Register.
468 * Used to throttle interrupts.
469 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
470 * @erst_base: ERST base address.
471 * @erst_dequeue: Event ring dequeue pointer.
472 *
473 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
474 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
475 * multiple segments of the same size. The HC places events on the ring and
476 * "updates the Cycle bit in the TRBs to indicate to software the current
477 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
478 * updates the dequeue pointer.
479 */
480struct xhci_intr_reg {
481 __le32 irq_pending;
482 __le32 irq_control;
483 __le32 erst_size;
484 __le32 rsvd;
485 __le64 erst_base;
486 __le64 erst_dequeue;
487};
488
489/* irq_pending bitmasks */
490#define ER_IRQ_PENDING(p) ((p) & 0x1)
491/* bits 2:31 need to be preserved */
492/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
493#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
494#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
495#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
496
497/* irq_control bitmasks */
498/* Minimum interval between interrupts (in 250ns intervals). The interval
499 * between interrupts will be longer if there are no events on the event ring.
500 * Default is 4000 (1 ms).
501 */
502#define ER_IRQ_INTERVAL_MASK (0xffff)
503/* Counter used to count down the time to the next interrupt - HW use only */
504#define ER_IRQ_COUNTER_MASK (0xffff << 16)
505
506/* erst_size bitmasks */
507/* Preserve bits 16:31 of erst_size */
508#define ERST_SIZE_MASK (0xffff << 16)
509
510/* erst_dequeue bitmasks */
511/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
512 * where the current dequeue pointer lies. This is an optional HW hint.
513 */
514#define ERST_DESI_MASK (0x7)
515/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
516 * a work queue (or delayed service routine)?
517 */
518#define ERST_EHB (1 << 3)
519#define ERST_PTR_MASK (0xf)
520
521/**
522 * struct xhci_run_regs
523 * @microframe_index:
524 * MFINDEX - current microframe number
525 *
526 * Section 5.5 Host Controller Runtime Registers:
527 * "Software should read and write these registers using only Dword (32 bit)
528 * or larger accesses"
529 */
530struct xhci_run_regs {
531 __le32 microframe_index;
532 __le32 rsvd[7];
533 struct xhci_intr_reg ir_set[128];
534};
535
536/**
537 * struct doorbell_array
538 *
539 * Bits 0 - 7: Endpoint target
540 * Bits 8 - 15: RsvdZ
541 * Bits 16 - 31: Stream ID
542 *
543 * Section 5.6
544 */
545struct xhci_doorbell_array {
546 __le32 doorbell[256];
547};
548
549#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
550#define DB_VALUE_HOST 0x00000000
551
552/**
553 * struct xhci_protocol_caps
554 * @revision: major revision, minor revision, capability ID,
555 * and next capability pointer.
556 * @name_string: Four ASCII characters to say which spec this xHC
557 * follows, typically "USB ".
558 * @port_info: Port offset, count, and protocol-defined information.
559 */
560struct xhci_protocol_caps {
561 u32 revision;
562 u32 name_string;
563 u32 port_info;
564};
565
566#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
567#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
568#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
569#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
570#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
571
572#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
573#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
574#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
575#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
576#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
577#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
578
579#define PLT_MASK (0x03 << 6)
580#define PLT_SYM (0x00 << 6)
581#define PLT_ASYM_RX (0x02 << 6)
582#define PLT_ASYM_TX (0x03 << 6)
583
584/**
585 * struct xhci_container_ctx
586 * @type: Type of context. Used to calculated offsets to contained contexts.
587 * @size: Size of the context data
588 * @bytes: The raw context data given to HW
589 * @dma: dma address of the bytes
590 *
591 * Represents either a Device or Input context. Holds a pointer to the raw
592 * memory used for the context (bytes) and dma address of it (dma).
593 */
594struct xhci_container_ctx {
595 unsigned type;
596#define XHCI_CTX_TYPE_DEVICE 0x1
597#define XHCI_CTX_TYPE_INPUT 0x2
598
599 int size;
600
601 u8 *bytes;
602 dma_addr_t dma;
603};
604
605/**
606 * struct xhci_slot_ctx
607 * @dev_info: Route string, device speed, hub info, and last valid endpoint
608 * @dev_info2: Max exit latency for device number, root hub port number
609 * @tt_info: tt_info is used to construct split transaction tokens
610 * @dev_state: slot state and device address
611 *
612 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
613 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
614 * reserved at the end of the slot context for HC internal use.
615 */
616struct xhci_slot_ctx {
617 __le32 dev_info;
618 __le32 dev_info2;
619 __le32 tt_info;
620 __le32 dev_state;
621 /* offset 0x10 to 0x1f reserved for HC internal use */
622 __le32 reserved[4];
623};
624
625/* dev_info bitmasks */
626/* Route String - 0:19 */
627#define ROUTE_STRING_MASK (0xfffff)
628/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
629#define DEV_SPEED (0xf << 20)
630#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
631/* bit 24 reserved */
632/* Is this LS/FS device connected through a HS hub? - bit 25 */
633#define DEV_MTT (0x1 << 25)
634/* Set if the device is a hub - bit 26 */
635#define DEV_HUB (0x1 << 26)
636/* Index of the last valid endpoint context in this device context - 27:31 */
637#define LAST_CTX_MASK (0x1f << 27)
638#define LAST_CTX(p) ((p) << 27)
639#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
640#define SLOT_FLAG (1 << 0)
641#define EP0_FLAG (1 << 1)
642
643/* dev_info2 bitmasks */
644/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
645#define MAX_EXIT (0xffff)
646/* Root hub port number that is needed to access the USB device */
647#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
648#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
649/* Maximum number of ports under a hub device */
650#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
651#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
652
653/* tt_info bitmasks */
654/*
655 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
656 * The Slot ID of the hub that isolates the high speed signaling from
657 * this low or full-speed device. '0' if attached to root hub port.
658 */
659#define TT_SLOT (0xff)
660/*
661 * The number of the downstream facing port of the high-speed hub
662 * '0' if the device is not low or full speed.
663 */
664#define TT_PORT (0xff << 8)
665#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
666#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
667
668/* dev_state bitmasks */
669/* USB device address - assigned by the HC */
670#define DEV_ADDR_MASK (0xff)
671/* bits 8:26 reserved */
672/* Slot state */
673#define SLOT_STATE (0x1f << 27)
674#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
675
676#define SLOT_STATE_DISABLED 0
677#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
678#define SLOT_STATE_DEFAULT 1
679#define SLOT_STATE_ADDRESSED 2
680#define SLOT_STATE_CONFIGURED 3
681
682/**
683 * struct xhci_ep_ctx
684 * @ep_info: endpoint state, streams, mult, and interval information.
685 * @ep_info2: information on endpoint type, max packet size, max burst size,
686 * error count, and whether the HC will force an event for all
687 * transactions.
688 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
689 * defines one stream, this points to the endpoint transfer ring.
690 * Otherwise, it points to a stream context array, which has a
691 * ring pointer for each flow.
692 * @tx_info:
693 * Average TRB lengths for the endpoint ring and
694 * max payload within an Endpoint Service Interval Time (ESIT).
695 *
696 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
697 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
698 * reserved at the end of the endpoint context for HC internal use.
699 */
700struct xhci_ep_ctx {
701 __le32 ep_info;
702 __le32 ep_info2;
703 __le64 deq;
704 __le32 tx_info;
705 /* offset 0x14 - 0x1f reserved for HC internal use */
706 __le32 reserved[3];
707};
708
709/* ep_info bitmasks */
710/*
711 * Endpoint State - bits 0:2
712 * 0 - disabled
713 * 1 - running
714 * 2 - halted due to halt condition - ok to manipulate endpoint ring
715 * 3 - stopped
716 * 4 - TRB error
717 * 5-7 - reserved
718 */
719#define EP_STATE_MASK (0x7)
720#define EP_STATE_DISABLED 0
721#define EP_STATE_RUNNING 1
722#define EP_STATE_HALTED 2
723#define EP_STATE_STOPPED 3
724#define EP_STATE_ERROR 4
725#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
726
727/* Mult - Max number of burtst within an interval, in EP companion desc. */
728#define EP_MULT(p) (((p) & 0x3) << 8)
729#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
730/* bits 10:14 are Max Primary Streams */
731/* bit 15 is Linear Stream Array */
732/* Interval - period between requests to an endpoint - 125u increments. */
733#define EP_INTERVAL(p) (((p) & 0xff) << 16)
734#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
735#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
736#define EP_MAXPSTREAMS_MASK (0x1f << 10)
737#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
738#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
739/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
740#define EP_HAS_LSA (1 << 15)
741/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
742#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
743
744/* ep_info2 bitmasks */
745/*
746 * Force Event - generate transfer events for all TRBs for this endpoint
747 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
748 */
749#define FORCE_EVENT (0x1)
750#define ERROR_COUNT(p) (((p) & 0x3) << 1)
751#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
752#define EP_TYPE(p) ((p) << 3)
753#define ISOC_OUT_EP 1
754#define BULK_OUT_EP 2
755#define INT_OUT_EP 3
756#define CTRL_EP 4
757#define ISOC_IN_EP 5
758#define BULK_IN_EP 6
759#define INT_IN_EP 7
760/* bit 6 reserved */
761/* bit 7 is Host Initiate Disable - for disabling stream selection */
762#define MAX_BURST(p) (((p)&0xff) << 8)
763#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
764#define MAX_PACKET(p) (((p)&0xffff) << 16)
765#define MAX_PACKET_MASK (0xffff << 16)
766#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
767
768/* tx_info bitmasks */
769#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
770#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
771#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
772#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
773
774/* deq bitmasks */
775#define EP_CTX_CYCLE_MASK (1 << 0)
776#define SCTX_DEQ_MASK (~0xfL)
777
778
779/**
780 * struct xhci_input_control_context
781 * Input control context; see section 6.2.5.
782 *
783 * @drop_context: set the bit of the endpoint context you want to disable
784 * @add_context: set the bit of the endpoint context you want to enable
785 */
786struct xhci_input_control_ctx {
787 __le32 drop_flags;
788 __le32 add_flags;
789 __le32 rsvd2[6];
790};
791
792#define EP_IS_ADDED(ctrl_ctx, i) \
793 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
794#define EP_IS_DROPPED(ctrl_ctx, i) \
795 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
796
797/* Represents everything that is needed to issue a command on the command ring.
798 * It's useful to pre-allocate these for commands that cannot fail due to
799 * out-of-memory errors, like freeing streams.
800 */
801struct xhci_command {
802 /* Input context for changing device state */
803 struct xhci_container_ctx *in_ctx;
804 u32 status;
805 int slot_id;
806 /* If completion is null, no one is waiting on this command
807 * and the structure can be freed after the command completes.
808 */
809 struct completion *completion;
810 union xhci_trb *command_trb;
811 struct list_head cmd_list;
812};
813
814/* drop context bitmasks */
815#define DROP_EP(x) (0x1 << x)
816/* add context bitmasks */
817#define ADD_EP(x) (0x1 << x)
818
819struct xhci_stream_ctx {
820 /* 64-bit stream ring address, cycle state, and stream type */
821 __le64 stream_ring;
822 /* offset 0x14 - 0x1f reserved for HC internal use */
823 __le32 reserved[2];
824};
825
826/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
827#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
828/* Secondary stream array type, dequeue pointer is to a transfer ring */
829#define SCT_SEC_TR 0
830/* Primary stream array type, dequeue pointer is to a transfer ring */
831#define SCT_PRI_TR 1
832/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
833#define SCT_SSA_8 2
834#define SCT_SSA_16 3
835#define SCT_SSA_32 4
836#define SCT_SSA_64 5
837#define SCT_SSA_128 6
838#define SCT_SSA_256 7
839
840/* Assume no secondary streams for now */
841struct xhci_stream_info {
842 struct xhci_ring **stream_rings;
843 /* Number of streams, including stream 0 (which drivers can't use) */
844 unsigned int num_streams;
845 /* The stream context array may be bigger than
846 * the number of streams the driver asked for
847 */
848 struct xhci_stream_ctx *stream_ctx_array;
849 unsigned int num_stream_ctxs;
850 dma_addr_t ctx_array_dma;
851 /* For mapping physical TRB addresses to segments in stream rings */
852 struct radix_tree_root trb_address_map;
853 struct xhci_command *free_streams_command;
854};
855
856#define SMALL_STREAM_ARRAY_SIZE 256
857#define MEDIUM_STREAM_ARRAY_SIZE 1024
858
859/* Some Intel xHCI host controllers need software to keep track of the bus
860 * bandwidth. Keep track of endpoint info here. Each root port is allocated
861 * the full bus bandwidth. We must also treat TTs (including each port under a
862 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
863 * (DMI) also limits the total bandwidth (across all domains) that can be used.
864 */
865struct xhci_bw_info {
866 /* ep_interval is zero-based */
867 unsigned int ep_interval;
868 /* mult and num_packets are one-based */
869 unsigned int mult;
870 unsigned int num_packets;
871 unsigned int max_packet_size;
872 unsigned int max_esit_payload;
873 unsigned int type;
874};
875
876/* "Block" sizes in bytes the hardware uses for different device speeds.
877 * The logic in this part of the hardware limits the number of bits the hardware
878 * can use, so must represent bandwidth in a less precise manner to mimic what
879 * the scheduler hardware computes.
880 */
881#define FS_BLOCK 1
882#define HS_BLOCK 4
883#define SS_BLOCK 16
884#define DMI_BLOCK 32
885
886/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
887 * with each byte transferred. SuperSpeed devices have an initial overhead to
888 * set up bursts. These are in blocks, see above. LS overhead has already been
889 * translated into FS blocks.
890 */
891#define DMI_OVERHEAD 8
892#define DMI_OVERHEAD_BURST 4
893#define SS_OVERHEAD 8
894#define SS_OVERHEAD_BURST 32
895#define HS_OVERHEAD 26
896#define FS_OVERHEAD 20
897#define LS_OVERHEAD 128
898/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
899 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
900 * of overhead associated with split transfers crossing microframe boundaries.
901 * 31 blocks is pure protocol overhead.
902 */
903#define TT_HS_OVERHEAD (31 + 94)
904#define TT_DMI_OVERHEAD (25 + 12)
905
906/* Bandwidth limits in blocks */
907#define FS_BW_LIMIT 1285
908#define TT_BW_LIMIT 1320
909#define HS_BW_LIMIT 1607
910#define SS_BW_LIMIT_IN 3906
911#define DMI_BW_LIMIT_IN 3906
912#define SS_BW_LIMIT_OUT 3906
913#define DMI_BW_LIMIT_OUT 3906
914
915/* Percentage of bus bandwidth reserved for non-periodic transfers */
916#define FS_BW_RESERVED 10
917#define HS_BW_RESERVED 20
918#define SS_BW_RESERVED 10
919
920struct xhci_virt_ep {
921 struct xhci_ring *ring;
922 /* Related to endpoints that are configured to use stream IDs only */
923 struct xhci_stream_info *stream_info;
924 /* Temporary storage in case the configure endpoint command fails and we
925 * have to restore the device state to the previous state
926 */
927 struct xhci_ring *new_ring;
928 unsigned int ep_state;
929#define SET_DEQ_PENDING (1 << 0)
930#define EP_HALTED (1 << 1) /* For stall handling */
931#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
932/* Transitioning the endpoint to using streams, don't enqueue URBs */
933#define EP_GETTING_STREAMS (1 << 3)
934#define EP_HAS_STREAMS (1 << 4)
935/* Transitioning the endpoint to not using streams, don't enqueue URBs */
936#define EP_GETTING_NO_STREAMS (1 << 5)
937#define EP_HARD_CLEAR_TOGGLE (1 << 6)
938#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
939/* usb_hub_clear_tt_buffer is in progress */
940#define EP_CLEARING_TT (1 << 8)
941 /* ---- Related to URB cancellation ---- */
942 struct list_head cancelled_td_list;
943 /* Watchdog timer for stop endpoint command to cancel URBs */
944 struct timer_list stop_cmd_timer;
945 struct xhci_hcd *xhci;
946 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
947 * command. We'll need to update the ring's dequeue segment and dequeue
948 * pointer after the command completes.
949 */
950 struct xhci_segment *queued_deq_seg;
951 union xhci_trb *queued_deq_ptr;
952 /*
953 * Sometimes the xHC can not process isochronous endpoint ring quickly
954 * enough, and it will miss some isoc tds on the ring and generate
955 * a Missed Service Error Event.
956 * Set skip flag when receive a Missed Service Error Event and
957 * process the missed tds on the endpoint ring.
958 */
959 bool skip;
960 /* Bandwidth checking storage */
961 struct xhci_bw_info bw_info;
962 struct list_head bw_endpoint_list;
963 /* Isoch Frame ID checking storage */
964 int next_frame_id;
965 /* Use new Isoch TRB layout needed for extended TBC support */
966 bool use_extended_tbc;
967};
968
969enum xhci_overhead_type {
970 LS_OVERHEAD_TYPE = 0,
971 FS_OVERHEAD_TYPE,
972 HS_OVERHEAD_TYPE,
973};
974
975struct xhci_interval_bw {
976 unsigned int num_packets;
977 /* Sorted by max packet size.
978 * Head of the list is the greatest max packet size.
979 */
980 struct list_head endpoints;
981 /* How many endpoints of each speed are present. */
982 unsigned int overhead[3];
983};
984
985#define XHCI_MAX_INTERVAL 16
986
987struct xhci_interval_bw_table {
988 unsigned int interval0_esit_payload;
989 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
990 /* Includes reserved bandwidth for async endpoints */
991 unsigned int bw_used;
992 unsigned int ss_bw_in;
993 unsigned int ss_bw_out;
994};
995
996
997struct xhci_virt_device {
998 struct usb_device *udev;
999 /*
1000 * Commands to the hardware are passed an "input context" that
1001 * tells the hardware what to change in its data structures.
1002 * The hardware will return changes in an "output context" that
1003 * software must allocate for the hardware. We need to keep
1004 * track of input and output contexts separately because
1005 * these commands might fail and we don't trust the hardware.
1006 */
1007 struct xhci_container_ctx *out_ctx;
1008 /* Used for addressing devices and configuration changes */
1009 struct xhci_container_ctx *in_ctx;
1010 struct xhci_virt_ep eps[31];
1011 u8 fake_port;
1012 u8 real_port;
1013 struct xhci_interval_bw_table *bw_table;
1014 struct xhci_tt_bw_info *tt_info;
1015 /*
1016 * flags for state tracking based on events and issued commands.
1017 * Software can not rely on states from output contexts because of
1018 * latency between events and xHC updating output context values.
1019 * See xhci 1.1 section 4.8.3 for more details
1020 */
1021 unsigned long flags;
1022#define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1023
1024 /* The current max exit latency for the enabled USB3 link states. */
1025 u16 current_mel;
1026 /* Used for the debugfs interfaces. */
1027 void *debugfs_private;
1028};
1029
1030/*
1031 * For each roothub, keep track of the bandwidth information for each periodic
1032 * interval.
1033 *
1034 * If a high speed hub is attached to the roothub, each TT associated with that
1035 * hub is a separate bandwidth domain. The interval information for the
1036 * endpoints on the devices under that TT will appear in the TT structure.
1037 */
1038struct xhci_root_port_bw_info {
1039 struct list_head tts;
1040 unsigned int num_active_tts;
1041 struct xhci_interval_bw_table bw_table;
1042};
1043
1044struct xhci_tt_bw_info {
1045 struct list_head tt_list;
1046 int slot_id;
1047 int ttport;
1048 struct xhci_interval_bw_table bw_table;
1049 int active_eps;
1050};
1051
1052
1053/**
1054 * struct xhci_device_context_array
1055 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1056 */
1057struct xhci_device_context_array {
1058 /* 64-bit device addresses; we only write 32-bit addresses */
1059 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1060 /* private xHCD pointers */
1061 dma_addr_t dma;
1062};
1063/* TODO: write function to set the 64-bit device DMA address */
1064/*
1065 * TODO: change this to be dynamically sized at HC mem init time since the HC
1066 * might not be able to handle the maximum number of devices possible.
1067 */
1068
1069
1070struct xhci_transfer_event {
1071 /* 64-bit buffer address, or immediate data */
1072 __le64 buffer;
1073 __le32 transfer_len;
1074 /* This field is interpreted differently based on the type of TRB */
1075 __le32 flags;
1076};
1077
1078/* Transfer event TRB length bit mask */
1079/* bits 0:23 */
1080#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1081
1082/** Transfer Event bit fields **/
1083#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1084
1085/* Completion Code - only applicable for some types of TRBs */
1086#define COMP_CODE_MASK (0xff << 24)
1087#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1088#define COMP_INVALID 0
1089#define COMP_SUCCESS 1
1090#define COMP_DATA_BUFFER_ERROR 2
1091#define COMP_BABBLE_DETECTED_ERROR 3
1092#define COMP_USB_TRANSACTION_ERROR 4
1093#define COMP_TRB_ERROR 5
1094#define COMP_STALL_ERROR 6
1095#define COMP_RESOURCE_ERROR 7
1096#define COMP_BANDWIDTH_ERROR 8
1097#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1098#define COMP_INVALID_STREAM_TYPE_ERROR 10
1099#define COMP_SLOT_NOT_ENABLED_ERROR 11
1100#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1101#define COMP_SHORT_PACKET 13
1102#define COMP_RING_UNDERRUN 14
1103#define COMP_RING_OVERRUN 15
1104#define COMP_VF_EVENT_RING_FULL_ERROR 16
1105#define COMP_PARAMETER_ERROR 17
1106#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1107#define COMP_CONTEXT_STATE_ERROR 19
1108#define COMP_NO_PING_RESPONSE_ERROR 20
1109#define COMP_EVENT_RING_FULL_ERROR 21
1110#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1111#define COMP_MISSED_SERVICE_ERROR 23
1112#define COMP_COMMAND_RING_STOPPED 24
1113#define COMP_COMMAND_ABORTED 25
1114#define COMP_STOPPED 26
1115#define COMP_STOPPED_LENGTH_INVALID 27
1116#define COMP_STOPPED_SHORT_PACKET 28
1117#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1118#define COMP_ISOCH_BUFFER_OVERRUN 31
1119#define COMP_EVENT_LOST_ERROR 32
1120#define COMP_UNDEFINED_ERROR 33
1121#define COMP_INVALID_STREAM_ID_ERROR 34
1122#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1123#define COMP_SPLIT_TRANSACTION_ERROR 36
1124
1125static inline const char *xhci_trb_comp_code_string(u8 status)
1126{
1127 switch (status) {
1128 case COMP_INVALID:
1129 return "Invalid";
1130 case COMP_SUCCESS:
1131 return "Success";
1132 case COMP_DATA_BUFFER_ERROR:
1133 return "Data Buffer Error";
1134 case COMP_BABBLE_DETECTED_ERROR:
1135 return "Babble Detected";
1136 case COMP_USB_TRANSACTION_ERROR:
1137 return "USB Transaction Error";
1138 case COMP_TRB_ERROR:
1139 return "TRB Error";
1140 case COMP_STALL_ERROR:
1141 return "Stall Error";
1142 case COMP_RESOURCE_ERROR:
1143 return "Resource Error";
1144 case COMP_BANDWIDTH_ERROR:
1145 return "Bandwidth Error";
1146 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1147 return "No Slots Available Error";
1148 case COMP_INVALID_STREAM_TYPE_ERROR:
1149 return "Invalid Stream Type Error";
1150 case COMP_SLOT_NOT_ENABLED_ERROR:
1151 return "Slot Not Enabled Error";
1152 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1153 return "Endpoint Not Enabled Error";
1154 case COMP_SHORT_PACKET:
1155 return "Short Packet";
1156 case COMP_RING_UNDERRUN:
1157 return "Ring Underrun";
1158 case COMP_RING_OVERRUN:
1159 return "Ring Overrun";
1160 case COMP_VF_EVENT_RING_FULL_ERROR:
1161 return "VF Event Ring Full Error";
1162 case COMP_PARAMETER_ERROR:
1163 return "Parameter Error";
1164 case COMP_BANDWIDTH_OVERRUN_ERROR:
1165 return "Bandwidth Overrun Error";
1166 case COMP_CONTEXT_STATE_ERROR:
1167 return "Context State Error";
1168 case COMP_NO_PING_RESPONSE_ERROR:
1169 return "No Ping Response Error";
1170 case COMP_EVENT_RING_FULL_ERROR:
1171 return "Event Ring Full Error";
1172 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1173 return "Incompatible Device Error";
1174 case COMP_MISSED_SERVICE_ERROR:
1175 return "Missed Service Error";
1176 case COMP_COMMAND_RING_STOPPED:
1177 return "Command Ring Stopped";
1178 case COMP_COMMAND_ABORTED:
1179 return "Command Aborted";
1180 case COMP_STOPPED:
1181 return "Stopped";
1182 case COMP_STOPPED_LENGTH_INVALID:
1183 return "Stopped - Length Invalid";
1184 case COMP_STOPPED_SHORT_PACKET:
1185 return "Stopped - Short Packet";
1186 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1187 return "Max Exit Latency Too Large Error";
1188 case COMP_ISOCH_BUFFER_OVERRUN:
1189 return "Isoch Buffer Overrun";
1190 case COMP_EVENT_LOST_ERROR:
1191 return "Event Lost Error";
1192 case COMP_UNDEFINED_ERROR:
1193 return "Undefined Error";
1194 case COMP_INVALID_STREAM_ID_ERROR:
1195 return "Invalid Stream ID Error";
1196 case COMP_SECONDARY_BANDWIDTH_ERROR:
1197 return "Secondary Bandwidth Error";
1198 case COMP_SPLIT_TRANSACTION_ERROR:
1199 return "Split Transaction Error";
1200 default:
1201 return "Unknown!!";
1202 }
1203}
1204
1205struct xhci_link_trb {
1206 /* 64-bit segment pointer*/
1207 __le64 segment_ptr;
1208 __le32 intr_target;
1209 __le32 control;
1210};
1211
1212/* control bitfields */
1213#define LINK_TOGGLE (0x1<<1)
1214
1215/* Command completion event TRB */
1216struct xhci_event_cmd {
1217 /* Pointer to command TRB, or the value passed by the event data trb */
1218 __le64 cmd_trb;
1219 __le32 status;
1220 __le32 flags;
1221};
1222
1223/* flags bitmasks */
1224
1225/* Address device - disable SetAddress */
1226#define TRB_BSR (1<<9)
1227
1228/* Configure Endpoint - Deconfigure */
1229#define TRB_DC (1<<9)
1230
1231/* Stop Ring - Transfer State Preserve */
1232#define TRB_TSP (1<<9)
1233
1234enum xhci_ep_reset_type {
1235 EP_HARD_RESET,
1236 EP_SOFT_RESET,
1237};
1238
1239/* Force Event */
1240#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1241#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1242
1243/* Set Latency Tolerance Value */
1244#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1245
1246/* Get Port Bandwidth */
1247#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1248
1249/* Force Header */
1250#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1251#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1252
1253enum xhci_setup_dev {
1254 SETUP_CONTEXT_ONLY,
1255 SETUP_CONTEXT_ADDRESS,
1256};
1257
1258/* bits 16:23 are the virtual function ID */
1259/* bits 24:31 are the slot ID */
1260#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1261#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1262
1263/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1264#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1265#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1266
1267#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1268#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1269#define LAST_EP_INDEX 30
1270
1271/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1272#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1273#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1274#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1275
1276/* Link TRB specific fields */
1277#define TRB_TC (1<<1)
1278
1279/* Port Status Change Event TRB fields */
1280/* Port ID - bits 31:24 */
1281#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1282
1283#define EVENT_DATA (1 << 2)
1284
1285/* Normal TRB fields */
1286/* transfer_len bitmasks - bits 0:16 */
1287#define TRB_LEN(p) ((p) & 0x1ffff)
1288/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1289#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1290#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1291/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1292#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1293/* Interrupter Target - which MSI-X vector to target the completion event at */
1294#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1295#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1296/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1297#define TRB_TBC(p) (((p) & 0x3) << 7)
1298#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1299
1300/* Cycle bit - indicates TRB ownership by HC or HCD */
1301#define TRB_CYCLE (1<<0)
1302/*
1303 * Force next event data TRB to be evaluated before task switch.
1304 * Used to pass OS data back after a TD completes.
1305 */
1306#define TRB_ENT (1<<1)
1307/* Interrupt on short packet */
1308#define TRB_ISP (1<<2)
1309/* Set PCIe no snoop attribute */
1310#define TRB_NO_SNOOP (1<<3)
1311/* Chain multiple TRBs into a TD */
1312#define TRB_CHAIN (1<<4)
1313/* Interrupt on completion */
1314#define TRB_IOC (1<<5)
1315/* The buffer pointer contains immediate data */
1316#define TRB_IDT (1<<6)
1317/* TDs smaller than this might use IDT */
1318#define TRB_IDT_MAX_SIZE 8
1319
1320/* Block Event Interrupt */
1321#define TRB_BEI (1<<9)
1322
1323/* Control transfer TRB specific fields */
1324#define TRB_DIR_IN (1<<16)
1325#define TRB_TX_TYPE(p) ((p) << 16)
1326#define TRB_DATA_OUT 2
1327#define TRB_DATA_IN 3
1328
1329/* Isochronous TRB specific fields */
1330#define TRB_SIA (1<<31)
1331#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1332
1333struct xhci_generic_trb {
1334 __le32 field[4];
1335};
1336
1337union xhci_trb {
1338 struct xhci_link_trb link;
1339 struct xhci_transfer_event trans_event;
1340 struct xhci_event_cmd event_cmd;
1341 struct xhci_generic_trb generic;
1342};
1343
1344/* TRB bit mask */
1345#define TRB_TYPE_BITMASK (0xfc00)
1346#define TRB_TYPE(p) ((p) << 10)
1347#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1348/* TRB type IDs */
1349/* bulk, interrupt, isoc scatter/gather, and control data stage */
1350#define TRB_NORMAL 1
1351/* setup stage for control transfers */
1352#define TRB_SETUP 2
1353/* data stage for control transfers */
1354#define TRB_DATA 3
1355/* status stage for control transfers */
1356#define TRB_STATUS 4
1357/* isoc transfers */
1358#define TRB_ISOC 5
1359/* TRB for linking ring segments */
1360#define TRB_LINK 6
1361#define TRB_EVENT_DATA 7
1362/* Transfer Ring No-op (not for the command ring) */
1363#define TRB_TR_NOOP 8
1364/* Command TRBs */
1365/* Enable Slot Command */
1366#define TRB_ENABLE_SLOT 9
1367/* Disable Slot Command */
1368#define TRB_DISABLE_SLOT 10
1369/* Address Device Command */
1370#define TRB_ADDR_DEV 11
1371/* Configure Endpoint Command */
1372#define TRB_CONFIG_EP 12
1373/* Evaluate Context Command */
1374#define TRB_EVAL_CONTEXT 13
1375/* Reset Endpoint Command */
1376#define TRB_RESET_EP 14
1377/* Stop Transfer Ring Command */
1378#define TRB_STOP_RING 15
1379/* Set Transfer Ring Dequeue Pointer Command */
1380#define TRB_SET_DEQ 16
1381/* Reset Device Command */
1382#define TRB_RESET_DEV 17
1383/* Force Event Command (opt) */
1384#define TRB_FORCE_EVENT 18
1385/* Negotiate Bandwidth Command (opt) */
1386#define TRB_NEG_BANDWIDTH 19
1387/* Set Latency Tolerance Value Command (opt) */
1388#define TRB_SET_LT 20
1389/* Get port bandwidth Command */
1390#define TRB_GET_BW 21
1391/* Force Header Command - generate a transaction or link management packet */
1392#define TRB_FORCE_HEADER 22
1393/* No-op Command - not for transfer rings */
1394#define TRB_CMD_NOOP 23
1395/* TRB IDs 24-31 reserved */
1396/* Event TRBS */
1397/* Transfer Event */
1398#define TRB_TRANSFER 32
1399/* Command Completion Event */
1400#define TRB_COMPLETION 33
1401/* Port Status Change Event */
1402#define TRB_PORT_STATUS 34
1403/* Bandwidth Request Event (opt) */
1404#define TRB_BANDWIDTH_EVENT 35
1405/* Doorbell Event (opt) */
1406#define TRB_DOORBELL 36
1407/* Host Controller Event */
1408#define TRB_HC_EVENT 37
1409/* Device Notification Event - device sent function wake notification */
1410#define TRB_DEV_NOTE 38
1411/* MFINDEX Wrap Event - microframe counter wrapped */
1412#define TRB_MFINDEX_WRAP 39
1413/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1414
1415/* Nec vendor-specific command completion event. */
1416#define TRB_NEC_CMD_COMP 48
1417/* Get NEC firmware revision. */
1418#define TRB_NEC_GET_FW 49
1419
1420static inline const char *xhci_trb_type_string(u8 type)
1421{
1422 switch (type) {
1423 case TRB_NORMAL:
1424 return "Normal";
1425 case TRB_SETUP:
1426 return "Setup Stage";
1427 case TRB_DATA:
1428 return "Data Stage";
1429 case TRB_STATUS:
1430 return "Status Stage";
1431 case TRB_ISOC:
1432 return "Isoch";
1433 case TRB_LINK:
1434 return "Link";
1435 case TRB_EVENT_DATA:
1436 return "Event Data";
1437 case TRB_TR_NOOP:
1438 return "No-Op";
1439 case TRB_ENABLE_SLOT:
1440 return "Enable Slot Command";
1441 case TRB_DISABLE_SLOT:
1442 return "Disable Slot Command";
1443 case TRB_ADDR_DEV:
1444 return "Address Device Command";
1445 case TRB_CONFIG_EP:
1446 return "Configure Endpoint Command";
1447 case TRB_EVAL_CONTEXT:
1448 return "Evaluate Context Command";
1449 case TRB_RESET_EP:
1450 return "Reset Endpoint Command";
1451 case TRB_STOP_RING:
1452 return "Stop Ring Command";
1453 case TRB_SET_DEQ:
1454 return "Set TR Dequeue Pointer Command";
1455 case TRB_RESET_DEV:
1456 return "Reset Device Command";
1457 case TRB_FORCE_EVENT:
1458 return "Force Event Command";
1459 case TRB_NEG_BANDWIDTH:
1460 return "Negotiate Bandwidth Command";
1461 case TRB_SET_LT:
1462 return "Set Latency Tolerance Value Command";
1463 case TRB_GET_BW:
1464 return "Get Port Bandwidth Command";
1465 case TRB_FORCE_HEADER:
1466 return "Force Header Command";
1467 case TRB_CMD_NOOP:
1468 return "No-Op Command";
1469 case TRB_TRANSFER:
1470 return "Transfer Event";
1471 case TRB_COMPLETION:
1472 return "Command Completion Event";
1473 case TRB_PORT_STATUS:
1474 return "Port Status Change Event";
1475 case TRB_BANDWIDTH_EVENT:
1476 return "Bandwidth Request Event";
1477 case TRB_DOORBELL:
1478 return "Doorbell Event";
1479 case TRB_HC_EVENT:
1480 return "Host Controller Event";
1481 case TRB_DEV_NOTE:
1482 return "Device Notification Event";
1483 case TRB_MFINDEX_WRAP:
1484 return "MFINDEX Wrap Event";
1485 case TRB_NEC_CMD_COMP:
1486 return "NEC Command Completion Event";
1487 case TRB_NEC_GET_FW:
1488 return "NET Get Firmware Revision Command";
1489 default:
1490 return "UNKNOWN";
1491 }
1492}
1493
1494#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1495/* Above, but for __le32 types -- can avoid work by swapping constants: */
1496#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1497 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1498#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1499 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1500
1501#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1502#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1503
1504/*
1505 * TRBS_PER_SEGMENT must be a multiple of 4,
1506 * since the command ring is 64-byte aligned.
1507 * It must also be greater than 16.
1508 */
1509#define TRBS_PER_SEGMENT 256
1510/* Allow two commands + a link TRB, along with any reserved command TRBs */
1511#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1512#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1513#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1514/* TRB buffer pointers can't cross 64KB boundaries */
1515#define TRB_MAX_BUFF_SHIFT 16
1516#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1517/* How much data is left before the 64KB boundary? */
1518#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1519 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1520#define MAX_SOFT_RETRY 3
1521
1522struct xhci_segment {
1523 union xhci_trb *trbs;
1524 /* private to HCD */
1525 struct xhci_segment *next;
1526 dma_addr_t dma;
1527 /* Max packet sized bounce buffer for td-fragmant alignment */
1528 dma_addr_t bounce_dma;
1529 void *bounce_buf;
1530 unsigned int bounce_offs;
1531 unsigned int bounce_len;
1532};
1533
1534struct xhci_td {
1535 struct list_head td_list;
1536 struct list_head cancelled_td_list;
1537 struct urb *urb;
1538 struct xhci_segment *start_seg;
1539 union xhci_trb *first_trb;
1540 union xhci_trb *last_trb;
1541 struct xhci_segment *bounce_seg;
1542 /* actual_length of the URB has already been set */
1543 bool urb_length_set;
1544};
1545
1546/* xHCI command default timeout value */
1547#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1548
1549/* command descriptor */
1550struct xhci_cd {
1551 struct xhci_command *command;
1552 union xhci_trb *cmd_trb;
1553};
1554
1555struct xhci_dequeue_state {
1556 struct xhci_segment *new_deq_seg;
1557 union xhci_trb *new_deq_ptr;
1558 int new_cycle_state;
1559 unsigned int stream_id;
1560};
1561
1562enum xhci_ring_type {
1563 TYPE_CTRL = 0,
1564 TYPE_ISOC,
1565 TYPE_BULK,
1566 TYPE_INTR,
1567 TYPE_STREAM,
1568 TYPE_COMMAND,
1569 TYPE_EVENT,
1570};
1571
1572static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1573{
1574 switch (type) {
1575 case TYPE_CTRL:
1576 return "CTRL";
1577 case TYPE_ISOC:
1578 return "ISOC";
1579 case TYPE_BULK:
1580 return "BULK";
1581 case TYPE_INTR:
1582 return "INTR";
1583 case TYPE_STREAM:
1584 return "STREAM";
1585 case TYPE_COMMAND:
1586 return "CMD";
1587 case TYPE_EVENT:
1588 return "EVENT";
1589 }
1590
1591 return "UNKNOWN";
1592}
1593
1594struct xhci_ring {
1595 struct xhci_segment *first_seg;
1596 struct xhci_segment *last_seg;
1597 union xhci_trb *enqueue;
1598 struct xhci_segment *enq_seg;
1599 union xhci_trb *dequeue;
1600 struct xhci_segment *deq_seg;
1601 struct list_head td_list;
1602 /*
1603 * Write the cycle state into the TRB cycle field to give ownership of
1604 * the TRB to the host controller (if we are the producer), or to check
1605 * if we own the TRB (if we are the consumer). See section 4.9.1.
1606 */
1607 u32 cycle_state;
1608 unsigned int err_count;
1609 unsigned int stream_id;
1610 unsigned int num_segs;
1611 unsigned int num_trbs_free;
1612 unsigned int num_trbs_free_temp;
1613 unsigned int bounce_buf_len;
1614 enum xhci_ring_type type;
1615 bool last_td_was_short;
1616 struct radix_tree_root *trb_address_map;
1617};
1618
1619struct xhci_erst_entry {
1620 /* 64-bit event ring segment address */
1621 __le64 seg_addr;
1622 __le32 seg_size;
1623 /* Set to zero */
1624 __le32 rsvd;
1625};
1626
1627struct xhci_erst {
1628 struct xhci_erst_entry *entries;
1629 unsigned int num_entries;
1630 /* xhci->event_ring keeps track of segment dma addresses */
1631 dma_addr_t erst_dma_addr;
1632 /* Num entries the ERST can contain */
1633 unsigned int erst_size;
1634};
1635
1636struct xhci_scratchpad {
1637 u64 *sp_array;
1638 dma_addr_t sp_dma;
1639 void **sp_buffers;
1640};
1641
1642struct urb_priv {
1643 int num_tds;
1644 int num_tds_done;
1645 struct xhci_td td[];
1646};
1647
1648/*
1649 * Each segment table entry is 4*32bits long. 1K seems like an ok size:
1650 * (1K bytes * 8bytes/bit) / (4*32 bits) = 64 segment entries in the table,
1651 * meaning 64 ring segments.
1652 * Initial allocated size of the ERST, in number of entries */
1653#define ERST_NUM_SEGS 1
1654/* Initial allocated size of the ERST, in number of entries */
1655#define ERST_SIZE 64
1656/* Initial number of event segment rings allocated */
1657#define ERST_ENTRIES 1
1658/* Poll every 60 seconds */
1659#define POLL_TIMEOUT 60
1660/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1661#define XHCI_STOP_EP_CMD_TIMEOUT 5
1662/* XXX: Make these module parameters */
1663
1664struct s3_save {
1665 u32 command;
1666 u32 dev_nt;
1667 u64 dcbaa_ptr;
1668 u32 config_reg;
1669 u32 irq_pending;
1670 u32 irq_control;
1671 u32 erst_size;
1672 u64 erst_base;
1673 u64 erst_dequeue;
1674};
1675
1676/* Use for lpm */
1677struct dev_info {
1678 u32 dev_id;
1679 struct list_head list;
1680};
1681
1682struct xhci_bus_state {
1683 unsigned long bus_suspended;
1684 unsigned long next_statechange;
1685
1686 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1687 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1688 u32 port_c_suspend;
1689 u32 suspended_ports;
1690 u32 port_remote_wakeup;
1691 unsigned long resume_done[USB_MAXCHILDREN];
1692 /* which ports have started to resume */
1693 unsigned long resuming_ports;
1694 /* Which ports are waiting on RExit to U0 transition. */
1695 unsigned long rexit_ports;
1696 struct completion rexit_done[USB_MAXCHILDREN];
1697 struct completion u3exit_done[USB_MAXCHILDREN];
1698};
1699
1700
1701/*
1702 * It can take up to 20 ms to transition from RExit to U0 on the
1703 * Intel Lynx Point LP xHCI host.
1704 */
1705#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1706struct xhci_port_cap {
1707 u32 *psi; /* array of protocol speed ID entries */
1708 u8 psi_count;
1709 u8 psi_uid_count;
1710 u8 maj_rev;
1711 u8 min_rev;
1712};
1713
1714struct xhci_port {
1715 __le32 __iomem *addr;
1716 int hw_portnum;
1717 int hcd_portnum;
1718 struct xhci_hub *rhub;
1719 struct xhci_port_cap *port_cap;
1720};
1721
1722struct xhci_hub {
1723 struct xhci_port **ports;
1724 unsigned int num_ports;
1725 struct usb_hcd *hcd;
1726 /* keep track of bus suspend info */
1727 struct xhci_bus_state bus_state;
1728 /* supported prococol extended capabiliy values */
1729 u8 maj_rev;
1730 u8 min_rev;
1731};
1732
1733/* There is one xhci_hcd structure per controller */
1734struct xhci_hcd {
1735 struct usb_hcd *main_hcd;
1736 struct usb_hcd *shared_hcd;
1737 /* glue to PCI and HCD framework */
1738 struct xhci_cap_regs __iomem *cap_regs;
1739 struct xhci_op_regs __iomem *op_regs;
1740 struct xhci_run_regs __iomem *run_regs;
1741 struct xhci_doorbell_array __iomem *dba;
1742 /* Our HCD's current interrupter register set */
1743 struct xhci_intr_reg __iomem *ir_set;
1744
1745 /* Cached register copies of read-only HC data */
1746 __u32 hcs_params1;
1747 __u32 hcs_params2;
1748 __u32 hcs_params3;
1749 __u32 hcc_params;
1750 __u32 hcc_params2;
1751
1752 spinlock_t lock;
1753
1754 /* packed release number */
1755 u8 sbrn;
1756 u16 hci_version;
1757 u8 max_slots;
1758 u8 max_interrupters;
1759 u8 max_ports;
1760 u8 isoc_threshold;
1761 /* imod_interval in ns (I * 250ns) */
1762 u32 imod_interval;
1763 int event_ring_max;
1764 /* 4KB min, 128MB max */
1765 int page_size;
1766 /* Valid values are 12 to 20, inclusive */
1767 int page_shift;
1768 /* msi-x vectors */
1769 int msix_count;
1770 /* optional clocks */
1771 struct clk *clk;
1772 struct clk *reg_clk;
1773 /* data structures */
1774 struct xhci_device_context_array *dcbaa;
1775 struct xhci_ring *cmd_ring;
1776 unsigned int cmd_ring_state;
1777#define CMD_RING_STATE_RUNNING (1 << 0)
1778#define CMD_RING_STATE_ABORTED (1 << 1)
1779#define CMD_RING_STATE_STOPPED (1 << 2)
1780 struct list_head cmd_list;
1781 unsigned int cmd_ring_reserved_trbs;
1782 struct delayed_work cmd_timer;
1783 struct completion cmd_ring_stop_completion;
1784 struct xhci_command *current_cmd;
1785 struct xhci_ring *event_ring;
1786 struct xhci_erst erst;
1787 /* Scratchpad */
1788 struct xhci_scratchpad *scratchpad;
1789 /* Store LPM test failed devices' information */
1790 struct list_head lpm_failed_devs;
1791
1792 /* slot enabling and address device helpers */
1793 /* these are not thread safe so use mutex */
1794 struct mutex mutex;
1795 /* For USB 3.0 LPM enable/disable. */
1796 struct xhci_command *lpm_command;
1797 /* Internal mirror of the HW's dcbaa */
1798 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1799 /* For keeping track of bandwidth domains per roothub. */
1800 struct xhci_root_port_bw_info *rh_bw;
1801
1802 /* DMA pools */
1803 struct dma_pool *device_pool;
1804 struct dma_pool *segment_pool;
1805 struct dma_pool *small_streams_pool;
1806 struct dma_pool *medium_streams_pool;
1807
1808 /* Host controller watchdog timer structures */
1809 unsigned int xhc_state;
1810
1811 u32 command;
1812 struct s3_save s3;
1813/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1814 *
1815 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1816 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1817 * that sees this status (other than the timer that set it) should stop touching
1818 * hardware immediately. Interrupt handlers should return immediately when
1819 * they see this status (any time they drop and re-acquire xhci->lock).
1820 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1821 * putting the TD on the canceled list, etc.
1822 *
1823 * There are no reports of xHCI host controllers that display this issue.
1824 */
1825#define XHCI_STATE_DYING (1 << 0)
1826#define XHCI_STATE_HALTED (1 << 1)
1827#define XHCI_STATE_REMOVING (1 << 2)
1828 unsigned long long quirks;
1829#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1830#define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1831#define XHCI_NEC_HOST BIT_ULL(2)
1832#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1833#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1834/*
1835 * Certain Intel host controllers have a limit to the number of endpoint
1836 * contexts they can handle. Ideally, they would signal that they can't handle
1837 * anymore endpoint contexts by returning a Resource Error for the Configure
1838 * Endpoint command, but they don't. Instead they expect software to keep track
1839 * of the number of active endpoints for them, across configure endpoint
1840 * commands, reset device commands, disable slot commands, and address device
1841 * commands.
1842 */
1843#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1844#define XHCI_BROKEN_MSI BIT_ULL(6)
1845#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1846#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1847#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1848#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1849#define XHCI_LPM_SUPPORT BIT_ULL(11)
1850#define XHCI_INTEL_HOST BIT_ULL(12)
1851#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1852#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1853#define XHCI_AVOID_BEI BIT_ULL(15)
1854#define XHCI_PLAT BIT_ULL(16)
1855#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1856#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1857/* For controllers with a broken beyond repair streams implementation */
1858#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1859#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1860#define XHCI_MTK_HOST BIT_ULL(21)
1861#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1862#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1863#define XHCI_MISSING_CAS BIT_ULL(24)
1864/* For controller with a broken Port Disable implementation */
1865#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1866#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1867#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1868#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1869#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1870#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1871#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1872#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1873#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1874#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1875#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1876#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1877
1878 unsigned int num_active_eps;
1879 unsigned int limit_active_eps;
1880 struct xhci_port *hw_ports;
1881 struct xhci_hub usb2_rhub;
1882 struct xhci_hub usb3_rhub;
1883 /* support xHCI 1.0 spec USB2 hardware LPM */
1884 unsigned hw_lpm_support:1;
1885 /* Broken Suspend flag for SNPS Suspend resume issue */
1886 unsigned broken_suspend:1;
1887 /* cached usb2 extened protocol capabilites */
1888 u32 *ext_caps;
1889 unsigned int num_ext_caps;
1890 /* cached extended protocol port capabilities */
1891 struct xhci_port_cap *port_caps;
1892 unsigned int num_port_caps;
1893 /* Compliance Mode Recovery Data */
1894 struct timer_list comp_mode_recovery_timer;
1895 u32 port_status_u0;
1896 u16 test_mode;
1897/* Compliance Mode Timer Triggered every 2 seconds */
1898#define COMP_MODE_RCVRY_MSECS 2000
1899
1900 struct dentry *debugfs_root;
1901 struct dentry *debugfs_slots;
1902 struct list_head regset_list;
1903
1904 void *dbc;
1905 /* platform-specific data -- must come last */
1906 unsigned long priv[] __aligned(sizeof(s64));
1907};
1908
1909/* Platform specific overrides to generic XHCI hc_driver ops */
1910struct xhci_driver_overrides {
1911 size_t extra_priv_size;
1912 int (*reset)(struct usb_hcd *hcd);
1913 int (*start)(struct usb_hcd *hcd);
1914};
1915
1916#define XHCI_CFC_DELAY 10
1917
1918/* convert between an HCD pointer and the corresponding EHCI_HCD */
1919static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1920{
1921 struct usb_hcd *primary_hcd;
1922
1923 if (usb_hcd_is_primary_hcd(hcd))
1924 primary_hcd = hcd;
1925 else
1926 primary_hcd = hcd->primary_hcd;
1927
1928 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1929}
1930
1931static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1932{
1933 return xhci->main_hcd;
1934}
1935
1936#define xhci_dbg(xhci, fmt, args...) \
1937 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1938#define xhci_err(xhci, fmt, args...) \
1939 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1940#define xhci_warn(xhci, fmt, args...) \
1941 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1942#define xhci_warn_ratelimited(xhci, fmt, args...) \
1943 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1944#define xhci_info(xhci, fmt, args...) \
1945 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1946
1947/*
1948 * Registers should always be accessed with double word or quad word accesses.
1949 *
1950 * Some xHCI implementations may support 64-bit address pointers. Registers
1951 * with 64-bit address pointers should be written to with dword accesses by
1952 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1953 * xHCI implementations that do not support 64-bit address pointers will ignore
1954 * the high dword, and write order is irrelevant.
1955 */
1956static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1957 __le64 __iomem *regs)
1958{
1959 return lo_hi_readq(regs);
1960}
1961static inline void xhci_write_64(struct xhci_hcd *xhci,
1962 const u64 val, __le64 __iomem *regs)
1963{
1964 lo_hi_writeq(val, regs);
1965}
1966
1967static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1968{
1969 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1970}
1971
1972/* xHCI debugging */
1973char *xhci_get_slot_state(struct xhci_hcd *xhci,
1974 struct xhci_container_ctx *ctx);
1975void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1976 const char *fmt, ...);
1977
1978/* xHCI memory management */
1979void xhci_mem_cleanup(struct xhci_hcd *xhci);
1980int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1981void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1982int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1983int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1984void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1985 struct usb_device *udev);
1986unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1987unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1988unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1989void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1990void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1991 struct xhci_virt_device *virt_dev,
1992 int old_active_eps);
1993void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1994void xhci_update_bw_info(struct xhci_hcd *xhci,
1995 struct xhci_container_ctx *in_ctx,
1996 struct xhci_input_control_ctx *ctrl_ctx,
1997 struct xhci_virt_device *virt_dev);
1998void xhci_endpoint_copy(struct xhci_hcd *xhci,
1999 struct xhci_container_ctx *in_ctx,
2000 struct xhci_container_ctx *out_ctx,
2001 unsigned int ep_index);
2002void xhci_slot_copy(struct xhci_hcd *xhci,
2003 struct xhci_container_ctx *in_ctx,
2004 struct xhci_container_ctx *out_ctx);
2005int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2006 struct usb_device *udev, struct usb_host_endpoint *ep,
2007 gfp_t mem_flags);
2008struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2009 unsigned int num_segs, unsigned int cycle_state,
2010 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2011void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2012int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2013 unsigned int num_trbs, gfp_t flags);
2014int xhci_alloc_erst(struct xhci_hcd *xhci,
2015 struct xhci_ring *evt_ring,
2016 struct xhci_erst *erst,
2017 gfp_t flags);
2018void xhci_initialize_ring_info(struct xhci_ring *ring,
2019 unsigned int cycle_state);
2020void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2021void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2022 struct xhci_virt_device *virt_dev,
2023 unsigned int ep_index);
2024struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2025 unsigned int num_stream_ctxs,
2026 unsigned int num_streams,
2027 unsigned int max_packet, gfp_t flags);
2028void xhci_free_stream_info(struct xhci_hcd *xhci,
2029 struct xhci_stream_info *stream_info);
2030void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2031 struct xhci_ep_ctx *ep_ctx,
2032 struct xhci_stream_info *stream_info);
2033void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2034 struct xhci_virt_ep *ep);
2035void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2036 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2037struct xhci_ring *xhci_dma_to_transfer_ring(
2038 struct xhci_virt_ep *ep,
2039 u64 address);
2040struct xhci_ring *xhci_stream_id_to_ring(
2041 struct xhci_virt_device *dev,
2042 unsigned int ep_index,
2043 unsigned int stream_id);
2044struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2045 bool allocate_completion, gfp_t mem_flags);
2046struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2047 bool allocate_completion, gfp_t mem_flags);
2048void xhci_urb_free_priv(struct urb_priv *urb_priv);
2049void xhci_free_command(struct xhci_hcd *xhci,
2050 struct xhci_command *command);
2051struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2052 int type, gfp_t flags);
2053void xhci_free_container_ctx(struct xhci_hcd *xhci,
2054 struct xhci_container_ctx *ctx);
2055
2056/* xHCI host controller glue */
2057typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2058int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
2059void xhci_quiesce(struct xhci_hcd *xhci);
2060int xhci_halt(struct xhci_hcd *xhci);
2061int xhci_start(struct xhci_hcd *xhci);
2062int xhci_reset(struct xhci_hcd *xhci);
2063int xhci_run(struct usb_hcd *hcd);
2064int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2065void xhci_shutdown(struct usb_hcd *hcd);
2066void xhci_init_driver(struct hc_driver *drv,
2067 const struct xhci_driver_overrides *over);
2068int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2069int xhci_ext_cap_init(struct xhci_hcd *xhci);
2070
2071int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2072int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2073
2074irqreturn_t xhci_irq(struct usb_hcd *hcd);
2075irqreturn_t xhci_msi_irq(int irq, void *hcd);
2076int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2077int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2078 struct xhci_virt_device *virt_dev,
2079 struct usb_device *hdev,
2080 struct usb_tt *tt, gfp_t mem_flags);
2081
2082/* xHCI ring, segment, TRB, and TD functions */
2083dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2084struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2085 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2086 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2087int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2088void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2089int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2090 u32 trb_type, u32 slot_id);
2091int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2092 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2093int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2094 u32 field1, u32 field2, u32 field3, u32 field4);
2095int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2096 int slot_id, unsigned int ep_index, int suspend);
2097int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2098 int slot_id, unsigned int ep_index);
2099int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2100 int slot_id, unsigned int ep_index);
2101int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2102 int slot_id, unsigned int ep_index);
2103int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2104 struct urb *urb, int slot_id, unsigned int ep_index);
2105int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2106 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2107 bool command_must_succeed);
2108int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2109 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2110int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2111 int slot_id, unsigned int ep_index,
2112 enum xhci_ep_reset_type reset_type);
2113int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2114 u32 slot_id);
2115void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
2116 unsigned int slot_id, unsigned int ep_index,
2117 unsigned int stream_id, struct xhci_td *cur_td,
2118 struct xhci_dequeue_state *state);
2119void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
2120 unsigned int slot_id, unsigned int ep_index,
2121 struct xhci_dequeue_state *deq_state);
2122void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2123 unsigned int ep_index, unsigned int stream_id,
2124 struct xhci_td *td);
2125void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2126void xhci_handle_command_timeout(struct work_struct *work);
2127
2128void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2129 unsigned int ep_index, unsigned int stream_id);
2130void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2131 unsigned int slot_id,
2132 unsigned int ep_index);
2133void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2134void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2135unsigned int count_trbs(u64 addr, u64 len);
2136
2137/* xHCI roothub code */
2138void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2139 u32 link_state);
2140void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2141 u32 port_bit);
2142int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2143 char *buf, u16 wLength);
2144int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2145int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2146struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2147
2148void xhci_hc_died(struct xhci_hcd *xhci);
2149
2150#ifdef CONFIG_PM
2151int xhci_bus_suspend(struct usb_hcd *hcd);
2152int xhci_bus_resume(struct usb_hcd *hcd);
2153unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2154#else
2155#define xhci_bus_suspend NULL
2156#define xhci_bus_resume NULL
2157#define xhci_get_resuming_ports NULL
2158#endif /* CONFIG_PM */
2159
2160u32 xhci_port_state_to_neutral(u32 state);
2161int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2162 u16 port);
2163void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2164
2165/* xHCI contexts */
2166struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2167struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2168struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2169
2170struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2171 unsigned int slot_id, unsigned int ep_index,
2172 unsigned int stream_id);
2173
2174static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2175 struct urb *urb)
2176{
2177 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2178 xhci_get_endpoint_index(&urb->ep->desc),
2179 urb->stream_id);
2180}
2181
2182/*
2183 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2184 * them anyways as we where unable to find a device that matches the
2185 * constraints.
2186 */
2187static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2188{
2189 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2190 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2191 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2192 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2193 !urb->num_sgs)
2194 return true;
2195
2196 return false;
2197}
2198
2199static inline char *xhci_slot_state_string(u32 state)
2200{
2201 switch (state) {
2202 case SLOT_STATE_ENABLED:
2203 return "enabled/disabled";
2204 case SLOT_STATE_DEFAULT:
2205 return "default";
2206 case SLOT_STATE_ADDRESSED:
2207 return "addressed";
2208 case SLOT_STATE_CONFIGURED:
2209 return "configured";
2210 default:
2211 return "reserved";
2212 }
2213}
2214
2215static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2216 u32 field3)
2217{
2218 static char str[256];
2219 int type = TRB_FIELD_TO_TYPE(field3);
2220
2221 switch (type) {
2222 case TRB_LINK:
2223 sprintf(str,
2224 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2225 field1, field0, GET_INTR_TARGET(field2),
2226 xhci_trb_type_string(type),
2227 field3 & TRB_IOC ? 'I' : 'i',
2228 field3 & TRB_CHAIN ? 'C' : 'c',
2229 field3 & TRB_TC ? 'T' : 't',
2230 field3 & TRB_CYCLE ? 'C' : 'c');
2231 break;
2232 case TRB_TRANSFER:
2233 case TRB_COMPLETION:
2234 case TRB_PORT_STATUS:
2235 case TRB_BANDWIDTH_EVENT:
2236 case TRB_DOORBELL:
2237 case TRB_HC_EVENT:
2238 case TRB_DEV_NOTE:
2239 case TRB_MFINDEX_WRAP:
2240 sprintf(str,
2241 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2242 field1, field0,
2243 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2244 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2245 /* Macro decrements 1, maybe it shouldn't?!? */
2246 TRB_TO_EP_INDEX(field3) + 1,
2247 xhci_trb_type_string(type),
2248 field3 & EVENT_DATA ? 'E' : 'e',
2249 field3 & TRB_CYCLE ? 'C' : 'c');
2250
2251 break;
2252 case TRB_SETUP:
2253 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2254 field0 & 0xff,
2255 (field0 & 0xff00) >> 8,
2256 (field0 & 0xff000000) >> 24,
2257 (field0 & 0xff0000) >> 16,
2258 (field1 & 0xff00) >> 8,
2259 field1 & 0xff,
2260 (field1 & 0xff000000) >> 16 |
2261 (field1 & 0xff0000) >> 16,
2262 TRB_LEN(field2), GET_TD_SIZE(field2),
2263 GET_INTR_TARGET(field2),
2264 xhci_trb_type_string(type),
2265 field3 & TRB_IDT ? 'I' : 'i',
2266 field3 & TRB_IOC ? 'I' : 'i',
2267 field3 & TRB_CYCLE ? 'C' : 'c');
2268 break;
2269 case TRB_DATA:
2270 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2271 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2272 GET_INTR_TARGET(field2),
2273 xhci_trb_type_string(type),
2274 field3 & TRB_IDT ? 'I' : 'i',
2275 field3 & TRB_IOC ? 'I' : 'i',
2276 field3 & TRB_CHAIN ? 'C' : 'c',
2277 field3 & TRB_NO_SNOOP ? 'S' : 's',
2278 field3 & TRB_ISP ? 'I' : 'i',
2279 field3 & TRB_ENT ? 'E' : 'e',
2280 field3 & TRB_CYCLE ? 'C' : 'c');
2281 break;
2282 case TRB_STATUS:
2283 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2284 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2285 GET_INTR_TARGET(field2),
2286 xhci_trb_type_string(type),
2287 field3 & TRB_IOC ? 'I' : 'i',
2288 field3 & TRB_CHAIN ? 'C' : 'c',
2289 field3 & TRB_ENT ? 'E' : 'e',
2290 field3 & TRB_CYCLE ? 'C' : 'c');
2291 break;
2292 case TRB_NORMAL:
2293 case TRB_ISOC:
2294 case TRB_EVENT_DATA:
2295 case TRB_TR_NOOP:
2296 sprintf(str,
2297 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2298 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2299 GET_INTR_TARGET(field2),
2300 xhci_trb_type_string(type),
2301 field3 & TRB_BEI ? 'B' : 'b',
2302 field3 & TRB_IDT ? 'I' : 'i',
2303 field3 & TRB_IOC ? 'I' : 'i',
2304 field3 & TRB_CHAIN ? 'C' : 'c',
2305 field3 & TRB_NO_SNOOP ? 'S' : 's',
2306 field3 & TRB_ISP ? 'I' : 'i',
2307 field3 & TRB_ENT ? 'E' : 'e',
2308 field3 & TRB_CYCLE ? 'C' : 'c');
2309 break;
2310
2311 case TRB_CMD_NOOP:
2312 case TRB_ENABLE_SLOT:
2313 sprintf(str,
2314 "%s: flags %c",
2315 xhci_trb_type_string(type),
2316 field3 & TRB_CYCLE ? 'C' : 'c');
2317 break;
2318 case TRB_DISABLE_SLOT:
2319 case TRB_NEG_BANDWIDTH:
2320 sprintf(str,
2321 "%s: slot %d flags %c",
2322 xhci_trb_type_string(type),
2323 TRB_TO_SLOT_ID(field3),
2324 field3 & TRB_CYCLE ? 'C' : 'c');
2325 break;
2326 case TRB_ADDR_DEV:
2327 sprintf(str,
2328 "%s: ctx %08x%08x slot %d flags %c:%c",
2329 xhci_trb_type_string(type),
2330 field1, field0,
2331 TRB_TO_SLOT_ID(field3),
2332 field3 & TRB_BSR ? 'B' : 'b',
2333 field3 & TRB_CYCLE ? 'C' : 'c');
2334 break;
2335 case TRB_CONFIG_EP:
2336 sprintf(str,
2337 "%s: ctx %08x%08x slot %d flags %c:%c",
2338 xhci_trb_type_string(type),
2339 field1, field0,
2340 TRB_TO_SLOT_ID(field3),
2341 field3 & TRB_DC ? 'D' : 'd',
2342 field3 & TRB_CYCLE ? 'C' : 'c');
2343 break;
2344 case TRB_EVAL_CONTEXT:
2345 sprintf(str,
2346 "%s: ctx %08x%08x slot %d flags %c",
2347 xhci_trb_type_string(type),
2348 field1, field0,
2349 TRB_TO_SLOT_ID(field3),
2350 field3 & TRB_CYCLE ? 'C' : 'c');
2351 break;
2352 case TRB_RESET_EP:
2353 sprintf(str,
2354 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2355 xhci_trb_type_string(type),
2356 field1, field0,
2357 TRB_TO_SLOT_ID(field3),
2358 /* Macro decrements 1, maybe it shouldn't?!? */
2359 TRB_TO_EP_INDEX(field3) + 1,
2360 field3 & TRB_TSP ? 'T' : 't',
2361 field3 & TRB_CYCLE ? 'C' : 'c');
2362 break;
2363 case TRB_STOP_RING:
2364 sprintf(str,
2365 "%s: slot %d sp %d ep %d flags %c",
2366 xhci_trb_type_string(type),
2367 TRB_TO_SLOT_ID(field3),
2368 TRB_TO_SUSPEND_PORT(field3),
2369 /* Macro decrements 1, maybe it shouldn't?!? */
2370 TRB_TO_EP_INDEX(field3) + 1,
2371 field3 & TRB_CYCLE ? 'C' : 'c');
2372 break;
2373 case TRB_SET_DEQ:
2374 sprintf(str,
2375 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2376 xhci_trb_type_string(type),
2377 field1, field0,
2378 TRB_TO_STREAM_ID(field2),
2379 TRB_TO_SLOT_ID(field3),
2380 /* Macro decrements 1, maybe it shouldn't?!? */
2381 TRB_TO_EP_INDEX(field3) + 1,
2382 field3 & TRB_CYCLE ? 'C' : 'c');
2383 break;
2384 case TRB_RESET_DEV:
2385 sprintf(str,
2386 "%s: slot %d flags %c",
2387 xhci_trb_type_string(type),
2388 TRB_TO_SLOT_ID(field3),
2389 field3 & TRB_CYCLE ? 'C' : 'c');
2390 break;
2391 case TRB_FORCE_EVENT:
2392 sprintf(str,
2393 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2394 xhci_trb_type_string(type),
2395 field1, field0,
2396 TRB_TO_VF_INTR_TARGET(field2),
2397 TRB_TO_VF_ID(field3),
2398 field3 & TRB_CYCLE ? 'C' : 'c');
2399 break;
2400 case TRB_SET_LT:
2401 sprintf(str,
2402 "%s: belt %d flags %c",
2403 xhci_trb_type_string(type),
2404 TRB_TO_BELT(field3),
2405 field3 & TRB_CYCLE ? 'C' : 'c');
2406 break;
2407 case TRB_GET_BW:
2408 sprintf(str,
2409 "%s: ctx %08x%08x slot %d speed %d flags %c",
2410 xhci_trb_type_string(type),
2411 field1, field0,
2412 TRB_TO_SLOT_ID(field3),
2413 TRB_TO_DEV_SPEED(field3),
2414 field3 & TRB_CYCLE ? 'C' : 'c');
2415 break;
2416 case TRB_FORCE_HEADER:
2417 sprintf(str,
2418 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2419 xhci_trb_type_string(type),
2420 field2, field1, field0 & 0xffffffe0,
2421 TRB_TO_PACKET_TYPE(field0),
2422 TRB_TO_ROOTHUB_PORT(field3),
2423 field3 & TRB_CYCLE ? 'C' : 'c');
2424 break;
2425 default:
2426 sprintf(str,
2427 "type '%s' -> raw %08x %08x %08x %08x",
2428 xhci_trb_type_string(type),
2429 field0, field1, field2, field3);
2430 }
2431
2432 return str;
2433}
2434
2435static inline const char *xhci_decode_ctrl_ctx(unsigned long drop,
2436 unsigned long add)
2437{
2438 static char str[1024];
2439 unsigned int bit;
2440 int ret = 0;
2441
2442 if (drop) {
2443 ret = sprintf(str, "Drop:");
2444 for_each_set_bit(bit, &drop, 32)
2445 ret += sprintf(str + ret, " %d%s",
2446 bit / 2,
2447 bit % 2 ? "in":"out");
2448 ret += sprintf(str + ret, ", ");
2449 }
2450
2451 if (add) {
2452 ret += sprintf(str + ret, "Add:%s%s",
2453 (add & SLOT_FLAG) ? " slot":"",
2454 (add & EP0_FLAG) ? " ep0":"");
2455 add &= ~(SLOT_FLAG | EP0_FLAG);
2456 for_each_set_bit(bit, &add, 32)
2457 ret += sprintf(str + ret, " %d%s",
2458 bit / 2,
2459 bit % 2 ? "in":"out");
2460 }
2461 return str;
2462}
2463
2464static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2465 u32 tt_info, u32 state)
2466{
2467 static char str[1024];
2468 u32 speed;
2469 u32 hub;
2470 u32 mtt;
2471 int ret = 0;
2472
2473 speed = info & DEV_SPEED;
2474 hub = info & DEV_HUB;
2475 mtt = info & DEV_MTT;
2476
2477 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2478 info & ROUTE_STRING_MASK,
2479 ({ char *s;
2480 switch (speed) {
2481 case SLOT_SPEED_FS:
2482 s = "full-speed";
2483 break;
2484 case SLOT_SPEED_LS:
2485 s = "low-speed";
2486 break;
2487 case SLOT_SPEED_HS:
2488 s = "high-speed";
2489 break;
2490 case SLOT_SPEED_SS:
2491 s = "super-speed";
2492 break;
2493 case SLOT_SPEED_SSP:
2494 s = "super-speed plus";
2495 break;
2496 default:
2497 s = "UNKNOWN speed";
2498 } s; }),
2499 mtt ? " multi-TT" : "",
2500 hub ? " Hub" : "",
2501 (info & LAST_CTX_MASK) >> 27,
2502 info2 & MAX_EXIT,
2503 DEVINFO_TO_ROOT_HUB_PORT(info2),
2504 DEVINFO_TO_MAX_PORTS(info2));
2505
2506 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2507 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2508 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2509 state & DEV_ADDR_MASK,
2510 xhci_slot_state_string(GET_SLOT_STATE(state)));
2511
2512 return str;
2513}
2514
2515
2516static inline const char *xhci_portsc_link_state_string(u32 portsc)
2517{
2518 switch (portsc & PORT_PLS_MASK) {
2519 case XDEV_U0:
2520 return "U0";
2521 case XDEV_U1:
2522 return "U1";
2523 case XDEV_U2:
2524 return "U2";
2525 case XDEV_U3:
2526 return "U3";
2527 case XDEV_DISABLED:
2528 return "Disabled";
2529 case XDEV_RXDETECT:
2530 return "RxDetect";
2531 case XDEV_INACTIVE:
2532 return "Inactive";
2533 case XDEV_POLLING:
2534 return "Polling";
2535 case XDEV_RECOVERY:
2536 return "Recovery";
2537 case XDEV_HOT_RESET:
2538 return "Hot Reset";
2539 case XDEV_COMP_MODE:
2540 return "Compliance mode";
2541 case XDEV_TEST_MODE:
2542 return "Test mode";
2543 case XDEV_RESUME:
2544 return "Resume";
2545 default:
2546 break;
2547 }
2548 return "Unknown";
2549}
2550
2551static inline const char *xhci_decode_portsc(u32 portsc)
2552{
2553 static char str[256];
2554 int ret;
2555
2556 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2557 portsc & PORT_POWER ? "Powered" : "Powered-off",
2558 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2559 portsc & PORT_PE ? "Enabled" : "Disabled",
2560 xhci_portsc_link_state_string(portsc),
2561 DEV_PORT_SPEED(portsc));
2562
2563 if (portsc & PORT_OC)
2564 ret += sprintf(str + ret, "OverCurrent ");
2565 if (portsc & PORT_RESET)
2566 ret += sprintf(str + ret, "In-Reset ");
2567
2568 ret += sprintf(str + ret, "Change: ");
2569 if (portsc & PORT_CSC)
2570 ret += sprintf(str + ret, "CSC ");
2571 if (portsc & PORT_PEC)
2572 ret += sprintf(str + ret, "PEC ");
2573 if (portsc & PORT_WRC)
2574 ret += sprintf(str + ret, "WRC ");
2575 if (portsc & PORT_OCC)
2576 ret += sprintf(str + ret, "OCC ");
2577 if (portsc & PORT_RC)
2578 ret += sprintf(str + ret, "PRC ");
2579 if (portsc & PORT_PLC)
2580 ret += sprintf(str + ret, "PLC ");
2581 if (portsc & PORT_CEC)
2582 ret += sprintf(str + ret, "CEC ");
2583 if (portsc & PORT_CAS)
2584 ret += sprintf(str + ret, "CAS ");
2585
2586 ret += sprintf(str + ret, "Wake: ");
2587 if (portsc & PORT_WKCONN_E)
2588 ret += sprintf(str + ret, "WCE ");
2589 if (portsc & PORT_WKDISC_E)
2590 ret += sprintf(str + ret, "WDE ");
2591 if (portsc & PORT_WKOC_E)
2592 ret += sprintf(str + ret, "WOE ");
2593
2594 return str;
2595}
2596
2597static inline const char *xhci_decode_usbsts(u32 usbsts)
2598{
2599 static char str[256];
2600 int ret = 0;
2601
2602 if (usbsts == ~(u32)0)
2603 return " 0xffffffff";
2604 if (usbsts & STS_HALT)
2605 ret += sprintf(str + ret, " HCHalted");
2606 if (usbsts & STS_FATAL)
2607 ret += sprintf(str + ret, " HSE");
2608 if (usbsts & STS_EINT)
2609 ret += sprintf(str + ret, " EINT");
2610 if (usbsts & STS_PORT)
2611 ret += sprintf(str + ret, " PCD");
2612 if (usbsts & STS_SAVE)
2613 ret += sprintf(str + ret, " SSS");
2614 if (usbsts & STS_RESTORE)
2615 ret += sprintf(str + ret, " RSS");
2616 if (usbsts & STS_SRE)
2617 ret += sprintf(str + ret, " SRE");
2618 if (usbsts & STS_CNR)
2619 ret += sprintf(str + ret, " CNR");
2620 if (usbsts & STS_HCE)
2621 ret += sprintf(str + ret, " HCE");
2622
2623 return str;
2624}
2625
2626static inline const char *xhci_decode_doorbell(u32 slot, u32 doorbell)
2627{
2628 static char str[256];
2629 u8 ep;
2630 u16 stream;
2631 int ret;
2632
2633 ep = (doorbell & 0xff);
2634 stream = doorbell >> 16;
2635
2636 if (slot == 0) {
2637 sprintf(str, "Command Ring %d", doorbell);
2638 return str;
2639 }
2640 ret = sprintf(str, "Slot %d ", slot);
2641 if (ep > 0 && ep < 32)
2642 ret = sprintf(str + ret, "ep%d%s",
2643 ep / 2,
2644 ep % 2 ? "in" : "out");
2645 else if (ep == 0 || ep < 248)
2646 ret = sprintf(str + ret, "Reserved %d", ep);
2647 else
2648 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2649 if (stream)
2650 ret = sprintf(str + ret, " Stream %d", stream);
2651
2652 return str;
2653}
2654
2655static inline const char *xhci_ep_state_string(u8 state)
2656{
2657 switch (state) {
2658 case EP_STATE_DISABLED:
2659 return "disabled";
2660 case EP_STATE_RUNNING:
2661 return "running";
2662 case EP_STATE_HALTED:
2663 return "halted";
2664 case EP_STATE_STOPPED:
2665 return "stopped";
2666 case EP_STATE_ERROR:
2667 return "error";
2668 default:
2669 return "INVALID";
2670 }
2671}
2672
2673static inline const char *xhci_ep_type_string(u8 type)
2674{
2675 switch (type) {
2676 case ISOC_OUT_EP:
2677 return "Isoc OUT";
2678 case BULK_OUT_EP:
2679 return "Bulk OUT";
2680 case INT_OUT_EP:
2681 return "Int OUT";
2682 case CTRL_EP:
2683 return "Ctrl";
2684 case ISOC_IN_EP:
2685 return "Isoc IN";
2686 case BULK_IN_EP:
2687 return "Bulk IN";
2688 case INT_IN_EP:
2689 return "Int IN";
2690 default:
2691 return "INVALID";
2692 }
2693}
2694
2695static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2696 u32 tx_info)
2697{
2698 static char str[1024];
2699 int ret;
2700
2701 u32 esit;
2702 u16 maxp;
2703 u16 avg;
2704
2705 u8 max_pstr;
2706 u8 ep_state;
2707 u8 interval;
2708 u8 ep_type;
2709 u8 burst;
2710 u8 cerr;
2711 u8 mult;
2712
2713 bool lsa;
2714 bool hid;
2715
2716 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2717 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2718
2719 ep_state = info & EP_STATE_MASK;
2720 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2721 interval = CTX_TO_EP_INTERVAL(info);
2722 mult = CTX_TO_EP_MULT(info) + 1;
2723 lsa = !!(info & EP_HAS_LSA);
2724
2725 cerr = (info2 & (3 << 1)) >> 1;
2726 ep_type = CTX_TO_EP_TYPE(info2);
2727 hid = !!(info2 & (1 << 7));
2728 burst = CTX_TO_MAX_BURST(info2);
2729 maxp = MAX_PACKET_DECODED(info2);
2730
2731 avg = EP_AVG_TRB_LENGTH(tx_info);
2732
2733 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2734 xhci_ep_state_string(ep_state), mult,
2735 max_pstr, lsa ? "LSA " : "");
2736
2737 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2738 (1 << interval) * 125, esit, cerr);
2739
2740 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2741 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2742 burst, maxp, deq);
2743
2744 ret += sprintf(str + ret, "avg trb len %d", avg);
2745
2746 return str;
2747}
2748
2749#endif /* __LINUX_XHCI_HCD_H */