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1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21/* Code sharing between pci-quirks and xhci hcd */
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25/* max buffer size for trace and debug messages */
26#define XHCI_MSG_MAX 500
27
28/* xHCI PCI Configuration Registers */
29#define XHCI_SBRN_OFFSET (0x60)
30
31/* Max number of USB devices for any host controller - limit in section 6.1 */
32#define MAX_HC_SLOTS 256
33/* Section 5.3.3 - MaxPorts */
34#define MAX_HC_PORTS 127
35
36/*
37 * xHCI register interface.
38 * This corresponds to the eXtensible Host Controller Interface (xHCI)
39 * Revision 0.95 specification
40 */
41
42/**
43 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
44 * @hc_capbase: length of the capabilities register and HC version number
45 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
46 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
47 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
48 * @hcc_params: HCCPARAMS - Capability Parameters
49 * @db_off: DBOFF - Doorbell array offset
50 * @run_regs_off: RTSOFF - Runtime register space offset
51 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
52 */
53struct xhci_cap_regs {
54 __le32 hc_capbase;
55 __le32 hcs_params1;
56 __le32 hcs_params2;
57 __le32 hcs_params3;
58 __le32 hcc_params;
59 __le32 db_off;
60 __le32 run_regs_off;
61 __le32 hcc_params2; /* xhci 1.1 */
62 /* Reserved up to (CAPLENGTH - 0x1C) */
63};
64
65/* hc_capbase bitmasks */
66/* bits 7:0 - how long is the Capabilities register */
67#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
68/* bits 31:16 */
69#define HC_VERSION(p) (((p) >> 16) & 0xffff)
70
71/* HCSPARAMS1 - hcs_params1 - bitmasks */
72/* bits 0:7, Max Device Slots */
73#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
74#define HCS_SLOTS_MASK 0xff
75/* bits 8:18, Max Interrupters */
76#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
77/* bits 24:31, Max Ports - max value is 0x7F = 127 ports */
78#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
79
80/* HCSPARAMS2 - hcs_params2 - bitmasks */
81/* bits 0:3, frames or uframes that SW needs to queue transactions
82 * ahead of the HW to meet periodic deadlines */
83#define HCS_IST(p) (((p) >> 0) & 0xf)
84/* bits 4:7, max number of Event Ring segments */
85#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
86/* bits 21:25 Hi 5 bits of Scratchpad buffers SW must allocate for the HW */
87/* bit 26 Scratchpad restore - for save/restore HW state - not used yet */
88/* bits 27:31 Lo 5 bits of Scratchpad buffers SW must allocate for the HW */
89#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
90
91/* HCSPARAMS3 - hcs_params3 - bitmasks */
92/* bits 0:7, Max U1 to U0 latency for the roothub ports */
93#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
94/* bits 16:31, Max U2 to U0 latency for the roothub ports */
95#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
96
97/* HCCPARAMS - hcc_params - bitmasks */
98/* true: HC can use 64-bit address pointers */
99#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
100/* true: HC can do bandwidth negotiation */
101#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
102/* true: HC uses 64-byte Device Context structures
103 * FIXME 64-byte context structures aren't supported yet.
104 */
105#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
106/* true: HC has port power switches */
107#define HCC_PPC(p) ((p) & (1 << 3))
108/* true: HC has port indicators */
109#define HCS_INDICATOR(p) ((p) & (1 << 4))
110/* true: HC has Light HC Reset Capability */
111#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
112/* true: HC supports latency tolerance messaging */
113#define HCC_LTC(p) ((p) & (1 << 6))
114/* true: no secondary Stream ID Support */
115#define HCC_NSS(p) ((p) & (1 << 7))
116/* true: HC supports Stopped - Short Packet */
117#define HCC_SPC(p) ((p) & (1 << 9))
118/* true: HC has Contiguous Frame ID Capability */
119#define HCC_CFC(p) ((p) & (1 << 11))
120/* Max size for Primary Stream Arrays - 2^(n+1), where n is bits 12:15 */
121#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
122/* Extended Capabilities pointer from PCI base - section 5.3.6 */
123#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
124
125#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
126
127/* db_off bitmask - bits 0:1 reserved */
128#define DBOFF_MASK (~0x3)
129
130/* run_regs_off bitmask - bits 0:4 reserved */
131#define RTSOFF_MASK (~0x1f)
132
133/* HCCPARAMS2 - hcc_params2 - bitmasks */
134/* true: HC supports U3 entry Capability */
135#define HCC2_U3C(p) ((p) & (1 << 0))
136/* true: HC supports Configure endpoint command Max exit latency too large */
137#define HCC2_CMC(p) ((p) & (1 << 1))
138/* true: HC supports Force Save context Capability */
139#define HCC2_FSC(p) ((p) & (1 << 2))
140/* true: HC supports Compliance Transition Capability */
141#define HCC2_CTC(p) ((p) & (1 << 3))
142/* true: HC support Large ESIT payload Capability > 48k */
143#define HCC2_LEC(p) ((p) & (1 << 4))
144/* true: HC support Configuration Information Capability */
145#define HCC2_CIC(p) ((p) & (1 << 5))
146/* true: HC support Extended TBC Capability, Isoc burst count > 65535 */
147#define HCC2_ETC(p) ((p) & (1 << 6))
148
149/* Number of registers per port */
150#define NUM_PORT_REGS 4
151
152#define PORTSC 0
153#define PORTPMSC 1
154#define PORTLI 2
155#define PORTHLPMC 3
156
157/**
158 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
159 * @command: USBCMD - xHC command register
160 * @status: USBSTS - xHC status register
161 * @page_size: This indicates the page size that the host controller
162 * supports. If bit n is set, the HC supports a page size
163 * of 2^(n+12), up to a 128MB page size.
164 * 4K is the minimum page size.
165 * @cmd_ring: CRP - 64-bit Command Ring Pointer
166 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
167 * @config_reg: CONFIG - Configure Register
168 * @port_status_base: PORTSCn - base address for Port Status and Control
169 * Each port has a Port Status and Control register,
170 * followed by a Port Power Management Status and Control
171 * register, a Port Link Info register, and a reserved
172 * register.
173 * @port_power_base: PORTPMSCn - base address for
174 * Port Power Management Status and Control
175 * @port_link_base: PORTLIn - base address for Port Link Info (current
176 * Link PM state and control) for USB 2.1 and USB 3.0
177 * devices.
178 */
179struct xhci_op_regs {
180 __le32 command;
181 __le32 status;
182 __le32 page_size;
183 __le32 reserved1;
184 __le32 reserved2;
185 __le32 dev_notification;
186 __le64 cmd_ring;
187 /* rsvd: offset 0x20-2F */
188 __le32 reserved3[4];
189 __le64 dcbaa_ptr;
190 __le32 config_reg;
191 /* rsvd: offset 0x3C-3FF */
192 __le32 reserved4[241];
193 /* port 1 registers, which serve as a base address for other ports */
194 __le32 port_status_base;
195 __le32 port_power_base;
196 __le32 port_link_base;
197 __le32 reserved5;
198 /* registers for ports 2-255 */
199 __le32 reserved6[NUM_PORT_REGS*254];
200};
201
202/* USBCMD - USB command - command bitmasks */
203/* start/stop HC execution - do not write unless HC is halted*/
204#define CMD_RUN XHCI_CMD_RUN
205/* Reset HC - resets internal HC state machine and all registers (except
206 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
207 * The xHCI driver must reinitialize the xHC after setting this bit.
208 */
209#define CMD_RESET (1 << 1)
210/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
211#define CMD_EIE XHCI_CMD_EIE
212/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
213#define CMD_HSEIE XHCI_CMD_HSEIE
214/* bits 4:6 are reserved (and should be preserved on writes). */
215/* light reset (port status stays unchanged) - reset completed when this is 0 */
216#define CMD_LRESET (1 << 7)
217/* host controller save/restore state. */
218#define CMD_CSS (1 << 8)
219#define CMD_CRS (1 << 9)
220/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
221#define CMD_EWE XHCI_CMD_EWE
222/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
223 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
224 * '0' means the xHC can power it off if all ports are in the disconnect,
225 * disabled, or powered-off state.
226 */
227#define CMD_PM_INDEX (1 << 11)
228/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
229#define CMD_ETE (1 << 14)
230/* bits 15:31 are reserved (and should be preserved on writes). */
231
232#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
233#define XHCI_RESET_SHORT_USEC (250 * 1000)
234
235/* IMAN - Interrupt Management Register */
236#define IMAN_IE (1 << 1)
237#define IMAN_IP (1 << 0)
238
239/* USBSTS - USB status - status bitmasks */
240/* HC not running - set to 1 when run/stop bit is cleared. */
241#define STS_HALT XHCI_STS_HALT
242/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
243#define STS_FATAL (1 << 2)
244/* event interrupt - clear this prior to clearing any IP flags in IR set*/
245#define STS_EINT (1 << 3)
246/* port change detect */
247#define STS_PORT (1 << 4)
248/* bits 5:7 reserved and zeroed */
249/* save state status - '1' means xHC is saving state */
250#define STS_SAVE (1 << 8)
251/* restore state status - '1' means xHC is restoring state */
252#define STS_RESTORE (1 << 9)
253/* true: save or restore error */
254#define STS_SRE (1 << 10)
255/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
256#define STS_CNR XHCI_STS_CNR
257/* true: internal Host Controller Error - SW needs to reset and reinitialize */
258#define STS_HCE (1 << 12)
259/* bits 13:31 reserved and should be preserved */
260
261/*
262 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
263 * Generate a device notification event when the HC sees a transaction with a
264 * notification type that matches a bit set in this bit field.
265 */
266#define DEV_NOTE_MASK (0xffff)
267#define ENABLE_DEV_NOTE(x) (1 << (x))
268/* Most of the device notification types should only be used for debug.
269 * SW does need to pay attention to function wake notifications.
270 */
271#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
272
273/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
274/* bit 0 is the command ring cycle state */
275/* stop ring operation after completion of the currently executing command */
276#define CMD_RING_PAUSE (1 << 1)
277/* stop ring immediately - abort the currently executing command */
278#define CMD_RING_ABORT (1 << 2)
279/* true: command ring is running */
280#define CMD_RING_RUNNING (1 << 3)
281/* bits 4:5 reserved and should be preserved */
282/* Command Ring pointer - bit mask for the lower 32 bits. */
283#define CMD_RING_RSVD_BITS (0x3f)
284
285/* CONFIG - Configure Register - config_reg bitmasks */
286/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
287#define MAX_DEVS(p) ((p) & 0xff)
288/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
289#define CONFIG_U3E (1 << 8)
290/* bit 9: Configuration Information Enable, xhci 1.1 */
291#define CONFIG_CIE (1 << 9)
292/* bits 10:31 - reserved and should be preserved */
293
294/* PORTSC - Port Status and Control Register - port_status_base bitmasks */
295/* true: device connected */
296#define PORT_CONNECT (1 << 0)
297/* true: port enabled */
298#define PORT_PE (1 << 1)
299/* bit 2 reserved and zeroed */
300/* true: port has an over-current condition */
301#define PORT_OC (1 << 3)
302/* true: port reset signaling asserted */
303#define PORT_RESET (1 << 4)
304/* Port Link State - bits 5:8
305 * A read gives the current link PM state of the port,
306 * a write with Link State Write Strobe set sets the link state.
307 */
308#define PORT_PLS_MASK (0xf << 5)
309#define XDEV_U0 (0x0 << 5)
310#define XDEV_U1 (0x1 << 5)
311#define XDEV_U2 (0x2 << 5)
312#define XDEV_U3 (0x3 << 5)
313#define XDEV_DISABLED (0x4 << 5)
314#define XDEV_RXDETECT (0x5 << 5)
315#define XDEV_INACTIVE (0x6 << 5)
316#define XDEV_POLLING (0x7 << 5)
317#define XDEV_RECOVERY (0x8 << 5)
318#define XDEV_HOT_RESET (0x9 << 5)
319#define XDEV_COMP_MODE (0xa << 5)
320#define XDEV_TEST_MODE (0xb << 5)
321#define XDEV_RESUME (0xf << 5)
322
323/* true: port has power (see HCC_PPC) */
324#define PORT_POWER (1 << 9)
325/* bits 10:13 indicate device speed:
326 * 0 - undefined speed - port hasn't be initialized by a reset yet
327 * 1 - full speed
328 * 2 - low speed
329 * 3 - high speed
330 * 4 - super speed
331 * 5-15 reserved
332 */
333#define DEV_SPEED_MASK (0xf << 10)
334#define XDEV_FS (0x1 << 10)
335#define XDEV_LS (0x2 << 10)
336#define XDEV_HS (0x3 << 10)
337#define XDEV_SS (0x4 << 10)
338#define XDEV_SSP (0x5 << 10)
339#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
340#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
341#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
342#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
343#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
344#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
345#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
346#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
347
348/* Bits 20:23 in the Slot Context are the speed for the device */
349#define SLOT_SPEED_FS (XDEV_FS << 10)
350#define SLOT_SPEED_LS (XDEV_LS << 10)
351#define SLOT_SPEED_HS (XDEV_HS << 10)
352#define SLOT_SPEED_SS (XDEV_SS << 10)
353#define SLOT_SPEED_SSP (XDEV_SSP << 10)
354/* Port Indicator Control */
355#define PORT_LED_OFF (0 << 14)
356#define PORT_LED_AMBER (1 << 14)
357#define PORT_LED_GREEN (2 << 14)
358#define PORT_LED_MASK (3 << 14)
359/* Port Link State Write Strobe - set this when changing link state */
360#define PORT_LINK_STROBE (1 << 16)
361/* true: connect status change */
362#define PORT_CSC (1 << 17)
363/* true: port enable change */
364#define PORT_PEC (1 << 18)
365/* true: warm reset for a USB 3.0 device is done. A "hot" reset puts the port
366 * into an enabled state, and the device into the default state. A "warm" reset
367 * also resets the link, forcing the device through the link training sequence.
368 * SW can also look at the Port Reset register to see when warm reset is done.
369 */
370#define PORT_WRC (1 << 19)
371/* true: over-current change */
372#define PORT_OCC (1 << 20)
373/* true: reset change - 1 to 0 transition of PORT_RESET */
374#define PORT_RC (1 << 21)
375/* port link status change - set on some port link state transitions:
376 * Transition Reason
377 * ------------------------------------------------------------------------------
378 * - U3 to Resume Wakeup signaling from a device
379 * - Resume to Recovery to U0 USB 3.0 device resume
380 * - Resume to U0 USB 2.0 device resume
381 * - U3 to Recovery to U0 Software resume of USB 3.0 device complete
382 * - U3 to U0 Software resume of USB 2.0 device complete
383 * - U2 to U0 L1 resume of USB 2.1 device complete
384 * - U0 to U0 (???) L1 entry rejection by USB 2.1 device
385 * - U0 to disabled L1 entry error with USB 2.1 device
386 * - Any state to inactive Error on USB 3.0 port
387 */
388#define PORT_PLC (1 << 22)
389/* port configure error change - port failed to configure its link partner */
390#define PORT_CEC (1 << 23)
391#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
392 PORT_RC | PORT_PLC | PORT_CEC)
393
394
395/* Cold Attach Status - xHC can set this bit to report device attached during
396 * Sx state. Warm port reset should be perfomed to clear this bit and move port
397 * to connected state.
398 */
399#define PORT_CAS (1 << 24)
400/* wake on connect (enable) */
401#define PORT_WKCONN_E (1 << 25)
402/* wake on disconnect (enable) */
403#define PORT_WKDISC_E (1 << 26)
404/* wake on over-current (enable) */
405#define PORT_WKOC_E (1 << 27)
406/* bits 28:29 reserved */
407/* true: device is non-removable - for USB 3.0 roothub emulation */
408#define PORT_DEV_REMOVE (1 << 30)
409/* Initiate a warm port reset - complete when PORT_WRC is '1' */
410#define PORT_WR (1 << 31)
411
412/* We mark duplicate entries with -1 */
413#define DUPLICATE_ENTRY ((u8)(-1))
414
415/* Port Power Management Status and Control - port_power_base bitmasks */
416/* Inactivity timer value for transitions into U1, in microseconds.
417 * Timeout can be up to 127us. 0xFF means an infinite timeout.
418 */
419#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
420#define PORT_U1_TIMEOUT_MASK 0xff
421/* Inactivity timer value for transitions into U2 */
422#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
423#define PORT_U2_TIMEOUT_MASK (0xff << 8)
424/* Bits 24:31 for port testing */
425
426/* USB2 Protocol PORTSPMSC */
427#define PORT_L1S_MASK 7
428#define PORT_L1S_SUCCESS 1
429#define PORT_RWE (1 << 3)
430#define PORT_HIRD(p) (((p) & 0xf) << 4)
431#define PORT_HIRD_MASK (0xf << 4)
432#define PORT_L1DS_MASK (0xff << 8)
433#define PORT_L1DS(p) (((p) & 0xff) << 8)
434#define PORT_HLE (1 << 16)
435#define PORT_TEST_MODE_SHIFT 28
436
437/* USB3 Protocol PORTLI Port Link Information */
438#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
439#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
440
441/* USB2 Protocol PORTHLPMC */
442#define PORT_HIRDM(p)((p) & 3)
443#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
444#define PORT_BESLD(p)(((p) & 0xf) << 10)
445
446/* use 512 microseconds as USB2 LPM L1 default timeout. */
447#define XHCI_L1_TIMEOUT 512
448
449/* Set default HIRD/BESL value to 4 (350/400us) for USB2 L1 LPM resume latency.
450 * Safe to use with mixed HIRD and BESL systems (host and device) and is used
451 * by other operating systems.
452 *
453 * XHCI 1.0 errata 8/14/12 Table 13 notes:
454 * "Software should choose xHC BESL/BESLD field values that do not violate a
455 * device's resume latency requirements,
456 * e.g. not program values > '4' if BLC = '1' and a HIRD device is attached,
457 * or not program values < '4' if BLC = '0' and a BESL device is attached.
458 */
459#define XHCI_DEFAULT_BESL 4
460
461/*
462 * USB3 specification define a 360ms tPollingLFPSTiemout for USB3 ports
463 * to complete link training. usually link trainig completes much faster
464 * so check status 10 times with 36ms sleep in places we need to wait for
465 * polling to complete.
466 */
467#define XHCI_PORT_POLLING_LFPS_TIME 36
468
469/**
470 * struct xhci_intr_reg - Interrupt Register Set
471 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
472 * interrupts and check for pending interrupts.
473 * @irq_control: IMOD - Interrupt Moderation Register.
474 * Used to throttle interrupts.
475 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
476 * @erst_base: ERST base address.
477 * @erst_dequeue: Event ring dequeue pointer.
478 *
479 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
480 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
481 * multiple segments of the same size. The HC places events on the ring and
482 * "updates the Cycle bit in the TRBs to indicate to software the current
483 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
484 * updates the dequeue pointer.
485 */
486struct xhci_intr_reg {
487 __le32 irq_pending;
488 __le32 irq_control;
489 __le32 erst_size;
490 __le32 rsvd;
491 __le64 erst_base;
492 __le64 erst_dequeue;
493};
494
495/* irq_pending bitmasks */
496#define ER_IRQ_PENDING(p) ((p) & 0x1)
497/* bits 2:31 need to be preserved */
498/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
499#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
500#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
501#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
502
503/* irq_control bitmasks */
504/* Minimum interval between interrupts (in 250ns intervals). The interval
505 * between interrupts will be longer if there are no events on the event ring.
506 * Default is 4000 (1 ms).
507 */
508#define ER_IRQ_INTERVAL_MASK (0xffff)
509/* Counter used to count down the time to the next interrupt - HW use only */
510#define ER_IRQ_COUNTER_MASK (0xffff << 16)
511
512/* erst_size bitmasks */
513/* Preserve bits 16:31 of erst_size */
514#define ERST_SIZE_MASK (0xffff << 16)
515
516/* erst_base bitmasks */
517#define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
518
519/* erst_dequeue bitmasks */
520/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
521 * where the current dequeue pointer lies. This is an optional HW hint.
522 */
523#define ERST_DESI_MASK (0x7)
524/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
525 * a work queue (or delayed service routine)?
526 */
527#define ERST_EHB (1 << 3)
528#define ERST_PTR_MASK (GENMASK_ULL(63, 4))
529
530/**
531 * struct xhci_run_regs
532 * @microframe_index:
533 * MFINDEX - current microframe number
534 *
535 * Section 5.5 Host Controller Runtime Registers:
536 * "Software should read and write these registers using only Dword (32 bit)
537 * or larger accesses"
538 */
539struct xhci_run_regs {
540 __le32 microframe_index;
541 __le32 rsvd[7];
542 struct xhci_intr_reg ir_set[128];
543};
544
545/**
546 * struct doorbell_array
547 *
548 * Bits 0 - 7: Endpoint target
549 * Bits 8 - 15: RsvdZ
550 * Bits 16 - 31: Stream ID
551 *
552 * Section 5.6
553 */
554struct xhci_doorbell_array {
555 __le32 doorbell[256];
556};
557
558#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
559#define DB_VALUE_HOST 0x00000000
560
561#define PLT_MASK (0x03 << 6)
562#define PLT_SYM (0x00 << 6)
563#define PLT_ASYM_RX (0x02 << 6)
564#define PLT_ASYM_TX (0x03 << 6)
565
566/**
567 * struct xhci_container_ctx
568 * @type: Type of context. Used to calculated offsets to contained contexts.
569 * @size: Size of the context data
570 * @bytes: The raw context data given to HW
571 * @dma: dma address of the bytes
572 *
573 * Represents either a Device or Input context. Holds a pointer to the raw
574 * memory used for the context (bytes) and dma address of it (dma).
575 */
576struct xhci_container_ctx {
577 unsigned type;
578#define XHCI_CTX_TYPE_DEVICE 0x1
579#define XHCI_CTX_TYPE_INPUT 0x2
580
581 int size;
582
583 u8 *bytes;
584 dma_addr_t dma;
585};
586
587/**
588 * struct xhci_slot_ctx
589 * @dev_info: Route string, device speed, hub info, and last valid endpoint
590 * @dev_info2: Max exit latency for device number, root hub port number
591 * @tt_info: tt_info is used to construct split transaction tokens
592 * @dev_state: slot state and device address
593 *
594 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
595 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
596 * reserved at the end of the slot context for HC internal use.
597 */
598struct xhci_slot_ctx {
599 __le32 dev_info;
600 __le32 dev_info2;
601 __le32 tt_info;
602 __le32 dev_state;
603 /* offset 0x10 to 0x1f reserved for HC internal use */
604 __le32 reserved[4];
605};
606
607/* dev_info bitmasks */
608/* Route String - 0:19 */
609#define ROUTE_STRING_MASK (0xfffff)
610/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
611#define DEV_SPEED (0xf << 20)
612#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
613/* bit 24 reserved */
614/* Is this LS/FS device connected through a HS hub? - bit 25 */
615#define DEV_MTT (0x1 << 25)
616/* Set if the device is a hub - bit 26 */
617#define DEV_HUB (0x1 << 26)
618/* Index of the last valid endpoint context in this device context - 27:31 */
619#define LAST_CTX_MASK (0x1f << 27)
620#define LAST_CTX(p) ((p) << 27)
621#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
622#define SLOT_FLAG (1 << 0)
623#define EP0_FLAG (1 << 1)
624
625/* dev_info2 bitmasks */
626/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
627#define MAX_EXIT (0xffff)
628/* Root hub port number that is needed to access the USB device */
629#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
630#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
631/* Maximum number of ports under a hub device */
632#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
633#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
634
635/* tt_info bitmasks */
636/*
637 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
638 * The Slot ID of the hub that isolates the high speed signaling from
639 * this low or full-speed device. '0' if attached to root hub port.
640 */
641#define TT_SLOT (0xff)
642/*
643 * The number of the downstream facing port of the high-speed hub
644 * '0' if the device is not low or full speed.
645 */
646#define TT_PORT (0xff << 8)
647#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
648#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
649
650/* dev_state bitmasks */
651/* USB device address - assigned by the HC */
652#define DEV_ADDR_MASK (0xff)
653/* bits 8:26 reserved */
654/* Slot state */
655#define SLOT_STATE (0x1f << 27)
656#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
657
658#define SLOT_STATE_DISABLED 0
659#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
660#define SLOT_STATE_DEFAULT 1
661#define SLOT_STATE_ADDRESSED 2
662#define SLOT_STATE_CONFIGURED 3
663
664/**
665 * struct xhci_ep_ctx
666 * @ep_info: endpoint state, streams, mult, and interval information.
667 * @ep_info2: information on endpoint type, max packet size, max burst size,
668 * error count, and whether the HC will force an event for all
669 * transactions.
670 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
671 * defines one stream, this points to the endpoint transfer ring.
672 * Otherwise, it points to a stream context array, which has a
673 * ring pointer for each flow.
674 * @tx_info:
675 * Average TRB lengths for the endpoint ring and
676 * max payload within an Endpoint Service Interval Time (ESIT).
677 *
678 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
679 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
680 * reserved at the end of the endpoint context for HC internal use.
681 */
682struct xhci_ep_ctx {
683 __le32 ep_info;
684 __le32 ep_info2;
685 __le64 deq;
686 __le32 tx_info;
687 /* offset 0x14 - 0x1f reserved for HC internal use */
688 __le32 reserved[3];
689};
690
691/* ep_info bitmasks */
692/*
693 * Endpoint State - bits 0:2
694 * 0 - disabled
695 * 1 - running
696 * 2 - halted due to halt condition - ok to manipulate endpoint ring
697 * 3 - stopped
698 * 4 - TRB error
699 * 5-7 - reserved
700 */
701#define EP_STATE_MASK (0x7)
702#define EP_STATE_DISABLED 0
703#define EP_STATE_RUNNING 1
704#define EP_STATE_HALTED 2
705#define EP_STATE_STOPPED 3
706#define EP_STATE_ERROR 4
707#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
708
709/* Mult - Max number of burtst within an interval, in EP companion desc. */
710#define EP_MULT(p) (((p) & 0x3) << 8)
711#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
712/* bits 10:14 are Max Primary Streams */
713/* bit 15 is Linear Stream Array */
714/* Interval - period between requests to an endpoint - 125u increments. */
715#define EP_INTERVAL(p) (((p) & 0xff) << 16)
716#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
717#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
718#define EP_MAXPSTREAMS_MASK (0x1f << 10)
719#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
720#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
721/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
722#define EP_HAS_LSA (1 << 15)
723/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
724#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
725
726/* ep_info2 bitmasks */
727/*
728 * Force Event - generate transfer events for all TRBs for this endpoint
729 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
730 */
731#define FORCE_EVENT (0x1)
732#define ERROR_COUNT(p) (((p) & 0x3) << 1)
733#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
734#define EP_TYPE(p) ((p) << 3)
735#define ISOC_OUT_EP 1
736#define BULK_OUT_EP 2
737#define INT_OUT_EP 3
738#define CTRL_EP 4
739#define ISOC_IN_EP 5
740#define BULK_IN_EP 6
741#define INT_IN_EP 7
742/* bit 6 reserved */
743/* bit 7 is Host Initiate Disable - for disabling stream selection */
744#define MAX_BURST(p) (((p)&0xff) << 8)
745#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
746#define MAX_PACKET(p) (((p)&0xffff) << 16)
747#define MAX_PACKET_MASK (0xffff << 16)
748#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
749
750/* tx_info bitmasks */
751#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
752#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
753#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
754#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
755
756/* deq bitmasks */
757#define EP_CTX_CYCLE_MASK (1 << 0)
758#define SCTX_DEQ_MASK (~0xfL)
759
760
761/**
762 * struct xhci_input_control_context
763 * Input control context; see section 6.2.5.
764 *
765 * @drop_context: set the bit of the endpoint context you want to disable
766 * @add_context: set the bit of the endpoint context you want to enable
767 */
768struct xhci_input_control_ctx {
769 __le32 drop_flags;
770 __le32 add_flags;
771 __le32 rsvd2[6];
772};
773
774#define EP_IS_ADDED(ctrl_ctx, i) \
775 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
776#define EP_IS_DROPPED(ctrl_ctx, i) \
777 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
778
779/* Represents everything that is needed to issue a command on the command ring.
780 * It's useful to pre-allocate these for commands that cannot fail due to
781 * out-of-memory errors, like freeing streams.
782 */
783struct xhci_command {
784 /* Input context for changing device state */
785 struct xhci_container_ctx *in_ctx;
786 u32 status;
787 int slot_id;
788 /* If completion is null, no one is waiting on this command
789 * and the structure can be freed after the command completes.
790 */
791 struct completion *completion;
792 union xhci_trb *command_trb;
793 struct list_head cmd_list;
794 /* xHCI command response timeout in milliseconds */
795 unsigned int timeout_ms;
796};
797
798/* drop context bitmasks */
799#define DROP_EP(x) (0x1 << x)
800/* add context bitmasks */
801#define ADD_EP(x) (0x1 << x)
802
803struct xhci_stream_ctx {
804 /* 64-bit stream ring address, cycle state, and stream type */
805 __le64 stream_ring;
806 /* offset 0x14 - 0x1f reserved for HC internal use */
807 __le32 reserved[2];
808};
809
810/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
811#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
812/* Secondary stream array type, dequeue pointer is to a transfer ring */
813#define SCT_SEC_TR 0
814/* Primary stream array type, dequeue pointer is to a transfer ring */
815#define SCT_PRI_TR 1
816/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
817#define SCT_SSA_8 2
818#define SCT_SSA_16 3
819#define SCT_SSA_32 4
820#define SCT_SSA_64 5
821#define SCT_SSA_128 6
822#define SCT_SSA_256 7
823
824/* Assume no secondary streams for now */
825struct xhci_stream_info {
826 struct xhci_ring **stream_rings;
827 /* Number of streams, including stream 0 (which drivers can't use) */
828 unsigned int num_streams;
829 /* The stream context array may be bigger than
830 * the number of streams the driver asked for
831 */
832 struct xhci_stream_ctx *stream_ctx_array;
833 unsigned int num_stream_ctxs;
834 dma_addr_t ctx_array_dma;
835 /* For mapping physical TRB addresses to segments in stream rings */
836 struct radix_tree_root trb_address_map;
837 struct xhci_command *free_streams_command;
838};
839
840#define SMALL_STREAM_ARRAY_SIZE 256
841#define MEDIUM_STREAM_ARRAY_SIZE 1024
842
843/* Some Intel xHCI host controllers need software to keep track of the bus
844 * bandwidth. Keep track of endpoint info here. Each root port is allocated
845 * the full bus bandwidth. We must also treat TTs (including each port under a
846 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
847 * (DMI) also limits the total bandwidth (across all domains) that can be used.
848 */
849struct xhci_bw_info {
850 /* ep_interval is zero-based */
851 unsigned int ep_interval;
852 /* mult and num_packets are one-based */
853 unsigned int mult;
854 unsigned int num_packets;
855 unsigned int max_packet_size;
856 unsigned int max_esit_payload;
857 unsigned int type;
858};
859
860/* "Block" sizes in bytes the hardware uses for different device speeds.
861 * The logic in this part of the hardware limits the number of bits the hardware
862 * can use, so must represent bandwidth in a less precise manner to mimic what
863 * the scheduler hardware computes.
864 */
865#define FS_BLOCK 1
866#define HS_BLOCK 4
867#define SS_BLOCK 16
868#define DMI_BLOCK 32
869
870/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
871 * with each byte transferred. SuperSpeed devices have an initial overhead to
872 * set up bursts. These are in blocks, see above. LS overhead has already been
873 * translated into FS blocks.
874 */
875#define DMI_OVERHEAD 8
876#define DMI_OVERHEAD_BURST 4
877#define SS_OVERHEAD 8
878#define SS_OVERHEAD_BURST 32
879#define HS_OVERHEAD 26
880#define FS_OVERHEAD 20
881#define LS_OVERHEAD 128
882/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
883 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
884 * of overhead associated with split transfers crossing microframe boundaries.
885 * 31 blocks is pure protocol overhead.
886 */
887#define TT_HS_OVERHEAD (31 + 94)
888#define TT_DMI_OVERHEAD (25 + 12)
889
890/* Bandwidth limits in blocks */
891#define FS_BW_LIMIT 1285
892#define TT_BW_LIMIT 1320
893#define HS_BW_LIMIT 1607
894#define SS_BW_LIMIT_IN 3906
895#define DMI_BW_LIMIT_IN 3906
896#define SS_BW_LIMIT_OUT 3906
897#define DMI_BW_LIMIT_OUT 3906
898
899/* Percentage of bus bandwidth reserved for non-periodic transfers */
900#define FS_BW_RESERVED 10
901#define HS_BW_RESERVED 20
902#define SS_BW_RESERVED 10
903
904struct xhci_virt_ep {
905 struct xhci_virt_device *vdev; /* parent */
906 unsigned int ep_index;
907 struct xhci_ring *ring;
908 /* Related to endpoints that are configured to use stream IDs only */
909 struct xhci_stream_info *stream_info;
910 /* Temporary storage in case the configure endpoint command fails and we
911 * have to restore the device state to the previous state
912 */
913 struct xhci_ring *new_ring;
914 unsigned int err_count;
915 unsigned int ep_state;
916#define SET_DEQ_PENDING (1 << 0)
917#define EP_HALTED (1 << 1) /* For stall handling */
918#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
919/* Transitioning the endpoint to using streams, don't enqueue URBs */
920#define EP_GETTING_STREAMS (1 << 3)
921#define EP_HAS_STREAMS (1 << 4)
922/* Transitioning the endpoint to not using streams, don't enqueue URBs */
923#define EP_GETTING_NO_STREAMS (1 << 5)
924#define EP_HARD_CLEAR_TOGGLE (1 << 6)
925#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
926/* usb_hub_clear_tt_buffer is in progress */
927#define EP_CLEARING_TT (1 << 8)
928 /* ---- Related to URB cancellation ---- */
929 struct list_head cancelled_td_list;
930 struct xhci_hcd *xhci;
931 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
932 * command. We'll need to update the ring's dequeue segment and dequeue
933 * pointer after the command completes.
934 */
935 struct xhci_segment *queued_deq_seg;
936 union xhci_trb *queued_deq_ptr;
937 /*
938 * Sometimes the xHC can not process isochronous endpoint ring quickly
939 * enough, and it will miss some isoc tds on the ring and generate
940 * a Missed Service Error Event.
941 * Set skip flag when receive a Missed Service Error Event and
942 * process the missed tds on the endpoint ring.
943 */
944 bool skip;
945 /* Bandwidth checking storage */
946 struct xhci_bw_info bw_info;
947 struct list_head bw_endpoint_list;
948 /* Isoch Frame ID checking storage */
949 int next_frame_id;
950 /* Use new Isoch TRB layout needed for extended TBC support */
951 bool use_extended_tbc;
952};
953
954enum xhci_overhead_type {
955 LS_OVERHEAD_TYPE = 0,
956 FS_OVERHEAD_TYPE,
957 HS_OVERHEAD_TYPE,
958};
959
960struct xhci_interval_bw {
961 unsigned int num_packets;
962 /* Sorted by max packet size.
963 * Head of the list is the greatest max packet size.
964 */
965 struct list_head endpoints;
966 /* How many endpoints of each speed are present. */
967 unsigned int overhead[3];
968};
969
970#define XHCI_MAX_INTERVAL 16
971
972struct xhci_interval_bw_table {
973 unsigned int interval0_esit_payload;
974 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
975 /* Includes reserved bandwidth for async endpoints */
976 unsigned int bw_used;
977 unsigned int ss_bw_in;
978 unsigned int ss_bw_out;
979};
980
981#define EP_CTX_PER_DEV 31
982
983struct xhci_virt_device {
984 int slot_id;
985 struct usb_device *udev;
986 /*
987 * Commands to the hardware are passed an "input context" that
988 * tells the hardware what to change in its data structures.
989 * The hardware will return changes in an "output context" that
990 * software must allocate for the hardware. We need to keep
991 * track of input and output contexts separately because
992 * these commands might fail and we don't trust the hardware.
993 */
994 struct xhci_container_ctx *out_ctx;
995 /* Used for addressing devices and configuration changes */
996 struct xhci_container_ctx *in_ctx;
997 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
998 u8 fake_port;
999 u8 real_port;
1000 struct xhci_interval_bw_table *bw_table;
1001 struct xhci_tt_bw_info *tt_info;
1002 /*
1003 * flags for state tracking based on events and issued commands.
1004 * Software can not rely on states from output contexts because of
1005 * latency between events and xHC updating output context values.
1006 * See xhci 1.1 section 4.8.3 for more details
1007 */
1008 unsigned long flags;
1009#define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
1010
1011 /* The current max exit latency for the enabled USB3 link states. */
1012 u16 current_mel;
1013 /* Used for the debugfs interfaces. */
1014 void *debugfs_private;
1015};
1016
1017/*
1018 * For each roothub, keep track of the bandwidth information for each periodic
1019 * interval.
1020 *
1021 * If a high speed hub is attached to the roothub, each TT associated with that
1022 * hub is a separate bandwidth domain. The interval information for the
1023 * endpoints on the devices under that TT will appear in the TT structure.
1024 */
1025struct xhci_root_port_bw_info {
1026 struct list_head tts;
1027 unsigned int num_active_tts;
1028 struct xhci_interval_bw_table bw_table;
1029};
1030
1031struct xhci_tt_bw_info {
1032 struct list_head tt_list;
1033 int slot_id;
1034 int ttport;
1035 struct xhci_interval_bw_table bw_table;
1036 int active_eps;
1037};
1038
1039
1040/**
1041 * struct xhci_device_context_array
1042 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
1043 */
1044struct xhci_device_context_array {
1045 /* 64-bit device addresses; we only write 32-bit addresses */
1046 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1047 /* private xHCD pointers */
1048 dma_addr_t dma;
1049};
1050/* TODO: write function to set the 64-bit device DMA address */
1051/*
1052 * TODO: change this to be dynamically sized at HC mem init time since the HC
1053 * might not be able to handle the maximum number of devices possible.
1054 */
1055
1056
1057struct xhci_transfer_event {
1058 /* 64-bit buffer address, or immediate data */
1059 __le64 buffer;
1060 __le32 transfer_len;
1061 /* This field is interpreted differently based on the type of TRB */
1062 __le32 flags;
1063};
1064
1065/* Transfer event TRB length bit mask */
1066/* bits 0:23 */
1067#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1068
1069/** Transfer Event bit fields **/
1070#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1071
1072/* Completion Code - only applicable for some types of TRBs */
1073#define COMP_CODE_MASK (0xff << 24)
1074#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1075#define COMP_INVALID 0
1076#define COMP_SUCCESS 1
1077#define COMP_DATA_BUFFER_ERROR 2
1078#define COMP_BABBLE_DETECTED_ERROR 3
1079#define COMP_USB_TRANSACTION_ERROR 4
1080#define COMP_TRB_ERROR 5
1081#define COMP_STALL_ERROR 6
1082#define COMP_RESOURCE_ERROR 7
1083#define COMP_BANDWIDTH_ERROR 8
1084#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1085#define COMP_INVALID_STREAM_TYPE_ERROR 10
1086#define COMP_SLOT_NOT_ENABLED_ERROR 11
1087#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1088#define COMP_SHORT_PACKET 13
1089#define COMP_RING_UNDERRUN 14
1090#define COMP_RING_OVERRUN 15
1091#define COMP_VF_EVENT_RING_FULL_ERROR 16
1092#define COMP_PARAMETER_ERROR 17
1093#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1094#define COMP_CONTEXT_STATE_ERROR 19
1095#define COMP_NO_PING_RESPONSE_ERROR 20
1096#define COMP_EVENT_RING_FULL_ERROR 21
1097#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1098#define COMP_MISSED_SERVICE_ERROR 23
1099#define COMP_COMMAND_RING_STOPPED 24
1100#define COMP_COMMAND_ABORTED 25
1101#define COMP_STOPPED 26
1102#define COMP_STOPPED_LENGTH_INVALID 27
1103#define COMP_STOPPED_SHORT_PACKET 28
1104#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1105#define COMP_ISOCH_BUFFER_OVERRUN 31
1106#define COMP_EVENT_LOST_ERROR 32
1107#define COMP_UNDEFINED_ERROR 33
1108#define COMP_INVALID_STREAM_ID_ERROR 34
1109#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1110#define COMP_SPLIT_TRANSACTION_ERROR 36
1111
1112static inline const char *xhci_trb_comp_code_string(u8 status)
1113{
1114 switch (status) {
1115 case COMP_INVALID:
1116 return "Invalid";
1117 case COMP_SUCCESS:
1118 return "Success";
1119 case COMP_DATA_BUFFER_ERROR:
1120 return "Data Buffer Error";
1121 case COMP_BABBLE_DETECTED_ERROR:
1122 return "Babble Detected";
1123 case COMP_USB_TRANSACTION_ERROR:
1124 return "USB Transaction Error";
1125 case COMP_TRB_ERROR:
1126 return "TRB Error";
1127 case COMP_STALL_ERROR:
1128 return "Stall Error";
1129 case COMP_RESOURCE_ERROR:
1130 return "Resource Error";
1131 case COMP_BANDWIDTH_ERROR:
1132 return "Bandwidth Error";
1133 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1134 return "No Slots Available Error";
1135 case COMP_INVALID_STREAM_TYPE_ERROR:
1136 return "Invalid Stream Type Error";
1137 case COMP_SLOT_NOT_ENABLED_ERROR:
1138 return "Slot Not Enabled Error";
1139 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1140 return "Endpoint Not Enabled Error";
1141 case COMP_SHORT_PACKET:
1142 return "Short Packet";
1143 case COMP_RING_UNDERRUN:
1144 return "Ring Underrun";
1145 case COMP_RING_OVERRUN:
1146 return "Ring Overrun";
1147 case COMP_VF_EVENT_RING_FULL_ERROR:
1148 return "VF Event Ring Full Error";
1149 case COMP_PARAMETER_ERROR:
1150 return "Parameter Error";
1151 case COMP_BANDWIDTH_OVERRUN_ERROR:
1152 return "Bandwidth Overrun Error";
1153 case COMP_CONTEXT_STATE_ERROR:
1154 return "Context State Error";
1155 case COMP_NO_PING_RESPONSE_ERROR:
1156 return "No Ping Response Error";
1157 case COMP_EVENT_RING_FULL_ERROR:
1158 return "Event Ring Full Error";
1159 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1160 return "Incompatible Device Error";
1161 case COMP_MISSED_SERVICE_ERROR:
1162 return "Missed Service Error";
1163 case COMP_COMMAND_RING_STOPPED:
1164 return "Command Ring Stopped";
1165 case COMP_COMMAND_ABORTED:
1166 return "Command Aborted";
1167 case COMP_STOPPED:
1168 return "Stopped";
1169 case COMP_STOPPED_LENGTH_INVALID:
1170 return "Stopped - Length Invalid";
1171 case COMP_STOPPED_SHORT_PACKET:
1172 return "Stopped - Short Packet";
1173 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1174 return "Max Exit Latency Too Large Error";
1175 case COMP_ISOCH_BUFFER_OVERRUN:
1176 return "Isoch Buffer Overrun";
1177 case COMP_EVENT_LOST_ERROR:
1178 return "Event Lost Error";
1179 case COMP_UNDEFINED_ERROR:
1180 return "Undefined Error";
1181 case COMP_INVALID_STREAM_ID_ERROR:
1182 return "Invalid Stream ID Error";
1183 case COMP_SECONDARY_BANDWIDTH_ERROR:
1184 return "Secondary Bandwidth Error";
1185 case COMP_SPLIT_TRANSACTION_ERROR:
1186 return "Split Transaction Error";
1187 default:
1188 return "Unknown!!";
1189 }
1190}
1191
1192struct xhci_link_trb {
1193 /* 64-bit segment pointer*/
1194 __le64 segment_ptr;
1195 __le32 intr_target;
1196 __le32 control;
1197};
1198
1199/* control bitfields */
1200#define LINK_TOGGLE (0x1<<1)
1201
1202/* Command completion event TRB */
1203struct xhci_event_cmd {
1204 /* Pointer to command TRB, or the value passed by the event data trb */
1205 __le64 cmd_trb;
1206 __le32 status;
1207 __le32 flags;
1208};
1209
1210/* flags bitmasks */
1211
1212/* Address device - disable SetAddress */
1213#define TRB_BSR (1<<9)
1214
1215/* Configure Endpoint - Deconfigure */
1216#define TRB_DC (1<<9)
1217
1218/* Stop Ring - Transfer State Preserve */
1219#define TRB_TSP (1<<9)
1220
1221enum xhci_ep_reset_type {
1222 EP_HARD_RESET,
1223 EP_SOFT_RESET,
1224};
1225
1226/* Force Event */
1227#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1228#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1229
1230/* Set Latency Tolerance Value */
1231#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1232
1233/* Get Port Bandwidth */
1234#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1235
1236/* Force Header */
1237#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1238#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1239
1240enum xhci_setup_dev {
1241 SETUP_CONTEXT_ONLY,
1242 SETUP_CONTEXT_ADDRESS,
1243};
1244
1245/* bits 16:23 are the virtual function ID */
1246/* bits 24:31 are the slot ID */
1247#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1248#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1249
1250/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
1251#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1252#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1253
1254#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1255#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1256#define LAST_EP_INDEX 30
1257
1258/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1259#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1260#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1261#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1262
1263/* Link TRB specific fields */
1264#define TRB_TC (1<<1)
1265
1266/* Port Status Change Event TRB fields */
1267/* Port ID - bits 31:24 */
1268#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1269
1270#define EVENT_DATA (1 << 2)
1271
1272/* Normal TRB fields */
1273/* transfer_len bitmasks - bits 0:16 */
1274#define TRB_LEN(p) ((p) & 0x1ffff)
1275/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1276#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1277#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1278/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1279#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1280/* Interrupter Target - which MSI-X vector to target the completion event at */
1281#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1282#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1283/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1284#define TRB_TBC(p) (((p) & 0x3) << 7)
1285#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1286
1287/* Cycle bit - indicates TRB ownership by HC or HCD */
1288#define TRB_CYCLE (1<<0)
1289/*
1290 * Force next event data TRB to be evaluated before task switch.
1291 * Used to pass OS data back after a TD completes.
1292 */
1293#define TRB_ENT (1<<1)
1294/* Interrupt on short packet */
1295#define TRB_ISP (1<<2)
1296/* Set PCIe no snoop attribute */
1297#define TRB_NO_SNOOP (1<<3)
1298/* Chain multiple TRBs into a TD */
1299#define TRB_CHAIN (1<<4)
1300/* Interrupt on completion */
1301#define TRB_IOC (1<<5)
1302/* The buffer pointer contains immediate data */
1303#define TRB_IDT (1<<6)
1304/* TDs smaller than this might use IDT */
1305#define TRB_IDT_MAX_SIZE 8
1306
1307/* Block Event Interrupt */
1308#define TRB_BEI (1<<9)
1309
1310/* Control transfer TRB specific fields */
1311#define TRB_DIR_IN (1<<16)
1312#define TRB_TX_TYPE(p) ((p) << 16)
1313#define TRB_DATA_OUT 2
1314#define TRB_DATA_IN 3
1315
1316/* Isochronous TRB specific fields */
1317#define TRB_SIA (1<<31)
1318#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1319
1320/* TRB cache size for xHC with TRB cache */
1321#define TRB_CACHE_SIZE_HS 8
1322#define TRB_CACHE_SIZE_SS 16
1323
1324struct xhci_generic_trb {
1325 __le32 field[4];
1326};
1327
1328union xhci_trb {
1329 struct xhci_link_trb link;
1330 struct xhci_transfer_event trans_event;
1331 struct xhci_event_cmd event_cmd;
1332 struct xhci_generic_trb generic;
1333};
1334
1335/* TRB bit mask */
1336#define TRB_TYPE_BITMASK (0xfc00)
1337#define TRB_TYPE(p) ((p) << 10)
1338#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1339/* TRB type IDs */
1340/* bulk, interrupt, isoc scatter/gather, and control data stage */
1341#define TRB_NORMAL 1
1342/* setup stage for control transfers */
1343#define TRB_SETUP 2
1344/* data stage for control transfers */
1345#define TRB_DATA 3
1346/* status stage for control transfers */
1347#define TRB_STATUS 4
1348/* isoc transfers */
1349#define TRB_ISOC 5
1350/* TRB for linking ring segments */
1351#define TRB_LINK 6
1352#define TRB_EVENT_DATA 7
1353/* Transfer Ring No-op (not for the command ring) */
1354#define TRB_TR_NOOP 8
1355/* Command TRBs */
1356/* Enable Slot Command */
1357#define TRB_ENABLE_SLOT 9
1358/* Disable Slot Command */
1359#define TRB_DISABLE_SLOT 10
1360/* Address Device Command */
1361#define TRB_ADDR_DEV 11
1362/* Configure Endpoint Command */
1363#define TRB_CONFIG_EP 12
1364/* Evaluate Context Command */
1365#define TRB_EVAL_CONTEXT 13
1366/* Reset Endpoint Command */
1367#define TRB_RESET_EP 14
1368/* Stop Transfer Ring Command */
1369#define TRB_STOP_RING 15
1370/* Set Transfer Ring Dequeue Pointer Command */
1371#define TRB_SET_DEQ 16
1372/* Reset Device Command */
1373#define TRB_RESET_DEV 17
1374/* Force Event Command (opt) */
1375#define TRB_FORCE_EVENT 18
1376/* Negotiate Bandwidth Command (opt) */
1377#define TRB_NEG_BANDWIDTH 19
1378/* Set Latency Tolerance Value Command (opt) */
1379#define TRB_SET_LT 20
1380/* Get port bandwidth Command */
1381#define TRB_GET_BW 21
1382/* Force Header Command - generate a transaction or link management packet */
1383#define TRB_FORCE_HEADER 22
1384/* No-op Command - not for transfer rings */
1385#define TRB_CMD_NOOP 23
1386/* TRB IDs 24-31 reserved */
1387/* Event TRBS */
1388/* Transfer Event */
1389#define TRB_TRANSFER 32
1390/* Command Completion Event */
1391#define TRB_COMPLETION 33
1392/* Port Status Change Event */
1393#define TRB_PORT_STATUS 34
1394/* Bandwidth Request Event (opt) */
1395#define TRB_BANDWIDTH_EVENT 35
1396/* Doorbell Event (opt) */
1397#define TRB_DOORBELL 36
1398/* Host Controller Event */
1399#define TRB_HC_EVENT 37
1400/* Device Notification Event - device sent function wake notification */
1401#define TRB_DEV_NOTE 38
1402/* MFINDEX Wrap Event - microframe counter wrapped */
1403#define TRB_MFINDEX_WRAP 39
1404/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1405#define TRB_VENDOR_DEFINED_LOW 48
1406/* Nec vendor-specific command completion event. */
1407#define TRB_NEC_CMD_COMP 48
1408/* Get NEC firmware revision. */
1409#define TRB_NEC_GET_FW 49
1410
1411static inline const char *xhci_trb_type_string(u8 type)
1412{
1413 switch (type) {
1414 case TRB_NORMAL:
1415 return "Normal";
1416 case TRB_SETUP:
1417 return "Setup Stage";
1418 case TRB_DATA:
1419 return "Data Stage";
1420 case TRB_STATUS:
1421 return "Status Stage";
1422 case TRB_ISOC:
1423 return "Isoch";
1424 case TRB_LINK:
1425 return "Link";
1426 case TRB_EVENT_DATA:
1427 return "Event Data";
1428 case TRB_TR_NOOP:
1429 return "No-Op";
1430 case TRB_ENABLE_SLOT:
1431 return "Enable Slot Command";
1432 case TRB_DISABLE_SLOT:
1433 return "Disable Slot Command";
1434 case TRB_ADDR_DEV:
1435 return "Address Device Command";
1436 case TRB_CONFIG_EP:
1437 return "Configure Endpoint Command";
1438 case TRB_EVAL_CONTEXT:
1439 return "Evaluate Context Command";
1440 case TRB_RESET_EP:
1441 return "Reset Endpoint Command";
1442 case TRB_STOP_RING:
1443 return "Stop Ring Command";
1444 case TRB_SET_DEQ:
1445 return "Set TR Dequeue Pointer Command";
1446 case TRB_RESET_DEV:
1447 return "Reset Device Command";
1448 case TRB_FORCE_EVENT:
1449 return "Force Event Command";
1450 case TRB_NEG_BANDWIDTH:
1451 return "Negotiate Bandwidth Command";
1452 case TRB_SET_LT:
1453 return "Set Latency Tolerance Value Command";
1454 case TRB_GET_BW:
1455 return "Get Port Bandwidth Command";
1456 case TRB_FORCE_HEADER:
1457 return "Force Header Command";
1458 case TRB_CMD_NOOP:
1459 return "No-Op Command";
1460 case TRB_TRANSFER:
1461 return "Transfer Event";
1462 case TRB_COMPLETION:
1463 return "Command Completion Event";
1464 case TRB_PORT_STATUS:
1465 return "Port Status Change Event";
1466 case TRB_BANDWIDTH_EVENT:
1467 return "Bandwidth Request Event";
1468 case TRB_DOORBELL:
1469 return "Doorbell Event";
1470 case TRB_HC_EVENT:
1471 return "Host Controller Event";
1472 case TRB_DEV_NOTE:
1473 return "Device Notification Event";
1474 case TRB_MFINDEX_WRAP:
1475 return "MFINDEX Wrap Event";
1476 case TRB_NEC_CMD_COMP:
1477 return "NEC Command Completion Event";
1478 case TRB_NEC_GET_FW:
1479 return "NET Get Firmware Revision Command";
1480 default:
1481 return "UNKNOWN";
1482 }
1483}
1484
1485#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1486/* Above, but for __le32 types -- can avoid work by swapping constants: */
1487#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1488 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1489#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1490 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1491
1492#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1493#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1494
1495/*
1496 * TRBS_PER_SEGMENT must be a multiple of 4,
1497 * since the command ring is 64-byte aligned.
1498 * It must also be greater than 16.
1499 */
1500#define TRBS_PER_SEGMENT 256
1501/* Allow two commands + a link TRB, along with any reserved command TRBs */
1502#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1503#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1504#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1505/* TRB buffer pointers can't cross 64KB boundaries */
1506#define TRB_MAX_BUFF_SHIFT 16
1507#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1508/* How much data is left before the 64KB boundary? */
1509#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1510 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1511#define MAX_SOFT_RETRY 3
1512/*
1513 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1514 * XHCI_AVOID_BEI quirk is in use.
1515 */
1516#define AVOID_BEI_INTERVAL_MIN 8
1517#define AVOID_BEI_INTERVAL_MAX 32
1518
1519struct xhci_segment {
1520 union xhci_trb *trbs;
1521 /* private to HCD */
1522 struct xhci_segment *next;
1523 unsigned int num;
1524 dma_addr_t dma;
1525 /* Max packet sized bounce buffer for td-fragmant alignment */
1526 dma_addr_t bounce_dma;
1527 void *bounce_buf;
1528 unsigned int bounce_offs;
1529 unsigned int bounce_len;
1530};
1531
1532enum xhci_cancelled_td_status {
1533 TD_DIRTY = 0,
1534 TD_HALTED,
1535 TD_CLEARING_CACHE,
1536 TD_CLEARED,
1537};
1538
1539struct xhci_td {
1540 struct list_head td_list;
1541 struct list_head cancelled_td_list;
1542 int status;
1543 enum xhci_cancelled_td_status cancel_status;
1544 struct urb *urb;
1545 struct xhci_segment *start_seg;
1546 union xhci_trb *first_trb;
1547 union xhci_trb *last_trb;
1548 struct xhci_segment *last_trb_seg;
1549 struct xhci_segment *bounce_seg;
1550 /* actual_length of the URB has already been set */
1551 bool urb_length_set;
1552 bool error_mid_td;
1553 unsigned int num_trbs;
1554};
1555
1556/*
1557 * xHCI command default timeout value in milliseconds.
1558 * USB 3.2 spec, section 9.2.6.1
1559 */
1560#define XHCI_CMD_DEFAULT_TIMEOUT 5000
1561
1562/* command descriptor */
1563struct xhci_cd {
1564 struct xhci_command *command;
1565 union xhci_trb *cmd_trb;
1566};
1567
1568enum xhci_ring_type {
1569 TYPE_CTRL = 0,
1570 TYPE_ISOC,
1571 TYPE_BULK,
1572 TYPE_INTR,
1573 TYPE_STREAM,
1574 TYPE_COMMAND,
1575 TYPE_EVENT,
1576};
1577
1578static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1579{
1580 switch (type) {
1581 case TYPE_CTRL:
1582 return "CTRL";
1583 case TYPE_ISOC:
1584 return "ISOC";
1585 case TYPE_BULK:
1586 return "BULK";
1587 case TYPE_INTR:
1588 return "INTR";
1589 case TYPE_STREAM:
1590 return "STREAM";
1591 case TYPE_COMMAND:
1592 return "CMD";
1593 case TYPE_EVENT:
1594 return "EVENT";
1595 }
1596
1597 return "UNKNOWN";
1598}
1599
1600struct xhci_ring {
1601 struct xhci_segment *first_seg;
1602 struct xhci_segment *last_seg;
1603 union xhci_trb *enqueue;
1604 struct xhci_segment *enq_seg;
1605 union xhci_trb *dequeue;
1606 struct xhci_segment *deq_seg;
1607 struct list_head td_list;
1608 /*
1609 * Write the cycle state into the TRB cycle field to give ownership of
1610 * the TRB to the host controller (if we are the producer), or to check
1611 * if we own the TRB (if we are the consumer). See section 4.9.1.
1612 */
1613 u32 cycle_state;
1614 unsigned int stream_id;
1615 unsigned int num_segs;
1616 unsigned int num_trbs_free; /* used only by xhci DbC */
1617 unsigned int bounce_buf_len;
1618 enum xhci_ring_type type;
1619 bool last_td_was_short;
1620 struct radix_tree_root *trb_address_map;
1621};
1622
1623struct xhci_erst_entry {
1624 /* 64-bit event ring segment address */
1625 __le64 seg_addr;
1626 __le32 seg_size;
1627 /* Set to zero */
1628 __le32 rsvd;
1629};
1630
1631struct xhci_erst {
1632 struct xhci_erst_entry *entries;
1633 unsigned int num_entries;
1634 /* xhci->event_ring keeps track of segment dma addresses */
1635 dma_addr_t erst_dma_addr;
1636 /* Num entries the ERST can contain */
1637 unsigned int erst_size;
1638};
1639
1640struct xhci_scratchpad {
1641 u64 *sp_array;
1642 dma_addr_t sp_dma;
1643 void **sp_buffers;
1644};
1645
1646struct urb_priv {
1647 int num_tds;
1648 int num_tds_done;
1649 struct xhci_td td[] __counted_by(num_tds);
1650};
1651
1652/* Reasonable limit for number of Event Ring segments (spec allows 32k) */
1653#define ERST_MAX_SEGS 2
1654/* Poll every 60 seconds */
1655#define POLL_TIMEOUT 60
1656/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1657#define XHCI_STOP_EP_CMD_TIMEOUT 5
1658/* XXX: Make these module parameters */
1659
1660struct s3_save {
1661 u32 command;
1662 u32 dev_nt;
1663 u64 dcbaa_ptr;
1664 u32 config_reg;
1665};
1666
1667/* Use for lpm */
1668struct dev_info {
1669 u32 dev_id;
1670 struct list_head list;
1671};
1672
1673struct xhci_bus_state {
1674 unsigned long bus_suspended;
1675 unsigned long next_statechange;
1676
1677 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1678 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1679 u32 port_c_suspend;
1680 u32 suspended_ports;
1681 u32 port_remote_wakeup;
1682 /* which ports have started to resume */
1683 unsigned long resuming_ports;
1684};
1685
1686struct xhci_interrupter {
1687 struct xhci_ring *event_ring;
1688 struct xhci_erst erst;
1689 struct xhci_intr_reg __iomem *ir_set;
1690 unsigned int intr_num;
1691 /* For interrupter registers save and restore over suspend/resume */
1692 u32 s3_irq_pending;
1693 u32 s3_irq_control;
1694 u32 s3_erst_size;
1695 u64 s3_erst_base;
1696 u64 s3_erst_dequeue;
1697};
1698/*
1699 * It can take up to 20 ms to transition from RExit to U0 on the
1700 * Intel Lynx Point LP xHCI host.
1701 */
1702#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1703struct xhci_port_cap {
1704 u32 *psi; /* array of protocol speed ID entries */
1705 u8 psi_count;
1706 u8 psi_uid_count;
1707 u8 maj_rev;
1708 u8 min_rev;
1709};
1710
1711struct xhci_port {
1712 __le32 __iomem *addr;
1713 int hw_portnum;
1714 int hcd_portnum;
1715 struct xhci_hub *rhub;
1716 struct xhci_port_cap *port_cap;
1717 unsigned int lpm_incapable:1;
1718 unsigned long resume_timestamp;
1719 bool rexit_active;
1720 struct completion rexit_done;
1721 struct completion u3exit_done;
1722};
1723
1724struct xhci_hub {
1725 struct xhci_port **ports;
1726 unsigned int num_ports;
1727 struct usb_hcd *hcd;
1728 /* keep track of bus suspend info */
1729 struct xhci_bus_state bus_state;
1730 /* supported prococol extended capabiliy values */
1731 u8 maj_rev;
1732 u8 min_rev;
1733};
1734
1735/* There is one xhci_hcd structure per controller */
1736struct xhci_hcd {
1737 struct usb_hcd *main_hcd;
1738 struct usb_hcd *shared_hcd;
1739 /* glue to PCI and HCD framework */
1740 struct xhci_cap_regs __iomem *cap_regs;
1741 struct xhci_op_regs __iomem *op_regs;
1742 struct xhci_run_regs __iomem *run_regs;
1743 struct xhci_doorbell_array __iomem *dba;
1744
1745 /* Cached register copies of read-only HC data */
1746 __u32 hcs_params1;
1747 __u32 hcs_params2;
1748 __u32 hcs_params3;
1749 __u32 hcc_params;
1750 __u32 hcc_params2;
1751
1752 spinlock_t lock;
1753
1754 /* packed release number */
1755 u8 sbrn;
1756 u16 hci_version;
1757 u8 max_slots;
1758 u16 max_interrupters;
1759 u8 max_ports;
1760 u8 isoc_threshold;
1761 /* imod_interval in ns (I * 250ns) */
1762 u32 imod_interval;
1763 u32 isoc_bei_interval;
1764 int event_ring_max;
1765 /* 4KB min, 128MB max */
1766 int page_size;
1767 /* Valid values are 12 to 20, inclusive */
1768 int page_shift;
1769 /* MSI-X/MSI vectors */
1770 int nvecs;
1771 /* optional clocks */
1772 struct clk *clk;
1773 struct clk *reg_clk;
1774 /* optional reset controller */
1775 struct reset_control *reset;
1776 /* data structures */
1777 struct xhci_device_context_array *dcbaa;
1778 struct xhci_interrupter **interrupters;
1779 struct xhci_ring *cmd_ring;
1780 unsigned int cmd_ring_state;
1781#define CMD_RING_STATE_RUNNING (1 << 0)
1782#define CMD_RING_STATE_ABORTED (1 << 1)
1783#define CMD_RING_STATE_STOPPED (1 << 2)
1784 struct list_head cmd_list;
1785 unsigned int cmd_ring_reserved_trbs;
1786 struct delayed_work cmd_timer;
1787 struct completion cmd_ring_stop_completion;
1788 struct xhci_command *current_cmd;
1789
1790 /* Scratchpad */
1791 struct xhci_scratchpad *scratchpad;
1792
1793 /* slot enabling and address device helpers */
1794 /* these are not thread safe so use mutex */
1795 struct mutex mutex;
1796 /* Internal mirror of the HW's dcbaa */
1797 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1798 /* For keeping track of bandwidth domains per roothub. */
1799 struct xhci_root_port_bw_info *rh_bw;
1800
1801 /* DMA pools */
1802 struct dma_pool *device_pool;
1803 struct dma_pool *segment_pool;
1804 struct dma_pool *small_streams_pool;
1805 struct dma_pool *medium_streams_pool;
1806
1807 /* Host controller watchdog timer structures */
1808 unsigned int xhc_state;
1809 unsigned long run_graceperiod;
1810 struct s3_save s3;
1811/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1812 *
1813 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1814 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1815 * that sees this status (other than the timer that set it) should stop touching
1816 * hardware immediately. Interrupt handlers should return immediately when
1817 * they see this status (any time they drop and re-acquire xhci->lock).
1818 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1819 * putting the TD on the canceled list, etc.
1820 *
1821 * There are no reports of xHCI host controllers that display this issue.
1822 */
1823#define XHCI_STATE_DYING (1 << 0)
1824#define XHCI_STATE_HALTED (1 << 1)
1825#define XHCI_STATE_REMOVING (1 << 2)
1826 unsigned long long quirks;
1827#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1828#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1829#define XHCI_NEC_HOST BIT_ULL(2)
1830#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1831#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1832/*
1833 * Certain Intel host controllers have a limit to the number of endpoint
1834 * contexts they can handle. Ideally, they would signal that they can't handle
1835 * anymore endpoint contexts by returning a Resource Error for the Configure
1836 * Endpoint command, but they don't. Instead they expect software to keep track
1837 * of the number of active endpoints for them, across configure endpoint
1838 * commands, reset device commands, disable slot commands, and address device
1839 * commands.
1840 */
1841#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1842#define XHCI_BROKEN_MSI BIT_ULL(6)
1843#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1844#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1845#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1846#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1847#define XHCI_LPM_SUPPORT BIT_ULL(11)
1848#define XHCI_INTEL_HOST BIT_ULL(12)
1849#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1850#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1851#define XHCI_AVOID_BEI BIT_ULL(15)
1852#define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1853#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1854#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1855/* For controllers with a broken beyond repair streams implementation */
1856#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1857#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1858#define XHCI_MTK_HOST BIT_ULL(21)
1859#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1860#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1861#define XHCI_MISSING_CAS BIT_ULL(24)
1862/* For controller with a broken Port Disable implementation */
1863#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1864#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1865#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1866#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1867#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1868#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1869#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1870#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1871#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1872#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1873#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1874#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1875#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1876#define XHCI_DISABLE_SPARSE BIT_ULL(38)
1877#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1878#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1879#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1880#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1881#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1882#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1883#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
1884#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1885
1886 unsigned int num_active_eps;
1887 unsigned int limit_active_eps;
1888 struct xhci_port *hw_ports;
1889 struct xhci_hub usb2_rhub;
1890 struct xhci_hub usb3_rhub;
1891 /* support xHCI 1.0 spec USB2 hardware LPM */
1892 unsigned hw_lpm_support:1;
1893 /* Broken Suspend flag for SNPS Suspend resume issue */
1894 unsigned broken_suspend:1;
1895 /* Indicates that omitting hcd is supported if root hub has no ports */
1896 unsigned allow_single_roothub:1;
1897 /* cached usb2 extened protocol capabilites */
1898 u32 *ext_caps;
1899 unsigned int num_ext_caps;
1900 /* cached extended protocol port capabilities */
1901 struct xhci_port_cap *port_caps;
1902 unsigned int num_port_caps;
1903 /* Compliance Mode Recovery Data */
1904 struct timer_list comp_mode_recovery_timer;
1905 u32 port_status_u0;
1906 u16 test_mode;
1907/* Compliance Mode Timer Triggered every 2 seconds */
1908#define COMP_MODE_RCVRY_MSECS 2000
1909
1910 struct dentry *debugfs_root;
1911 struct dentry *debugfs_slots;
1912 struct list_head regset_list;
1913
1914 void *dbc;
1915 /* platform-specific data -- must come last */
1916 unsigned long priv[] __aligned(sizeof(s64));
1917};
1918
1919/* Platform specific overrides to generic XHCI hc_driver ops */
1920struct xhci_driver_overrides {
1921 size_t extra_priv_size;
1922 int (*reset)(struct usb_hcd *hcd);
1923 int (*start)(struct usb_hcd *hcd);
1924 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1925 struct usb_host_endpoint *ep);
1926 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1927 struct usb_host_endpoint *ep);
1928 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1929 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1930 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1931 struct usb_tt *tt, gfp_t mem_flags);
1932 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1933 u16 wIndex, char *buf, u16 wLength);
1934};
1935
1936#define XHCI_CFC_DELAY 10
1937
1938/* convert between an HCD pointer and the corresponding EHCI_HCD */
1939static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1940{
1941 struct usb_hcd *primary_hcd;
1942
1943 if (usb_hcd_is_primary_hcd(hcd))
1944 primary_hcd = hcd;
1945 else
1946 primary_hcd = hcd->primary_hcd;
1947
1948 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1949}
1950
1951static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1952{
1953 return xhci->main_hcd;
1954}
1955
1956static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1957{
1958 if (xhci->shared_hcd)
1959 return xhci->shared_hcd;
1960
1961 if (!xhci->usb2_rhub.num_ports)
1962 return xhci->main_hcd;
1963
1964 return NULL;
1965}
1966
1967static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1968{
1969 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1970
1971 return hcd == xhci_get_usb3_hcd(xhci);
1972}
1973
1974static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1975{
1976 return xhci->allow_single_roothub &&
1977 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1978}
1979
1980#define xhci_dbg(xhci, fmt, args...) \
1981 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1982#define xhci_err(xhci, fmt, args...) \
1983 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1984#define xhci_warn(xhci, fmt, args...) \
1985 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1986#define xhci_warn_ratelimited(xhci, fmt, args...) \
1987 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1988#define xhci_info(xhci, fmt, args...) \
1989 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1990
1991/*
1992 * Registers should always be accessed with double word or quad word accesses.
1993 *
1994 * Some xHCI implementations may support 64-bit address pointers. Registers
1995 * with 64-bit address pointers should be written to with dword accesses by
1996 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1997 * xHCI implementations that do not support 64-bit address pointers will ignore
1998 * the high dword, and write order is irrelevant.
1999 */
2000static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
2001 __le64 __iomem *regs)
2002{
2003 return lo_hi_readq(regs);
2004}
2005static inline void xhci_write_64(struct xhci_hcd *xhci,
2006 const u64 val, __le64 __iomem *regs)
2007{
2008 lo_hi_writeq(val, regs);
2009}
2010
2011static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
2012{
2013 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
2014}
2015
2016/* xHCI debugging */
2017char *xhci_get_slot_state(struct xhci_hcd *xhci,
2018 struct xhci_container_ctx *ctx);
2019void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
2020 const char *fmt, ...);
2021
2022/* xHCI memory management */
2023void xhci_mem_cleanup(struct xhci_hcd *xhci);
2024int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
2025void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
2026int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
2027int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2028void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
2029 struct usb_device *udev);
2030unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
2031unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
2032void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2033void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2034 struct xhci_virt_device *virt_dev,
2035 int old_active_eps);
2036void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2037void xhci_update_bw_info(struct xhci_hcd *xhci,
2038 struct xhci_container_ctx *in_ctx,
2039 struct xhci_input_control_ctx *ctrl_ctx,
2040 struct xhci_virt_device *virt_dev);
2041void xhci_endpoint_copy(struct xhci_hcd *xhci,
2042 struct xhci_container_ctx *in_ctx,
2043 struct xhci_container_ctx *out_ctx,
2044 unsigned int ep_index);
2045void xhci_slot_copy(struct xhci_hcd *xhci,
2046 struct xhci_container_ctx *in_ctx,
2047 struct xhci_container_ctx *out_ctx);
2048int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2049 struct usb_device *udev, struct usb_host_endpoint *ep,
2050 gfp_t mem_flags);
2051struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2052 unsigned int num_segs, unsigned int cycle_state,
2053 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2054void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2055int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2056 unsigned int num_trbs, gfp_t flags);
2057void xhci_initialize_ring_info(struct xhci_ring *ring,
2058 unsigned int cycle_state);
2059void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2060 struct xhci_virt_device *virt_dev,
2061 unsigned int ep_index);
2062struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2063 unsigned int num_stream_ctxs,
2064 unsigned int num_streams,
2065 unsigned int max_packet, gfp_t flags);
2066void xhci_free_stream_info(struct xhci_hcd *xhci,
2067 struct xhci_stream_info *stream_info);
2068void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2069 struct xhci_ep_ctx *ep_ctx,
2070 struct xhci_stream_info *stream_info);
2071void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2072 struct xhci_virt_ep *ep);
2073void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2074 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2075struct xhci_ring *xhci_dma_to_transfer_ring(
2076 struct xhci_virt_ep *ep,
2077 u64 address);
2078struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2079 bool allocate_completion, gfp_t mem_flags);
2080struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2081 bool allocate_completion, gfp_t mem_flags);
2082void xhci_urb_free_priv(struct urb_priv *urb_priv);
2083void xhci_free_command(struct xhci_hcd *xhci,
2084 struct xhci_command *command);
2085struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2086 int type, gfp_t flags);
2087void xhci_free_container_ctx(struct xhci_hcd *xhci,
2088 struct xhci_container_ctx *ctx);
2089struct xhci_interrupter *
2090xhci_create_secondary_interrupter(struct usb_hcd *hcd, int num_seg);
2091void xhci_remove_secondary_interrupter(struct usb_hcd
2092 *hcd, struct xhci_interrupter *ir);
2093
2094/* xHCI host controller glue */
2095typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2096int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
2097int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
2098 u32 mask, u32 done, int usec, unsigned int exit_state);
2099void xhci_quiesce(struct xhci_hcd *xhci);
2100int xhci_halt(struct xhci_hcd *xhci);
2101int xhci_start(struct xhci_hcd *xhci);
2102int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
2103int xhci_run(struct usb_hcd *hcd);
2104int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2105void xhci_shutdown(struct usb_hcd *hcd);
2106void xhci_stop(struct usb_hcd *hcd);
2107void xhci_init_driver(struct hc_driver *drv,
2108 const struct xhci_driver_overrides *over);
2109int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2110 struct usb_host_endpoint *ep);
2111int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2112 struct usb_host_endpoint *ep);
2113int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2114void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2115int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
2116 struct usb_tt *tt, gfp_t mem_flags);
2117int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2118int xhci_ext_cap_init(struct xhci_hcd *xhci);
2119
2120int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2121int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
2122
2123irqreturn_t xhci_irq(struct usb_hcd *hcd);
2124irqreturn_t xhci_msi_irq(int irq, void *hcd);
2125int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2126int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2127 struct xhci_virt_device *virt_dev,
2128 struct usb_device *hdev,
2129 struct usb_tt *tt, gfp_t mem_flags);
2130
2131/* xHCI ring, segment, TRB, and TD functions */
2132dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2133struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2134 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2135 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2136int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2137void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2138int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2139 u32 trb_type, u32 slot_id);
2140int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2141 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2142int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2143 u32 field1, u32 field2, u32 field3, u32 field4);
2144int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2145 int slot_id, unsigned int ep_index, int suspend);
2146int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2147 int slot_id, unsigned int ep_index);
2148int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2149 int slot_id, unsigned int ep_index);
2150int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2151 int slot_id, unsigned int ep_index);
2152int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2153 struct urb *urb, int slot_id, unsigned int ep_index);
2154int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2155 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2156 bool command_must_succeed);
2157int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2158 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2159int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2160 int slot_id, unsigned int ep_index,
2161 enum xhci_ep_reset_type reset_type);
2162int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2163 u32 slot_id);
2164void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2165 unsigned int ep_index, unsigned int stream_id,
2166 struct xhci_td *td);
2167void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2168void xhci_handle_command_timeout(struct work_struct *work);
2169
2170void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2171 unsigned int ep_index, unsigned int stream_id);
2172void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2173 unsigned int slot_id,
2174 unsigned int ep_index);
2175void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2176void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2177unsigned int count_trbs(u64 addr, u64 len);
2178
2179/* xHCI roothub code */
2180void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2181 u32 link_state);
2182void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2183 u32 port_bit);
2184int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2185 char *buf, u16 wLength);
2186int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2187int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2188struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2189
2190void xhci_hc_died(struct xhci_hcd *xhci);
2191
2192#ifdef CONFIG_PM
2193int xhci_bus_suspend(struct usb_hcd *hcd);
2194int xhci_bus_resume(struct usb_hcd *hcd);
2195unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2196#else
2197#define xhci_bus_suspend NULL
2198#define xhci_bus_resume NULL
2199#define xhci_get_resuming_ports NULL
2200#endif /* CONFIG_PM */
2201
2202u32 xhci_port_state_to_neutral(u32 state);
2203int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2204 u16 port);
2205void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2206
2207/* xHCI contexts */
2208struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2209struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2210struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2211
2212struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2213 unsigned int slot_id, unsigned int ep_index,
2214 unsigned int stream_id);
2215
2216static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2217 struct urb *urb)
2218{
2219 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2220 xhci_get_endpoint_index(&urb->ep->desc),
2221 urb->stream_id);
2222}
2223
2224/*
2225 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
2226 * them anyways as we where unable to find a device that matches the
2227 * constraints.
2228 */
2229static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2230{
2231 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2232 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2233 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2234 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2235 !urb->num_sgs)
2236 return true;
2237
2238 return false;
2239}
2240
2241static inline char *xhci_slot_state_string(u32 state)
2242{
2243 switch (state) {
2244 case SLOT_STATE_ENABLED:
2245 return "enabled/disabled";
2246 case SLOT_STATE_DEFAULT:
2247 return "default";
2248 case SLOT_STATE_ADDRESSED:
2249 return "addressed";
2250 case SLOT_STATE_CONFIGURED:
2251 return "configured";
2252 default:
2253 return "reserved";
2254 }
2255}
2256
2257static inline const char *xhci_decode_trb(char *str, size_t size,
2258 u32 field0, u32 field1, u32 field2, u32 field3)
2259{
2260 int type = TRB_FIELD_TO_TYPE(field3);
2261
2262 switch (type) {
2263 case TRB_LINK:
2264 snprintf(str, size,
2265 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2266 field1, field0, GET_INTR_TARGET(field2),
2267 xhci_trb_type_string(type),
2268 field3 & TRB_IOC ? 'I' : 'i',
2269 field3 & TRB_CHAIN ? 'C' : 'c',
2270 field3 & TRB_TC ? 'T' : 't',
2271 field3 & TRB_CYCLE ? 'C' : 'c');
2272 break;
2273 case TRB_TRANSFER:
2274 case TRB_COMPLETION:
2275 case TRB_PORT_STATUS:
2276 case TRB_BANDWIDTH_EVENT:
2277 case TRB_DOORBELL:
2278 case TRB_HC_EVENT:
2279 case TRB_DEV_NOTE:
2280 case TRB_MFINDEX_WRAP:
2281 snprintf(str, size,
2282 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2283 field1, field0,
2284 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2285 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2286 /* Macro decrements 1, maybe it shouldn't?!? */
2287 TRB_TO_EP_INDEX(field3) + 1,
2288 xhci_trb_type_string(type),
2289 field3 & EVENT_DATA ? 'E' : 'e',
2290 field3 & TRB_CYCLE ? 'C' : 'c');
2291
2292 break;
2293 case TRB_SETUP:
2294 snprintf(str, size,
2295 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2296 field0 & 0xff,
2297 (field0 & 0xff00) >> 8,
2298 (field0 & 0xff000000) >> 24,
2299 (field0 & 0xff0000) >> 16,
2300 (field1 & 0xff00) >> 8,
2301 field1 & 0xff,
2302 (field1 & 0xff000000) >> 16 |
2303 (field1 & 0xff0000) >> 16,
2304 TRB_LEN(field2), GET_TD_SIZE(field2),
2305 GET_INTR_TARGET(field2),
2306 xhci_trb_type_string(type),
2307 field3 & TRB_IDT ? 'I' : 'i',
2308 field3 & TRB_IOC ? 'I' : 'i',
2309 field3 & TRB_CYCLE ? 'C' : 'c');
2310 break;
2311 case TRB_DATA:
2312 snprintf(str, size,
2313 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2314 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2315 GET_INTR_TARGET(field2),
2316 xhci_trb_type_string(type),
2317 field3 & TRB_IDT ? 'I' : 'i',
2318 field3 & TRB_IOC ? 'I' : 'i',
2319 field3 & TRB_CHAIN ? 'C' : 'c',
2320 field3 & TRB_NO_SNOOP ? 'S' : 's',
2321 field3 & TRB_ISP ? 'I' : 'i',
2322 field3 & TRB_ENT ? 'E' : 'e',
2323 field3 & TRB_CYCLE ? 'C' : 'c');
2324 break;
2325 case TRB_STATUS:
2326 snprintf(str, size,
2327 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2328 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2329 GET_INTR_TARGET(field2),
2330 xhci_trb_type_string(type),
2331 field3 & TRB_IOC ? 'I' : 'i',
2332 field3 & TRB_CHAIN ? 'C' : 'c',
2333 field3 & TRB_ENT ? 'E' : 'e',
2334 field3 & TRB_CYCLE ? 'C' : 'c');
2335 break;
2336 case TRB_NORMAL:
2337 case TRB_ISOC:
2338 case TRB_EVENT_DATA:
2339 case TRB_TR_NOOP:
2340 snprintf(str, size,
2341 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2342 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2343 GET_INTR_TARGET(field2),
2344 xhci_trb_type_string(type),
2345 field3 & TRB_BEI ? 'B' : 'b',
2346 field3 & TRB_IDT ? 'I' : 'i',
2347 field3 & TRB_IOC ? 'I' : 'i',
2348 field3 & TRB_CHAIN ? 'C' : 'c',
2349 field3 & TRB_NO_SNOOP ? 'S' : 's',
2350 field3 & TRB_ISP ? 'I' : 'i',
2351 field3 & TRB_ENT ? 'E' : 'e',
2352 field3 & TRB_CYCLE ? 'C' : 'c');
2353 break;
2354
2355 case TRB_CMD_NOOP:
2356 case TRB_ENABLE_SLOT:
2357 snprintf(str, size,
2358 "%s: flags %c",
2359 xhci_trb_type_string(type),
2360 field3 & TRB_CYCLE ? 'C' : 'c');
2361 break;
2362 case TRB_DISABLE_SLOT:
2363 case TRB_NEG_BANDWIDTH:
2364 snprintf(str, size,
2365 "%s: slot %d flags %c",
2366 xhci_trb_type_string(type),
2367 TRB_TO_SLOT_ID(field3),
2368 field3 & TRB_CYCLE ? 'C' : 'c');
2369 break;
2370 case TRB_ADDR_DEV:
2371 snprintf(str, size,
2372 "%s: ctx %08x%08x slot %d flags %c:%c",
2373 xhci_trb_type_string(type),
2374 field1, field0,
2375 TRB_TO_SLOT_ID(field3),
2376 field3 & TRB_BSR ? 'B' : 'b',
2377 field3 & TRB_CYCLE ? 'C' : 'c');
2378 break;
2379 case TRB_CONFIG_EP:
2380 snprintf(str, size,
2381 "%s: ctx %08x%08x slot %d flags %c:%c",
2382 xhci_trb_type_string(type),
2383 field1, field0,
2384 TRB_TO_SLOT_ID(field3),
2385 field3 & TRB_DC ? 'D' : 'd',
2386 field3 & TRB_CYCLE ? 'C' : 'c');
2387 break;
2388 case TRB_EVAL_CONTEXT:
2389 snprintf(str, size,
2390 "%s: ctx %08x%08x slot %d flags %c",
2391 xhci_trb_type_string(type),
2392 field1, field0,
2393 TRB_TO_SLOT_ID(field3),
2394 field3 & TRB_CYCLE ? 'C' : 'c');
2395 break;
2396 case TRB_RESET_EP:
2397 snprintf(str, size,
2398 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2399 xhci_trb_type_string(type),
2400 field1, field0,
2401 TRB_TO_SLOT_ID(field3),
2402 /* Macro decrements 1, maybe it shouldn't?!? */
2403 TRB_TO_EP_INDEX(field3) + 1,
2404 field3 & TRB_TSP ? 'T' : 't',
2405 field3 & TRB_CYCLE ? 'C' : 'c');
2406 break;
2407 case TRB_STOP_RING:
2408 snprintf(str, size,
2409 "%s: slot %d sp %d ep %d flags %c",
2410 xhci_trb_type_string(type),
2411 TRB_TO_SLOT_ID(field3),
2412 TRB_TO_SUSPEND_PORT(field3),
2413 /* Macro decrements 1, maybe it shouldn't?!? */
2414 TRB_TO_EP_INDEX(field3) + 1,
2415 field3 & TRB_CYCLE ? 'C' : 'c');
2416 break;
2417 case TRB_SET_DEQ:
2418 snprintf(str, size,
2419 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2420 xhci_trb_type_string(type),
2421 field1, field0,
2422 TRB_TO_STREAM_ID(field2),
2423 TRB_TO_SLOT_ID(field3),
2424 /* Macro decrements 1, maybe it shouldn't?!? */
2425 TRB_TO_EP_INDEX(field3) + 1,
2426 field3 & TRB_CYCLE ? 'C' : 'c');
2427 break;
2428 case TRB_RESET_DEV:
2429 snprintf(str, size,
2430 "%s: slot %d flags %c",
2431 xhci_trb_type_string(type),
2432 TRB_TO_SLOT_ID(field3),
2433 field3 & TRB_CYCLE ? 'C' : 'c');
2434 break;
2435 case TRB_FORCE_EVENT:
2436 snprintf(str, size,
2437 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2438 xhci_trb_type_string(type),
2439 field1, field0,
2440 TRB_TO_VF_INTR_TARGET(field2),
2441 TRB_TO_VF_ID(field3),
2442 field3 & TRB_CYCLE ? 'C' : 'c');
2443 break;
2444 case TRB_SET_LT:
2445 snprintf(str, size,
2446 "%s: belt %d flags %c",
2447 xhci_trb_type_string(type),
2448 TRB_TO_BELT(field3),
2449 field3 & TRB_CYCLE ? 'C' : 'c');
2450 break;
2451 case TRB_GET_BW:
2452 snprintf(str, size,
2453 "%s: ctx %08x%08x slot %d speed %d flags %c",
2454 xhci_trb_type_string(type),
2455 field1, field0,
2456 TRB_TO_SLOT_ID(field3),
2457 TRB_TO_DEV_SPEED(field3),
2458 field3 & TRB_CYCLE ? 'C' : 'c');
2459 break;
2460 case TRB_FORCE_HEADER:
2461 snprintf(str, size,
2462 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2463 xhci_trb_type_string(type),
2464 field2, field1, field0 & 0xffffffe0,
2465 TRB_TO_PACKET_TYPE(field0),
2466 TRB_TO_ROOTHUB_PORT(field3),
2467 field3 & TRB_CYCLE ? 'C' : 'c');
2468 break;
2469 default:
2470 snprintf(str, size,
2471 "type '%s' -> raw %08x %08x %08x %08x",
2472 xhci_trb_type_string(type),
2473 field0, field1, field2, field3);
2474 }
2475
2476 return str;
2477}
2478
2479static inline const char *xhci_decode_ctrl_ctx(char *str,
2480 unsigned long drop, unsigned long add)
2481{
2482 unsigned int bit;
2483 int ret = 0;
2484
2485 str[0] = '\0';
2486
2487 if (drop) {
2488 ret = sprintf(str, "Drop:");
2489 for_each_set_bit(bit, &drop, 32)
2490 ret += sprintf(str + ret, " %d%s",
2491 bit / 2,
2492 bit % 2 ? "in":"out");
2493 ret += sprintf(str + ret, ", ");
2494 }
2495
2496 if (add) {
2497 ret += sprintf(str + ret, "Add:%s%s",
2498 (add & SLOT_FLAG) ? " slot":"",
2499 (add & EP0_FLAG) ? " ep0":"");
2500 add &= ~(SLOT_FLAG | EP0_FLAG);
2501 for_each_set_bit(bit, &add, 32)
2502 ret += sprintf(str + ret, " %d%s",
2503 bit / 2,
2504 bit % 2 ? "in":"out");
2505 }
2506 return str;
2507}
2508
2509static inline const char *xhci_decode_slot_context(char *str,
2510 u32 info, u32 info2, u32 tt_info, u32 state)
2511{
2512 u32 speed;
2513 u32 hub;
2514 u32 mtt;
2515 int ret = 0;
2516
2517 speed = info & DEV_SPEED;
2518 hub = info & DEV_HUB;
2519 mtt = info & DEV_MTT;
2520
2521 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2522 info & ROUTE_STRING_MASK,
2523 ({ char *s;
2524 switch (speed) {
2525 case SLOT_SPEED_FS:
2526 s = "full-speed";
2527 break;
2528 case SLOT_SPEED_LS:
2529 s = "low-speed";
2530 break;
2531 case SLOT_SPEED_HS:
2532 s = "high-speed";
2533 break;
2534 case SLOT_SPEED_SS:
2535 s = "super-speed";
2536 break;
2537 case SLOT_SPEED_SSP:
2538 s = "super-speed plus";
2539 break;
2540 default:
2541 s = "UNKNOWN speed";
2542 } s; }),
2543 mtt ? " multi-TT" : "",
2544 hub ? " Hub" : "",
2545 (info & LAST_CTX_MASK) >> 27,
2546 info2 & MAX_EXIT,
2547 DEVINFO_TO_ROOT_HUB_PORT(info2),
2548 DEVINFO_TO_MAX_PORTS(info2));
2549
2550 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2551 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2552 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2553 state & DEV_ADDR_MASK,
2554 xhci_slot_state_string(GET_SLOT_STATE(state)));
2555
2556 return str;
2557}
2558
2559
2560static inline const char *xhci_portsc_link_state_string(u32 portsc)
2561{
2562 switch (portsc & PORT_PLS_MASK) {
2563 case XDEV_U0:
2564 return "U0";
2565 case XDEV_U1:
2566 return "U1";
2567 case XDEV_U2:
2568 return "U2";
2569 case XDEV_U3:
2570 return "U3";
2571 case XDEV_DISABLED:
2572 return "Disabled";
2573 case XDEV_RXDETECT:
2574 return "RxDetect";
2575 case XDEV_INACTIVE:
2576 return "Inactive";
2577 case XDEV_POLLING:
2578 return "Polling";
2579 case XDEV_RECOVERY:
2580 return "Recovery";
2581 case XDEV_HOT_RESET:
2582 return "Hot Reset";
2583 case XDEV_COMP_MODE:
2584 return "Compliance mode";
2585 case XDEV_TEST_MODE:
2586 return "Test mode";
2587 case XDEV_RESUME:
2588 return "Resume";
2589 default:
2590 break;
2591 }
2592 return "Unknown";
2593}
2594
2595static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2596{
2597 int ret;
2598
2599 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2600 portsc & PORT_POWER ? "Powered" : "Powered-off",
2601 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2602 portsc & PORT_PE ? "Enabled" : "Disabled",
2603 xhci_portsc_link_state_string(portsc),
2604 DEV_PORT_SPEED(portsc));
2605
2606 if (portsc & PORT_OC)
2607 ret += sprintf(str + ret, "OverCurrent ");
2608 if (portsc & PORT_RESET)
2609 ret += sprintf(str + ret, "In-Reset ");
2610
2611 ret += sprintf(str + ret, "Change: ");
2612 if (portsc & PORT_CSC)
2613 ret += sprintf(str + ret, "CSC ");
2614 if (portsc & PORT_PEC)
2615 ret += sprintf(str + ret, "PEC ");
2616 if (portsc & PORT_WRC)
2617 ret += sprintf(str + ret, "WRC ");
2618 if (portsc & PORT_OCC)
2619 ret += sprintf(str + ret, "OCC ");
2620 if (portsc & PORT_RC)
2621 ret += sprintf(str + ret, "PRC ");
2622 if (portsc & PORT_PLC)
2623 ret += sprintf(str + ret, "PLC ");
2624 if (portsc & PORT_CEC)
2625 ret += sprintf(str + ret, "CEC ");
2626 if (portsc & PORT_CAS)
2627 ret += sprintf(str + ret, "CAS ");
2628
2629 ret += sprintf(str + ret, "Wake: ");
2630 if (portsc & PORT_WKCONN_E)
2631 ret += sprintf(str + ret, "WCE ");
2632 if (portsc & PORT_WKDISC_E)
2633 ret += sprintf(str + ret, "WDE ");
2634 if (portsc & PORT_WKOC_E)
2635 ret += sprintf(str + ret, "WOE ");
2636
2637 return str;
2638}
2639
2640static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2641{
2642 int ret = 0;
2643
2644 ret = sprintf(str, " 0x%08x", usbsts);
2645
2646 if (usbsts == ~(u32)0)
2647 return str;
2648
2649 if (usbsts & STS_HALT)
2650 ret += sprintf(str + ret, " HCHalted");
2651 if (usbsts & STS_FATAL)
2652 ret += sprintf(str + ret, " HSE");
2653 if (usbsts & STS_EINT)
2654 ret += sprintf(str + ret, " EINT");
2655 if (usbsts & STS_PORT)
2656 ret += sprintf(str + ret, " PCD");
2657 if (usbsts & STS_SAVE)
2658 ret += sprintf(str + ret, " SSS");
2659 if (usbsts & STS_RESTORE)
2660 ret += sprintf(str + ret, " RSS");
2661 if (usbsts & STS_SRE)
2662 ret += sprintf(str + ret, " SRE");
2663 if (usbsts & STS_CNR)
2664 ret += sprintf(str + ret, " CNR");
2665 if (usbsts & STS_HCE)
2666 ret += sprintf(str + ret, " HCE");
2667
2668 return str;
2669}
2670
2671static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2672{
2673 u8 ep;
2674 u16 stream;
2675 int ret;
2676
2677 ep = (doorbell & 0xff);
2678 stream = doorbell >> 16;
2679
2680 if (slot == 0) {
2681 sprintf(str, "Command Ring %d", doorbell);
2682 return str;
2683 }
2684 ret = sprintf(str, "Slot %d ", slot);
2685 if (ep > 0 && ep < 32)
2686 ret = sprintf(str + ret, "ep%d%s",
2687 ep / 2,
2688 ep % 2 ? "in" : "out");
2689 else if (ep == 0 || ep < 248)
2690 ret = sprintf(str + ret, "Reserved %d", ep);
2691 else
2692 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2693 if (stream)
2694 ret = sprintf(str + ret, " Stream %d", stream);
2695
2696 return str;
2697}
2698
2699static inline const char *xhci_ep_state_string(u8 state)
2700{
2701 switch (state) {
2702 case EP_STATE_DISABLED:
2703 return "disabled";
2704 case EP_STATE_RUNNING:
2705 return "running";
2706 case EP_STATE_HALTED:
2707 return "halted";
2708 case EP_STATE_STOPPED:
2709 return "stopped";
2710 case EP_STATE_ERROR:
2711 return "error";
2712 default:
2713 return "INVALID";
2714 }
2715}
2716
2717static inline const char *xhci_ep_type_string(u8 type)
2718{
2719 switch (type) {
2720 case ISOC_OUT_EP:
2721 return "Isoc OUT";
2722 case BULK_OUT_EP:
2723 return "Bulk OUT";
2724 case INT_OUT_EP:
2725 return "Int OUT";
2726 case CTRL_EP:
2727 return "Ctrl";
2728 case ISOC_IN_EP:
2729 return "Isoc IN";
2730 case BULK_IN_EP:
2731 return "Bulk IN";
2732 case INT_IN_EP:
2733 return "Int IN";
2734 default:
2735 return "INVALID";
2736 }
2737}
2738
2739static inline const char *xhci_decode_ep_context(char *str, u32 info,
2740 u32 info2, u64 deq, u32 tx_info)
2741{
2742 int ret;
2743
2744 u32 esit;
2745 u16 maxp;
2746 u16 avg;
2747
2748 u8 max_pstr;
2749 u8 ep_state;
2750 u8 interval;
2751 u8 ep_type;
2752 u8 burst;
2753 u8 cerr;
2754 u8 mult;
2755
2756 bool lsa;
2757 bool hid;
2758
2759 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2760 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2761
2762 ep_state = info & EP_STATE_MASK;
2763 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2764 interval = CTX_TO_EP_INTERVAL(info);
2765 mult = CTX_TO_EP_MULT(info) + 1;
2766 lsa = !!(info & EP_HAS_LSA);
2767
2768 cerr = (info2 & (3 << 1)) >> 1;
2769 ep_type = CTX_TO_EP_TYPE(info2);
2770 hid = !!(info2 & (1 << 7));
2771 burst = CTX_TO_MAX_BURST(info2);
2772 maxp = MAX_PACKET_DECODED(info2);
2773
2774 avg = EP_AVG_TRB_LENGTH(tx_info);
2775
2776 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2777 xhci_ep_state_string(ep_state), mult,
2778 max_pstr, lsa ? "LSA " : "");
2779
2780 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2781 (1 << interval) * 125, esit, cerr);
2782
2783 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2784 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2785 burst, maxp, deq);
2786
2787 ret += sprintf(str + ret, "avg trb len %d", avg);
2788
2789 return str;
2790}
2791
2792#endif /* __LINUX_XHCI_HCD_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2
3/*
4 * xHCI host controller driver
5 *
6 * Copyright (C) 2008 Intel Corp.
7 *
8 * Author: Sarah Sharp
9 * Some code borrowed from the Linux EHCI driver.
10 */
11
12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21/* Code sharing between pci-quirks and xhci hcd */
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25#include "xhci-port.h"
26#include "xhci-caps.h"
27
28/* max buffer size for trace and debug messages */
29#define XHCI_MSG_MAX 500
30
31/* xHCI PCI Configuration Registers */
32#define XHCI_SBRN_OFFSET (0x60)
33
34/* Max number of USB devices for any host controller - limit in section 6.1 */
35#define MAX_HC_SLOTS 256
36/* Section 5.3.3 - MaxPorts */
37#define MAX_HC_PORTS 127
38
39/*
40 * xHCI register interface.
41 * This corresponds to the eXtensible Host Controller Interface (xHCI)
42 * Revision 0.95 specification
43 */
44
45/**
46 * struct xhci_cap_regs - xHCI Host Controller Capability Registers.
47 * @hc_capbase: length of the capabilities register and HC version number
48 * @hcs_params1: HCSPARAMS1 - Structural Parameters 1
49 * @hcs_params2: HCSPARAMS2 - Structural Parameters 2
50 * @hcs_params3: HCSPARAMS3 - Structural Parameters 3
51 * @hcc_params: HCCPARAMS - Capability Parameters
52 * @db_off: DBOFF - Doorbell array offset
53 * @run_regs_off: RTSOFF - Runtime register space offset
54 * @hcc_params2: HCCPARAMS2 Capability Parameters 2, xhci 1.1 only
55 */
56struct xhci_cap_regs {
57 __le32 hc_capbase;
58 __le32 hcs_params1;
59 __le32 hcs_params2;
60 __le32 hcs_params3;
61 __le32 hcc_params;
62 __le32 db_off;
63 __le32 run_regs_off;
64 __le32 hcc_params2; /* xhci 1.1 */
65 /* Reserved up to (CAPLENGTH - 0x1C) */
66};
67
68/* Number of registers per port */
69#define NUM_PORT_REGS 4
70
71#define PORTSC 0
72#define PORTPMSC 1
73#define PORTLI 2
74#define PORTHLPMC 3
75
76/**
77 * struct xhci_op_regs - xHCI Host Controller Operational Registers.
78 * @command: USBCMD - xHC command register
79 * @status: USBSTS - xHC status register
80 * @page_size: This indicates the page size that the host controller
81 * supports. If bit n is set, the HC supports a page size
82 * of 2^(n+12), up to a 128MB page size.
83 * 4K is the minimum page size.
84 * @cmd_ring: CRP - 64-bit Command Ring Pointer
85 * @dcbaa_ptr: DCBAAP - 64-bit Device Context Base Address Array Pointer
86 * @config_reg: CONFIG - Configure Register
87 * @port_status_base: PORTSCn - base address for Port Status and Control
88 * Each port has a Port Status and Control register,
89 * followed by a Port Power Management Status and Control
90 * register, a Port Link Info register, and a reserved
91 * register.
92 * @port_power_base: PORTPMSCn - base address for
93 * Port Power Management Status and Control
94 * @port_link_base: PORTLIn - base address for Port Link Info (current
95 * Link PM state and control) for USB 2.1 and USB 3.0
96 * devices.
97 */
98struct xhci_op_regs {
99 __le32 command;
100 __le32 status;
101 __le32 page_size;
102 __le32 reserved1;
103 __le32 reserved2;
104 __le32 dev_notification;
105 __le64 cmd_ring;
106 /* rsvd: offset 0x20-2F */
107 __le32 reserved3[4];
108 __le64 dcbaa_ptr;
109 __le32 config_reg;
110 /* rsvd: offset 0x3C-3FF */
111 __le32 reserved4[241];
112 /* port 1 registers, which serve as a base address for other ports */
113 __le32 port_status_base;
114 __le32 port_power_base;
115 __le32 port_link_base;
116 __le32 reserved5;
117 /* registers for ports 2-255 */
118 __le32 reserved6[NUM_PORT_REGS*254];
119};
120
121/* USBCMD - USB command - command bitmasks */
122/* start/stop HC execution - do not write unless HC is halted*/
123#define CMD_RUN XHCI_CMD_RUN
124/* Reset HC - resets internal HC state machine and all registers (except
125 * PCI config regs). HC does NOT drive a USB reset on the downstream ports.
126 * The xHCI driver must reinitialize the xHC after setting this bit.
127 */
128#define CMD_RESET (1 << 1)
129/* Event Interrupt Enable - a '1' allows interrupts from the host controller */
130#define CMD_EIE XHCI_CMD_EIE
131/* Host System Error Interrupt Enable - get out-of-band signal for HC errors */
132#define CMD_HSEIE XHCI_CMD_HSEIE
133/* bits 4:6 are reserved (and should be preserved on writes). */
134/* light reset (port status stays unchanged) - reset completed when this is 0 */
135#define CMD_LRESET (1 << 7)
136/* host controller save/restore state. */
137#define CMD_CSS (1 << 8)
138#define CMD_CRS (1 << 9)
139/* Enable Wrap Event - '1' means xHC generates an event when MFINDEX wraps. */
140#define CMD_EWE XHCI_CMD_EWE
141/* MFINDEX power management - '1' means xHC can stop MFINDEX counter if all root
142 * hubs are in U3 (selective suspend), disconnect, disabled, or powered-off.
143 * '0' means the xHC can power it off if all ports are in the disconnect,
144 * disabled, or powered-off state.
145 */
146#define CMD_PM_INDEX (1 << 11)
147/* bit 14 Extended TBC Enable, changes Isoc TRB fields to support larger TBC */
148#define CMD_ETE (1 << 14)
149/* bits 15:31 are reserved (and should be preserved on writes). */
150
151#define XHCI_RESET_LONG_USEC (10 * 1000 * 1000)
152#define XHCI_RESET_SHORT_USEC (250 * 1000)
153
154/* IMAN - Interrupt Management Register */
155#define IMAN_IE (1 << 1)
156#define IMAN_IP (1 << 0)
157
158/* USBSTS - USB status - status bitmasks */
159/* HC not running - set to 1 when run/stop bit is cleared. */
160#define STS_HALT XHCI_STS_HALT
161/* serious error, e.g. PCI parity error. The HC will clear the run/stop bit. */
162#define STS_FATAL (1 << 2)
163/* event interrupt - clear this prior to clearing any IP flags in IR set*/
164#define STS_EINT (1 << 3)
165/* port change detect */
166#define STS_PORT (1 << 4)
167/* bits 5:7 reserved and zeroed */
168/* save state status - '1' means xHC is saving state */
169#define STS_SAVE (1 << 8)
170/* restore state status - '1' means xHC is restoring state */
171#define STS_RESTORE (1 << 9)
172/* true: save or restore error */
173#define STS_SRE (1 << 10)
174/* true: Controller Not Ready to accept doorbell or op reg writes after reset */
175#define STS_CNR XHCI_STS_CNR
176/* true: internal Host Controller Error - SW needs to reset and reinitialize */
177#define STS_HCE (1 << 12)
178/* bits 13:31 reserved and should be preserved */
179
180/*
181 * DNCTRL - Device Notification Control Register - dev_notification bitmasks
182 * Generate a device notification event when the HC sees a transaction with a
183 * notification type that matches a bit set in this bit field.
184 */
185#define DEV_NOTE_MASK (0xffff)
186#define ENABLE_DEV_NOTE(x) (1 << (x))
187/* Most of the device notification types should only be used for debug.
188 * SW does need to pay attention to function wake notifications.
189 */
190#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
191
192/* CRCR - Command Ring Control Register - cmd_ring bitmasks */
193/* bit 0 is the command ring cycle state */
194/* stop ring operation after completion of the currently executing command */
195#define CMD_RING_PAUSE (1 << 1)
196/* stop ring immediately - abort the currently executing command */
197#define CMD_RING_ABORT (1 << 2)
198/* true: command ring is running */
199#define CMD_RING_RUNNING (1 << 3)
200/* bits 4:5 reserved and should be preserved */
201/* Command Ring pointer - bit mask for the lower 32 bits. */
202#define CMD_RING_RSVD_BITS (0x3f)
203
204/* CONFIG - Configure Register - config_reg bitmasks */
205/* bits 0:7 - maximum number of device slots enabled (NumSlotsEn) */
206#define MAX_DEVS(p) ((p) & 0xff)
207/* bit 8: U3 Entry Enabled, assert PLC when root port enters U3, xhci 1.1 */
208#define CONFIG_U3E (1 << 8)
209/* bit 9: Configuration Information Enable, xhci 1.1 */
210#define CONFIG_CIE (1 << 9)
211/* bits 10:31 - reserved and should be preserved */
212
213/**
214 * struct xhci_intr_reg - Interrupt Register Set
215 * @irq_pending: IMAN - Interrupt Management Register. Used to enable
216 * interrupts and check for pending interrupts.
217 * @irq_control: IMOD - Interrupt Moderation Register.
218 * Used to throttle interrupts.
219 * @erst_size: Number of segments in the Event Ring Segment Table (ERST).
220 * @erst_base: ERST base address.
221 * @erst_dequeue: Event ring dequeue pointer.
222 *
223 * Each interrupter (defined by a MSI-X vector) has an event ring and an Event
224 * Ring Segment Table (ERST) associated with it. The event ring is comprised of
225 * multiple segments of the same size. The HC places events on the ring and
226 * "updates the Cycle bit in the TRBs to indicate to software the current
227 * position of the Enqueue Pointer." The HCD (Linux) processes those events and
228 * updates the dequeue pointer.
229 */
230struct xhci_intr_reg {
231 __le32 irq_pending;
232 __le32 irq_control;
233 __le32 erst_size;
234 __le32 rsvd;
235 __le64 erst_base;
236 __le64 erst_dequeue;
237};
238
239/* irq_pending bitmasks */
240#define ER_IRQ_PENDING(p) ((p) & 0x1)
241/* bits 2:31 need to be preserved */
242/* THIS IS BUGGY - FIXME - IP IS WRITE 1 TO CLEAR */
243#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
244#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
245#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
246
247/* irq_control bitmasks */
248/* Minimum interval between interrupts (in 250ns intervals). The interval
249 * between interrupts will be longer if there are no events on the event ring.
250 * Default is 4000 (1 ms).
251 */
252#define ER_IRQ_INTERVAL_MASK (0xffff)
253/* Counter used to count down the time to the next interrupt - HW use only */
254#define ER_IRQ_COUNTER_MASK (0xffff << 16)
255
256/* erst_size bitmasks */
257/* Preserve bits 16:31 of erst_size */
258#define ERST_SIZE_MASK (0xffff << 16)
259
260/* erst_base bitmasks */
261#define ERST_BASE_RSVDP (GENMASK_ULL(5, 0))
262
263/* erst_dequeue bitmasks */
264/* Dequeue ERST Segment Index (DESI) - Segment number (or alias)
265 * where the current dequeue pointer lies. This is an optional HW hint.
266 */
267#define ERST_DESI_MASK (0x7)
268/* Event Handler Busy (EHB) - is the event ring scheduled to be serviced by
269 * a work queue (or delayed service routine)?
270 */
271#define ERST_EHB (1 << 3)
272#define ERST_PTR_MASK (GENMASK_ULL(63, 4))
273
274/**
275 * struct xhci_run_regs
276 * @microframe_index:
277 * MFINDEX - current microframe number
278 *
279 * Section 5.5 Host Controller Runtime Registers:
280 * "Software should read and write these registers using only Dword (32 bit)
281 * or larger accesses"
282 */
283struct xhci_run_regs {
284 __le32 microframe_index;
285 __le32 rsvd[7];
286 struct xhci_intr_reg ir_set[128];
287};
288
289/**
290 * struct doorbell_array
291 *
292 * Bits 0 - 7: Endpoint target
293 * Bits 8 - 15: RsvdZ
294 * Bits 16 - 31: Stream ID
295 *
296 * Section 5.6
297 */
298struct xhci_doorbell_array {
299 __le32 doorbell[256];
300};
301
302#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
303#define DB_VALUE_HOST 0x00000000
304
305#define PLT_MASK (0x03 << 6)
306#define PLT_SYM (0x00 << 6)
307#define PLT_ASYM_RX (0x02 << 6)
308#define PLT_ASYM_TX (0x03 << 6)
309
310/**
311 * struct xhci_container_ctx
312 * @type: Type of context. Used to calculated offsets to contained contexts.
313 * @size: Size of the context data
314 * @bytes: The raw context data given to HW
315 * @dma: dma address of the bytes
316 *
317 * Represents either a Device or Input context. Holds a pointer to the raw
318 * memory used for the context (bytes) and dma address of it (dma).
319 */
320struct xhci_container_ctx {
321 unsigned type;
322#define XHCI_CTX_TYPE_DEVICE 0x1
323#define XHCI_CTX_TYPE_INPUT 0x2
324
325 int size;
326
327 u8 *bytes;
328 dma_addr_t dma;
329};
330
331/**
332 * struct xhci_slot_ctx
333 * @dev_info: Route string, device speed, hub info, and last valid endpoint
334 * @dev_info2: Max exit latency for device number, root hub port number
335 * @tt_info: tt_info is used to construct split transaction tokens
336 * @dev_state: slot state and device address
337 *
338 * Slot Context - section 6.2.1.1. This assumes the HC uses 32-byte context
339 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
340 * reserved at the end of the slot context for HC internal use.
341 */
342struct xhci_slot_ctx {
343 __le32 dev_info;
344 __le32 dev_info2;
345 __le32 tt_info;
346 __le32 dev_state;
347 /* offset 0x10 to 0x1f reserved for HC internal use */
348 __le32 reserved[4];
349};
350
351/* dev_info bitmasks */
352/* Route String - 0:19 */
353#define ROUTE_STRING_MASK (0xfffff)
354/* Device speed - values defined by PORTSC Device Speed field - 20:23 */
355#define DEV_SPEED (0xf << 20)
356#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
357/* bit 24 reserved */
358/* Is this LS/FS device connected through a HS hub? - bit 25 */
359#define DEV_MTT (0x1 << 25)
360/* Set if the device is a hub - bit 26 */
361#define DEV_HUB (0x1 << 26)
362/* Index of the last valid endpoint context in this device context - 27:31 */
363#define LAST_CTX_MASK (0x1f << 27)
364#define LAST_CTX(p) ((p) << 27)
365#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
366#define SLOT_FLAG (1 << 0)
367#define EP0_FLAG (1 << 1)
368
369/* dev_info2 bitmasks */
370/* Max Exit Latency (ms) - worst case time to wake up all links in dev path */
371#define MAX_EXIT (0xffff)
372/* Root hub port number that is needed to access the USB device */
373#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
374#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
375/* Maximum number of ports under a hub device */
376#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
377#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
378
379/* tt_info bitmasks */
380/*
381 * TT Hub Slot ID - for low or full speed devices attached to a high-speed hub
382 * The Slot ID of the hub that isolates the high speed signaling from
383 * this low or full-speed device. '0' if attached to root hub port.
384 */
385#define TT_SLOT (0xff)
386/*
387 * The number of the downstream facing port of the high-speed hub
388 * '0' if the device is not low or full speed.
389 */
390#define TT_PORT (0xff << 8)
391#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
392#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
393
394/* dev_state bitmasks */
395/* USB device address - assigned by the HC */
396#define DEV_ADDR_MASK (0xff)
397/* bits 8:26 reserved */
398/* Slot state */
399#define SLOT_STATE (0x1f << 27)
400#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
401
402#define SLOT_STATE_DISABLED 0
403#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
404#define SLOT_STATE_DEFAULT 1
405#define SLOT_STATE_ADDRESSED 2
406#define SLOT_STATE_CONFIGURED 3
407
408/**
409 * struct xhci_ep_ctx
410 * @ep_info: endpoint state, streams, mult, and interval information.
411 * @ep_info2: information on endpoint type, max packet size, max burst size,
412 * error count, and whether the HC will force an event for all
413 * transactions.
414 * @deq: 64-bit ring dequeue pointer address. If the endpoint only
415 * defines one stream, this points to the endpoint transfer ring.
416 * Otherwise, it points to a stream context array, which has a
417 * ring pointer for each flow.
418 * @tx_info:
419 * Average TRB lengths for the endpoint ring and
420 * max payload within an Endpoint Service Interval Time (ESIT).
421 *
422 * Endpoint Context - section 6.2.1.2. This assumes the HC uses 32-byte context
423 * structures. If the HC uses 64-byte contexts, there is an additional 32 bytes
424 * reserved at the end of the endpoint context for HC internal use.
425 */
426struct xhci_ep_ctx {
427 __le32 ep_info;
428 __le32 ep_info2;
429 __le64 deq;
430 __le32 tx_info;
431 /* offset 0x14 - 0x1f reserved for HC internal use */
432 __le32 reserved[3];
433};
434
435/* ep_info bitmasks */
436/*
437 * Endpoint State - bits 0:2
438 * 0 - disabled
439 * 1 - running
440 * 2 - halted due to halt condition - ok to manipulate endpoint ring
441 * 3 - stopped
442 * 4 - TRB error
443 * 5-7 - reserved
444 */
445#define EP_STATE_MASK (0x7)
446#define EP_STATE_DISABLED 0
447#define EP_STATE_RUNNING 1
448#define EP_STATE_HALTED 2
449#define EP_STATE_STOPPED 3
450#define EP_STATE_ERROR 4
451#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
452
453/* Mult - Max number of burtst within an interval, in EP companion desc. */
454#define EP_MULT(p) (((p) & 0x3) << 8)
455#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
456/* bits 10:14 are Max Primary Streams */
457/* bit 15 is Linear Stream Array */
458/* Interval - period between requests to an endpoint - 125u increments. */
459#define EP_INTERVAL(p) (((p) & 0xff) << 16)
460#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
461#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
462#define EP_MAXPSTREAMS_MASK (0x1f << 10)
463#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
464#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
465/* Endpoint is set up with a Linear Stream Array (vs. Secondary Stream Array) */
466#define EP_HAS_LSA (1 << 15)
467/* hosts with LEC=1 use bits 31:24 as ESIT high bits. */
468#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
469
470/* ep_info2 bitmasks */
471/*
472 * Force Event - generate transfer events for all TRBs for this endpoint
473 * This will tell the HC to ignore the IOC and ISP flags (for debugging only).
474 */
475#define FORCE_EVENT (0x1)
476#define ERROR_COUNT(p) (((p) & 0x3) << 1)
477#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
478#define EP_TYPE(p) ((p) << 3)
479#define ISOC_OUT_EP 1
480#define BULK_OUT_EP 2
481#define INT_OUT_EP 3
482#define CTRL_EP 4
483#define ISOC_IN_EP 5
484#define BULK_IN_EP 6
485#define INT_IN_EP 7
486/* bit 6 reserved */
487/* bit 7 is Host Initiate Disable - for disabling stream selection */
488#define MAX_BURST(p) (((p)&0xff) << 8)
489#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
490#define MAX_PACKET(p) (((p)&0xffff) << 16)
491#define MAX_PACKET_MASK (0xffff << 16)
492#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
493
494/* tx_info bitmasks */
495#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
496#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
497#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
498#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
499
500/* deq bitmasks */
501#define EP_CTX_CYCLE_MASK (1 << 0)
502#define SCTX_DEQ_MASK (~0xfL)
503
504
505/**
506 * struct xhci_input_control_context
507 * Input control context; see section 6.2.5.
508 *
509 * @drop_context: set the bit of the endpoint context you want to disable
510 * @add_context: set the bit of the endpoint context you want to enable
511 */
512struct xhci_input_control_ctx {
513 __le32 drop_flags;
514 __le32 add_flags;
515 __le32 rsvd2[6];
516};
517
518#define EP_IS_ADDED(ctrl_ctx, i) \
519 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
520#define EP_IS_DROPPED(ctrl_ctx, i) \
521 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
522
523/* Represents everything that is needed to issue a command on the command ring.
524 * It's useful to pre-allocate these for commands that cannot fail due to
525 * out-of-memory errors, like freeing streams.
526 */
527struct xhci_command {
528 /* Input context for changing device state */
529 struct xhci_container_ctx *in_ctx;
530 u32 status;
531 int slot_id;
532 /* If completion is null, no one is waiting on this command
533 * and the structure can be freed after the command completes.
534 */
535 struct completion *completion;
536 union xhci_trb *command_trb;
537 struct list_head cmd_list;
538 /* xHCI command response timeout in milliseconds */
539 unsigned int timeout_ms;
540};
541
542/* drop context bitmasks */
543#define DROP_EP(x) (0x1 << x)
544/* add context bitmasks */
545#define ADD_EP(x) (0x1 << x)
546
547struct xhci_stream_ctx {
548 /* 64-bit stream ring address, cycle state, and stream type */
549 __le64 stream_ring;
550 /* offset 0x14 - 0x1f reserved for HC internal use */
551 __le32 reserved[2];
552};
553
554/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
555#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
556/* Secondary stream array type, dequeue pointer is to a transfer ring */
557#define SCT_SEC_TR 0
558/* Primary stream array type, dequeue pointer is to a transfer ring */
559#define SCT_PRI_TR 1
560/* Dequeue pointer is for a secondary stream array (SSA) with 8 entries */
561#define SCT_SSA_8 2
562#define SCT_SSA_16 3
563#define SCT_SSA_32 4
564#define SCT_SSA_64 5
565#define SCT_SSA_128 6
566#define SCT_SSA_256 7
567
568/* Assume no secondary streams for now */
569struct xhci_stream_info {
570 struct xhci_ring **stream_rings;
571 /* Number of streams, including stream 0 (which drivers can't use) */
572 unsigned int num_streams;
573 /* The stream context array may be bigger than
574 * the number of streams the driver asked for
575 */
576 struct xhci_stream_ctx *stream_ctx_array;
577 unsigned int num_stream_ctxs;
578 dma_addr_t ctx_array_dma;
579 /* For mapping physical TRB addresses to segments in stream rings */
580 struct radix_tree_root trb_address_map;
581 struct xhci_command *free_streams_command;
582};
583
584#define SMALL_STREAM_ARRAY_SIZE 256
585#define MEDIUM_STREAM_ARRAY_SIZE 1024
586
587/* Some Intel xHCI host controllers need software to keep track of the bus
588 * bandwidth. Keep track of endpoint info here. Each root port is allocated
589 * the full bus bandwidth. We must also treat TTs (including each port under a
590 * multi-TT hub) as a separate bandwidth domain. The direct memory interface
591 * (DMI) also limits the total bandwidth (across all domains) that can be used.
592 */
593struct xhci_bw_info {
594 /* ep_interval is zero-based */
595 unsigned int ep_interval;
596 /* mult and num_packets are one-based */
597 unsigned int mult;
598 unsigned int num_packets;
599 unsigned int max_packet_size;
600 unsigned int max_esit_payload;
601 unsigned int type;
602};
603
604/* "Block" sizes in bytes the hardware uses for different device speeds.
605 * The logic in this part of the hardware limits the number of bits the hardware
606 * can use, so must represent bandwidth in a less precise manner to mimic what
607 * the scheduler hardware computes.
608 */
609#define FS_BLOCK 1
610#define HS_BLOCK 4
611#define SS_BLOCK 16
612#define DMI_BLOCK 32
613
614/* Each device speed has a protocol overhead (CRC, bit stuffing, etc) associated
615 * with each byte transferred. SuperSpeed devices have an initial overhead to
616 * set up bursts. These are in blocks, see above. LS overhead has already been
617 * translated into FS blocks.
618 */
619#define DMI_OVERHEAD 8
620#define DMI_OVERHEAD_BURST 4
621#define SS_OVERHEAD 8
622#define SS_OVERHEAD_BURST 32
623#define HS_OVERHEAD 26
624#define FS_OVERHEAD 20
625#define LS_OVERHEAD 128
626/* The TTs need to claim roughly twice as much bandwidth (94 bytes per
627 * microframe ~= 24Mbps) of the HS bus as the devices can actually use because
628 * of overhead associated with split transfers crossing microframe boundaries.
629 * 31 blocks is pure protocol overhead.
630 */
631#define TT_HS_OVERHEAD (31 + 94)
632#define TT_DMI_OVERHEAD (25 + 12)
633
634/* Bandwidth limits in blocks */
635#define FS_BW_LIMIT 1285
636#define TT_BW_LIMIT 1320
637#define HS_BW_LIMIT 1607
638#define SS_BW_LIMIT_IN 3906
639#define DMI_BW_LIMIT_IN 3906
640#define SS_BW_LIMIT_OUT 3906
641#define DMI_BW_LIMIT_OUT 3906
642
643/* Percentage of bus bandwidth reserved for non-periodic transfers */
644#define FS_BW_RESERVED 10
645#define HS_BW_RESERVED 20
646#define SS_BW_RESERVED 10
647
648struct xhci_virt_ep {
649 struct xhci_virt_device *vdev; /* parent */
650 unsigned int ep_index;
651 struct xhci_ring *ring;
652 /* Related to endpoints that are configured to use stream IDs only */
653 struct xhci_stream_info *stream_info;
654 /* Temporary storage in case the configure endpoint command fails and we
655 * have to restore the device state to the previous state
656 */
657 struct xhci_ring *new_ring;
658 unsigned int err_count;
659 unsigned int ep_state;
660#define SET_DEQ_PENDING (1 << 0)
661#define EP_HALTED (1 << 1) /* For stall handling */
662#define EP_STOP_CMD_PENDING (1 << 2) /* For URB cancellation */
663/* Transitioning the endpoint to using streams, don't enqueue URBs */
664#define EP_GETTING_STREAMS (1 << 3)
665#define EP_HAS_STREAMS (1 << 4)
666/* Transitioning the endpoint to not using streams, don't enqueue URBs */
667#define EP_GETTING_NO_STREAMS (1 << 5)
668#define EP_HARD_CLEAR_TOGGLE (1 << 6)
669#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
670/* usb_hub_clear_tt_buffer is in progress */
671#define EP_CLEARING_TT (1 << 8)
672 /* ---- Related to URB cancellation ---- */
673 struct list_head cancelled_td_list;
674 struct xhci_hcd *xhci;
675 /* Dequeue pointer and dequeue segment for a submitted Set TR Dequeue
676 * command. We'll need to update the ring's dequeue segment and dequeue
677 * pointer after the command completes.
678 */
679 struct xhci_segment *queued_deq_seg;
680 union xhci_trb *queued_deq_ptr;
681 /*
682 * Sometimes the xHC can not process isochronous endpoint ring quickly
683 * enough, and it will miss some isoc tds on the ring and generate
684 * a Missed Service Error Event.
685 * Set skip flag when receive a Missed Service Error Event and
686 * process the missed tds on the endpoint ring.
687 */
688 bool skip;
689 /* Bandwidth checking storage */
690 struct xhci_bw_info bw_info;
691 struct list_head bw_endpoint_list;
692 /* Isoch Frame ID checking storage */
693 int next_frame_id;
694 /* Use new Isoch TRB layout needed for extended TBC support */
695 bool use_extended_tbc;
696};
697
698enum xhci_overhead_type {
699 LS_OVERHEAD_TYPE = 0,
700 FS_OVERHEAD_TYPE,
701 HS_OVERHEAD_TYPE,
702};
703
704struct xhci_interval_bw {
705 unsigned int num_packets;
706 /* Sorted by max packet size.
707 * Head of the list is the greatest max packet size.
708 */
709 struct list_head endpoints;
710 /* How many endpoints of each speed are present. */
711 unsigned int overhead[3];
712};
713
714#define XHCI_MAX_INTERVAL 16
715
716struct xhci_interval_bw_table {
717 unsigned int interval0_esit_payload;
718 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
719 /* Includes reserved bandwidth for async endpoints */
720 unsigned int bw_used;
721 unsigned int ss_bw_in;
722 unsigned int ss_bw_out;
723};
724
725#define EP_CTX_PER_DEV 31
726
727struct xhci_virt_device {
728 int slot_id;
729 struct usb_device *udev;
730 /*
731 * Commands to the hardware are passed an "input context" that
732 * tells the hardware what to change in its data structures.
733 * The hardware will return changes in an "output context" that
734 * software must allocate for the hardware. We need to keep
735 * track of input and output contexts separately because
736 * these commands might fail and we don't trust the hardware.
737 */
738 struct xhci_container_ctx *out_ctx;
739 /* Used for addressing devices and configuration changes */
740 struct xhci_container_ctx *in_ctx;
741 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
742 struct xhci_port *rhub_port;
743 struct xhci_interval_bw_table *bw_table;
744 struct xhci_tt_bw_info *tt_info;
745 /*
746 * flags for state tracking based on events and issued commands.
747 * Software can not rely on states from output contexts because of
748 * latency between events and xHC updating output context values.
749 * See xhci 1.1 section 4.8.3 for more details
750 */
751 unsigned long flags;
752#define VDEV_PORT_ERROR BIT(0) /* Port error, link inactive */
753
754 /* The current max exit latency for the enabled USB3 link states. */
755 u16 current_mel;
756 /* Used for the debugfs interfaces. */
757 void *debugfs_private;
758};
759
760/*
761 * For each roothub, keep track of the bandwidth information for each periodic
762 * interval.
763 *
764 * If a high speed hub is attached to the roothub, each TT associated with that
765 * hub is a separate bandwidth domain. The interval information for the
766 * endpoints on the devices under that TT will appear in the TT structure.
767 */
768struct xhci_root_port_bw_info {
769 struct list_head tts;
770 unsigned int num_active_tts;
771 struct xhci_interval_bw_table bw_table;
772};
773
774struct xhci_tt_bw_info {
775 struct list_head tt_list;
776 int slot_id;
777 int ttport;
778 struct xhci_interval_bw_table bw_table;
779 int active_eps;
780};
781
782
783/**
784 * struct xhci_device_context_array
785 * @dev_context_ptr array of 64-bit DMA addresses for device contexts
786 */
787struct xhci_device_context_array {
788 /* 64-bit device addresses; we only write 32-bit addresses */
789 __le64 dev_context_ptrs[MAX_HC_SLOTS];
790 /* private xHCD pointers */
791 dma_addr_t dma;
792};
793/* TODO: write function to set the 64-bit device DMA address */
794/*
795 * TODO: change this to be dynamically sized at HC mem init time since the HC
796 * might not be able to handle the maximum number of devices possible.
797 */
798
799
800struct xhci_transfer_event {
801 /* 64-bit buffer address, or immediate data */
802 __le64 buffer;
803 __le32 transfer_len;
804 /* This field is interpreted differently based on the type of TRB */
805 __le32 flags;
806};
807
808/* Transfer event TRB length bit mask */
809/* bits 0:23 */
810#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
811
812/** Transfer Event bit fields **/
813#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
814
815/* Completion Code - only applicable for some types of TRBs */
816#define COMP_CODE_MASK (0xff << 24)
817#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
818#define COMP_INVALID 0
819#define COMP_SUCCESS 1
820#define COMP_DATA_BUFFER_ERROR 2
821#define COMP_BABBLE_DETECTED_ERROR 3
822#define COMP_USB_TRANSACTION_ERROR 4
823#define COMP_TRB_ERROR 5
824#define COMP_STALL_ERROR 6
825#define COMP_RESOURCE_ERROR 7
826#define COMP_BANDWIDTH_ERROR 8
827#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
828#define COMP_INVALID_STREAM_TYPE_ERROR 10
829#define COMP_SLOT_NOT_ENABLED_ERROR 11
830#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
831#define COMP_SHORT_PACKET 13
832#define COMP_RING_UNDERRUN 14
833#define COMP_RING_OVERRUN 15
834#define COMP_VF_EVENT_RING_FULL_ERROR 16
835#define COMP_PARAMETER_ERROR 17
836#define COMP_BANDWIDTH_OVERRUN_ERROR 18
837#define COMP_CONTEXT_STATE_ERROR 19
838#define COMP_NO_PING_RESPONSE_ERROR 20
839#define COMP_EVENT_RING_FULL_ERROR 21
840#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
841#define COMP_MISSED_SERVICE_ERROR 23
842#define COMP_COMMAND_RING_STOPPED 24
843#define COMP_COMMAND_ABORTED 25
844#define COMP_STOPPED 26
845#define COMP_STOPPED_LENGTH_INVALID 27
846#define COMP_STOPPED_SHORT_PACKET 28
847#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
848#define COMP_ISOCH_BUFFER_OVERRUN 31
849#define COMP_EVENT_LOST_ERROR 32
850#define COMP_UNDEFINED_ERROR 33
851#define COMP_INVALID_STREAM_ID_ERROR 34
852#define COMP_SECONDARY_BANDWIDTH_ERROR 35
853#define COMP_SPLIT_TRANSACTION_ERROR 36
854
855static inline const char *xhci_trb_comp_code_string(u8 status)
856{
857 switch (status) {
858 case COMP_INVALID:
859 return "Invalid";
860 case COMP_SUCCESS:
861 return "Success";
862 case COMP_DATA_BUFFER_ERROR:
863 return "Data Buffer Error";
864 case COMP_BABBLE_DETECTED_ERROR:
865 return "Babble Detected";
866 case COMP_USB_TRANSACTION_ERROR:
867 return "USB Transaction Error";
868 case COMP_TRB_ERROR:
869 return "TRB Error";
870 case COMP_STALL_ERROR:
871 return "Stall Error";
872 case COMP_RESOURCE_ERROR:
873 return "Resource Error";
874 case COMP_BANDWIDTH_ERROR:
875 return "Bandwidth Error";
876 case COMP_NO_SLOTS_AVAILABLE_ERROR:
877 return "No Slots Available Error";
878 case COMP_INVALID_STREAM_TYPE_ERROR:
879 return "Invalid Stream Type Error";
880 case COMP_SLOT_NOT_ENABLED_ERROR:
881 return "Slot Not Enabled Error";
882 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
883 return "Endpoint Not Enabled Error";
884 case COMP_SHORT_PACKET:
885 return "Short Packet";
886 case COMP_RING_UNDERRUN:
887 return "Ring Underrun";
888 case COMP_RING_OVERRUN:
889 return "Ring Overrun";
890 case COMP_VF_EVENT_RING_FULL_ERROR:
891 return "VF Event Ring Full Error";
892 case COMP_PARAMETER_ERROR:
893 return "Parameter Error";
894 case COMP_BANDWIDTH_OVERRUN_ERROR:
895 return "Bandwidth Overrun Error";
896 case COMP_CONTEXT_STATE_ERROR:
897 return "Context State Error";
898 case COMP_NO_PING_RESPONSE_ERROR:
899 return "No Ping Response Error";
900 case COMP_EVENT_RING_FULL_ERROR:
901 return "Event Ring Full Error";
902 case COMP_INCOMPATIBLE_DEVICE_ERROR:
903 return "Incompatible Device Error";
904 case COMP_MISSED_SERVICE_ERROR:
905 return "Missed Service Error";
906 case COMP_COMMAND_RING_STOPPED:
907 return "Command Ring Stopped";
908 case COMP_COMMAND_ABORTED:
909 return "Command Aborted";
910 case COMP_STOPPED:
911 return "Stopped";
912 case COMP_STOPPED_LENGTH_INVALID:
913 return "Stopped - Length Invalid";
914 case COMP_STOPPED_SHORT_PACKET:
915 return "Stopped - Short Packet";
916 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
917 return "Max Exit Latency Too Large Error";
918 case COMP_ISOCH_BUFFER_OVERRUN:
919 return "Isoch Buffer Overrun";
920 case COMP_EVENT_LOST_ERROR:
921 return "Event Lost Error";
922 case COMP_UNDEFINED_ERROR:
923 return "Undefined Error";
924 case COMP_INVALID_STREAM_ID_ERROR:
925 return "Invalid Stream ID Error";
926 case COMP_SECONDARY_BANDWIDTH_ERROR:
927 return "Secondary Bandwidth Error";
928 case COMP_SPLIT_TRANSACTION_ERROR:
929 return "Split Transaction Error";
930 default:
931 return "Unknown!!";
932 }
933}
934
935struct xhci_link_trb {
936 /* 64-bit segment pointer*/
937 __le64 segment_ptr;
938 __le32 intr_target;
939 __le32 control;
940};
941
942/* control bitfields */
943#define LINK_TOGGLE (0x1<<1)
944
945/* Command completion event TRB */
946struct xhci_event_cmd {
947 /* Pointer to command TRB, or the value passed by the event data trb */
948 __le64 cmd_trb;
949 __le32 status;
950 __le32 flags;
951};
952
953/* flags bitmasks */
954
955/* Address device - disable SetAddress */
956#define TRB_BSR (1<<9)
957
958/* Configure Endpoint - Deconfigure */
959#define TRB_DC (1<<9)
960
961/* Stop Ring - Transfer State Preserve */
962#define TRB_TSP (1<<9)
963
964enum xhci_ep_reset_type {
965 EP_HARD_RESET,
966 EP_SOFT_RESET,
967};
968
969/* Force Event */
970#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
971#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
972
973/* Set Latency Tolerance Value */
974#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
975
976/* Get Port Bandwidth */
977#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
978
979/* Force Header */
980#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
981#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
982
983enum xhci_setup_dev {
984 SETUP_CONTEXT_ONLY,
985 SETUP_CONTEXT_ADDRESS,
986};
987
988/* bits 16:23 are the virtual function ID */
989/* bits 24:31 are the slot ID */
990#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
991#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
992
993/* Stop Endpoint TRB - ep_index to endpoint ID for this TRB */
994#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
995#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
996
997#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
998#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
999#define LAST_EP_INDEX 30
1000
1001/* Set TR Dequeue Pointer command TRB fields, 6.4.3.9 */
1002#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1003#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1004#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1005
1006/* Link TRB specific fields */
1007#define TRB_TC (1<<1)
1008
1009/* Port Status Change Event TRB fields */
1010/* Port ID - bits 31:24 */
1011#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1012
1013#define EVENT_DATA (1 << 2)
1014
1015/* Normal TRB fields */
1016/* transfer_len bitmasks - bits 0:16 */
1017#define TRB_LEN(p) ((p) & 0x1ffff)
1018/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */
1019#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1020#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1021/* xhci 1.1 uses the TD_SIZE field for TBC if Extended TBC is enabled (ETE) */
1022#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1023/* Interrupter Target - which MSI-X vector to target the completion event at */
1024#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1025#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1026/* Total burst count field, Rsvdz on xhci 1.1 with Extended TBC enabled (ETE) */
1027#define TRB_TBC(p) (((p) & 0x3) << 7)
1028#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1029
1030/* Cycle bit - indicates TRB ownership by HC or HCD */
1031#define TRB_CYCLE (1<<0)
1032/*
1033 * Force next event data TRB to be evaluated before task switch.
1034 * Used to pass OS data back after a TD completes.
1035 */
1036#define TRB_ENT (1<<1)
1037/* Interrupt on short packet */
1038#define TRB_ISP (1<<2)
1039/* Set PCIe no snoop attribute */
1040#define TRB_NO_SNOOP (1<<3)
1041/* Chain multiple TRBs into a TD */
1042#define TRB_CHAIN (1<<4)
1043/* Interrupt on completion */
1044#define TRB_IOC (1<<5)
1045/* The buffer pointer contains immediate data */
1046#define TRB_IDT (1<<6)
1047/* TDs smaller than this might use IDT */
1048#define TRB_IDT_MAX_SIZE 8
1049
1050/* Block Event Interrupt */
1051#define TRB_BEI (1<<9)
1052
1053/* Control transfer TRB specific fields */
1054#define TRB_DIR_IN (1<<16)
1055#define TRB_TX_TYPE(p) ((p) << 16)
1056#define TRB_DATA_OUT 2
1057#define TRB_DATA_IN 3
1058
1059/* Isochronous TRB specific fields */
1060#define TRB_SIA (1<<31)
1061#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1062
1063/* TRB cache size for xHC with TRB cache */
1064#define TRB_CACHE_SIZE_HS 8
1065#define TRB_CACHE_SIZE_SS 16
1066
1067struct xhci_generic_trb {
1068 __le32 field[4];
1069};
1070
1071union xhci_trb {
1072 struct xhci_link_trb link;
1073 struct xhci_transfer_event trans_event;
1074 struct xhci_event_cmd event_cmd;
1075 struct xhci_generic_trb generic;
1076};
1077
1078/* TRB bit mask */
1079#define TRB_TYPE_BITMASK (0xfc00)
1080#define TRB_TYPE(p) ((p) << 10)
1081#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1082/* TRB type IDs */
1083/* bulk, interrupt, isoc scatter/gather, and control data stage */
1084#define TRB_NORMAL 1
1085/* setup stage for control transfers */
1086#define TRB_SETUP 2
1087/* data stage for control transfers */
1088#define TRB_DATA 3
1089/* status stage for control transfers */
1090#define TRB_STATUS 4
1091/* isoc transfers */
1092#define TRB_ISOC 5
1093/* TRB for linking ring segments */
1094#define TRB_LINK 6
1095#define TRB_EVENT_DATA 7
1096/* Transfer Ring No-op (not for the command ring) */
1097#define TRB_TR_NOOP 8
1098/* Command TRBs */
1099/* Enable Slot Command */
1100#define TRB_ENABLE_SLOT 9
1101/* Disable Slot Command */
1102#define TRB_DISABLE_SLOT 10
1103/* Address Device Command */
1104#define TRB_ADDR_DEV 11
1105/* Configure Endpoint Command */
1106#define TRB_CONFIG_EP 12
1107/* Evaluate Context Command */
1108#define TRB_EVAL_CONTEXT 13
1109/* Reset Endpoint Command */
1110#define TRB_RESET_EP 14
1111/* Stop Transfer Ring Command */
1112#define TRB_STOP_RING 15
1113/* Set Transfer Ring Dequeue Pointer Command */
1114#define TRB_SET_DEQ 16
1115/* Reset Device Command */
1116#define TRB_RESET_DEV 17
1117/* Force Event Command (opt) */
1118#define TRB_FORCE_EVENT 18
1119/* Negotiate Bandwidth Command (opt) */
1120#define TRB_NEG_BANDWIDTH 19
1121/* Set Latency Tolerance Value Command (opt) */
1122#define TRB_SET_LT 20
1123/* Get port bandwidth Command */
1124#define TRB_GET_BW 21
1125/* Force Header Command - generate a transaction or link management packet */
1126#define TRB_FORCE_HEADER 22
1127/* No-op Command - not for transfer rings */
1128#define TRB_CMD_NOOP 23
1129/* TRB IDs 24-31 reserved */
1130/* Event TRBS */
1131/* Transfer Event */
1132#define TRB_TRANSFER 32
1133/* Command Completion Event */
1134#define TRB_COMPLETION 33
1135/* Port Status Change Event */
1136#define TRB_PORT_STATUS 34
1137/* Bandwidth Request Event (opt) */
1138#define TRB_BANDWIDTH_EVENT 35
1139/* Doorbell Event (opt) */
1140#define TRB_DOORBELL 36
1141/* Host Controller Event */
1142#define TRB_HC_EVENT 37
1143/* Device Notification Event - device sent function wake notification */
1144#define TRB_DEV_NOTE 38
1145/* MFINDEX Wrap Event - microframe counter wrapped */
1146#define TRB_MFINDEX_WRAP 39
1147/* TRB IDs 40-47 reserved, 48-63 is vendor-defined */
1148#define TRB_VENDOR_DEFINED_LOW 48
1149/* Nec vendor-specific command completion event. */
1150#define TRB_NEC_CMD_COMP 48
1151/* Get NEC firmware revision. */
1152#define TRB_NEC_GET_FW 49
1153
1154static inline const char *xhci_trb_type_string(u8 type)
1155{
1156 switch (type) {
1157 case TRB_NORMAL:
1158 return "Normal";
1159 case TRB_SETUP:
1160 return "Setup Stage";
1161 case TRB_DATA:
1162 return "Data Stage";
1163 case TRB_STATUS:
1164 return "Status Stage";
1165 case TRB_ISOC:
1166 return "Isoch";
1167 case TRB_LINK:
1168 return "Link";
1169 case TRB_EVENT_DATA:
1170 return "Event Data";
1171 case TRB_TR_NOOP:
1172 return "No-Op";
1173 case TRB_ENABLE_SLOT:
1174 return "Enable Slot Command";
1175 case TRB_DISABLE_SLOT:
1176 return "Disable Slot Command";
1177 case TRB_ADDR_DEV:
1178 return "Address Device Command";
1179 case TRB_CONFIG_EP:
1180 return "Configure Endpoint Command";
1181 case TRB_EVAL_CONTEXT:
1182 return "Evaluate Context Command";
1183 case TRB_RESET_EP:
1184 return "Reset Endpoint Command";
1185 case TRB_STOP_RING:
1186 return "Stop Ring Command";
1187 case TRB_SET_DEQ:
1188 return "Set TR Dequeue Pointer Command";
1189 case TRB_RESET_DEV:
1190 return "Reset Device Command";
1191 case TRB_FORCE_EVENT:
1192 return "Force Event Command";
1193 case TRB_NEG_BANDWIDTH:
1194 return "Negotiate Bandwidth Command";
1195 case TRB_SET_LT:
1196 return "Set Latency Tolerance Value Command";
1197 case TRB_GET_BW:
1198 return "Get Port Bandwidth Command";
1199 case TRB_FORCE_HEADER:
1200 return "Force Header Command";
1201 case TRB_CMD_NOOP:
1202 return "No-Op Command";
1203 case TRB_TRANSFER:
1204 return "Transfer Event";
1205 case TRB_COMPLETION:
1206 return "Command Completion Event";
1207 case TRB_PORT_STATUS:
1208 return "Port Status Change Event";
1209 case TRB_BANDWIDTH_EVENT:
1210 return "Bandwidth Request Event";
1211 case TRB_DOORBELL:
1212 return "Doorbell Event";
1213 case TRB_HC_EVENT:
1214 return "Host Controller Event";
1215 case TRB_DEV_NOTE:
1216 return "Device Notification Event";
1217 case TRB_MFINDEX_WRAP:
1218 return "MFINDEX Wrap Event";
1219 case TRB_NEC_CMD_COMP:
1220 return "NEC Command Completion Event";
1221 case TRB_NEC_GET_FW:
1222 return "NET Get Firmware Revision Command";
1223 default:
1224 return "UNKNOWN";
1225 }
1226}
1227
1228#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1229/* Above, but for __le32 types -- can avoid work by swapping constants: */
1230#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1231 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1232#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1233 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1234
1235#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1236#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1237
1238/*
1239 * TRBS_PER_SEGMENT must be a multiple of 4,
1240 * since the command ring is 64-byte aligned.
1241 * It must also be greater than 16.
1242 */
1243#define TRBS_PER_SEGMENT 256
1244/* Allow two commands + a link TRB, along with any reserved command TRBs */
1245#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1246#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1247#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1248/* TRB buffer pointers can't cross 64KB boundaries */
1249#define TRB_MAX_BUFF_SHIFT 16
1250#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1251/* How much data is left before the 64KB boundary? */
1252#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1253 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1254#define MAX_SOFT_RETRY 3
1255/*
1256 * Limits of consecutive isoc trbs that can Block Event Interrupt (BEI) if
1257 * XHCI_AVOID_BEI quirk is in use.
1258 */
1259#define AVOID_BEI_INTERVAL_MIN 8
1260#define AVOID_BEI_INTERVAL_MAX 32
1261
1262struct xhci_segment {
1263 union xhci_trb *trbs;
1264 /* private to HCD */
1265 struct xhci_segment *next;
1266 unsigned int num;
1267 dma_addr_t dma;
1268 /* Max packet sized bounce buffer for td-fragmant alignment */
1269 dma_addr_t bounce_dma;
1270 void *bounce_buf;
1271 unsigned int bounce_offs;
1272 unsigned int bounce_len;
1273};
1274
1275enum xhci_cancelled_td_status {
1276 TD_DIRTY = 0,
1277 TD_HALTED,
1278 TD_CLEARING_CACHE,
1279 TD_CLEARED,
1280};
1281
1282struct xhci_td {
1283 struct list_head td_list;
1284 struct list_head cancelled_td_list;
1285 int status;
1286 enum xhci_cancelled_td_status cancel_status;
1287 struct urb *urb;
1288 struct xhci_segment *start_seg;
1289 union xhci_trb *first_trb;
1290 union xhci_trb *last_trb;
1291 struct xhci_segment *last_trb_seg;
1292 struct xhci_segment *bounce_seg;
1293 /* actual_length of the URB has already been set */
1294 bool urb_length_set;
1295 bool error_mid_td;
1296 unsigned int num_trbs;
1297};
1298
1299/*
1300 * xHCI command default timeout value in milliseconds.
1301 * USB 3.2 spec, section 9.2.6.1
1302 */
1303#define XHCI_CMD_DEFAULT_TIMEOUT 5000
1304
1305/* command descriptor */
1306struct xhci_cd {
1307 struct xhci_command *command;
1308 union xhci_trb *cmd_trb;
1309};
1310
1311enum xhci_ring_type {
1312 TYPE_CTRL = 0,
1313 TYPE_ISOC,
1314 TYPE_BULK,
1315 TYPE_INTR,
1316 TYPE_STREAM,
1317 TYPE_COMMAND,
1318 TYPE_EVENT,
1319};
1320
1321static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1322{
1323 switch (type) {
1324 case TYPE_CTRL:
1325 return "CTRL";
1326 case TYPE_ISOC:
1327 return "ISOC";
1328 case TYPE_BULK:
1329 return "BULK";
1330 case TYPE_INTR:
1331 return "INTR";
1332 case TYPE_STREAM:
1333 return "STREAM";
1334 case TYPE_COMMAND:
1335 return "CMD";
1336 case TYPE_EVENT:
1337 return "EVENT";
1338 }
1339
1340 return "UNKNOWN";
1341}
1342
1343struct xhci_ring {
1344 struct xhci_segment *first_seg;
1345 struct xhci_segment *last_seg;
1346 union xhci_trb *enqueue;
1347 struct xhci_segment *enq_seg;
1348 union xhci_trb *dequeue;
1349 struct xhci_segment *deq_seg;
1350 struct list_head td_list;
1351 /*
1352 * Write the cycle state into the TRB cycle field to give ownership of
1353 * the TRB to the host controller (if we are the producer), or to check
1354 * if we own the TRB (if we are the consumer). See section 4.9.1.
1355 */
1356 u32 cycle_state;
1357 unsigned int stream_id;
1358 unsigned int num_segs;
1359 unsigned int num_trbs_free; /* used only by xhci DbC */
1360 unsigned int bounce_buf_len;
1361 enum xhci_ring_type type;
1362 bool last_td_was_short;
1363 struct radix_tree_root *trb_address_map;
1364};
1365
1366struct xhci_erst_entry {
1367 /* 64-bit event ring segment address */
1368 __le64 seg_addr;
1369 __le32 seg_size;
1370 /* Set to zero */
1371 __le32 rsvd;
1372};
1373
1374struct xhci_erst {
1375 struct xhci_erst_entry *entries;
1376 unsigned int num_entries;
1377 /* xhci->event_ring keeps track of segment dma addresses */
1378 dma_addr_t erst_dma_addr;
1379 /* Num entries the ERST can contain */
1380 unsigned int erst_size;
1381};
1382
1383struct xhci_scratchpad {
1384 u64 *sp_array;
1385 dma_addr_t sp_dma;
1386 void **sp_buffers;
1387};
1388
1389struct urb_priv {
1390 int num_tds;
1391 int num_tds_done;
1392 struct xhci_td td[] __counted_by(num_tds);
1393};
1394
1395/* Number of Event Ring segments to allocate, when amount is not specified. (spec allows 32k) */
1396#define ERST_DEFAULT_SEGS 2
1397/* Poll every 60 seconds */
1398#define POLL_TIMEOUT 60
1399/* Stop endpoint command timeout (secs) for URB cancellation watchdog timer */
1400#define XHCI_STOP_EP_CMD_TIMEOUT 5
1401/* XXX: Make these module parameters */
1402
1403struct s3_save {
1404 u32 command;
1405 u32 dev_nt;
1406 u64 dcbaa_ptr;
1407 u32 config_reg;
1408};
1409
1410/* Use for lpm */
1411struct dev_info {
1412 u32 dev_id;
1413 struct list_head list;
1414};
1415
1416struct xhci_bus_state {
1417 unsigned long bus_suspended;
1418 unsigned long next_statechange;
1419
1420 /* Port suspend arrays are indexed by the portnum of the fake roothub */
1421 /* ports suspend status arrays - max 31 ports for USB2, 15 for USB3 */
1422 u32 port_c_suspend;
1423 u32 suspended_ports;
1424 u32 port_remote_wakeup;
1425 /* which ports have started to resume */
1426 unsigned long resuming_ports;
1427};
1428
1429struct xhci_interrupter {
1430 struct xhci_ring *event_ring;
1431 struct xhci_erst erst;
1432 struct xhci_intr_reg __iomem *ir_set;
1433 unsigned int intr_num;
1434 bool ip_autoclear;
1435 u32 isoc_bei_interval;
1436 /* For interrupter registers save and restore over suspend/resume */
1437 u32 s3_irq_pending;
1438 u32 s3_irq_control;
1439 u32 s3_erst_size;
1440 u64 s3_erst_base;
1441 u64 s3_erst_dequeue;
1442};
1443/*
1444 * It can take up to 20 ms to transition from RExit to U0 on the
1445 * Intel Lynx Point LP xHCI host.
1446 */
1447#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1448struct xhci_port_cap {
1449 u32 *psi; /* array of protocol speed ID entries */
1450 u8 psi_count;
1451 u8 psi_uid_count;
1452 u8 maj_rev;
1453 u8 min_rev;
1454};
1455
1456struct xhci_port {
1457 __le32 __iomem *addr;
1458 int hw_portnum;
1459 int hcd_portnum;
1460 struct xhci_hub *rhub;
1461 struct xhci_port_cap *port_cap;
1462 unsigned int lpm_incapable:1;
1463 unsigned long resume_timestamp;
1464 bool rexit_active;
1465 /* Slot ID is the index of the device directly connected to the port */
1466 int slot_id;
1467 struct completion rexit_done;
1468 struct completion u3exit_done;
1469};
1470
1471struct xhci_hub {
1472 struct xhci_port **ports;
1473 unsigned int num_ports;
1474 struct usb_hcd *hcd;
1475 /* keep track of bus suspend info */
1476 struct xhci_bus_state bus_state;
1477 /* supported prococol extended capabiliy values */
1478 u8 maj_rev;
1479 u8 min_rev;
1480};
1481
1482/* There is one xhci_hcd structure per controller */
1483struct xhci_hcd {
1484 struct usb_hcd *main_hcd;
1485 struct usb_hcd *shared_hcd;
1486 /* glue to PCI and HCD framework */
1487 struct xhci_cap_regs __iomem *cap_regs;
1488 struct xhci_op_regs __iomem *op_regs;
1489 struct xhci_run_regs __iomem *run_regs;
1490 struct xhci_doorbell_array __iomem *dba;
1491
1492 /* Cached register copies of read-only HC data */
1493 __u32 hcs_params1;
1494 __u32 hcs_params2;
1495 __u32 hcs_params3;
1496 __u32 hcc_params;
1497 __u32 hcc_params2;
1498
1499 spinlock_t lock;
1500
1501 /* packed release number */
1502 u8 sbrn;
1503 u16 hci_version;
1504 u8 max_slots;
1505 u16 max_interrupters;
1506 u8 max_ports;
1507 u8 isoc_threshold;
1508 /* imod_interval in ns (I * 250ns) */
1509 u32 imod_interval;
1510 int event_ring_max;
1511 /* 4KB min, 128MB max */
1512 int page_size;
1513 /* Valid values are 12 to 20, inclusive */
1514 int page_shift;
1515 /* MSI-X/MSI vectors */
1516 int nvecs;
1517 /* optional clocks */
1518 struct clk *clk;
1519 struct clk *reg_clk;
1520 /* optional reset controller */
1521 struct reset_control *reset;
1522 /* data structures */
1523 struct xhci_device_context_array *dcbaa;
1524 struct xhci_interrupter **interrupters;
1525 struct xhci_ring *cmd_ring;
1526 unsigned int cmd_ring_state;
1527#define CMD_RING_STATE_RUNNING (1 << 0)
1528#define CMD_RING_STATE_ABORTED (1 << 1)
1529#define CMD_RING_STATE_STOPPED (1 << 2)
1530 struct list_head cmd_list;
1531 unsigned int cmd_ring_reserved_trbs;
1532 struct delayed_work cmd_timer;
1533 struct completion cmd_ring_stop_completion;
1534 struct xhci_command *current_cmd;
1535
1536 /* Scratchpad */
1537 struct xhci_scratchpad *scratchpad;
1538
1539 /* slot enabling and address device helpers */
1540 /* these are not thread safe so use mutex */
1541 struct mutex mutex;
1542 /* Internal mirror of the HW's dcbaa */
1543 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1544 /* For keeping track of bandwidth domains per roothub. */
1545 struct xhci_root_port_bw_info *rh_bw;
1546
1547 /* DMA pools */
1548 struct dma_pool *device_pool;
1549 struct dma_pool *segment_pool;
1550 struct dma_pool *small_streams_pool;
1551 struct dma_pool *medium_streams_pool;
1552
1553 /* Host controller watchdog timer structures */
1554 unsigned int xhc_state;
1555 unsigned long run_graceperiod;
1556 struct s3_save s3;
1557/* Host controller is dying - not responding to commands. "I'm not dead yet!"
1558 *
1559 * xHC interrupts have been disabled and a watchdog timer will (or has already)
1560 * halt the xHCI host, and complete all URBs with an -ESHUTDOWN code. Any code
1561 * that sees this status (other than the timer that set it) should stop touching
1562 * hardware immediately. Interrupt handlers should return immediately when
1563 * they see this status (any time they drop and re-acquire xhci->lock).
1564 * xhci_urb_dequeue() should call usb_hcd_check_unlink_urb() and return without
1565 * putting the TD on the canceled list, etc.
1566 *
1567 * There are no reports of xHCI host controllers that display this issue.
1568 */
1569#define XHCI_STATE_DYING (1 << 0)
1570#define XHCI_STATE_HALTED (1 << 1)
1571#define XHCI_STATE_REMOVING (1 << 2)
1572 unsigned long long quirks;
1573#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1574#define XHCI_RESET_EP_QUIRK BIT_ULL(1) /* Deprecated */
1575#define XHCI_NEC_HOST BIT_ULL(2)
1576#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1577#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1578/*
1579 * Certain Intel host controllers have a limit to the number of endpoint
1580 * contexts they can handle. Ideally, they would signal that they can't handle
1581 * anymore endpoint contexts by returning a Resource Error for the Configure
1582 * Endpoint command, but they don't. Instead they expect software to keep track
1583 * of the number of active endpoints for them, across configure endpoint
1584 * commands, reset device commands, disable slot commands, and address device
1585 * commands.
1586 */
1587#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1588#define XHCI_BROKEN_MSI BIT_ULL(6)
1589#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1590#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1591#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1592#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1593#define XHCI_LPM_SUPPORT BIT_ULL(11)
1594#define XHCI_INTEL_HOST BIT_ULL(12)
1595#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1596#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1597#define XHCI_AVOID_BEI BIT_ULL(15)
1598#define XHCI_PLAT BIT_ULL(16) /* Deprecated */
1599#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1600#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1601/* For controllers with a broken beyond repair streams implementation */
1602#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1603#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1604#define XHCI_MTK_HOST BIT_ULL(21)
1605#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1606#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1607#define XHCI_MISSING_CAS BIT_ULL(24)
1608/* For controller with a broken Port Disable implementation */
1609#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1610#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1611#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1612#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1613#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1614#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1615#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1616#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1617#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1618#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1619#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1620#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1621#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1622#define XHCI_DISABLE_SPARSE BIT_ULL(38)
1623#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1624#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1625#define XHCI_BROKEN_D3COLD_S2I BIT_ULL(41)
1626#define XHCI_EP_CTX_BROKEN_DCS BIT_ULL(42)
1627#define XHCI_SUSPEND_RESUME_CLKS BIT_ULL(43)
1628#define XHCI_RESET_TO_DEFAULT BIT_ULL(44)
1629#define XHCI_ZHAOXIN_TRB_FETCH BIT_ULL(45)
1630#define XHCI_ZHAOXIN_HOST BIT_ULL(46)
1631
1632 unsigned int num_active_eps;
1633 unsigned int limit_active_eps;
1634 struct xhci_port *hw_ports;
1635 struct xhci_hub usb2_rhub;
1636 struct xhci_hub usb3_rhub;
1637 /* support xHCI 1.0 spec USB2 hardware LPM */
1638 unsigned hw_lpm_support:1;
1639 /* Broken Suspend flag for SNPS Suspend resume issue */
1640 unsigned broken_suspend:1;
1641 /* Indicates that omitting hcd is supported if root hub has no ports */
1642 unsigned allow_single_roothub:1;
1643 /* cached usb2 extened protocol capabilites */
1644 u32 *ext_caps;
1645 unsigned int num_ext_caps;
1646 /* cached extended protocol port capabilities */
1647 struct xhci_port_cap *port_caps;
1648 unsigned int num_port_caps;
1649 /* Compliance Mode Recovery Data */
1650 struct timer_list comp_mode_recovery_timer;
1651 u32 port_status_u0;
1652 u16 test_mode;
1653/* Compliance Mode Timer Triggered every 2 seconds */
1654#define COMP_MODE_RCVRY_MSECS 2000
1655
1656 struct dentry *debugfs_root;
1657 struct dentry *debugfs_slots;
1658 struct list_head regset_list;
1659
1660 void *dbc;
1661 /* platform-specific data -- must come last */
1662 unsigned long priv[] __aligned(sizeof(s64));
1663};
1664
1665/* Platform specific overrides to generic XHCI hc_driver ops */
1666struct xhci_driver_overrides {
1667 size_t extra_priv_size;
1668 int (*reset)(struct usb_hcd *hcd);
1669 int (*start)(struct usb_hcd *hcd);
1670 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1671 struct usb_host_endpoint *ep);
1672 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1673 struct usb_host_endpoint *ep);
1674 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1675 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1676 int (*update_hub_device)(struct usb_hcd *hcd, struct usb_device *hdev,
1677 struct usb_tt *tt, gfp_t mem_flags);
1678 int (*hub_control)(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1679 u16 wIndex, char *buf, u16 wLength);
1680};
1681
1682#define XHCI_CFC_DELAY 10
1683
1684/* convert between an HCD pointer and the corresponding EHCI_HCD */
1685static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1686{
1687 struct usb_hcd *primary_hcd;
1688
1689 if (usb_hcd_is_primary_hcd(hcd))
1690 primary_hcd = hcd;
1691 else
1692 primary_hcd = hcd->primary_hcd;
1693
1694 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1695}
1696
1697static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1698{
1699 return xhci->main_hcd;
1700}
1701
1702static inline struct usb_hcd *xhci_get_usb3_hcd(struct xhci_hcd *xhci)
1703{
1704 if (xhci->shared_hcd)
1705 return xhci->shared_hcd;
1706
1707 if (!xhci->usb2_rhub.num_ports)
1708 return xhci->main_hcd;
1709
1710 return NULL;
1711}
1712
1713static inline bool xhci_hcd_is_usb3(struct usb_hcd *hcd)
1714{
1715 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1716
1717 return hcd == xhci_get_usb3_hcd(xhci);
1718}
1719
1720static inline bool xhci_has_one_roothub(struct xhci_hcd *xhci)
1721{
1722 return xhci->allow_single_roothub &&
1723 (!xhci->usb2_rhub.num_ports || !xhci->usb3_rhub.num_ports);
1724}
1725
1726#define xhci_dbg(xhci, fmt, args...) \
1727 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1728#define xhci_err(xhci, fmt, args...) \
1729 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1730#define xhci_warn(xhci, fmt, args...) \
1731 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1732#define xhci_warn_ratelimited(xhci, fmt, args...) \
1733 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1734#define xhci_info(xhci, fmt, args...) \
1735 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1736
1737/*
1738 * Registers should always be accessed with double word or quad word accesses.
1739 *
1740 * Some xHCI implementations may support 64-bit address pointers. Registers
1741 * with 64-bit address pointers should be written to with dword accesses by
1742 * writing the low dword first (ptr[0]), then the high dword (ptr[1]) second.
1743 * xHCI implementations that do not support 64-bit address pointers will ignore
1744 * the high dword, and write order is irrelevant.
1745 */
1746static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1747 __le64 __iomem *regs)
1748{
1749 return lo_hi_readq(regs);
1750}
1751static inline void xhci_write_64(struct xhci_hcd *xhci,
1752 const u64 val, __le64 __iomem *regs)
1753{
1754 lo_hi_writeq(val, regs);
1755}
1756
1757static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1758{
1759 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1760}
1761
1762/* xHCI debugging */
1763char *xhci_get_slot_state(struct xhci_hcd *xhci,
1764 struct xhci_container_ctx *ctx);
1765void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1766 const char *fmt, ...);
1767
1768/* xHCI memory management */
1769void xhci_mem_cleanup(struct xhci_hcd *xhci);
1770int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1771void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1772int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1773int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1774void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1775 struct usb_device *udev);
1776unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1777unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1778void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1779void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1780 struct xhci_virt_device *virt_dev,
1781 int old_active_eps);
1782void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1783void xhci_update_bw_info(struct xhci_hcd *xhci,
1784 struct xhci_container_ctx *in_ctx,
1785 struct xhci_input_control_ctx *ctrl_ctx,
1786 struct xhci_virt_device *virt_dev);
1787void xhci_endpoint_copy(struct xhci_hcd *xhci,
1788 struct xhci_container_ctx *in_ctx,
1789 struct xhci_container_ctx *out_ctx,
1790 unsigned int ep_index);
1791void xhci_slot_copy(struct xhci_hcd *xhci,
1792 struct xhci_container_ctx *in_ctx,
1793 struct xhci_container_ctx *out_ctx);
1794int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1795 struct usb_device *udev, struct usb_host_endpoint *ep,
1796 gfp_t mem_flags);
1797struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
1798 unsigned int num_segs, unsigned int cycle_state,
1799 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
1800void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
1801int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
1802 unsigned int num_trbs, gfp_t flags);
1803void xhci_initialize_ring_info(struct xhci_ring *ring,
1804 unsigned int cycle_state);
1805void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
1806 struct xhci_virt_device *virt_dev,
1807 unsigned int ep_index);
1808struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
1809 unsigned int num_stream_ctxs,
1810 unsigned int num_streams,
1811 unsigned int max_packet, gfp_t flags);
1812void xhci_free_stream_info(struct xhci_hcd *xhci,
1813 struct xhci_stream_info *stream_info);
1814void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
1815 struct xhci_ep_ctx *ep_ctx,
1816 struct xhci_stream_info *stream_info);
1817void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
1818 struct xhci_virt_ep *ep);
1819void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
1820 struct xhci_virt_device *virt_dev, bool drop_control_ep);
1821struct xhci_ring *xhci_dma_to_transfer_ring(
1822 struct xhci_virt_ep *ep,
1823 u64 address);
1824struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1825 bool allocate_completion, gfp_t mem_flags);
1826struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
1827 bool allocate_completion, gfp_t mem_flags);
1828void xhci_urb_free_priv(struct urb_priv *urb_priv);
1829void xhci_free_command(struct xhci_hcd *xhci,
1830 struct xhci_command *command);
1831struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
1832 int type, gfp_t flags);
1833void xhci_free_container_ctx(struct xhci_hcd *xhci,
1834 struct xhci_container_ctx *ctx);
1835struct xhci_interrupter *
1836xhci_create_secondary_interrupter(struct usb_hcd *hcd, unsigned int segs);
1837void xhci_remove_secondary_interrupter(struct usb_hcd
1838 *hcd, struct xhci_interrupter *ir);
1839
1840/* xHCI host controller glue */
1841typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
1842int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, u64 timeout_us);
1843int xhci_handshake_check_state(struct xhci_hcd *xhci, void __iomem *ptr,
1844 u32 mask, u32 done, int usec, unsigned int exit_state);
1845void xhci_quiesce(struct xhci_hcd *xhci);
1846int xhci_halt(struct xhci_hcd *xhci);
1847int xhci_start(struct xhci_hcd *xhci);
1848int xhci_reset(struct xhci_hcd *xhci, u64 timeout_us);
1849int xhci_run(struct usb_hcd *hcd);
1850int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
1851void xhci_shutdown(struct usb_hcd *hcd);
1852void xhci_stop(struct usb_hcd *hcd);
1853void xhci_init_driver(struct hc_driver *drv,
1854 const struct xhci_driver_overrides *over);
1855int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1856 struct usb_host_endpoint *ep);
1857int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1858 struct usb_host_endpoint *ep);
1859int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1860void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
1861int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
1862 struct usb_tt *tt, gfp_t mem_flags);
1863int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
1864int xhci_ext_cap_init(struct xhci_hcd *xhci);
1865
1866int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
1867int xhci_resume(struct xhci_hcd *xhci, pm_message_t msg);
1868
1869irqreturn_t xhci_irq(struct usb_hcd *hcd);
1870irqreturn_t xhci_msi_irq(int irq, void *hcd);
1871int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
1872int xhci_alloc_tt_info(struct xhci_hcd *xhci,
1873 struct xhci_virt_device *virt_dev,
1874 struct usb_device *hdev,
1875 struct usb_tt *tt, gfp_t mem_flags);
1876
1877/* xHCI ring, segment, TRB, and TD functions */
1878dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
1879struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1880 struct xhci_segment *start_seg, union xhci_trb *start_trb,
1881 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
1882int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
1883void xhci_ring_cmd_db(struct xhci_hcd *xhci);
1884int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
1885 u32 trb_type, u32 slot_id);
1886int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1887 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
1888int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
1889 u32 field1, u32 field2, u32 field3, u32 field4);
1890int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
1891 int slot_id, unsigned int ep_index, int suspend);
1892int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1893 int slot_id, unsigned int ep_index);
1894int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1895 int slot_id, unsigned int ep_index);
1896int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
1897 int slot_id, unsigned int ep_index);
1898int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
1899 struct urb *urb, int slot_id, unsigned int ep_index);
1900int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
1901 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
1902 bool command_must_succeed);
1903int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
1904 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
1905int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
1906 int slot_id, unsigned int ep_index,
1907 enum xhci_ep_reset_type reset_type);
1908int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
1909 u32 slot_id);
1910void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
1911 unsigned int ep_index, unsigned int stream_id,
1912 struct xhci_td *td);
1913void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
1914void xhci_handle_command_timeout(struct work_struct *work);
1915
1916void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
1917 unsigned int ep_index, unsigned int stream_id);
1918void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
1919 unsigned int slot_id,
1920 unsigned int ep_index);
1921void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
1922void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
1923unsigned int count_trbs(u64 addr, u64 len);
1924
1925/* xHCI roothub code */
1926void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
1927 u32 link_state);
1928void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
1929 u32 port_bit);
1930int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
1931 char *buf, u16 wLength);
1932int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
1933int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
1934struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
1935
1936void xhci_hc_died(struct xhci_hcd *xhci);
1937
1938#ifdef CONFIG_PM
1939int xhci_bus_suspend(struct usb_hcd *hcd);
1940int xhci_bus_resume(struct usb_hcd *hcd);
1941unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
1942#else
1943#define xhci_bus_suspend NULL
1944#define xhci_bus_resume NULL
1945#define xhci_get_resuming_ports NULL
1946#endif /* CONFIG_PM */
1947
1948u32 xhci_port_state_to_neutral(u32 state);
1949void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
1950
1951/* xHCI contexts */
1952struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
1953struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
1954struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
1955
1956struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
1957 unsigned int slot_id, unsigned int ep_index,
1958 unsigned int stream_id);
1959
1960static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
1961 struct urb *urb)
1962{
1963 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
1964 xhci_get_endpoint_index(&urb->ep->desc),
1965 urb->stream_id);
1966}
1967
1968/*
1969 * TODO: As per spec Isochronous IDT transmissions are supported. We bypass
1970 * them anyways as we where unable to find a device that matches the
1971 * constraints.
1972 */
1973static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
1974{
1975 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
1976 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
1977 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
1978 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
1979 !urb->num_sgs)
1980 return true;
1981
1982 return false;
1983}
1984
1985static inline char *xhci_slot_state_string(u32 state)
1986{
1987 switch (state) {
1988 case SLOT_STATE_ENABLED:
1989 return "enabled/disabled";
1990 case SLOT_STATE_DEFAULT:
1991 return "default";
1992 case SLOT_STATE_ADDRESSED:
1993 return "addressed";
1994 case SLOT_STATE_CONFIGURED:
1995 return "configured";
1996 default:
1997 return "reserved";
1998 }
1999}
2000
2001static inline const char *xhci_decode_trb(char *str, size_t size,
2002 u32 field0, u32 field1, u32 field2, u32 field3)
2003{
2004 int type = TRB_FIELD_TO_TYPE(field3);
2005
2006 switch (type) {
2007 case TRB_LINK:
2008 snprintf(str, size,
2009 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2010 field1, field0, GET_INTR_TARGET(field2),
2011 xhci_trb_type_string(type),
2012 field3 & TRB_IOC ? 'I' : 'i',
2013 field3 & TRB_CHAIN ? 'C' : 'c',
2014 field3 & TRB_TC ? 'T' : 't',
2015 field3 & TRB_CYCLE ? 'C' : 'c');
2016 break;
2017 case TRB_TRANSFER:
2018 case TRB_COMPLETION:
2019 case TRB_PORT_STATUS:
2020 case TRB_BANDWIDTH_EVENT:
2021 case TRB_DOORBELL:
2022 case TRB_HC_EVENT:
2023 case TRB_DEV_NOTE:
2024 case TRB_MFINDEX_WRAP:
2025 snprintf(str, size,
2026 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2027 field1, field0,
2028 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2029 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2030 /* Macro decrements 1, maybe it shouldn't?!? */
2031 TRB_TO_EP_INDEX(field3) + 1,
2032 xhci_trb_type_string(type),
2033 field3 & EVENT_DATA ? 'E' : 'e',
2034 field3 & TRB_CYCLE ? 'C' : 'c');
2035
2036 break;
2037 case TRB_SETUP:
2038 snprintf(str, size,
2039 "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2040 field0 & 0xff,
2041 (field0 & 0xff00) >> 8,
2042 (field0 & 0xff000000) >> 24,
2043 (field0 & 0xff0000) >> 16,
2044 (field1 & 0xff00) >> 8,
2045 field1 & 0xff,
2046 (field1 & 0xff000000) >> 16 |
2047 (field1 & 0xff0000) >> 16,
2048 TRB_LEN(field2), GET_TD_SIZE(field2),
2049 GET_INTR_TARGET(field2),
2050 xhci_trb_type_string(type),
2051 field3 & TRB_IDT ? 'I' : 'i',
2052 field3 & TRB_IOC ? 'I' : 'i',
2053 field3 & TRB_CYCLE ? 'C' : 'c');
2054 break;
2055 case TRB_DATA:
2056 snprintf(str, size,
2057 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2058 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2059 GET_INTR_TARGET(field2),
2060 xhci_trb_type_string(type),
2061 field3 & TRB_IDT ? 'I' : 'i',
2062 field3 & TRB_IOC ? 'I' : 'i',
2063 field3 & TRB_CHAIN ? 'C' : 'c',
2064 field3 & TRB_NO_SNOOP ? 'S' : 's',
2065 field3 & TRB_ISP ? 'I' : 'i',
2066 field3 & TRB_ENT ? 'E' : 'e',
2067 field3 & TRB_CYCLE ? 'C' : 'c');
2068 break;
2069 case TRB_STATUS:
2070 snprintf(str, size,
2071 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2072 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2073 GET_INTR_TARGET(field2),
2074 xhci_trb_type_string(type),
2075 field3 & TRB_IOC ? 'I' : 'i',
2076 field3 & TRB_CHAIN ? 'C' : 'c',
2077 field3 & TRB_ENT ? 'E' : 'e',
2078 field3 & TRB_CYCLE ? 'C' : 'c');
2079 break;
2080 case TRB_NORMAL:
2081 case TRB_ISOC:
2082 case TRB_EVENT_DATA:
2083 case TRB_TR_NOOP:
2084 snprintf(str, size,
2085 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2086 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2087 GET_INTR_TARGET(field2),
2088 xhci_trb_type_string(type),
2089 field3 & TRB_BEI ? 'B' : 'b',
2090 field3 & TRB_IDT ? 'I' : 'i',
2091 field3 & TRB_IOC ? 'I' : 'i',
2092 field3 & TRB_CHAIN ? 'C' : 'c',
2093 field3 & TRB_NO_SNOOP ? 'S' : 's',
2094 field3 & TRB_ISP ? 'I' : 'i',
2095 field3 & TRB_ENT ? 'E' : 'e',
2096 field3 & TRB_CYCLE ? 'C' : 'c');
2097 break;
2098
2099 case TRB_CMD_NOOP:
2100 case TRB_ENABLE_SLOT:
2101 snprintf(str, size,
2102 "%s: flags %c",
2103 xhci_trb_type_string(type),
2104 field3 & TRB_CYCLE ? 'C' : 'c');
2105 break;
2106 case TRB_DISABLE_SLOT:
2107 case TRB_NEG_BANDWIDTH:
2108 snprintf(str, size,
2109 "%s: slot %d flags %c",
2110 xhci_trb_type_string(type),
2111 TRB_TO_SLOT_ID(field3),
2112 field3 & TRB_CYCLE ? 'C' : 'c');
2113 break;
2114 case TRB_ADDR_DEV:
2115 snprintf(str, size,
2116 "%s: ctx %08x%08x slot %d flags %c:%c",
2117 xhci_trb_type_string(type),
2118 field1, field0,
2119 TRB_TO_SLOT_ID(field3),
2120 field3 & TRB_BSR ? 'B' : 'b',
2121 field3 & TRB_CYCLE ? 'C' : 'c');
2122 break;
2123 case TRB_CONFIG_EP:
2124 snprintf(str, size,
2125 "%s: ctx %08x%08x slot %d flags %c:%c",
2126 xhci_trb_type_string(type),
2127 field1, field0,
2128 TRB_TO_SLOT_ID(field3),
2129 field3 & TRB_DC ? 'D' : 'd',
2130 field3 & TRB_CYCLE ? 'C' : 'c');
2131 break;
2132 case TRB_EVAL_CONTEXT:
2133 snprintf(str, size,
2134 "%s: ctx %08x%08x slot %d flags %c",
2135 xhci_trb_type_string(type),
2136 field1, field0,
2137 TRB_TO_SLOT_ID(field3),
2138 field3 & TRB_CYCLE ? 'C' : 'c');
2139 break;
2140 case TRB_RESET_EP:
2141 snprintf(str, size,
2142 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2143 xhci_trb_type_string(type),
2144 field1, field0,
2145 TRB_TO_SLOT_ID(field3),
2146 /* Macro decrements 1, maybe it shouldn't?!? */
2147 TRB_TO_EP_INDEX(field3) + 1,
2148 field3 & TRB_TSP ? 'T' : 't',
2149 field3 & TRB_CYCLE ? 'C' : 'c');
2150 break;
2151 case TRB_STOP_RING:
2152 snprintf(str, size,
2153 "%s: slot %d sp %d ep %d flags %c",
2154 xhci_trb_type_string(type),
2155 TRB_TO_SLOT_ID(field3),
2156 TRB_TO_SUSPEND_PORT(field3),
2157 /* Macro decrements 1, maybe it shouldn't?!? */
2158 TRB_TO_EP_INDEX(field3) + 1,
2159 field3 & TRB_CYCLE ? 'C' : 'c');
2160 break;
2161 case TRB_SET_DEQ:
2162 snprintf(str, size,
2163 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2164 xhci_trb_type_string(type),
2165 field1, field0,
2166 TRB_TO_STREAM_ID(field2),
2167 TRB_TO_SLOT_ID(field3),
2168 /* Macro decrements 1, maybe it shouldn't?!? */
2169 TRB_TO_EP_INDEX(field3) + 1,
2170 field3 & TRB_CYCLE ? 'C' : 'c');
2171 break;
2172 case TRB_RESET_DEV:
2173 snprintf(str, size,
2174 "%s: slot %d flags %c",
2175 xhci_trb_type_string(type),
2176 TRB_TO_SLOT_ID(field3),
2177 field3 & TRB_CYCLE ? 'C' : 'c');
2178 break;
2179 case TRB_FORCE_EVENT:
2180 snprintf(str, size,
2181 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2182 xhci_trb_type_string(type),
2183 field1, field0,
2184 TRB_TO_VF_INTR_TARGET(field2),
2185 TRB_TO_VF_ID(field3),
2186 field3 & TRB_CYCLE ? 'C' : 'c');
2187 break;
2188 case TRB_SET_LT:
2189 snprintf(str, size,
2190 "%s: belt %d flags %c",
2191 xhci_trb_type_string(type),
2192 TRB_TO_BELT(field3),
2193 field3 & TRB_CYCLE ? 'C' : 'c');
2194 break;
2195 case TRB_GET_BW:
2196 snprintf(str, size,
2197 "%s: ctx %08x%08x slot %d speed %d flags %c",
2198 xhci_trb_type_string(type),
2199 field1, field0,
2200 TRB_TO_SLOT_ID(field3),
2201 TRB_TO_DEV_SPEED(field3),
2202 field3 & TRB_CYCLE ? 'C' : 'c');
2203 break;
2204 case TRB_FORCE_HEADER:
2205 snprintf(str, size,
2206 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2207 xhci_trb_type_string(type),
2208 field2, field1, field0 & 0xffffffe0,
2209 TRB_TO_PACKET_TYPE(field0),
2210 TRB_TO_ROOTHUB_PORT(field3),
2211 field3 & TRB_CYCLE ? 'C' : 'c');
2212 break;
2213 default:
2214 snprintf(str, size,
2215 "type '%s' -> raw %08x %08x %08x %08x",
2216 xhci_trb_type_string(type),
2217 field0, field1, field2, field3);
2218 }
2219
2220 return str;
2221}
2222
2223static inline const char *xhci_decode_ctrl_ctx(char *str,
2224 unsigned long drop, unsigned long add)
2225{
2226 unsigned int bit;
2227 int ret = 0;
2228
2229 str[0] = '\0';
2230
2231 if (drop) {
2232 ret = sprintf(str, "Drop:");
2233 for_each_set_bit(bit, &drop, 32)
2234 ret += sprintf(str + ret, " %d%s",
2235 bit / 2,
2236 bit % 2 ? "in":"out");
2237 ret += sprintf(str + ret, ", ");
2238 }
2239
2240 if (add) {
2241 ret += sprintf(str + ret, "Add:%s%s",
2242 (add & SLOT_FLAG) ? " slot":"",
2243 (add & EP0_FLAG) ? " ep0":"");
2244 add &= ~(SLOT_FLAG | EP0_FLAG);
2245 for_each_set_bit(bit, &add, 32)
2246 ret += sprintf(str + ret, " %d%s",
2247 bit / 2,
2248 bit % 2 ? "in":"out");
2249 }
2250 return str;
2251}
2252
2253static inline const char *xhci_decode_slot_context(char *str,
2254 u32 info, u32 info2, u32 tt_info, u32 state)
2255{
2256 u32 speed;
2257 u32 hub;
2258 u32 mtt;
2259 int ret = 0;
2260
2261 speed = info & DEV_SPEED;
2262 hub = info & DEV_HUB;
2263 mtt = info & DEV_MTT;
2264
2265 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2266 info & ROUTE_STRING_MASK,
2267 ({ char *s;
2268 switch (speed) {
2269 case SLOT_SPEED_FS:
2270 s = "full-speed";
2271 break;
2272 case SLOT_SPEED_LS:
2273 s = "low-speed";
2274 break;
2275 case SLOT_SPEED_HS:
2276 s = "high-speed";
2277 break;
2278 case SLOT_SPEED_SS:
2279 s = "super-speed";
2280 break;
2281 case SLOT_SPEED_SSP:
2282 s = "super-speed plus";
2283 break;
2284 default:
2285 s = "UNKNOWN speed";
2286 } s; }),
2287 mtt ? " multi-TT" : "",
2288 hub ? " Hub" : "",
2289 (info & LAST_CTX_MASK) >> 27,
2290 info2 & MAX_EXIT,
2291 DEVINFO_TO_ROOT_HUB_PORT(info2),
2292 DEVINFO_TO_MAX_PORTS(info2));
2293
2294 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2295 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2296 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2297 state & DEV_ADDR_MASK,
2298 xhci_slot_state_string(GET_SLOT_STATE(state)));
2299
2300 return str;
2301}
2302
2303
2304static inline const char *xhci_portsc_link_state_string(u32 portsc)
2305{
2306 switch (portsc & PORT_PLS_MASK) {
2307 case XDEV_U0:
2308 return "U0";
2309 case XDEV_U1:
2310 return "U1";
2311 case XDEV_U2:
2312 return "U2";
2313 case XDEV_U3:
2314 return "U3";
2315 case XDEV_DISABLED:
2316 return "Disabled";
2317 case XDEV_RXDETECT:
2318 return "RxDetect";
2319 case XDEV_INACTIVE:
2320 return "Inactive";
2321 case XDEV_POLLING:
2322 return "Polling";
2323 case XDEV_RECOVERY:
2324 return "Recovery";
2325 case XDEV_HOT_RESET:
2326 return "Hot Reset";
2327 case XDEV_COMP_MODE:
2328 return "Compliance mode";
2329 case XDEV_TEST_MODE:
2330 return "Test mode";
2331 case XDEV_RESUME:
2332 return "Resume";
2333 default:
2334 break;
2335 }
2336 return "Unknown";
2337}
2338
2339static inline const char *xhci_decode_portsc(char *str, u32 portsc)
2340{
2341 int ret;
2342
2343 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2344 portsc & PORT_POWER ? "Powered" : "Powered-off",
2345 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2346 portsc & PORT_PE ? "Enabled" : "Disabled",
2347 xhci_portsc_link_state_string(portsc),
2348 DEV_PORT_SPEED(portsc));
2349
2350 if (portsc & PORT_OC)
2351 ret += sprintf(str + ret, "OverCurrent ");
2352 if (portsc & PORT_RESET)
2353 ret += sprintf(str + ret, "In-Reset ");
2354
2355 ret += sprintf(str + ret, "Change: ");
2356 if (portsc & PORT_CSC)
2357 ret += sprintf(str + ret, "CSC ");
2358 if (portsc & PORT_PEC)
2359 ret += sprintf(str + ret, "PEC ");
2360 if (portsc & PORT_WRC)
2361 ret += sprintf(str + ret, "WRC ");
2362 if (portsc & PORT_OCC)
2363 ret += sprintf(str + ret, "OCC ");
2364 if (portsc & PORT_RC)
2365 ret += sprintf(str + ret, "PRC ");
2366 if (portsc & PORT_PLC)
2367 ret += sprintf(str + ret, "PLC ");
2368 if (portsc & PORT_CEC)
2369 ret += sprintf(str + ret, "CEC ");
2370 if (portsc & PORT_CAS)
2371 ret += sprintf(str + ret, "CAS ");
2372
2373 ret += sprintf(str + ret, "Wake: ");
2374 if (portsc & PORT_WKCONN_E)
2375 ret += sprintf(str + ret, "WCE ");
2376 if (portsc & PORT_WKDISC_E)
2377 ret += sprintf(str + ret, "WDE ");
2378 if (portsc & PORT_WKOC_E)
2379 ret += sprintf(str + ret, "WOE ");
2380
2381 return str;
2382}
2383
2384static inline const char *xhci_decode_usbsts(char *str, u32 usbsts)
2385{
2386 int ret = 0;
2387
2388 ret = sprintf(str, " 0x%08x", usbsts);
2389
2390 if (usbsts == ~(u32)0)
2391 return str;
2392
2393 if (usbsts & STS_HALT)
2394 ret += sprintf(str + ret, " HCHalted");
2395 if (usbsts & STS_FATAL)
2396 ret += sprintf(str + ret, " HSE");
2397 if (usbsts & STS_EINT)
2398 ret += sprintf(str + ret, " EINT");
2399 if (usbsts & STS_PORT)
2400 ret += sprintf(str + ret, " PCD");
2401 if (usbsts & STS_SAVE)
2402 ret += sprintf(str + ret, " SSS");
2403 if (usbsts & STS_RESTORE)
2404 ret += sprintf(str + ret, " RSS");
2405 if (usbsts & STS_SRE)
2406 ret += sprintf(str + ret, " SRE");
2407 if (usbsts & STS_CNR)
2408 ret += sprintf(str + ret, " CNR");
2409 if (usbsts & STS_HCE)
2410 ret += sprintf(str + ret, " HCE");
2411
2412 return str;
2413}
2414
2415static inline const char *xhci_decode_doorbell(char *str, u32 slot, u32 doorbell)
2416{
2417 u8 ep;
2418 u16 stream;
2419 int ret;
2420
2421 ep = (doorbell & 0xff);
2422 stream = doorbell >> 16;
2423
2424 if (slot == 0) {
2425 sprintf(str, "Command Ring %d", doorbell);
2426 return str;
2427 }
2428 ret = sprintf(str, "Slot %d ", slot);
2429 if (ep > 0 && ep < 32)
2430 ret = sprintf(str + ret, "ep%d%s",
2431 ep / 2,
2432 ep % 2 ? "in" : "out");
2433 else if (ep == 0 || ep < 248)
2434 ret = sprintf(str + ret, "Reserved %d", ep);
2435 else
2436 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2437 if (stream)
2438 ret = sprintf(str + ret, " Stream %d", stream);
2439
2440 return str;
2441}
2442
2443static inline const char *xhci_ep_state_string(u8 state)
2444{
2445 switch (state) {
2446 case EP_STATE_DISABLED:
2447 return "disabled";
2448 case EP_STATE_RUNNING:
2449 return "running";
2450 case EP_STATE_HALTED:
2451 return "halted";
2452 case EP_STATE_STOPPED:
2453 return "stopped";
2454 case EP_STATE_ERROR:
2455 return "error";
2456 default:
2457 return "INVALID";
2458 }
2459}
2460
2461static inline const char *xhci_ep_type_string(u8 type)
2462{
2463 switch (type) {
2464 case ISOC_OUT_EP:
2465 return "Isoc OUT";
2466 case BULK_OUT_EP:
2467 return "Bulk OUT";
2468 case INT_OUT_EP:
2469 return "Int OUT";
2470 case CTRL_EP:
2471 return "Ctrl";
2472 case ISOC_IN_EP:
2473 return "Isoc IN";
2474 case BULK_IN_EP:
2475 return "Bulk IN";
2476 case INT_IN_EP:
2477 return "Int IN";
2478 default:
2479 return "INVALID";
2480 }
2481}
2482
2483static inline const char *xhci_decode_ep_context(char *str, u32 info,
2484 u32 info2, u64 deq, u32 tx_info)
2485{
2486 int ret;
2487
2488 u32 esit;
2489 u16 maxp;
2490 u16 avg;
2491
2492 u8 max_pstr;
2493 u8 ep_state;
2494 u8 interval;
2495 u8 ep_type;
2496 u8 burst;
2497 u8 cerr;
2498 u8 mult;
2499
2500 bool lsa;
2501 bool hid;
2502
2503 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2504 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2505
2506 ep_state = info & EP_STATE_MASK;
2507 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2508 interval = CTX_TO_EP_INTERVAL(info);
2509 mult = CTX_TO_EP_MULT(info) + 1;
2510 lsa = !!(info & EP_HAS_LSA);
2511
2512 cerr = (info2 & (3 << 1)) >> 1;
2513 ep_type = CTX_TO_EP_TYPE(info2);
2514 hid = !!(info2 & (1 << 7));
2515 burst = CTX_TO_MAX_BURST(info2);
2516 maxp = MAX_PACKET_DECODED(info2);
2517
2518 avg = EP_AVG_TRB_LENGTH(tx_info);
2519
2520 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2521 xhci_ep_state_string(ep_state), mult,
2522 max_pstr, lsa ? "LSA " : "");
2523
2524 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2525 (1 << interval) * 125, esit, cerr);
2526
2527 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2528 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2529 burst, maxp, deq);
2530
2531 ret += sprintf(str + ret, "avg trb len %d", avg);
2532
2533 return str;
2534}
2535
2536#endif /* __LINUX_XHCI_HCD_H */