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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Analog Devices Industrial Ethernet PHYs
4 *
5 * Copyright 2019 Analog Devices Inc.
6 */
7#include <linux/kernel.h>
8#include <linux/bitfield.h>
9#include <linux/delay.h>
10#include <linux/errno.h>
11#include <linux/ethtool_netlink.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/mii.h>
15#include <linux/phy.h>
16#include <linux/property.h>
17
18#define PHY_ID_ADIN1200 0x0283bc20
19#define PHY_ID_ADIN1300 0x0283bc30
20
21#define ADIN1300_MII_EXT_REG_PTR 0x0010
22#define ADIN1300_MII_EXT_REG_DATA 0x0011
23
24#define ADIN1300_PHY_CTRL1 0x0012
25#define ADIN1300_AUTO_MDI_EN BIT(10)
26#define ADIN1300_MAN_MDIX_EN BIT(9)
27#define ADIN1300_DIAG_CLK_EN BIT(2)
28
29#define ADIN1300_RX_ERR_CNT 0x0014
30
31#define ADIN1300_PHY_CTRL_STATUS2 0x0015
32#define ADIN1300_NRG_PD_EN BIT(3)
33#define ADIN1300_NRG_PD_TX_EN BIT(2)
34#define ADIN1300_NRG_PD_STATUS BIT(1)
35
36#define ADIN1300_PHY_CTRL2 0x0016
37#define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
38#define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
39#define ADIN1300_GROUP_MDIO_EN BIT(6)
40#define ADIN1300_DOWNSPEEDS_EN \
41 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
42
43#define ADIN1300_PHY_CTRL3 0x0017
44#define ADIN1300_LINKING_EN BIT(13)
45#define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10)
46
47#define ADIN1300_INT_MASK_REG 0x0018
48#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
49#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
50#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
51#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
52#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
53#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
54#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
55#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
56#define ADIN1300_INT_HW_IRQ_EN BIT(0)
57#define ADIN1300_INT_MASK_EN \
58 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN)
59#define ADIN1300_INT_STATUS_REG 0x0019
60
61#define ADIN1300_PHY_STATUS1 0x001a
62#define ADIN1300_PAIR_01_SWAP BIT(11)
63
64/* EEE register addresses, accessible via Clause 22 access using
65 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA.
66 * The bit-fields are the same as specified by IEEE for EEE.
67 */
68#define ADIN1300_EEE_CAP_REG 0x8000
69#define ADIN1300_EEE_ADV_REG 0x8001
70#define ADIN1300_EEE_LPABLE_REG 0x8002
71
72#define ADIN1300_FLD_EN_REG 0x8E27
73#define ADIN1300_FLD_PCS_ERR_100_EN BIT(7)
74#define ADIN1300_FLD_PCS_ERR_1000_EN BIT(6)
75#define ADIN1300_FLD_SLCR_OUT_STUCK_100_EN BIT(5)
76#define ADIN1300_FLD_SLCR_OUT_STUCK_1000_EN BIT(4)
77#define ADIN1300_FLD_SLCR_IN_ZDET_100_EN BIT(3)
78#define ADIN1300_FLD_SLCR_IN_ZDET_1000_EN BIT(2)
79#define ADIN1300_FLD_SLCR_IN_INVLD_100_EN BIT(1)
80#define ADIN1300_FLD_SLCR_IN_INVLD_1000_EN BIT(0)
81/* These bits are the ones which are enabled by default. */
82#define ADIN1300_FLD_EN_ON \
83 (ADIN1300_FLD_SLCR_OUT_STUCK_100_EN | \
84 ADIN1300_FLD_SLCR_OUT_STUCK_1000_EN | \
85 ADIN1300_FLD_SLCR_IN_ZDET_100_EN | \
86 ADIN1300_FLD_SLCR_IN_ZDET_1000_EN | \
87 ADIN1300_FLD_SLCR_IN_INVLD_1000_EN)
88
89#define ADIN1300_CLOCK_STOP_REG 0x9400
90#define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
91
92#define ADIN1300_CDIAG_RUN 0xba1b
93#define ADIN1300_CDIAG_RUN_EN BIT(0)
94
95/*
96 * The XSIM3/2/1 and XSHRT3/2/1 are actually relative.
97 * For CDIAG_DTLD_RSLTS(0) it's ADIN1300_CDIAG_RSLT_XSIM3/2/1
98 * For CDIAG_DTLD_RSLTS(1) it's ADIN1300_CDIAG_RSLT_XSIM3/2/0
99 * For CDIAG_DTLD_RSLTS(2) it's ADIN1300_CDIAG_RSLT_XSIM3/1/0
100 * For CDIAG_DTLD_RSLTS(3) it's ADIN1300_CDIAG_RSLT_XSIM2/1/0
101 */
102#define ADIN1300_CDIAG_DTLD_RSLTS(x) (0xba1d + (x))
103#define ADIN1300_CDIAG_RSLT_BUSY BIT(10)
104#define ADIN1300_CDIAG_RSLT_XSIM3 BIT(9)
105#define ADIN1300_CDIAG_RSLT_XSIM2 BIT(8)
106#define ADIN1300_CDIAG_RSLT_XSIM1 BIT(7)
107#define ADIN1300_CDIAG_RSLT_SIM BIT(6)
108#define ADIN1300_CDIAG_RSLT_XSHRT3 BIT(5)
109#define ADIN1300_CDIAG_RSLT_XSHRT2 BIT(4)
110#define ADIN1300_CDIAG_RSLT_XSHRT1 BIT(3)
111#define ADIN1300_CDIAG_RSLT_SHRT BIT(2)
112#define ADIN1300_CDIAG_RSLT_OPEN BIT(1)
113#define ADIN1300_CDIAG_RSLT_GOOD BIT(0)
114
115#define ADIN1300_CDIAG_FLT_DIST(x) (0xba21 + (x))
116
117#define ADIN1300_GE_SOFT_RESET_REG 0xff0c
118#define ADIN1300_GE_SOFT_RESET BIT(0)
119
120#define ADIN1300_GE_CLK_CFG_REG 0xff1f
121#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0)
122#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5)
123#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4)
124#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3)
125#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2)
126#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1)
127#define ADIN1300_GE_CLK_CFG_25 BIT(0)
128
129#define ADIN1300_GE_RGMII_CFG_REG 0xff23
130#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
131#define ADIN1300_GE_RGMII_RX_SEL(x) \
132 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
133#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
134#define ADIN1300_GE_RGMII_GTX_SEL(x) \
135 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
136#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
137#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
138#define ADIN1300_GE_RGMII_EN BIT(0)
139
140/* RGMII internal delay settings for rx and tx for ADIN1300 */
141#define ADIN1300_RGMII_1_60_NS 0x0001
142#define ADIN1300_RGMII_1_80_NS 0x0002
143#define ADIN1300_RGMII_2_00_NS 0x0000
144#define ADIN1300_RGMII_2_20_NS 0x0006
145#define ADIN1300_RGMII_2_40_NS 0x0007
146
147#define ADIN1300_GE_RMII_CFG_REG 0xff24
148#define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)
149#define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \
150 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
151#define ADIN1300_GE_RMII_EN BIT(0)
152
153/* RMII fifo depth values */
154#define ADIN1300_RMII_4_BITS 0x0000
155#define ADIN1300_RMII_8_BITS 0x0001
156#define ADIN1300_RMII_12_BITS 0x0002
157#define ADIN1300_RMII_16_BITS 0x0003
158#define ADIN1300_RMII_20_BITS 0x0004
159#define ADIN1300_RMII_24_BITS 0x0005
160
161/**
162 * struct adin_cfg_reg_map - map a config value to aregister value
163 * @cfg: value in device configuration
164 * @reg: value in the register
165 */
166struct adin_cfg_reg_map {
167 int cfg;
168 int reg;
169};
170
171static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
172 { 1600, ADIN1300_RGMII_1_60_NS },
173 { 1800, ADIN1300_RGMII_1_80_NS },
174 { 2000, ADIN1300_RGMII_2_00_NS },
175 { 2200, ADIN1300_RGMII_2_20_NS },
176 { 2400, ADIN1300_RGMII_2_40_NS },
177 { },
178};
179
180static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = {
181 { 4, ADIN1300_RMII_4_BITS },
182 { 8, ADIN1300_RMII_8_BITS },
183 { 12, ADIN1300_RMII_12_BITS },
184 { 16, ADIN1300_RMII_16_BITS },
185 { 20, ADIN1300_RMII_20_BITS },
186 { 24, ADIN1300_RMII_24_BITS },
187 { },
188};
189
190/**
191 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22
192 * @devad: device address used in Clause 45 access
193 * @cl45_regnum: register address defined by Clause 45
194 * @adin_regnum: equivalent register address accessible via Clause 22
195 */
196struct adin_clause45_mmd_map {
197 int devad;
198 u16 cl45_regnum;
199 u16 adin_regnum;
200};
201
202static const struct adin_clause45_mmd_map adin_clause45_mmd_map[] = {
203 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
204 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG },
205 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG },
206 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
207 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
208};
209
210struct adin_hw_stat {
211 const char *string;
212 u16 reg1;
213 u16 reg2;
214};
215
216static const struct adin_hw_stat adin_hw_stats[] = {
217 { "total_frames_checked_count", 0x940A, 0x940B }, /* hi + lo */
218 { "length_error_frames_count", 0x940C },
219 { "alignment_error_frames_count", 0x940D },
220 { "symbol_error_count", 0x940E },
221 { "oversized_frames_count", 0x940F },
222 { "undersized_frames_count", 0x9410 },
223 { "odd_nibble_frames_count", 0x9411 },
224 { "odd_preamble_packet_count", 0x9412 },
225 { "dribble_bits_frames_count", 0x9413 },
226 { "false_carrier_events_count", 0x9414 },
227};
228
229/**
230 * struct adin_priv - ADIN PHY driver private data
231 * @stats: statistic counters for the PHY
232 */
233struct adin_priv {
234 u64 stats[ARRAY_SIZE(adin_hw_stats)];
235};
236
237static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
238{
239 size_t i;
240
241 for (i = 0; tbl[i].cfg; i++) {
242 if (tbl[i].cfg == cfg)
243 return tbl[i].reg;
244 }
245
246 return -EINVAL;
247}
248
249static u32 adin_get_reg_value(struct phy_device *phydev,
250 const char *prop_name,
251 const struct adin_cfg_reg_map *tbl,
252 u32 dflt)
253{
254 struct device *dev = &phydev->mdio.dev;
255 u32 val;
256 int rc;
257
258 if (device_property_read_u32(dev, prop_name, &val))
259 return dflt;
260
261 rc = adin_lookup_reg_value(tbl, val);
262 if (rc < 0) {
263 phydev_warn(phydev,
264 "Unsupported value %u for %s using default (%u)\n",
265 val, prop_name, dflt);
266 return dflt;
267 }
268
269 return rc;
270}
271
272static int adin_config_rgmii_mode(struct phy_device *phydev)
273{
274 u32 val;
275 int reg;
276
277 if (!phy_interface_is_rgmii(phydev))
278 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
279 ADIN1300_GE_RGMII_CFG_REG,
280 ADIN1300_GE_RGMII_EN);
281
282 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
283 if (reg < 0)
284 return reg;
285
286 reg |= ADIN1300_GE_RGMII_EN;
287
288 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
289 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
290 reg |= ADIN1300_GE_RGMII_RXID_EN;
291
292 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
293 adin_rgmii_delays,
294 ADIN1300_RGMII_2_00_NS);
295 reg &= ~ADIN1300_GE_RGMII_RX_MSK;
296 reg |= ADIN1300_GE_RGMII_RX_SEL(val);
297 } else {
298 reg &= ~ADIN1300_GE_RGMII_RXID_EN;
299 }
300
301 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
302 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
303 reg |= ADIN1300_GE_RGMII_TXID_EN;
304
305 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
306 adin_rgmii_delays,
307 ADIN1300_RGMII_2_00_NS);
308 reg &= ~ADIN1300_GE_RGMII_GTX_MSK;
309 reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
310 } else {
311 reg &= ~ADIN1300_GE_RGMII_TXID_EN;
312 }
313
314 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
315 ADIN1300_GE_RGMII_CFG_REG, reg);
316}
317
318static int adin_config_rmii_mode(struct phy_device *phydev)
319{
320 u32 val;
321 int reg;
322
323 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
324 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
325 ADIN1300_GE_RMII_CFG_REG,
326 ADIN1300_GE_RMII_EN);
327
328 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
329 if (reg < 0)
330 return reg;
331
332 reg |= ADIN1300_GE_RMII_EN;
333
334 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
335 adin_rmii_fifo_depths,
336 ADIN1300_RMII_8_BITS);
337
338 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK;
339 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val);
340
341 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
342 ADIN1300_GE_RMII_CFG_REG, reg);
343}
344
345static int adin_get_downshift(struct phy_device *phydev, u8 *data)
346{
347 int val, cnt, enable;
348
349 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
350 if (val < 0)
351 return val;
352
353 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
354 if (cnt < 0)
355 return cnt;
356
357 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val);
358 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
359
360 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE;
361
362 return 0;
363}
364
365static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
366{
367 u16 val;
368 int rc;
369
370 if (cnt == DOWNSHIFT_DEV_DISABLE)
371 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
372 ADIN1300_DOWNSPEEDS_EN);
373
374 if (cnt > 7)
375 return -E2BIG;
376
377 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
378
379 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
380 ADIN1300_DOWNSPEED_RETRIES_MSK,
381 val);
382 if (rc < 0)
383 return rc;
384
385 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
386 ADIN1300_DOWNSPEEDS_EN);
387}
388
389static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)
390{
391 int val;
392
393 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);
394 if (val < 0)
395 return val;
396
397 if (ADIN1300_NRG_PD_EN & val) {
398 if (val & ADIN1300_NRG_PD_TX_EN)
399 /* default is 1 second */
400 *tx_interval = ETHTOOL_PHY_EDPD_DFLT_TX_MSECS;
401 else
402 *tx_interval = ETHTOOL_PHY_EDPD_NO_TX;
403 } else {
404 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
405 }
406
407 return 0;
408}
409
410static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
411{
412 u16 val;
413
414 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
415 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
416 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN));
417
418 val = ADIN1300_NRG_PD_EN;
419
420 switch (tx_interval) {
421 case 1000: /* 1 second */
422 fallthrough;
423 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
424 val |= ADIN1300_NRG_PD_TX_EN;
425 fallthrough;
426 case ETHTOOL_PHY_EDPD_NO_TX:
427 break;
428 default:
429 return -EINVAL;
430 }
431
432 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,
433 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN),
434 val);
435}
436
437static int adin_get_fast_down(struct phy_device *phydev, u8 *msecs)
438{
439 int reg;
440
441 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_FLD_EN_REG);
442 if (reg < 0)
443 return reg;
444
445 if (reg & ADIN1300_FLD_EN_ON)
446 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_ON;
447 else
448 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
449
450 return 0;
451}
452
453static int adin_set_fast_down(struct phy_device *phydev, const u8 *msecs)
454{
455 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_ON)
456 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
457 ADIN1300_FLD_EN_REG,
458 ADIN1300_FLD_EN_ON);
459
460 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
461 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
462 ADIN1300_FLD_EN_REG,
463 ADIN1300_FLD_EN_ON);
464
465 return -EINVAL;
466}
467
468static int adin_get_tunable(struct phy_device *phydev,
469 struct ethtool_tunable *tuna, void *data)
470{
471 switch (tuna->id) {
472 case ETHTOOL_PHY_DOWNSHIFT:
473 return adin_get_downshift(phydev, data);
474 case ETHTOOL_PHY_EDPD:
475 return adin_get_edpd(phydev, data);
476 case ETHTOOL_PHY_FAST_LINK_DOWN:
477 return adin_get_fast_down(phydev, data);
478 default:
479 return -EOPNOTSUPP;
480 }
481}
482
483static int adin_set_tunable(struct phy_device *phydev,
484 struct ethtool_tunable *tuna, const void *data)
485{
486 switch (tuna->id) {
487 case ETHTOOL_PHY_DOWNSHIFT:
488 return adin_set_downshift(phydev, *(const u8 *)data);
489 case ETHTOOL_PHY_EDPD:
490 return adin_set_edpd(phydev, *(const u16 *)data);
491 case ETHTOOL_PHY_FAST_LINK_DOWN:
492 return adin_set_fast_down(phydev, data);
493 default:
494 return -EOPNOTSUPP;
495 }
496}
497
498static int adin_config_clk_out(struct phy_device *phydev)
499{
500 struct device *dev = &phydev->mdio.dev;
501 const char *val = NULL;
502 u8 sel = 0;
503
504 device_property_read_string(dev, "adi,phy-output-clock", &val);
505 if (!val) {
506 /* property not present, do not enable GP_CLK pin */
507 } else if (strcmp(val, "25mhz-reference") == 0) {
508 sel |= ADIN1300_GE_CLK_CFG_25;
509 } else if (strcmp(val, "125mhz-free-running") == 0) {
510 sel |= ADIN1300_GE_CLK_CFG_FREE_125;
511 } else if (strcmp(val, "adaptive-free-running") == 0) {
512 sel |= ADIN1300_GE_CLK_CFG_HRT_FREE;
513 } else {
514 phydev_err(phydev, "invalid adi,phy-output-clock\n");
515 return -EINVAL;
516 }
517
518 if (device_property_read_bool(dev, "adi,phy-output-reference-clock"))
519 sel |= ADIN1300_GE_CLK_CFG_REF_EN;
520
521 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG,
522 ADIN1300_GE_CLK_CFG_MASK, sel);
523}
524
525static int adin_config_init(struct phy_device *phydev)
526{
527 int rc;
528
529 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
530
531 rc = adin_config_rgmii_mode(phydev);
532 if (rc < 0)
533 return rc;
534
535 rc = adin_config_rmii_mode(phydev);
536 if (rc < 0)
537 return rc;
538
539 rc = adin_set_downshift(phydev, 4);
540 if (rc < 0)
541 return rc;
542
543 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
544 if (rc < 0)
545 return rc;
546
547 rc = adin_config_clk_out(phydev);
548 if (rc < 0)
549 return rc;
550
551 phydev_dbg(phydev, "PHY is using mode '%s'\n",
552 phy_modes(phydev->interface));
553
554 return 0;
555}
556
557static int adin_phy_ack_intr(struct phy_device *phydev)
558{
559 /* Clear pending interrupts */
560 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
561
562 return rc < 0 ? rc : 0;
563}
564
565static int adin_phy_config_intr(struct phy_device *phydev)
566{
567 int err;
568
569 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
570 err = adin_phy_ack_intr(phydev);
571 if (err)
572 return err;
573
574 err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
575 ADIN1300_INT_MASK_EN);
576 } else {
577 err = phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
578 ADIN1300_INT_MASK_EN);
579 if (err)
580 return err;
581
582 err = adin_phy_ack_intr(phydev);
583 }
584
585 return err;
586}
587
588static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev)
589{
590 int irq_status;
591
592 irq_status = phy_read(phydev, ADIN1300_INT_STATUS_REG);
593 if (irq_status < 0) {
594 phy_error(phydev);
595 return IRQ_NONE;
596 }
597
598 if (!(irq_status & ADIN1300_INT_LINK_STAT_CHNG_EN))
599 return IRQ_NONE;
600
601 phy_trigger_machine(phydev);
602
603 return IRQ_HANDLED;
604}
605
606static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
607 u16 cl45_regnum)
608{
609 const struct adin_clause45_mmd_map *m;
610 int i;
611
612 if (devad == MDIO_MMD_VEND1)
613 return cl45_regnum;
614
615 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) {
616 m = &adin_clause45_mmd_map[i];
617 if (m->devad == devad && m->cl45_regnum == cl45_regnum)
618 return m->adin_regnum;
619 }
620
621 phydev_err(phydev,
622 "No translation available for devad: %d reg: %04x\n",
623 devad, cl45_regnum);
624
625 return -EINVAL;
626}
627
628static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
629{
630 struct mii_bus *bus = phydev->mdio.bus;
631 int phy_addr = phydev->mdio.addr;
632 int adin_regnum;
633 int err;
634
635 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
636 if (adin_regnum < 0)
637 return adin_regnum;
638
639 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
640 adin_regnum);
641 if (err)
642 return err;
643
644 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA);
645}
646
647static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
648 u16 val)
649{
650 struct mii_bus *bus = phydev->mdio.bus;
651 int phy_addr = phydev->mdio.addr;
652 int adin_regnum;
653 int err;
654
655 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
656 if (adin_regnum < 0)
657 return adin_regnum;
658
659 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
660 adin_regnum);
661 if (err)
662 return err;
663
664 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
665}
666
667static int adin_config_mdix(struct phy_device *phydev)
668{
669 bool auto_en, mdix_en;
670 int reg;
671
672 mdix_en = false;
673 auto_en = false;
674 switch (phydev->mdix_ctrl) {
675 case ETH_TP_MDI:
676 break;
677 case ETH_TP_MDI_X:
678 mdix_en = true;
679 break;
680 case ETH_TP_MDI_AUTO:
681 auto_en = true;
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
688 if (reg < 0)
689 return reg;
690
691 if (mdix_en)
692 reg |= ADIN1300_MAN_MDIX_EN;
693 else
694 reg &= ~ADIN1300_MAN_MDIX_EN;
695
696 if (auto_en)
697 reg |= ADIN1300_AUTO_MDI_EN;
698 else
699 reg &= ~ADIN1300_AUTO_MDI_EN;
700
701 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
702}
703
704static int adin_config_aneg(struct phy_device *phydev)
705{
706 int ret;
707
708 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
709 if (ret < 0)
710 return ret;
711
712 ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
713 if (ret < 0)
714 return ret;
715
716 ret = adin_config_mdix(phydev);
717 if (ret)
718 return ret;
719
720 return genphy_config_aneg(phydev);
721}
722
723static int adin_mdix_update(struct phy_device *phydev)
724{
725 bool auto_en, mdix_en;
726 bool swapped;
727 int reg;
728
729 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
730 if (reg < 0)
731 return reg;
732
733 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN);
734 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN);
735
736 /* If MDI/MDIX is forced, just read it from the control reg */
737 if (!auto_en) {
738 if (mdix_en)
739 phydev->mdix = ETH_TP_MDI_X;
740 else
741 phydev->mdix = ETH_TP_MDI;
742 return 0;
743 }
744
745 /**
746 * Otherwise, we need to deduce it from the PHY status2 reg.
747 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies
748 * a preference for MDIX when it is set.
749 */
750 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
751 if (reg < 0)
752 return reg;
753
754 swapped = !!(reg & ADIN1300_PAIR_01_SWAP);
755
756 if (mdix_en != swapped)
757 phydev->mdix = ETH_TP_MDI_X;
758 else
759 phydev->mdix = ETH_TP_MDI;
760
761 return 0;
762}
763
764static int adin_read_status(struct phy_device *phydev)
765{
766 int ret;
767
768 ret = adin_mdix_update(phydev);
769 if (ret < 0)
770 return ret;
771
772 return genphy_read_status(phydev);
773}
774
775static int adin_soft_reset(struct phy_device *phydev)
776{
777 int rc;
778
779 /* The reset bit is self-clearing, set it and wait */
780 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
781 ADIN1300_GE_SOFT_RESET_REG,
782 ADIN1300_GE_SOFT_RESET);
783 if (rc < 0)
784 return rc;
785
786 msleep(20);
787
788 /* If we get a read error something may be wrong */
789 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
790 ADIN1300_GE_SOFT_RESET_REG);
791
792 return rc < 0 ? rc : 0;
793}
794
795static int adin_get_sset_count(struct phy_device *phydev)
796{
797 return ARRAY_SIZE(adin_hw_stats);
798}
799
800static void adin_get_strings(struct phy_device *phydev, u8 *data)
801{
802 int i;
803
804 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
805 strscpy(&data[i * ETH_GSTRING_LEN],
806 adin_hw_stats[i].string, ETH_GSTRING_LEN);
807 }
808}
809
810static int adin_read_mmd_stat_regs(struct phy_device *phydev,
811 const struct adin_hw_stat *stat,
812 u32 *val)
813{
814 int ret;
815
816 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
817 if (ret < 0)
818 return ret;
819
820 *val = (ret & 0xffff);
821
822 if (stat->reg2 == 0)
823 return 0;
824
825 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
826 if (ret < 0)
827 return ret;
828
829 *val <<= 16;
830 *val |= (ret & 0xffff);
831
832 return 0;
833}
834
835static u64 adin_get_stat(struct phy_device *phydev, int i)
836{
837 const struct adin_hw_stat *stat = &adin_hw_stats[i];
838 struct adin_priv *priv = phydev->priv;
839 u32 val;
840 int ret;
841
842 if (stat->reg1 > 0x1f) {
843 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
844 if (ret < 0)
845 return (u64)(~0);
846 } else {
847 ret = phy_read(phydev, stat->reg1);
848 if (ret < 0)
849 return (u64)(~0);
850 val = (ret & 0xffff);
851 }
852
853 priv->stats[i] += val;
854
855 return priv->stats[i];
856}
857
858static void adin_get_stats(struct phy_device *phydev,
859 struct ethtool_stats *stats, u64 *data)
860{
861 int i, rc;
862
863 /* latch copies of all the frame-checker counters */
864 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
865 if (rc < 0)
866 return;
867
868 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
869 data[i] = adin_get_stat(phydev, i);
870}
871
872static int adin_probe(struct phy_device *phydev)
873{
874 struct device *dev = &phydev->mdio.dev;
875 struct adin_priv *priv;
876
877 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
878 if (!priv)
879 return -ENOMEM;
880
881 phydev->priv = priv;
882
883 return 0;
884}
885
886static int adin_cable_test_start(struct phy_device *phydev)
887{
888 int ret;
889
890 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
891 if (ret < 0)
892 return ret;
893
894 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
895 if (ret < 0)
896 return ret;
897
898 /* wait a bit for the clock to stabilize */
899 msleep(50);
900
901 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN,
902 ADIN1300_CDIAG_RUN_EN);
903}
904
905static int adin_cable_test_report_trans(int result)
906{
907 int mask;
908
909 if (result & ADIN1300_CDIAG_RSLT_GOOD)
910 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
911 if (result & ADIN1300_CDIAG_RSLT_OPEN)
912 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
913
914 /* short with other pairs */
915 mask = ADIN1300_CDIAG_RSLT_XSHRT3 |
916 ADIN1300_CDIAG_RSLT_XSHRT2 |
917 ADIN1300_CDIAG_RSLT_XSHRT1;
918 if (result & mask)
919 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
920
921 if (result & ADIN1300_CDIAG_RSLT_SHRT)
922 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
923
924 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
925}
926
927static int adin_cable_test_report_pair(struct phy_device *phydev,
928 unsigned int pair)
929{
930 int fault_rslt;
931 int ret;
932
933 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
934 ADIN1300_CDIAG_DTLD_RSLTS(pair));
935 if (ret < 0)
936 return ret;
937
938 fault_rslt = adin_cable_test_report_trans(ret);
939
940 ret = ethnl_cable_test_result(phydev, pair, fault_rslt);
941 if (ret < 0)
942 return ret;
943
944 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
945 ADIN1300_CDIAG_FLT_DIST(pair));
946 if (ret < 0)
947 return ret;
948
949 switch (fault_rslt) {
950 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN:
951 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:
952 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:
953 return ethnl_cable_test_fault_length(phydev, pair, ret * 100);
954 default:
955 return 0;
956 }
957}
958
959static int adin_cable_test_report(struct phy_device *phydev)
960{
961 unsigned int pair;
962 int ret;
963
964 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) {
965 ret = adin_cable_test_report_pair(phydev, pair);
966 if (ret < 0)
967 return ret;
968 }
969
970 return 0;
971}
972
973static int adin_cable_test_get_status(struct phy_device *phydev,
974 bool *finished)
975{
976 int ret;
977
978 *finished = false;
979
980 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN);
981 if (ret < 0)
982 return ret;
983
984 if (ret & ADIN1300_CDIAG_RUN_EN)
985 return 0;
986
987 *finished = true;
988
989 return adin_cable_test_report(phydev);
990}
991
992static struct phy_driver adin_driver[] = {
993 {
994 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
995 .name = "ADIN1200",
996 .flags = PHY_POLL_CABLE_TEST,
997 .probe = adin_probe,
998 .config_init = adin_config_init,
999 .soft_reset = adin_soft_reset,
1000 .config_aneg = adin_config_aneg,
1001 .read_status = adin_read_status,
1002 .get_tunable = adin_get_tunable,
1003 .set_tunable = adin_set_tunable,
1004 .config_intr = adin_phy_config_intr,
1005 .handle_interrupt = adin_phy_handle_interrupt,
1006 .get_sset_count = adin_get_sset_count,
1007 .get_strings = adin_get_strings,
1008 .get_stats = adin_get_stats,
1009 .resume = genphy_resume,
1010 .suspend = genphy_suspend,
1011 .read_mmd = adin_read_mmd,
1012 .write_mmd = adin_write_mmd,
1013 .cable_test_start = adin_cable_test_start,
1014 .cable_test_get_status = adin_cable_test_get_status,
1015 },
1016 {
1017 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
1018 .name = "ADIN1300",
1019 .flags = PHY_POLL_CABLE_TEST,
1020 .probe = adin_probe,
1021 .config_init = adin_config_init,
1022 .soft_reset = adin_soft_reset,
1023 .config_aneg = adin_config_aneg,
1024 .read_status = adin_read_status,
1025 .get_tunable = adin_get_tunable,
1026 .set_tunable = adin_set_tunable,
1027 .config_intr = adin_phy_config_intr,
1028 .handle_interrupt = adin_phy_handle_interrupt,
1029 .get_sset_count = adin_get_sset_count,
1030 .get_strings = adin_get_strings,
1031 .get_stats = adin_get_stats,
1032 .resume = genphy_resume,
1033 .suspend = genphy_suspend,
1034 .read_mmd = adin_read_mmd,
1035 .write_mmd = adin_write_mmd,
1036 .cable_test_start = adin_cable_test_start,
1037 .cable_test_get_status = adin_cable_test_get_status,
1038 },
1039};
1040
1041module_phy_driver(adin_driver);
1042
1043static struct mdio_device_id __maybe_unused adin_tbl[] = {
1044 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
1045 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
1046 { }
1047};
1048
1049MODULE_DEVICE_TABLE(mdio, adin_tbl);
1050MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
1051MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/**
3 * Driver for Analog Devices Industrial Ethernet PHYs
4 *
5 * Copyright 2019 Analog Devices Inc.
6 */
7#include <linux/kernel.h>
8#include <linux/bitfield.h>
9#include <linux/delay.h>
10#include <linux/errno.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/mii.h>
14#include <linux/phy.h>
15#include <linux/property.h>
16
17#define PHY_ID_ADIN1200 0x0283bc20
18#define PHY_ID_ADIN1300 0x0283bc30
19
20#define ADIN1300_MII_EXT_REG_PTR 0x0010
21#define ADIN1300_MII_EXT_REG_DATA 0x0011
22
23#define ADIN1300_PHY_CTRL1 0x0012
24#define ADIN1300_AUTO_MDI_EN BIT(10)
25#define ADIN1300_MAN_MDIX_EN BIT(9)
26
27#define ADIN1300_RX_ERR_CNT 0x0014
28
29#define ADIN1300_PHY_CTRL_STATUS2 0x0015
30#define ADIN1300_NRG_PD_EN BIT(3)
31#define ADIN1300_NRG_PD_TX_EN BIT(2)
32#define ADIN1300_NRG_PD_STATUS BIT(1)
33
34#define ADIN1300_PHY_CTRL2 0x0016
35#define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
36#define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
37#define ADIN1300_GROUP_MDIO_EN BIT(6)
38#define ADIN1300_DOWNSPEEDS_EN \
39 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
40
41#define ADIN1300_PHY_CTRL3 0x0017
42#define ADIN1300_LINKING_EN BIT(13)
43#define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10)
44
45#define ADIN1300_INT_MASK_REG 0x0018
46#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
47#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
48#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
49#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
50#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
51#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
52#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
53#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
54#define ADIN1300_INT_HW_IRQ_EN BIT(0)
55#define ADIN1300_INT_MASK_EN \
56 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN)
57#define ADIN1300_INT_STATUS_REG 0x0019
58
59#define ADIN1300_PHY_STATUS1 0x001a
60#define ADIN1300_PAIR_01_SWAP BIT(11)
61
62/* EEE register addresses, accessible via Clause 22 access using
63 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA.
64 * The bit-fields are the same as specified by IEEE for EEE.
65 */
66#define ADIN1300_EEE_CAP_REG 0x8000
67#define ADIN1300_EEE_ADV_REG 0x8001
68#define ADIN1300_EEE_LPABLE_REG 0x8002
69#define ADIN1300_CLOCK_STOP_REG 0x9400
70#define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
71
72#define ADIN1300_GE_SOFT_RESET_REG 0xff0c
73#define ADIN1300_GE_SOFT_RESET BIT(0)
74
75#define ADIN1300_GE_RGMII_CFG_REG 0xff23
76#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
77#define ADIN1300_GE_RGMII_RX_SEL(x) \
78 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
79#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
80#define ADIN1300_GE_RGMII_GTX_SEL(x) \
81 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
82#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
83#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
84#define ADIN1300_GE_RGMII_EN BIT(0)
85
86/* RGMII internal delay settings for rx and tx for ADIN1300 */
87#define ADIN1300_RGMII_1_60_NS 0x0001
88#define ADIN1300_RGMII_1_80_NS 0x0002
89#define ADIN1300_RGMII_2_00_NS 0x0000
90#define ADIN1300_RGMII_2_20_NS 0x0006
91#define ADIN1300_RGMII_2_40_NS 0x0007
92
93#define ADIN1300_GE_RMII_CFG_REG 0xff24
94#define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)
95#define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \
96 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
97#define ADIN1300_GE_RMII_EN BIT(0)
98
99/* RMII fifo depth values */
100#define ADIN1300_RMII_4_BITS 0x0000
101#define ADIN1300_RMII_8_BITS 0x0001
102#define ADIN1300_RMII_12_BITS 0x0002
103#define ADIN1300_RMII_16_BITS 0x0003
104#define ADIN1300_RMII_20_BITS 0x0004
105#define ADIN1300_RMII_24_BITS 0x0005
106
107/**
108 * struct adin_cfg_reg_map - map a config value to aregister value
109 * @cfg: value in device configuration
110 * @reg: value in the register
111 */
112struct adin_cfg_reg_map {
113 int cfg;
114 int reg;
115};
116
117static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
118 { 1600, ADIN1300_RGMII_1_60_NS },
119 { 1800, ADIN1300_RGMII_1_80_NS },
120 { 2000, ADIN1300_RGMII_2_00_NS },
121 { 2200, ADIN1300_RGMII_2_20_NS },
122 { 2400, ADIN1300_RGMII_2_40_NS },
123 { },
124};
125
126static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = {
127 { 4, ADIN1300_RMII_4_BITS },
128 { 8, ADIN1300_RMII_8_BITS },
129 { 12, ADIN1300_RMII_12_BITS },
130 { 16, ADIN1300_RMII_16_BITS },
131 { 20, ADIN1300_RMII_20_BITS },
132 { 24, ADIN1300_RMII_24_BITS },
133 { },
134};
135
136/**
137 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22
138 * @devad: device address used in Clause 45 access
139 * @cl45_regnum: register address defined by Clause 45
140 * @adin_regnum: equivalent register address accessible via Clause 22
141 */
142struct adin_clause45_mmd_map {
143 int devad;
144 u16 cl45_regnum;
145 u16 adin_regnum;
146};
147
148static const struct adin_clause45_mmd_map adin_clause45_mmd_map[] = {
149 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
150 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG },
151 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG },
152 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
153 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
154};
155
156struct adin_hw_stat {
157 const char *string;
158 u16 reg1;
159 u16 reg2;
160};
161
162static const struct adin_hw_stat adin_hw_stats[] = {
163 { "total_frames_checked_count", 0x940A, 0x940B }, /* hi + lo */
164 { "length_error_frames_count", 0x940C },
165 { "alignment_error_frames_count", 0x940D },
166 { "symbol_error_count", 0x940E },
167 { "oversized_frames_count", 0x940F },
168 { "undersized_frames_count", 0x9410 },
169 { "odd_nibble_frames_count", 0x9411 },
170 { "odd_preamble_packet_count", 0x9412 },
171 { "dribble_bits_frames_count", 0x9413 },
172 { "false_carrier_events_count", 0x9414 },
173};
174
175/**
176 * struct adin_priv - ADIN PHY driver private data
177 * @stats: statistic counters for the PHY
178 */
179struct adin_priv {
180 u64 stats[ARRAY_SIZE(adin_hw_stats)];
181};
182
183static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
184{
185 size_t i;
186
187 for (i = 0; tbl[i].cfg; i++) {
188 if (tbl[i].cfg == cfg)
189 return tbl[i].reg;
190 }
191
192 return -EINVAL;
193}
194
195static u32 adin_get_reg_value(struct phy_device *phydev,
196 const char *prop_name,
197 const struct adin_cfg_reg_map *tbl,
198 u32 dflt)
199{
200 struct device *dev = &phydev->mdio.dev;
201 u32 val;
202 int rc;
203
204 if (device_property_read_u32(dev, prop_name, &val))
205 return dflt;
206
207 rc = adin_lookup_reg_value(tbl, val);
208 if (rc < 0) {
209 phydev_warn(phydev,
210 "Unsupported value %u for %s using default (%u)\n",
211 val, prop_name, dflt);
212 return dflt;
213 }
214
215 return rc;
216}
217
218static int adin_config_rgmii_mode(struct phy_device *phydev)
219{
220 u32 val;
221 int reg;
222
223 if (!phy_interface_is_rgmii(phydev))
224 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
225 ADIN1300_GE_RGMII_CFG_REG,
226 ADIN1300_GE_RGMII_EN);
227
228 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
229 if (reg < 0)
230 return reg;
231
232 reg |= ADIN1300_GE_RGMII_EN;
233
234 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
235 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
236 reg |= ADIN1300_GE_RGMII_RXID_EN;
237
238 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
239 adin_rgmii_delays,
240 ADIN1300_RGMII_2_00_NS);
241 reg &= ~ADIN1300_GE_RGMII_RX_MSK;
242 reg |= ADIN1300_GE_RGMII_RX_SEL(val);
243 } else {
244 reg &= ~ADIN1300_GE_RGMII_RXID_EN;
245 }
246
247 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
248 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
249 reg |= ADIN1300_GE_RGMII_TXID_EN;
250
251 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
252 adin_rgmii_delays,
253 ADIN1300_RGMII_2_00_NS);
254 reg &= ~ADIN1300_GE_RGMII_GTX_MSK;
255 reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
256 } else {
257 reg &= ~ADIN1300_GE_RGMII_TXID_EN;
258 }
259
260 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
261 ADIN1300_GE_RGMII_CFG_REG, reg);
262}
263
264static int adin_config_rmii_mode(struct phy_device *phydev)
265{
266 u32 val;
267 int reg;
268
269 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
270 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
271 ADIN1300_GE_RMII_CFG_REG,
272 ADIN1300_GE_RMII_EN);
273
274 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
275 if (reg < 0)
276 return reg;
277
278 reg |= ADIN1300_GE_RMII_EN;
279
280 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
281 adin_rmii_fifo_depths,
282 ADIN1300_RMII_8_BITS);
283
284 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK;
285 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val);
286
287 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
288 ADIN1300_GE_RMII_CFG_REG, reg);
289}
290
291static int adin_get_downshift(struct phy_device *phydev, u8 *data)
292{
293 int val, cnt, enable;
294
295 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
296 if (val < 0)
297 return val;
298
299 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
300 if (cnt < 0)
301 return cnt;
302
303 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val);
304 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
305
306 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE;
307
308 return 0;
309}
310
311static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
312{
313 u16 val;
314 int rc;
315
316 if (cnt == DOWNSHIFT_DEV_DISABLE)
317 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
318 ADIN1300_DOWNSPEEDS_EN);
319
320 if (cnt > 7)
321 return -E2BIG;
322
323 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
324 val |= ADIN1300_LINKING_EN;
325
326 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
327 ADIN1300_LINKING_EN | ADIN1300_DOWNSPEED_RETRIES_MSK,
328 val);
329 if (rc < 0)
330 return rc;
331
332 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
333 ADIN1300_DOWNSPEEDS_EN);
334}
335
336static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)
337{
338 int val;
339
340 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);
341 if (val < 0)
342 return val;
343
344 if (ADIN1300_NRG_PD_EN & val) {
345 if (val & ADIN1300_NRG_PD_TX_EN)
346 /* default is 1 second */
347 *tx_interval = ETHTOOL_PHY_EDPD_DFLT_TX_MSECS;
348 else
349 *tx_interval = ETHTOOL_PHY_EDPD_NO_TX;
350 } else {
351 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
352 }
353
354 return 0;
355}
356
357static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
358{
359 u16 val;
360
361 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
362 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
363 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN));
364
365 val = ADIN1300_NRG_PD_EN;
366
367 switch (tx_interval) {
368 case 1000: /* 1 second */
369 fallthrough;
370 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
371 val |= ADIN1300_NRG_PD_TX_EN;
372 fallthrough;
373 case ETHTOOL_PHY_EDPD_NO_TX:
374 break;
375 default:
376 return -EINVAL;
377 }
378
379 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,
380 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN),
381 val);
382}
383
384static int adin_get_tunable(struct phy_device *phydev,
385 struct ethtool_tunable *tuna, void *data)
386{
387 switch (tuna->id) {
388 case ETHTOOL_PHY_DOWNSHIFT:
389 return adin_get_downshift(phydev, data);
390 case ETHTOOL_PHY_EDPD:
391 return adin_get_edpd(phydev, data);
392 default:
393 return -EOPNOTSUPP;
394 }
395}
396
397static int adin_set_tunable(struct phy_device *phydev,
398 struct ethtool_tunable *tuna, const void *data)
399{
400 switch (tuna->id) {
401 case ETHTOOL_PHY_DOWNSHIFT:
402 return adin_set_downshift(phydev, *(const u8 *)data);
403 case ETHTOOL_PHY_EDPD:
404 return adin_set_edpd(phydev, *(const u16 *)data);
405 default:
406 return -EOPNOTSUPP;
407 }
408}
409
410static int adin_config_init(struct phy_device *phydev)
411{
412 int rc;
413
414 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
415
416 rc = adin_config_rgmii_mode(phydev);
417 if (rc < 0)
418 return rc;
419
420 rc = adin_config_rmii_mode(phydev);
421 if (rc < 0)
422 return rc;
423
424 rc = adin_set_downshift(phydev, 4);
425 if (rc < 0)
426 return rc;
427
428 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
429 if (rc < 0)
430 return rc;
431
432 phydev_dbg(phydev, "PHY is using mode '%s'\n",
433 phy_modes(phydev->interface));
434
435 return 0;
436}
437
438static int adin_phy_ack_intr(struct phy_device *phydev)
439{
440 /* Clear pending interrupts */
441 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
442
443 return rc < 0 ? rc : 0;
444}
445
446static int adin_phy_config_intr(struct phy_device *phydev)
447{
448 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
449 return phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
450 ADIN1300_INT_MASK_EN);
451
452 return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
453 ADIN1300_INT_MASK_EN);
454}
455
456static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
457 u16 cl45_regnum)
458{
459 const struct adin_clause45_mmd_map *m;
460 int i;
461
462 if (devad == MDIO_MMD_VEND1)
463 return cl45_regnum;
464
465 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) {
466 m = &adin_clause45_mmd_map[i];
467 if (m->devad == devad && m->cl45_regnum == cl45_regnum)
468 return m->adin_regnum;
469 }
470
471 phydev_err(phydev,
472 "No translation available for devad: %d reg: %04x\n",
473 devad, cl45_regnum);
474
475 return -EINVAL;
476}
477
478static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
479{
480 struct mii_bus *bus = phydev->mdio.bus;
481 int phy_addr = phydev->mdio.addr;
482 int adin_regnum;
483 int err;
484
485 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
486 if (adin_regnum < 0)
487 return adin_regnum;
488
489 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
490 adin_regnum);
491 if (err)
492 return err;
493
494 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA);
495}
496
497static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
498 u16 val)
499{
500 struct mii_bus *bus = phydev->mdio.bus;
501 int phy_addr = phydev->mdio.addr;
502 int adin_regnum;
503 int err;
504
505 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
506 if (adin_regnum < 0)
507 return adin_regnum;
508
509 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
510 adin_regnum);
511 if (err)
512 return err;
513
514 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
515}
516
517static int adin_config_mdix(struct phy_device *phydev)
518{
519 bool auto_en, mdix_en;
520 int reg;
521
522 mdix_en = false;
523 auto_en = false;
524 switch (phydev->mdix_ctrl) {
525 case ETH_TP_MDI:
526 break;
527 case ETH_TP_MDI_X:
528 mdix_en = true;
529 break;
530 case ETH_TP_MDI_AUTO:
531 auto_en = true;
532 break;
533 default:
534 return -EINVAL;
535 }
536
537 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
538 if (reg < 0)
539 return reg;
540
541 if (mdix_en)
542 reg |= ADIN1300_MAN_MDIX_EN;
543 else
544 reg &= ~ADIN1300_MAN_MDIX_EN;
545
546 if (auto_en)
547 reg |= ADIN1300_AUTO_MDI_EN;
548 else
549 reg &= ~ADIN1300_AUTO_MDI_EN;
550
551 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
552}
553
554static int adin_config_aneg(struct phy_device *phydev)
555{
556 int ret;
557
558 ret = adin_config_mdix(phydev);
559 if (ret)
560 return ret;
561
562 return genphy_config_aneg(phydev);
563}
564
565static int adin_mdix_update(struct phy_device *phydev)
566{
567 bool auto_en, mdix_en;
568 bool swapped;
569 int reg;
570
571 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
572 if (reg < 0)
573 return reg;
574
575 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN);
576 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN);
577
578 /* If MDI/MDIX is forced, just read it from the control reg */
579 if (!auto_en) {
580 if (mdix_en)
581 phydev->mdix = ETH_TP_MDI_X;
582 else
583 phydev->mdix = ETH_TP_MDI;
584 return 0;
585 }
586
587 /**
588 * Otherwise, we need to deduce it from the PHY status2 reg.
589 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies
590 * a preference for MDIX when it is set.
591 */
592 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
593 if (reg < 0)
594 return reg;
595
596 swapped = !!(reg & ADIN1300_PAIR_01_SWAP);
597
598 if (mdix_en != swapped)
599 phydev->mdix = ETH_TP_MDI_X;
600 else
601 phydev->mdix = ETH_TP_MDI;
602
603 return 0;
604}
605
606static int adin_read_status(struct phy_device *phydev)
607{
608 int ret;
609
610 ret = adin_mdix_update(phydev);
611 if (ret < 0)
612 return ret;
613
614 return genphy_read_status(phydev);
615}
616
617static int adin_soft_reset(struct phy_device *phydev)
618{
619 int rc;
620
621 /* The reset bit is self-clearing, set it and wait */
622 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
623 ADIN1300_GE_SOFT_RESET_REG,
624 ADIN1300_GE_SOFT_RESET);
625 if (rc < 0)
626 return rc;
627
628 msleep(20);
629
630 /* If we get a read error something may be wrong */
631 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
632 ADIN1300_GE_SOFT_RESET_REG);
633
634 return rc < 0 ? rc : 0;
635}
636
637static int adin_get_sset_count(struct phy_device *phydev)
638{
639 return ARRAY_SIZE(adin_hw_stats);
640}
641
642static void adin_get_strings(struct phy_device *phydev, u8 *data)
643{
644 int i;
645
646 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
647 strlcpy(&data[i * ETH_GSTRING_LEN],
648 adin_hw_stats[i].string, ETH_GSTRING_LEN);
649 }
650}
651
652static int adin_read_mmd_stat_regs(struct phy_device *phydev,
653 const struct adin_hw_stat *stat,
654 u32 *val)
655{
656 int ret;
657
658 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
659 if (ret < 0)
660 return ret;
661
662 *val = (ret & 0xffff);
663
664 if (stat->reg2 == 0)
665 return 0;
666
667 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
668 if (ret < 0)
669 return ret;
670
671 *val <<= 16;
672 *val |= (ret & 0xffff);
673
674 return 0;
675}
676
677static u64 adin_get_stat(struct phy_device *phydev, int i)
678{
679 const struct adin_hw_stat *stat = &adin_hw_stats[i];
680 struct adin_priv *priv = phydev->priv;
681 u32 val;
682 int ret;
683
684 if (stat->reg1 > 0x1f) {
685 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
686 if (ret < 0)
687 return (u64)(~0);
688 } else {
689 ret = phy_read(phydev, stat->reg1);
690 if (ret < 0)
691 return (u64)(~0);
692 val = (ret & 0xffff);
693 }
694
695 priv->stats[i] += val;
696
697 return priv->stats[i];
698}
699
700static void adin_get_stats(struct phy_device *phydev,
701 struct ethtool_stats *stats, u64 *data)
702{
703 int i, rc;
704
705 /* latch copies of all the frame-checker counters */
706 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
707 if (rc < 0)
708 return;
709
710 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
711 data[i] = adin_get_stat(phydev, i);
712}
713
714static int adin_probe(struct phy_device *phydev)
715{
716 struct device *dev = &phydev->mdio.dev;
717 struct adin_priv *priv;
718
719 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
720 if (!priv)
721 return -ENOMEM;
722
723 phydev->priv = priv;
724
725 return 0;
726}
727
728static struct phy_driver adin_driver[] = {
729 {
730 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
731 .name = "ADIN1200",
732 .probe = adin_probe,
733 .config_init = adin_config_init,
734 .soft_reset = adin_soft_reset,
735 .config_aneg = adin_config_aneg,
736 .read_status = adin_read_status,
737 .get_tunable = adin_get_tunable,
738 .set_tunable = adin_set_tunable,
739 .ack_interrupt = adin_phy_ack_intr,
740 .config_intr = adin_phy_config_intr,
741 .get_sset_count = adin_get_sset_count,
742 .get_strings = adin_get_strings,
743 .get_stats = adin_get_stats,
744 .resume = genphy_resume,
745 .suspend = genphy_suspend,
746 .read_mmd = adin_read_mmd,
747 .write_mmd = adin_write_mmd,
748 },
749 {
750 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
751 .name = "ADIN1300",
752 .probe = adin_probe,
753 .config_init = adin_config_init,
754 .soft_reset = adin_soft_reset,
755 .config_aneg = adin_config_aneg,
756 .read_status = adin_read_status,
757 .get_tunable = adin_get_tunable,
758 .set_tunable = adin_set_tunable,
759 .ack_interrupt = adin_phy_ack_intr,
760 .config_intr = adin_phy_config_intr,
761 .get_sset_count = adin_get_sset_count,
762 .get_strings = adin_get_strings,
763 .get_stats = adin_get_stats,
764 .resume = genphy_resume,
765 .suspend = genphy_suspend,
766 .read_mmd = adin_read_mmd,
767 .write_mmd = adin_write_mmd,
768 },
769};
770
771module_phy_driver(adin_driver);
772
773static struct mdio_device_id __maybe_unused adin_tbl[] = {
774 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
775 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
776 { }
777};
778
779MODULE_DEVICE_TABLE(mdio, adin_tbl);
780MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
781MODULE_LICENSE("GPL");