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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Analog Devices Industrial Ethernet PHYs
4 *
5 * Copyright 2019 Analog Devices Inc.
6 */
7#include <linux/kernel.h>
8#include <linux/bitfield.h>
9#include <linux/delay.h>
10#include <linux/errno.h>
11#include <linux/ethtool_netlink.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/mii.h>
15#include <linux/phy.h>
16#include <linux/property.h>
17
18#define PHY_ID_ADIN1200 0x0283bc20
19#define PHY_ID_ADIN1300 0x0283bc30
20
21#define ADIN1300_MII_EXT_REG_PTR 0x0010
22#define ADIN1300_MII_EXT_REG_DATA 0x0011
23
24#define ADIN1300_PHY_CTRL1 0x0012
25#define ADIN1300_AUTO_MDI_EN BIT(10)
26#define ADIN1300_MAN_MDIX_EN BIT(9)
27#define ADIN1300_DIAG_CLK_EN BIT(2)
28
29#define ADIN1300_RX_ERR_CNT 0x0014
30
31#define ADIN1300_PHY_CTRL_STATUS2 0x0015
32#define ADIN1300_NRG_PD_EN BIT(3)
33#define ADIN1300_NRG_PD_TX_EN BIT(2)
34#define ADIN1300_NRG_PD_STATUS BIT(1)
35
36#define ADIN1300_PHY_CTRL2 0x0016
37#define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
38#define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
39#define ADIN1300_GROUP_MDIO_EN BIT(6)
40#define ADIN1300_DOWNSPEEDS_EN \
41 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
42
43#define ADIN1300_PHY_CTRL3 0x0017
44#define ADIN1300_LINKING_EN BIT(13)
45#define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10)
46
47#define ADIN1300_INT_MASK_REG 0x0018
48#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
49#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
50#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
51#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
52#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
53#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
54#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
55#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
56#define ADIN1300_INT_HW_IRQ_EN BIT(0)
57#define ADIN1300_INT_MASK_EN \
58 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN)
59#define ADIN1300_INT_STATUS_REG 0x0019
60
61#define ADIN1300_PHY_STATUS1 0x001a
62#define ADIN1300_PAIR_01_SWAP BIT(11)
63
64/* EEE register addresses, accessible via Clause 22 access using
65 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA.
66 * The bit-fields are the same as specified by IEEE for EEE.
67 */
68#define ADIN1300_EEE_CAP_REG 0x8000
69#define ADIN1300_EEE_ADV_REG 0x8001
70#define ADIN1300_EEE_LPABLE_REG 0x8002
71
72#define ADIN1300_FLD_EN_REG 0x8E27
73#define ADIN1300_FLD_PCS_ERR_100_EN BIT(7)
74#define ADIN1300_FLD_PCS_ERR_1000_EN BIT(6)
75#define ADIN1300_FLD_SLCR_OUT_STUCK_100_EN BIT(5)
76#define ADIN1300_FLD_SLCR_OUT_STUCK_1000_EN BIT(4)
77#define ADIN1300_FLD_SLCR_IN_ZDET_100_EN BIT(3)
78#define ADIN1300_FLD_SLCR_IN_ZDET_1000_EN BIT(2)
79#define ADIN1300_FLD_SLCR_IN_INVLD_100_EN BIT(1)
80#define ADIN1300_FLD_SLCR_IN_INVLD_1000_EN BIT(0)
81/* These bits are the ones which are enabled by default. */
82#define ADIN1300_FLD_EN_ON \
83 (ADIN1300_FLD_SLCR_OUT_STUCK_100_EN | \
84 ADIN1300_FLD_SLCR_OUT_STUCK_1000_EN | \
85 ADIN1300_FLD_SLCR_IN_ZDET_100_EN | \
86 ADIN1300_FLD_SLCR_IN_ZDET_1000_EN | \
87 ADIN1300_FLD_SLCR_IN_INVLD_1000_EN)
88
89#define ADIN1300_CLOCK_STOP_REG 0x9400
90#define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
91
92#define ADIN1300_CDIAG_RUN 0xba1b
93#define ADIN1300_CDIAG_RUN_EN BIT(0)
94
95/*
96 * The XSIM3/2/1 and XSHRT3/2/1 are actually relative.
97 * For CDIAG_DTLD_RSLTS(0) it's ADIN1300_CDIAG_RSLT_XSIM3/2/1
98 * For CDIAG_DTLD_RSLTS(1) it's ADIN1300_CDIAG_RSLT_XSIM3/2/0
99 * For CDIAG_DTLD_RSLTS(2) it's ADIN1300_CDIAG_RSLT_XSIM3/1/0
100 * For CDIAG_DTLD_RSLTS(3) it's ADIN1300_CDIAG_RSLT_XSIM2/1/0
101 */
102#define ADIN1300_CDIAG_DTLD_RSLTS(x) (0xba1d + (x))
103#define ADIN1300_CDIAG_RSLT_BUSY BIT(10)
104#define ADIN1300_CDIAG_RSLT_XSIM3 BIT(9)
105#define ADIN1300_CDIAG_RSLT_XSIM2 BIT(8)
106#define ADIN1300_CDIAG_RSLT_XSIM1 BIT(7)
107#define ADIN1300_CDIAG_RSLT_SIM BIT(6)
108#define ADIN1300_CDIAG_RSLT_XSHRT3 BIT(5)
109#define ADIN1300_CDIAG_RSLT_XSHRT2 BIT(4)
110#define ADIN1300_CDIAG_RSLT_XSHRT1 BIT(3)
111#define ADIN1300_CDIAG_RSLT_SHRT BIT(2)
112#define ADIN1300_CDIAG_RSLT_OPEN BIT(1)
113#define ADIN1300_CDIAG_RSLT_GOOD BIT(0)
114
115#define ADIN1300_CDIAG_FLT_DIST(x) (0xba21 + (x))
116
117#define ADIN1300_GE_SOFT_RESET_REG 0xff0c
118#define ADIN1300_GE_SOFT_RESET BIT(0)
119
120#define ADIN1300_GE_CLK_CFG_REG 0xff1f
121#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0)
122#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5)
123#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4)
124#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3)
125#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2)
126#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1)
127#define ADIN1300_GE_CLK_CFG_25 BIT(0)
128
129#define ADIN1300_GE_RGMII_CFG_REG 0xff23
130#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
131#define ADIN1300_GE_RGMII_RX_SEL(x) \
132 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
133#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
134#define ADIN1300_GE_RGMII_GTX_SEL(x) \
135 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
136#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
137#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
138#define ADIN1300_GE_RGMII_EN BIT(0)
139
140/* RGMII internal delay settings for rx and tx for ADIN1300 */
141#define ADIN1300_RGMII_1_60_NS 0x0001
142#define ADIN1300_RGMII_1_80_NS 0x0002
143#define ADIN1300_RGMII_2_00_NS 0x0000
144#define ADIN1300_RGMII_2_20_NS 0x0006
145#define ADIN1300_RGMII_2_40_NS 0x0007
146
147#define ADIN1300_GE_RMII_CFG_REG 0xff24
148#define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)
149#define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \
150 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
151#define ADIN1300_GE_RMII_EN BIT(0)
152
153/* RMII fifo depth values */
154#define ADIN1300_RMII_4_BITS 0x0000
155#define ADIN1300_RMII_8_BITS 0x0001
156#define ADIN1300_RMII_12_BITS 0x0002
157#define ADIN1300_RMII_16_BITS 0x0003
158#define ADIN1300_RMII_20_BITS 0x0004
159#define ADIN1300_RMII_24_BITS 0x0005
160
161/**
162 * struct adin_cfg_reg_map - map a config value to aregister value
163 * @cfg: value in device configuration
164 * @reg: value in the register
165 */
166struct adin_cfg_reg_map {
167 int cfg;
168 int reg;
169};
170
171static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
172 { 1600, ADIN1300_RGMII_1_60_NS },
173 { 1800, ADIN1300_RGMII_1_80_NS },
174 { 2000, ADIN1300_RGMII_2_00_NS },
175 { 2200, ADIN1300_RGMII_2_20_NS },
176 { 2400, ADIN1300_RGMII_2_40_NS },
177 { },
178};
179
180static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = {
181 { 4, ADIN1300_RMII_4_BITS },
182 { 8, ADIN1300_RMII_8_BITS },
183 { 12, ADIN1300_RMII_12_BITS },
184 { 16, ADIN1300_RMII_16_BITS },
185 { 20, ADIN1300_RMII_20_BITS },
186 { 24, ADIN1300_RMII_24_BITS },
187 { },
188};
189
190/**
191 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22
192 * @devad: device address used in Clause 45 access
193 * @cl45_regnum: register address defined by Clause 45
194 * @adin_regnum: equivalent register address accessible via Clause 22
195 */
196struct adin_clause45_mmd_map {
197 int devad;
198 u16 cl45_regnum;
199 u16 adin_regnum;
200};
201
202static const struct adin_clause45_mmd_map adin_clause45_mmd_map[] = {
203 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
204 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG },
205 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG },
206 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
207 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
208};
209
210struct adin_hw_stat {
211 const char *string;
212 u16 reg1;
213 u16 reg2;
214};
215
216static const struct adin_hw_stat adin_hw_stats[] = {
217 { "total_frames_checked_count", 0x940A, 0x940B }, /* hi + lo */
218 { "length_error_frames_count", 0x940C },
219 { "alignment_error_frames_count", 0x940D },
220 { "symbol_error_count", 0x940E },
221 { "oversized_frames_count", 0x940F },
222 { "undersized_frames_count", 0x9410 },
223 { "odd_nibble_frames_count", 0x9411 },
224 { "odd_preamble_packet_count", 0x9412 },
225 { "dribble_bits_frames_count", 0x9413 },
226 { "false_carrier_events_count", 0x9414 },
227};
228
229/**
230 * struct adin_priv - ADIN PHY driver private data
231 * @stats: statistic counters for the PHY
232 */
233struct adin_priv {
234 u64 stats[ARRAY_SIZE(adin_hw_stats)];
235};
236
237static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
238{
239 size_t i;
240
241 for (i = 0; tbl[i].cfg; i++) {
242 if (tbl[i].cfg == cfg)
243 return tbl[i].reg;
244 }
245
246 return -EINVAL;
247}
248
249static u32 adin_get_reg_value(struct phy_device *phydev,
250 const char *prop_name,
251 const struct adin_cfg_reg_map *tbl,
252 u32 dflt)
253{
254 struct device *dev = &phydev->mdio.dev;
255 u32 val;
256 int rc;
257
258 if (device_property_read_u32(dev, prop_name, &val))
259 return dflt;
260
261 rc = adin_lookup_reg_value(tbl, val);
262 if (rc < 0) {
263 phydev_warn(phydev,
264 "Unsupported value %u for %s using default (%u)\n",
265 val, prop_name, dflt);
266 return dflt;
267 }
268
269 return rc;
270}
271
272static int adin_config_rgmii_mode(struct phy_device *phydev)
273{
274 u32 val;
275 int reg;
276
277 if (!phy_interface_is_rgmii(phydev))
278 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
279 ADIN1300_GE_RGMII_CFG_REG,
280 ADIN1300_GE_RGMII_EN);
281
282 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
283 if (reg < 0)
284 return reg;
285
286 reg |= ADIN1300_GE_RGMII_EN;
287
288 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
289 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
290 reg |= ADIN1300_GE_RGMII_RXID_EN;
291
292 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
293 adin_rgmii_delays,
294 ADIN1300_RGMII_2_00_NS);
295 reg &= ~ADIN1300_GE_RGMII_RX_MSK;
296 reg |= ADIN1300_GE_RGMII_RX_SEL(val);
297 } else {
298 reg &= ~ADIN1300_GE_RGMII_RXID_EN;
299 }
300
301 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
302 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
303 reg |= ADIN1300_GE_RGMII_TXID_EN;
304
305 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
306 adin_rgmii_delays,
307 ADIN1300_RGMII_2_00_NS);
308 reg &= ~ADIN1300_GE_RGMII_GTX_MSK;
309 reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
310 } else {
311 reg &= ~ADIN1300_GE_RGMII_TXID_EN;
312 }
313
314 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
315 ADIN1300_GE_RGMII_CFG_REG, reg);
316}
317
318static int adin_config_rmii_mode(struct phy_device *phydev)
319{
320 u32 val;
321 int reg;
322
323 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
324 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
325 ADIN1300_GE_RMII_CFG_REG,
326 ADIN1300_GE_RMII_EN);
327
328 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
329 if (reg < 0)
330 return reg;
331
332 reg |= ADIN1300_GE_RMII_EN;
333
334 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
335 adin_rmii_fifo_depths,
336 ADIN1300_RMII_8_BITS);
337
338 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK;
339 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val);
340
341 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
342 ADIN1300_GE_RMII_CFG_REG, reg);
343}
344
345static int adin_get_downshift(struct phy_device *phydev, u8 *data)
346{
347 int val, cnt, enable;
348
349 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
350 if (val < 0)
351 return val;
352
353 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
354 if (cnt < 0)
355 return cnt;
356
357 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val);
358 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
359
360 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE;
361
362 return 0;
363}
364
365static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
366{
367 u16 val;
368 int rc;
369
370 if (cnt == DOWNSHIFT_DEV_DISABLE)
371 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
372 ADIN1300_DOWNSPEEDS_EN);
373
374 if (cnt > 7)
375 return -E2BIG;
376
377 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
378
379 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
380 ADIN1300_DOWNSPEED_RETRIES_MSK,
381 val);
382 if (rc < 0)
383 return rc;
384
385 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
386 ADIN1300_DOWNSPEEDS_EN);
387}
388
389static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)
390{
391 int val;
392
393 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);
394 if (val < 0)
395 return val;
396
397 if (ADIN1300_NRG_PD_EN & val) {
398 if (val & ADIN1300_NRG_PD_TX_EN)
399 /* default is 1 second */
400 *tx_interval = ETHTOOL_PHY_EDPD_DFLT_TX_MSECS;
401 else
402 *tx_interval = ETHTOOL_PHY_EDPD_NO_TX;
403 } else {
404 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
405 }
406
407 return 0;
408}
409
410static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
411{
412 u16 val;
413
414 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
415 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
416 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN));
417
418 val = ADIN1300_NRG_PD_EN;
419
420 switch (tx_interval) {
421 case 1000: /* 1 second */
422 fallthrough;
423 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
424 val |= ADIN1300_NRG_PD_TX_EN;
425 fallthrough;
426 case ETHTOOL_PHY_EDPD_NO_TX:
427 break;
428 default:
429 return -EINVAL;
430 }
431
432 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,
433 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN),
434 val);
435}
436
437static int adin_get_fast_down(struct phy_device *phydev, u8 *msecs)
438{
439 int reg;
440
441 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_FLD_EN_REG);
442 if (reg < 0)
443 return reg;
444
445 if (reg & ADIN1300_FLD_EN_ON)
446 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_ON;
447 else
448 *msecs = ETHTOOL_PHY_FAST_LINK_DOWN_OFF;
449
450 return 0;
451}
452
453static int adin_set_fast_down(struct phy_device *phydev, const u8 *msecs)
454{
455 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_ON)
456 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
457 ADIN1300_FLD_EN_REG,
458 ADIN1300_FLD_EN_ON);
459
460 if (*msecs == ETHTOOL_PHY_FAST_LINK_DOWN_OFF)
461 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
462 ADIN1300_FLD_EN_REG,
463 ADIN1300_FLD_EN_ON);
464
465 return -EINVAL;
466}
467
468static int adin_get_tunable(struct phy_device *phydev,
469 struct ethtool_tunable *tuna, void *data)
470{
471 switch (tuna->id) {
472 case ETHTOOL_PHY_DOWNSHIFT:
473 return adin_get_downshift(phydev, data);
474 case ETHTOOL_PHY_EDPD:
475 return adin_get_edpd(phydev, data);
476 case ETHTOOL_PHY_FAST_LINK_DOWN:
477 return adin_get_fast_down(phydev, data);
478 default:
479 return -EOPNOTSUPP;
480 }
481}
482
483static int adin_set_tunable(struct phy_device *phydev,
484 struct ethtool_tunable *tuna, const void *data)
485{
486 switch (tuna->id) {
487 case ETHTOOL_PHY_DOWNSHIFT:
488 return adin_set_downshift(phydev, *(const u8 *)data);
489 case ETHTOOL_PHY_EDPD:
490 return adin_set_edpd(phydev, *(const u16 *)data);
491 case ETHTOOL_PHY_FAST_LINK_DOWN:
492 return adin_set_fast_down(phydev, data);
493 default:
494 return -EOPNOTSUPP;
495 }
496}
497
498static int adin_config_clk_out(struct phy_device *phydev)
499{
500 struct device *dev = &phydev->mdio.dev;
501 const char *val = NULL;
502 u8 sel = 0;
503
504 device_property_read_string(dev, "adi,phy-output-clock", &val);
505 if (!val) {
506 /* property not present, do not enable GP_CLK pin */
507 } else if (strcmp(val, "25mhz-reference") == 0) {
508 sel |= ADIN1300_GE_CLK_CFG_25;
509 } else if (strcmp(val, "125mhz-free-running") == 0) {
510 sel |= ADIN1300_GE_CLK_CFG_FREE_125;
511 } else if (strcmp(val, "adaptive-free-running") == 0) {
512 sel |= ADIN1300_GE_CLK_CFG_HRT_FREE;
513 } else {
514 phydev_err(phydev, "invalid adi,phy-output-clock\n");
515 return -EINVAL;
516 }
517
518 if (device_property_read_bool(dev, "adi,phy-output-reference-clock"))
519 sel |= ADIN1300_GE_CLK_CFG_REF_EN;
520
521 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG,
522 ADIN1300_GE_CLK_CFG_MASK, sel);
523}
524
525static int adin_config_init(struct phy_device *phydev)
526{
527 int rc;
528
529 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
530
531 rc = adin_config_rgmii_mode(phydev);
532 if (rc < 0)
533 return rc;
534
535 rc = adin_config_rmii_mode(phydev);
536 if (rc < 0)
537 return rc;
538
539 rc = adin_set_downshift(phydev, 4);
540 if (rc < 0)
541 return rc;
542
543 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
544 if (rc < 0)
545 return rc;
546
547 rc = adin_config_clk_out(phydev);
548 if (rc < 0)
549 return rc;
550
551 phydev_dbg(phydev, "PHY is using mode '%s'\n",
552 phy_modes(phydev->interface));
553
554 return 0;
555}
556
557static int adin_phy_ack_intr(struct phy_device *phydev)
558{
559 /* Clear pending interrupts */
560 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
561
562 return rc < 0 ? rc : 0;
563}
564
565static int adin_phy_config_intr(struct phy_device *phydev)
566{
567 int err;
568
569 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
570 err = adin_phy_ack_intr(phydev);
571 if (err)
572 return err;
573
574 err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
575 ADIN1300_INT_MASK_EN);
576 } else {
577 err = phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
578 ADIN1300_INT_MASK_EN);
579 if (err)
580 return err;
581
582 err = adin_phy_ack_intr(phydev);
583 }
584
585 return err;
586}
587
588static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev)
589{
590 int irq_status;
591
592 irq_status = phy_read(phydev, ADIN1300_INT_STATUS_REG);
593 if (irq_status < 0) {
594 phy_error(phydev);
595 return IRQ_NONE;
596 }
597
598 if (!(irq_status & ADIN1300_INT_LINK_STAT_CHNG_EN))
599 return IRQ_NONE;
600
601 phy_trigger_machine(phydev);
602
603 return IRQ_HANDLED;
604}
605
606static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
607 u16 cl45_regnum)
608{
609 const struct adin_clause45_mmd_map *m;
610 int i;
611
612 if (devad == MDIO_MMD_VEND1)
613 return cl45_regnum;
614
615 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) {
616 m = &adin_clause45_mmd_map[i];
617 if (m->devad == devad && m->cl45_regnum == cl45_regnum)
618 return m->adin_regnum;
619 }
620
621 phydev_err(phydev,
622 "No translation available for devad: %d reg: %04x\n",
623 devad, cl45_regnum);
624
625 return -EINVAL;
626}
627
628static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
629{
630 struct mii_bus *bus = phydev->mdio.bus;
631 int phy_addr = phydev->mdio.addr;
632 int adin_regnum;
633 int err;
634
635 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
636 if (adin_regnum < 0)
637 return adin_regnum;
638
639 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
640 adin_regnum);
641 if (err)
642 return err;
643
644 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA);
645}
646
647static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
648 u16 val)
649{
650 struct mii_bus *bus = phydev->mdio.bus;
651 int phy_addr = phydev->mdio.addr;
652 int adin_regnum;
653 int err;
654
655 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
656 if (adin_regnum < 0)
657 return adin_regnum;
658
659 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
660 adin_regnum);
661 if (err)
662 return err;
663
664 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
665}
666
667static int adin_config_mdix(struct phy_device *phydev)
668{
669 bool auto_en, mdix_en;
670 int reg;
671
672 mdix_en = false;
673 auto_en = false;
674 switch (phydev->mdix_ctrl) {
675 case ETH_TP_MDI:
676 break;
677 case ETH_TP_MDI_X:
678 mdix_en = true;
679 break;
680 case ETH_TP_MDI_AUTO:
681 auto_en = true;
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
688 if (reg < 0)
689 return reg;
690
691 if (mdix_en)
692 reg |= ADIN1300_MAN_MDIX_EN;
693 else
694 reg &= ~ADIN1300_MAN_MDIX_EN;
695
696 if (auto_en)
697 reg |= ADIN1300_AUTO_MDI_EN;
698 else
699 reg &= ~ADIN1300_AUTO_MDI_EN;
700
701 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
702}
703
704static int adin_config_aneg(struct phy_device *phydev)
705{
706 int ret;
707
708 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
709 if (ret < 0)
710 return ret;
711
712 ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
713 if (ret < 0)
714 return ret;
715
716 ret = adin_config_mdix(phydev);
717 if (ret)
718 return ret;
719
720 return genphy_config_aneg(phydev);
721}
722
723static int adin_mdix_update(struct phy_device *phydev)
724{
725 bool auto_en, mdix_en;
726 bool swapped;
727 int reg;
728
729 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
730 if (reg < 0)
731 return reg;
732
733 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN);
734 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN);
735
736 /* If MDI/MDIX is forced, just read it from the control reg */
737 if (!auto_en) {
738 if (mdix_en)
739 phydev->mdix = ETH_TP_MDI_X;
740 else
741 phydev->mdix = ETH_TP_MDI;
742 return 0;
743 }
744
745 /**
746 * Otherwise, we need to deduce it from the PHY status2 reg.
747 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies
748 * a preference for MDIX when it is set.
749 */
750 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
751 if (reg < 0)
752 return reg;
753
754 swapped = !!(reg & ADIN1300_PAIR_01_SWAP);
755
756 if (mdix_en != swapped)
757 phydev->mdix = ETH_TP_MDI_X;
758 else
759 phydev->mdix = ETH_TP_MDI;
760
761 return 0;
762}
763
764static int adin_read_status(struct phy_device *phydev)
765{
766 int ret;
767
768 ret = adin_mdix_update(phydev);
769 if (ret < 0)
770 return ret;
771
772 return genphy_read_status(phydev);
773}
774
775static int adin_soft_reset(struct phy_device *phydev)
776{
777 int rc;
778
779 /* The reset bit is self-clearing, set it and wait */
780 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
781 ADIN1300_GE_SOFT_RESET_REG,
782 ADIN1300_GE_SOFT_RESET);
783 if (rc < 0)
784 return rc;
785
786 msleep(20);
787
788 /* If we get a read error something may be wrong */
789 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
790 ADIN1300_GE_SOFT_RESET_REG);
791
792 return rc < 0 ? rc : 0;
793}
794
795static int adin_get_sset_count(struct phy_device *phydev)
796{
797 return ARRAY_SIZE(adin_hw_stats);
798}
799
800static void adin_get_strings(struct phy_device *phydev, u8 *data)
801{
802 int i;
803
804 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
805 strscpy(&data[i * ETH_GSTRING_LEN],
806 adin_hw_stats[i].string, ETH_GSTRING_LEN);
807 }
808}
809
810static int adin_read_mmd_stat_regs(struct phy_device *phydev,
811 const struct adin_hw_stat *stat,
812 u32 *val)
813{
814 int ret;
815
816 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
817 if (ret < 0)
818 return ret;
819
820 *val = (ret & 0xffff);
821
822 if (stat->reg2 == 0)
823 return 0;
824
825 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
826 if (ret < 0)
827 return ret;
828
829 *val <<= 16;
830 *val |= (ret & 0xffff);
831
832 return 0;
833}
834
835static u64 adin_get_stat(struct phy_device *phydev, int i)
836{
837 const struct adin_hw_stat *stat = &adin_hw_stats[i];
838 struct adin_priv *priv = phydev->priv;
839 u32 val;
840 int ret;
841
842 if (stat->reg1 > 0x1f) {
843 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
844 if (ret < 0)
845 return (u64)(~0);
846 } else {
847 ret = phy_read(phydev, stat->reg1);
848 if (ret < 0)
849 return (u64)(~0);
850 val = (ret & 0xffff);
851 }
852
853 priv->stats[i] += val;
854
855 return priv->stats[i];
856}
857
858static void adin_get_stats(struct phy_device *phydev,
859 struct ethtool_stats *stats, u64 *data)
860{
861 int i, rc;
862
863 /* latch copies of all the frame-checker counters */
864 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
865 if (rc < 0)
866 return;
867
868 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
869 data[i] = adin_get_stat(phydev, i);
870}
871
872static int adin_probe(struct phy_device *phydev)
873{
874 struct device *dev = &phydev->mdio.dev;
875 struct adin_priv *priv;
876
877 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
878 if (!priv)
879 return -ENOMEM;
880
881 phydev->priv = priv;
882
883 return 0;
884}
885
886static int adin_cable_test_start(struct phy_device *phydev)
887{
888 int ret;
889
890 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
891 if (ret < 0)
892 return ret;
893
894 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
895 if (ret < 0)
896 return ret;
897
898 /* wait a bit for the clock to stabilize */
899 msleep(50);
900
901 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN,
902 ADIN1300_CDIAG_RUN_EN);
903}
904
905static int adin_cable_test_report_trans(int result)
906{
907 int mask;
908
909 if (result & ADIN1300_CDIAG_RSLT_GOOD)
910 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
911 if (result & ADIN1300_CDIAG_RSLT_OPEN)
912 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
913
914 /* short with other pairs */
915 mask = ADIN1300_CDIAG_RSLT_XSHRT3 |
916 ADIN1300_CDIAG_RSLT_XSHRT2 |
917 ADIN1300_CDIAG_RSLT_XSHRT1;
918 if (result & mask)
919 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
920
921 if (result & ADIN1300_CDIAG_RSLT_SHRT)
922 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
923
924 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
925}
926
927static int adin_cable_test_report_pair(struct phy_device *phydev,
928 unsigned int pair)
929{
930 int fault_rslt;
931 int ret;
932
933 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
934 ADIN1300_CDIAG_DTLD_RSLTS(pair));
935 if (ret < 0)
936 return ret;
937
938 fault_rslt = adin_cable_test_report_trans(ret);
939
940 ret = ethnl_cable_test_result(phydev, pair, fault_rslt);
941 if (ret < 0)
942 return ret;
943
944 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
945 ADIN1300_CDIAG_FLT_DIST(pair));
946 if (ret < 0)
947 return ret;
948
949 switch (fault_rslt) {
950 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN:
951 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:
952 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:
953 return ethnl_cable_test_fault_length(phydev, pair, ret * 100);
954 default:
955 return 0;
956 }
957}
958
959static int adin_cable_test_report(struct phy_device *phydev)
960{
961 unsigned int pair;
962 int ret;
963
964 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) {
965 ret = adin_cable_test_report_pair(phydev, pair);
966 if (ret < 0)
967 return ret;
968 }
969
970 return 0;
971}
972
973static int adin_cable_test_get_status(struct phy_device *phydev,
974 bool *finished)
975{
976 int ret;
977
978 *finished = false;
979
980 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN);
981 if (ret < 0)
982 return ret;
983
984 if (ret & ADIN1300_CDIAG_RUN_EN)
985 return 0;
986
987 *finished = true;
988
989 return adin_cable_test_report(phydev);
990}
991
992static struct phy_driver adin_driver[] = {
993 {
994 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
995 .name = "ADIN1200",
996 .flags = PHY_POLL_CABLE_TEST,
997 .probe = adin_probe,
998 .config_init = adin_config_init,
999 .soft_reset = adin_soft_reset,
1000 .config_aneg = adin_config_aneg,
1001 .read_status = adin_read_status,
1002 .get_tunable = adin_get_tunable,
1003 .set_tunable = adin_set_tunable,
1004 .config_intr = adin_phy_config_intr,
1005 .handle_interrupt = adin_phy_handle_interrupt,
1006 .get_sset_count = adin_get_sset_count,
1007 .get_strings = adin_get_strings,
1008 .get_stats = adin_get_stats,
1009 .resume = genphy_resume,
1010 .suspend = genphy_suspend,
1011 .read_mmd = adin_read_mmd,
1012 .write_mmd = adin_write_mmd,
1013 .cable_test_start = adin_cable_test_start,
1014 .cable_test_get_status = adin_cable_test_get_status,
1015 },
1016 {
1017 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
1018 .name = "ADIN1300",
1019 .flags = PHY_POLL_CABLE_TEST,
1020 .probe = adin_probe,
1021 .config_init = adin_config_init,
1022 .soft_reset = adin_soft_reset,
1023 .config_aneg = adin_config_aneg,
1024 .read_status = adin_read_status,
1025 .get_tunable = adin_get_tunable,
1026 .set_tunable = adin_set_tunable,
1027 .config_intr = adin_phy_config_intr,
1028 .handle_interrupt = adin_phy_handle_interrupt,
1029 .get_sset_count = adin_get_sset_count,
1030 .get_strings = adin_get_strings,
1031 .get_stats = adin_get_stats,
1032 .resume = genphy_resume,
1033 .suspend = genphy_suspend,
1034 .read_mmd = adin_read_mmd,
1035 .write_mmd = adin_write_mmd,
1036 .cable_test_start = adin_cable_test_start,
1037 .cable_test_get_status = adin_cable_test_get_status,
1038 },
1039};
1040
1041module_phy_driver(adin_driver);
1042
1043static struct mdio_device_id __maybe_unused adin_tbl[] = {
1044 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
1045 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
1046 { }
1047};
1048
1049MODULE_DEVICE_TABLE(mdio, adin_tbl);
1050MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
1051MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Analog Devices Industrial Ethernet PHYs
4 *
5 * Copyright 2019 Analog Devices Inc.
6 */
7#include <linux/kernel.h>
8#include <linux/bitfield.h>
9#include <linux/delay.h>
10#include <linux/errno.h>
11#include <linux/ethtool_netlink.h>
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/mii.h>
15#include <linux/phy.h>
16#include <linux/property.h>
17
18#define PHY_ID_ADIN1200 0x0283bc20
19#define PHY_ID_ADIN1300 0x0283bc30
20
21#define ADIN1300_MII_EXT_REG_PTR 0x0010
22#define ADIN1300_MII_EXT_REG_DATA 0x0011
23
24#define ADIN1300_PHY_CTRL1 0x0012
25#define ADIN1300_AUTO_MDI_EN BIT(10)
26#define ADIN1300_MAN_MDIX_EN BIT(9)
27#define ADIN1300_DIAG_CLK_EN BIT(2)
28
29#define ADIN1300_RX_ERR_CNT 0x0014
30
31#define ADIN1300_PHY_CTRL_STATUS2 0x0015
32#define ADIN1300_NRG_PD_EN BIT(3)
33#define ADIN1300_NRG_PD_TX_EN BIT(2)
34#define ADIN1300_NRG_PD_STATUS BIT(1)
35
36#define ADIN1300_PHY_CTRL2 0x0016
37#define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
38#define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
39#define ADIN1300_GROUP_MDIO_EN BIT(6)
40#define ADIN1300_DOWNSPEEDS_EN \
41 (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
42
43#define ADIN1300_PHY_CTRL3 0x0017
44#define ADIN1300_LINKING_EN BIT(13)
45#define ADIN1300_DOWNSPEED_RETRIES_MSK GENMASK(12, 10)
46
47#define ADIN1300_INT_MASK_REG 0x0018
48#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
49#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
50#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
51#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
52#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
53#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
54#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
55#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
56#define ADIN1300_INT_HW_IRQ_EN BIT(0)
57#define ADIN1300_INT_MASK_EN \
58 (ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_HW_IRQ_EN)
59#define ADIN1300_INT_STATUS_REG 0x0019
60
61#define ADIN1300_PHY_STATUS1 0x001a
62#define ADIN1300_PAIR_01_SWAP BIT(11)
63
64/* EEE register addresses, accessible via Clause 22 access using
65 * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA.
66 * The bit-fields are the same as specified by IEEE for EEE.
67 */
68#define ADIN1300_EEE_CAP_REG 0x8000
69#define ADIN1300_EEE_ADV_REG 0x8001
70#define ADIN1300_EEE_LPABLE_REG 0x8002
71#define ADIN1300_CLOCK_STOP_REG 0x9400
72#define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
73
74#define ADIN1300_CDIAG_RUN 0xba1b
75#define ADIN1300_CDIAG_RUN_EN BIT(0)
76
77/*
78 * The XSIM3/2/1 and XSHRT3/2/1 are actually relative.
79 * For CDIAG_DTLD_RSLTS(0) it's ADIN1300_CDIAG_RSLT_XSIM3/2/1
80 * For CDIAG_DTLD_RSLTS(1) it's ADIN1300_CDIAG_RSLT_XSIM3/2/0
81 * For CDIAG_DTLD_RSLTS(2) it's ADIN1300_CDIAG_RSLT_XSIM3/1/0
82 * For CDIAG_DTLD_RSLTS(3) it's ADIN1300_CDIAG_RSLT_XSIM2/1/0
83 */
84#define ADIN1300_CDIAG_DTLD_RSLTS(x) (0xba1d + (x))
85#define ADIN1300_CDIAG_RSLT_BUSY BIT(10)
86#define ADIN1300_CDIAG_RSLT_XSIM3 BIT(9)
87#define ADIN1300_CDIAG_RSLT_XSIM2 BIT(8)
88#define ADIN1300_CDIAG_RSLT_XSIM1 BIT(7)
89#define ADIN1300_CDIAG_RSLT_SIM BIT(6)
90#define ADIN1300_CDIAG_RSLT_XSHRT3 BIT(5)
91#define ADIN1300_CDIAG_RSLT_XSHRT2 BIT(4)
92#define ADIN1300_CDIAG_RSLT_XSHRT1 BIT(3)
93#define ADIN1300_CDIAG_RSLT_SHRT BIT(2)
94#define ADIN1300_CDIAG_RSLT_OPEN BIT(1)
95#define ADIN1300_CDIAG_RSLT_GOOD BIT(0)
96
97#define ADIN1300_CDIAG_FLT_DIST(x) (0xba21 + (x))
98
99#define ADIN1300_GE_SOFT_RESET_REG 0xff0c
100#define ADIN1300_GE_SOFT_RESET BIT(0)
101
102#define ADIN1300_GE_CLK_CFG_REG 0xff1f
103#define ADIN1300_GE_CLK_CFG_MASK GENMASK(5, 0)
104#define ADIN1300_GE_CLK_CFG_RCVR_125 BIT(5)
105#define ADIN1300_GE_CLK_CFG_FREE_125 BIT(4)
106#define ADIN1300_GE_CLK_CFG_REF_EN BIT(3)
107#define ADIN1300_GE_CLK_CFG_HRT_RCVR BIT(2)
108#define ADIN1300_GE_CLK_CFG_HRT_FREE BIT(1)
109#define ADIN1300_GE_CLK_CFG_25 BIT(0)
110
111#define ADIN1300_GE_RGMII_CFG_REG 0xff23
112#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
113#define ADIN1300_GE_RGMII_RX_SEL(x) \
114 FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
115#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
116#define ADIN1300_GE_RGMII_GTX_SEL(x) \
117 FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
118#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
119#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
120#define ADIN1300_GE_RGMII_EN BIT(0)
121
122/* RGMII internal delay settings for rx and tx for ADIN1300 */
123#define ADIN1300_RGMII_1_60_NS 0x0001
124#define ADIN1300_RGMII_1_80_NS 0x0002
125#define ADIN1300_RGMII_2_00_NS 0x0000
126#define ADIN1300_RGMII_2_20_NS 0x0006
127#define ADIN1300_RGMII_2_40_NS 0x0007
128
129#define ADIN1300_GE_RMII_CFG_REG 0xff24
130#define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)
131#define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \
132 FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
133#define ADIN1300_GE_RMII_EN BIT(0)
134
135/* RMII fifo depth values */
136#define ADIN1300_RMII_4_BITS 0x0000
137#define ADIN1300_RMII_8_BITS 0x0001
138#define ADIN1300_RMII_12_BITS 0x0002
139#define ADIN1300_RMII_16_BITS 0x0003
140#define ADIN1300_RMII_20_BITS 0x0004
141#define ADIN1300_RMII_24_BITS 0x0005
142
143/**
144 * struct adin_cfg_reg_map - map a config value to aregister value
145 * @cfg: value in device configuration
146 * @reg: value in the register
147 */
148struct adin_cfg_reg_map {
149 int cfg;
150 int reg;
151};
152
153static const struct adin_cfg_reg_map adin_rgmii_delays[] = {
154 { 1600, ADIN1300_RGMII_1_60_NS },
155 { 1800, ADIN1300_RGMII_1_80_NS },
156 { 2000, ADIN1300_RGMII_2_00_NS },
157 { 2200, ADIN1300_RGMII_2_20_NS },
158 { 2400, ADIN1300_RGMII_2_40_NS },
159 { },
160};
161
162static const struct adin_cfg_reg_map adin_rmii_fifo_depths[] = {
163 { 4, ADIN1300_RMII_4_BITS },
164 { 8, ADIN1300_RMII_8_BITS },
165 { 12, ADIN1300_RMII_12_BITS },
166 { 16, ADIN1300_RMII_16_BITS },
167 { 20, ADIN1300_RMII_20_BITS },
168 { 24, ADIN1300_RMII_24_BITS },
169 { },
170};
171
172/**
173 * struct adin_clause45_mmd_map - map to convert Clause 45 regs to Clause 22
174 * @devad: device address used in Clause 45 access
175 * @cl45_regnum: register address defined by Clause 45
176 * @adin_regnum: equivalent register address accessible via Clause 22
177 */
178struct adin_clause45_mmd_map {
179 int devad;
180 u16 cl45_regnum;
181 u16 adin_regnum;
182};
183
184static const struct adin_clause45_mmd_map adin_clause45_mmd_map[] = {
185 { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
186 { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG },
187 { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG },
188 { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
189 { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
190};
191
192struct adin_hw_stat {
193 const char *string;
194 u16 reg1;
195 u16 reg2;
196};
197
198static const struct adin_hw_stat adin_hw_stats[] = {
199 { "total_frames_checked_count", 0x940A, 0x940B }, /* hi + lo */
200 { "length_error_frames_count", 0x940C },
201 { "alignment_error_frames_count", 0x940D },
202 { "symbol_error_count", 0x940E },
203 { "oversized_frames_count", 0x940F },
204 { "undersized_frames_count", 0x9410 },
205 { "odd_nibble_frames_count", 0x9411 },
206 { "odd_preamble_packet_count", 0x9412 },
207 { "dribble_bits_frames_count", 0x9413 },
208 { "false_carrier_events_count", 0x9414 },
209};
210
211/**
212 * struct adin_priv - ADIN PHY driver private data
213 * @stats: statistic counters for the PHY
214 */
215struct adin_priv {
216 u64 stats[ARRAY_SIZE(adin_hw_stats)];
217};
218
219static int adin_lookup_reg_value(const struct adin_cfg_reg_map *tbl, int cfg)
220{
221 size_t i;
222
223 for (i = 0; tbl[i].cfg; i++) {
224 if (tbl[i].cfg == cfg)
225 return tbl[i].reg;
226 }
227
228 return -EINVAL;
229}
230
231static u32 adin_get_reg_value(struct phy_device *phydev,
232 const char *prop_name,
233 const struct adin_cfg_reg_map *tbl,
234 u32 dflt)
235{
236 struct device *dev = &phydev->mdio.dev;
237 u32 val;
238 int rc;
239
240 if (device_property_read_u32(dev, prop_name, &val))
241 return dflt;
242
243 rc = adin_lookup_reg_value(tbl, val);
244 if (rc < 0) {
245 phydev_warn(phydev,
246 "Unsupported value %u for %s using default (%u)\n",
247 val, prop_name, dflt);
248 return dflt;
249 }
250
251 return rc;
252}
253
254static int adin_config_rgmii_mode(struct phy_device *phydev)
255{
256 u32 val;
257 int reg;
258
259 if (!phy_interface_is_rgmii(phydev))
260 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
261 ADIN1300_GE_RGMII_CFG_REG,
262 ADIN1300_GE_RGMII_EN);
263
264 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
265 if (reg < 0)
266 return reg;
267
268 reg |= ADIN1300_GE_RGMII_EN;
269
270 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
271 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
272 reg |= ADIN1300_GE_RGMII_RXID_EN;
273
274 val = adin_get_reg_value(phydev, "adi,rx-internal-delay-ps",
275 adin_rgmii_delays,
276 ADIN1300_RGMII_2_00_NS);
277 reg &= ~ADIN1300_GE_RGMII_RX_MSK;
278 reg |= ADIN1300_GE_RGMII_RX_SEL(val);
279 } else {
280 reg &= ~ADIN1300_GE_RGMII_RXID_EN;
281 }
282
283 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
284 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
285 reg |= ADIN1300_GE_RGMII_TXID_EN;
286
287 val = adin_get_reg_value(phydev, "adi,tx-internal-delay-ps",
288 adin_rgmii_delays,
289 ADIN1300_RGMII_2_00_NS);
290 reg &= ~ADIN1300_GE_RGMII_GTX_MSK;
291 reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
292 } else {
293 reg &= ~ADIN1300_GE_RGMII_TXID_EN;
294 }
295
296 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
297 ADIN1300_GE_RGMII_CFG_REG, reg);
298}
299
300static int adin_config_rmii_mode(struct phy_device *phydev)
301{
302 u32 val;
303 int reg;
304
305 if (phydev->interface != PHY_INTERFACE_MODE_RMII)
306 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
307 ADIN1300_GE_RMII_CFG_REG,
308 ADIN1300_GE_RMII_EN);
309
310 reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
311 if (reg < 0)
312 return reg;
313
314 reg |= ADIN1300_GE_RMII_EN;
315
316 val = adin_get_reg_value(phydev, "adi,fifo-depth-bits",
317 adin_rmii_fifo_depths,
318 ADIN1300_RMII_8_BITS);
319
320 reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK;
321 reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val);
322
323 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
324 ADIN1300_GE_RMII_CFG_REG, reg);
325}
326
327static int adin_get_downshift(struct phy_device *phydev, u8 *data)
328{
329 int val, cnt, enable;
330
331 val = phy_read(phydev, ADIN1300_PHY_CTRL2);
332 if (val < 0)
333 return val;
334
335 cnt = phy_read(phydev, ADIN1300_PHY_CTRL3);
336 if (cnt < 0)
337 return cnt;
338
339 enable = FIELD_GET(ADIN1300_DOWNSPEEDS_EN, val);
340 cnt = FIELD_GET(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
341
342 *data = (enable && cnt) ? cnt : DOWNSHIFT_DEV_DISABLE;
343
344 return 0;
345}
346
347static int adin_set_downshift(struct phy_device *phydev, u8 cnt)
348{
349 u16 val;
350 int rc;
351
352 if (cnt == DOWNSHIFT_DEV_DISABLE)
353 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL2,
354 ADIN1300_DOWNSPEEDS_EN);
355
356 if (cnt > 7)
357 return -E2BIG;
358
359 val = FIELD_PREP(ADIN1300_DOWNSPEED_RETRIES_MSK, cnt);
360
361 rc = phy_modify(phydev, ADIN1300_PHY_CTRL3,
362 ADIN1300_DOWNSPEED_RETRIES_MSK,
363 val);
364 if (rc < 0)
365 return rc;
366
367 return phy_set_bits(phydev, ADIN1300_PHY_CTRL2,
368 ADIN1300_DOWNSPEEDS_EN);
369}
370
371static int adin_get_edpd(struct phy_device *phydev, u16 *tx_interval)
372{
373 int val;
374
375 val = phy_read(phydev, ADIN1300_PHY_CTRL_STATUS2);
376 if (val < 0)
377 return val;
378
379 if (ADIN1300_NRG_PD_EN & val) {
380 if (val & ADIN1300_NRG_PD_TX_EN)
381 /* default is 1 second */
382 *tx_interval = ETHTOOL_PHY_EDPD_DFLT_TX_MSECS;
383 else
384 *tx_interval = ETHTOOL_PHY_EDPD_NO_TX;
385 } else {
386 *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
387 }
388
389 return 0;
390}
391
392static int adin_set_edpd(struct phy_device *phydev, u16 tx_interval)
393{
394 u16 val;
395
396 if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
397 return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
398 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN));
399
400 val = ADIN1300_NRG_PD_EN;
401
402 switch (tx_interval) {
403 case 1000: /* 1 second */
404 fallthrough;
405 case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
406 val |= ADIN1300_NRG_PD_TX_EN;
407 fallthrough;
408 case ETHTOOL_PHY_EDPD_NO_TX:
409 break;
410 default:
411 return -EINVAL;
412 }
413
414 return phy_modify(phydev, ADIN1300_PHY_CTRL_STATUS2,
415 (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN),
416 val);
417}
418
419static int adin_get_tunable(struct phy_device *phydev,
420 struct ethtool_tunable *tuna, void *data)
421{
422 switch (tuna->id) {
423 case ETHTOOL_PHY_DOWNSHIFT:
424 return adin_get_downshift(phydev, data);
425 case ETHTOOL_PHY_EDPD:
426 return adin_get_edpd(phydev, data);
427 default:
428 return -EOPNOTSUPP;
429 }
430}
431
432static int adin_set_tunable(struct phy_device *phydev,
433 struct ethtool_tunable *tuna, const void *data)
434{
435 switch (tuna->id) {
436 case ETHTOOL_PHY_DOWNSHIFT:
437 return adin_set_downshift(phydev, *(const u8 *)data);
438 case ETHTOOL_PHY_EDPD:
439 return adin_set_edpd(phydev, *(const u16 *)data);
440 default:
441 return -EOPNOTSUPP;
442 }
443}
444
445static int adin_config_clk_out(struct phy_device *phydev)
446{
447 struct device *dev = &phydev->mdio.dev;
448 const char *val = NULL;
449 u8 sel = 0;
450
451 device_property_read_string(dev, "adi,phy-output-clock", &val);
452 if (!val) {
453 /* property not present, do not enable GP_CLK pin */
454 } else if (strcmp(val, "25mhz-reference") == 0) {
455 sel |= ADIN1300_GE_CLK_CFG_25;
456 } else if (strcmp(val, "125mhz-free-running") == 0) {
457 sel |= ADIN1300_GE_CLK_CFG_FREE_125;
458 } else if (strcmp(val, "adaptive-free-running") == 0) {
459 sel |= ADIN1300_GE_CLK_CFG_HRT_FREE;
460 } else {
461 phydev_err(phydev, "invalid adi,phy-output-clock\n");
462 return -EINVAL;
463 }
464
465 if (device_property_read_bool(dev, "adi,phy-output-reference-clock"))
466 sel |= ADIN1300_GE_CLK_CFG_REF_EN;
467
468 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG,
469 ADIN1300_GE_CLK_CFG_MASK, sel);
470}
471
472static int adin_config_init(struct phy_device *phydev)
473{
474 int rc;
475
476 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
477
478 rc = adin_config_rgmii_mode(phydev);
479 if (rc < 0)
480 return rc;
481
482 rc = adin_config_rmii_mode(phydev);
483 if (rc < 0)
484 return rc;
485
486 rc = adin_set_downshift(phydev, 4);
487 if (rc < 0)
488 return rc;
489
490 rc = adin_set_edpd(phydev, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS);
491 if (rc < 0)
492 return rc;
493
494 rc = adin_config_clk_out(phydev);
495 if (rc < 0)
496 return rc;
497
498 phydev_dbg(phydev, "PHY is using mode '%s'\n",
499 phy_modes(phydev->interface));
500
501 return 0;
502}
503
504static int adin_phy_ack_intr(struct phy_device *phydev)
505{
506 /* Clear pending interrupts */
507 int rc = phy_read(phydev, ADIN1300_INT_STATUS_REG);
508
509 return rc < 0 ? rc : 0;
510}
511
512static int adin_phy_config_intr(struct phy_device *phydev)
513{
514 int err;
515
516 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
517 err = adin_phy_ack_intr(phydev);
518 if (err)
519 return err;
520
521 err = phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
522 ADIN1300_INT_MASK_EN);
523 } else {
524 err = phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
525 ADIN1300_INT_MASK_EN);
526 if (err)
527 return err;
528
529 err = adin_phy_ack_intr(phydev);
530 }
531
532 return err;
533}
534
535static irqreturn_t adin_phy_handle_interrupt(struct phy_device *phydev)
536{
537 int irq_status;
538
539 irq_status = phy_read(phydev, ADIN1300_INT_STATUS_REG);
540 if (irq_status < 0) {
541 phy_error(phydev);
542 return IRQ_NONE;
543 }
544
545 if (!(irq_status & ADIN1300_INT_LINK_STAT_CHNG_EN))
546 return IRQ_NONE;
547
548 phy_trigger_machine(phydev);
549
550 return IRQ_HANDLED;
551}
552
553static int adin_cl45_to_adin_reg(struct phy_device *phydev, int devad,
554 u16 cl45_regnum)
555{
556 const struct adin_clause45_mmd_map *m;
557 int i;
558
559 if (devad == MDIO_MMD_VEND1)
560 return cl45_regnum;
561
562 for (i = 0; i < ARRAY_SIZE(adin_clause45_mmd_map); i++) {
563 m = &adin_clause45_mmd_map[i];
564 if (m->devad == devad && m->cl45_regnum == cl45_regnum)
565 return m->adin_regnum;
566 }
567
568 phydev_err(phydev,
569 "No translation available for devad: %d reg: %04x\n",
570 devad, cl45_regnum);
571
572 return -EINVAL;
573}
574
575static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
576{
577 struct mii_bus *bus = phydev->mdio.bus;
578 int phy_addr = phydev->mdio.addr;
579 int adin_regnum;
580 int err;
581
582 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
583 if (adin_regnum < 0)
584 return adin_regnum;
585
586 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
587 adin_regnum);
588 if (err)
589 return err;
590
591 return __mdiobus_read(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA);
592}
593
594static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
595 u16 val)
596{
597 struct mii_bus *bus = phydev->mdio.bus;
598 int phy_addr = phydev->mdio.addr;
599 int adin_regnum;
600 int err;
601
602 adin_regnum = adin_cl45_to_adin_reg(phydev, devad, regnum);
603 if (adin_regnum < 0)
604 return adin_regnum;
605
606 err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
607 adin_regnum);
608 if (err)
609 return err;
610
611 return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
612}
613
614static int adin_config_mdix(struct phy_device *phydev)
615{
616 bool auto_en, mdix_en;
617 int reg;
618
619 mdix_en = false;
620 auto_en = false;
621 switch (phydev->mdix_ctrl) {
622 case ETH_TP_MDI:
623 break;
624 case ETH_TP_MDI_X:
625 mdix_en = true;
626 break;
627 case ETH_TP_MDI_AUTO:
628 auto_en = true;
629 break;
630 default:
631 return -EINVAL;
632 }
633
634 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
635 if (reg < 0)
636 return reg;
637
638 if (mdix_en)
639 reg |= ADIN1300_MAN_MDIX_EN;
640 else
641 reg &= ~ADIN1300_MAN_MDIX_EN;
642
643 if (auto_en)
644 reg |= ADIN1300_AUTO_MDI_EN;
645 else
646 reg &= ~ADIN1300_AUTO_MDI_EN;
647
648 return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
649}
650
651static int adin_config_aneg(struct phy_device *phydev)
652{
653 int ret;
654
655 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
656 if (ret < 0)
657 return ret;
658
659 ret = phy_set_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
660 if (ret < 0)
661 return ret;
662
663 ret = adin_config_mdix(phydev);
664 if (ret)
665 return ret;
666
667 return genphy_config_aneg(phydev);
668}
669
670static int adin_mdix_update(struct phy_device *phydev)
671{
672 bool auto_en, mdix_en;
673 bool swapped;
674 int reg;
675
676 reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
677 if (reg < 0)
678 return reg;
679
680 auto_en = !!(reg & ADIN1300_AUTO_MDI_EN);
681 mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN);
682
683 /* If MDI/MDIX is forced, just read it from the control reg */
684 if (!auto_en) {
685 if (mdix_en)
686 phydev->mdix = ETH_TP_MDI_X;
687 else
688 phydev->mdix = ETH_TP_MDI;
689 return 0;
690 }
691
692 /**
693 * Otherwise, we need to deduce it from the PHY status2 reg.
694 * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies
695 * a preference for MDIX when it is set.
696 */
697 reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
698 if (reg < 0)
699 return reg;
700
701 swapped = !!(reg & ADIN1300_PAIR_01_SWAP);
702
703 if (mdix_en != swapped)
704 phydev->mdix = ETH_TP_MDI_X;
705 else
706 phydev->mdix = ETH_TP_MDI;
707
708 return 0;
709}
710
711static int adin_read_status(struct phy_device *phydev)
712{
713 int ret;
714
715 ret = adin_mdix_update(phydev);
716 if (ret < 0)
717 return ret;
718
719 return genphy_read_status(phydev);
720}
721
722static int adin_soft_reset(struct phy_device *phydev)
723{
724 int rc;
725
726 /* The reset bit is self-clearing, set it and wait */
727 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
728 ADIN1300_GE_SOFT_RESET_REG,
729 ADIN1300_GE_SOFT_RESET);
730 if (rc < 0)
731 return rc;
732
733 msleep(20);
734
735 /* If we get a read error something may be wrong */
736 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
737 ADIN1300_GE_SOFT_RESET_REG);
738
739 return rc < 0 ? rc : 0;
740}
741
742static int adin_get_sset_count(struct phy_device *phydev)
743{
744 return ARRAY_SIZE(adin_hw_stats);
745}
746
747static void adin_get_strings(struct phy_device *phydev, u8 *data)
748{
749 int i;
750
751 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
752 strscpy(&data[i * ETH_GSTRING_LEN],
753 adin_hw_stats[i].string, ETH_GSTRING_LEN);
754 }
755}
756
757static int adin_read_mmd_stat_regs(struct phy_device *phydev,
758 const struct adin_hw_stat *stat,
759 u32 *val)
760{
761 int ret;
762
763 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
764 if (ret < 0)
765 return ret;
766
767 *val = (ret & 0xffff);
768
769 if (stat->reg2 == 0)
770 return 0;
771
772 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
773 if (ret < 0)
774 return ret;
775
776 *val <<= 16;
777 *val |= (ret & 0xffff);
778
779 return 0;
780}
781
782static u64 adin_get_stat(struct phy_device *phydev, int i)
783{
784 const struct adin_hw_stat *stat = &adin_hw_stats[i];
785 struct adin_priv *priv = phydev->priv;
786 u32 val;
787 int ret;
788
789 if (stat->reg1 > 0x1f) {
790 ret = adin_read_mmd_stat_regs(phydev, stat, &val);
791 if (ret < 0)
792 return (u64)(~0);
793 } else {
794 ret = phy_read(phydev, stat->reg1);
795 if (ret < 0)
796 return (u64)(~0);
797 val = (ret & 0xffff);
798 }
799
800 priv->stats[i] += val;
801
802 return priv->stats[i];
803}
804
805static void adin_get_stats(struct phy_device *phydev,
806 struct ethtool_stats *stats, u64 *data)
807{
808 int i, rc;
809
810 /* latch copies of all the frame-checker counters */
811 rc = phy_read(phydev, ADIN1300_RX_ERR_CNT);
812 if (rc < 0)
813 return;
814
815 for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
816 data[i] = adin_get_stat(phydev, i);
817}
818
819static int adin_probe(struct phy_device *phydev)
820{
821 struct device *dev = &phydev->mdio.dev;
822 struct adin_priv *priv;
823
824 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
825 if (!priv)
826 return -ENOMEM;
827
828 phydev->priv = priv;
829
830 return 0;
831}
832
833static int adin_cable_test_start(struct phy_device *phydev)
834{
835 int ret;
836
837 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL3, ADIN1300_LINKING_EN);
838 if (ret < 0)
839 return ret;
840
841 ret = phy_clear_bits(phydev, ADIN1300_PHY_CTRL1, ADIN1300_DIAG_CLK_EN);
842 if (ret < 0)
843 return ret;
844
845 /* wait a bit for the clock to stabilize */
846 msleep(50);
847
848 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN,
849 ADIN1300_CDIAG_RUN_EN);
850}
851
852static int adin_cable_test_report_trans(int result)
853{
854 int mask;
855
856 if (result & ADIN1300_CDIAG_RSLT_GOOD)
857 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
858 if (result & ADIN1300_CDIAG_RSLT_OPEN)
859 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
860
861 /* short with other pairs */
862 mask = ADIN1300_CDIAG_RSLT_XSHRT3 |
863 ADIN1300_CDIAG_RSLT_XSHRT2 |
864 ADIN1300_CDIAG_RSLT_XSHRT1;
865 if (result & mask)
866 return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
867
868 if (result & ADIN1300_CDIAG_RSLT_SHRT)
869 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
870
871 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
872}
873
874static int adin_cable_test_report_pair(struct phy_device *phydev,
875 unsigned int pair)
876{
877 int fault_rslt;
878 int ret;
879
880 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
881 ADIN1300_CDIAG_DTLD_RSLTS(pair));
882 if (ret < 0)
883 return ret;
884
885 fault_rslt = adin_cable_test_report_trans(ret);
886
887 ret = ethnl_cable_test_result(phydev, pair, fault_rslt);
888 if (ret < 0)
889 return ret;
890
891 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1,
892 ADIN1300_CDIAG_FLT_DIST(pair));
893 if (ret < 0)
894 return ret;
895
896 switch (fault_rslt) {
897 case ETHTOOL_A_CABLE_RESULT_CODE_OPEN:
898 case ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT:
899 case ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT:
900 return ethnl_cable_test_fault_length(phydev, pair, ret * 100);
901 default:
902 return 0;
903 }
904}
905
906static int adin_cable_test_report(struct phy_device *phydev)
907{
908 unsigned int pair;
909 int ret;
910
911 for (pair = ETHTOOL_A_CABLE_PAIR_A; pair <= ETHTOOL_A_CABLE_PAIR_D; pair++) {
912 ret = adin_cable_test_report_pair(phydev, pair);
913 if (ret < 0)
914 return ret;
915 }
916
917 return 0;
918}
919
920static int adin_cable_test_get_status(struct phy_device *phydev,
921 bool *finished)
922{
923 int ret;
924
925 *finished = false;
926
927 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_CDIAG_RUN);
928 if (ret < 0)
929 return ret;
930
931 if (ret & ADIN1300_CDIAG_RUN_EN)
932 return 0;
933
934 *finished = true;
935
936 return adin_cable_test_report(phydev);
937}
938
939static struct phy_driver adin_driver[] = {
940 {
941 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200),
942 .name = "ADIN1200",
943 .flags = PHY_POLL_CABLE_TEST,
944 .probe = adin_probe,
945 .config_init = adin_config_init,
946 .soft_reset = adin_soft_reset,
947 .config_aneg = adin_config_aneg,
948 .read_status = adin_read_status,
949 .get_tunable = adin_get_tunable,
950 .set_tunable = adin_set_tunable,
951 .config_intr = adin_phy_config_intr,
952 .handle_interrupt = adin_phy_handle_interrupt,
953 .get_sset_count = adin_get_sset_count,
954 .get_strings = adin_get_strings,
955 .get_stats = adin_get_stats,
956 .resume = genphy_resume,
957 .suspend = genphy_suspend,
958 .read_mmd = adin_read_mmd,
959 .write_mmd = adin_write_mmd,
960 .cable_test_start = adin_cable_test_start,
961 .cable_test_get_status = adin_cable_test_get_status,
962 },
963 {
964 PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300),
965 .name = "ADIN1300",
966 .flags = PHY_POLL_CABLE_TEST,
967 .probe = adin_probe,
968 .config_init = adin_config_init,
969 .soft_reset = adin_soft_reset,
970 .config_aneg = adin_config_aneg,
971 .read_status = adin_read_status,
972 .get_tunable = adin_get_tunable,
973 .set_tunable = adin_set_tunable,
974 .config_intr = adin_phy_config_intr,
975 .handle_interrupt = adin_phy_handle_interrupt,
976 .get_sset_count = adin_get_sset_count,
977 .get_strings = adin_get_strings,
978 .get_stats = adin_get_stats,
979 .resume = genphy_resume,
980 .suspend = genphy_suspend,
981 .read_mmd = adin_read_mmd,
982 .write_mmd = adin_write_mmd,
983 .cable_test_start = adin_cable_test_start,
984 .cable_test_get_status = adin_cable_test_get_status,
985 },
986};
987
988module_phy_driver(adin_driver);
989
990static struct mdio_device_id __maybe_unused adin_tbl[] = {
991 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1200) },
992 { PHY_ID_MATCH_MODEL(PHY_ID_ADIN1300) },
993 { }
994};
995
996MODULE_DEVICE_TABLE(mdio, adin_tbl);
997MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
998MODULE_LICENSE("GPL");