Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/cpu.h>
8#include <linux/cpufreq.h>
9#include <linux/err.h>
10#include <linux/module.h>
11#include <linux/nvmem-consumer.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/pm_opp.h>
15#include <linux/platform_device.h>
16#include <linux/regulator/consumer.h>
17
18#define PU_SOC_VOLTAGE_NORMAL 1250000
19#define PU_SOC_VOLTAGE_HIGH 1275000
20#define FREQ_1P2_GHZ 1200000000
21
22static struct regulator *arm_reg;
23static struct regulator *pu_reg;
24static struct regulator *soc_reg;
25
26enum IMX6_CPUFREQ_CLKS {
27 ARM,
28 PLL1_SYS,
29 STEP,
30 PLL1_SW,
31 PLL2_PFD2_396M,
32 /* MX6UL requires two more clks */
33 PLL2_BUS,
34 SECONDARY_SEL,
35};
36#define IMX6Q_CPUFREQ_CLK_NUM 5
37#define IMX6UL_CPUFREQ_CLK_NUM 7
38
39static int num_clks;
40static struct clk_bulk_data clks[] = {
41 { .id = "arm" },
42 { .id = "pll1_sys" },
43 { .id = "step" },
44 { .id = "pll1_sw" },
45 { .id = "pll2_pfd2_396m" },
46 { .id = "pll2_bus" },
47 { .id = "secondary_sel" },
48};
49
50static struct device *cpu_dev;
51static struct cpufreq_frequency_table *freq_table;
52static unsigned int max_freq;
53static unsigned int transition_latency;
54
55static u32 *imx6_soc_volt;
56static u32 soc_opp_count;
57
58static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
59{
60 struct dev_pm_opp *opp;
61 unsigned long freq_hz, volt, volt_old;
62 unsigned int old_freq, new_freq;
63 bool pll1_sys_temp_enabled = false;
64 int ret;
65
66 new_freq = freq_table[index].frequency;
67 freq_hz = new_freq * 1000;
68 old_freq = clk_get_rate(clks[ARM].clk) / 1000;
69
70 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
71 if (IS_ERR(opp)) {
72 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
73 return PTR_ERR(opp);
74 }
75
76 volt = dev_pm_opp_get_voltage(opp);
77 dev_pm_opp_put(opp);
78
79 volt_old = regulator_get_voltage(arm_reg);
80
81 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
82 old_freq / 1000, volt_old / 1000,
83 new_freq / 1000, volt / 1000);
84
85 /* scaling up? scale voltage before frequency */
86 if (new_freq > old_freq) {
87 if (!IS_ERR(pu_reg)) {
88 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
89 if (ret) {
90 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
91 return ret;
92 }
93 }
94 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
95 if (ret) {
96 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
97 return ret;
98 }
99 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
100 if (ret) {
101 dev_err(cpu_dev,
102 "failed to scale vddarm up: %d\n", ret);
103 return ret;
104 }
105 }
106
107 /*
108 * The setpoints are selected per PLL/PDF frequencies, so we need to
109 * reprogram PLL for frequency scaling. The procedure of reprogramming
110 * PLL1 is as below.
111 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
112 * flow is slightly different from other i.MX6 OSC.
113 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
114 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
115 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
116 * - Disable pll2_pfd2_396m_clk
117 */
118 if (of_machine_is_compatible("fsl,imx6ul") ||
119 of_machine_is_compatible("fsl,imx6ull")) {
120 /*
121 * When changing pll1_sw_clk's parent to pll1_sys_clk,
122 * CPU may run at higher than 528MHz, this will lead to
123 * the system unstable if the voltage is lower than the
124 * voltage of 528MHz, so lower the CPU frequency to one
125 * half before changing CPU frequency.
126 */
127 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
128 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
129 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
130 clk_set_parent(clks[SECONDARY_SEL].clk,
131 clks[PLL2_BUS].clk);
132 else
133 clk_set_parent(clks[SECONDARY_SEL].clk,
134 clks[PLL2_PFD2_396M].clk);
135 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
136 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
137 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
138 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
139 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
140 }
141 } else {
142 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
143 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
144 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
145 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
146 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
147 } else {
148 /* pll1_sys needs to be enabled for divider rate change to work. */
149 pll1_sys_temp_enabled = true;
150 clk_prepare_enable(clks[PLL1_SYS].clk);
151 }
152 }
153
154 /* Ensure the arm clock divider is what we expect */
155 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
156 if (ret) {
157 int ret1;
158
159 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
160 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
161 if (ret1)
162 dev_warn(cpu_dev,
163 "failed to restore vddarm voltage: %d\n", ret1);
164 return ret;
165 }
166
167 /* PLL1 is only needed until after ARM-PODF is set. */
168 if (pll1_sys_temp_enabled)
169 clk_disable_unprepare(clks[PLL1_SYS].clk);
170
171 /* scaling down? scale voltage after frequency */
172 if (new_freq < old_freq) {
173 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
174 if (ret)
175 dev_warn(cpu_dev,
176 "failed to scale vddarm down: %d\n", ret);
177 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
178 if (ret)
179 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
180 if (!IS_ERR(pu_reg)) {
181 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
182 if (ret)
183 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
184 }
185 }
186
187 return 0;
188}
189
190static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
191{
192 policy->clk = clks[ARM].clk;
193 cpufreq_generic_init(policy, freq_table, transition_latency);
194 policy->suspend_freq = max_freq;
195
196 return 0;
197}
198
199static struct cpufreq_driver imx6q_cpufreq_driver = {
200 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
201 CPUFREQ_IS_COOLING_DEV,
202 .verify = cpufreq_generic_frequency_table_verify,
203 .target_index = imx6q_set_target,
204 .get = cpufreq_generic_get,
205 .init = imx6q_cpufreq_init,
206 .register_em = cpufreq_register_em_with_opp,
207 .name = "imx6q-cpufreq",
208 .attr = cpufreq_generic_attr,
209 .suspend = cpufreq_generic_suspend,
210};
211
212static void imx6x_disable_freq_in_opp(struct device *dev, unsigned long freq)
213{
214 int ret = dev_pm_opp_disable(dev, freq);
215
216 if (ret < 0 && ret != -ENODEV)
217 dev_warn(dev, "failed to disable %ldMHz OPP\n", freq / 1000000);
218}
219
220#define OCOTP_CFG3 0x440
221#define OCOTP_CFG3_SPEED_SHIFT 16
222#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
223#define OCOTP_CFG3_SPEED_996MHZ 0x2
224#define OCOTP_CFG3_SPEED_852MHZ 0x1
225
226static int imx6q_opp_check_speed_grading(struct device *dev)
227{
228 struct device_node *np;
229 void __iomem *base;
230 u32 val;
231 int ret;
232
233 if (of_property_present(dev->of_node, "nvmem-cells")) {
234 ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
235 if (ret)
236 return ret;
237 } else {
238 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
239 if (!np)
240 return -ENOENT;
241
242 base = of_iomap(np, 0);
243 of_node_put(np);
244 if (!base) {
245 dev_err(dev, "failed to map ocotp\n");
246 return -EFAULT;
247 }
248
249 /*
250 * SPEED_GRADING[1:0] defines the max speed of ARM:
251 * 2b'11: 1200000000Hz;
252 * 2b'10: 996000000Hz;
253 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
254 * 2b'00: 792000000Hz;
255 * We need to set the max speed of ARM according to fuse map.
256 */
257 val = readl_relaxed(base + OCOTP_CFG3);
258 iounmap(base);
259 }
260
261 val >>= OCOTP_CFG3_SPEED_SHIFT;
262 val &= 0x3;
263
264 if (val < OCOTP_CFG3_SPEED_996MHZ)
265 imx6x_disable_freq_in_opp(dev, 996000000);
266
267 if (of_machine_is_compatible("fsl,imx6q") ||
268 of_machine_is_compatible("fsl,imx6qp")) {
269 if (val != OCOTP_CFG3_SPEED_852MHZ)
270 imx6x_disable_freq_in_opp(dev, 852000000);
271
272 if (val != OCOTP_CFG3_SPEED_1P2GHZ)
273 imx6x_disable_freq_in_opp(dev, 1200000000);
274 }
275
276 return 0;
277}
278
279#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
280#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
281#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
282
283static int imx6ul_opp_check_speed_grading(struct device *dev)
284{
285 u32 val;
286 int ret = 0;
287
288 if (of_property_present(dev->of_node, "nvmem-cells")) {
289 ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
290 if (ret)
291 return ret;
292 } else {
293 struct device_node *np;
294 void __iomem *base;
295
296 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
297 if (!np)
298 np = of_find_compatible_node(NULL, NULL,
299 "fsl,imx6ull-ocotp");
300 if (!np)
301 return -ENOENT;
302
303 base = of_iomap(np, 0);
304 of_node_put(np);
305 if (!base) {
306 dev_err(dev, "failed to map ocotp\n");
307 return -EFAULT;
308 }
309
310 val = readl_relaxed(base + OCOTP_CFG3);
311 iounmap(base);
312 }
313
314 /*
315 * Speed GRADING[1:0] defines the max speed of ARM:
316 * 2b'00: Reserved;
317 * 2b'01: 528000000Hz;
318 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
319 * 2b'11: 900000000Hz on i.MX6ULL only;
320 * We need to set the max speed of ARM according to fuse map.
321 */
322 val >>= OCOTP_CFG3_SPEED_SHIFT;
323 val &= 0x3;
324
325 if (of_machine_is_compatible("fsl,imx6ul"))
326 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
327 imx6x_disable_freq_in_opp(dev, 696000000);
328
329 if (of_machine_is_compatible("fsl,imx6ull")) {
330 if (val < OCOTP_CFG3_6ULL_SPEED_792MHZ)
331 imx6x_disable_freq_in_opp(dev, 792000000);
332
333 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
334 imx6x_disable_freq_in_opp(dev, 900000000);
335 }
336
337 return ret;
338}
339
340static int imx6q_cpufreq_probe(struct platform_device *pdev)
341{
342 struct device_node *np;
343 struct dev_pm_opp *opp;
344 unsigned long min_volt, max_volt;
345 int num, ret;
346 const struct property *prop;
347 const __be32 *val;
348 u32 nr, i, j;
349
350 cpu_dev = get_cpu_device(0);
351 if (!cpu_dev) {
352 pr_err("failed to get cpu0 device\n");
353 return -ENODEV;
354 }
355
356 np = of_node_get(cpu_dev->of_node);
357 if (!np) {
358 dev_err(cpu_dev, "failed to find cpu0 node\n");
359 return -ENOENT;
360 }
361
362 if (of_machine_is_compatible("fsl,imx6ul") ||
363 of_machine_is_compatible("fsl,imx6ull"))
364 num_clks = IMX6UL_CPUFREQ_CLK_NUM;
365 else
366 num_clks = IMX6Q_CPUFREQ_CLK_NUM;
367
368 ret = clk_bulk_get(cpu_dev, num_clks, clks);
369 if (ret)
370 goto put_node;
371
372 arm_reg = regulator_get(cpu_dev, "arm");
373 pu_reg = regulator_get_optional(cpu_dev, "pu");
374 soc_reg = regulator_get(cpu_dev, "soc");
375 if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
376 PTR_ERR(soc_reg) == -EPROBE_DEFER ||
377 PTR_ERR(pu_reg) == -EPROBE_DEFER) {
378 ret = -EPROBE_DEFER;
379 dev_dbg(cpu_dev, "regulators not ready, defer\n");
380 goto put_reg;
381 }
382 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
383 dev_err(cpu_dev, "failed to get regulators\n");
384 ret = -ENOENT;
385 goto put_reg;
386 }
387
388 ret = dev_pm_opp_of_add_table(cpu_dev);
389 if (ret < 0) {
390 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
391 goto put_reg;
392 }
393
394 if (of_machine_is_compatible("fsl,imx6ul") ||
395 of_machine_is_compatible("fsl,imx6ull")) {
396 ret = imx6ul_opp_check_speed_grading(cpu_dev);
397 } else {
398 ret = imx6q_opp_check_speed_grading(cpu_dev);
399 }
400 if (ret) {
401 dev_err_probe(cpu_dev, ret, "failed to read ocotp\n");
402 goto out_free_opp;
403 }
404
405 num = dev_pm_opp_get_opp_count(cpu_dev);
406 if (num < 0) {
407 ret = num;
408 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
409 goto out_free_opp;
410 }
411
412 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
413 if (ret) {
414 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
415 goto out_free_opp;
416 }
417
418 /* Make imx6_soc_volt array's size same as arm opp number */
419 imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
420 GFP_KERNEL);
421 if (imx6_soc_volt == NULL) {
422 ret = -ENOMEM;
423 goto free_freq_table;
424 }
425
426 prop = of_find_property(np, "fsl,soc-operating-points", NULL);
427 if (!prop || !prop->value)
428 goto soc_opp_out;
429
430 /*
431 * Each OPP is a set of tuples consisting of frequency and
432 * voltage like <freq-kHz vol-uV>.
433 */
434 nr = prop->length / sizeof(u32);
435 if (nr % 2 || (nr / 2) < num)
436 goto soc_opp_out;
437
438 for (j = 0; j < num; j++) {
439 val = prop->value;
440 for (i = 0; i < nr / 2; i++) {
441 unsigned long freq = be32_to_cpup(val++);
442 unsigned long volt = be32_to_cpup(val++);
443 if (freq_table[j].frequency == freq) {
444 imx6_soc_volt[soc_opp_count++] = volt;
445 break;
446 }
447 }
448 }
449
450soc_opp_out:
451 /* use fixed soc opp volt if no valid soc opp info found in dtb */
452 if (soc_opp_count != num) {
453 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
454 for (j = 0; j < num; j++)
455 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
456 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
457 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
458 }
459
460 if (of_property_read_u32(np, "clock-latency", &transition_latency))
461 transition_latency = CPUFREQ_ETERNAL;
462
463 /*
464 * Calculate the ramp time for max voltage change in the
465 * VDDSOC and VDDPU regulators.
466 */
467 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
468 if (ret > 0)
469 transition_latency += ret * 1000;
470 if (!IS_ERR(pu_reg)) {
471 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
472 if (ret > 0)
473 transition_latency += ret * 1000;
474 }
475
476 /*
477 * OPP is maintained in order of increasing frequency, and
478 * freq_table initialised from OPP is therefore sorted in the
479 * same order.
480 */
481 max_freq = freq_table[--num].frequency;
482 opp = dev_pm_opp_find_freq_exact(cpu_dev,
483 freq_table[0].frequency * 1000, true);
484 min_volt = dev_pm_opp_get_voltage(opp);
485 dev_pm_opp_put(opp);
486 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
487 max_volt = dev_pm_opp_get_voltage(opp);
488 dev_pm_opp_put(opp);
489
490 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
491 if (ret > 0)
492 transition_latency += ret * 1000;
493
494 ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
495 if (ret) {
496 dev_err(cpu_dev, "failed register driver: %d\n", ret);
497 goto free_freq_table;
498 }
499
500 of_node_put(np);
501 return 0;
502
503free_freq_table:
504 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
505out_free_opp:
506 dev_pm_opp_of_remove_table(cpu_dev);
507put_reg:
508 if (!IS_ERR(arm_reg))
509 regulator_put(arm_reg);
510 if (!IS_ERR(pu_reg))
511 regulator_put(pu_reg);
512 if (!IS_ERR(soc_reg))
513 regulator_put(soc_reg);
514
515 clk_bulk_put(num_clks, clks);
516put_node:
517 of_node_put(np);
518
519 return ret;
520}
521
522static void imx6q_cpufreq_remove(struct platform_device *pdev)
523{
524 cpufreq_unregister_driver(&imx6q_cpufreq_driver);
525 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
526 dev_pm_opp_of_remove_table(cpu_dev);
527 regulator_put(arm_reg);
528 if (!IS_ERR(pu_reg))
529 regulator_put(pu_reg);
530 regulator_put(soc_reg);
531
532 clk_bulk_put(num_clks, clks);
533}
534
535static struct platform_driver imx6q_cpufreq_platdrv = {
536 .driver = {
537 .name = "imx6q-cpufreq",
538 },
539 .probe = imx6q_cpufreq_probe,
540 .remove_new = imx6q_cpufreq_remove,
541};
542module_platform_driver(imx6q_cpufreq_platdrv);
543
544MODULE_ALIAS("platform:imx6q-cpufreq");
545MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
546MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
547MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Freescale Semiconductor, Inc.
4 */
5
6#include <linux/clk.h>
7#include <linux/cpu.h>
8#include <linux/cpufreq.h>
9#include <linux/err.h>
10#include <linux/module.h>
11#include <linux/nvmem-consumer.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/pm_opp.h>
15#include <linux/platform_device.h>
16#include <linux/regulator/consumer.h>
17
18#define PU_SOC_VOLTAGE_NORMAL 1250000
19#define PU_SOC_VOLTAGE_HIGH 1275000
20#define FREQ_1P2_GHZ 1200000000
21
22static struct regulator *arm_reg;
23static struct regulator *pu_reg;
24static struct regulator *soc_reg;
25
26enum IMX6_CPUFREQ_CLKS {
27 ARM,
28 PLL1_SYS,
29 STEP,
30 PLL1_SW,
31 PLL2_PFD2_396M,
32 /* MX6UL requires two more clks */
33 PLL2_BUS,
34 SECONDARY_SEL,
35};
36#define IMX6Q_CPUFREQ_CLK_NUM 5
37#define IMX6UL_CPUFREQ_CLK_NUM 7
38
39static int num_clks;
40static struct clk_bulk_data clks[] = {
41 { .id = "arm" },
42 { .id = "pll1_sys" },
43 { .id = "step" },
44 { .id = "pll1_sw" },
45 { .id = "pll2_pfd2_396m" },
46 { .id = "pll2_bus" },
47 { .id = "secondary_sel" },
48};
49
50static struct device *cpu_dev;
51static bool free_opp;
52static struct cpufreq_frequency_table *freq_table;
53static unsigned int max_freq;
54static unsigned int transition_latency;
55
56static u32 *imx6_soc_volt;
57static u32 soc_opp_count;
58
59static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
60{
61 struct dev_pm_opp *opp;
62 unsigned long freq_hz, volt, volt_old;
63 unsigned int old_freq, new_freq;
64 bool pll1_sys_temp_enabled = false;
65 int ret;
66
67 new_freq = freq_table[index].frequency;
68 freq_hz = new_freq * 1000;
69 old_freq = clk_get_rate(clks[ARM].clk) / 1000;
70
71 opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
72 if (IS_ERR(opp)) {
73 dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
74 return PTR_ERR(opp);
75 }
76
77 volt = dev_pm_opp_get_voltage(opp);
78 dev_pm_opp_put(opp);
79
80 volt_old = regulator_get_voltage(arm_reg);
81
82 dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
83 old_freq / 1000, volt_old / 1000,
84 new_freq / 1000, volt / 1000);
85
86 /* scaling up? scale voltage before frequency */
87 if (new_freq > old_freq) {
88 if (!IS_ERR(pu_reg)) {
89 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
90 if (ret) {
91 dev_err(cpu_dev, "failed to scale vddpu up: %d\n", ret);
92 return ret;
93 }
94 }
95 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
96 if (ret) {
97 dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
98 return ret;
99 }
100 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
101 if (ret) {
102 dev_err(cpu_dev,
103 "failed to scale vddarm up: %d\n", ret);
104 return ret;
105 }
106 }
107
108 /*
109 * The setpoints are selected per PLL/PDF frequencies, so we need to
110 * reprogram PLL for frequency scaling. The procedure of reprogramming
111 * PLL1 is as below.
112 * For i.MX6UL, it has a secondary clk mux, the cpu frequency change
113 * flow is slightly different from other i.MX6 OSC.
114 * The cpu frequeny change flow for i.MX6(except i.MX6UL) is as below:
115 * - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
116 * - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
117 * - Disable pll2_pfd2_396m_clk
118 */
119 if (of_machine_is_compatible("fsl,imx6ul") ||
120 of_machine_is_compatible("fsl,imx6ull")) {
121 /*
122 * When changing pll1_sw_clk's parent to pll1_sys_clk,
123 * CPU may run at higher than 528MHz, this will lead to
124 * the system unstable if the voltage is lower than the
125 * voltage of 528MHz, so lower the CPU frequency to one
126 * half before changing CPU frequency.
127 */
128 clk_set_rate(clks[ARM].clk, (old_freq >> 1) * 1000);
129 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
130 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk))
131 clk_set_parent(clks[SECONDARY_SEL].clk,
132 clks[PLL2_BUS].clk);
133 else
134 clk_set_parent(clks[SECONDARY_SEL].clk,
135 clks[PLL2_PFD2_396M].clk);
136 clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
137 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
138 if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
139 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
140 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
141 }
142 } else {
143 clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
144 clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
145 if (freq_hz > clk_get_rate(clks[PLL2_PFD2_396M].clk)) {
146 clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
147 clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
148 } else {
149 /* pll1_sys needs to be enabled for divider rate change to work. */
150 pll1_sys_temp_enabled = true;
151 clk_prepare_enable(clks[PLL1_SYS].clk);
152 }
153 }
154
155 /* Ensure the arm clock divider is what we expect */
156 ret = clk_set_rate(clks[ARM].clk, new_freq * 1000);
157 if (ret) {
158 int ret1;
159
160 dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
161 ret1 = regulator_set_voltage_tol(arm_reg, volt_old, 0);
162 if (ret1)
163 dev_warn(cpu_dev,
164 "failed to restore vddarm voltage: %d\n", ret1);
165 return ret;
166 }
167
168 /* PLL1 is only needed until after ARM-PODF is set. */
169 if (pll1_sys_temp_enabled)
170 clk_disable_unprepare(clks[PLL1_SYS].clk);
171
172 /* scaling down? scale voltage after frequency */
173 if (new_freq < old_freq) {
174 ret = regulator_set_voltage_tol(arm_reg, volt, 0);
175 if (ret)
176 dev_warn(cpu_dev,
177 "failed to scale vddarm down: %d\n", ret);
178 ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
179 if (ret)
180 dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
181 if (!IS_ERR(pu_reg)) {
182 ret = regulator_set_voltage_tol(pu_reg, imx6_soc_volt[index], 0);
183 if (ret)
184 dev_warn(cpu_dev, "failed to scale vddpu down: %d\n", ret);
185 }
186 }
187
188 return 0;
189}
190
191static int imx6q_cpufreq_init(struct cpufreq_policy *policy)
192{
193 policy->clk = clks[ARM].clk;
194 cpufreq_generic_init(policy, freq_table, transition_latency);
195 policy->suspend_freq = max_freq;
196 dev_pm_opp_of_register_em(cpu_dev, policy->cpus);
197
198 return 0;
199}
200
201static struct cpufreq_driver imx6q_cpufreq_driver = {
202 .flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
203 CPUFREQ_IS_COOLING_DEV,
204 .verify = cpufreq_generic_frequency_table_verify,
205 .target_index = imx6q_set_target,
206 .get = cpufreq_generic_get,
207 .init = imx6q_cpufreq_init,
208 .name = "imx6q-cpufreq",
209 .attr = cpufreq_generic_attr,
210 .suspend = cpufreq_generic_suspend,
211};
212
213#define OCOTP_CFG3 0x440
214#define OCOTP_CFG3_SPEED_SHIFT 16
215#define OCOTP_CFG3_SPEED_1P2GHZ 0x3
216#define OCOTP_CFG3_SPEED_996MHZ 0x2
217#define OCOTP_CFG3_SPEED_852MHZ 0x1
218
219static int imx6q_opp_check_speed_grading(struct device *dev)
220{
221 struct device_node *np;
222 void __iomem *base;
223 u32 val;
224 int ret;
225
226 if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
227 ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
228 if (ret)
229 return ret;
230 } else {
231 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
232 if (!np)
233 return -ENOENT;
234
235 base = of_iomap(np, 0);
236 of_node_put(np);
237 if (!base) {
238 dev_err(dev, "failed to map ocotp\n");
239 return -EFAULT;
240 }
241
242 /*
243 * SPEED_GRADING[1:0] defines the max speed of ARM:
244 * 2b'11: 1200000000Hz;
245 * 2b'10: 996000000Hz;
246 * 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
247 * 2b'00: 792000000Hz;
248 * We need to set the max speed of ARM according to fuse map.
249 */
250 val = readl_relaxed(base + OCOTP_CFG3);
251 iounmap(base);
252 }
253
254 val >>= OCOTP_CFG3_SPEED_SHIFT;
255 val &= 0x3;
256
257 if (val < OCOTP_CFG3_SPEED_996MHZ)
258 if (dev_pm_opp_disable(dev, 996000000))
259 dev_warn(dev, "failed to disable 996MHz OPP\n");
260
261 if (of_machine_is_compatible("fsl,imx6q") ||
262 of_machine_is_compatible("fsl,imx6qp")) {
263 if (val != OCOTP_CFG3_SPEED_852MHZ)
264 if (dev_pm_opp_disable(dev, 852000000))
265 dev_warn(dev, "failed to disable 852MHz OPP\n");
266 if (val != OCOTP_CFG3_SPEED_1P2GHZ)
267 if (dev_pm_opp_disable(dev, 1200000000))
268 dev_warn(dev, "failed to disable 1.2GHz OPP\n");
269 }
270
271 return 0;
272}
273
274#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
275#define OCOTP_CFG3_6ULL_SPEED_792MHZ 0x2
276#define OCOTP_CFG3_6ULL_SPEED_900MHZ 0x3
277
278static int imx6ul_opp_check_speed_grading(struct device *dev)
279{
280 u32 val;
281 int ret = 0;
282
283 if (of_find_property(dev->of_node, "nvmem-cells", NULL)) {
284 ret = nvmem_cell_read_u32(dev, "speed_grade", &val);
285 if (ret)
286 return ret;
287 } else {
288 struct device_node *np;
289 void __iomem *base;
290
291 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
292 if (!np)
293 np = of_find_compatible_node(NULL, NULL,
294 "fsl,imx6ull-ocotp");
295 if (!np)
296 return -ENOENT;
297
298 base = of_iomap(np, 0);
299 of_node_put(np);
300 if (!base) {
301 dev_err(dev, "failed to map ocotp\n");
302 return -EFAULT;
303 }
304
305 val = readl_relaxed(base + OCOTP_CFG3);
306 iounmap(base);
307 }
308
309 /*
310 * Speed GRADING[1:0] defines the max speed of ARM:
311 * 2b'00: Reserved;
312 * 2b'01: 528000000Hz;
313 * 2b'10: 696000000Hz on i.MX6UL, 792000000Hz on i.MX6ULL;
314 * 2b'11: 900000000Hz on i.MX6ULL only;
315 * We need to set the max speed of ARM according to fuse map.
316 */
317 val >>= OCOTP_CFG3_SPEED_SHIFT;
318 val &= 0x3;
319
320 if (of_machine_is_compatible("fsl,imx6ul")) {
321 if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
322 if (dev_pm_opp_disable(dev, 696000000))
323 dev_warn(dev, "failed to disable 696MHz OPP\n");
324 }
325
326 if (of_machine_is_compatible("fsl,imx6ull")) {
327 if (val != OCOTP_CFG3_6ULL_SPEED_792MHZ)
328 if (dev_pm_opp_disable(dev, 792000000))
329 dev_warn(dev, "failed to disable 792MHz OPP\n");
330
331 if (val != OCOTP_CFG3_6ULL_SPEED_900MHZ)
332 if (dev_pm_opp_disable(dev, 900000000))
333 dev_warn(dev, "failed to disable 900MHz OPP\n");
334 }
335
336 return ret;
337}
338
339static int imx6q_cpufreq_probe(struct platform_device *pdev)
340{
341 struct device_node *np;
342 struct dev_pm_opp *opp;
343 unsigned long min_volt, max_volt;
344 int num, ret;
345 const struct property *prop;
346 const __be32 *val;
347 u32 nr, i, j;
348
349 cpu_dev = get_cpu_device(0);
350 if (!cpu_dev) {
351 pr_err("failed to get cpu0 device\n");
352 return -ENODEV;
353 }
354
355 np = of_node_get(cpu_dev->of_node);
356 if (!np) {
357 dev_err(cpu_dev, "failed to find cpu0 node\n");
358 return -ENOENT;
359 }
360
361 if (of_machine_is_compatible("fsl,imx6ul") ||
362 of_machine_is_compatible("fsl,imx6ull"))
363 num_clks = IMX6UL_CPUFREQ_CLK_NUM;
364 else
365 num_clks = IMX6Q_CPUFREQ_CLK_NUM;
366
367 ret = clk_bulk_get(cpu_dev, num_clks, clks);
368 if (ret)
369 goto put_node;
370
371 arm_reg = regulator_get(cpu_dev, "arm");
372 pu_reg = regulator_get_optional(cpu_dev, "pu");
373 soc_reg = regulator_get(cpu_dev, "soc");
374 if (PTR_ERR(arm_reg) == -EPROBE_DEFER ||
375 PTR_ERR(soc_reg) == -EPROBE_DEFER ||
376 PTR_ERR(pu_reg) == -EPROBE_DEFER) {
377 ret = -EPROBE_DEFER;
378 dev_dbg(cpu_dev, "regulators not ready, defer\n");
379 goto put_reg;
380 }
381 if (IS_ERR(arm_reg) || IS_ERR(soc_reg)) {
382 dev_err(cpu_dev, "failed to get regulators\n");
383 ret = -ENOENT;
384 goto put_reg;
385 }
386
387 ret = dev_pm_opp_of_add_table(cpu_dev);
388 if (ret < 0) {
389 dev_err(cpu_dev, "failed to init OPP table: %d\n", ret);
390 goto put_reg;
391 }
392
393 /* Because we have added the OPPs here, we must free them */
394 free_opp = true;
395
396 if (of_machine_is_compatible("fsl,imx6ul") ||
397 of_machine_is_compatible("fsl,imx6ull")) {
398 ret = imx6ul_opp_check_speed_grading(cpu_dev);
399 } else {
400 ret = imx6q_opp_check_speed_grading(cpu_dev);
401 }
402 if (ret) {
403 if (ret != -EPROBE_DEFER)
404 dev_err(cpu_dev, "failed to read ocotp: %d\n",
405 ret);
406 goto out_free_opp;
407 }
408
409 num = dev_pm_opp_get_opp_count(cpu_dev);
410 if (num < 0) {
411 ret = num;
412 dev_err(cpu_dev, "no OPP table is found: %d\n", ret);
413 goto out_free_opp;
414 }
415
416 ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &freq_table);
417 if (ret) {
418 dev_err(cpu_dev, "failed to init cpufreq table: %d\n", ret);
419 goto out_free_opp;
420 }
421
422 /* Make imx6_soc_volt array's size same as arm opp number */
423 imx6_soc_volt = devm_kcalloc(cpu_dev, num, sizeof(*imx6_soc_volt),
424 GFP_KERNEL);
425 if (imx6_soc_volt == NULL) {
426 ret = -ENOMEM;
427 goto free_freq_table;
428 }
429
430 prop = of_find_property(np, "fsl,soc-operating-points", NULL);
431 if (!prop || !prop->value)
432 goto soc_opp_out;
433
434 /*
435 * Each OPP is a set of tuples consisting of frequency and
436 * voltage like <freq-kHz vol-uV>.
437 */
438 nr = prop->length / sizeof(u32);
439 if (nr % 2 || (nr / 2) < num)
440 goto soc_opp_out;
441
442 for (j = 0; j < num; j++) {
443 val = prop->value;
444 for (i = 0; i < nr / 2; i++) {
445 unsigned long freq = be32_to_cpup(val++);
446 unsigned long volt = be32_to_cpup(val++);
447 if (freq_table[j].frequency == freq) {
448 imx6_soc_volt[soc_opp_count++] = volt;
449 break;
450 }
451 }
452 }
453
454soc_opp_out:
455 /* use fixed soc opp volt if no valid soc opp info found in dtb */
456 if (soc_opp_count != num) {
457 dev_warn(cpu_dev, "can NOT find valid fsl,soc-operating-points property in dtb, use default value!\n");
458 for (j = 0; j < num; j++)
459 imx6_soc_volt[j] = PU_SOC_VOLTAGE_NORMAL;
460 if (freq_table[num - 1].frequency * 1000 == FREQ_1P2_GHZ)
461 imx6_soc_volt[num - 1] = PU_SOC_VOLTAGE_HIGH;
462 }
463
464 if (of_property_read_u32(np, "clock-latency", &transition_latency))
465 transition_latency = CPUFREQ_ETERNAL;
466
467 /*
468 * Calculate the ramp time for max voltage change in the
469 * VDDSOC and VDDPU regulators.
470 */
471 ret = regulator_set_voltage_time(soc_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
472 if (ret > 0)
473 transition_latency += ret * 1000;
474 if (!IS_ERR(pu_reg)) {
475 ret = regulator_set_voltage_time(pu_reg, imx6_soc_volt[0], imx6_soc_volt[num - 1]);
476 if (ret > 0)
477 transition_latency += ret * 1000;
478 }
479
480 /*
481 * OPP is maintained in order of increasing frequency, and
482 * freq_table initialised from OPP is therefore sorted in the
483 * same order.
484 */
485 max_freq = freq_table[--num].frequency;
486 opp = dev_pm_opp_find_freq_exact(cpu_dev,
487 freq_table[0].frequency * 1000, true);
488 min_volt = dev_pm_opp_get_voltage(opp);
489 dev_pm_opp_put(opp);
490 opp = dev_pm_opp_find_freq_exact(cpu_dev, max_freq * 1000, true);
491 max_volt = dev_pm_opp_get_voltage(opp);
492 dev_pm_opp_put(opp);
493
494 ret = regulator_set_voltage_time(arm_reg, min_volt, max_volt);
495 if (ret > 0)
496 transition_latency += ret * 1000;
497
498 ret = cpufreq_register_driver(&imx6q_cpufreq_driver);
499 if (ret) {
500 dev_err(cpu_dev, "failed register driver: %d\n", ret);
501 goto free_freq_table;
502 }
503
504 of_node_put(np);
505 return 0;
506
507free_freq_table:
508 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
509out_free_opp:
510 if (free_opp)
511 dev_pm_opp_of_remove_table(cpu_dev);
512put_reg:
513 if (!IS_ERR(arm_reg))
514 regulator_put(arm_reg);
515 if (!IS_ERR(pu_reg))
516 regulator_put(pu_reg);
517 if (!IS_ERR(soc_reg))
518 regulator_put(soc_reg);
519
520 clk_bulk_put(num_clks, clks);
521put_node:
522 of_node_put(np);
523
524 return ret;
525}
526
527static int imx6q_cpufreq_remove(struct platform_device *pdev)
528{
529 cpufreq_unregister_driver(&imx6q_cpufreq_driver);
530 dev_pm_opp_free_cpufreq_table(cpu_dev, &freq_table);
531 if (free_opp)
532 dev_pm_opp_of_remove_table(cpu_dev);
533 regulator_put(arm_reg);
534 if (!IS_ERR(pu_reg))
535 regulator_put(pu_reg);
536 regulator_put(soc_reg);
537
538 clk_bulk_put(num_clks, clks);
539
540 return 0;
541}
542
543static struct platform_driver imx6q_cpufreq_platdrv = {
544 .driver = {
545 .name = "imx6q-cpufreq",
546 },
547 .probe = imx6q_cpufreq_probe,
548 .remove = imx6q_cpufreq_remove,
549};
550module_platform_driver(imx6q_cpufreq_platdrv);
551
552MODULE_ALIAS("platform:imx6q-cpufreq");
553MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
554MODULE_DESCRIPTION("Freescale i.MX6Q cpufreq driver");
555MODULE_LICENSE("GPL");