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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#include <linux/module.h>
12#include <linux/ioport.h>
13#include <linux/init.h>
14#include <linux/console.h>
15#include <linux/sysrq.h>
16#include <linux/platform_device.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/ktime.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/rational.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/io.h>
29#include <linux/dma-mapping.h>
30
31#include <asm/irq.h>
32#include <linux/dma/imx-dma.h>
33
34#include "serial_mctrl_gpio.h"
35
36/* Register definitions */
37#define URXD0 0x0 /* Receiver Register */
38#define URTX0 0x40 /* Transmitter Register */
39#define UCR1 0x80 /* Control Register 1 */
40#define UCR2 0x84 /* Control Register 2 */
41#define UCR3 0x88 /* Control Register 3 */
42#define UCR4 0x8c /* Control Register 4 */
43#define UFCR 0x90 /* FIFO Control Register */
44#define USR1 0x94 /* Status Register 1 */
45#define USR2 0x98 /* Status Register 2 */
46#define UESC 0x9c /* Escape Character Register */
47#define UTIM 0xa0 /* Escape Timer Register */
48#define UBIR 0xa4 /* BRM Incremental Register */
49#define UBMR 0xa8 /* BRM Modulator Register */
50#define UBRC 0xac /* Baud Rate Count Register */
51#define IMX21_ONEMS 0xb0 /* One Millisecond register */
52#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
53#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
54
55/* UART Control Register Bit Fields.*/
56#define URXD_DUMMY_READ (1<<16)
57#define URXD_CHARRDY (1<<15)
58#define URXD_ERR (1<<14)
59#define URXD_OVRRUN (1<<13)
60#define URXD_FRMERR (1<<12)
61#define URXD_BRK (1<<11)
62#define URXD_PRERR (1<<10)
63#define URXD_RX_DATA (0xFF<<0)
64#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
65#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
66#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
67#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
68#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
69#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
70#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
71#define UCR1_IREN (1<<7) /* Infrared interface enable */
72#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
73#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
74#define UCR1_SNDBRK (1<<4) /* Send break */
75#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
76#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
77#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
78#define UCR1_DOZE (1<<1) /* Doze */
79#define UCR1_UARTEN (1<<0) /* UART enabled */
80#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
81#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
82#define UCR2_CTSC (1<<13) /* CTS pin control */
83#define UCR2_CTS (1<<12) /* Clear to send */
84#define UCR2_ESCEN (1<<11) /* Escape enable */
85#define UCR2_PREN (1<<8) /* Parity enable */
86#define UCR2_PROE (1<<7) /* Parity odd/even */
87#define UCR2_STPB (1<<6) /* Stop */
88#define UCR2_WS (1<<5) /* Word size */
89#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
90#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
91#define UCR2_TXEN (1<<2) /* Transmitter enabled */
92#define UCR2_RXEN (1<<1) /* Receiver enabled */
93#define UCR2_SRST (1<<0) /* SW reset */
94#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
95#define UCR3_PARERREN (1<<12) /* Parity enable */
96#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
97#define UCR3_DSR (1<<10) /* Data set ready */
98#define UCR3_DCD (1<<9) /* Data carrier detect */
99#define UCR3_RI (1<<8) /* Ring indicator */
100#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
101#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
102#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
103#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
104#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
105#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
106#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
107#define UCR3_BPEN (1<<0) /* Preset registers enable */
108#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
109#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
110#define UCR4_INVR (1<<9) /* Inverted infrared reception */
111#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
112#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
113#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
114#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
115#define UCR4_IRSC (1<<5) /* IR special case */
116#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
117#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
118#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
119#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
120#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
121#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
122#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
123#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
124#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
125#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
126#define USR1_RTSS (1<<14) /* RTS pin status */
127#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
128#define USR1_RTSD (1<<12) /* RTS delta */
129#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
130#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
131#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
132#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
133#define USR1_DTRD (1<<7) /* DTR Delta */
134#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
135#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
136#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
137#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
138#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
139#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
140#define USR2_IDLE (1<<12) /* Idle condition */
141#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
142#define USR2_RIIN (1<<9) /* Ring Indicator Input */
143#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
144#define USR2_WAKE (1<<7) /* Wake */
145#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
146#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
147#define USR2_TXDC (1<<3) /* Transmitter complete */
148#define USR2_BRCD (1<<2) /* Break condition */
149#define USR2_ORE (1<<1) /* Overrun error */
150#define USR2_RDR (1<<0) /* Recv data ready */
151#define UTS_FRCPERR (1<<13) /* Force parity error */
152#define UTS_LOOP (1<<12) /* Loop tx and rx */
153#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
154#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
155#define UTS_TXFULL (1<<4) /* TxFIFO full */
156#define UTS_RXFULL (1<<3) /* RxFIFO full */
157#define UTS_SOFTRST (1<<0) /* Software reset */
158
159/* We've been assigned a range on the "Low-density serial ports" major */
160#define SERIAL_IMX_MAJOR 207
161#define MINOR_START 16
162#define DEV_NAME "ttymxc"
163
164/*
165 * This determines how often we check the modem status signals
166 * for any change. They generally aren't connected to an IRQ
167 * so we have to poll them. We also check immediately before
168 * filling the TX fifo incase CTS has been dropped.
169 */
170#define MCTRL_TIMEOUT (250*HZ/1000)
171
172#define DRIVER_NAME "IMX-uart"
173
174#define UART_NR 8
175
176/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
177enum imx_uart_type {
178 IMX1_UART,
179 IMX21_UART,
180};
181
182/* device type dependent stuff */
183struct imx_uart_data {
184 unsigned uts_reg;
185 enum imx_uart_type devtype;
186};
187
188enum imx_tx_state {
189 OFF,
190 WAIT_AFTER_RTS,
191 SEND,
192 WAIT_AFTER_SEND,
193};
194
195struct imx_port {
196 struct uart_port port;
197 struct timer_list timer;
198 unsigned int old_status;
199 unsigned int have_rtscts:1;
200 unsigned int have_rtsgpio:1;
201 unsigned int dte_mode:1;
202 unsigned int inverted_tx:1;
203 unsigned int inverted_rx:1;
204 struct clk *clk_ipg;
205 struct clk *clk_per;
206 const struct imx_uart_data *devdata;
207
208 struct mctrl_gpios *gpios;
209
210 /* counter to stop 0xff flood */
211 int idle_counter;
212
213 /* DMA fields */
214 unsigned int dma_is_enabled:1;
215 unsigned int dma_is_rxing:1;
216 unsigned int dma_is_txing:1;
217 struct dma_chan *dma_chan_rx, *dma_chan_tx;
218 struct scatterlist rx_sgl, tx_sgl[2];
219 void *rx_buf;
220 struct circ_buf rx_ring;
221 unsigned int rx_buf_size;
222 unsigned int rx_period_length;
223 unsigned int rx_periods;
224 dma_cookie_t rx_cookie;
225 unsigned int tx_bytes;
226 unsigned int dma_tx_nents;
227 unsigned int saved_reg[10];
228 bool context_saved;
229
230 enum imx_tx_state tx_state;
231 struct hrtimer trigger_start_tx;
232 struct hrtimer trigger_stop_tx;
233};
234
235struct imx_port_ucrs {
236 unsigned int ucr1;
237 unsigned int ucr2;
238 unsigned int ucr3;
239};
240
241static const struct imx_uart_data imx_uart_imx1_devdata = {
242 .uts_reg = IMX1_UTS,
243 .devtype = IMX1_UART,
244};
245
246static const struct imx_uart_data imx_uart_imx21_devdata = {
247 .uts_reg = IMX21_UTS,
248 .devtype = IMX21_UART,
249};
250
251static const struct of_device_id imx_uart_dt_ids[] = {
252 /*
253 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are
254 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
255 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
256 * doesn't make any distinction between these two variants.
257 */
258 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
259 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
260 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
261 { /* sentinel */ }
262};
263MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
264
265static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
266{
267 writel(val, sport->port.membase + offset);
268}
269
270static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
271{
272 return readl(sport->port.membase + offset);
273}
274
275static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
276{
277 return sport->devdata->uts_reg;
278}
279
280static inline int imx_uart_is_imx1(struct imx_port *sport)
281{
282 return sport->devdata->devtype == IMX1_UART;
283}
284
285/*
286 * Save and restore functions for UCR1, UCR2 and UCR3 registers
287 */
288#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
289static void imx_uart_ucrs_save(struct imx_port *sport,
290 struct imx_port_ucrs *ucr)
291{
292 /* save control registers */
293 ucr->ucr1 = imx_uart_readl(sport, UCR1);
294 ucr->ucr2 = imx_uart_readl(sport, UCR2);
295 ucr->ucr3 = imx_uart_readl(sport, UCR3);
296}
297
298static void imx_uart_ucrs_restore(struct imx_port *sport,
299 struct imx_port_ucrs *ucr)
300{
301 /* restore control registers */
302 imx_uart_writel(sport, ucr->ucr1, UCR1);
303 imx_uart_writel(sport, ucr->ucr2, UCR2);
304 imx_uart_writel(sport, ucr->ucr3, UCR3);
305}
306#endif
307
308/* called with port.lock taken and irqs caller dependent */
309static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
310{
311 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
312
313 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
314}
315
316/* called with port.lock taken and irqs caller dependent */
317static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
318{
319 *ucr2 &= ~UCR2_CTSC;
320 *ucr2 |= UCR2_CTS;
321
322 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
323}
324
325static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
326{
327 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
328}
329
330/* called with port.lock taken and irqs off */
331static void imx_uart_soft_reset(struct imx_port *sport)
332{
333 int i = 10;
334 u32 ucr2, ubir, ubmr, uts;
335
336 /*
337 * According to the Reference Manual description of the UART SRST bit:
338 *
339 * "Reset the transmit and receive state machines,
340 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
341 * and UTS[6-3]".
342 *
343 * We don't need to restore the old values from USR1, USR2, URXD and
344 * UTXD. UBRC is read only, so only save/restore the other three
345 * registers.
346 */
347 ubir = imx_uart_readl(sport, UBIR);
348 ubmr = imx_uart_readl(sport, UBMR);
349 uts = imx_uart_readl(sport, IMX21_UTS);
350
351 ucr2 = imx_uart_readl(sport, UCR2);
352 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
353
354 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
355 udelay(1);
356
357 /* Restore the registers */
358 imx_uart_writel(sport, ubir, UBIR);
359 imx_uart_writel(sport, ubmr, UBMR);
360 imx_uart_writel(sport, uts, IMX21_UTS);
361
362 sport->idle_counter = 0;
363}
364
365static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
366{
367 unsigned int uts;
368
369 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
370 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
371 uts &= ~UTS_LOOP;
372 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
373}
374
375/* called with port.lock taken and irqs off */
376static void imx_uart_start_rx(struct uart_port *port)
377{
378 struct imx_port *sport = (struct imx_port *)port;
379 unsigned int ucr1, ucr2;
380
381 ucr1 = imx_uart_readl(sport, UCR1);
382 ucr2 = imx_uart_readl(sport, UCR2);
383
384 ucr2 |= UCR2_RXEN;
385
386 if (sport->dma_is_enabled) {
387 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
388 } else {
389 ucr1 |= UCR1_RRDYEN;
390 ucr2 |= UCR2_ATEN;
391 }
392
393 /* Write UCR2 first as it includes RXEN */
394 imx_uart_writel(sport, ucr2, UCR2);
395 imx_uart_writel(sport, ucr1, UCR1);
396 imx_uart_disable_loopback_rs485(sport);
397}
398
399/* called with port.lock taken and irqs off */
400static void imx_uart_stop_tx(struct uart_port *port)
401{
402 struct imx_port *sport = (struct imx_port *)port;
403 u32 ucr1, ucr4, usr2;
404
405 if (sport->tx_state == OFF)
406 return;
407
408 /*
409 * We are maybe in the SMP context, so if the DMA TX thread is running
410 * on other cpu, we have to wait for it to finish.
411 */
412 if (sport->dma_is_txing)
413 return;
414
415 ucr1 = imx_uart_readl(sport, UCR1);
416 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
417
418 ucr4 = imx_uart_readl(sport, UCR4);
419 usr2 = imx_uart_readl(sport, USR2);
420 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
421 /* The shifter is still busy, so retry once TC triggers */
422 return;
423 }
424
425 ucr4 &= ~UCR4_TCEN;
426 imx_uart_writel(sport, ucr4, UCR4);
427
428 /* in rs485 mode disable transmitter */
429 if (port->rs485.flags & SER_RS485_ENABLED) {
430 if (sport->tx_state == SEND) {
431 sport->tx_state = WAIT_AFTER_SEND;
432
433 if (port->rs485.delay_rts_after_send > 0) {
434 start_hrtimer_ms(&sport->trigger_stop_tx,
435 port->rs485.delay_rts_after_send);
436 return;
437 }
438
439 /* continue without any delay */
440 }
441
442 if (sport->tx_state == WAIT_AFTER_RTS ||
443 sport->tx_state == WAIT_AFTER_SEND) {
444 u32 ucr2;
445
446 hrtimer_try_to_cancel(&sport->trigger_start_tx);
447
448 ucr2 = imx_uart_readl(sport, UCR2);
449 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
450 imx_uart_rts_active(sport, &ucr2);
451 else
452 imx_uart_rts_inactive(sport, &ucr2);
453 imx_uart_writel(sport, ucr2, UCR2);
454
455 if (!port->rs485_rx_during_tx_gpio)
456 imx_uart_start_rx(port);
457
458 sport->tx_state = OFF;
459 }
460 } else {
461 sport->tx_state = OFF;
462 }
463}
464
465static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
466{
467 struct imx_port *sport = (struct imx_port *)port;
468 u32 ucr1, ucr2, ucr4, uts;
469
470 ucr1 = imx_uart_readl(sport, UCR1);
471 ucr2 = imx_uart_readl(sport, UCR2);
472 ucr4 = imx_uart_readl(sport, UCR4);
473
474 if (sport->dma_is_enabled) {
475 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
476 } else {
477 ucr1 &= ~UCR1_RRDYEN;
478 ucr2 &= ~UCR2_ATEN;
479 ucr4 &= ~UCR4_OREN;
480 }
481 imx_uart_writel(sport, ucr1, UCR1);
482 imx_uart_writel(sport, ucr4, UCR4);
483
484 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
485 if (port->rs485.flags & SER_RS485_ENABLED &&
486 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
487 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
488 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
489 uts |= UTS_LOOP;
490 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
491 ucr2 |= UCR2_RXEN;
492 } else {
493 ucr2 &= ~UCR2_RXEN;
494 }
495
496 imx_uart_writel(sport, ucr2, UCR2);
497}
498
499/* called with port.lock taken and irqs off */
500static void imx_uart_stop_rx(struct uart_port *port)
501{
502 /*
503 * Stop RX and enable loopback in order to make sure RS485 bus
504 * is not blocked. Se comment in imx_uart_probe().
505 */
506 imx_uart_stop_rx_with_loopback_ctrl(port, true);
507}
508
509/* called with port.lock taken and irqs off */
510static void imx_uart_enable_ms(struct uart_port *port)
511{
512 struct imx_port *sport = (struct imx_port *)port;
513
514 mod_timer(&sport->timer, jiffies);
515
516 mctrl_gpio_enable_ms(sport->gpios);
517}
518
519static void imx_uart_dma_tx(struct imx_port *sport);
520
521/* called with port.lock taken and irqs off */
522static inline void imx_uart_transmit_buffer(struct imx_port *sport)
523{
524 struct circ_buf *xmit = &sport->port.state->xmit;
525
526 if (sport->port.x_char) {
527 /* Send next char */
528 imx_uart_writel(sport, sport->port.x_char, URTX0);
529 sport->port.icount.tx++;
530 sport->port.x_char = 0;
531 return;
532 }
533
534 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
535 imx_uart_stop_tx(&sport->port);
536 return;
537 }
538
539 if (sport->dma_is_enabled) {
540 u32 ucr1;
541 /*
542 * We've just sent a X-char Ensure the TX DMA is enabled
543 * and the TX IRQ is disabled.
544 **/
545 ucr1 = imx_uart_readl(sport, UCR1);
546 ucr1 &= ~UCR1_TRDYEN;
547 if (sport->dma_is_txing) {
548 ucr1 |= UCR1_TXDMAEN;
549 imx_uart_writel(sport, ucr1, UCR1);
550 } else {
551 imx_uart_writel(sport, ucr1, UCR1);
552 imx_uart_dma_tx(sport);
553 }
554
555 return;
556 }
557
558 while (!uart_circ_empty(xmit) &&
559 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
560 /* send xmit->buf[xmit->tail]
561 * out the port here */
562 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
563 uart_xmit_advance(&sport->port, 1);
564 }
565
566 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
567 uart_write_wakeup(&sport->port);
568
569 if (uart_circ_empty(xmit))
570 imx_uart_stop_tx(&sport->port);
571}
572
573static void imx_uart_dma_tx_callback(void *data)
574{
575 struct imx_port *sport = data;
576 struct scatterlist *sgl = &sport->tx_sgl[0];
577 struct circ_buf *xmit = &sport->port.state->xmit;
578 unsigned long flags;
579 u32 ucr1;
580
581 uart_port_lock_irqsave(&sport->port, &flags);
582
583 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
584
585 ucr1 = imx_uart_readl(sport, UCR1);
586 ucr1 &= ~UCR1_TXDMAEN;
587 imx_uart_writel(sport, ucr1, UCR1);
588
589 uart_xmit_advance(&sport->port, sport->tx_bytes);
590
591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
592
593 sport->dma_is_txing = 0;
594
595 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
596 uart_write_wakeup(&sport->port);
597
598 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
599 imx_uart_dma_tx(sport);
600 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
601 u32 ucr4 = imx_uart_readl(sport, UCR4);
602 ucr4 |= UCR4_TCEN;
603 imx_uart_writel(sport, ucr4, UCR4);
604 }
605
606 uart_port_unlock_irqrestore(&sport->port, flags);
607}
608
609/* called with port.lock taken and irqs off */
610static void imx_uart_dma_tx(struct imx_port *sport)
611{
612 struct circ_buf *xmit = &sport->port.state->xmit;
613 struct scatterlist *sgl = sport->tx_sgl;
614 struct dma_async_tx_descriptor *desc;
615 struct dma_chan *chan = sport->dma_chan_tx;
616 struct device *dev = sport->port.dev;
617 u32 ucr1, ucr4;
618 int ret;
619
620 if (sport->dma_is_txing)
621 return;
622
623 ucr4 = imx_uart_readl(sport, UCR4);
624 ucr4 &= ~UCR4_TCEN;
625 imx_uart_writel(sport, ucr4, UCR4);
626
627 sport->tx_bytes = uart_circ_chars_pending(xmit);
628
629 if (xmit->tail < xmit->head || xmit->head == 0) {
630 sport->dma_tx_nents = 1;
631 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
632 } else {
633 sport->dma_tx_nents = 2;
634 sg_init_table(sgl, 2);
635 sg_set_buf(sgl, xmit->buf + xmit->tail,
636 UART_XMIT_SIZE - xmit->tail);
637 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
638 }
639
640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
641 if (ret == 0) {
642 dev_err(dev, "DMA mapping error for TX.\n");
643 return;
644 }
645 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
646 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
647 if (!desc) {
648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
649 DMA_TO_DEVICE);
650 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
651 return;
652 }
653 desc->callback = imx_uart_dma_tx_callback;
654 desc->callback_param = sport;
655
656 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
657 uart_circ_chars_pending(xmit));
658
659 ucr1 = imx_uart_readl(sport, UCR1);
660 ucr1 |= UCR1_TXDMAEN;
661 imx_uart_writel(sport, ucr1, UCR1);
662
663 /* fire it */
664 sport->dma_is_txing = 1;
665 dmaengine_submit(desc);
666 dma_async_issue_pending(chan);
667 return;
668}
669
670/* called with port.lock taken and irqs off */
671static void imx_uart_start_tx(struct uart_port *port)
672{
673 struct imx_port *sport = (struct imx_port *)port;
674 u32 ucr1;
675
676 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
677 return;
678
679 /*
680 * We cannot simply do nothing here if sport->tx_state == SEND already
681 * because UCR1_TXMPTYEN might already have been cleared in
682 * imx_uart_stop_tx(), but tx_state is still SEND.
683 */
684
685 if (port->rs485.flags & SER_RS485_ENABLED) {
686 if (sport->tx_state == OFF) {
687 u32 ucr2 = imx_uart_readl(sport, UCR2);
688 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
689 imx_uart_rts_active(sport, &ucr2);
690 else
691 imx_uart_rts_inactive(sport, &ucr2);
692 imx_uart_writel(sport, ucr2, UCR2);
693
694 /*
695 * Since we are about to transmit we can not stop RX
696 * with loopback enabled because that will make our
697 * transmitted data being just looped to RX.
698 */
699 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
700 !port->rs485_rx_during_tx_gpio)
701 imx_uart_stop_rx_with_loopback_ctrl(port, false);
702
703 sport->tx_state = WAIT_AFTER_RTS;
704
705 if (port->rs485.delay_rts_before_send > 0) {
706 start_hrtimer_ms(&sport->trigger_start_tx,
707 port->rs485.delay_rts_before_send);
708 return;
709 }
710
711 /* continue without any delay */
712 }
713
714 if (sport->tx_state == WAIT_AFTER_SEND
715 || sport->tx_state == WAIT_AFTER_RTS) {
716
717 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
718
719 /*
720 * Enable transmitter and shifter empty irq only if DMA
721 * is off. In the DMA case this is done in the
722 * tx-callback.
723 */
724 if (!sport->dma_is_enabled) {
725 u32 ucr4 = imx_uart_readl(sport, UCR4);
726 ucr4 |= UCR4_TCEN;
727 imx_uart_writel(sport, ucr4, UCR4);
728 }
729
730 sport->tx_state = SEND;
731 }
732 } else {
733 sport->tx_state = SEND;
734 }
735
736 if (!sport->dma_is_enabled) {
737 ucr1 = imx_uart_readl(sport, UCR1);
738 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
739 }
740
741 if (sport->dma_is_enabled) {
742 if (sport->port.x_char) {
743 /* We have X-char to send, so enable TX IRQ and
744 * disable TX DMA to let TX interrupt to send X-char */
745 ucr1 = imx_uart_readl(sport, UCR1);
746 ucr1 &= ~UCR1_TXDMAEN;
747 ucr1 |= UCR1_TRDYEN;
748 imx_uart_writel(sport, ucr1, UCR1);
749 return;
750 }
751
752 if (!uart_circ_empty(&port->state->xmit) &&
753 !uart_tx_stopped(port))
754 imx_uart_dma_tx(sport);
755 return;
756 }
757}
758
759static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
760{
761 struct imx_port *sport = dev_id;
762 u32 usr1;
763
764 imx_uart_writel(sport, USR1_RTSD, USR1);
765 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
766 uart_handle_cts_change(&sport->port, usr1);
767 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
768
769 return IRQ_HANDLED;
770}
771
772static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
773{
774 struct imx_port *sport = dev_id;
775 irqreturn_t ret;
776
777 uart_port_lock(&sport->port);
778
779 ret = __imx_uart_rtsint(irq, dev_id);
780
781 uart_port_unlock(&sport->port);
782
783 return ret;
784}
785
786static irqreturn_t imx_uart_txint(int irq, void *dev_id)
787{
788 struct imx_port *sport = dev_id;
789
790 uart_port_lock(&sport->port);
791 imx_uart_transmit_buffer(sport);
792 uart_port_unlock(&sport->port);
793 return IRQ_HANDLED;
794}
795
796/* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
797 * This is to be called from Rx ISRs only when some bytes were actually
798 * received.
799 *
800 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
801 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
802 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
803 * that is terminated by any activity on RxD line, or could be stopped by
804 * issuing soft reset to the UART (just stop/start of RX does not help). Note
805 * that what we do here is sending isolated start bit about 2.4 times shorter
806 * than it is to be on UART configured baud rate.
807 */
808static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
809{
810 /* To detect hardware 0xff flood we monitor RxD line between RX
811 * interrupts to isolate "receiving" of char(s) with no activity
812 * on RxD line, that'd never happen on actual data transfers.
813 *
814 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
815 * race here if we clear USR2_WAKE when receiving of a char is in
816 * progress, so we might get RX interrupt later with USR2_WAKE bit
817 * cleared. Note though that as we don't try to clear USR2_WAKE when we
818 * detected no activity, this race may hide actual activity only once.
819 *
820 * Yet another case where receive interrupt may occur without RxD
821 * activity is expiration of aging timer, so we consider this as well.
822 *
823 * We use 'idle_counter' to ensure that we got at least so many RX
824 * interrupts without any detected activity on RxD line. 2 cases
825 * described plus 1 to be on the safe side gives us a margin of 3,
826 * below. In practice I was not able to produce a false positive to
827 * induce soft reset at regular data transfers even using 1 as the
828 * margin, so 3 is actually very strong.
829 *
830 * We count interrupts, not chars in 'idle-counter' for simplicity.
831 */
832
833 if (usr2 & USR2_WAKE) {
834 imx_uart_writel(sport, USR2_WAKE, USR2);
835 sport->idle_counter = 0;
836 } else if (++sport->idle_counter > 3) {
837 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
838 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
839 }
840}
841
842static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
843{
844 struct imx_port *sport = dev_id;
845 struct tty_port *port = &sport->port.state->port;
846 u32 usr2, rx;
847
848 /* If we received something, check for 0xff flood */
849 usr2 = imx_uart_readl(sport, USR2);
850 if (usr2 & USR2_RDR)
851 imx_uart_check_flood(sport, usr2);
852
853 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
854 unsigned int flg = TTY_NORMAL;
855 sport->port.icount.rx++;
856
857 if (unlikely(rx & URXD_ERR)) {
858 if (rx & URXD_BRK) {
859 sport->port.icount.brk++;
860 if (uart_handle_break(&sport->port))
861 continue;
862 }
863 else if (rx & URXD_PRERR)
864 sport->port.icount.parity++;
865 else if (rx & URXD_FRMERR)
866 sport->port.icount.frame++;
867 if (rx & URXD_OVRRUN)
868 sport->port.icount.overrun++;
869
870 if (rx & sport->port.ignore_status_mask)
871 continue;
872
873 rx &= (sport->port.read_status_mask | 0xFF);
874
875 if (rx & URXD_BRK)
876 flg = TTY_BREAK;
877 else if (rx & URXD_PRERR)
878 flg = TTY_PARITY;
879 else if (rx & URXD_FRMERR)
880 flg = TTY_FRAME;
881 if (rx & URXD_OVRRUN)
882 flg = TTY_OVERRUN;
883
884 sport->port.sysrq = 0;
885 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
886 continue;
887 }
888
889 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
890 continue;
891
892 if (tty_insert_flip_char(port, rx, flg) == 0)
893 sport->port.icount.buf_overrun++;
894 }
895
896 tty_flip_buffer_push(port);
897
898 return IRQ_HANDLED;
899}
900
901static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
902{
903 struct imx_port *sport = dev_id;
904 irqreturn_t ret;
905
906 uart_port_lock(&sport->port);
907
908 ret = __imx_uart_rxint(irq, dev_id);
909
910 uart_port_unlock(&sport->port);
911
912 return ret;
913}
914
915static void imx_uart_clear_rx_errors(struct imx_port *sport);
916
917/*
918 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
919 */
920static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
921{
922 unsigned int tmp = TIOCM_DSR;
923 unsigned usr1 = imx_uart_readl(sport, USR1);
924 unsigned usr2 = imx_uart_readl(sport, USR2);
925
926 if (usr1 & USR1_RTSS)
927 tmp |= TIOCM_CTS;
928
929 /* in DCE mode DCDIN is always 0 */
930 if (!(usr2 & USR2_DCDIN))
931 tmp |= TIOCM_CAR;
932
933 if (sport->dte_mode)
934 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
935 tmp |= TIOCM_RI;
936
937 return tmp;
938}
939
940/*
941 * Handle any change of modem status signal since we were last called.
942 */
943static void imx_uart_mctrl_check(struct imx_port *sport)
944{
945 unsigned int status, changed;
946
947 status = imx_uart_get_hwmctrl(sport);
948 changed = status ^ sport->old_status;
949
950 if (changed == 0)
951 return;
952
953 sport->old_status = status;
954
955 if (changed & TIOCM_RI && status & TIOCM_RI)
956 sport->port.icount.rng++;
957 if (changed & TIOCM_DSR)
958 sport->port.icount.dsr++;
959 if (changed & TIOCM_CAR)
960 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
961 if (changed & TIOCM_CTS)
962 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
963
964 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
965}
966
967static irqreturn_t imx_uart_int(int irq, void *dev_id)
968{
969 struct imx_port *sport = dev_id;
970 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
971 irqreturn_t ret = IRQ_NONE;
972
973 uart_port_lock(&sport->port);
974
975 usr1 = imx_uart_readl(sport, USR1);
976 usr2 = imx_uart_readl(sport, USR2);
977 ucr1 = imx_uart_readl(sport, UCR1);
978 ucr2 = imx_uart_readl(sport, UCR2);
979 ucr3 = imx_uart_readl(sport, UCR3);
980 ucr4 = imx_uart_readl(sport, UCR4);
981
982 /*
983 * Even if a condition is true that can trigger an irq only handle it if
984 * the respective irq source is enabled. This prevents some undesired
985 * actions, for example if a character that sits in the RX FIFO and that
986 * should be fetched via DMA is tried to be fetched using PIO. Or the
987 * receiver is currently off and so reading from URXD0 results in an
988 * exception. So just mask the (raw) status bits for disabled irqs.
989 */
990 if ((ucr1 & UCR1_RRDYEN) == 0)
991 usr1 &= ~USR1_RRDY;
992 if ((ucr2 & UCR2_ATEN) == 0)
993 usr1 &= ~USR1_AGTIM;
994 if ((ucr1 & UCR1_TRDYEN) == 0)
995 usr1 &= ~USR1_TRDY;
996 if ((ucr4 & UCR4_TCEN) == 0)
997 usr2 &= ~USR2_TXDC;
998 if ((ucr3 & UCR3_DTRDEN) == 0)
999 usr1 &= ~USR1_DTRD;
1000 if ((ucr1 & UCR1_RTSDEN) == 0)
1001 usr1 &= ~USR1_RTSD;
1002 if ((ucr3 & UCR3_AWAKEN) == 0)
1003 usr1 &= ~USR1_AWAKE;
1004 if ((ucr4 & UCR4_OREN) == 0)
1005 usr2 &= ~USR2_ORE;
1006
1007 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1008 imx_uart_writel(sport, USR1_AGTIM, USR1);
1009
1010 __imx_uart_rxint(irq, dev_id);
1011 ret = IRQ_HANDLED;
1012 }
1013
1014 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1015 imx_uart_transmit_buffer(sport);
1016 ret = IRQ_HANDLED;
1017 }
1018
1019 if (usr1 & USR1_DTRD) {
1020 imx_uart_writel(sport, USR1_DTRD, USR1);
1021
1022 imx_uart_mctrl_check(sport);
1023
1024 ret = IRQ_HANDLED;
1025 }
1026
1027 if (usr1 & USR1_RTSD) {
1028 __imx_uart_rtsint(irq, dev_id);
1029 ret = IRQ_HANDLED;
1030 }
1031
1032 if (usr1 & USR1_AWAKE) {
1033 imx_uart_writel(sport, USR1_AWAKE, USR1);
1034 ret = IRQ_HANDLED;
1035 }
1036
1037 if (usr2 & USR2_ORE) {
1038 sport->port.icount.overrun++;
1039 imx_uart_writel(sport, USR2_ORE, USR2);
1040 ret = IRQ_HANDLED;
1041 }
1042
1043 uart_port_unlock(&sport->port);
1044
1045 return ret;
1046}
1047
1048/*
1049 * Return TIOCSER_TEMT when transmitter is not busy.
1050 */
1051static unsigned int imx_uart_tx_empty(struct uart_port *port)
1052{
1053 struct imx_port *sport = (struct imx_port *)port;
1054 unsigned int ret;
1055
1056 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1057
1058 /* If the TX DMA is working, return 0. */
1059 if (sport->dma_is_txing)
1060 ret = 0;
1061
1062 return ret;
1063}
1064
1065/* called with port.lock taken and irqs off */
1066static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1067{
1068 struct imx_port *sport = (struct imx_port *)port;
1069 unsigned int ret = imx_uart_get_hwmctrl(sport);
1070
1071 mctrl_gpio_get(sport->gpios, &ret);
1072
1073 return ret;
1074}
1075
1076/* called with port.lock taken and irqs off */
1077static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1078{
1079 struct imx_port *sport = (struct imx_port *)port;
1080 u32 ucr3, uts;
1081
1082 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1083 u32 ucr2;
1084
1085 /*
1086 * Turn off autoRTS if RTS is lowered and restore autoRTS
1087 * setting if RTS is raised.
1088 */
1089 ucr2 = imx_uart_readl(sport, UCR2);
1090 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1091 if (mctrl & TIOCM_RTS) {
1092 ucr2 |= UCR2_CTS;
1093 /*
1094 * UCR2_IRTS is unset if and only if the port is
1095 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1096 * to get the state to restore to.
1097 */
1098 if (!(ucr2 & UCR2_IRTS))
1099 ucr2 |= UCR2_CTSC;
1100 }
1101 imx_uart_writel(sport, ucr2, UCR2);
1102 }
1103
1104 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1105 if (!(mctrl & TIOCM_DTR))
1106 ucr3 |= UCR3_DSR;
1107 imx_uart_writel(sport, ucr3, UCR3);
1108
1109 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1110 if (mctrl & TIOCM_LOOP)
1111 uts |= UTS_LOOP;
1112 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1113
1114 mctrl_gpio_set(sport->gpios, mctrl);
1115}
1116
1117/*
1118 * Interrupts always disabled.
1119 */
1120static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1121{
1122 struct imx_port *sport = (struct imx_port *)port;
1123 unsigned long flags;
1124 u32 ucr1;
1125
1126 uart_port_lock_irqsave(&sport->port, &flags);
1127
1128 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1129
1130 if (break_state != 0)
1131 ucr1 |= UCR1_SNDBRK;
1132
1133 imx_uart_writel(sport, ucr1, UCR1);
1134
1135 uart_port_unlock_irqrestore(&sport->port, flags);
1136}
1137
1138/*
1139 * This is our per-port timeout handler, for checking the
1140 * modem status signals.
1141 */
1142static void imx_uart_timeout(struct timer_list *t)
1143{
1144 struct imx_port *sport = from_timer(sport, t, timer);
1145 unsigned long flags;
1146
1147 if (sport->port.state) {
1148 uart_port_lock_irqsave(&sport->port, &flags);
1149 imx_uart_mctrl_check(sport);
1150 uart_port_unlock_irqrestore(&sport->port, flags);
1151
1152 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1153 }
1154}
1155
1156/*
1157 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1158 * [1] the RX DMA buffer is full.
1159 * [2] the aging timer expires
1160 *
1161 * Condition [2] is triggered when a character has been sitting in the FIFO
1162 * for at least 8 byte durations.
1163 */
1164static void imx_uart_dma_rx_callback(void *data)
1165{
1166 struct imx_port *sport = data;
1167 struct dma_chan *chan = sport->dma_chan_rx;
1168 struct scatterlist *sgl = &sport->rx_sgl;
1169 struct tty_port *port = &sport->port.state->port;
1170 struct dma_tx_state state;
1171 struct circ_buf *rx_ring = &sport->rx_ring;
1172 enum dma_status status;
1173 unsigned int w_bytes = 0;
1174 unsigned int r_bytes;
1175 unsigned int bd_size;
1176
1177 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1178
1179 if (status == DMA_ERROR) {
1180 uart_port_lock(&sport->port);
1181 imx_uart_clear_rx_errors(sport);
1182 uart_port_unlock(&sport->port);
1183 return;
1184 }
1185
1186 /*
1187 * The state-residue variable represents the empty space
1188 * relative to the entire buffer. Taking this in consideration
1189 * the head is always calculated base on the buffer total
1190 * length - DMA transaction residue. The UART script from the
1191 * SDMA firmware will jump to the next buffer descriptor,
1192 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1193 * Taking this in consideration the tail is always at the
1194 * beginning of the buffer descriptor that contains the head.
1195 */
1196
1197 /* Calculate the head */
1198 rx_ring->head = sg_dma_len(sgl) - state.residue;
1199
1200 /* Calculate the tail. */
1201 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1202 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1203
1204 if (rx_ring->head <= sg_dma_len(sgl) &&
1205 rx_ring->head > rx_ring->tail) {
1206
1207 /* Move data from tail to head */
1208 r_bytes = rx_ring->head - rx_ring->tail;
1209
1210 /* If we received something, check for 0xff flood */
1211 uart_port_lock(&sport->port);
1212 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1213 uart_port_unlock(&sport->port);
1214
1215 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1216
1217 /* CPU claims ownership of RX DMA buffer */
1218 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1219 DMA_FROM_DEVICE);
1220
1221 w_bytes = tty_insert_flip_string(port,
1222 sport->rx_buf + rx_ring->tail, r_bytes);
1223
1224 /* UART retrieves ownership of RX DMA buffer */
1225 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1226 DMA_FROM_DEVICE);
1227
1228 if (w_bytes != r_bytes)
1229 sport->port.icount.buf_overrun++;
1230
1231 sport->port.icount.rx += w_bytes;
1232 }
1233 } else {
1234 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1235 WARN_ON(rx_ring->head <= rx_ring->tail);
1236 }
1237
1238 if (w_bytes) {
1239 tty_flip_buffer_push(port);
1240 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1241 }
1242}
1243
1244static int imx_uart_start_rx_dma(struct imx_port *sport)
1245{
1246 struct scatterlist *sgl = &sport->rx_sgl;
1247 struct dma_chan *chan = sport->dma_chan_rx;
1248 struct device *dev = sport->port.dev;
1249 struct dma_async_tx_descriptor *desc;
1250 int ret;
1251
1252 sport->rx_ring.head = 0;
1253 sport->rx_ring.tail = 0;
1254
1255 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1256 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1257 if (ret == 0) {
1258 dev_err(dev, "DMA mapping error for RX.\n");
1259 return -EINVAL;
1260 }
1261
1262 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1263 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1264 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1265
1266 if (!desc) {
1267 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1268 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1269 return -EINVAL;
1270 }
1271 desc->callback = imx_uart_dma_rx_callback;
1272 desc->callback_param = sport;
1273
1274 dev_dbg(dev, "RX: prepare for the DMA.\n");
1275 sport->dma_is_rxing = 1;
1276 sport->rx_cookie = dmaengine_submit(desc);
1277 dma_async_issue_pending(chan);
1278 return 0;
1279}
1280
1281static void imx_uart_clear_rx_errors(struct imx_port *sport)
1282{
1283 struct tty_port *port = &sport->port.state->port;
1284 u32 usr1, usr2;
1285
1286 usr1 = imx_uart_readl(sport, USR1);
1287 usr2 = imx_uart_readl(sport, USR2);
1288
1289 if (usr2 & USR2_BRCD) {
1290 sport->port.icount.brk++;
1291 imx_uart_writel(sport, USR2_BRCD, USR2);
1292 uart_handle_break(&sport->port);
1293 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1294 sport->port.icount.buf_overrun++;
1295 tty_flip_buffer_push(port);
1296 } else {
1297 if (usr1 & USR1_FRAMERR) {
1298 sport->port.icount.frame++;
1299 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1300 } else if (usr1 & USR1_PARITYERR) {
1301 sport->port.icount.parity++;
1302 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1303 }
1304 }
1305
1306 if (usr2 & USR2_ORE) {
1307 sport->port.icount.overrun++;
1308 imx_uart_writel(sport, USR2_ORE, USR2);
1309 }
1310
1311 sport->idle_counter = 0;
1312
1313}
1314
1315#define TXTL_DEFAULT 2 /* reset default */
1316#define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1317#define TXTL_DMA 8 /* DMA burst setting */
1318#define RXTL_DMA 9 /* DMA burst setting */
1319
1320static void imx_uart_setup_ufcr(struct imx_port *sport,
1321 unsigned char txwl, unsigned char rxwl)
1322{
1323 unsigned int val;
1324
1325 /* set receiver / transmitter trigger level */
1326 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1327 val |= txwl << UFCR_TXTL_SHF | rxwl;
1328 imx_uart_writel(sport, val, UFCR);
1329}
1330
1331static void imx_uart_dma_exit(struct imx_port *sport)
1332{
1333 if (sport->dma_chan_rx) {
1334 dmaengine_terminate_sync(sport->dma_chan_rx);
1335 dma_release_channel(sport->dma_chan_rx);
1336 sport->dma_chan_rx = NULL;
1337 sport->rx_cookie = -EINVAL;
1338 kfree(sport->rx_buf);
1339 sport->rx_buf = NULL;
1340 }
1341
1342 if (sport->dma_chan_tx) {
1343 dmaengine_terminate_sync(sport->dma_chan_tx);
1344 dma_release_channel(sport->dma_chan_tx);
1345 sport->dma_chan_tx = NULL;
1346 }
1347}
1348
1349static int imx_uart_dma_init(struct imx_port *sport)
1350{
1351 struct dma_slave_config slave_config = {};
1352 struct device *dev = sport->port.dev;
1353 struct dma_chan *chan;
1354 int ret;
1355
1356 /* Prepare for RX : */
1357 chan = dma_request_chan(dev, "rx");
1358 if (IS_ERR(chan)) {
1359 dev_dbg(dev, "cannot get the DMA channel.\n");
1360 sport->dma_chan_rx = NULL;
1361 ret = PTR_ERR(chan);
1362 goto err;
1363 }
1364 sport->dma_chan_rx = chan;
1365
1366 slave_config.direction = DMA_DEV_TO_MEM;
1367 slave_config.src_addr = sport->port.mapbase + URXD0;
1368 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1369 /* one byte less than the watermark level to enable the aging timer */
1370 slave_config.src_maxburst = RXTL_DMA - 1;
1371 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1372 if (ret) {
1373 dev_err(dev, "error in RX dma configuration.\n");
1374 goto err;
1375 }
1376
1377 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1378 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1379 if (!sport->rx_buf) {
1380 ret = -ENOMEM;
1381 goto err;
1382 }
1383 sport->rx_ring.buf = sport->rx_buf;
1384
1385 /* Prepare for TX : */
1386 chan = dma_request_chan(dev, "tx");
1387 if (IS_ERR(chan)) {
1388 dev_err(dev, "cannot get the TX DMA channel!\n");
1389 sport->dma_chan_tx = NULL;
1390 ret = PTR_ERR(chan);
1391 goto err;
1392 }
1393 sport->dma_chan_tx = chan;
1394
1395 slave_config.direction = DMA_MEM_TO_DEV;
1396 slave_config.dst_addr = sport->port.mapbase + URTX0;
1397 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1398 slave_config.dst_maxburst = TXTL_DMA;
1399 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1400 if (ret) {
1401 dev_err(dev, "error in TX dma configuration.");
1402 goto err;
1403 }
1404
1405 return 0;
1406err:
1407 imx_uart_dma_exit(sport);
1408 return ret;
1409}
1410
1411static void imx_uart_enable_dma(struct imx_port *sport)
1412{
1413 u32 ucr1;
1414
1415 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1416
1417 /* set UCR1 */
1418 ucr1 = imx_uart_readl(sport, UCR1);
1419 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1420 imx_uart_writel(sport, ucr1, UCR1);
1421
1422 sport->dma_is_enabled = 1;
1423}
1424
1425static void imx_uart_disable_dma(struct imx_port *sport)
1426{
1427 u32 ucr1;
1428
1429 /* clear UCR1 */
1430 ucr1 = imx_uart_readl(sport, UCR1);
1431 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1432 imx_uart_writel(sport, ucr1, UCR1);
1433
1434 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1435
1436 sport->dma_is_enabled = 0;
1437}
1438
1439/* half the RX buffer size */
1440#define CTSTL 16
1441
1442static int imx_uart_startup(struct uart_port *port)
1443{
1444 struct imx_port *sport = (struct imx_port *)port;
1445 int retval;
1446 unsigned long flags;
1447 int dma_is_inited = 0;
1448 u32 ucr1, ucr2, ucr3, ucr4;
1449
1450 retval = clk_prepare_enable(sport->clk_per);
1451 if (retval)
1452 return retval;
1453 retval = clk_prepare_enable(sport->clk_ipg);
1454 if (retval) {
1455 clk_disable_unprepare(sport->clk_per);
1456 return retval;
1457 }
1458
1459 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1460
1461 /* disable the DREN bit (Data Ready interrupt enable) before
1462 * requesting IRQs
1463 */
1464 ucr4 = imx_uart_readl(sport, UCR4);
1465
1466 /* set the trigger level for CTS */
1467 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1468 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1469
1470 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1471
1472 /* Can we enable the DMA support? */
1473 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
1474 lockdep_set_subclass(&port->lock, 1);
1475 dma_is_inited = 1;
1476 }
1477
1478 uart_port_lock_irqsave(&sport->port, &flags);
1479
1480 /* Reset fifo's and state machines */
1481 imx_uart_soft_reset(sport);
1482
1483 /*
1484 * Finally, clear and enable interrupts
1485 */
1486 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1487 imx_uart_writel(sport, USR2_ORE, USR2);
1488
1489 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1490 ucr1 |= UCR1_UARTEN;
1491 if (sport->have_rtscts)
1492 ucr1 |= UCR1_RTSDEN;
1493
1494 imx_uart_writel(sport, ucr1, UCR1);
1495
1496 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1497 if (!dma_is_inited)
1498 ucr4 |= UCR4_OREN;
1499 if (sport->inverted_rx)
1500 ucr4 |= UCR4_INVR;
1501 imx_uart_writel(sport, ucr4, UCR4);
1502
1503 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1504 /*
1505 * configure tx polarity before enabling tx
1506 */
1507 if (sport->inverted_tx)
1508 ucr3 |= UCR3_INVT;
1509
1510 if (!imx_uart_is_imx1(sport)) {
1511 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1512
1513 if (sport->dte_mode)
1514 /* disable broken interrupts */
1515 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1516 }
1517 imx_uart_writel(sport, ucr3, UCR3);
1518
1519 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1520 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1521 if (!sport->have_rtscts)
1522 ucr2 |= UCR2_IRTS;
1523 /*
1524 * make sure the edge sensitive RTS-irq is disabled,
1525 * we're using RTSD instead.
1526 */
1527 if (!imx_uart_is_imx1(sport))
1528 ucr2 &= ~UCR2_RTSEN;
1529 imx_uart_writel(sport, ucr2, UCR2);
1530
1531 /*
1532 * Enable modem status interrupts
1533 */
1534 imx_uart_enable_ms(&sport->port);
1535
1536 if (dma_is_inited) {
1537 imx_uart_enable_dma(sport);
1538 imx_uart_start_rx_dma(sport);
1539 } else {
1540 ucr1 = imx_uart_readl(sport, UCR1);
1541 ucr1 |= UCR1_RRDYEN;
1542 imx_uart_writel(sport, ucr1, UCR1);
1543
1544 ucr2 = imx_uart_readl(sport, UCR2);
1545 ucr2 |= UCR2_ATEN;
1546 imx_uart_writel(sport, ucr2, UCR2);
1547 }
1548
1549 imx_uart_disable_loopback_rs485(sport);
1550
1551 uart_port_unlock_irqrestore(&sport->port, flags);
1552
1553 return 0;
1554}
1555
1556static void imx_uart_shutdown(struct uart_port *port)
1557{
1558 struct imx_port *sport = (struct imx_port *)port;
1559 unsigned long flags;
1560 u32 ucr1, ucr2, ucr4, uts;
1561
1562 if (sport->dma_is_enabled) {
1563 dmaengine_terminate_sync(sport->dma_chan_tx);
1564 if (sport->dma_is_txing) {
1565 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1566 sport->dma_tx_nents, DMA_TO_DEVICE);
1567 sport->dma_is_txing = 0;
1568 }
1569 dmaengine_terminate_sync(sport->dma_chan_rx);
1570 if (sport->dma_is_rxing) {
1571 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1572 1, DMA_FROM_DEVICE);
1573 sport->dma_is_rxing = 0;
1574 }
1575
1576 uart_port_lock_irqsave(&sport->port, &flags);
1577 imx_uart_stop_tx(port);
1578 imx_uart_stop_rx(port);
1579 imx_uart_disable_dma(sport);
1580 uart_port_unlock_irqrestore(&sport->port, flags);
1581 imx_uart_dma_exit(sport);
1582 }
1583
1584 mctrl_gpio_disable_ms(sport->gpios);
1585
1586 uart_port_lock_irqsave(&sport->port, &flags);
1587 ucr2 = imx_uart_readl(sport, UCR2);
1588 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1589 imx_uart_writel(sport, ucr2, UCR2);
1590 uart_port_unlock_irqrestore(&sport->port, flags);
1591
1592 /*
1593 * Stop our timer.
1594 */
1595 del_timer_sync(&sport->timer);
1596
1597 /*
1598 * Disable all interrupts, port and break condition.
1599 */
1600
1601 uart_port_lock_irqsave(&sport->port, &flags);
1602
1603 ucr1 = imx_uart_readl(sport, UCR1);
1604 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1605 UCR1_ATDMAEN | UCR1_SNDBRK);
1606 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1607 if (port->rs485.flags & SER_RS485_ENABLED &&
1608 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1609 sport->have_rtscts && !sport->have_rtsgpio) {
1610 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1611 uts |= UTS_LOOP;
1612 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1613 ucr1 |= UCR1_UARTEN;
1614 } else {
1615 ucr1 &= ~UCR1_UARTEN;
1616 }
1617 imx_uart_writel(sport, ucr1, UCR1);
1618
1619 ucr4 = imx_uart_readl(sport, UCR4);
1620 ucr4 &= ~UCR4_TCEN;
1621 imx_uart_writel(sport, ucr4, UCR4);
1622
1623 uart_port_unlock_irqrestore(&sport->port, flags);
1624
1625 clk_disable_unprepare(sport->clk_per);
1626 clk_disable_unprepare(sport->clk_ipg);
1627}
1628
1629/* called with port.lock taken and irqs off */
1630static void imx_uart_flush_buffer(struct uart_port *port)
1631{
1632 struct imx_port *sport = (struct imx_port *)port;
1633 struct scatterlist *sgl = &sport->tx_sgl[0];
1634
1635 if (!sport->dma_chan_tx)
1636 return;
1637
1638 sport->tx_bytes = 0;
1639 dmaengine_terminate_all(sport->dma_chan_tx);
1640 if (sport->dma_is_txing) {
1641 u32 ucr1;
1642
1643 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1644 DMA_TO_DEVICE);
1645 ucr1 = imx_uart_readl(sport, UCR1);
1646 ucr1 &= ~UCR1_TXDMAEN;
1647 imx_uart_writel(sport, ucr1, UCR1);
1648 sport->dma_is_txing = 0;
1649 }
1650
1651 imx_uart_soft_reset(sport);
1652
1653}
1654
1655static void
1656imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1657 const struct ktermios *old)
1658{
1659 struct imx_port *sport = (struct imx_port *)port;
1660 unsigned long flags;
1661 u32 ucr2, old_ucr2, ufcr;
1662 unsigned int baud, quot;
1663 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1664 unsigned long div;
1665 unsigned long num, denom, old_ubir, old_ubmr;
1666 uint64_t tdiv64;
1667
1668 /*
1669 * We only support CS7 and CS8.
1670 */
1671 while ((termios->c_cflag & CSIZE) != CS7 &&
1672 (termios->c_cflag & CSIZE) != CS8) {
1673 termios->c_cflag &= ~CSIZE;
1674 termios->c_cflag |= old_csize;
1675 old_csize = CS8;
1676 }
1677
1678 del_timer_sync(&sport->timer);
1679
1680 /*
1681 * Ask the core to calculate the divisor for us.
1682 */
1683 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1684 quot = uart_get_divisor(port, baud);
1685
1686 uart_port_lock_irqsave(&sport->port, &flags);
1687
1688 /*
1689 * Read current UCR2 and save it for future use, then clear all the bits
1690 * except those we will or may need to preserve.
1691 */
1692 old_ucr2 = imx_uart_readl(sport, UCR2);
1693 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1694
1695 ucr2 |= UCR2_SRST | UCR2_IRTS;
1696 if ((termios->c_cflag & CSIZE) == CS8)
1697 ucr2 |= UCR2_WS;
1698
1699 if (!sport->have_rtscts)
1700 termios->c_cflag &= ~CRTSCTS;
1701
1702 if (port->rs485.flags & SER_RS485_ENABLED) {
1703 /*
1704 * RTS is mandatory for rs485 operation, so keep
1705 * it under manual control and keep transmitter
1706 * disabled.
1707 */
1708 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1709 imx_uart_rts_active(sport, &ucr2);
1710 else
1711 imx_uart_rts_inactive(sport, &ucr2);
1712
1713 } else if (termios->c_cflag & CRTSCTS) {
1714 /*
1715 * Only let receiver control RTS output if we were not requested
1716 * to have RTS inactive (which then should take precedence).
1717 */
1718 if (ucr2 & UCR2_CTS)
1719 ucr2 |= UCR2_CTSC;
1720 }
1721
1722 if (termios->c_cflag & CRTSCTS)
1723 ucr2 &= ~UCR2_IRTS;
1724 if (termios->c_cflag & CSTOPB)
1725 ucr2 |= UCR2_STPB;
1726 if (termios->c_cflag & PARENB) {
1727 ucr2 |= UCR2_PREN;
1728 if (termios->c_cflag & PARODD)
1729 ucr2 |= UCR2_PROE;
1730 }
1731
1732 sport->port.read_status_mask = 0;
1733 if (termios->c_iflag & INPCK)
1734 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1735 if (termios->c_iflag & (BRKINT | PARMRK))
1736 sport->port.read_status_mask |= URXD_BRK;
1737
1738 /*
1739 * Characters to ignore
1740 */
1741 sport->port.ignore_status_mask = 0;
1742 if (termios->c_iflag & IGNPAR)
1743 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1744 if (termios->c_iflag & IGNBRK) {
1745 sport->port.ignore_status_mask |= URXD_BRK;
1746 /*
1747 * If we're ignoring parity and break indicators,
1748 * ignore overruns too (for real raw support).
1749 */
1750 if (termios->c_iflag & IGNPAR)
1751 sport->port.ignore_status_mask |= URXD_OVRRUN;
1752 }
1753
1754 if ((termios->c_cflag & CREAD) == 0)
1755 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1756
1757 /*
1758 * Update the per-port timeout.
1759 */
1760 uart_update_timeout(port, termios->c_cflag, baud);
1761
1762 /* custom-baudrate handling */
1763 div = sport->port.uartclk / (baud * 16);
1764 if (baud == 38400 && quot != div)
1765 baud = sport->port.uartclk / (quot * 16);
1766
1767 div = sport->port.uartclk / (baud * 16);
1768 if (div > 7)
1769 div = 7;
1770 if (!div)
1771 div = 1;
1772
1773 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1774 1 << 16, 1 << 16, &num, &denom);
1775
1776 tdiv64 = sport->port.uartclk;
1777 tdiv64 *= num;
1778 do_div(tdiv64, denom * 16 * div);
1779 tty_termios_encode_baud_rate(termios,
1780 (speed_t)tdiv64, (speed_t)tdiv64);
1781
1782 num -= 1;
1783 denom -= 1;
1784
1785 ufcr = imx_uart_readl(sport, UFCR);
1786 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1787 imx_uart_writel(sport, ufcr, UFCR);
1788
1789 /*
1790 * Two registers below should always be written both and in this
1791 * particular order. One consequence is that we need to check if any of
1792 * them changes and then update both. We do need the check for change
1793 * as even writing the same values seem to "restart"
1794 * transmission/receiving logic in the hardware, that leads to data
1795 * breakage even when rate doesn't in fact change. E.g., user switches
1796 * RTS/CTS handshake and suddenly gets broken bytes.
1797 */
1798 old_ubir = imx_uart_readl(sport, UBIR);
1799 old_ubmr = imx_uart_readl(sport, UBMR);
1800 if (old_ubir != num || old_ubmr != denom) {
1801 imx_uart_writel(sport, num, UBIR);
1802 imx_uart_writel(sport, denom, UBMR);
1803 }
1804
1805 if (!imx_uart_is_imx1(sport))
1806 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1807 IMX21_ONEMS);
1808
1809 imx_uart_writel(sport, ucr2, UCR2);
1810
1811 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1812 imx_uart_enable_ms(&sport->port);
1813
1814 uart_port_unlock_irqrestore(&sport->port, flags);
1815}
1816
1817static const char *imx_uart_type(struct uart_port *port)
1818{
1819 return port->type == PORT_IMX ? "IMX" : NULL;
1820}
1821
1822/*
1823 * Configure/autoconfigure the port.
1824 */
1825static void imx_uart_config_port(struct uart_port *port, int flags)
1826{
1827 if (flags & UART_CONFIG_TYPE)
1828 port->type = PORT_IMX;
1829}
1830
1831/*
1832 * Verify the new serial_struct (for TIOCSSERIAL).
1833 * The only change we allow are to the flags and type, and
1834 * even then only between PORT_IMX and PORT_UNKNOWN
1835 */
1836static int
1837imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1838{
1839 int ret = 0;
1840
1841 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1842 ret = -EINVAL;
1843 if (port->irq != ser->irq)
1844 ret = -EINVAL;
1845 if (ser->io_type != UPIO_MEM)
1846 ret = -EINVAL;
1847 if (port->uartclk / 16 != ser->baud_base)
1848 ret = -EINVAL;
1849 if (port->mapbase != (unsigned long)ser->iomem_base)
1850 ret = -EINVAL;
1851 if (port->iobase != ser->port)
1852 ret = -EINVAL;
1853 if (ser->hub6 != 0)
1854 ret = -EINVAL;
1855 return ret;
1856}
1857
1858#if defined(CONFIG_CONSOLE_POLL)
1859
1860static int imx_uart_poll_init(struct uart_port *port)
1861{
1862 struct imx_port *sport = (struct imx_port *)port;
1863 unsigned long flags;
1864 u32 ucr1, ucr2;
1865 int retval;
1866
1867 retval = clk_prepare_enable(sport->clk_ipg);
1868 if (retval)
1869 return retval;
1870 retval = clk_prepare_enable(sport->clk_per);
1871 if (retval)
1872 clk_disable_unprepare(sport->clk_ipg);
1873
1874 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1875
1876 uart_port_lock_irqsave(&sport->port, &flags);
1877
1878 /*
1879 * Be careful about the order of enabling bits here. First enable the
1880 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1881 * This prevents that a character that already sits in the RX fifo is
1882 * triggering an irq but the try to fetch it from there results in an
1883 * exception because UARTEN or RXEN is still off.
1884 */
1885 ucr1 = imx_uart_readl(sport, UCR1);
1886 ucr2 = imx_uart_readl(sport, UCR2);
1887
1888 if (imx_uart_is_imx1(sport))
1889 ucr1 |= IMX1_UCR1_UARTCLKEN;
1890
1891 ucr1 |= UCR1_UARTEN;
1892 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1893
1894 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1895 ucr2 &= ~UCR2_ATEN;
1896
1897 imx_uart_writel(sport, ucr1, UCR1);
1898 imx_uart_writel(sport, ucr2, UCR2);
1899
1900 /* now enable irqs */
1901 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1902 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1903
1904 uart_port_unlock_irqrestore(&sport->port, flags);
1905
1906 return 0;
1907}
1908
1909static int imx_uart_poll_get_char(struct uart_port *port)
1910{
1911 struct imx_port *sport = (struct imx_port *)port;
1912 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1913 return NO_POLL_CHAR;
1914
1915 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1916}
1917
1918static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1919{
1920 struct imx_port *sport = (struct imx_port *)port;
1921 unsigned int status;
1922
1923 /* drain */
1924 do {
1925 status = imx_uart_readl(sport, USR1);
1926 } while (~status & USR1_TRDY);
1927
1928 /* write */
1929 imx_uart_writel(sport, c, URTX0);
1930
1931 /* flush */
1932 do {
1933 status = imx_uart_readl(sport, USR2);
1934 } while (~status & USR2_TXDC);
1935}
1936#endif
1937
1938/* called with port.lock taken and irqs off or from .probe without locking */
1939static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1940 struct serial_rs485 *rs485conf)
1941{
1942 struct imx_port *sport = (struct imx_port *)port;
1943 u32 ucr2;
1944
1945 if (rs485conf->flags & SER_RS485_ENABLED) {
1946 /* Enable receiver if low-active RTS signal is requested */
1947 if (sport->have_rtscts && !sport->have_rtsgpio &&
1948 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1949 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1950
1951 /* disable transmitter */
1952 ucr2 = imx_uart_readl(sport, UCR2);
1953 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1954 imx_uart_rts_active(sport, &ucr2);
1955 else
1956 imx_uart_rts_inactive(sport, &ucr2);
1957 imx_uart_writel(sport, ucr2, UCR2);
1958 }
1959
1960 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1961 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1962 rs485conf->flags & SER_RS485_RX_DURING_TX)
1963 imx_uart_start_rx(port);
1964
1965 return 0;
1966}
1967
1968static const struct uart_ops imx_uart_pops = {
1969 .tx_empty = imx_uart_tx_empty,
1970 .set_mctrl = imx_uart_set_mctrl,
1971 .get_mctrl = imx_uart_get_mctrl,
1972 .stop_tx = imx_uart_stop_tx,
1973 .start_tx = imx_uart_start_tx,
1974 .stop_rx = imx_uart_stop_rx,
1975 .enable_ms = imx_uart_enable_ms,
1976 .break_ctl = imx_uart_break_ctl,
1977 .startup = imx_uart_startup,
1978 .shutdown = imx_uart_shutdown,
1979 .flush_buffer = imx_uart_flush_buffer,
1980 .set_termios = imx_uart_set_termios,
1981 .type = imx_uart_type,
1982 .config_port = imx_uart_config_port,
1983 .verify_port = imx_uart_verify_port,
1984#if defined(CONFIG_CONSOLE_POLL)
1985 .poll_init = imx_uart_poll_init,
1986 .poll_get_char = imx_uart_poll_get_char,
1987 .poll_put_char = imx_uart_poll_put_char,
1988#endif
1989};
1990
1991static struct imx_port *imx_uart_ports[UART_NR];
1992
1993#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
1994static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1995{
1996 struct imx_port *sport = (struct imx_port *)port;
1997
1998 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1999 barrier();
2000
2001 imx_uart_writel(sport, ch, URTX0);
2002}
2003
2004/*
2005 * Interrupts are disabled on entering
2006 */
2007static void
2008imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2009{
2010 struct imx_port *sport = imx_uart_ports[co->index];
2011 struct imx_port_ucrs old_ucr;
2012 unsigned long flags;
2013 unsigned int ucr1;
2014 int locked = 1;
2015
2016 if (sport->port.sysrq)
2017 locked = 0;
2018 else if (oops_in_progress)
2019 locked = uart_port_trylock_irqsave(&sport->port, &flags);
2020 else
2021 uart_port_lock_irqsave(&sport->port, &flags);
2022
2023 /*
2024 * First, save UCR1/2/3 and then disable interrupts
2025 */
2026 imx_uart_ucrs_save(sport, &old_ucr);
2027 ucr1 = old_ucr.ucr1;
2028
2029 if (imx_uart_is_imx1(sport))
2030 ucr1 |= IMX1_UCR1_UARTCLKEN;
2031 ucr1 |= UCR1_UARTEN;
2032 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2033
2034 imx_uart_writel(sport, ucr1, UCR1);
2035
2036 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2037
2038 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2039
2040 /*
2041 * Finally, wait for transmitter to become empty
2042 * and restore UCR1/2/3
2043 */
2044 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2045
2046 imx_uart_ucrs_restore(sport, &old_ucr);
2047
2048 if (locked)
2049 uart_port_unlock_irqrestore(&sport->port, flags);
2050}
2051
2052/*
2053 * If the port was already initialised (eg, by a boot loader),
2054 * try to determine the current setup.
2055 */
2056static void
2057imx_uart_console_get_options(struct imx_port *sport, int *baud,
2058 int *parity, int *bits)
2059{
2060
2061 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2062 /* ok, the port was enabled */
2063 unsigned int ucr2, ubir, ubmr, uartclk;
2064 unsigned int baud_raw;
2065 unsigned int ucfr_rfdiv;
2066
2067 ucr2 = imx_uart_readl(sport, UCR2);
2068
2069 *parity = 'n';
2070 if (ucr2 & UCR2_PREN) {
2071 if (ucr2 & UCR2_PROE)
2072 *parity = 'o';
2073 else
2074 *parity = 'e';
2075 }
2076
2077 if (ucr2 & UCR2_WS)
2078 *bits = 8;
2079 else
2080 *bits = 7;
2081
2082 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2083 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2084
2085 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2086 if (ucfr_rfdiv == 6)
2087 ucfr_rfdiv = 7;
2088 else
2089 ucfr_rfdiv = 6 - ucfr_rfdiv;
2090
2091 uartclk = clk_get_rate(sport->clk_per);
2092 uartclk /= ucfr_rfdiv;
2093
2094 { /*
2095 * The next code provides exact computation of
2096 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2097 * without need of float support or long long division,
2098 * which would be required to prevent 32bit arithmetic overflow
2099 */
2100 unsigned int mul = ubir + 1;
2101 unsigned int div = 16 * (ubmr + 1);
2102 unsigned int rem = uartclk % div;
2103
2104 baud_raw = (uartclk / div) * mul;
2105 baud_raw += (rem * mul + div / 2) / div;
2106 *baud = (baud_raw + 50) / 100 * 100;
2107 }
2108
2109 if (*baud != baud_raw)
2110 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2111 baud_raw, *baud);
2112 }
2113}
2114
2115static int
2116imx_uart_console_setup(struct console *co, char *options)
2117{
2118 struct imx_port *sport;
2119 int baud = 9600;
2120 int bits = 8;
2121 int parity = 'n';
2122 int flow = 'n';
2123 int retval;
2124
2125 /*
2126 * Check whether an invalid uart number has been specified, and
2127 * if so, search for the first available port that does have
2128 * console support.
2129 */
2130 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2131 co->index = 0;
2132 sport = imx_uart_ports[co->index];
2133 if (sport == NULL)
2134 return -ENODEV;
2135
2136 /* For setting the registers, we only need to enable the ipg clock. */
2137 retval = clk_prepare_enable(sport->clk_ipg);
2138 if (retval)
2139 goto error_console;
2140
2141 if (options)
2142 uart_parse_options(options, &baud, &parity, &bits, &flow);
2143 else
2144 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2145
2146 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2147
2148 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2149
2150 if (retval) {
2151 clk_disable_unprepare(sport->clk_ipg);
2152 goto error_console;
2153 }
2154
2155 retval = clk_prepare_enable(sport->clk_per);
2156 if (retval)
2157 clk_disable_unprepare(sport->clk_ipg);
2158
2159error_console:
2160 return retval;
2161}
2162
2163static int
2164imx_uart_console_exit(struct console *co)
2165{
2166 struct imx_port *sport = imx_uart_ports[co->index];
2167
2168 clk_disable_unprepare(sport->clk_per);
2169 clk_disable_unprepare(sport->clk_ipg);
2170
2171 return 0;
2172}
2173
2174static struct uart_driver imx_uart_uart_driver;
2175static struct console imx_uart_console = {
2176 .name = DEV_NAME,
2177 .write = imx_uart_console_write,
2178 .device = uart_console_device,
2179 .setup = imx_uart_console_setup,
2180 .exit = imx_uart_console_exit,
2181 .flags = CON_PRINTBUFFER,
2182 .index = -1,
2183 .data = &imx_uart_uart_driver,
2184};
2185
2186#define IMX_CONSOLE &imx_uart_console
2187
2188#else
2189#define IMX_CONSOLE NULL
2190#endif
2191
2192static struct uart_driver imx_uart_uart_driver = {
2193 .owner = THIS_MODULE,
2194 .driver_name = DRIVER_NAME,
2195 .dev_name = DEV_NAME,
2196 .major = SERIAL_IMX_MAJOR,
2197 .minor = MINOR_START,
2198 .nr = ARRAY_SIZE(imx_uart_ports),
2199 .cons = IMX_CONSOLE,
2200};
2201
2202static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2203{
2204 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2205 unsigned long flags;
2206
2207 uart_port_lock_irqsave(&sport->port, &flags);
2208 if (sport->tx_state == WAIT_AFTER_RTS)
2209 imx_uart_start_tx(&sport->port);
2210 uart_port_unlock_irqrestore(&sport->port, flags);
2211
2212 return HRTIMER_NORESTART;
2213}
2214
2215static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2216{
2217 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2218 unsigned long flags;
2219
2220 uart_port_lock_irqsave(&sport->port, &flags);
2221 if (sport->tx_state == WAIT_AFTER_SEND)
2222 imx_uart_stop_tx(&sport->port);
2223 uart_port_unlock_irqrestore(&sport->port, flags);
2224
2225 return HRTIMER_NORESTART;
2226}
2227
2228static const struct serial_rs485 imx_rs485_supported = {
2229 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2230 SER_RS485_RX_DURING_TX,
2231 .delay_rts_before_send = 1,
2232 .delay_rts_after_send = 1,
2233};
2234
2235/* Default RX DMA buffer configuration */
2236#define RX_DMA_PERIODS 16
2237#define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2238
2239static int imx_uart_probe(struct platform_device *pdev)
2240{
2241 struct device_node *np = pdev->dev.of_node;
2242 struct imx_port *sport;
2243 void __iomem *base;
2244 u32 dma_buf_conf[2];
2245 int ret = 0;
2246 u32 ucr1, ucr2, uts;
2247 struct resource *res;
2248 int txirq, rxirq, rtsirq;
2249
2250 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2251 if (!sport)
2252 return -ENOMEM;
2253
2254 sport->devdata = of_device_get_match_data(&pdev->dev);
2255
2256 ret = of_alias_get_id(np, "serial");
2257 if (ret < 0) {
2258 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2259 return ret;
2260 }
2261 sport->port.line = ret;
2262
2263 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2264 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2265
2266 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2267
2268 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2269
2270 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2271
2272 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2273
2274 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2275 sport->rx_period_length = dma_buf_conf[0];
2276 sport->rx_periods = dma_buf_conf[1];
2277 } else {
2278 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2279 sport->rx_periods = RX_DMA_PERIODS;
2280 }
2281
2282 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2283 dev_err(&pdev->dev, "serial%d out of range\n",
2284 sport->port.line);
2285 return -EINVAL;
2286 }
2287
2288 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2289 if (IS_ERR(base))
2290 return PTR_ERR(base);
2291
2292 rxirq = platform_get_irq(pdev, 0);
2293 if (rxirq < 0)
2294 return rxirq;
2295 txirq = platform_get_irq_optional(pdev, 1);
2296 rtsirq = platform_get_irq_optional(pdev, 2);
2297
2298 sport->port.dev = &pdev->dev;
2299 sport->port.mapbase = res->start;
2300 sport->port.membase = base;
2301 sport->port.type = PORT_IMX;
2302 sport->port.iotype = UPIO_MEM;
2303 sport->port.irq = rxirq;
2304 sport->port.fifosize = 32;
2305 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2306 sport->port.ops = &imx_uart_pops;
2307 sport->port.rs485_config = imx_uart_rs485_config;
2308 /* RTS is required to control the RS485 transmitter */
2309 if (sport->have_rtscts || sport->have_rtsgpio)
2310 sport->port.rs485_supported = imx_rs485_supported;
2311 sport->port.flags = UPF_BOOT_AUTOCONF;
2312 timer_setup(&sport->timer, imx_uart_timeout, 0);
2313
2314 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2315 if (IS_ERR(sport->gpios))
2316 return PTR_ERR(sport->gpios);
2317
2318 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2319 if (IS_ERR(sport->clk_ipg)) {
2320 ret = PTR_ERR(sport->clk_ipg);
2321 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2322 return ret;
2323 }
2324
2325 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2326 if (IS_ERR(sport->clk_per)) {
2327 ret = PTR_ERR(sport->clk_per);
2328 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2329 return ret;
2330 }
2331
2332 sport->port.uartclk = clk_get_rate(sport->clk_per);
2333
2334 /* For register access, we only need to enable the ipg clock. */
2335 ret = clk_prepare_enable(sport->clk_ipg);
2336 if (ret) {
2337 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2338 return ret;
2339 }
2340
2341 ret = uart_get_rs485_mode(&sport->port);
2342 if (ret)
2343 goto err_clk;
2344
2345 /*
2346 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2347 * signal cannot be set low during transmission in case the
2348 * receiver is off (limitation of the i.MX UART IP).
2349 */
2350 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2351 sport->have_rtscts && !sport->have_rtsgpio &&
2352 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2353 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2354 dev_err(&pdev->dev,
2355 "low-active RTS not possible when receiver is off, enabling receiver\n");
2356
2357 /* Disable interrupts before requesting them */
2358 ucr1 = imx_uart_readl(sport, UCR1);
2359 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2360 imx_uart_writel(sport, ucr1, UCR1);
2361
2362 /* Disable Ageing Timer interrupt */
2363 ucr2 = imx_uart_readl(sport, UCR2);
2364 ucr2 &= ~UCR2_ATEN;
2365 imx_uart_writel(sport, ucr2, UCR2);
2366
2367 /*
2368 * In case RS485 is enabled without GPIO RTS control, the UART IP
2369 * is used to control CTS signal. Keep both the UART and Receiver
2370 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2371 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2372 * data from being fed into the RX FIFO, enable loopback mode in
2373 * UTS register, which disconnects the RX path from external RXD
2374 * pin and connects it to the Transceiver, which is disabled, so
2375 * no data can be fed to the RX FIFO that way.
2376 */
2377 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2378 sport->have_rtscts && !sport->have_rtsgpio) {
2379 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2380 uts |= UTS_LOOP;
2381 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2382
2383 ucr1 = imx_uart_readl(sport, UCR1);
2384 ucr1 |= UCR1_UARTEN;
2385 imx_uart_writel(sport, ucr1, UCR1);
2386
2387 ucr2 = imx_uart_readl(sport, UCR2);
2388 ucr2 |= UCR2_RXEN;
2389 imx_uart_writel(sport, ucr2, UCR2);
2390 }
2391
2392 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2393 /*
2394 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2395 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2396 * and DCD (when they are outputs) or enables the respective
2397 * irqs. So set this bit early, i.e. before requesting irqs.
2398 */
2399 u32 ufcr = imx_uart_readl(sport, UFCR);
2400 if (!(ufcr & UFCR_DCEDTE))
2401 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2402
2403 /*
2404 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2405 * enabled later because they cannot be cleared
2406 * (confirmed on i.MX25) which makes them unusable.
2407 */
2408 imx_uart_writel(sport,
2409 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2410 UCR3);
2411
2412 } else {
2413 u32 ucr3 = UCR3_DSR;
2414 u32 ufcr = imx_uart_readl(sport, UFCR);
2415 if (ufcr & UFCR_DCEDTE)
2416 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2417
2418 if (!imx_uart_is_imx1(sport))
2419 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2420 imx_uart_writel(sport, ucr3, UCR3);
2421 }
2422
2423 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2424 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2425 sport->trigger_start_tx.function = imx_trigger_start_tx;
2426 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2427
2428 /*
2429 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2430 * chips only have one interrupt.
2431 */
2432 if (txirq > 0) {
2433 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2434 dev_name(&pdev->dev), sport);
2435 if (ret) {
2436 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2437 ret);
2438 goto err_clk;
2439 }
2440
2441 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2442 dev_name(&pdev->dev), sport);
2443 if (ret) {
2444 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2445 ret);
2446 goto err_clk;
2447 }
2448
2449 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2450 dev_name(&pdev->dev), sport);
2451 if (ret) {
2452 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2453 ret);
2454 goto err_clk;
2455 }
2456 } else {
2457 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2458 dev_name(&pdev->dev), sport);
2459 if (ret) {
2460 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2461 goto err_clk;
2462 }
2463 }
2464
2465 imx_uart_ports[sport->port.line] = sport;
2466
2467 platform_set_drvdata(pdev, sport);
2468
2469 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2470
2471err_clk:
2472 clk_disable_unprepare(sport->clk_ipg);
2473
2474 return ret;
2475}
2476
2477static void imx_uart_remove(struct platform_device *pdev)
2478{
2479 struct imx_port *sport = platform_get_drvdata(pdev);
2480
2481 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2482}
2483
2484static void imx_uart_restore_context(struct imx_port *sport)
2485{
2486 unsigned long flags;
2487
2488 uart_port_lock_irqsave(&sport->port, &flags);
2489 if (!sport->context_saved) {
2490 uart_port_unlock_irqrestore(&sport->port, flags);
2491 return;
2492 }
2493
2494 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2495 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2496 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2497 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2498 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2499 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2500 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2501 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2502 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2503 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2504 sport->context_saved = false;
2505 uart_port_unlock_irqrestore(&sport->port, flags);
2506}
2507
2508static void imx_uart_save_context(struct imx_port *sport)
2509{
2510 unsigned long flags;
2511
2512 /* Save necessary regs */
2513 uart_port_lock_irqsave(&sport->port, &flags);
2514 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2515 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2516 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2517 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2518 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2519 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2520 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2521 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2522 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2523 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2524 sport->context_saved = true;
2525 uart_port_unlock_irqrestore(&sport->port, flags);
2526}
2527
2528static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2529{
2530 u32 ucr3;
2531
2532 ucr3 = imx_uart_readl(sport, UCR3);
2533 if (on) {
2534 imx_uart_writel(sport, USR1_AWAKE, USR1);
2535 ucr3 |= UCR3_AWAKEN;
2536 } else {
2537 ucr3 &= ~UCR3_AWAKEN;
2538 }
2539 imx_uart_writel(sport, ucr3, UCR3);
2540
2541 if (sport->have_rtscts) {
2542 u32 ucr1 = imx_uart_readl(sport, UCR1);
2543 if (on) {
2544 imx_uart_writel(sport, USR1_RTSD, USR1);
2545 ucr1 |= UCR1_RTSDEN;
2546 } else {
2547 ucr1 &= ~UCR1_RTSDEN;
2548 }
2549 imx_uart_writel(sport, ucr1, UCR1);
2550 }
2551}
2552
2553static int imx_uart_suspend_noirq(struct device *dev)
2554{
2555 struct imx_port *sport = dev_get_drvdata(dev);
2556
2557 imx_uart_save_context(sport);
2558
2559 clk_disable(sport->clk_ipg);
2560
2561 pinctrl_pm_select_sleep_state(dev);
2562
2563 return 0;
2564}
2565
2566static int imx_uart_resume_noirq(struct device *dev)
2567{
2568 struct imx_port *sport = dev_get_drvdata(dev);
2569 int ret;
2570
2571 pinctrl_pm_select_default_state(dev);
2572
2573 ret = clk_enable(sport->clk_ipg);
2574 if (ret)
2575 return ret;
2576
2577 imx_uart_restore_context(sport);
2578
2579 return 0;
2580}
2581
2582static int imx_uart_suspend(struct device *dev)
2583{
2584 struct imx_port *sport = dev_get_drvdata(dev);
2585 int ret;
2586
2587 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2588 disable_irq(sport->port.irq);
2589
2590 ret = clk_prepare_enable(sport->clk_ipg);
2591 if (ret)
2592 return ret;
2593
2594 /* enable wakeup from i.MX UART */
2595 imx_uart_enable_wakeup(sport, true);
2596
2597 return 0;
2598}
2599
2600static int imx_uart_resume(struct device *dev)
2601{
2602 struct imx_port *sport = dev_get_drvdata(dev);
2603
2604 /* disable wakeup from i.MX UART */
2605 imx_uart_enable_wakeup(sport, false);
2606
2607 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2608 enable_irq(sport->port.irq);
2609
2610 clk_disable_unprepare(sport->clk_ipg);
2611
2612 return 0;
2613}
2614
2615static int imx_uart_freeze(struct device *dev)
2616{
2617 struct imx_port *sport = dev_get_drvdata(dev);
2618
2619 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2620
2621 return clk_prepare_enable(sport->clk_ipg);
2622}
2623
2624static int imx_uart_thaw(struct device *dev)
2625{
2626 struct imx_port *sport = dev_get_drvdata(dev);
2627
2628 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2629
2630 clk_disable_unprepare(sport->clk_ipg);
2631
2632 return 0;
2633}
2634
2635static const struct dev_pm_ops imx_uart_pm_ops = {
2636 .suspend_noirq = imx_uart_suspend_noirq,
2637 .resume_noirq = imx_uart_resume_noirq,
2638 .freeze_noirq = imx_uart_suspend_noirq,
2639 .thaw_noirq = imx_uart_resume_noirq,
2640 .restore_noirq = imx_uart_resume_noirq,
2641 .suspend = imx_uart_suspend,
2642 .resume = imx_uart_resume,
2643 .freeze = imx_uart_freeze,
2644 .thaw = imx_uart_thaw,
2645 .restore = imx_uart_thaw,
2646};
2647
2648static struct platform_driver imx_uart_platform_driver = {
2649 .probe = imx_uart_probe,
2650 .remove_new = imx_uart_remove,
2651
2652 .driver = {
2653 .name = "imx-uart",
2654 .of_match_table = imx_uart_dt_ids,
2655 .pm = &imx_uart_pm_ops,
2656 },
2657};
2658
2659static int __init imx_uart_init(void)
2660{
2661 int ret = uart_register_driver(&imx_uart_uart_driver);
2662
2663 if (ret)
2664 return ret;
2665
2666 ret = platform_driver_register(&imx_uart_platform_driver);
2667 if (ret != 0)
2668 uart_unregister_driver(&imx_uart_uart_driver);
2669
2670 return ret;
2671}
2672
2673static void __exit imx_uart_exit(void)
2674{
2675 platform_driver_unregister(&imx_uart_platform_driver);
2676 uart_unregister_driver(&imx_uart_uart_driver);
2677}
2678
2679module_init(imx_uart_init);
2680module_exit(imx_uart_exit);
2681
2682MODULE_AUTHOR("Sascha Hauer");
2683MODULE_DESCRIPTION("IMX generic serial port driver");
2684MODULE_LICENSE("GPL");
2685MODULE_ALIAS("platform:imx-uart");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#include <linux/module.h>
12#include <linux/ioport.h>
13#include <linux/init.h>
14#include <linux/console.h>
15#include <linux/sysrq.h>
16#include <linux/platform_device.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/ktime.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/rational.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/io.h>
30#include <linux/dma-mapping.h>
31
32#include <asm/irq.h>
33#include <linux/platform_data/serial-imx.h>
34#include <linux/platform_data/dma-imx.h>
35
36#include "serial_mctrl_gpio.h"
37
38/* Register definitions */
39#define URXD0 0x0 /* Receiver Register */
40#define URTX0 0x40 /* Transmitter Register */
41#define UCR1 0x80 /* Control Register 1 */
42#define UCR2 0x84 /* Control Register 2 */
43#define UCR3 0x88 /* Control Register 3 */
44#define UCR4 0x8c /* Control Register 4 */
45#define UFCR 0x90 /* FIFO Control Register */
46#define USR1 0x94 /* Status Register 1 */
47#define USR2 0x98 /* Status Register 2 */
48#define UESC 0x9c /* Escape Character Register */
49#define UTIM 0xa0 /* Escape Timer Register */
50#define UBIR 0xa4 /* BRM Incremental Register */
51#define UBMR 0xa8 /* BRM Modulator Register */
52#define UBRC 0xac /* Baud Rate Count Register */
53#define IMX21_ONEMS 0xb0 /* One Millisecond register */
54#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
55#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
56
57/* UART Control Register Bit Fields.*/
58#define URXD_DUMMY_READ (1<<16)
59#define URXD_CHARRDY (1<<15)
60#define URXD_ERR (1<<14)
61#define URXD_OVRRUN (1<<13)
62#define URXD_FRMERR (1<<12)
63#define URXD_BRK (1<<11)
64#define URXD_PRERR (1<<10)
65#define URXD_RX_DATA (0xFF<<0)
66#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
67#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
68#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
69#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
70#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
71#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
72#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
73#define UCR1_IREN (1<<7) /* Infrared interface enable */
74#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
75#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
76#define UCR1_SNDBRK (1<<4) /* Send break */
77#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
78#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
79#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
80#define UCR1_DOZE (1<<1) /* Doze */
81#define UCR1_UARTEN (1<<0) /* UART enabled */
82#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
83#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
84#define UCR2_CTSC (1<<13) /* CTS pin control */
85#define UCR2_CTS (1<<12) /* Clear to send */
86#define UCR2_ESCEN (1<<11) /* Escape enable */
87#define UCR2_PREN (1<<8) /* Parity enable */
88#define UCR2_PROE (1<<7) /* Parity odd/even */
89#define UCR2_STPB (1<<6) /* Stop */
90#define UCR2_WS (1<<5) /* Word size */
91#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
92#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
93#define UCR2_TXEN (1<<2) /* Transmitter enabled */
94#define UCR2_RXEN (1<<1) /* Receiver enabled */
95#define UCR2_SRST (1<<0) /* SW reset */
96#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
97#define UCR3_PARERREN (1<<12) /* Parity enable */
98#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
99#define UCR3_DSR (1<<10) /* Data set ready */
100#define UCR3_DCD (1<<9) /* Data carrier detect */
101#define UCR3_RI (1<<8) /* Ring indicator */
102#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
103#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
104#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
105#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
106#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
107#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
108#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
109#define UCR3_BPEN (1<<0) /* Preset registers enable */
110#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
111#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
112#define UCR4_INVR (1<<9) /* Inverted infrared reception */
113#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
114#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
115#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
116#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
117#define UCR4_IRSC (1<<5) /* IR special case */
118#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
119#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
120#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
121#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
122#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
123#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
124#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
125#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
126#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
127#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
128#define USR1_RTSS (1<<14) /* RTS pin status */
129#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
130#define USR1_RTSD (1<<12) /* RTS delta */
131#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
132#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
133#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
134#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
135#define USR1_DTRD (1<<7) /* DTR Delta */
136#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
137#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
138#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
139#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
140#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
141#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
142#define USR2_IDLE (1<<12) /* Idle condition */
143#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
144#define USR2_RIIN (1<<9) /* Ring Indicator Input */
145#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
146#define USR2_WAKE (1<<7) /* Wake */
147#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
148#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
149#define USR2_TXDC (1<<3) /* Transmitter complete */
150#define USR2_BRCD (1<<2) /* Break condition */
151#define USR2_ORE (1<<1) /* Overrun error */
152#define USR2_RDR (1<<0) /* Recv data ready */
153#define UTS_FRCPERR (1<<13) /* Force parity error */
154#define UTS_LOOP (1<<12) /* Loop tx and rx */
155#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
156#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
157#define UTS_TXFULL (1<<4) /* TxFIFO full */
158#define UTS_RXFULL (1<<3) /* RxFIFO full */
159#define UTS_SOFTRST (1<<0) /* Software reset */
160
161/* We've been assigned a range on the "Low-density serial ports" major */
162#define SERIAL_IMX_MAJOR 207
163#define MINOR_START 16
164#define DEV_NAME "ttymxc"
165
166/*
167 * This determines how often we check the modem status signals
168 * for any change. They generally aren't connected to an IRQ
169 * so we have to poll them. We also check immediately before
170 * filling the TX fifo incase CTS has been dropped.
171 */
172#define MCTRL_TIMEOUT (250*HZ/1000)
173
174#define DRIVER_NAME "IMX-uart"
175
176#define UART_NR 8
177
178/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
179enum imx_uart_type {
180 IMX1_UART,
181 IMX21_UART,
182 IMX53_UART,
183 IMX6Q_UART,
184};
185
186/* device type dependent stuff */
187struct imx_uart_data {
188 unsigned uts_reg;
189 enum imx_uart_type devtype;
190};
191
192enum imx_tx_state {
193 OFF,
194 WAIT_AFTER_RTS,
195 SEND,
196 WAIT_AFTER_SEND,
197};
198
199struct imx_port {
200 struct uart_port port;
201 struct timer_list timer;
202 unsigned int old_status;
203 unsigned int have_rtscts:1;
204 unsigned int have_rtsgpio:1;
205 unsigned int dte_mode:1;
206 unsigned int inverted_tx:1;
207 unsigned int inverted_rx:1;
208 struct clk *clk_ipg;
209 struct clk *clk_per;
210 const struct imx_uart_data *devdata;
211
212 struct mctrl_gpios *gpios;
213
214 /* shadow registers */
215 unsigned int ucr1;
216 unsigned int ucr2;
217 unsigned int ucr3;
218 unsigned int ucr4;
219 unsigned int ufcr;
220
221 /* DMA fields */
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
227 void *rx_buf;
228 struct circ_buf rx_ring;
229 unsigned int rx_periods;
230 dma_cookie_t rx_cookie;
231 unsigned int tx_bytes;
232 unsigned int dma_tx_nents;
233 unsigned int saved_reg[10];
234 bool context_saved;
235
236 enum imx_tx_state tx_state;
237 struct hrtimer trigger_start_tx;
238 struct hrtimer trigger_stop_tx;
239};
240
241struct imx_port_ucrs {
242 unsigned int ucr1;
243 unsigned int ucr2;
244 unsigned int ucr3;
245};
246
247static struct imx_uart_data imx_uart_devdata[] = {
248 [IMX1_UART] = {
249 .uts_reg = IMX1_UTS,
250 .devtype = IMX1_UART,
251 },
252 [IMX21_UART] = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX21_UART,
255 },
256 [IMX53_UART] = {
257 .uts_reg = IMX21_UTS,
258 .devtype = IMX53_UART,
259 },
260 [IMX6Q_UART] = {
261 .uts_reg = IMX21_UTS,
262 .devtype = IMX6Q_UART,
263 },
264};
265
266static const struct platform_device_id imx_uart_devtype[] = {
267 {
268 .name = "imx1-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
270 }, {
271 .name = "imx21-uart",
272 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
273 }, {
274 .name = "imx53-uart",
275 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
276 }, {
277 .name = "imx6q-uart",
278 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
279 }, {
280 /* sentinel */
281 }
282};
283MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
284
285static const struct of_device_id imx_uart_dt_ids[] = {
286 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
287 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
288 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
289 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
290 { /* sentinel */ }
291};
292MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
293
294static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
295{
296 switch (offset) {
297 case UCR1:
298 sport->ucr1 = val;
299 break;
300 case UCR2:
301 sport->ucr2 = val;
302 break;
303 case UCR3:
304 sport->ucr3 = val;
305 break;
306 case UCR4:
307 sport->ucr4 = val;
308 break;
309 case UFCR:
310 sport->ufcr = val;
311 break;
312 default:
313 break;
314 }
315 writel(val, sport->port.membase + offset);
316}
317
318static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
319{
320 switch (offset) {
321 case UCR1:
322 return sport->ucr1;
323 break;
324 case UCR2:
325 /*
326 * UCR2_SRST is the only bit in the cached registers that might
327 * differ from the value that was last written. As it only
328 * automatically becomes one after being cleared, reread
329 * conditionally.
330 */
331 if (!(sport->ucr2 & UCR2_SRST))
332 sport->ucr2 = readl(sport->port.membase + offset);
333 return sport->ucr2;
334 break;
335 case UCR3:
336 return sport->ucr3;
337 break;
338 case UCR4:
339 return sport->ucr4;
340 break;
341 case UFCR:
342 return sport->ufcr;
343 break;
344 default:
345 return readl(sport->port.membase + offset);
346 }
347}
348
349static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
350{
351 return sport->devdata->uts_reg;
352}
353
354static inline int imx_uart_is_imx1(struct imx_port *sport)
355{
356 return sport->devdata->devtype == IMX1_UART;
357}
358
359static inline int imx_uart_is_imx21(struct imx_port *sport)
360{
361 return sport->devdata->devtype == IMX21_UART;
362}
363
364static inline int imx_uart_is_imx53(struct imx_port *sport)
365{
366 return sport->devdata->devtype == IMX53_UART;
367}
368
369static inline int imx_uart_is_imx6q(struct imx_port *sport)
370{
371 return sport->devdata->devtype == IMX6Q_UART;
372}
373/*
374 * Save and restore functions for UCR1, UCR2 and UCR3 registers
375 */
376#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
377static void imx_uart_ucrs_save(struct imx_port *sport,
378 struct imx_port_ucrs *ucr)
379{
380 /* save control registers */
381 ucr->ucr1 = imx_uart_readl(sport, UCR1);
382 ucr->ucr2 = imx_uart_readl(sport, UCR2);
383 ucr->ucr3 = imx_uart_readl(sport, UCR3);
384}
385
386static void imx_uart_ucrs_restore(struct imx_port *sport,
387 struct imx_port_ucrs *ucr)
388{
389 /* restore control registers */
390 imx_uart_writel(sport, ucr->ucr1, UCR1);
391 imx_uart_writel(sport, ucr->ucr2, UCR2);
392 imx_uart_writel(sport, ucr->ucr3, UCR3);
393}
394#endif
395
396/* called with port.lock taken and irqs caller dependent */
397static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
398{
399 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
400
401 sport->port.mctrl |= TIOCM_RTS;
402 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
403}
404
405/* called with port.lock taken and irqs caller dependent */
406static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
407{
408 *ucr2 &= ~UCR2_CTSC;
409 *ucr2 |= UCR2_CTS;
410
411 sport->port.mctrl &= ~TIOCM_RTS;
412 mctrl_gpio_set(sport->gpios, sport->port.mctrl);
413}
414
415static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
416{
417 long sec = msec / MSEC_PER_SEC;
418 long nsec = (msec % MSEC_PER_SEC) * 1000000;
419 ktime_t t = ktime_set(sec, nsec);
420
421 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
422}
423
424/* called with port.lock taken and irqs off */
425static void imx_uart_start_rx(struct uart_port *port)
426{
427 struct imx_port *sport = (struct imx_port *)port;
428 unsigned int ucr1, ucr2;
429
430 ucr1 = imx_uart_readl(sport, UCR1);
431 ucr2 = imx_uart_readl(sport, UCR2);
432
433 ucr2 |= UCR2_RXEN;
434
435 if (sport->dma_is_enabled) {
436 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
437 } else {
438 ucr1 |= UCR1_RRDYEN;
439 ucr2 |= UCR2_ATEN;
440 }
441
442 /* Write UCR2 first as it includes RXEN */
443 imx_uart_writel(sport, ucr2, UCR2);
444 imx_uart_writel(sport, ucr1, UCR1);
445}
446
447/* called with port.lock taken and irqs off */
448static void imx_uart_stop_tx(struct uart_port *port)
449{
450 struct imx_port *sport = (struct imx_port *)port;
451 u32 ucr1, ucr4, usr2;
452
453 if (sport->tx_state == OFF)
454 return;
455
456 /*
457 * We are maybe in the SMP context, so if the DMA TX thread is running
458 * on other cpu, we have to wait for it to finish.
459 */
460 if (sport->dma_is_txing)
461 return;
462
463 ucr1 = imx_uart_readl(sport, UCR1);
464 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
465
466 usr2 = imx_uart_readl(sport, USR2);
467 if (!(usr2 & USR2_TXDC)) {
468 /* The shifter is still busy, so retry once TC triggers */
469 return;
470 }
471
472 ucr4 = imx_uart_readl(sport, UCR4);
473 ucr4 &= ~UCR4_TCEN;
474 imx_uart_writel(sport, ucr4, UCR4);
475
476 /* in rs485 mode disable transmitter */
477 if (port->rs485.flags & SER_RS485_ENABLED) {
478 if (sport->tx_state == SEND) {
479 sport->tx_state = WAIT_AFTER_SEND;
480 start_hrtimer_ms(&sport->trigger_stop_tx,
481 port->rs485.delay_rts_after_send);
482 return;
483 }
484
485 if (sport->tx_state == WAIT_AFTER_RTS ||
486 sport->tx_state == WAIT_AFTER_SEND) {
487 u32 ucr2;
488
489 hrtimer_try_to_cancel(&sport->trigger_start_tx);
490
491 ucr2 = imx_uart_readl(sport, UCR2);
492 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
493 imx_uart_rts_active(sport, &ucr2);
494 else
495 imx_uart_rts_inactive(sport, &ucr2);
496 imx_uart_writel(sport, ucr2, UCR2);
497
498 imx_uart_start_rx(port);
499
500 sport->tx_state = OFF;
501 }
502 } else {
503 sport->tx_state = OFF;
504 }
505}
506
507/* called with port.lock taken and irqs off */
508static void imx_uart_stop_rx(struct uart_port *port)
509{
510 struct imx_port *sport = (struct imx_port *)port;
511 u32 ucr1, ucr2;
512
513 ucr1 = imx_uart_readl(sport, UCR1);
514 ucr2 = imx_uart_readl(sport, UCR2);
515
516 if (sport->dma_is_enabled) {
517 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
518 } else {
519 ucr1 &= ~UCR1_RRDYEN;
520 ucr2 &= ~UCR2_ATEN;
521 }
522 imx_uart_writel(sport, ucr1, UCR1);
523
524 ucr2 &= ~UCR2_RXEN;
525 imx_uart_writel(sport, ucr2, UCR2);
526}
527
528/* called with port.lock taken and irqs off */
529static void imx_uart_enable_ms(struct uart_port *port)
530{
531 struct imx_port *sport = (struct imx_port *)port;
532
533 mod_timer(&sport->timer, jiffies);
534
535 mctrl_gpio_enable_ms(sport->gpios);
536}
537
538static void imx_uart_dma_tx(struct imx_port *sport);
539
540/* called with port.lock taken and irqs off */
541static inline void imx_uart_transmit_buffer(struct imx_port *sport)
542{
543 struct circ_buf *xmit = &sport->port.state->xmit;
544
545 if (sport->port.x_char) {
546 /* Send next char */
547 imx_uart_writel(sport, sport->port.x_char, URTX0);
548 sport->port.icount.tx++;
549 sport->port.x_char = 0;
550 return;
551 }
552
553 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
554 imx_uart_stop_tx(&sport->port);
555 return;
556 }
557
558 if (sport->dma_is_enabled) {
559 u32 ucr1;
560 /*
561 * We've just sent a X-char Ensure the TX DMA is enabled
562 * and the TX IRQ is disabled.
563 **/
564 ucr1 = imx_uart_readl(sport, UCR1);
565 ucr1 &= ~UCR1_TRDYEN;
566 if (sport->dma_is_txing) {
567 ucr1 |= UCR1_TXDMAEN;
568 imx_uart_writel(sport, ucr1, UCR1);
569 } else {
570 imx_uart_writel(sport, ucr1, UCR1);
571 imx_uart_dma_tx(sport);
572 }
573
574 return;
575 }
576
577 while (!uart_circ_empty(xmit) &&
578 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
579 /* send xmit->buf[xmit->tail]
580 * out the port here */
581 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
582 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
583 sport->port.icount.tx++;
584 }
585
586 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
587 uart_write_wakeup(&sport->port);
588
589 if (uart_circ_empty(xmit))
590 imx_uart_stop_tx(&sport->port);
591}
592
593static void imx_uart_dma_tx_callback(void *data)
594{
595 struct imx_port *sport = data;
596 struct scatterlist *sgl = &sport->tx_sgl[0];
597 struct circ_buf *xmit = &sport->port.state->xmit;
598 unsigned long flags;
599 u32 ucr1;
600
601 spin_lock_irqsave(&sport->port.lock, flags);
602
603 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
604
605 ucr1 = imx_uart_readl(sport, UCR1);
606 ucr1 &= ~UCR1_TXDMAEN;
607 imx_uart_writel(sport, ucr1, UCR1);
608
609 /* update the stat */
610 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
611 sport->port.icount.tx += sport->tx_bytes;
612
613 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
614
615 sport->dma_is_txing = 0;
616
617 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
618 uart_write_wakeup(&sport->port);
619
620 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
621 imx_uart_dma_tx(sport);
622 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
623 u32 ucr4 = imx_uart_readl(sport, UCR4);
624 ucr4 |= UCR4_TCEN;
625 imx_uart_writel(sport, ucr4, UCR4);
626 }
627
628 spin_unlock_irqrestore(&sport->port.lock, flags);
629}
630
631/* called with port.lock taken and irqs off */
632static void imx_uart_dma_tx(struct imx_port *sport)
633{
634 struct circ_buf *xmit = &sport->port.state->xmit;
635 struct scatterlist *sgl = sport->tx_sgl;
636 struct dma_async_tx_descriptor *desc;
637 struct dma_chan *chan = sport->dma_chan_tx;
638 struct device *dev = sport->port.dev;
639 u32 ucr1, ucr4;
640 int ret;
641
642 if (sport->dma_is_txing)
643 return;
644
645 ucr4 = imx_uart_readl(sport, UCR4);
646 ucr4 &= ~UCR4_TCEN;
647 imx_uart_writel(sport, ucr4, UCR4);
648
649 sport->tx_bytes = uart_circ_chars_pending(xmit);
650
651 if (xmit->tail < xmit->head || xmit->head == 0) {
652 sport->dma_tx_nents = 1;
653 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
654 } else {
655 sport->dma_tx_nents = 2;
656 sg_init_table(sgl, 2);
657 sg_set_buf(sgl, xmit->buf + xmit->tail,
658 UART_XMIT_SIZE - xmit->tail);
659 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
660 }
661
662 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
663 if (ret == 0) {
664 dev_err(dev, "DMA mapping error for TX.\n");
665 return;
666 }
667 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
668 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
669 if (!desc) {
670 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
671 DMA_TO_DEVICE);
672 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
673 return;
674 }
675 desc->callback = imx_uart_dma_tx_callback;
676 desc->callback_param = sport;
677
678 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
679 uart_circ_chars_pending(xmit));
680
681 ucr1 = imx_uart_readl(sport, UCR1);
682 ucr1 |= UCR1_TXDMAEN;
683 imx_uart_writel(sport, ucr1, UCR1);
684
685 /* fire it */
686 sport->dma_is_txing = 1;
687 dmaengine_submit(desc);
688 dma_async_issue_pending(chan);
689 return;
690}
691
692/* called with port.lock taken and irqs off */
693static void imx_uart_start_tx(struct uart_port *port)
694{
695 struct imx_port *sport = (struct imx_port *)port;
696 u32 ucr1;
697
698 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
699 return;
700
701 /*
702 * We cannot simply do nothing here if sport->tx_state == SEND already
703 * because UCR1_TXMPTYEN might already have been cleared in
704 * imx_uart_stop_tx(), but tx_state is still SEND.
705 */
706
707 if (port->rs485.flags & SER_RS485_ENABLED) {
708 if (sport->tx_state == OFF) {
709 u32 ucr2 = imx_uart_readl(sport, UCR2);
710 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
711 imx_uart_rts_active(sport, &ucr2);
712 else
713 imx_uart_rts_inactive(sport, &ucr2);
714 imx_uart_writel(sport, ucr2, UCR2);
715
716 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
717 imx_uart_stop_rx(port);
718
719 sport->tx_state = WAIT_AFTER_RTS;
720 start_hrtimer_ms(&sport->trigger_start_tx,
721 port->rs485.delay_rts_before_send);
722 return;
723 }
724
725 if (sport->tx_state == WAIT_AFTER_SEND
726 || sport->tx_state == WAIT_AFTER_RTS) {
727
728 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
729
730 /*
731 * Enable transmitter and shifter empty irq only if DMA
732 * is off. In the DMA case this is done in the
733 * tx-callback.
734 */
735 if (!sport->dma_is_enabled) {
736 u32 ucr4 = imx_uart_readl(sport, UCR4);
737 ucr4 |= UCR4_TCEN;
738 imx_uart_writel(sport, ucr4, UCR4);
739 }
740
741 sport->tx_state = SEND;
742 }
743 } else {
744 sport->tx_state = SEND;
745 }
746
747 if (!sport->dma_is_enabled) {
748 ucr1 = imx_uart_readl(sport, UCR1);
749 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
750 }
751
752 if (sport->dma_is_enabled) {
753 if (sport->port.x_char) {
754 /* We have X-char to send, so enable TX IRQ and
755 * disable TX DMA to let TX interrupt to send X-char */
756 ucr1 = imx_uart_readl(sport, UCR1);
757 ucr1 &= ~UCR1_TXDMAEN;
758 ucr1 |= UCR1_TRDYEN;
759 imx_uart_writel(sport, ucr1, UCR1);
760 return;
761 }
762
763 if (!uart_circ_empty(&port->state->xmit) &&
764 !uart_tx_stopped(port))
765 imx_uart_dma_tx(sport);
766 return;
767 }
768}
769
770static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
771{
772 struct imx_port *sport = dev_id;
773 u32 usr1;
774
775 imx_uart_writel(sport, USR1_RTSD, USR1);
776 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
777 uart_handle_cts_change(&sport->port, !!usr1);
778 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
779
780 return IRQ_HANDLED;
781}
782
783static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
784{
785 struct imx_port *sport = dev_id;
786 irqreturn_t ret;
787
788 spin_lock(&sport->port.lock);
789
790 ret = __imx_uart_rtsint(irq, dev_id);
791
792 spin_unlock(&sport->port.lock);
793
794 return ret;
795}
796
797static irqreturn_t imx_uart_txint(int irq, void *dev_id)
798{
799 struct imx_port *sport = dev_id;
800
801 spin_lock(&sport->port.lock);
802 imx_uart_transmit_buffer(sport);
803 spin_unlock(&sport->port.lock);
804 return IRQ_HANDLED;
805}
806
807static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
808{
809 struct imx_port *sport = dev_id;
810 unsigned int rx, flg, ignored = 0;
811 struct tty_port *port = &sport->port.state->port;
812
813 while (imx_uart_readl(sport, USR2) & USR2_RDR) {
814 u32 usr2;
815
816 flg = TTY_NORMAL;
817 sport->port.icount.rx++;
818
819 rx = imx_uart_readl(sport, URXD0);
820
821 usr2 = imx_uart_readl(sport, USR2);
822 if (usr2 & USR2_BRCD) {
823 imx_uart_writel(sport, USR2_BRCD, USR2);
824 if (uart_handle_break(&sport->port))
825 continue;
826 }
827
828 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
829 continue;
830
831 if (unlikely(rx & URXD_ERR)) {
832 if (rx & URXD_BRK)
833 sport->port.icount.brk++;
834 else if (rx & URXD_PRERR)
835 sport->port.icount.parity++;
836 else if (rx & URXD_FRMERR)
837 sport->port.icount.frame++;
838 if (rx & URXD_OVRRUN)
839 sport->port.icount.overrun++;
840
841 if (rx & sport->port.ignore_status_mask) {
842 if (++ignored > 100)
843 goto out;
844 continue;
845 }
846
847 rx &= (sport->port.read_status_mask | 0xFF);
848
849 if (rx & URXD_BRK)
850 flg = TTY_BREAK;
851 else if (rx & URXD_PRERR)
852 flg = TTY_PARITY;
853 else if (rx & URXD_FRMERR)
854 flg = TTY_FRAME;
855 if (rx & URXD_OVRRUN)
856 flg = TTY_OVERRUN;
857
858 sport->port.sysrq = 0;
859 }
860
861 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
862 goto out;
863
864 if (tty_insert_flip_char(port, rx, flg) == 0)
865 sport->port.icount.buf_overrun++;
866 }
867
868out:
869 tty_flip_buffer_push(port);
870
871 return IRQ_HANDLED;
872}
873
874static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
875{
876 struct imx_port *sport = dev_id;
877 irqreturn_t ret;
878
879 spin_lock(&sport->port.lock);
880
881 ret = __imx_uart_rxint(irq, dev_id);
882
883 spin_unlock(&sport->port.lock);
884
885 return ret;
886}
887
888static void imx_uart_clear_rx_errors(struct imx_port *sport);
889
890/*
891 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
892 */
893static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
894{
895 unsigned int tmp = TIOCM_DSR;
896 unsigned usr1 = imx_uart_readl(sport, USR1);
897 unsigned usr2 = imx_uart_readl(sport, USR2);
898
899 if (usr1 & USR1_RTSS)
900 tmp |= TIOCM_CTS;
901
902 /* in DCE mode DCDIN is always 0 */
903 if (!(usr2 & USR2_DCDIN))
904 tmp |= TIOCM_CAR;
905
906 if (sport->dte_mode)
907 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
908 tmp |= TIOCM_RI;
909
910 return tmp;
911}
912
913/*
914 * Handle any change of modem status signal since we were last called.
915 */
916static void imx_uart_mctrl_check(struct imx_port *sport)
917{
918 unsigned int status, changed;
919
920 status = imx_uart_get_hwmctrl(sport);
921 changed = status ^ sport->old_status;
922
923 if (changed == 0)
924 return;
925
926 sport->old_status = status;
927
928 if (changed & TIOCM_RI && status & TIOCM_RI)
929 sport->port.icount.rng++;
930 if (changed & TIOCM_DSR)
931 sport->port.icount.dsr++;
932 if (changed & TIOCM_CAR)
933 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
934 if (changed & TIOCM_CTS)
935 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
936
937 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
938}
939
940static irqreturn_t imx_uart_int(int irq, void *dev_id)
941{
942 struct imx_port *sport = dev_id;
943 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
944 irqreturn_t ret = IRQ_NONE;
945
946 spin_lock(&sport->port.lock);
947
948 usr1 = imx_uart_readl(sport, USR1);
949 usr2 = imx_uart_readl(sport, USR2);
950 ucr1 = imx_uart_readl(sport, UCR1);
951 ucr2 = imx_uart_readl(sport, UCR2);
952 ucr3 = imx_uart_readl(sport, UCR3);
953 ucr4 = imx_uart_readl(sport, UCR4);
954
955 /*
956 * Even if a condition is true that can trigger an irq only handle it if
957 * the respective irq source is enabled. This prevents some undesired
958 * actions, for example if a character that sits in the RX FIFO and that
959 * should be fetched via DMA is tried to be fetched using PIO. Or the
960 * receiver is currently off and so reading from URXD0 results in an
961 * exception. So just mask the (raw) status bits for disabled irqs.
962 */
963 if ((ucr1 & UCR1_RRDYEN) == 0)
964 usr1 &= ~USR1_RRDY;
965 if ((ucr2 & UCR2_ATEN) == 0)
966 usr1 &= ~USR1_AGTIM;
967 if ((ucr1 & UCR1_TRDYEN) == 0)
968 usr1 &= ~USR1_TRDY;
969 if ((ucr4 & UCR4_TCEN) == 0)
970 usr2 &= ~USR2_TXDC;
971 if ((ucr3 & UCR3_DTRDEN) == 0)
972 usr1 &= ~USR1_DTRD;
973 if ((ucr1 & UCR1_RTSDEN) == 0)
974 usr1 &= ~USR1_RTSD;
975 if ((ucr3 & UCR3_AWAKEN) == 0)
976 usr1 &= ~USR1_AWAKE;
977 if ((ucr4 & UCR4_OREN) == 0)
978 usr2 &= ~USR2_ORE;
979
980 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
981 imx_uart_writel(sport, USR1_AGTIM, USR1);
982
983 __imx_uart_rxint(irq, dev_id);
984 ret = IRQ_HANDLED;
985 }
986
987 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
988 imx_uart_transmit_buffer(sport);
989 ret = IRQ_HANDLED;
990 }
991
992 if (usr1 & USR1_DTRD) {
993 imx_uart_writel(sport, USR1_DTRD, USR1);
994
995 imx_uart_mctrl_check(sport);
996
997 ret = IRQ_HANDLED;
998 }
999
1000 if (usr1 & USR1_RTSD) {
1001 __imx_uart_rtsint(irq, dev_id);
1002 ret = IRQ_HANDLED;
1003 }
1004
1005 if (usr1 & USR1_AWAKE) {
1006 imx_uart_writel(sport, USR1_AWAKE, USR1);
1007 ret = IRQ_HANDLED;
1008 }
1009
1010 if (usr2 & USR2_ORE) {
1011 sport->port.icount.overrun++;
1012 imx_uart_writel(sport, USR2_ORE, USR2);
1013 ret = IRQ_HANDLED;
1014 }
1015
1016 spin_unlock(&sport->port.lock);
1017
1018 return ret;
1019}
1020
1021/*
1022 * Return TIOCSER_TEMT when transmitter is not busy.
1023 */
1024static unsigned int imx_uart_tx_empty(struct uart_port *port)
1025{
1026 struct imx_port *sport = (struct imx_port *)port;
1027 unsigned int ret;
1028
1029 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1030
1031 /* If the TX DMA is working, return 0. */
1032 if (sport->dma_is_txing)
1033 ret = 0;
1034
1035 return ret;
1036}
1037
1038/* called with port.lock taken and irqs off */
1039static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1040{
1041 struct imx_port *sport = (struct imx_port *)port;
1042 unsigned int ret = imx_uart_get_hwmctrl(sport);
1043
1044 mctrl_gpio_get(sport->gpios, &ret);
1045
1046 return ret;
1047}
1048
1049/* called with port.lock taken and irqs off */
1050static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1051{
1052 struct imx_port *sport = (struct imx_port *)port;
1053 u32 ucr3, uts;
1054
1055 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1056 u32 ucr2;
1057
1058 /*
1059 * Turn off autoRTS if RTS is lowered and restore autoRTS
1060 * setting if RTS is raised.
1061 */
1062 ucr2 = imx_uart_readl(sport, UCR2);
1063 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1064 if (mctrl & TIOCM_RTS) {
1065 ucr2 |= UCR2_CTS;
1066 /*
1067 * UCR2_IRTS is unset if and only if the port is
1068 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1069 * to get the state to restore to.
1070 */
1071 if (!(ucr2 & UCR2_IRTS))
1072 ucr2 |= UCR2_CTSC;
1073 }
1074 imx_uart_writel(sport, ucr2, UCR2);
1075 }
1076
1077 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1078 if (!(mctrl & TIOCM_DTR))
1079 ucr3 |= UCR3_DSR;
1080 imx_uart_writel(sport, ucr3, UCR3);
1081
1082 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1083 if (mctrl & TIOCM_LOOP)
1084 uts |= UTS_LOOP;
1085 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1086
1087 mctrl_gpio_set(sport->gpios, mctrl);
1088}
1089
1090/*
1091 * Interrupts always disabled.
1092 */
1093static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1094{
1095 struct imx_port *sport = (struct imx_port *)port;
1096 unsigned long flags;
1097 u32 ucr1;
1098
1099 spin_lock_irqsave(&sport->port.lock, flags);
1100
1101 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1102
1103 if (break_state != 0)
1104 ucr1 |= UCR1_SNDBRK;
1105
1106 imx_uart_writel(sport, ucr1, UCR1);
1107
1108 spin_unlock_irqrestore(&sport->port.lock, flags);
1109}
1110
1111/*
1112 * This is our per-port timeout handler, for checking the
1113 * modem status signals.
1114 */
1115static void imx_uart_timeout(struct timer_list *t)
1116{
1117 struct imx_port *sport = from_timer(sport, t, timer);
1118 unsigned long flags;
1119
1120 if (sport->port.state) {
1121 spin_lock_irqsave(&sport->port.lock, flags);
1122 imx_uart_mctrl_check(sport);
1123 spin_unlock_irqrestore(&sport->port.lock, flags);
1124
1125 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1126 }
1127}
1128
1129/*
1130 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1131 * [1] the RX DMA buffer is full.
1132 * [2] the aging timer expires
1133 *
1134 * Condition [2] is triggered when a character has been sitting in the FIFO
1135 * for at least 8 byte durations.
1136 */
1137static void imx_uart_dma_rx_callback(void *data)
1138{
1139 struct imx_port *sport = data;
1140 struct dma_chan *chan = sport->dma_chan_rx;
1141 struct scatterlist *sgl = &sport->rx_sgl;
1142 struct tty_port *port = &sport->port.state->port;
1143 struct dma_tx_state state;
1144 struct circ_buf *rx_ring = &sport->rx_ring;
1145 enum dma_status status;
1146 unsigned int w_bytes = 0;
1147 unsigned int r_bytes;
1148 unsigned int bd_size;
1149
1150 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1151
1152 if (status == DMA_ERROR) {
1153 imx_uart_clear_rx_errors(sport);
1154 return;
1155 }
1156
1157 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1158
1159 /*
1160 * The state-residue variable represents the empty space
1161 * relative to the entire buffer. Taking this in consideration
1162 * the head is always calculated base on the buffer total
1163 * length - DMA transaction residue. The UART script from the
1164 * SDMA firmware will jump to the next buffer descriptor,
1165 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1166 * Taking this in consideration the tail is always at the
1167 * beginning of the buffer descriptor that contains the head.
1168 */
1169
1170 /* Calculate the head */
1171 rx_ring->head = sg_dma_len(sgl) - state.residue;
1172
1173 /* Calculate the tail. */
1174 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1175 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1176
1177 if (rx_ring->head <= sg_dma_len(sgl) &&
1178 rx_ring->head > rx_ring->tail) {
1179
1180 /* Move data from tail to head */
1181 r_bytes = rx_ring->head - rx_ring->tail;
1182
1183 /* CPU claims ownership of RX DMA buffer */
1184 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1185 DMA_FROM_DEVICE);
1186
1187 w_bytes = tty_insert_flip_string(port,
1188 sport->rx_buf + rx_ring->tail, r_bytes);
1189
1190 /* UART retrieves ownership of RX DMA buffer */
1191 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1192 DMA_FROM_DEVICE);
1193
1194 if (w_bytes != r_bytes)
1195 sport->port.icount.buf_overrun++;
1196
1197 sport->port.icount.rx += w_bytes;
1198 } else {
1199 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1200 WARN_ON(rx_ring->head <= rx_ring->tail);
1201 }
1202 }
1203
1204 if (w_bytes) {
1205 tty_flip_buffer_push(port);
1206 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1207 }
1208}
1209
1210/* RX DMA buffer periods */
1211#define RX_DMA_PERIODS 16
1212#define RX_BUF_SIZE (RX_DMA_PERIODS * PAGE_SIZE / 4)
1213
1214static int imx_uart_start_rx_dma(struct imx_port *sport)
1215{
1216 struct scatterlist *sgl = &sport->rx_sgl;
1217 struct dma_chan *chan = sport->dma_chan_rx;
1218 struct device *dev = sport->port.dev;
1219 struct dma_async_tx_descriptor *desc;
1220 int ret;
1221
1222 sport->rx_ring.head = 0;
1223 sport->rx_ring.tail = 0;
1224 sport->rx_periods = RX_DMA_PERIODS;
1225
1226 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1227 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1228 if (ret == 0) {
1229 dev_err(dev, "DMA mapping error for RX.\n");
1230 return -EINVAL;
1231 }
1232
1233 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1234 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1235 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1236
1237 if (!desc) {
1238 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1239 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1240 return -EINVAL;
1241 }
1242 desc->callback = imx_uart_dma_rx_callback;
1243 desc->callback_param = sport;
1244
1245 dev_dbg(dev, "RX: prepare for the DMA.\n");
1246 sport->dma_is_rxing = 1;
1247 sport->rx_cookie = dmaengine_submit(desc);
1248 dma_async_issue_pending(chan);
1249 return 0;
1250}
1251
1252static void imx_uart_clear_rx_errors(struct imx_port *sport)
1253{
1254 struct tty_port *port = &sport->port.state->port;
1255 u32 usr1, usr2;
1256
1257 usr1 = imx_uart_readl(sport, USR1);
1258 usr2 = imx_uart_readl(sport, USR2);
1259
1260 if (usr2 & USR2_BRCD) {
1261 sport->port.icount.brk++;
1262 imx_uart_writel(sport, USR2_BRCD, USR2);
1263 uart_handle_break(&sport->port);
1264 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1265 sport->port.icount.buf_overrun++;
1266 tty_flip_buffer_push(port);
1267 } else {
1268 if (usr1 & USR1_FRAMERR) {
1269 sport->port.icount.frame++;
1270 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1271 } else if (usr1 & USR1_PARITYERR) {
1272 sport->port.icount.parity++;
1273 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1274 }
1275 }
1276
1277 if (usr2 & USR2_ORE) {
1278 sport->port.icount.overrun++;
1279 imx_uart_writel(sport, USR2_ORE, USR2);
1280 }
1281
1282}
1283
1284#define TXTL_DEFAULT 2 /* reset default */
1285#define RXTL_DEFAULT 1 /* reset default */
1286#define TXTL_DMA 8 /* DMA burst setting */
1287#define RXTL_DMA 9 /* DMA burst setting */
1288
1289static void imx_uart_setup_ufcr(struct imx_port *sport,
1290 unsigned char txwl, unsigned char rxwl)
1291{
1292 unsigned int val;
1293
1294 /* set receiver / transmitter trigger level */
1295 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1296 val |= txwl << UFCR_TXTL_SHF | rxwl;
1297 imx_uart_writel(sport, val, UFCR);
1298}
1299
1300static void imx_uart_dma_exit(struct imx_port *sport)
1301{
1302 if (sport->dma_chan_rx) {
1303 dmaengine_terminate_sync(sport->dma_chan_rx);
1304 dma_release_channel(sport->dma_chan_rx);
1305 sport->dma_chan_rx = NULL;
1306 sport->rx_cookie = -EINVAL;
1307 kfree(sport->rx_buf);
1308 sport->rx_buf = NULL;
1309 }
1310
1311 if (sport->dma_chan_tx) {
1312 dmaengine_terminate_sync(sport->dma_chan_tx);
1313 dma_release_channel(sport->dma_chan_tx);
1314 sport->dma_chan_tx = NULL;
1315 }
1316}
1317
1318static int imx_uart_dma_init(struct imx_port *sport)
1319{
1320 struct dma_slave_config slave_config = {};
1321 struct device *dev = sport->port.dev;
1322 int ret;
1323
1324 /* Prepare for RX : */
1325 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1326 if (!sport->dma_chan_rx) {
1327 dev_dbg(dev, "cannot get the DMA channel.\n");
1328 ret = -EINVAL;
1329 goto err;
1330 }
1331
1332 slave_config.direction = DMA_DEV_TO_MEM;
1333 slave_config.src_addr = sport->port.mapbase + URXD0;
1334 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1335 /* one byte less than the watermark level to enable the aging timer */
1336 slave_config.src_maxburst = RXTL_DMA - 1;
1337 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1338 if (ret) {
1339 dev_err(dev, "error in RX dma configuration.\n");
1340 goto err;
1341 }
1342
1343 sport->rx_buf = kzalloc(RX_BUF_SIZE, GFP_KERNEL);
1344 if (!sport->rx_buf) {
1345 ret = -ENOMEM;
1346 goto err;
1347 }
1348 sport->rx_ring.buf = sport->rx_buf;
1349
1350 /* Prepare for TX : */
1351 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1352 if (!sport->dma_chan_tx) {
1353 dev_err(dev, "cannot get the TX DMA channel!\n");
1354 ret = -EINVAL;
1355 goto err;
1356 }
1357
1358 slave_config.direction = DMA_MEM_TO_DEV;
1359 slave_config.dst_addr = sport->port.mapbase + URTX0;
1360 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1361 slave_config.dst_maxburst = TXTL_DMA;
1362 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1363 if (ret) {
1364 dev_err(dev, "error in TX dma configuration.");
1365 goto err;
1366 }
1367
1368 return 0;
1369err:
1370 imx_uart_dma_exit(sport);
1371 return ret;
1372}
1373
1374static void imx_uart_enable_dma(struct imx_port *sport)
1375{
1376 u32 ucr1;
1377
1378 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1379
1380 /* set UCR1 */
1381 ucr1 = imx_uart_readl(sport, UCR1);
1382 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1383 imx_uart_writel(sport, ucr1, UCR1);
1384
1385 sport->dma_is_enabled = 1;
1386}
1387
1388static void imx_uart_disable_dma(struct imx_port *sport)
1389{
1390 u32 ucr1;
1391
1392 /* clear UCR1 */
1393 ucr1 = imx_uart_readl(sport, UCR1);
1394 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1395 imx_uart_writel(sport, ucr1, UCR1);
1396
1397 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1398
1399 sport->dma_is_enabled = 0;
1400}
1401
1402/* half the RX buffer size */
1403#define CTSTL 16
1404
1405static int imx_uart_startup(struct uart_port *port)
1406{
1407 struct imx_port *sport = (struct imx_port *)port;
1408 int retval, i;
1409 unsigned long flags;
1410 int dma_is_inited = 0;
1411 u32 ucr1, ucr2, ucr3, ucr4;
1412
1413 retval = clk_prepare_enable(sport->clk_per);
1414 if (retval)
1415 return retval;
1416 retval = clk_prepare_enable(sport->clk_ipg);
1417 if (retval) {
1418 clk_disable_unprepare(sport->clk_per);
1419 return retval;
1420 }
1421
1422 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1423
1424 /* disable the DREN bit (Data Ready interrupt enable) before
1425 * requesting IRQs
1426 */
1427 ucr4 = imx_uart_readl(sport, UCR4);
1428
1429 /* set the trigger level for CTS */
1430 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1431 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1432
1433 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1434
1435 /* Can we enable the DMA support? */
1436 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1437 dma_is_inited = 1;
1438
1439 spin_lock_irqsave(&sport->port.lock, flags);
1440 /* Reset fifo's and state machines */
1441 i = 100;
1442
1443 ucr2 = imx_uart_readl(sport, UCR2);
1444 ucr2 &= ~UCR2_SRST;
1445 imx_uart_writel(sport, ucr2, UCR2);
1446
1447 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1448 udelay(1);
1449
1450 /*
1451 * Finally, clear and enable interrupts
1452 */
1453 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1454 imx_uart_writel(sport, USR2_ORE, USR2);
1455
1456 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1457 ucr1 |= UCR1_UARTEN;
1458 if (sport->have_rtscts)
1459 ucr1 |= UCR1_RTSDEN;
1460
1461 imx_uart_writel(sport, ucr1, UCR1);
1462
1463 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1464 if (!sport->dma_is_enabled)
1465 ucr4 |= UCR4_OREN;
1466 if (sport->inverted_rx)
1467 ucr4 |= UCR4_INVR;
1468 imx_uart_writel(sport, ucr4, UCR4);
1469
1470 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1471 /*
1472 * configure tx polarity before enabling tx
1473 */
1474 if (sport->inverted_tx)
1475 ucr3 |= UCR3_INVT;
1476
1477 if (!imx_uart_is_imx1(sport)) {
1478 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1479
1480 if (sport->dte_mode)
1481 /* disable broken interrupts */
1482 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1483 }
1484 imx_uart_writel(sport, ucr3, UCR3);
1485
1486 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1487 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1488 if (!sport->have_rtscts)
1489 ucr2 |= UCR2_IRTS;
1490 /*
1491 * make sure the edge sensitive RTS-irq is disabled,
1492 * we're using RTSD instead.
1493 */
1494 if (!imx_uart_is_imx1(sport))
1495 ucr2 &= ~UCR2_RTSEN;
1496 imx_uart_writel(sport, ucr2, UCR2);
1497
1498 /*
1499 * Enable modem status interrupts
1500 */
1501 imx_uart_enable_ms(&sport->port);
1502
1503 if (dma_is_inited) {
1504 imx_uart_enable_dma(sport);
1505 imx_uart_start_rx_dma(sport);
1506 } else {
1507 ucr1 = imx_uart_readl(sport, UCR1);
1508 ucr1 |= UCR1_RRDYEN;
1509 imx_uart_writel(sport, ucr1, UCR1);
1510
1511 ucr2 = imx_uart_readl(sport, UCR2);
1512 ucr2 |= UCR2_ATEN;
1513 imx_uart_writel(sport, ucr2, UCR2);
1514 }
1515
1516 spin_unlock_irqrestore(&sport->port.lock, flags);
1517
1518 return 0;
1519}
1520
1521static void imx_uart_shutdown(struct uart_port *port)
1522{
1523 struct imx_port *sport = (struct imx_port *)port;
1524 unsigned long flags;
1525 u32 ucr1, ucr2, ucr4;
1526
1527 if (sport->dma_is_enabled) {
1528 dmaengine_terminate_sync(sport->dma_chan_tx);
1529 if (sport->dma_is_txing) {
1530 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1531 sport->dma_tx_nents, DMA_TO_DEVICE);
1532 sport->dma_is_txing = 0;
1533 }
1534 dmaengine_terminate_sync(sport->dma_chan_rx);
1535 if (sport->dma_is_rxing) {
1536 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1537 1, DMA_FROM_DEVICE);
1538 sport->dma_is_rxing = 0;
1539 }
1540
1541 spin_lock_irqsave(&sport->port.lock, flags);
1542 imx_uart_stop_tx(port);
1543 imx_uart_stop_rx(port);
1544 imx_uart_disable_dma(sport);
1545 spin_unlock_irqrestore(&sport->port.lock, flags);
1546 imx_uart_dma_exit(sport);
1547 }
1548
1549 mctrl_gpio_disable_ms(sport->gpios);
1550
1551 spin_lock_irqsave(&sport->port.lock, flags);
1552 ucr2 = imx_uart_readl(sport, UCR2);
1553 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1554 imx_uart_writel(sport, ucr2, UCR2);
1555
1556 ucr4 = imx_uart_readl(sport, UCR4);
1557 ucr4 &= ~UCR4_OREN;
1558 imx_uart_writel(sport, ucr4, UCR4);
1559 spin_unlock_irqrestore(&sport->port.lock, flags);
1560
1561 /*
1562 * Stop our timer.
1563 */
1564 del_timer_sync(&sport->timer);
1565
1566 /*
1567 * Disable all interrupts, port and break condition.
1568 */
1569
1570 spin_lock_irqsave(&sport->port.lock, flags);
1571 ucr1 = imx_uart_readl(sport, UCR1);
1572 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN | UCR1_RXDMAEN | UCR1_ATDMAEN);
1573
1574 imx_uart_writel(sport, ucr1, UCR1);
1575 spin_unlock_irqrestore(&sport->port.lock, flags);
1576
1577 clk_disable_unprepare(sport->clk_per);
1578 clk_disable_unprepare(sport->clk_ipg);
1579}
1580
1581/* called with port.lock taken and irqs off */
1582static void imx_uart_flush_buffer(struct uart_port *port)
1583{
1584 struct imx_port *sport = (struct imx_port *)port;
1585 struct scatterlist *sgl = &sport->tx_sgl[0];
1586 u32 ucr2;
1587 int i = 100, ubir, ubmr, uts;
1588
1589 if (!sport->dma_chan_tx)
1590 return;
1591
1592 sport->tx_bytes = 0;
1593 dmaengine_terminate_all(sport->dma_chan_tx);
1594 if (sport->dma_is_txing) {
1595 u32 ucr1;
1596
1597 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1598 DMA_TO_DEVICE);
1599 ucr1 = imx_uart_readl(sport, UCR1);
1600 ucr1 &= ~UCR1_TXDMAEN;
1601 imx_uart_writel(sport, ucr1, UCR1);
1602 sport->dma_is_txing = 0;
1603 }
1604
1605 /*
1606 * According to the Reference Manual description of the UART SRST bit:
1607 *
1608 * "Reset the transmit and receive state machines,
1609 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1610 * and UTS[6-3]".
1611 *
1612 * We don't need to restore the old values from USR1, USR2, URXD and
1613 * UTXD. UBRC is read only, so only save/restore the other three
1614 * registers.
1615 */
1616 ubir = imx_uart_readl(sport, UBIR);
1617 ubmr = imx_uart_readl(sport, UBMR);
1618 uts = imx_uart_readl(sport, IMX21_UTS);
1619
1620 ucr2 = imx_uart_readl(sport, UCR2);
1621 ucr2 &= ~UCR2_SRST;
1622 imx_uart_writel(sport, ucr2, UCR2);
1623
1624 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
1625 udelay(1);
1626
1627 /* Restore the registers */
1628 imx_uart_writel(sport, ubir, UBIR);
1629 imx_uart_writel(sport, ubmr, UBMR);
1630 imx_uart_writel(sport, uts, IMX21_UTS);
1631}
1632
1633static void
1634imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1635 struct ktermios *old)
1636{
1637 struct imx_port *sport = (struct imx_port *)port;
1638 unsigned long flags;
1639 u32 ucr2, old_ucr2, ufcr;
1640 unsigned int baud, quot;
1641 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1642 unsigned long div;
1643 unsigned long num, denom, old_ubir, old_ubmr;
1644 uint64_t tdiv64;
1645
1646 /*
1647 * We only support CS7 and CS8.
1648 */
1649 while ((termios->c_cflag & CSIZE) != CS7 &&
1650 (termios->c_cflag & CSIZE) != CS8) {
1651 termios->c_cflag &= ~CSIZE;
1652 termios->c_cflag |= old_csize;
1653 old_csize = CS8;
1654 }
1655
1656 del_timer_sync(&sport->timer);
1657
1658 /*
1659 * Ask the core to calculate the divisor for us.
1660 */
1661 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1662 quot = uart_get_divisor(port, baud);
1663
1664 spin_lock_irqsave(&sport->port.lock, flags);
1665
1666 /*
1667 * Read current UCR2 and save it for future use, then clear all the bits
1668 * except those we will or may need to preserve.
1669 */
1670 old_ucr2 = imx_uart_readl(sport, UCR2);
1671 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1672
1673 ucr2 |= UCR2_SRST | UCR2_IRTS;
1674 if ((termios->c_cflag & CSIZE) == CS8)
1675 ucr2 |= UCR2_WS;
1676
1677 if (!sport->have_rtscts)
1678 termios->c_cflag &= ~CRTSCTS;
1679
1680 if (port->rs485.flags & SER_RS485_ENABLED) {
1681 /*
1682 * RTS is mandatory for rs485 operation, so keep
1683 * it under manual control and keep transmitter
1684 * disabled.
1685 */
1686 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1687 imx_uart_rts_active(sport, &ucr2);
1688 else
1689 imx_uart_rts_inactive(sport, &ucr2);
1690
1691 } else if (termios->c_cflag & CRTSCTS) {
1692 /*
1693 * Only let receiver control RTS output if we were not requested
1694 * to have RTS inactive (which then should take precedence).
1695 */
1696 if (ucr2 & UCR2_CTS)
1697 ucr2 |= UCR2_CTSC;
1698 }
1699
1700 if (termios->c_cflag & CRTSCTS)
1701 ucr2 &= ~UCR2_IRTS;
1702 if (termios->c_cflag & CSTOPB)
1703 ucr2 |= UCR2_STPB;
1704 if (termios->c_cflag & PARENB) {
1705 ucr2 |= UCR2_PREN;
1706 if (termios->c_cflag & PARODD)
1707 ucr2 |= UCR2_PROE;
1708 }
1709
1710 sport->port.read_status_mask = 0;
1711 if (termios->c_iflag & INPCK)
1712 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1713 if (termios->c_iflag & (BRKINT | PARMRK))
1714 sport->port.read_status_mask |= URXD_BRK;
1715
1716 /*
1717 * Characters to ignore
1718 */
1719 sport->port.ignore_status_mask = 0;
1720 if (termios->c_iflag & IGNPAR)
1721 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1722 if (termios->c_iflag & IGNBRK) {
1723 sport->port.ignore_status_mask |= URXD_BRK;
1724 /*
1725 * If we're ignoring parity and break indicators,
1726 * ignore overruns too (for real raw support).
1727 */
1728 if (termios->c_iflag & IGNPAR)
1729 sport->port.ignore_status_mask |= URXD_OVRRUN;
1730 }
1731
1732 if ((termios->c_cflag & CREAD) == 0)
1733 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1734
1735 /*
1736 * Update the per-port timeout.
1737 */
1738 uart_update_timeout(port, termios->c_cflag, baud);
1739
1740 /* custom-baudrate handling */
1741 div = sport->port.uartclk / (baud * 16);
1742 if (baud == 38400 && quot != div)
1743 baud = sport->port.uartclk / (quot * 16);
1744
1745 div = sport->port.uartclk / (baud * 16);
1746 if (div > 7)
1747 div = 7;
1748 if (!div)
1749 div = 1;
1750
1751 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1752 1 << 16, 1 << 16, &num, &denom);
1753
1754 tdiv64 = sport->port.uartclk;
1755 tdiv64 *= num;
1756 do_div(tdiv64, denom * 16 * div);
1757 tty_termios_encode_baud_rate(termios,
1758 (speed_t)tdiv64, (speed_t)tdiv64);
1759
1760 num -= 1;
1761 denom -= 1;
1762
1763 ufcr = imx_uart_readl(sport, UFCR);
1764 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1765 imx_uart_writel(sport, ufcr, UFCR);
1766
1767 /*
1768 * Two registers below should always be written both and in this
1769 * particular order. One consequence is that we need to check if any of
1770 * them changes and then update both. We do need the check for change
1771 * as even writing the same values seem to "restart"
1772 * transmission/receiving logic in the hardware, that leads to data
1773 * breakage even when rate doesn't in fact change. E.g., user switches
1774 * RTS/CTS handshake and suddenly gets broken bytes.
1775 */
1776 old_ubir = imx_uart_readl(sport, UBIR);
1777 old_ubmr = imx_uart_readl(sport, UBMR);
1778 if (old_ubir != num || old_ubmr != denom) {
1779 imx_uart_writel(sport, num, UBIR);
1780 imx_uart_writel(sport, denom, UBMR);
1781 }
1782
1783 if (!imx_uart_is_imx1(sport))
1784 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1785 IMX21_ONEMS);
1786
1787 imx_uart_writel(sport, ucr2, UCR2);
1788
1789 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1790 imx_uart_enable_ms(&sport->port);
1791
1792 spin_unlock_irqrestore(&sport->port.lock, flags);
1793}
1794
1795static const char *imx_uart_type(struct uart_port *port)
1796{
1797 struct imx_port *sport = (struct imx_port *)port;
1798
1799 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1800}
1801
1802/*
1803 * Configure/autoconfigure the port.
1804 */
1805static void imx_uart_config_port(struct uart_port *port, int flags)
1806{
1807 struct imx_port *sport = (struct imx_port *)port;
1808
1809 if (flags & UART_CONFIG_TYPE)
1810 sport->port.type = PORT_IMX;
1811}
1812
1813/*
1814 * Verify the new serial_struct (for TIOCSSERIAL).
1815 * The only change we allow are to the flags and type, and
1816 * even then only between PORT_IMX and PORT_UNKNOWN
1817 */
1818static int
1819imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1820{
1821 struct imx_port *sport = (struct imx_port *)port;
1822 int ret = 0;
1823
1824 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1825 ret = -EINVAL;
1826 if (sport->port.irq != ser->irq)
1827 ret = -EINVAL;
1828 if (ser->io_type != UPIO_MEM)
1829 ret = -EINVAL;
1830 if (sport->port.uartclk / 16 != ser->baud_base)
1831 ret = -EINVAL;
1832 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1833 ret = -EINVAL;
1834 if (sport->port.iobase != ser->port)
1835 ret = -EINVAL;
1836 if (ser->hub6 != 0)
1837 ret = -EINVAL;
1838 return ret;
1839}
1840
1841#if defined(CONFIG_CONSOLE_POLL)
1842
1843static int imx_uart_poll_init(struct uart_port *port)
1844{
1845 struct imx_port *sport = (struct imx_port *)port;
1846 unsigned long flags;
1847 u32 ucr1, ucr2;
1848 int retval;
1849
1850 retval = clk_prepare_enable(sport->clk_ipg);
1851 if (retval)
1852 return retval;
1853 retval = clk_prepare_enable(sport->clk_per);
1854 if (retval)
1855 clk_disable_unprepare(sport->clk_ipg);
1856
1857 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1858
1859 spin_lock_irqsave(&sport->port.lock, flags);
1860
1861 /*
1862 * Be careful about the order of enabling bits here. First enable the
1863 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1864 * This prevents that a character that already sits in the RX fifo is
1865 * triggering an irq but the try to fetch it from there results in an
1866 * exception because UARTEN or RXEN is still off.
1867 */
1868 ucr1 = imx_uart_readl(sport, UCR1);
1869 ucr2 = imx_uart_readl(sport, UCR2);
1870
1871 if (imx_uart_is_imx1(sport))
1872 ucr1 |= IMX1_UCR1_UARTCLKEN;
1873
1874 ucr1 |= UCR1_UARTEN;
1875 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1876
1877 ucr2 |= UCR2_RXEN;
1878 ucr2 &= ~UCR2_ATEN;
1879
1880 imx_uart_writel(sport, ucr1, UCR1);
1881 imx_uart_writel(sport, ucr2, UCR2);
1882
1883 /* now enable irqs */
1884 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1885 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1886
1887 spin_unlock_irqrestore(&sport->port.lock, flags);
1888
1889 return 0;
1890}
1891
1892static int imx_uart_poll_get_char(struct uart_port *port)
1893{
1894 struct imx_port *sport = (struct imx_port *)port;
1895 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1896 return NO_POLL_CHAR;
1897
1898 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1899}
1900
1901static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1902{
1903 struct imx_port *sport = (struct imx_port *)port;
1904 unsigned int status;
1905
1906 /* drain */
1907 do {
1908 status = imx_uart_readl(sport, USR1);
1909 } while (~status & USR1_TRDY);
1910
1911 /* write */
1912 imx_uart_writel(sport, c, URTX0);
1913
1914 /* flush */
1915 do {
1916 status = imx_uart_readl(sport, USR2);
1917 } while (~status & USR2_TXDC);
1918}
1919#endif
1920
1921/* called with port.lock taken and irqs off or from .probe without locking */
1922static int imx_uart_rs485_config(struct uart_port *port,
1923 struct serial_rs485 *rs485conf)
1924{
1925 struct imx_port *sport = (struct imx_port *)port;
1926 u32 ucr2;
1927
1928 /* RTS is required to control the transmitter */
1929 if (!sport->have_rtscts && !sport->have_rtsgpio)
1930 rs485conf->flags &= ~SER_RS485_ENABLED;
1931
1932 if (rs485conf->flags & SER_RS485_ENABLED) {
1933 /* Enable receiver if low-active RTS signal is requested */
1934 if (sport->have_rtscts && !sport->have_rtsgpio &&
1935 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1936 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1937
1938 /* disable transmitter */
1939 ucr2 = imx_uart_readl(sport, UCR2);
1940 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1941 imx_uart_rts_active(sport, &ucr2);
1942 else
1943 imx_uart_rts_inactive(sport, &ucr2);
1944 imx_uart_writel(sport, ucr2, UCR2);
1945 }
1946
1947 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1948 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1949 rs485conf->flags & SER_RS485_RX_DURING_TX)
1950 imx_uart_start_rx(port);
1951
1952 port->rs485 = *rs485conf;
1953
1954 return 0;
1955}
1956
1957static const struct uart_ops imx_uart_pops = {
1958 .tx_empty = imx_uart_tx_empty,
1959 .set_mctrl = imx_uart_set_mctrl,
1960 .get_mctrl = imx_uart_get_mctrl,
1961 .stop_tx = imx_uart_stop_tx,
1962 .start_tx = imx_uart_start_tx,
1963 .stop_rx = imx_uart_stop_rx,
1964 .enable_ms = imx_uart_enable_ms,
1965 .break_ctl = imx_uart_break_ctl,
1966 .startup = imx_uart_startup,
1967 .shutdown = imx_uart_shutdown,
1968 .flush_buffer = imx_uart_flush_buffer,
1969 .set_termios = imx_uart_set_termios,
1970 .type = imx_uart_type,
1971 .config_port = imx_uart_config_port,
1972 .verify_port = imx_uart_verify_port,
1973#if defined(CONFIG_CONSOLE_POLL)
1974 .poll_init = imx_uart_poll_init,
1975 .poll_get_char = imx_uart_poll_get_char,
1976 .poll_put_char = imx_uart_poll_put_char,
1977#endif
1978};
1979
1980static struct imx_port *imx_uart_ports[UART_NR];
1981
1982#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
1983static void imx_uart_console_putchar(struct uart_port *port, int ch)
1984{
1985 struct imx_port *sport = (struct imx_port *)port;
1986
1987 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1988 barrier();
1989
1990 imx_uart_writel(sport, ch, URTX0);
1991}
1992
1993/*
1994 * Interrupts are disabled on entering
1995 */
1996static void
1997imx_uart_console_write(struct console *co, const char *s, unsigned int count)
1998{
1999 struct imx_port *sport = imx_uart_ports[co->index];
2000 struct imx_port_ucrs old_ucr;
2001 unsigned int ucr1;
2002 unsigned long flags = 0;
2003 int locked = 1;
2004 int retval;
2005
2006 retval = clk_enable(sport->clk_per);
2007 if (retval)
2008 return;
2009 retval = clk_enable(sport->clk_ipg);
2010 if (retval) {
2011 clk_disable(sport->clk_per);
2012 return;
2013 }
2014
2015 if (sport->port.sysrq)
2016 locked = 0;
2017 else if (oops_in_progress)
2018 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2019 else
2020 spin_lock_irqsave(&sport->port.lock, flags);
2021
2022 /*
2023 * First, save UCR1/2/3 and then disable interrupts
2024 */
2025 imx_uart_ucrs_save(sport, &old_ucr);
2026 ucr1 = old_ucr.ucr1;
2027
2028 if (imx_uart_is_imx1(sport))
2029 ucr1 |= IMX1_UCR1_UARTCLKEN;
2030 ucr1 |= UCR1_UARTEN;
2031 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2032
2033 imx_uart_writel(sport, ucr1, UCR1);
2034
2035 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2036
2037 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2038
2039 /*
2040 * Finally, wait for transmitter to become empty
2041 * and restore UCR1/2/3
2042 */
2043 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2044
2045 imx_uart_ucrs_restore(sport, &old_ucr);
2046
2047 if (locked)
2048 spin_unlock_irqrestore(&sport->port.lock, flags);
2049
2050 clk_disable(sport->clk_ipg);
2051 clk_disable(sport->clk_per);
2052}
2053
2054/*
2055 * If the port was already initialised (eg, by a boot loader),
2056 * try to determine the current setup.
2057 */
2058static void __init
2059imx_uart_console_get_options(struct imx_port *sport, int *baud,
2060 int *parity, int *bits)
2061{
2062
2063 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2064 /* ok, the port was enabled */
2065 unsigned int ucr2, ubir, ubmr, uartclk;
2066 unsigned int baud_raw;
2067 unsigned int ucfr_rfdiv;
2068
2069 ucr2 = imx_uart_readl(sport, UCR2);
2070
2071 *parity = 'n';
2072 if (ucr2 & UCR2_PREN) {
2073 if (ucr2 & UCR2_PROE)
2074 *parity = 'o';
2075 else
2076 *parity = 'e';
2077 }
2078
2079 if (ucr2 & UCR2_WS)
2080 *bits = 8;
2081 else
2082 *bits = 7;
2083
2084 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2085 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2086
2087 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2088 if (ucfr_rfdiv == 6)
2089 ucfr_rfdiv = 7;
2090 else
2091 ucfr_rfdiv = 6 - ucfr_rfdiv;
2092
2093 uartclk = clk_get_rate(sport->clk_per);
2094 uartclk /= ucfr_rfdiv;
2095
2096 { /*
2097 * The next code provides exact computation of
2098 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2099 * without need of float support or long long division,
2100 * which would be required to prevent 32bit arithmetic overflow
2101 */
2102 unsigned int mul = ubir + 1;
2103 unsigned int div = 16 * (ubmr + 1);
2104 unsigned int rem = uartclk % div;
2105
2106 baud_raw = (uartclk / div) * mul;
2107 baud_raw += (rem * mul + div / 2) / div;
2108 *baud = (baud_raw + 50) / 100 * 100;
2109 }
2110
2111 if (*baud != baud_raw)
2112 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2113 baud_raw, *baud);
2114 }
2115}
2116
2117static int __init
2118imx_uart_console_setup(struct console *co, char *options)
2119{
2120 struct imx_port *sport;
2121 int baud = 9600;
2122 int bits = 8;
2123 int parity = 'n';
2124 int flow = 'n';
2125 int retval;
2126
2127 /*
2128 * Check whether an invalid uart number has been specified, and
2129 * if so, search for the first available port that does have
2130 * console support.
2131 */
2132 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2133 co->index = 0;
2134 sport = imx_uart_ports[co->index];
2135 if (sport == NULL)
2136 return -ENODEV;
2137
2138 /* For setting the registers, we only need to enable the ipg clock. */
2139 retval = clk_prepare_enable(sport->clk_ipg);
2140 if (retval)
2141 goto error_console;
2142
2143 if (options)
2144 uart_parse_options(options, &baud, &parity, &bits, &flow);
2145 else
2146 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2147
2148 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2149
2150 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2151
2152 clk_disable(sport->clk_ipg);
2153 if (retval) {
2154 clk_unprepare(sport->clk_ipg);
2155 goto error_console;
2156 }
2157
2158 retval = clk_prepare(sport->clk_per);
2159 if (retval)
2160 clk_unprepare(sport->clk_ipg);
2161
2162error_console:
2163 return retval;
2164}
2165
2166static struct uart_driver imx_uart_uart_driver;
2167static struct console imx_uart_console = {
2168 .name = DEV_NAME,
2169 .write = imx_uart_console_write,
2170 .device = uart_console_device,
2171 .setup = imx_uart_console_setup,
2172 .flags = CON_PRINTBUFFER,
2173 .index = -1,
2174 .data = &imx_uart_uart_driver,
2175};
2176
2177#define IMX_CONSOLE &imx_uart_console
2178
2179#else
2180#define IMX_CONSOLE NULL
2181#endif
2182
2183static struct uart_driver imx_uart_uart_driver = {
2184 .owner = THIS_MODULE,
2185 .driver_name = DRIVER_NAME,
2186 .dev_name = DEV_NAME,
2187 .major = SERIAL_IMX_MAJOR,
2188 .minor = MINOR_START,
2189 .nr = ARRAY_SIZE(imx_uart_ports),
2190 .cons = IMX_CONSOLE,
2191};
2192
2193#ifdef CONFIG_OF
2194/*
2195 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2196 * could successfully get all information from dt or a negative errno.
2197 */
2198static int imx_uart_probe_dt(struct imx_port *sport,
2199 struct platform_device *pdev)
2200{
2201 struct device_node *np = pdev->dev.of_node;
2202 int ret;
2203
2204 sport->devdata = of_device_get_match_data(&pdev->dev);
2205 if (!sport->devdata)
2206 /* no device tree device */
2207 return 1;
2208
2209 ret = of_alias_get_id(np, "serial");
2210 if (ret < 0) {
2211 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2212 return ret;
2213 }
2214 sport->port.line = ret;
2215
2216 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2217 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2218 sport->have_rtscts = 1;
2219
2220 if (of_get_property(np, "fsl,dte-mode", NULL))
2221 sport->dte_mode = 1;
2222
2223 if (of_get_property(np, "rts-gpios", NULL))
2224 sport->have_rtsgpio = 1;
2225
2226 if (of_get_property(np, "fsl,inverted-tx", NULL))
2227 sport->inverted_tx = 1;
2228
2229 if (of_get_property(np, "fsl,inverted-rx", NULL))
2230 sport->inverted_rx = 1;
2231
2232 return 0;
2233}
2234#else
2235static inline int imx_uart_probe_dt(struct imx_port *sport,
2236 struct platform_device *pdev)
2237{
2238 return 1;
2239}
2240#endif
2241
2242static void imx_uart_probe_pdata(struct imx_port *sport,
2243 struct platform_device *pdev)
2244{
2245 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2246
2247 sport->port.line = pdev->id;
2248 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2249
2250 if (!pdata)
2251 return;
2252
2253 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2254 sport->have_rtscts = 1;
2255}
2256
2257static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2258{
2259 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2260 unsigned long flags;
2261
2262 spin_lock_irqsave(&sport->port.lock, flags);
2263 if (sport->tx_state == WAIT_AFTER_RTS)
2264 imx_uart_start_tx(&sport->port);
2265 spin_unlock_irqrestore(&sport->port.lock, flags);
2266
2267 return HRTIMER_NORESTART;
2268}
2269
2270static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2271{
2272 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2273 unsigned long flags;
2274
2275 spin_lock_irqsave(&sport->port.lock, flags);
2276 if (sport->tx_state == WAIT_AFTER_SEND)
2277 imx_uart_stop_tx(&sport->port);
2278 spin_unlock_irqrestore(&sport->port.lock, flags);
2279
2280 return HRTIMER_NORESTART;
2281}
2282
2283static int imx_uart_probe(struct platform_device *pdev)
2284{
2285 struct imx_port *sport;
2286 void __iomem *base;
2287 int ret = 0;
2288 u32 ucr1;
2289 struct resource *res;
2290 int txirq, rxirq, rtsirq;
2291
2292 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2293 if (!sport)
2294 return -ENOMEM;
2295
2296 ret = imx_uart_probe_dt(sport, pdev);
2297 if (ret > 0)
2298 imx_uart_probe_pdata(sport, pdev);
2299 else if (ret < 0)
2300 return ret;
2301
2302 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2303 dev_err(&pdev->dev, "serial%d out of range\n",
2304 sport->port.line);
2305 return -EINVAL;
2306 }
2307
2308 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2309 base = devm_ioremap_resource(&pdev->dev, res);
2310 if (IS_ERR(base))
2311 return PTR_ERR(base);
2312
2313 rxirq = platform_get_irq(pdev, 0);
2314 if (rxirq < 0)
2315 return rxirq;
2316 txirq = platform_get_irq_optional(pdev, 1);
2317 rtsirq = platform_get_irq_optional(pdev, 2);
2318
2319 sport->port.dev = &pdev->dev;
2320 sport->port.mapbase = res->start;
2321 sport->port.membase = base;
2322 sport->port.type = PORT_IMX,
2323 sport->port.iotype = UPIO_MEM;
2324 sport->port.irq = rxirq;
2325 sport->port.fifosize = 32;
2326 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2327 sport->port.ops = &imx_uart_pops;
2328 sport->port.rs485_config = imx_uart_rs485_config;
2329 sport->port.flags = UPF_BOOT_AUTOCONF;
2330 timer_setup(&sport->timer, imx_uart_timeout, 0);
2331
2332 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2333 if (IS_ERR(sport->gpios))
2334 return PTR_ERR(sport->gpios);
2335
2336 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2337 if (IS_ERR(sport->clk_ipg)) {
2338 ret = PTR_ERR(sport->clk_ipg);
2339 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2340 return ret;
2341 }
2342
2343 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2344 if (IS_ERR(sport->clk_per)) {
2345 ret = PTR_ERR(sport->clk_per);
2346 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2347 return ret;
2348 }
2349
2350 sport->port.uartclk = clk_get_rate(sport->clk_per);
2351
2352 /* For register access, we only need to enable the ipg clock. */
2353 ret = clk_prepare_enable(sport->clk_ipg);
2354 if (ret) {
2355 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2356 return ret;
2357 }
2358
2359 /* initialize shadow register values */
2360 sport->ucr1 = readl(sport->port.membase + UCR1);
2361 sport->ucr2 = readl(sport->port.membase + UCR2);
2362 sport->ucr3 = readl(sport->port.membase + UCR3);
2363 sport->ucr4 = readl(sport->port.membase + UCR4);
2364 sport->ufcr = readl(sport->port.membase + UFCR);
2365
2366 ret = uart_get_rs485_mode(&sport->port);
2367 if (ret) {
2368 clk_disable_unprepare(sport->clk_ipg);
2369 return ret;
2370 }
2371
2372 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2373 (!sport->have_rtscts && !sport->have_rtsgpio))
2374 dev_err(&pdev->dev, "no RTS control, disabling rs485\n");
2375
2376 /*
2377 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2378 * signal cannot be set low during transmission in case the
2379 * receiver is off (limitation of the i.MX UART IP).
2380 */
2381 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2382 sport->have_rtscts && !sport->have_rtsgpio &&
2383 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2384 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2385 dev_err(&pdev->dev,
2386 "low-active RTS not possible when receiver is off, enabling receiver\n");
2387
2388 imx_uart_rs485_config(&sport->port, &sport->port.rs485);
2389
2390 /* Disable interrupts before requesting them */
2391 ucr1 = imx_uart_readl(sport, UCR1);
2392 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2393 UCR1_TRDYEN | UCR1_RTSDEN);
2394 imx_uart_writel(sport, ucr1, UCR1);
2395
2396 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2397 /*
2398 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2399 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2400 * and DCD (when they are outputs) or enables the respective
2401 * irqs. So set this bit early, i.e. before requesting irqs.
2402 */
2403 u32 ufcr = imx_uart_readl(sport, UFCR);
2404 if (!(ufcr & UFCR_DCEDTE))
2405 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2406
2407 /*
2408 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2409 * enabled later because they cannot be cleared
2410 * (confirmed on i.MX25) which makes them unusable.
2411 */
2412 imx_uart_writel(sport,
2413 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2414 UCR3);
2415
2416 } else {
2417 u32 ucr3 = UCR3_DSR;
2418 u32 ufcr = imx_uart_readl(sport, UFCR);
2419 if (ufcr & UFCR_DCEDTE)
2420 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2421
2422 if (!imx_uart_is_imx1(sport))
2423 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2424 imx_uart_writel(sport, ucr3, UCR3);
2425 }
2426
2427 clk_disable_unprepare(sport->clk_ipg);
2428
2429 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2430 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2431 sport->trigger_start_tx.function = imx_trigger_start_tx;
2432 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2433
2434 /*
2435 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2436 * chips only have one interrupt.
2437 */
2438 if (txirq > 0) {
2439 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2440 dev_name(&pdev->dev), sport);
2441 if (ret) {
2442 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2443 ret);
2444 return ret;
2445 }
2446
2447 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2448 dev_name(&pdev->dev), sport);
2449 if (ret) {
2450 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2451 ret);
2452 return ret;
2453 }
2454
2455 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2456 dev_name(&pdev->dev), sport);
2457 if (ret) {
2458 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2459 ret);
2460 return ret;
2461 }
2462 } else {
2463 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2464 dev_name(&pdev->dev), sport);
2465 if (ret) {
2466 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2467 return ret;
2468 }
2469 }
2470
2471 imx_uart_ports[sport->port.line] = sport;
2472
2473 platform_set_drvdata(pdev, sport);
2474
2475 return uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2476}
2477
2478static int imx_uart_remove(struct platform_device *pdev)
2479{
2480 struct imx_port *sport = platform_get_drvdata(pdev);
2481
2482 return uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2483}
2484
2485static void imx_uart_restore_context(struct imx_port *sport)
2486{
2487 unsigned long flags;
2488
2489 spin_lock_irqsave(&sport->port.lock, flags);
2490 if (!sport->context_saved) {
2491 spin_unlock_irqrestore(&sport->port.lock, flags);
2492 return;
2493 }
2494
2495 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2496 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2497 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2498 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2499 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2500 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2501 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2502 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2503 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2504 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2505 sport->context_saved = false;
2506 spin_unlock_irqrestore(&sport->port.lock, flags);
2507}
2508
2509static void imx_uart_save_context(struct imx_port *sport)
2510{
2511 unsigned long flags;
2512
2513 /* Save necessary regs */
2514 spin_lock_irqsave(&sport->port.lock, flags);
2515 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2516 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2517 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2518 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2519 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2520 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2521 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2522 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2523 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2524 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2525 sport->context_saved = true;
2526 spin_unlock_irqrestore(&sport->port.lock, flags);
2527}
2528
2529static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2530{
2531 u32 ucr3;
2532
2533 ucr3 = imx_uart_readl(sport, UCR3);
2534 if (on) {
2535 imx_uart_writel(sport, USR1_AWAKE, USR1);
2536 ucr3 |= UCR3_AWAKEN;
2537 } else {
2538 ucr3 &= ~UCR3_AWAKEN;
2539 }
2540 imx_uart_writel(sport, ucr3, UCR3);
2541
2542 if (sport->have_rtscts) {
2543 u32 ucr1 = imx_uart_readl(sport, UCR1);
2544 if (on)
2545 ucr1 |= UCR1_RTSDEN;
2546 else
2547 ucr1 &= ~UCR1_RTSDEN;
2548 imx_uart_writel(sport, ucr1, UCR1);
2549 }
2550}
2551
2552static int imx_uart_suspend_noirq(struct device *dev)
2553{
2554 struct imx_port *sport = dev_get_drvdata(dev);
2555
2556 imx_uart_save_context(sport);
2557
2558 clk_disable(sport->clk_ipg);
2559
2560 pinctrl_pm_select_sleep_state(dev);
2561
2562 return 0;
2563}
2564
2565static int imx_uart_resume_noirq(struct device *dev)
2566{
2567 struct imx_port *sport = dev_get_drvdata(dev);
2568 int ret;
2569
2570 pinctrl_pm_select_default_state(dev);
2571
2572 ret = clk_enable(sport->clk_ipg);
2573 if (ret)
2574 return ret;
2575
2576 imx_uart_restore_context(sport);
2577
2578 return 0;
2579}
2580
2581static int imx_uart_suspend(struct device *dev)
2582{
2583 struct imx_port *sport = dev_get_drvdata(dev);
2584 int ret;
2585
2586 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2587 disable_irq(sport->port.irq);
2588
2589 ret = clk_prepare_enable(sport->clk_ipg);
2590 if (ret)
2591 return ret;
2592
2593 /* enable wakeup from i.MX UART */
2594 imx_uart_enable_wakeup(sport, true);
2595
2596 return 0;
2597}
2598
2599static int imx_uart_resume(struct device *dev)
2600{
2601 struct imx_port *sport = dev_get_drvdata(dev);
2602
2603 /* disable wakeup from i.MX UART */
2604 imx_uart_enable_wakeup(sport, false);
2605
2606 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2607 enable_irq(sport->port.irq);
2608
2609 clk_disable_unprepare(sport->clk_ipg);
2610
2611 return 0;
2612}
2613
2614static int imx_uart_freeze(struct device *dev)
2615{
2616 struct imx_port *sport = dev_get_drvdata(dev);
2617
2618 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2619
2620 return clk_prepare_enable(sport->clk_ipg);
2621}
2622
2623static int imx_uart_thaw(struct device *dev)
2624{
2625 struct imx_port *sport = dev_get_drvdata(dev);
2626
2627 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2628
2629 clk_disable_unprepare(sport->clk_ipg);
2630
2631 return 0;
2632}
2633
2634static const struct dev_pm_ops imx_uart_pm_ops = {
2635 .suspend_noirq = imx_uart_suspend_noirq,
2636 .resume_noirq = imx_uart_resume_noirq,
2637 .freeze_noirq = imx_uart_suspend_noirq,
2638 .restore_noirq = imx_uart_resume_noirq,
2639 .suspend = imx_uart_suspend,
2640 .resume = imx_uart_resume,
2641 .freeze = imx_uart_freeze,
2642 .thaw = imx_uart_thaw,
2643 .restore = imx_uart_thaw,
2644};
2645
2646static struct platform_driver imx_uart_platform_driver = {
2647 .probe = imx_uart_probe,
2648 .remove = imx_uart_remove,
2649
2650 .id_table = imx_uart_devtype,
2651 .driver = {
2652 .name = "imx-uart",
2653 .of_match_table = imx_uart_dt_ids,
2654 .pm = &imx_uart_pm_ops,
2655 },
2656};
2657
2658static int __init imx_uart_init(void)
2659{
2660 int ret = uart_register_driver(&imx_uart_uart_driver);
2661
2662 if (ret)
2663 return ret;
2664
2665 ret = platform_driver_register(&imx_uart_platform_driver);
2666 if (ret != 0)
2667 uart_unregister_driver(&imx_uart_uart_driver);
2668
2669 return ret;
2670}
2671
2672static void __exit imx_uart_exit(void)
2673{
2674 platform_driver_unregister(&imx_uart_platform_driver);
2675 uart_unregister_driver(&imx_uart_uart_driver);
2676}
2677
2678module_init(imx_uart_init);
2679module_exit(imx_uart_exit);
2680
2681MODULE_AUTHOR("Sascha Hauer");
2682MODULE_DESCRIPTION("IMX generic serial port driver");
2683MODULE_LICENSE("GPL");
2684MODULE_ALIAS("platform:imx-uart");