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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11#include <linux/module.h>
12#include <linux/ioport.h>
13#include <linux/init.h>
14#include <linux/console.h>
15#include <linux/sysrq.h>
16#include <linux/platform_device.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/ktime.h>
24#include <linux/pinctrl/consumer.h>
25#include <linux/rational.h>
26#include <linux/slab.h>
27#include <linux/of.h>
28#include <linux/io.h>
29#include <linux/dma-mapping.h>
30
31#include <asm/irq.h>
32#include <linux/dma/imx-dma.h>
33
34#include "serial_mctrl_gpio.h"
35
36/* Register definitions */
37#define URXD0 0x0 /* Receiver Register */
38#define URTX0 0x40 /* Transmitter Register */
39#define UCR1 0x80 /* Control Register 1 */
40#define UCR2 0x84 /* Control Register 2 */
41#define UCR3 0x88 /* Control Register 3 */
42#define UCR4 0x8c /* Control Register 4 */
43#define UFCR 0x90 /* FIFO Control Register */
44#define USR1 0x94 /* Status Register 1 */
45#define USR2 0x98 /* Status Register 2 */
46#define UESC 0x9c /* Escape Character Register */
47#define UTIM 0xa0 /* Escape Timer Register */
48#define UBIR 0xa4 /* BRM Incremental Register */
49#define UBMR 0xa8 /* BRM Modulator Register */
50#define UBRC 0xac /* Baud Rate Count Register */
51#define IMX21_ONEMS 0xb0 /* One Millisecond register */
52#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
53#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
54
55/* UART Control Register Bit Fields.*/
56#define URXD_DUMMY_READ (1<<16)
57#define URXD_CHARRDY (1<<15)
58#define URXD_ERR (1<<14)
59#define URXD_OVRRUN (1<<13)
60#define URXD_FRMERR (1<<12)
61#define URXD_BRK (1<<11)
62#define URXD_PRERR (1<<10)
63#define URXD_RX_DATA (0xFF<<0)
64#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
65#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
66#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
67#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
68#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
69#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
70#define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
71#define UCR1_IREN (1<<7) /* Infrared interface enable */
72#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
73#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
74#define UCR1_SNDBRK (1<<4) /* Send break */
75#define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
76#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
77#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
78#define UCR1_DOZE (1<<1) /* Doze */
79#define UCR1_UARTEN (1<<0) /* UART enabled */
80#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
81#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
82#define UCR2_CTSC (1<<13) /* CTS pin control */
83#define UCR2_CTS (1<<12) /* Clear to send */
84#define UCR2_ESCEN (1<<11) /* Escape enable */
85#define UCR2_PREN (1<<8) /* Parity enable */
86#define UCR2_PROE (1<<7) /* Parity odd/even */
87#define UCR2_STPB (1<<6) /* Stop */
88#define UCR2_WS (1<<5) /* Word size */
89#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
90#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
91#define UCR2_TXEN (1<<2) /* Transmitter enabled */
92#define UCR2_RXEN (1<<1) /* Receiver enabled */
93#define UCR2_SRST (1<<0) /* SW reset */
94#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
95#define UCR3_PARERREN (1<<12) /* Parity enable */
96#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
97#define UCR3_DSR (1<<10) /* Data set ready */
98#define UCR3_DCD (1<<9) /* Data carrier detect */
99#define UCR3_RI (1<<8) /* Ring indicator */
100#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
101#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
102#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
103#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
104#define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
105#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
106#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
107#define UCR3_BPEN (1<<0) /* Preset registers enable */
108#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
109#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
110#define UCR4_INVR (1<<9) /* Inverted infrared reception */
111#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
112#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
113#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
114#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
115#define UCR4_IRSC (1<<5) /* IR special case */
116#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
117#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
118#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
119#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
120#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
121#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
122#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
123#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
124#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
125#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
126#define USR1_RTSS (1<<14) /* RTS pin status */
127#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
128#define USR1_RTSD (1<<12) /* RTS delta */
129#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
130#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
131#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
132#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
133#define USR1_DTRD (1<<7) /* DTR Delta */
134#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
135#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
136#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
137#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
138#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
139#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
140#define USR2_IDLE (1<<12) /* Idle condition */
141#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
142#define USR2_RIIN (1<<9) /* Ring Indicator Input */
143#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
144#define USR2_WAKE (1<<7) /* Wake */
145#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
146#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
147#define USR2_TXDC (1<<3) /* Transmitter complete */
148#define USR2_BRCD (1<<2) /* Break condition */
149#define USR2_ORE (1<<1) /* Overrun error */
150#define USR2_RDR (1<<0) /* Recv data ready */
151#define UTS_FRCPERR (1<<13) /* Force parity error */
152#define UTS_LOOP (1<<12) /* Loop tx and rx */
153#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
154#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
155#define UTS_TXFULL (1<<4) /* TxFIFO full */
156#define UTS_RXFULL (1<<3) /* RxFIFO full */
157#define UTS_SOFTRST (1<<0) /* Software reset */
158
159/* We've been assigned a range on the "Low-density serial ports" major */
160#define SERIAL_IMX_MAJOR 207
161#define MINOR_START 16
162#define DEV_NAME "ttymxc"
163
164/*
165 * This determines how often we check the modem status signals
166 * for any change. They generally aren't connected to an IRQ
167 * so we have to poll them. We also check immediately before
168 * filling the TX fifo incase CTS has been dropped.
169 */
170#define MCTRL_TIMEOUT (250*HZ/1000)
171
172#define DRIVER_NAME "IMX-uart"
173
174#define UART_NR 8
175
176/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
177enum imx_uart_type {
178 IMX1_UART,
179 IMX21_UART,
180};
181
182/* device type dependent stuff */
183struct imx_uart_data {
184 unsigned uts_reg;
185 enum imx_uart_type devtype;
186};
187
188enum imx_tx_state {
189 OFF,
190 WAIT_AFTER_RTS,
191 SEND,
192 WAIT_AFTER_SEND,
193};
194
195struct imx_port {
196 struct uart_port port;
197 struct timer_list timer;
198 unsigned int old_status;
199 unsigned int have_rtscts:1;
200 unsigned int have_rtsgpio:1;
201 unsigned int dte_mode:1;
202 unsigned int inverted_tx:1;
203 unsigned int inverted_rx:1;
204 struct clk *clk_ipg;
205 struct clk *clk_per;
206 const struct imx_uart_data *devdata;
207
208 struct mctrl_gpios *gpios;
209
210 /* counter to stop 0xff flood */
211 int idle_counter;
212
213 /* DMA fields */
214 unsigned int dma_is_enabled:1;
215 unsigned int dma_is_rxing:1;
216 unsigned int dma_is_txing:1;
217 struct dma_chan *dma_chan_rx, *dma_chan_tx;
218 struct scatterlist rx_sgl, tx_sgl[2];
219 void *rx_buf;
220 struct circ_buf rx_ring;
221 unsigned int rx_buf_size;
222 unsigned int rx_period_length;
223 unsigned int rx_periods;
224 dma_cookie_t rx_cookie;
225 unsigned int tx_bytes;
226 unsigned int dma_tx_nents;
227 unsigned int saved_reg[10];
228 bool context_saved;
229
230 enum imx_tx_state tx_state;
231 struct hrtimer trigger_start_tx;
232 struct hrtimer trigger_stop_tx;
233};
234
235struct imx_port_ucrs {
236 unsigned int ucr1;
237 unsigned int ucr2;
238 unsigned int ucr3;
239};
240
241static const struct imx_uart_data imx_uart_imx1_devdata = {
242 .uts_reg = IMX1_UTS,
243 .devtype = IMX1_UART,
244};
245
246static const struct imx_uart_data imx_uart_imx21_devdata = {
247 .uts_reg = IMX21_UTS,
248 .devtype = IMX21_UART,
249};
250
251static const struct of_device_id imx_uart_dt_ids[] = {
252 /*
253 * For reasons unknown to me, some UART devices (e.g. imx6ul's) are
254 * compatible to fsl,imx6q-uart, but not fsl,imx21-uart, while the
255 * original imx6q's UART is compatible to fsl,imx21-uart. This driver
256 * doesn't make any distinction between these two variants.
257 */
258 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_imx21_devdata, },
259 { .compatible = "fsl,imx1-uart", .data = &imx_uart_imx1_devdata, },
260 { .compatible = "fsl,imx21-uart", .data = &imx_uart_imx21_devdata, },
261 { /* sentinel */ }
262};
263MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
264
265static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
266{
267 writel(val, sport->port.membase + offset);
268}
269
270static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
271{
272 return readl(sport->port.membase + offset);
273}
274
275static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
276{
277 return sport->devdata->uts_reg;
278}
279
280static inline int imx_uart_is_imx1(struct imx_port *sport)
281{
282 return sport->devdata->devtype == IMX1_UART;
283}
284
285/*
286 * Save and restore functions for UCR1, UCR2 and UCR3 registers
287 */
288#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
289static void imx_uart_ucrs_save(struct imx_port *sport,
290 struct imx_port_ucrs *ucr)
291{
292 /* save control registers */
293 ucr->ucr1 = imx_uart_readl(sport, UCR1);
294 ucr->ucr2 = imx_uart_readl(sport, UCR2);
295 ucr->ucr3 = imx_uart_readl(sport, UCR3);
296}
297
298static void imx_uart_ucrs_restore(struct imx_port *sport,
299 struct imx_port_ucrs *ucr)
300{
301 /* restore control registers */
302 imx_uart_writel(sport, ucr->ucr1, UCR1);
303 imx_uart_writel(sport, ucr->ucr2, UCR2);
304 imx_uart_writel(sport, ucr->ucr3, UCR3);
305}
306#endif
307
308/* called with port.lock taken and irqs caller dependent */
309static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
310{
311 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
312
313 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
314}
315
316/* called with port.lock taken and irqs caller dependent */
317static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
318{
319 *ucr2 &= ~UCR2_CTSC;
320 *ucr2 |= UCR2_CTS;
321
322 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
323}
324
325static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
326{
327 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
328}
329
330/* called with port.lock taken and irqs off */
331static void imx_uart_soft_reset(struct imx_port *sport)
332{
333 int i = 10;
334 u32 ucr2, ubir, ubmr, uts;
335
336 /*
337 * According to the Reference Manual description of the UART SRST bit:
338 *
339 * "Reset the transmit and receive state machines,
340 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
341 * and UTS[6-3]".
342 *
343 * We don't need to restore the old values from USR1, USR2, URXD and
344 * UTXD. UBRC is read only, so only save/restore the other three
345 * registers.
346 */
347 ubir = imx_uart_readl(sport, UBIR);
348 ubmr = imx_uart_readl(sport, UBMR);
349 uts = imx_uart_readl(sport, IMX21_UTS);
350
351 ucr2 = imx_uart_readl(sport, UCR2);
352 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
353
354 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
355 udelay(1);
356
357 /* Restore the registers */
358 imx_uart_writel(sport, ubir, UBIR);
359 imx_uart_writel(sport, ubmr, UBMR);
360 imx_uart_writel(sport, uts, IMX21_UTS);
361
362 sport->idle_counter = 0;
363}
364
365static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
366{
367 unsigned int uts;
368
369 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
370 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
371 uts &= ~UTS_LOOP;
372 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
373}
374
375/* called with port.lock taken and irqs off */
376static void imx_uart_start_rx(struct uart_port *port)
377{
378 struct imx_port *sport = (struct imx_port *)port;
379 unsigned int ucr1, ucr2;
380
381 ucr1 = imx_uart_readl(sport, UCR1);
382 ucr2 = imx_uart_readl(sport, UCR2);
383
384 ucr2 |= UCR2_RXEN;
385
386 if (sport->dma_is_enabled) {
387 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
388 } else {
389 ucr1 |= UCR1_RRDYEN;
390 ucr2 |= UCR2_ATEN;
391 }
392
393 /* Write UCR2 first as it includes RXEN */
394 imx_uart_writel(sport, ucr2, UCR2);
395 imx_uart_writel(sport, ucr1, UCR1);
396 imx_uart_disable_loopback_rs485(sport);
397}
398
399/* called with port.lock taken and irqs off */
400static void imx_uart_stop_tx(struct uart_port *port)
401{
402 struct imx_port *sport = (struct imx_port *)port;
403 u32 ucr1, ucr4, usr2;
404
405 if (sport->tx_state == OFF)
406 return;
407
408 /*
409 * We are maybe in the SMP context, so if the DMA TX thread is running
410 * on other cpu, we have to wait for it to finish.
411 */
412 if (sport->dma_is_txing)
413 return;
414
415 ucr1 = imx_uart_readl(sport, UCR1);
416 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
417
418 ucr4 = imx_uart_readl(sport, UCR4);
419 usr2 = imx_uart_readl(sport, USR2);
420 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
421 /* The shifter is still busy, so retry once TC triggers */
422 return;
423 }
424
425 ucr4 &= ~UCR4_TCEN;
426 imx_uart_writel(sport, ucr4, UCR4);
427
428 /* in rs485 mode disable transmitter */
429 if (port->rs485.flags & SER_RS485_ENABLED) {
430 if (sport->tx_state == SEND) {
431 sport->tx_state = WAIT_AFTER_SEND;
432
433 if (port->rs485.delay_rts_after_send > 0) {
434 start_hrtimer_ms(&sport->trigger_stop_tx,
435 port->rs485.delay_rts_after_send);
436 return;
437 }
438
439 /* continue without any delay */
440 }
441
442 if (sport->tx_state == WAIT_AFTER_RTS ||
443 sport->tx_state == WAIT_AFTER_SEND) {
444 u32 ucr2;
445
446 hrtimer_try_to_cancel(&sport->trigger_start_tx);
447
448 ucr2 = imx_uart_readl(sport, UCR2);
449 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
450 imx_uart_rts_active(sport, &ucr2);
451 else
452 imx_uart_rts_inactive(sport, &ucr2);
453 imx_uart_writel(sport, ucr2, UCR2);
454
455 if (!port->rs485_rx_during_tx_gpio)
456 imx_uart_start_rx(port);
457
458 sport->tx_state = OFF;
459 }
460 } else {
461 sport->tx_state = OFF;
462 }
463}
464
465static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
466{
467 struct imx_port *sport = (struct imx_port *)port;
468 u32 ucr1, ucr2, ucr4, uts;
469
470 ucr1 = imx_uart_readl(sport, UCR1);
471 ucr2 = imx_uart_readl(sport, UCR2);
472 ucr4 = imx_uart_readl(sport, UCR4);
473
474 if (sport->dma_is_enabled) {
475 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
476 } else {
477 ucr1 &= ~UCR1_RRDYEN;
478 ucr2 &= ~UCR2_ATEN;
479 ucr4 &= ~UCR4_OREN;
480 }
481 imx_uart_writel(sport, ucr1, UCR1);
482 imx_uart_writel(sport, ucr4, UCR4);
483
484 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
485 if (port->rs485.flags & SER_RS485_ENABLED &&
486 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
487 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
488 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
489 uts |= UTS_LOOP;
490 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
491 ucr2 |= UCR2_RXEN;
492 } else {
493 ucr2 &= ~UCR2_RXEN;
494 }
495
496 imx_uart_writel(sport, ucr2, UCR2);
497}
498
499/* called with port.lock taken and irqs off */
500static void imx_uart_stop_rx(struct uart_port *port)
501{
502 /*
503 * Stop RX and enable loopback in order to make sure RS485 bus
504 * is not blocked. Se comment in imx_uart_probe().
505 */
506 imx_uart_stop_rx_with_loopback_ctrl(port, true);
507}
508
509/* called with port.lock taken and irqs off */
510static void imx_uart_enable_ms(struct uart_port *port)
511{
512 struct imx_port *sport = (struct imx_port *)port;
513
514 mod_timer(&sport->timer, jiffies);
515
516 mctrl_gpio_enable_ms(sport->gpios);
517}
518
519static void imx_uart_dma_tx(struct imx_port *sport);
520
521/* called with port.lock taken and irqs off */
522static inline void imx_uart_transmit_buffer(struct imx_port *sport)
523{
524 struct circ_buf *xmit = &sport->port.state->xmit;
525
526 if (sport->port.x_char) {
527 /* Send next char */
528 imx_uart_writel(sport, sport->port.x_char, URTX0);
529 sport->port.icount.tx++;
530 sport->port.x_char = 0;
531 return;
532 }
533
534 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
535 imx_uart_stop_tx(&sport->port);
536 return;
537 }
538
539 if (sport->dma_is_enabled) {
540 u32 ucr1;
541 /*
542 * We've just sent a X-char Ensure the TX DMA is enabled
543 * and the TX IRQ is disabled.
544 **/
545 ucr1 = imx_uart_readl(sport, UCR1);
546 ucr1 &= ~UCR1_TRDYEN;
547 if (sport->dma_is_txing) {
548 ucr1 |= UCR1_TXDMAEN;
549 imx_uart_writel(sport, ucr1, UCR1);
550 } else {
551 imx_uart_writel(sport, ucr1, UCR1);
552 imx_uart_dma_tx(sport);
553 }
554
555 return;
556 }
557
558 while (!uart_circ_empty(xmit) &&
559 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
560 /* send xmit->buf[xmit->tail]
561 * out the port here */
562 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
563 uart_xmit_advance(&sport->port, 1);
564 }
565
566 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
567 uart_write_wakeup(&sport->port);
568
569 if (uart_circ_empty(xmit))
570 imx_uart_stop_tx(&sport->port);
571}
572
573static void imx_uart_dma_tx_callback(void *data)
574{
575 struct imx_port *sport = data;
576 struct scatterlist *sgl = &sport->tx_sgl[0];
577 struct circ_buf *xmit = &sport->port.state->xmit;
578 unsigned long flags;
579 u32 ucr1;
580
581 uart_port_lock_irqsave(&sport->port, &flags);
582
583 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
584
585 ucr1 = imx_uart_readl(sport, UCR1);
586 ucr1 &= ~UCR1_TXDMAEN;
587 imx_uart_writel(sport, ucr1, UCR1);
588
589 uart_xmit_advance(&sport->port, sport->tx_bytes);
590
591 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
592
593 sport->dma_is_txing = 0;
594
595 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
596 uart_write_wakeup(&sport->port);
597
598 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
599 imx_uart_dma_tx(sport);
600 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
601 u32 ucr4 = imx_uart_readl(sport, UCR4);
602 ucr4 |= UCR4_TCEN;
603 imx_uart_writel(sport, ucr4, UCR4);
604 }
605
606 uart_port_unlock_irqrestore(&sport->port, flags);
607}
608
609/* called with port.lock taken and irqs off */
610static void imx_uart_dma_tx(struct imx_port *sport)
611{
612 struct circ_buf *xmit = &sport->port.state->xmit;
613 struct scatterlist *sgl = sport->tx_sgl;
614 struct dma_async_tx_descriptor *desc;
615 struct dma_chan *chan = sport->dma_chan_tx;
616 struct device *dev = sport->port.dev;
617 u32 ucr1, ucr4;
618 int ret;
619
620 if (sport->dma_is_txing)
621 return;
622
623 ucr4 = imx_uart_readl(sport, UCR4);
624 ucr4 &= ~UCR4_TCEN;
625 imx_uart_writel(sport, ucr4, UCR4);
626
627 sport->tx_bytes = uart_circ_chars_pending(xmit);
628
629 if (xmit->tail < xmit->head || xmit->head == 0) {
630 sport->dma_tx_nents = 1;
631 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
632 } else {
633 sport->dma_tx_nents = 2;
634 sg_init_table(sgl, 2);
635 sg_set_buf(sgl, xmit->buf + xmit->tail,
636 UART_XMIT_SIZE - xmit->tail);
637 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
638 }
639
640 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
641 if (ret == 0) {
642 dev_err(dev, "DMA mapping error for TX.\n");
643 return;
644 }
645 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
646 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
647 if (!desc) {
648 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
649 DMA_TO_DEVICE);
650 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
651 return;
652 }
653 desc->callback = imx_uart_dma_tx_callback;
654 desc->callback_param = sport;
655
656 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
657 uart_circ_chars_pending(xmit));
658
659 ucr1 = imx_uart_readl(sport, UCR1);
660 ucr1 |= UCR1_TXDMAEN;
661 imx_uart_writel(sport, ucr1, UCR1);
662
663 /* fire it */
664 sport->dma_is_txing = 1;
665 dmaengine_submit(desc);
666 dma_async_issue_pending(chan);
667 return;
668}
669
670/* called with port.lock taken and irqs off */
671static void imx_uart_start_tx(struct uart_port *port)
672{
673 struct imx_port *sport = (struct imx_port *)port;
674 u32 ucr1;
675
676 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
677 return;
678
679 /*
680 * We cannot simply do nothing here if sport->tx_state == SEND already
681 * because UCR1_TXMPTYEN might already have been cleared in
682 * imx_uart_stop_tx(), but tx_state is still SEND.
683 */
684
685 if (port->rs485.flags & SER_RS485_ENABLED) {
686 if (sport->tx_state == OFF) {
687 u32 ucr2 = imx_uart_readl(sport, UCR2);
688 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
689 imx_uart_rts_active(sport, &ucr2);
690 else
691 imx_uart_rts_inactive(sport, &ucr2);
692 imx_uart_writel(sport, ucr2, UCR2);
693
694 /*
695 * Since we are about to transmit we can not stop RX
696 * with loopback enabled because that will make our
697 * transmitted data being just looped to RX.
698 */
699 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
700 !port->rs485_rx_during_tx_gpio)
701 imx_uart_stop_rx_with_loopback_ctrl(port, false);
702
703 sport->tx_state = WAIT_AFTER_RTS;
704
705 if (port->rs485.delay_rts_before_send > 0) {
706 start_hrtimer_ms(&sport->trigger_start_tx,
707 port->rs485.delay_rts_before_send);
708 return;
709 }
710
711 /* continue without any delay */
712 }
713
714 if (sport->tx_state == WAIT_AFTER_SEND
715 || sport->tx_state == WAIT_AFTER_RTS) {
716
717 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
718
719 /*
720 * Enable transmitter and shifter empty irq only if DMA
721 * is off. In the DMA case this is done in the
722 * tx-callback.
723 */
724 if (!sport->dma_is_enabled) {
725 u32 ucr4 = imx_uart_readl(sport, UCR4);
726 ucr4 |= UCR4_TCEN;
727 imx_uart_writel(sport, ucr4, UCR4);
728 }
729
730 sport->tx_state = SEND;
731 }
732 } else {
733 sport->tx_state = SEND;
734 }
735
736 if (!sport->dma_is_enabled) {
737 ucr1 = imx_uart_readl(sport, UCR1);
738 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
739 }
740
741 if (sport->dma_is_enabled) {
742 if (sport->port.x_char) {
743 /* We have X-char to send, so enable TX IRQ and
744 * disable TX DMA to let TX interrupt to send X-char */
745 ucr1 = imx_uart_readl(sport, UCR1);
746 ucr1 &= ~UCR1_TXDMAEN;
747 ucr1 |= UCR1_TRDYEN;
748 imx_uart_writel(sport, ucr1, UCR1);
749 return;
750 }
751
752 if (!uart_circ_empty(&port->state->xmit) &&
753 !uart_tx_stopped(port))
754 imx_uart_dma_tx(sport);
755 return;
756 }
757}
758
759static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
760{
761 struct imx_port *sport = dev_id;
762 u32 usr1;
763
764 imx_uart_writel(sport, USR1_RTSD, USR1);
765 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
766 uart_handle_cts_change(&sport->port, usr1);
767 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
768
769 return IRQ_HANDLED;
770}
771
772static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
773{
774 struct imx_port *sport = dev_id;
775 irqreturn_t ret;
776
777 uart_port_lock(&sport->port);
778
779 ret = __imx_uart_rtsint(irq, dev_id);
780
781 uart_port_unlock(&sport->port);
782
783 return ret;
784}
785
786static irqreturn_t imx_uart_txint(int irq, void *dev_id)
787{
788 struct imx_port *sport = dev_id;
789
790 uart_port_lock(&sport->port);
791 imx_uart_transmit_buffer(sport);
792 uart_port_unlock(&sport->port);
793 return IRQ_HANDLED;
794}
795
796/* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
797 * This is to be called from Rx ISRs only when some bytes were actually
798 * received.
799 *
800 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
801 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
802 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
803 * that is terminated by any activity on RxD line, or could be stopped by
804 * issuing soft reset to the UART (just stop/start of RX does not help). Note
805 * that what we do here is sending isolated start bit about 2.4 times shorter
806 * than it is to be on UART configured baud rate.
807 */
808static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
809{
810 /* To detect hardware 0xff flood we monitor RxD line between RX
811 * interrupts to isolate "receiving" of char(s) with no activity
812 * on RxD line, that'd never happen on actual data transfers.
813 *
814 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
815 * race here if we clear USR2_WAKE when receiving of a char is in
816 * progress, so we might get RX interrupt later with USR2_WAKE bit
817 * cleared. Note though that as we don't try to clear USR2_WAKE when we
818 * detected no activity, this race may hide actual activity only once.
819 *
820 * Yet another case where receive interrupt may occur without RxD
821 * activity is expiration of aging timer, so we consider this as well.
822 *
823 * We use 'idle_counter' to ensure that we got at least so many RX
824 * interrupts without any detected activity on RxD line. 2 cases
825 * described plus 1 to be on the safe side gives us a margin of 3,
826 * below. In practice I was not able to produce a false positive to
827 * induce soft reset at regular data transfers even using 1 as the
828 * margin, so 3 is actually very strong.
829 *
830 * We count interrupts, not chars in 'idle-counter' for simplicity.
831 */
832
833 if (usr2 & USR2_WAKE) {
834 imx_uart_writel(sport, USR2_WAKE, USR2);
835 sport->idle_counter = 0;
836 } else if (++sport->idle_counter > 3) {
837 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
838 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
839 }
840}
841
842static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
843{
844 struct imx_port *sport = dev_id;
845 struct tty_port *port = &sport->port.state->port;
846 u32 usr2, rx;
847
848 /* If we received something, check for 0xff flood */
849 usr2 = imx_uart_readl(sport, USR2);
850 if (usr2 & USR2_RDR)
851 imx_uart_check_flood(sport, usr2);
852
853 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
854 unsigned int flg = TTY_NORMAL;
855 sport->port.icount.rx++;
856
857 if (unlikely(rx & URXD_ERR)) {
858 if (rx & URXD_BRK) {
859 sport->port.icount.brk++;
860 if (uart_handle_break(&sport->port))
861 continue;
862 }
863 else if (rx & URXD_PRERR)
864 sport->port.icount.parity++;
865 else if (rx & URXD_FRMERR)
866 sport->port.icount.frame++;
867 if (rx & URXD_OVRRUN)
868 sport->port.icount.overrun++;
869
870 if (rx & sport->port.ignore_status_mask)
871 continue;
872
873 rx &= (sport->port.read_status_mask | 0xFF);
874
875 if (rx & URXD_BRK)
876 flg = TTY_BREAK;
877 else if (rx & URXD_PRERR)
878 flg = TTY_PARITY;
879 else if (rx & URXD_FRMERR)
880 flg = TTY_FRAME;
881 if (rx & URXD_OVRRUN)
882 flg = TTY_OVERRUN;
883
884 sport->port.sysrq = 0;
885 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
886 continue;
887 }
888
889 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
890 continue;
891
892 if (tty_insert_flip_char(port, rx, flg) == 0)
893 sport->port.icount.buf_overrun++;
894 }
895
896 tty_flip_buffer_push(port);
897
898 return IRQ_HANDLED;
899}
900
901static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
902{
903 struct imx_port *sport = dev_id;
904 irqreturn_t ret;
905
906 uart_port_lock(&sport->port);
907
908 ret = __imx_uart_rxint(irq, dev_id);
909
910 uart_port_unlock(&sport->port);
911
912 return ret;
913}
914
915static void imx_uart_clear_rx_errors(struct imx_port *sport);
916
917/*
918 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
919 */
920static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
921{
922 unsigned int tmp = TIOCM_DSR;
923 unsigned usr1 = imx_uart_readl(sport, USR1);
924 unsigned usr2 = imx_uart_readl(sport, USR2);
925
926 if (usr1 & USR1_RTSS)
927 tmp |= TIOCM_CTS;
928
929 /* in DCE mode DCDIN is always 0 */
930 if (!(usr2 & USR2_DCDIN))
931 tmp |= TIOCM_CAR;
932
933 if (sport->dte_mode)
934 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
935 tmp |= TIOCM_RI;
936
937 return tmp;
938}
939
940/*
941 * Handle any change of modem status signal since we were last called.
942 */
943static void imx_uart_mctrl_check(struct imx_port *sport)
944{
945 unsigned int status, changed;
946
947 status = imx_uart_get_hwmctrl(sport);
948 changed = status ^ sport->old_status;
949
950 if (changed == 0)
951 return;
952
953 sport->old_status = status;
954
955 if (changed & TIOCM_RI && status & TIOCM_RI)
956 sport->port.icount.rng++;
957 if (changed & TIOCM_DSR)
958 sport->port.icount.dsr++;
959 if (changed & TIOCM_CAR)
960 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
961 if (changed & TIOCM_CTS)
962 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
963
964 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
965}
966
967static irqreturn_t imx_uart_int(int irq, void *dev_id)
968{
969 struct imx_port *sport = dev_id;
970 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
971 irqreturn_t ret = IRQ_NONE;
972
973 uart_port_lock(&sport->port);
974
975 usr1 = imx_uart_readl(sport, USR1);
976 usr2 = imx_uart_readl(sport, USR2);
977 ucr1 = imx_uart_readl(sport, UCR1);
978 ucr2 = imx_uart_readl(sport, UCR2);
979 ucr3 = imx_uart_readl(sport, UCR3);
980 ucr4 = imx_uart_readl(sport, UCR4);
981
982 /*
983 * Even if a condition is true that can trigger an irq only handle it if
984 * the respective irq source is enabled. This prevents some undesired
985 * actions, for example if a character that sits in the RX FIFO and that
986 * should be fetched via DMA is tried to be fetched using PIO. Or the
987 * receiver is currently off and so reading from URXD0 results in an
988 * exception. So just mask the (raw) status bits for disabled irqs.
989 */
990 if ((ucr1 & UCR1_RRDYEN) == 0)
991 usr1 &= ~USR1_RRDY;
992 if ((ucr2 & UCR2_ATEN) == 0)
993 usr1 &= ~USR1_AGTIM;
994 if ((ucr1 & UCR1_TRDYEN) == 0)
995 usr1 &= ~USR1_TRDY;
996 if ((ucr4 & UCR4_TCEN) == 0)
997 usr2 &= ~USR2_TXDC;
998 if ((ucr3 & UCR3_DTRDEN) == 0)
999 usr1 &= ~USR1_DTRD;
1000 if ((ucr1 & UCR1_RTSDEN) == 0)
1001 usr1 &= ~USR1_RTSD;
1002 if ((ucr3 & UCR3_AWAKEN) == 0)
1003 usr1 &= ~USR1_AWAKE;
1004 if ((ucr4 & UCR4_OREN) == 0)
1005 usr2 &= ~USR2_ORE;
1006
1007 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1008 imx_uart_writel(sport, USR1_AGTIM, USR1);
1009
1010 __imx_uart_rxint(irq, dev_id);
1011 ret = IRQ_HANDLED;
1012 }
1013
1014 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1015 imx_uart_transmit_buffer(sport);
1016 ret = IRQ_HANDLED;
1017 }
1018
1019 if (usr1 & USR1_DTRD) {
1020 imx_uart_writel(sport, USR1_DTRD, USR1);
1021
1022 imx_uart_mctrl_check(sport);
1023
1024 ret = IRQ_HANDLED;
1025 }
1026
1027 if (usr1 & USR1_RTSD) {
1028 __imx_uart_rtsint(irq, dev_id);
1029 ret = IRQ_HANDLED;
1030 }
1031
1032 if (usr1 & USR1_AWAKE) {
1033 imx_uart_writel(sport, USR1_AWAKE, USR1);
1034 ret = IRQ_HANDLED;
1035 }
1036
1037 if (usr2 & USR2_ORE) {
1038 sport->port.icount.overrun++;
1039 imx_uart_writel(sport, USR2_ORE, USR2);
1040 ret = IRQ_HANDLED;
1041 }
1042
1043 uart_port_unlock(&sport->port);
1044
1045 return ret;
1046}
1047
1048/*
1049 * Return TIOCSER_TEMT when transmitter is not busy.
1050 */
1051static unsigned int imx_uart_tx_empty(struct uart_port *port)
1052{
1053 struct imx_port *sport = (struct imx_port *)port;
1054 unsigned int ret;
1055
1056 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1057
1058 /* If the TX DMA is working, return 0. */
1059 if (sport->dma_is_txing)
1060 ret = 0;
1061
1062 return ret;
1063}
1064
1065/* called with port.lock taken and irqs off */
1066static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1067{
1068 struct imx_port *sport = (struct imx_port *)port;
1069 unsigned int ret = imx_uart_get_hwmctrl(sport);
1070
1071 mctrl_gpio_get(sport->gpios, &ret);
1072
1073 return ret;
1074}
1075
1076/* called with port.lock taken and irqs off */
1077static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1078{
1079 struct imx_port *sport = (struct imx_port *)port;
1080 u32 ucr3, uts;
1081
1082 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1083 u32 ucr2;
1084
1085 /*
1086 * Turn off autoRTS if RTS is lowered and restore autoRTS
1087 * setting if RTS is raised.
1088 */
1089 ucr2 = imx_uart_readl(sport, UCR2);
1090 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1091 if (mctrl & TIOCM_RTS) {
1092 ucr2 |= UCR2_CTS;
1093 /*
1094 * UCR2_IRTS is unset if and only if the port is
1095 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1096 * to get the state to restore to.
1097 */
1098 if (!(ucr2 & UCR2_IRTS))
1099 ucr2 |= UCR2_CTSC;
1100 }
1101 imx_uart_writel(sport, ucr2, UCR2);
1102 }
1103
1104 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1105 if (!(mctrl & TIOCM_DTR))
1106 ucr3 |= UCR3_DSR;
1107 imx_uart_writel(sport, ucr3, UCR3);
1108
1109 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1110 if (mctrl & TIOCM_LOOP)
1111 uts |= UTS_LOOP;
1112 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1113
1114 mctrl_gpio_set(sport->gpios, mctrl);
1115}
1116
1117/*
1118 * Interrupts always disabled.
1119 */
1120static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1121{
1122 struct imx_port *sport = (struct imx_port *)port;
1123 unsigned long flags;
1124 u32 ucr1;
1125
1126 uart_port_lock_irqsave(&sport->port, &flags);
1127
1128 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1129
1130 if (break_state != 0)
1131 ucr1 |= UCR1_SNDBRK;
1132
1133 imx_uart_writel(sport, ucr1, UCR1);
1134
1135 uart_port_unlock_irqrestore(&sport->port, flags);
1136}
1137
1138/*
1139 * This is our per-port timeout handler, for checking the
1140 * modem status signals.
1141 */
1142static void imx_uart_timeout(struct timer_list *t)
1143{
1144 struct imx_port *sport = from_timer(sport, t, timer);
1145 unsigned long flags;
1146
1147 if (sport->port.state) {
1148 uart_port_lock_irqsave(&sport->port, &flags);
1149 imx_uart_mctrl_check(sport);
1150 uart_port_unlock_irqrestore(&sport->port, flags);
1151
1152 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1153 }
1154}
1155
1156/*
1157 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1158 * [1] the RX DMA buffer is full.
1159 * [2] the aging timer expires
1160 *
1161 * Condition [2] is triggered when a character has been sitting in the FIFO
1162 * for at least 8 byte durations.
1163 */
1164static void imx_uart_dma_rx_callback(void *data)
1165{
1166 struct imx_port *sport = data;
1167 struct dma_chan *chan = sport->dma_chan_rx;
1168 struct scatterlist *sgl = &sport->rx_sgl;
1169 struct tty_port *port = &sport->port.state->port;
1170 struct dma_tx_state state;
1171 struct circ_buf *rx_ring = &sport->rx_ring;
1172 enum dma_status status;
1173 unsigned int w_bytes = 0;
1174 unsigned int r_bytes;
1175 unsigned int bd_size;
1176
1177 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1178
1179 if (status == DMA_ERROR) {
1180 uart_port_lock(&sport->port);
1181 imx_uart_clear_rx_errors(sport);
1182 uart_port_unlock(&sport->port);
1183 return;
1184 }
1185
1186 /*
1187 * The state-residue variable represents the empty space
1188 * relative to the entire buffer. Taking this in consideration
1189 * the head is always calculated base on the buffer total
1190 * length - DMA transaction residue. The UART script from the
1191 * SDMA firmware will jump to the next buffer descriptor,
1192 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1193 * Taking this in consideration the tail is always at the
1194 * beginning of the buffer descriptor that contains the head.
1195 */
1196
1197 /* Calculate the head */
1198 rx_ring->head = sg_dma_len(sgl) - state.residue;
1199
1200 /* Calculate the tail. */
1201 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1202 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1203
1204 if (rx_ring->head <= sg_dma_len(sgl) &&
1205 rx_ring->head > rx_ring->tail) {
1206
1207 /* Move data from tail to head */
1208 r_bytes = rx_ring->head - rx_ring->tail;
1209
1210 /* If we received something, check for 0xff flood */
1211 uart_port_lock(&sport->port);
1212 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1213 uart_port_unlock(&sport->port);
1214
1215 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1216
1217 /* CPU claims ownership of RX DMA buffer */
1218 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1219 DMA_FROM_DEVICE);
1220
1221 w_bytes = tty_insert_flip_string(port,
1222 sport->rx_buf + rx_ring->tail, r_bytes);
1223
1224 /* UART retrieves ownership of RX DMA buffer */
1225 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1226 DMA_FROM_DEVICE);
1227
1228 if (w_bytes != r_bytes)
1229 sport->port.icount.buf_overrun++;
1230
1231 sport->port.icount.rx += w_bytes;
1232 }
1233 } else {
1234 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1235 WARN_ON(rx_ring->head <= rx_ring->tail);
1236 }
1237
1238 if (w_bytes) {
1239 tty_flip_buffer_push(port);
1240 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1241 }
1242}
1243
1244static int imx_uart_start_rx_dma(struct imx_port *sport)
1245{
1246 struct scatterlist *sgl = &sport->rx_sgl;
1247 struct dma_chan *chan = sport->dma_chan_rx;
1248 struct device *dev = sport->port.dev;
1249 struct dma_async_tx_descriptor *desc;
1250 int ret;
1251
1252 sport->rx_ring.head = 0;
1253 sport->rx_ring.tail = 0;
1254
1255 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1256 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1257 if (ret == 0) {
1258 dev_err(dev, "DMA mapping error for RX.\n");
1259 return -EINVAL;
1260 }
1261
1262 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1263 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1264 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1265
1266 if (!desc) {
1267 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1268 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1269 return -EINVAL;
1270 }
1271 desc->callback = imx_uart_dma_rx_callback;
1272 desc->callback_param = sport;
1273
1274 dev_dbg(dev, "RX: prepare for the DMA.\n");
1275 sport->dma_is_rxing = 1;
1276 sport->rx_cookie = dmaengine_submit(desc);
1277 dma_async_issue_pending(chan);
1278 return 0;
1279}
1280
1281static void imx_uart_clear_rx_errors(struct imx_port *sport)
1282{
1283 struct tty_port *port = &sport->port.state->port;
1284 u32 usr1, usr2;
1285
1286 usr1 = imx_uart_readl(sport, USR1);
1287 usr2 = imx_uart_readl(sport, USR2);
1288
1289 if (usr2 & USR2_BRCD) {
1290 sport->port.icount.brk++;
1291 imx_uart_writel(sport, USR2_BRCD, USR2);
1292 uart_handle_break(&sport->port);
1293 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1294 sport->port.icount.buf_overrun++;
1295 tty_flip_buffer_push(port);
1296 } else {
1297 if (usr1 & USR1_FRAMERR) {
1298 sport->port.icount.frame++;
1299 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1300 } else if (usr1 & USR1_PARITYERR) {
1301 sport->port.icount.parity++;
1302 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1303 }
1304 }
1305
1306 if (usr2 & USR2_ORE) {
1307 sport->port.icount.overrun++;
1308 imx_uart_writel(sport, USR2_ORE, USR2);
1309 }
1310
1311 sport->idle_counter = 0;
1312
1313}
1314
1315#define TXTL_DEFAULT 2 /* reset default */
1316#define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1317#define TXTL_DMA 8 /* DMA burst setting */
1318#define RXTL_DMA 9 /* DMA burst setting */
1319
1320static void imx_uart_setup_ufcr(struct imx_port *sport,
1321 unsigned char txwl, unsigned char rxwl)
1322{
1323 unsigned int val;
1324
1325 /* set receiver / transmitter trigger level */
1326 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1327 val |= txwl << UFCR_TXTL_SHF | rxwl;
1328 imx_uart_writel(sport, val, UFCR);
1329}
1330
1331static void imx_uart_dma_exit(struct imx_port *sport)
1332{
1333 if (sport->dma_chan_rx) {
1334 dmaengine_terminate_sync(sport->dma_chan_rx);
1335 dma_release_channel(sport->dma_chan_rx);
1336 sport->dma_chan_rx = NULL;
1337 sport->rx_cookie = -EINVAL;
1338 kfree(sport->rx_buf);
1339 sport->rx_buf = NULL;
1340 }
1341
1342 if (sport->dma_chan_tx) {
1343 dmaengine_terminate_sync(sport->dma_chan_tx);
1344 dma_release_channel(sport->dma_chan_tx);
1345 sport->dma_chan_tx = NULL;
1346 }
1347}
1348
1349static int imx_uart_dma_init(struct imx_port *sport)
1350{
1351 struct dma_slave_config slave_config = {};
1352 struct device *dev = sport->port.dev;
1353 struct dma_chan *chan;
1354 int ret;
1355
1356 /* Prepare for RX : */
1357 chan = dma_request_chan(dev, "rx");
1358 if (IS_ERR(chan)) {
1359 dev_dbg(dev, "cannot get the DMA channel.\n");
1360 sport->dma_chan_rx = NULL;
1361 ret = PTR_ERR(chan);
1362 goto err;
1363 }
1364 sport->dma_chan_rx = chan;
1365
1366 slave_config.direction = DMA_DEV_TO_MEM;
1367 slave_config.src_addr = sport->port.mapbase + URXD0;
1368 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1369 /* one byte less than the watermark level to enable the aging timer */
1370 slave_config.src_maxburst = RXTL_DMA - 1;
1371 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1372 if (ret) {
1373 dev_err(dev, "error in RX dma configuration.\n");
1374 goto err;
1375 }
1376
1377 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1378 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1379 if (!sport->rx_buf) {
1380 ret = -ENOMEM;
1381 goto err;
1382 }
1383 sport->rx_ring.buf = sport->rx_buf;
1384
1385 /* Prepare for TX : */
1386 chan = dma_request_chan(dev, "tx");
1387 if (IS_ERR(chan)) {
1388 dev_err(dev, "cannot get the TX DMA channel!\n");
1389 sport->dma_chan_tx = NULL;
1390 ret = PTR_ERR(chan);
1391 goto err;
1392 }
1393 sport->dma_chan_tx = chan;
1394
1395 slave_config.direction = DMA_MEM_TO_DEV;
1396 slave_config.dst_addr = sport->port.mapbase + URTX0;
1397 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1398 slave_config.dst_maxburst = TXTL_DMA;
1399 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1400 if (ret) {
1401 dev_err(dev, "error in TX dma configuration.");
1402 goto err;
1403 }
1404
1405 return 0;
1406err:
1407 imx_uart_dma_exit(sport);
1408 return ret;
1409}
1410
1411static void imx_uart_enable_dma(struct imx_port *sport)
1412{
1413 u32 ucr1;
1414
1415 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1416
1417 /* set UCR1 */
1418 ucr1 = imx_uart_readl(sport, UCR1);
1419 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1420 imx_uart_writel(sport, ucr1, UCR1);
1421
1422 sport->dma_is_enabled = 1;
1423}
1424
1425static void imx_uart_disable_dma(struct imx_port *sport)
1426{
1427 u32 ucr1;
1428
1429 /* clear UCR1 */
1430 ucr1 = imx_uart_readl(sport, UCR1);
1431 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1432 imx_uart_writel(sport, ucr1, UCR1);
1433
1434 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1435
1436 sport->dma_is_enabled = 0;
1437}
1438
1439/* half the RX buffer size */
1440#define CTSTL 16
1441
1442static int imx_uart_startup(struct uart_port *port)
1443{
1444 struct imx_port *sport = (struct imx_port *)port;
1445 int retval;
1446 unsigned long flags;
1447 int dma_is_inited = 0;
1448 u32 ucr1, ucr2, ucr3, ucr4;
1449
1450 retval = clk_prepare_enable(sport->clk_per);
1451 if (retval)
1452 return retval;
1453 retval = clk_prepare_enable(sport->clk_ipg);
1454 if (retval) {
1455 clk_disable_unprepare(sport->clk_per);
1456 return retval;
1457 }
1458
1459 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1460
1461 /* disable the DREN bit (Data Ready interrupt enable) before
1462 * requesting IRQs
1463 */
1464 ucr4 = imx_uart_readl(sport, UCR4);
1465
1466 /* set the trigger level for CTS */
1467 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1468 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1469
1470 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1471
1472 /* Can we enable the DMA support? */
1473 if (!uart_console(port) && imx_uart_dma_init(sport) == 0) {
1474 lockdep_set_subclass(&port->lock, 1);
1475 dma_is_inited = 1;
1476 }
1477
1478 uart_port_lock_irqsave(&sport->port, &flags);
1479
1480 /* Reset fifo's and state machines */
1481 imx_uart_soft_reset(sport);
1482
1483 /*
1484 * Finally, clear and enable interrupts
1485 */
1486 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1487 imx_uart_writel(sport, USR2_ORE, USR2);
1488
1489 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1490 ucr1 |= UCR1_UARTEN;
1491 if (sport->have_rtscts)
1492 ucr1 |= UCR1_RTSDEN;
1493
1494 imx_uart_writel(sport, ucr1, UCR1);
1495
1496 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1497 if (!dma_is_inited)
1498 ucr4 |= UCR4_OREN;
1499 if (sport->inverted_rx)
1500 ucr4 |= UCR4_INVR;
1501 imx_uart_writel(sport, ucr4, UCR4);
1502
1503 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1504 /*
1505 * configure tx polarity before enabling tx
1506 */
1507 if (sport->inverted_tx)
1508 ucr3 |= UCR3_INVT;
1509
1510 if (!imx_uart_is_imx1(sport)) {
1511 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1512
1513 if (sport->dte_mode)
1514 /* disable broken interrupts */
1515 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1516 }
1517 imx_uart_writel(sport, ucr3, UCR3);
1518
1519 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1520 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1521 if (!sport->have_rtscts)
1522 ucr2 |= UCR2_IRTS;
1523 /*
1524 * make sure the edge sensitive RTS-irq is disabled,
1525 * we're using RTSD instead.
1526 */
1527 if (!imx_uart_is_imx1(sport))
1528 ucr2 &= ~UCR2_RTSEN;
1529 imx_uart_writel(sport, ucr2, UCR2);
1530
1531 /*
1532 * Enable modem status interrupts
1533 */
1534 imx_uart_enable_ms(&sport->port);
1535
1536 if (dma_is_inited) {
1537 imx_uart_enable_dma(sport);
1538 imx_uart_start_rx_dma(sport);
1539 } else {
1540 ucr1 = imx_uart_readl(sport, UCR1);
1541 ucr1 |= UCR1_RRDYEN;
1542 imx_uart_writel(sport, ucr1, UCR1);
1543
1544 ucr2 = imx_uart_readl(sport, UCR2);
1545 ucr2 |= UCR2_ATEN;
1546 imx_uart_writel(sport, ucr2, UCR2);
1547 }
1548
1549 imx_uart_disable_loopback_rs485(sport);
1550
1551 uart_port_unlock_irqrestore(&sport->port, flags);
1552
1553 return 0;
1554}
1555
1556static void imx_uart_shutdown(struct uart_port *port)
1557{
1558 struct imx_port *sport = (struct imx_port *)port;
1559 unsigned long flags;
1560 u32 ucr1, ucr2, ucr4, uts;
1561
1562 if (sport->dma_is_enabled) {
1563 dmaengine_terminate_sync(sport->dma_chan_tx);
1564 if (sport->dma_is_txing) {
1565 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1566 sport->dma_tx_nents, DMA_TO_DEVICE);
1567 sport->dma_is_txing = 0;
1568 }
1569 dmaengine_terminate_sync(sport->dma_chan_rx);
1570 if (sport->dma_is_rxing) {
1571 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1572 1, DMA_FROM_DEVICE);
1573 sport->dma_is_rxing = 0;
1574 }
1575
1576 uart_port_lock_irqsave(&sport->port, &flags);
1577 imx_uart_stop_tx(port);
1578 imx_uart_stop_rx(port);
1579 imx_uart_disable_dma(sport);
1580 uart_port_unlock_irqrestore(&sport->port, flags);
1581 imx_uart_dma_exit(sport);
1582 }
1583
1584 mctrl_gpio_disable_ms(sport->gpios);
1585
1586 uart_port_lock_irqsave(&sport->port, &flags);
1587 ucr2 = imx_uart_readl(sport, UCR2);
1588 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1589 imx_uart_writel(sport, ucr2, UCR2);
1590 uart_port_unlock_irqrestore(&sport->port, flags);
1591
1592 /*
1593 * Stop our timer.
1594 */
1595 del_timer_sync(&sport->timer);
1596
1597 /*
1598 * Disable all interrupts, port and break condition.
1599 */
1600
1601 uart_port_lock_irqsave(&sport->port, &flags);
1602
1603 ucr1 = imx_uart_readl(sport, UCR1);
1604 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1605 UCR1_ATDMAEN | UCR1_SNDBRK);
1606 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1607 if (port->rs485.flags & SER_RS485_ENABLED &&
1608 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1609 sport->have_rtscts && !sport->have_rtsgpio) {
1610 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1611 uts |= UTS_LOOP;
1612 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1613 ucr1 |= UCR1_UARTEN;
1614 } else {
1615 ucr1 &= ~UCR1_UARTEN;
1616 }
1617 imx_uart_writel(sport, ucr1, UCR1);
1618
1619 ucr4 = imx_uart_readl(sport, UCR4);
1620 ucr4 &= ~UCR4_TCEN;
1621 imx_uart_writel(sport, ucr4, UCR4);
1622
1623 uart_port_unlock_irqrestore(&sport->port, flags);
1624
1625 clk_disable_unprepare(sport->clk_per);
1626 clk_disable_unprepare(sport->clk_ipg);
1627}
1628
1629/* called with port.lock taken and irqs off */
1630static void imx_uart_flush_buffer(struct uart_port *port)
1631{
1632 struct imx_port *sport = (struct imx_port *)port;
1633 struct scatterlist *sgl = &sport->tx_sgl[0];
1634
1635 if (!sport->dma_chan_tx)
1636 return;
1637
1638 sport->tx_bytes = 0;
1639 dmaengine_terminate_all(sport->dma_chan_tx);
1640 if (sport->dma_is_txing) {
1641 u32 ucr1;
1642
1643 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1644 DMA_TO_DEVICE);
1645 ucr1 = imx_uart_readl(sport, UCR1);
1646 ucr1 &= ~UCR1_TXDMAEN;
1647 imx_uart_writel(sport, ucr1, UCR1);
1648 sport->dma_is_txing = 0;
1649 }
1650
1651 imx_uart_soft_reset(sport);
1652
1653}
1654
1655static void
1656imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1657 const struct ktermios *old)
1658{
1659 struct imx_port *sport = (struct imx_port *)port;
1660 unsigned long flags;
1661 u32 ucr2, old_ucr2, ufcr;
1662 unsigned int baud, quot;
1663 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1664 unsigned long div;
1665 unsigned long num, denom, old_ubir, old_ubmr;
1666 uint64_t tdiv64;
1667
1668 /*
1669 * We only support CS7 and CS8.
1670 */
1671 while ((termios->c_cflag & CSIZE) != CS7 &&
1672 (termios->c_cflag & CSIZE) != CS8) {
1673 termios->c_cflag &= ~CSIZE;
1674 termios->c_cflag |= old_csize;
1675 old_csize = CS8;
1676 }
1677
1678 del_timer_sync(&sport->timer);
1679
1680 /*
1681 * Ask the core to calculate the divisor for us.
1682 */
1683 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1684 quot = uart_get_divisor(port, baud);
1685
1686 uart_port_lock_irqsave(&sport->port, &flags);
1687
1688 /*
1689 * Read current UCR2 and save it for future use, then clear all the bits
1690 * except those we will or may need to preserve.
1691 */
1692 old_ucr2 = imx_uart_readl(sport, UCR2);
1693 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1694
1695 ucr2 |= UCR2_SRST | UCR2_IRTS;
1696 if ((termios->c_cflag & CSIZE) == CS8)
1697 ucr2 |= UCR2_WS;
1698
1699 if (!sport->have_rtscts)
1700 termios->c_cflag &= ~CRTSCTS;
1701
1702 if (port->rs485.flags & SER_RS485_ENABLED) {
1703 /*
1704 * RTS is mandatory for rs485 operation, so keep
1705 * it under manual control and keep transmitter
1706 * disabled.
1707 */
1708 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1709 imx_uart_rts_active(sport, &ucr2);
1710 else
1711 imx_uart_rts_inactive(sport, &ucr2);
1712
1713 } else if (termios->c_cflag & CRTSCTS) {
1714 /*
1715 * Only let receiver control RTS output if we were not requested
1716 * to have RTS inactive (which then should take precedence).
1717 */
1718 if (ucr2 & UCR2_CTS)
1719 ucr2 |= UCR2_CTSC;
1720 }
1721
1722 if (termios->c_cflag & CRTSCTS)
1723 ucr2 &= ~UCR2_IRTS;
1724 if (termios->c_cflag & CSTOPB)
1725 ucr2 |= UCR2_STPB;
1726 if (termios->c_cflag & PARENB) {
1727 ucr2 |= UCR2_PREN;
1728 if (termios->c_cflag & PARODD)
1729 ucr2 |= UCR2_PROE;
1730 }
1731
1732 sport->port.read_status_mask = 0;
1733 if (termios->c_iflag & INPCK)
1734 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1735 if (termios->c_iflag & (BRKINT | PARMRK))
1736 sport->port.read_status_mask |= URXD_BRK;
1737
1738 /*
1739 * Characters to ignore
1740 */
1741 sport->port.ignore_status_mask = 0;
1742 if (termios->c_iflag & IGNPAR)
1743 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1744 if (termios->c_iflag & IGNBRK) {
1745 sport->port.ignore_status_mask |= URXD_BRK;
1746 /*
1747 * If we're ignoring parity and break indicators,
1748 * ignore overruns too (for real raw support).
1749 */
1750 if (termios->c_iflag & IGNPAR)
1751 sport->port.ignore_status_mask |= URXD_OVRRUN;
1752 }
1753
1754 if ((termios->c_cflag & CREAD) == 0)
1755 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1756
1757 /*
1758 * Update the per-port timeout.
1759 */
1760 uart_update_timeout(port, termios->c_cflag, baud);
1761
1762 /* custom-baudrate handling */
1763 div = sport->port.uartclk / (baud * 16);
1764 if (baud == 38400 && quot != div)
1765 baud = sport->port.uartclk / (quot * 16);
1766
1767 div = sport->port.uartclk / (baud * 16);
1768 if (div > 7)
1769 div = 7;
1770 if (!div)
1771 div = 1;
1772
1773 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1774 1 << 16, 1 << 16, &num, &denom);
1775
1776 tdiv64 = sport->port.uartclk;
1777 tdiv64 *= num;
1778 do_div(tdiv64, denom * 16 * div);
1779 tty_termios_encode_baud_rate(termios,
1780 (speed_t)tdiv64, (speed_t)tdiv64);
1781
1782 num -= 1;
1783 denom -= 1;
1784
1785 ufcr = imx_uart_readl(sport, UFCR);
1786 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1787 imx_uart_writel(sport, ufcr, UFCR);
1788
1789 /*
1790 * Two registers below should always be written both and in this
1791 * particular order. One consequence is that we need to check if any of
1792 * them changes and then update both. We do need the check for change
1793 * as even writing the same values seem to "restart"
1794 * transmission/receiving logic in the hardware, that leads to data
1795 * breakage even when rate doesn't in fact change. E.g., user switches
1796 * RTS/CTS handshake and suddenly gets broken bytes.
1797 */
1798 old_ubir = imx_uart_readl(sport, UBIR);
1799 old_ubmr = imx_uart_readl(sport, UBMR);
1800 if (old_ubir != num || old_ubmr != denom) {
1801 imx_uart_writel(sport, num, UBIR);
1802 imx_uart_writel(sport, denom, UBMR);
1803 }
1804
1805 if (!imx_uart_is_imx1(sport))
1806 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1807 IMX21_ONEMS);
1808
1809 imx_uart_writel(sport, ucr2, UCR2);
1810
1811 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1812 imx_uart_enable_ms(&sport->port);
1813
1814 uart_port_unlock_irqrestore(&sport->port, flags);
1815}
1816
1817static const char *imx_uart_type(struct uart_port *port)
1818{
1819 return port->type == PORT_IMX ? "IMX" : NULL;
1820}
1821
1822/*
1823 * Configure/autoconfigure the port.
1824 */
1825static void imx_uart_config_port(struct uart_port *port, int flags)
1826{
1827 if (flags & UART_CONFIG_TYPE)
1828 port->type = PORT_IMX;
1829}
1830
1831/*
1832 * Verify the new serial_struct (for TIOCSSERIAL).
1833 * The only change we allow are to the flags and type, and
1834 * even then only between PORT_IMX and PORT_UNKNOWN
1835 */
1836static int
1837imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1838{
1839 int ret = 0;
1840
1841 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1842 ret = -EINVAL;
1843 if (port->irq != ser->irq)
1844 ret = -EINVAL;
1845 if (ser->io_type != UPIO_MEM)
1846 ret = -EINVAL;
1847 if (port->uartclk / 16 != ser->baud_base)
1848 ret = -EINVAL;
1849 if (port->mapbase != (unsigned long)ser->iomem_base)
1850 ret = -EINVAL;
1851 if (port->iobase != ser->port)
1852 ret = -EINVAL;
1853 if (ser->hub6 != 0)
1854 ret = -EINVAL;
1855 return ret;
1856}
1857
1858#if defined(CONFIG_CONSOLE_POLL)
1859
1860static int imx_uart_poll_init(struct uart_port *port)
1861{
1862 struct imx_port *sport = (struct imx_port *)port;
1863 unsigned long flags;
1864 u32 ucr1, ucr2;
1865 int retval;
1866
1867 retval = clk_prepare_enable(sport->clk_ipg);
1868 if (retval)
1869 return retval;
1870 retval = clk_prepare_enable(sport->clk_per);
1871 if (retval)
1872 clk_disable_unprepare(sport->clk_ipg);
1873
1874 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1875
1876 uart_port_lock_irqsave(&sport->port, &flags);
1877
1878 /*
1879 * Be careful about the order of enabling bits here. First enable the
1880 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1881 * This prevents that a character that already sits in the RX fifo is
1882 * triggering an irq but the try to fetch it from there results in an
1883 * exception because UARTEN or RXEN is still off.
1884 */
1885 ucr1 = imx_uart_readl(sport, UCR1);
1886 ucr2 = imx_uart_readl(sport, UCR2);
1887
1888 if (imx_uart_is_imx1(sport))
1889 ucr1 |= IMX1_UCR1_UARTCLKEN;
1890
1891 ucr1 |= UCR1_UARTEN;
1892 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1893
1894 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1895 ucr2 &= ~UCR2_ATEN;
1896
1897 imx_uart_writel(sport, ucr1, UCR1);
1898 imx_uart_writel(sport, ucr2, UCR2);
1899
1900 /* now enable irqs */
1901 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1902 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1903
1904 uart_port_unlock_irqrestore(&sport->port, flags);
1905
1906 return 0;
1907}
1908
1909static int imx_uart_poll_get_char(struct uart_port *port)
1910{
1911 struct imx_port *sport = (struct imx_port *)port;
1912 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1913 return NO_POLL_CHAR;
1914
1915 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1916}
1917
1918static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1919{
1920 struct imx_port *sport = (struct imx_port *)port;
1921 unsigned int status;
1922
1923 /* drain */
1924 do {
1925 status = imx_uart_readl(sport, USR1);
1926 } while (~status & USR1_TRDY);
1927
1928 /* write */
1929 imx_uart_writel(sport, c, URTX0);
1930
1931 /* flush */
1932 do {
1933 status = imx_uart_readl(sport, USR2);
1934 } while (~status & USR2_TXDC);
1935}
1936#endif
1937
1938/* called with port.lock taken and irqs off or from .probe without locking */
1939static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1940 struct serial_rs485 *rs485conf)
1941{
1942 struct imx_port *sport = (struct imx_port *)port;
1943 u32 ucr2;
1944
1945 if (rs485conf->flags & SER_RS485_ENABLED) {
1946 /* Enable receiver if low-active RTS signal is requested */
1947 if (sport->have_rtscts && !sport->have_rtsgpio &&
1948 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1949 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1950
1951 /* disable transmitter */
1952 ucr2 = imx_uart_readl(sport, UCR2);
1953 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1954 imx_uart_rts_active(sport, &ucr2);
1955 else
1956 imx_uart_rts_inactive(sport, &ucr2);
1957 imx_uart_writel(sport, ucr2, UCR2);
1958 }
1959
1960 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1961 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1962 rs485conf->flags & SER_RS485_RX_DURING_TX)
1963 imx_uart_start_rx(port);
1964
1965 return 0;
1966}
1967
1968static const struct uart_ops imx_uart_pops = {
1969 .tx_empty = imx_uart_tx_empty,
1970 .set_mctrl = imx_uart_set_mctrl,
1971 .get_mctrl = imx_uart_get_mctrl,
1972 .stop_tx = imx_uart_stop_tx,
1973 .start_tx = imx_uart_start_tx,
1974 .stop_rx = imx_uart_stop_rx,
1975 .enable_ms = imx_uart_enable_ms,
1976 .break_ctl = imx_uart_break_ctl,
1977 .startup = imx_uart_startup,
1978 .shutdown = imx_uart_shutdown,
1979 .flush_buffer = imx_uart_flush_buffer,
1980 .set_termios = imx_uart_set_termios,
1981 .type = imx_uart_type,
1982 .config_port = imx_uart_config_port,
1983 .verify_port = imx_uart_verify_port,
1984#if defined(CONFIG_CONSOLE_POLL)
1985 .poll_init = imx_uart_poll_init,
1986 .poll_get_char = imx_uart_poll_get_char,
1987 .poll_put_char = imx_uart_poll_put_char,
1988#endif
1989};
1990
1991static struct imx_port *imx_uart_ports[UART_NR];
1992
1993#if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
1994static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1995{
1996 struct imx_port *sport = (struct imx_port *)port;
1997
1998 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1999 barrier();
2000
2001 imx_uart_writel(sport, ch, URTX0);
2002}
2003
2004/*
2005 * Interrupts are disabled on entering
2006 */
2007static void
2008imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2009{
2010 struct imx_port *sport = imx_uart_ports[co->index];
2011 struct imx_port_ucrs old_ucr;
2012 unsigned long flags;
2013 unsigned int ucr1;
2014 int locked = 1;
2015
2016 if (sport->port.sysrq)
2017 locked = 0;
2018 else if (oops_in_progress)
2019 locked = uart_port_trylock_irqsave(&sport->port, &flags);
2020 else
2021 uart_port_lock_irqsave(&sport->port, &flags);
2022
2023 /*
2024 * First, save UCR1/2/3 and then disable interrupts
2025 */
2026 imx_uart_ucrs_save(sport, &old_ucr);
2027 ucr1 = old_ucr.ucr1;
2028
2029 if (imx_uart_is_imx1(sport))
2030 ucr1 |= IMX1_UCR1_UARTCLKEN;
2031 ucr1 |= UCR1_UARTEN;
2032 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2033
2034 imx_uart_writel(sport, ucr1, UCR1);
2035
2036 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2037
2038 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2039
2040 /*
2041 * Finally, wait for transmitter to become empty
2042 * and restore UCR1/2/3
2043 */
2044 while (!(imx_uart_readl(sport, USR2) & USR2_TXDC));
2045
2046 imx_uart_ucrs_restore(sport, &old_ucr);
2047
2048 if (locked)
2049 uart_port_unlock_irqrestore(&sport->port, flags);
2050}
2051
2052/*
2053 * If the port was already initialised (eg, by a boot loader),
2054 * try to determine the current setup.
2055 */
2056static void
2057imx_uart_console_get_options(struct imx_port *sport, int *baud,
2058 int *parity, int *bits)
2059{
2060
2061 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2062 /* ok, the port was enabled */
2063 unsigned int ucr2, ubir, ubmr, uartclk;
2064 unsigned int baud_raw;
2065 unsigned int ucfr_rfdiv;
2066
2067 ucr2 = imx_uart_readl(sport, UCR2);
2068
2069 *parity = 'n';
2070 if (ucr2 & UCR2_PREN) {
2071 if (ucr2 & UCR2_PROE)
2072 *parity = 'o';
2073 else
2074 *parity = 'e';
2075 }
2076
2077 if (ucr2 & UCR2_WS)
2078 *bits = 8;
2079 else
2080 *bits = 7;
2081
2082 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2083 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2084
2085 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2086 if (ucfr_rfdiv == 6)
2087 ucfr_rfdiv = 7;
2088 else
2089 ucfr_rfdiv = 6 - ucfr_rfdiv;
2090
2091 uartclk = clk_get_rate(sport->clk_per);
2092 uartclk /= ucfr_rfdiv;
2093
2094 { /*
2095 * The next code provides exact computation of
2096 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2097 * without need of float support or long long division,
2098 * which would be required to prevent 32bit arithmetic overflow
2099 */
2100 unsigned int mul = ubir + 1;
2101 unsigned int div = 16 * (ubmr + 1);
2102 unsigned int rem = uartclk % div;
2103
2104 baud_raw = (uartclk / div) * mul;
2105 baud_raw += (rem * mul + div / 2) / div;
2106 *baud = (baud_raw + 50) / 100 * 100;
2107 }
2108
2109 if (*baud != baud_raw)
2110 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2111 baud_raw, *baud);
2112 }
2113}
2114
2115static int
2116imx_uart_console_setup(struct console *co, char *options)
2117{
2118 struct imx_port *sport;
2119 int baud = 9600;
2120 int bits = 8;
2121 int parity = 'n';
2122 int flow = 'n';
2123 int retval;
2124
2125 /*
2126 * Check whether an invalid uart number has been specified, and
2127 * if so, search for the first available port that does have
2128 * console support.
2129 */
2130 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2131 co->index = 0;
2132 sport = imx_uart_ports[co->index];
2133 if (sport == NULL)
2134 return -ENODEV;
2135
2136 /* For setting the registers, we only need to enable the ipg clock. */
2137 retval = clk_prepare_enable(sport->clk_ipg);
2138 if (retval)
2139 goto error_console;
2140
2141 if (options)
2142 uart_parse_options(options, &baud, &parity, &bits, &flow);
2143 else
2144 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2145
2146 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2147
2148 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2149
2150 if (retval) {
2151 clk_disable_unprepare(sport->clk_ipg);
2152 goto error_console;
2153 }
2154
2155 retval = clk_prepare_enable(sport->clk_per);
2156 if (retval)
2157 clk_disable_unprepare(sport->clk_ipg);
2158
2159error_console:
2160 return retval;
2161}
2162
2163static int
2164imx_uart_console_exit(struct console *co)
2165{
2166 struct imx_port *sport = imx_uart_ports[co->index];
2167
2168 clk_disable_unprepare(sport->clk_per);
2169 clk_disable_unprepare(sport->clk_ipg);
2170
2171 return 0;
2172}
2173
2174static struct uart_driver imx_uart_uart_driver;
2175static struct console imx_uart_console = {
2176 .name = DEV_NAME,
2177 .write = imx_uart_console_write,
2178 .device = uart_console_device,
2179 .setup = imx_uart_console_setup,
2180 .exit = imx_uart_console_exit,
2181 .flags = CON_PRINTBUFFER,
2182 .index = -1,
2183 .data = &imx_uart_uart_driver,
2184};
2185
2186#define IMX_CONSOLE &imx_uart_console
2187
2188#else
2189#define IMX_CONSOLE NULL
2190#endif
2191
2192static struct uart_driver imx_uart_uart_driver = {
2193 .owner = THIS_MODULE,
2194 .driver_name = DRIVER_NAME,
2195 .dev_name = DEV_NAME,
2196 .major = SERIAL_IMX_MAJOR,
2197 .minor = MINOR_START,
2198 .nr = ARRAY_SIZE(imx_uart_ports),
2199 .cons = IMX_CONSOLE,
2200};
2201
2202static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2203{
2204 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2205 unsigned long flags;
2206
2207 uart_port_lock_irqsave(&sport->port, &flags);
2208 if (sport->tx_state == WAIT_AFTER_RTS)
2209 imx_uart_start_tx(&sport->port);
2210 uart_port_unlock_irqrestore(&sport->port, flags);
2211
2212 return HRTIMER_NORESTART;
2213}
2214
2215static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2216{
2217 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2218 unsigned long flags;
2219
2220 uart_port_lock_irqsave(&sport->port, &flags);
2221 if (sport->tx_state == WAIT_AFTER_SEND)
2222 imx_uart_stop_tx(&sport->port);
2223 uart_port_unlock_irqrestore(&sport->port, flags);
2224
2225 return HRTIMER_NORESTART;
2226}
2227
2228static const struct serial_rs485 imx_rs485_supported = {
2229 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2230 SER_RS485_RX_DURING_TX,
2231 .delay_rts_before_send = 1,
2232 .delay_rts_after_send = 1,
2233};
2234
2235/* Default RX DMA buffer configuration */
2236#define RX_DMA_PERIODS 16
2237#define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2238
2239static int imx_uart_probe(struct platform_device *pdev)
2240{
2241 struct device_node *np = pdev->dev.of_node;
2242 struct imx_port *sport;
2243 void __iomem *base;
2244 u32 dma_buf_conf[2];
2245 int ret = 0;
2246 u32 ucr1, ucr2, uts;
2247 struct resource *res;
2248 int txirq, rxirq, rtsirq;
2249
2250 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2251 if (!sport)
2252 return -ENOMEM;
2253
2254 sport->devdata = of_device_get_match_data(&pdev->dev);
2255
2256 ret = of_alias_get_id(np, "serial");
2257 if (ret < 0) {
2258 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2259 return ret;
2260 }
2261 sport->port.line = ret;
2262
2263 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2264 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2265
2266 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2267
2268 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2269
2270 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2271
2272 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2273
2274 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2275 sport->rx_period_length = dma_buf_conf[0];
2276 sport->rx_periods = dma_buf_conf[1];
2277 } else {
2278 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2279 sport->rx_periods = RX_DMA_PERIODS;
2280 }
2281
2282 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2283 dev_err(&pdev->dev, "serial%d out of range\n",
2284 sport->port.line);
2285 return -EINVAL;
2286 }
2287
2288 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2289 if (IS_ERR(base))
2290 return PTR_ERR(base);
2291
2292 rxirq = platform_get_irq(pdev, 0);
2293 if (rxirq < 0)
2294 return rxirq;
2295 txirq = platform_get_irq_optional(pdev, 1);
2296 rtsirq = platform_get_irq_optional(pdev, 2);
2297
2298 sport->port.dev = &pdev->dev;
2299 sport->port.mapbase = res->start;
2300 sport->port.membase = base;
2301 sport->port.type = PORT_IMX;
2302 sport->port.iotype = UPIO_MEM;
2303 sport->port.irq = rxirq;
2304 sport->port.fifosize = 32;
2305 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2306 sport->port.ops = &imx_uart_pops;
2307 sport->port.rs485_config = imx_uart_rs485_config;
2308 /* RTS is required to control the RS485 transmitter */
2309 if (sport->have_rtscts || sport->have_rtsgpio)
2310 sport->port.rs485_supported = imx_rs485_supported;
2311 sport->port.flags = UPF_BOOT_AUTOCONF;
2312 timer_setup(&sport->timer, imx_uart_timeout, 0);
2313
2314 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2315 if (IS_ERR(sport->gpios))
2316 return PTR_ERR(sport->gpios);
2317
2318 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2319 if (IS_ERR(sport->clk_ipg)) {
2320 ret = PTR_ERR(sport->clk_ipg);
2321 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2322 return ret;
2323 }
2324
2325 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2326 if (IS_ERR(sport->clk_per)) {
2327 ret = PTR_ERR(sport->clk_per);
2328 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2329 return ret;
2330 }
2331
2332 sport->port.uartclk = clk_get_rate(sport->clk_per);
2333
2334 /* For register access, we only need to enable the ipg clock. */
2335 ret = clk_prepare_enable(sport->clk_ipg);
2336 if (ret) {
2337 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2338 return ret;
2339 }
2340
2341 ret = uart_get_rs485_mode(&sport->port);
2342 if (ret)
2343 goto err_clk;
2344
2345 /*
2346 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2347 * signal cannot be set low during transmission in case the
2348 * receiver is off (limitation of the i.MX UART IP).
2349 */
2350 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2351 sport->have_rtscts && !sport->have_rtsgpio &&
2352 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2353 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2354 dev_err(&pdev->dev,
2355 "low-active RTS not possible when receiver is off, enabling receiver\n");
2356
2357 /* Disable interrupts before requesting them */
2358 ucr1 = imx_uart_readl(sport, UCR1);
2359 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2360 imx_uart_writel(sport, ucr1, UCR1);
2361
2362 /* Disable Ageing Timer interrupt */
2363 ucr2 = imx_uart_readl(sport, UCR2);
2364 ucr2 &= ~UCR2_ATEN;
2365 imx_uart_writel(sport, ucr2, UCR2);
2366
2367 /*
2368 * In case RS485 is enabled without GPIO RTS control, the UART IP
2369 * is used to control CTS signal. Keep both the UART and Receiver
2370 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2371 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2372 * data from being fed into the RX FIFO, enable loopback mode in
2373 * UTS register, which disconnects the RX path from external RXD
2374 * pin and connects it to the Transceiver, which is disabled, so
2375 * no data can be fed to the RX FIFO that way.
2376 */
2377 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2378 sport->have_rtscts && !sport->have_rtsgpio) {
2379 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2380 uts |= UTS_LOOP;
2381 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2382
2383 ucr1 = imx_uart_readl(sport, UCR1);
2384 ucr1 |= UCR1_UARTEN;
2385 imx_uart_writel(sport, ucr1, UCR1);
2386
2387 ucr2 = imx_uart_readl(sport, UCR2);
2388 ucr2 |= UCR2_RXEN;
2389 imx_uart_writel(sport, ucr2, UCR2);
2390 }
2391
2392 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2393 /*
2394 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2395 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2396 * and DCD (when they are outputs) or enables the respective
2397 * irqs. So set this bit early, i.e. before requesting irqs.
2398 */
2399 u32 ufcr = imx_uart_readl(sport, UFCR);
2400 if (!(ufcr & UFCR_DCEDTE))
2401 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2402
2403 /*
2404 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2405 * enabled later because they cannot be cleared
2406 * (confirmed on i.MX25) which makes them unusable.
2407 */
2408 imx_uart_writel(sport,
2409 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2410 UCR3);
2411
2412 } else {
2413 u32 ucr3 = UCR3_DSR;
2414 u32 ufcr = imx_uart_readl(sport, UFCR);
2415 if (ufcr & UFCR_DCEDTE)
2416 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2417
2418 if (!imx_uart_is_imx1(sport))
2419 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2420 imx_uart_writel(sport, ucr3, UCR3);
2421 }
2422
2423 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2424 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2425 sport->trigger_start_tx.function = imx_trigger_start_tx;
2426 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2427
2428 /*
2429 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2430 * chips only have one interrupt.
2431 */
2432 if (txirq > 0) {
2433 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2434 dev_name(&pdev->dev), sport);
2435 if (ret) {
2436 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2437 ret);
2438 goto err_clk;
2439 }
2440
2441 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2442 dev_name(&pdev->dev), sport);
2443 if (ret) {
2444 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2445 ret);
2446 goto err_clk;
2447 }
2448
2449 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2450 dev_name(&pdev->dev), sport);
2451 if (ret) {
2452 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2453 ret);
2454 goto err_clk;
2455 }
2456 } else {
2457 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2458 dev_name(&pdev->dev), sport);
2459 if (ret) {
2460 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2461 goto err_clk;
2462 }
2463 }
2464
2465 imx_uart_ports[sport->port.line] = sport;
2466
2467 platform_set_drvdata(pdev, sport);
2468
2469 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2470
2471err_clk:
2472 clk_disable_unprepare(sport->clk_ipg);
2473
2474 return ret;
2475}
2476
2477static void imx_uart_remove(struct platform_device *pdev)
2478{
2479 struct imx_port *sport = platform_get_drvdata(pdev);
2480
2481 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2482}
2483
2484static void imx_uart_restore_context(struct imx_port *sport)
2485{
2486 unsigned long flags;
2487
2488 uart_port_lock_irqsave(&sport->port, &flags);
2489 if (!sport->context_saved) {
2490 uart_port_unlock_irqrestore(&sport->port, flags);
2491 return;
2492 }
2493
2494 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2495 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2496 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2497 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2498 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2499 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2500 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2501 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2502 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2503 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2504 sport->context_saved = false;
2505 uart_port_unlock_irqrestore(&sport->port, flags);
2506}
2507
2508static void imx_uart_save_context(struct imx_port *sport)
2509{
2510 unsigned long flags;
2511
2512 /* Save necessary regs */
2513 uart_port_lock_irqsave(&sport->port, &flags);
2514 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2515 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2516 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2517 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2518 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2519 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2520 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2521 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2522 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2523 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2524 sport->context_saved = true;
2525 uart_port_unlock_irqrestore(&sport->port, flags);
2526}
2527
2528static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2529{
2530 u32 ucr3;
2531
2532 ucr3 = imx_uart_readl(sport, UCR3);
2533 if (on) {
2534 imx_uart_writel(sport, USR1_AWAKE, USR1);
2535 ucr3 |= UCR3_AWAKEN;
2536 } else {
2537 ucr3 &= ~UCR3_AWAKEN;
2538 }
2539 imx_uart_writel(sport, ucr3, UCR3);
2540
2541 if (sport->have_rtscts) {
2542 u32 ucr1 = imx_uart_readl(sport, UCR1);
2543 if (on) {
2544 imx_uart_writel(sport, USR1_RTSD, USR1);
2545 ucr1 |= UCR1_RTSDEN;
2546 } else {
2547 ucr1 &= ~UCR1_RTSDEN;
2548 }
2549 imx_uart_writel(sport, ucr1, UCR1);
2550 }
2551}
2552
2553static int imx_uart_suspend_noirq(struct device *dev)
2554{
2555 struct imx_port *sport = dev_get_drvdata(dev);
2556
2557 imx_uart_save_context(sport);
2558
2559 clk_disable(sport->clk_ipg);
2560
2561 pinctrl_pm_select_sleep_state(dev);
2562
2563 return 0;
2564}
2565
2566static int imx_uart_resume_noirq(struct device *dev)
2567{
2568 struct imx_port *sport = dev_get_drvdata(dev);
2569 int ret;
2570
2571 pinctrl_pm_select_default_state(dev);
2572
2573 ret = clk_enable(sport->clk_ipg);
2574 if (ret)
2575 return ret;
2576
2577 imx_uart_restore_context(sport);
2578
2579 return 0;
2580}
2581
2582static int imx_uart_suspend(struct device *dev)
2583{
2584 struct imx_port *sport = dev_get_drvdata(dev);
2585 int ret;
2586
2587 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2588 disable_irq(sport->port.irq);
2589
2590 ret = clk_prepare_enable(sport->clk_ipg);
2591 if (ret)
2592 return ret;
2593
2594 /* enable wakeup from i.MX UART */
2595 imx_uart_enable_wakeup(sport, true);
2596
2597 return 0;
2598}
2599
2600static int imx_uart_resume(struct device *dev)
2601{
2602 struct imx_port *sport = dev_get_drvdata(dev);
2603
2604 /* disable wakeup from i.MX UART */
2605 imx_uart_enable_wakeup(sport, false);
2606
2607 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2608 enable_irq(sport->port.irq);
2609
2610 clk_disable_unprepare(sport->clk_ipg);
2611
2612 return 0;
2613}
2614
2615static int imx_uart_freeze(struct device *dev)
2616{
2617 struct imx_port *sport = dev_get_drvdata(dev);
2618
2619 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2620
2621 return clk_prepare_enable(sport->clk_ipg);
2622}
2623
2624static int imx_uart_thaw(struct device *dev)
2625{
2626 struct imx_port *sport = dev_get_drvdata(dev);
2627
2628 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2629
2630 clk_disable_unprepare(sport->clk_ipg);
2631
2632 return 0;
2633}
2634
2635static const struct dev_pm_ops imx_uart_pm_ops = {
2636 .suspend_noirq = imx_uart_suspend_noirq,
2637 .resume_noirq = imx_uart_resume_noirq,
2638 .freeze_noirq = imx_uart_suspend_noirq,
2639 .thaw_noirq = imx_uart_resume_noirq,
2640 .restore_noirq = imx_uart_resume_noirq,
2641 .suspend = imx_uart_suspend,
2642 .resume = imx_uart_resume,
2643 .freeze = imx_uart_freeze,
2644 .thaw = imx_uart_thaw,
2645 .restore = imx_uart_thaw,
2646};
2647
2648static struct platform_driver imx_uart_platform_driver = {
2649 .probe = imx_uart_probe,
2650 .remove_new = imx_uart_remove,
2651
2652 .driver = {
2653 .name = "imx-uart",
2654 .of_match_table = imx_uart_dt_ids,
2655 .pm = &imx_uart_pm_ops,
2656 },
2657};
2658
2659static int __init imx_uart_init(void)
2660{
2661 int ret = uart_register_driver(&imx_uart_uart_driver);
2662
2663 if (ret)
2664 return ret;
2665
2666 ret = platform_driver_register(&imx_uart_platform_driver);
2667 if (ret != 0)
2668 uart_unregister_driver(&imx_uart_uart_driver);
2669
2670 return ret;
2671}
2672
2673static void __exit imx_uart_exit(void)
2674{
2675 platform_driver_unregister(&imx_uart_platform_driver);
2676 uart_unregister_driver(&imx_uart_uart_driver);
2677}
2678
2679module_init(imx_uart_init);
2680module_exit(imx_uart_exit);
2681
2682MODULE_AUTHOR("Sascha Hauer");
2683MODULE_DESCRIPTION("IMX generic serial port driver");
2684MODULE_LICENSE("GPL");
2685MODULE_ALIAS("platform:imx-uart");
1/*
2 * Driver for Motorola/Freescale IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21#define SUPPORT_SYSRQ
22#endif
23
24#include <linux/module.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/platform_device.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/clk.h>
35#include <linux/delay.h>
36#include <linux/rational.h>
37#include <linux/slab.h>
38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/io.h>
41#include <linux/dma-mapping.h>
42
43#include <asm/irq.h>
44#include <linux/platform_data/serial-imx.h>
45#include <linux/platform_data/dma-imx.h>
46
47#include "serial_mctrl_gpio.h"
48
49/* Register definitions */
50#define URXD0 0x0 /* Receiver Register */
51#define URTX0 0x40 /* Transmitter Register */
52#define UCR1 0x80 /* Control Register 1 */
53#define UCR2 0x84 /* Control Register 2 */
54#define UCR3 0x88 /* Control Register 3 */
55#define UCR4 0x8c /* Control Register 4 */
56#define UFCR 0x90 /* FIFO Control Register */
57#define USR1 0x94 /* Status Register 1 */
58#define USR2 0x98 /* Status Register 2 */
59#define UESC 0x9c /* Escape Character Register */
60#define UTIM 0xa0 /* Escape Timer Register */
61#define UBIR 0xa4 /* BRM Incremental Register */
62#define UBMR 0xa8 /* BRM Modulator Register */
63#define UBRC 0xac /* Baud Rate Count Register */
64#define IMX21_ONEMS 0xb0 /* One Millisecond register */
65#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
66#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
67
68/* UART Control Register Bit Fields.*/
69#define URXD_DUMMY_READ (1<<16)
70#define URXD_CHARRDY (1<<15)
71#define URXD_ERR (1<<14)
72#define URXD_OVRRUN (1<<13)
73#define URXD_FRMERR (1<<12)
74#define URXD_BRK (1<<11)
75#define URXD_PRERR (1<<10)
76#define URXD_RX_DATA (0xFF<<0)
77#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
78#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
79#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
80#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
81#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
83#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
84#define UCR1_IREN (1<<7) /* Infrared interface enable */
85#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
86#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
87#define UCR1_SNDBRK (1<<4) /* Send break */
88#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
89#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
90#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
91#define UCR1_DOZE (1<<1) /* Doze */
92#define UCR1_UARTEN (1<<0) /* UART enabled */
93#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
94#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
95#define UCR2_CTSC (1<<13) /* CTS pin control */
96#define UCR2_CTS (1<<12) /* Clear to send */
97#define UCR2_ESCEN (1<<11) /* Escape enable */
98#define UCR2_PREN (1<<8) /* Parity enable */
99#define UCR2_PROE (1<<7) /* Parity odd/even */
100#define UCR2_STPB (1<<6) /* Stop */
101#define UCR2_WS (1<<5) /* Word size */
102#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
103#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
104#define UCR2_TXEN (1<<2) /* Transmitter enabled */
105#define UCR2_RXEN (1<<1) /* Receiver enabled */
106#define UCR2_SRST (1<<0) /* SW reset */
107#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
108#define UCR3_PARERREN (1<<12) /* Parity enable */
109#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
110#define UCR3_DSR (1<<10) /* Data set ready */
111#define UCR3_DCD (1<<9) /* Data carrier detect */
112#define UCR3_RI (1<<8) /* Ring indicator */
113#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
114#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
115#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
116#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
117#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
118#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
119#define UCR3_BPEN (1<<0) /* Preset registers enable */
120#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
121#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
122#define UCR4_INVR (1<<9) /* Inverted infrared reception */
123#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
124#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
125#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
126#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
127#define UCR4_IRSC (1<<5) /* IR special case */
128#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
129#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
130#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
131#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
132#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
133#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
134#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
135#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
136#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
137#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
138#define USR1_RTSS (1<<14) /* RTS pin status */
139#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
140#define USR1_RTSD (1<<12) /* RTS delta */
141#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
142#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
143#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
144#define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
145#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
146#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
147#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
148#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
149#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
150#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
151#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
152#define USR2_IDLE (1<<12) /* Idle condition */
153#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
154#define USR2_RIIN (1<<9) /* Ring Indicator Input */
155#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
156#define USR2_WAKE (1<<7) /* Wake */
157#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
158#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
159#define USR2_TXDC (1<<3) /* Transmitter complete */
160#define USR2_BRCD (1<<2) /* Break condition */
161#define USR2_ORE (1<<1) /* Overrun error */
162#define USR2_RDR (1<<0) /* Recv data ready */
163#define UTS_FRCPERR (1<<13) /* Force parity error */
164#define UTS_LOOP (1<<12) /* Loop tx and rx */
165#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
166#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
167#define UTS_TXFULL (1<<4) /* TxFIFO full */
168#define UTS_RXFULL (1<<3) /* RxFIFO full */
169#define UTS_SOFTRST (1<<0) /* Software reset */
170
171/* We've been assigned a range on the "Low-density serial ports" major */
172#define SERIAL_IMX_MAJOR 207
173#define MINOR_START 16
174#define DEV_NAME "ttymxc"
175
176/*
177 * This determines how often we check the modem status signals
178 * for any change. They generally aren't connected to an IRQ
179 * so we have to poll them. We also check immediately before
180 * filling the TX fifo incase CTS has been dropped.
181 */
182#define MCTRL_TIMEOUT (250*HZ/1000)
183
184#define DRIVER_NAME "IMX-uart"
185
186#define UART_NR 8
187
188/* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
189enum imx_uart_type {
190 IMX1_UART,
191 IMX21_UART,
192 IMX6Q_UART,
193};
194
195/* device type dependent stuff */
196struct imx_uart_data {
197 unsigned uts_reg;
198 enum imx_uart_type devtype;
199};
200
201struct imx_port {
202 struct uart_port port;
203 struct timer_list timer;
204 unsigned int old_status;
205 unsigned int have_rtscts:1;
206 unsigned int dte_mode:1;
207 unsigned int irda_inv_rx:1;
208 unsigned int irda_inv_tx:1;
209 unsigned short trcv_delay; /* transceiver delay */
210 struct clk *clk_ipg;
211 struct clk *clk_per;
212 const struct imx_uart_data *devdata;
213
214 struct mctrl_gpios *gpios;
215
216 /* DMA fields */
217 unsigned int dma_is_inited:1;
218 unsigned int dma_is_enabled:1;
219 unsigned int dma_is_rxing:1;
220 unsigned int dma_is_txing:1;
221 struct dma_chan *dma_chan_rx, *dma_chan_tx;
222 struct scatterlist rx_sgl, tx_sgl[2];
223 void *rx_buf;
224 unsigned int tx_bytes;
225 unsigned int dma_tx_nents;
226 wait_queue_head_t dma_wait;
227 unsigned int saved_reg[10];
228 bool context_saved;
229};
230
231struct imx_port_ucrs {
232 unsigned int ucr1;
233 unsigned int ucr2;
234 unsigned int ucr3;
235};
236
237static struct imx_uart_data imx_uart_devdata[] = {
238 [IMX1_UART] = {
239 .uts_reg = IMX1_UTS,
240 .devtype = IMX1_UART,
241 },
242 [IMX21_UART] = {
243 .uts_reg = IMX21_UTS,
244 .devtype = IMX21_UART,
245 },
246 [IMX6Q_UART] = {
247 .uts_reg = IMX21_UTS,
248 .devtype = IMX6Q_UART,
249 },
250};
251
252static const struct platform_device_id imx_uart_devtype[] = {
253 {
254 .name = "imx1-uart",
255 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
256 }, {
257 .name = "imx21-uart",
258 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
259 }, {
260 .name = "imx6q-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
262 }, {
263 /* sentinel */
264 }
265};
266MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
267
268static const struct of_device_id imx_uart_dt_ids[] = {
269 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
270 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
271 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
272 { /* sentinel */ }
273};
274MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
275
276static inline unsigned uts_reg(struct imx_port *sport)
277{
278 return sport->devdata->uts_reg;
279}
280
281static inline int is_imx1_uart(struct imx_port *sport)
282{
283 return sport->devdata->devtype == IMX1_UART;
284}
285
286static inline int is_imx21_uart(struct imx_port *sport)
287{
288 return sport->devdata->devtype == IMX21_UART;
289}
290
291static inline int is_imx6q_uart(struct imx_port *sport)
292{
293 return sport->devdata->devtype == IMX6Q_UART;
294}
295/*
296 * Save and restore functions for UCR1, UCR2 and UCR3 registers
297 */
298#if defined(CONFIG_SERIAL_IMX_CONSOLE)
299static void imx_port_ucrs_save(struct uart_port *port,
300 struct imx_port_ucrs *ucr)
301{
302 /* save control registers */
303 ucr->ucr1 = readl(port->membase + UCR1);
304 ucr->ucr2 = readl(port->membase + UCR2);
305 ucr->ucr3 = readl(port->membase + UCR3);
306}
307
308static void imx_port_ucrs_restore(struct uart_port *port,
309 struct imx_port_ucrs *ucr)
310{
311 /* restore control registers */
312 writel(ucr->ucr1, port->membase + UCR1);
313 writel(ucr->ucr2, port->membase + UCR2);
314 writel(ucr->ucr3, port->membase + UCR3);
315}
316#endif
317
318static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
319{
320 *ucr2 &= ~UCR2_CTSC;
321 *ucr2 |= UCR2_CTS;
322
323 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
324}
325
326static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
327{
328 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
329
330 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
331}
332
333static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
334{
335 *ucr2 |= UCR2_CTSC;
336}
337
338/*
339 * interrupts disabled on entry
340 */
341static void imx_stop_tx(struct uart_port *port)
342{
343 struct imx_port *sport = (struct imx_port *)port;
344 unsigned long temp;
345
346 /*
347 * We are maybe in the SMP context, so if the DMA TX thread is running
348 * on other cpu, we have to wait for it to finish.
349 */
350 if (sport->dma_is_enabled && sport->dma_is_txing)
351 return;
352
353 temp = readl(port->membase + UCR1);
354 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
355
356 /* in rs485 mode disable transmitter if shifter is empty */
357 if (port->rs485.flags & SER_RS485_ENABLED &&
358 readl(port->membase + USR2) & USR2_TXDC) {
359 temp = readl(port->membase + UCR2);
360 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
361 imx_port_rts_inactive(sport, &temp);
362 else
363 imx_port_rts_active(sport, &temp);
364 writel(temp, port->membase + UCR2);
365
366 temp = readl(port->membase + UCR4);
367 temp &= ~UCR4_TCEN;
368 writel(temp, port->membase + UCR4);
369 }
370}
371
372/*
373 * interrupts disabled on entry
374 */
375static void imx_stop_rx(struct uart_port *port)
376{
377 struct imx_port *sport = (struct imx_port *)port;
378 unsigned long temp;
379
380 if (sport->dma_is_enabled && sport->dma_is_rxing) {
381 if (sport->port.suspended) {
382 dmaengine_terminate_all(sport->dma_chan_rx);
383 sport->dma_is_rxing = 0;
384 } else {
385 return;
386 }
387 }
388
389 temp = readl(sport->port.membase + UCR2);
390 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
391
392 /* disable the `Receiver Ready Interrrupt` */
393 temp = readl(sport->port.membase + UCR1);
394 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
395}
396
397/*
398 * Set the modem control timer to fire immediately.
399 */
400static void imx_enable_ms(struct uart_port *port)
401{
402 struct imx_port *sport = (struct imx_port *)port;
403
404 mod_timer(&sport->timer, jiffies);
405
406 mctrl_gpio_enable_ms(sport->gpios);
407}
408
409static void imx_dma_tx(struct imx_port *sport);
410static inline void imx_transmit_buffer(struct imx_port *sport)
411{
412 struct circ_buf *xmit = &sport->port.state->xmit;
413 unsigned long temp;
414
415 if (sport->port.x_char) {
416 /* Send next char */
417 writel(sport->port.x_char, sport->port.membase + URTX0);
418 sport->port.icount.tx++;
419 sport->port.x_char = 0;
420 return;
421 }
422
423 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
424 imx_stop_tx(&sport->port);
425 return;
426 }
427
428 if (sport->dma_is_enabled) {
429 /*
430 * We've just sent a X-char Ensure the TX DMA is enabled
431 * and the TX IRQ is disabled.
432 **/
433 temp = readl(sport->port.membase + UCR1);
434 temp &= ~UCR1_TXMPTYEN;
435 if (sport->dma_is_txing) {
436 temp |= UCR1_TDMAEN;
437 writel(temp, sport->port.membase + UCR1);
438 } else {
439 writel(temp, sport->port.membase + UCR1);
440 imx_dma_tx(sport);
441 }
442 }
443
444 while (!uart_circ_empty(xmit) &&
445 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
446 /* send xmit->buf[xmit->tail]
447 * out the port here */
448 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
449 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
450 sport->port.icount.tx++;
451 }
452
453 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
454 uart_write_wakeup(&sport->port);
455
456 if (uart_circ_empty(xmit))
457 imx_stop_tx(&sport->port);
458}
459
460static void dma_tx_callback(void *data)
461{
462 struct imx_port *sport = data;
463 struct scatterlist *sgl = &sport->tx_sgl[0];
464 struct circ_buf *xmit = &sport->port.state->xmit;
465 unsigned long flags;
466 unsigned long temp;
467
468 spin_lock_irqsave(&sport->port.lock, flags);
469
470 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
471
472 temp = readl(sport->port.membase + UCR1);
473 temp &= ~UCR1_TDMAEN;
474 writel(temp, sport->port.membase + UCR1);
475
476 /* update the stat */
477 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
478 sport->port.icount.tx += sport->tx_bytes;
479
480 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
481
482 sport->dma_is_txing = 0;
483
484 spin_unlock_irqrestore(&sport->port.lock, flags);
485
486 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
487 uart_write_wakeup(&sport->port);
488
489 if (waitqueue_active(&sport->dma_wait)) {
490 wake_up(&sport->dma_wait);
491 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
492 return;
493 }
494
495 spin_lock_irqsave(&sport->port.lock, flags);
496 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
497 imx_dma_tx(sport);
498 spin_unlock_irqrestore(&sport->port.lock, flags);
499}
500
501static void imx_dma_tx(struct imx_port *sport)
502{
503 struct circ_buf *xmit = &sport->port.state->xmit;
504 struct scatterlist *sgl = sport->tx_sgl;
505 struct dma_async_tx_descriptor *desc;
506 struct dma_chan *chan = sport->dma_chan_tx;
507 struct device *dev = sport->port.dev;
508 unsigned long temp;
509 int ret;
510
511 if (sport->dma_is_txing)
512 return;
513
514 sport->tx_bytes = uart_circ_chars_pending(xmit);
515
516 if (xmit->tail < xmit->head) {
517 sport->dma_tx_nents = 1;
518 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
519 } else {
520 sport->dma_tx_nents = 2;
521 sg_init_table(sgl, 2);
522 sg_set_buf(sgl, xmit->buf + xmit->tail,
523 UART_XMIT_SIZE - xmit->tail);
524 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
525 }
526
527 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
528 if (ret == 0) {
529 dev_err(dev, "DMA mapping error for TX.\n");
530 return;
531 }
532 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
533 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
534 if (!desc) {
535 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
536 DMA_TO_DEVICE);
537 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
538 return;
539 }
540 desc->callback = dma_tx_callback;
541 desc->callback_param = sport;
542
543 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
544 uart_circ_chars_pending(xmit));
545
546 temp = readl(sport->port.membase + UCR1);
547 temp |= UCR1_TDMAEN;
548 writel(temp, sport->port.membase + UCR1);
549
550 /* fire it */
551 sport->dma_is_txing = 1;
552 dmaengine_submit(desc);
553 dma_async_issue_pending(chan);
554 return;
555}
556
557/*
558 * interrupts disabled on entry
559 */
560static void imx_start_tx(struct uart_port *port)
561{
562 struct imx_port *sport = (struct imx_port *)port;
563 unsigned long temp;
564
565 if (port->rs485.flags & SER_RS485_ENABLED) {
566 temp = readl(port->membase + UCR2);
567 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
568 imx_port_rts_inactive(sport, &temp);
569 else
570 imx_port_rts_active(sport, &temp);
571 writel(temp, port->membase + UCR2);
572
573 /* enable transmitter and shifter empty irq */
574 temp = readl(port->membase + UCR4);
575 temp |= UCR4_TCEN;
576 writel(temp, port->membase + UCR4);
577 }
578
579 if (!sport->dma_is_enabled) {
580 temp = readl(sport->port.membase + UCR1);
581 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
582 }
583
584 if (sport->dma_is_enabled) {
585 if (sport->port.x_char) {
586 /* We have X-char to send, so enable TX IRQ and
587 * disable TX DMA to let TX interrupt to send X-char */
588 temp = readl(sport->port.membase + UCR1);
589 temp &= ~UCR1_TDMAEN;
590 temp |= UCR1_TXMPTYEN;
591 writel(temp, sport->port.membase + UCR1);
592 return;
593 }
594
595 if (!uart_circ_empty(&port->state->xmit) &&
596 !uart_tx_stopped(port))
597 imx_dma_tx(sport);
598 return;
599 }
600}
601
602static irqreturn_t imx_rtsint(int irq, void *dev_id)
603{
604 struct imx_port *sport = dev_id;
605 unsigned int val;
606 unsigned long flags;
607
608 spin_lock_irqsave(&sport->port.lock, flags);
609
610 writel(USR1_RTSD, sport->port.membase + USR1);
611 val = readl(sport->port.membase + USR1) & USR1_RTSS;
612 uart_handle_cts_change(&sport->port, !!val);
613 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
614
615 spin_unlock_irqrestore(&sport->port.lock, flags);
616 return IRQ_HANDLED;
617}
618
619static irqreturn_t imx_txint(int irq, void *dev_id)
620{
621 struct imx_port *sport = dev_id;
622 unsigned long flags;
623
624 spin_lock_irqsave(&sport->port.lock, flags);
625 imx_transmit_buffer(sport);
626 spin_unlock_irqrestore(&sport->port.lock, flags);
627 return IRQ_HANDLED;
628}
629
630static irqreturn_t imx_rxint(int irq, void *dev_id)
631{
632 struct imx_port *sport = dev_id;
633 unsigned int rx, flg, ignored = 0;
634 struct tty_port *port = &sport->port.state->port;
635 unsigned long flags, temp;
636
637 spin_lock_irqsave(&sport->port.lock, flags);
638
639 while (readl(sport->port.membase + USR2) & USR2_RDR) {
640 flg = TTY_NORMAL;
641 sport->port.icount.rx++;
642
643 rx = readl(sport->port.membase + URXD0);
644
645 temp = readl(sport->port.membase + USR2);
646 if (temp & USR2_BRCD) {
647 writel(USR2_BRCD, sport->port.membase + USR2);
648 if (uart_handle_break(&sport->port))
649 continue;
650 }
651
652 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
653 continue;
654
655 if (unlikely(rx & URXD_ERR)) {
656 if (rx & URXD_BRK)
657 sport->port.icount.brk++;
658 else if (rx & URXD_PRERR)
659 sport->port.icount.parity++;
660 else if (rx & URXD_FRMERR)
661 sport->port.icount.frame++;
662 if (rx & URXD_OVRRUN)
663 sport->port.icount.overrun++;
664
665 if (rx & sport->port.ignore_status_mask) {
666 if (++ignored > 100)
667 goto out;
668 continue;
669 }
670
671 rx &= (sport->port.read_status_mask | 0xFF);
672
673 if (rx & URXD_BRK)
674 flg = TTY_BREAK;
675 else if (rx & URXD_PRERR)
676 flg = TTY_PARITY;
677 else if (rx & URXD_FRMERR)
678 flg = TTY_FRAME;
679 if (rx & URXD_OVRRUN)
680 flg = TTY_OVERRUN;
681
682#ifdef SUPPORT_SYSRQ
683 sport->port.sysrq = 0;
684#endif
685 }
686
687 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
688 goto out;
689
690 if (tty_insert_flip_char(port, rx, flg) == 0)
691 sport->port.icount.buf_overrun++;
692 }
693
694out:
695 spin_unlock_irqrestore(&sport->port.lock, flags);
696 tty_flip_buffer_push(port);
697 return IRQ_HANDLED;
698}
699
700static int start_rx_dma(struct imx_port *sport);
701/*
702 * If the RXFIFO is filled with some data, and then we
703 * arise a DMA operation to receive them.
704 */
705static void imx_dma_rxint(struct imx_port *sport)
706{
707 unsigned long temp;
708 unsigned long flags;
709
710 spin_lock_irqsave(&sport->port.lock, flags);
711
712 temp = readl(sport->port.membase + USR2);
713 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
714 sport->dma_is_rxing = 1;
715
716 /* disable the receiver ready and aging timer interrupts */
717 temp = readl(sport->port.membase + UCR1);
718 temp &= ~(UCR1_RRDYEN);
719 writel(temp, sport->port.membase + UCR1);
720
721 temp = readl(sport->port.membase + UCR2);
722 temp &= ~(UCR2_ATEN);
723 writel(temp, sport->port.membase + UCR2);
724
725 /* tell the DMA to receive the data. */
726 start_rx_dma(sport);
727 }
728
729 spin_unlock_irqrestore(&sport->port.lock, flags);
730}
731
732static irqreturn_t imx_int(int irq, void *dev_id)
733{
734 struct imx_port *sport = dev_id;
735 unsigned int sts;
736 unsigned int sts2;
737
738 sts = readl(sport->port.membase + USR1);
739 sts2 = readl(sport->port.membase + USR2);
740
741 if (sts & (USR1_RRDY | USR1_AGTIM)) {
742 if (sport->dma_is_enabled)
743 imx_dma_rxint(sport);
744 else
745 imx_rxint(irq, dev_id);
746 }
747
748 if ((sts & USR1_TRDY &&
749 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
750 (sts2 & USR2_TXDC &&
751 readl(sport->port.membase + UCR4) & UCR4_TCEN))
752 imx_txint(irq, dev_id);
753
754 if (sts & USR1_RTSD)
755 imx_rtsint(irq, dev_id);
756
757 if (sts & USR1_AWAKE)
758 writel(USR1_AWAKE, sport->port.membase + USR1);
759
760 if (sts2 & USR2_ORE) {
761 sport->port.icount.overrun++;
762 writel(USR2_ORE, sport->port.membase + USR2);
763 }
764
765 return IRQ_HANDLED;
766}
767
768/*
769 * Return TIOCSER_TEMT when transmitter is not busy.
770 */
771static unsigned int imx_tx_empty(struct uart_port *port)
772{
773 struct imx_port *sport = (struct imx_port *)port;
774 unsigned int ret;
775
776 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
777
778 /* If the TX DMA is working, return 0. */
779 if (sport->dma_is_enabled && sport->dma_is_txing)
780 ret = 0;
781
782 return ret;
783}
784
785/*
786 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
787 */
788static unsigned int imx_get_hwmctrl(struct imx_port *sport)
789{
790 unsigned int tmp = TIOCM_DSR;
791 unsigned usr1 = readl(sport->port.membase + USR1);
792
793 if (usr1 & USR1_RTSS)
794 tmp |= TIOCM_CTS;
795
796 /* in DCE mode DCDIN is always 0 */
797 if (!(usr1 & USR2_DCDIN))
798 tmp |= TIOCM_CAR;
799
800 /* in DCE mode RIIN is always 0 */
801 if (readl(sport->port.membase + USR2) & USR2_RIIN)
802 tmp |= TIOCM_RI;
803
804 return tmp;
805}
806
807static unsigned int imx_get_mctrl(struct uart_port *port)
808{
809 struct imx_port *sport = (struct imx_port *)port;
810 unsigned int ret = imx_get_hwmctrl(sport);
811
812 mctrl_gpio_get(sport->gpios, &ret);
813
814 return ret;
815}
816
817static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
818{
819 struct imx_port *sport = (struct imx_port *)port;
820 unsigned long temp;
821
822 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
823 temp = readl(sport->port.membase + UCR2);
824 temp &= ~(UCR2_CTS | UCR2_CTSC);
825 if (mctrl & TIOCM_RTS)
826 temp |= UCR2_CTS | UCR2_CTSC;
827 writel(temp, sport->port.membase + UCR2);
828 }
829
830 temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
831 if (!(mctrl & TIOCM_DTR))
832 temp |= UCR3_DSR;
833 writel(temp, sport->port.membase + UCR3);
834
835 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
836 if (mctrl & TIOCM_LOOP)
837 temp |= UTS_LOOP;
838 writel(temp, sport->port.membase + uts_reg(sport));
839
840 mctrl_gpio_set(sport->gpios, mctrl);
841}
842
843/*
844 * Interrupts always disabled.
845 */
846static void imx_break_ctl(struct uart_port *port, int break_state)
847{
848 struct imx_port *sport = (struct imx_port *)port;
849 unsigned long flags, temp;
850
851 spin_lock_irqsave(&sport->port.lock, flags);
852
853 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
854
855 if (break_state != 0)
856 temp |= UCR1_SNDBRK;
857
858 writel(temp, sport->port.membase + UCR1);
859
860 spin_unlock_irqrestore(&sport->port.lock, flags);
861}
862
863/*
864 * Handle any change of modem status signal since we were last called.
865 */
866static void imx_mctrl_check(struct imx_port *sport)
867{
868 unsigned int status, changed;
869
870 status = imx_get_hwmctrl(sport);
871 changed = status ^ sport->old_status;
872
873 if (changed == 0)
874 return;
875
876 sport->old_status = status;
877
878 if (changed & TIOCM_RI)
879 sport->port.icount.rng++;
880 if (changed & TIOCM_DSR)
881 sport->port.icount.dsr++;
882 if (changed & TIOCM_CAR)
883 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
884 if (changed & TIOCM_CTS)
885 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
886
887 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
888}
889
890/*
891 * This is our per-port timeout handler, for checking the
892 * modem status signals.
893 */
894static void imx_timeout(unsigned long data)
895{
896 struct imx_port *sport = (struct imx_port *)data;
897 unsigned long flags;
898
899 if (sport->port.state) {
900 spin_lock_irqsave(&sport->port.lock, flags);
901 imx_mctrl_check(sport);
902 spin_unlock_irqrestore(&sport->port.lock, flags);
903
904 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
905 }
906}
907
908#define RX_BUF_SIZE (PAGE_SIZE)
909static void imx_rx_dma_done(struct imx_port *sport)
910{
911 unsigned long temp;
912 unsigned long flags;
913
914 spin_lock_irqsave(&sport->port.lock, flags);
915
916 /* re-enable interrupts to get notified when new symbols are incoming */
917 temp = readl(sport->port.membase + UCR1);
918 temp |= UCR1_RRDYEN;
919 writel(temp, sport->port.membase + UCR1);
920
921 temp = readl(sport->port.membase + UCR2);
922 temp |= UCR2_ATEN;
923 writel(temp, sport->port.membase + UCR2);
924
925 sport->dma_is_rxing = 0;
926
927 /* Is the shutdown waiting for us? */
928 if (waitqueue_active(&sport->dma_wait))
929 wake_up(&sport->dma_wait);
930
931 spin_unlock_irqrestore(&sport->port.lock, flags);
932}
933
934/*
935 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
936 * [1] the RX DMA buffer is full.
937 * [2] the aging timer expires
938 *
939 * Condition [2] is triggered when a character has been sitting in the FIFO
940 * for at least 8 byte durations.
941 */
942static void dma_rx_callback(void *data)
943{
944 struct imx_port *sport = data;
945 struct dma_chan *chan = sport->dma_chan_rx;
946 struct scatterlist *sgl = &sport->rx_sgl;
947 struct tty_port *port = &sport->port.state->port;
948 struct dma_tx_state state;
949 enum dma_status status;
950 unsigned int count;
951
952 /* unmap it first */
953 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
954
955 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
956 count = RX_BUF_SIZE - state.residue;
957
958 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
959
960 if (count) {
961 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
962 int bytes = tty_insert_flip_string(port, sport->rx_buf,
963 count);
964
965 if (bytes != count)
966 sport->port.icount.buf_overrun++;
967 }
968 tty_flip_buffer_push(port);
969 sport->port.icount.rx += count;
970 }
971
972 /*
973 * Restart RX DMA directly if more data is available in order to skip
974 * the roundtrip through the IRQ handler. If there is some data already
975 * in the FIFO, DMA needs to be restarted soon anyways.
976 *
977 * Otherwise stop the DMA and reactivate FIFO IRQs to restart DMA once
978 * data starts to arrive again.
979 */
980 if (readl(sport->port.membase + USR2) & USR2_RDR)
981 start_rx_dma(sport);
982 else
983 imx_rx_dma_done(sport);
984}
985
986static int start_rx_dma(struct imx_port *sport)
987{
988 struct scatterlist *sgl = &sport->rx_sgl;
989 struct dma_chan *chan = sport->dma_chan_rx;
990 struct device *dev = sport->port.dev;
991 struct dma_async_tx_descriptor *desc;
992 int ret;
993
994 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
995 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
996 if (ret == 0) {
997 dev_err(dev, "DMA mapping error for RX.\n");
998 return -EINVAL;
999 }
1000 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
1001 DMA_PREP_INTERRUPT);
1002 if (!desc) {
1003 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1004 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1005 return -EINVAL;
1006 }
1007 desc->callback = dma_rx_callback;
1008 desc->callback_param = sport;
1009
1010 dev_dbg(dev, "RX: prepare for the DMA.\n");
1011 dmaengine_submit(desc);
1012 dma_async_issue_pending(chan);
1013 return 0;
1014}
1015
1016#define TXTL_DEFAULT 2 /* reset default */
1017#define RXTL_DEFAULT 1 /* reset default */
1018#define TXTL_DMA 8 /* DMA burst setting */
1019#define RXTL_DMA 9 /* DMA burst setting */
1020
1021static void imx_setup_ufcr(struct imx_port *sport,
1022 unsigned char txwl, unsigned char rxwl)
1023{
1024 unsigned int val;
1025
1026 /* set receiver / transmitter trigger level */
1027 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1028 val |= txwl << UFCR_TXTL_SHF | rxwl;
1029 writel(val, sport->port.membase + UFCR);
1030}
1031
1032static void imx_uart_dma_exit(struct imx_port *sport)
1033{
1034 if (sport->dma_chan_rx) {
1035 dma_release_channel(sport->dma_chan_rx);
1036 sport->dma_chan_rx = NULL;
1037
1038 kfree(sport->rx_buf);
1039 sport->rx_buf = NULL;
1040 }
1041
1042 if (sport->dma_chan_tx) {
1043 dma_release_channel(sport->dma_chan_tx);
1044 sport->dma_chan_tx = NULL;
1045 }
1046
1047 sport->dma_is_inited = 0;
1048}
1049
1050static int imx_uart_dma_init(struct imx_port *sport)
1051{
1052 struct dma_slave_config slave_config = {};
1053 struct device *dev = sport->port.dev;
1054 int ret;
1055
1056 /* Prepare for RX : */
1057 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1058 if (!sport->dma_chan_rx) {
1059 dev_dbg(dev, "cannot get the DMA channel.\n");
1060 ret = -EINVAL;
1061 goto err;
1062 }
1063
1064 slave_config.direction = DMA_DEV_TO_MEM;
1065 slave_config.src_addr = sport->port.mapbase + URXD0;
1066 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1067 /* one byte less than the watermark level to enable the aging timer */
1068 slave_config.src_maxburst = RXTL_DMA - 1;
1069 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1070 if (ret) {
1071 dev_err(dev, "error in RX dma configuration.\n");
1072 goto err;
1073 }
1074
1075 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1076 if (!sport->rx_buf) {
1077 ret = -ENOMEM;
1078 goto err;
1079 }
1080
1081 /* Prepare for TX : */
1082 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1083 if (!sport->dma_chan_tx) {
1084 dev_err(dev, "cannot get the TX DMA channel!\n");
1085 ret = -EINVAL;
1086 goto err;
1087 }
1088
1089 slave_config.direction = DMA_MEM_TO_DEV;
1090 slave_config.dst_addr = sport->port.mapbase + URTX0;
1091 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1092 slave_config.dst_maxburst = TXTL_DMA;
1093 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1094 if (ret) {
1095 dev_err(dev, "error in TX dma configuration.");
1096 goto err;
1097 }
1098
1099 sport->dma_is_inited = 1;
1100
1101 return 0;
1102err:
1103 imx_uart_dma_exit(sport);
1104 return ret;
1105}
1106
1107static void imx_enable_dma(struct imx_port *sport)
1108{
1109 unsigned long temp;
1110
1111 init_waitqueue_head(&sport->dma_wait);
1112
1113 /* set UCR1 */
1114 temp = readl(sport->port.membase + UCR1);
1115 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1116 writel(temp, sport->port.membase + UCR1);
1117
1118 temp = readl(sport->port.membase + UCR2);
1119 temp |= UCR2_ATEN;
1120 writel(temp, sport->port.membase + UCR2);
1121
1122 imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1123
1124 sport->dma_is_enabled = 1;
1125}
1126
1127static void imx_disable_dma(struct imx_port *sport)
1128{
1129 unsigned long temp;
1130
1131 /* clear UCR1 */
1132 temp = readl(sport->port.membase + UCR1);
1133 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1134 writel(temp, sport->port.membase + UCR1);
1135
1136 /* clear UCR2 */
1137 temp = readl(sport->port.membase + UCR2);
1138 temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1139 writel(temp, sport->port.membase + UCR2);
1140
1141 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1142
1143 sport->dma_is_enabled = 0;
1144}
1145
1146/* half the RX buffer size */
1147#define CTSTL 16
1148
1149static int imx_startup(struct uart_port *port)
1150{
1151 struct imx_port *sport = (struct imx_port *)port;
1152 int retval, i;
1153 unsigned long flags, temp;
1154
1155 retval = clk_prepare_enable(sport->clk_per);
1156 if (retval)
1157 return retval;
1158 retval = clk_prepare_enable(sport->clk_ipg);
1159 if (retval) {
1160 clk_disable_unprepare(sport->clk_per);
1161 return retval;
1162 }
1163
1164 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1165
1166 /* disable the DREN bit (Data Ready interrupt enable) before
1167 * requesting IRQs
1168 */
1169 temp = readl(sport->port.membase + UCR4);
1170
1171 /* set the trigger level for CTS */
1172 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1173 temp |= CTSTL << UCR4_CTSTL_SHF;
1174
1175 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1176
1177 /* Can we enable the DMA support? */
1178 if (is_imx6q_uart(sport) && !uart_console(port) &&
1179 !sport->dma_is_inited)
1180 imx_uart_dma_init(sport);
1181
1182 spin_lock_irqsave(&sport->port.lock, flags);
1183 /* Reset fifo's and state machines */
1184 i = 100;
1185
1186 temp = readl(sport->port.membase + UCR2);
1187 temp &= ~UCR2_SRST;
1188 writel(temp, sport->port.membase + UCR2);
1189
1190 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1191 udelay(1);
1192
1193 /*
1194 * Finally, clear and enable interrupts
1195 */
1196 writel(USR1_RTSD, sport->port.membase + USR1);
1197 writel(USR2_ORE, sport->port.membase + USR2);
1198
1199 if (sport->dma_is_inited && !sport->dma_is_enabled)
1200 imx_enable_dma(sport);
1201
1202 temp = readl(sport->port.membase + UCR1);
1203 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1204
1205 writel(temp, sport->port.membase + UCR1);
1206
1207 temp = readl(sport->port.membase + UCR4);
1208 temp |= UCR4_OREN;
1209 writel(temp, sport->port.membase + UCR4);
1210
1211 temp = readl(sport->port.membase + UCR2);
1212 temp |= (UCR2_RXEN | UCR2_TXEN);
1213 if (!sport->have_rtscts)
1214 temp |= UCR2_IRTS;
1215 writel(temp, sport->port.membase + UCR2);
1216
1217 if (!is_imx1_uart(sport)) {
1218 temp = readl(sport->port.membase + UCR3);
1219 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1220 writel(temp, sport->port.membase + UCR3);
1221 }
1222
1223 /*
1224 * Enable modem status interrupts
1225 */
1226 imx_enable_ms(&sport->port);
1227 spin_unlock_irqrestore(&sport->port.lock, flags);
1228
1229 return 0;
1230}
1231
1232static void imx_shutdown(struct uart_port *port)
1233{
1234 struct imx_port *sport = (struct imx_port *)port;
1235 unsigned long temp;
1236 unsigned long flags;
1237
1238 if (sport->dma_is_enabled) {
1239 int ret;
1240
1241 /* We have to wait for the DMA to finish. */
1242 ret = wait_event_interruptible(sport->dma_wait,
1243 !sport->dma_is_rxing && !sport->dma_is_txing);
1244 if (ret != 0) {
1245 sport->dma_is_rxing = 0;
1246 sport->dma_is_txing = 0;
1247 dmaengine_terminate_all(sport->dma_chan_tx);
1248 dmaengine_terminate_all(sport->dma_chan_rx);
1249 }
1250 spin_lock_irqsave(&sport->port.lock, flags);
1251 imx_stop_tx(port);
1252 imx_stop_rx(port);
1253 imx_disable_dma(sport);
1254 spin_unlock_irqrestore(&sport->port.lock, flags);
1255 imx_uart_dma_exit(sport);
1256 }
1257
1258 mctrl_gpio_disable_ms(sport->gpios);
1259
1260 spin_lock_irqsave(&sport->port.lock, flags);
1261 temp = readl(sport->port.membase + UCR2);
1262 temp &= ~(UCR2_TXEN);
1263 writel(temp, sport->port.membase + UCR2);
1264 spin_unlock_irqrestore(&sport->port.lock, flags);
1265
1266 /*
1267 * Stop our timer.
1268 */
1269 del_timer_sync(&sport->timer);
1270
1271 /*
1272 * Disable all interrupts, port and break condition.
1273 */
1274
1275 spin_lock_irqsave(&sport->port.lock, flags);
1276 temp = readl(sport->port.membase + UCR1);
1277 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1278
1279 writel(temp, sport->port.membase + UCR1);
1280 spin_unlock_irqrestore(&sport->port.lock, flags);
1281
1282 clk_disable_unprepare(sport->clk_per);
1283 clk_disable_unprepare(sport->clk_ipg);
1284}
1285
1286static void imx_flush_buffer(struct uart_port *port)
1287{
1288 struct imx_port *sport = (struct imx_port *)port;
1289 struct scatterlist *sgl = &sport->tx_sgl[0];
1290 unsigned long temp;
1291 int i = 100, ubir, ubmr, uts;
1292
1293 if (!sport->dma_chan_tx)
1294 return;
1295
1296 sport->tx_bytes = 0;
1297 dmaengine_terminate_all(sport->dma_chan_tx);
1298 if (sport->dma_is_txing) {
1299 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1300 DMA_TO_DEVICE);
1301 temp = readl(sport->port.membase + UCR1);
1302 temp &= ~UCR1_TDMAEN;
1303 writel(temp, sport->port.membase + UCR1);
1304 sport->dma_is_txing = false;
1305 }
1306
1307 /*
1308 * According to the Reference Manual description of the UART SRST bit:
1309 * "Reset the transmit and receive state machines,
1310 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1311 * and UTS[6-3]". As we don't need to restore the old values from
1312 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1313 */
1314 ubir = readl(sport->port.membase + UBIR);
1315 ubmr = readl(sport->port.membase + UBMR);
1316 uts = readl(sport->port.membase + IMX21_UTS);
1317
1318 temp = readl(sport->port.membase + UCR2);
1319 temp &= ~UCR2_SRST;
1320 writel(temp, sport->port.membase + UCR2);
1321
1322 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1323 udelay(1);
1324
1325 /* Restore the registers */
1326 writel(ubir, sport->port.membase + UBIR);
1327 writel(ubmr, sport->port.membase + UBMR);
1328 writel(uts, sport->port.membase + IMX21_UTS);
1329}
1330
1331static void
1332imx_set_termios(struct uart_port *port, struct ktermios *termios,
1333 struct ktermios *old)
1334{
1335 struct imx_port *sport = (struct imx_port *)port;
1336 unsigned long flags;
1337 unsigned long ucr2, old_ucr1, old_ucr2;
1338 unsigned int baud, quot;
1339 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1340 unsigned long div, ufcr;
1341 unsigned long num, denom;
1342 uint64_t tdiv64;
1343
1344 /*
1345 * We only support CS7 and CS8.
1346 */
1347 while ((termios->c_cflag & CSIZE) != CS7 &&
1348 (termios->c_cflag & CSIZE) != CS8) {
1349 termios->c_cflag &= ~CSIZE;
1350 termios->c_cflag |= old_csize;
1351 old_csize = CS8;
1352 }
1353
1354 if ((termios->c_cflag & CSIZE) == CS8)
1355 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1356 else
1357 ucr2 = UCR2_SRST | UCR2_IRTS;
1358
1359 if (termios->c_cflag & CRTSCTS) {
1360 if (sport->have_rtscts) {
1361 ucr2 &= ~UCR2_IRTS;
1362
1363 if (port->rs485.flags & SER_RS485_ENABLED) {
1364 /*
1365 * RTS is mandatory for rs485 operation, so keep
1366 * it under manual control and keep transmitter
1367 * disabled.
1368 */
1369 if (port->rs485.flags &
1370 SER_RS485_RTS_AFTER_SEND)
1371 imx_port_rts_inactive(sport, &ucr2);
1372 else
1373 imx_port_rts_active(sport, &ucr2);
1374 } else {
1375 imx_port_rts_auto(sport, &ucr2);
1376 }
1377 } else {
1378 termios->c_cflag &= ~CRTSCTS;
1379 }
1380 } else if (port->rs485.flags & SER_RS485_ENABLED) {
1381 /* disable transmitter */
1382 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1383 imx_port_rts_inactive(sport, &ucr2);
1384 else
1385 imx_port_rts_active(sport, &ucr2);
1386 }
1387
1388
1389 if (termios->c_cflag & CSTOPB)
1390 ucr2 |= UCR2_STPB;
1391 if (termios->c_cflag & PARENB) {
1392 ucr2 |= UCR2_PREN;
1393 if (termios->c_cflag & PARODD)
1394 ucr2 |= UCR2_PROE;
1395 }
1396
1397 del_timer_sync(&sport->timer);
1398
1399 /*
1400 * Ask the core to calculate the divisor for us.
1401 */
1402 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1403 quot = uart_get_divisor(port, baud);
1404
1405 spin_lock_irqsave(&sport->port.lock, flags);
1406
1407 sport->port.read_status_mask = 0;
1408 if (termios->c_iflag & INPCK)
1409 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1410 if (termios->c_iflag & (BRKINT | PARMRK))
1411 sport->port.read_status_mask |= URXD_BRK;
1412
1413 /*
1414 * Characters to ignore
1415 */
1416 sport->port.ignore_status_mask = 0;
1417 if (termios->c_iflag & IGNPAR)
1418 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1419 if (termios->c_iflag & IGNBRK) {
1420 sport->port.ignore_status_mask |= URXD_BRK;
1421 /*
1422 * If we're ignoring parity and break indicators,
1423 * ignore overruns too (for real raw support).
1424 */
1425 if (termios->c_iflag & IGNPAR)
1426 sport->port.ignore_status_mask |= URXD_OVRRUN;
1427 }
1428
1429 if ((termios->c_cflag & CREAD) == 0)
1430 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1431
1432 /*
1433 * Update the per-port timeout.
1434 */
1435 uart_update_timeout(port, termios->c_cflag, baud);
1436
1437 /*
1438 * disable interrupts and drain transmitter
1439 */
1440 old_ucr1 = readl(sport->port.membase + UCR1);
1441 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1442 sport->port.membase + UCR1);
1443
1444 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1445 barrier();
1446
1447 /* then, disable everything */
1448 old_ucr2 = readl(sport->port.membase + UCR2);
1449 writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1450 sport->port.membase + UCR2);
1451 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1452
1453 /* custom-baudrate handling */
1454 div = sport->port.uartclk / (baud * 16);
1455 if (baud == 38400 && quot != div)
1456 baud = sport->port.uartclk / (quot * 16);
1457
1458 div = sport->port.uartclk / (baud * 16);
1459 if (div > 7)
1460 div = 7;
1461 if (!div)
1462 div = 1;
1463
1464 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1465 1 << 16, 1 << 16, &num, &denom);
1466
1467 tdiv64 = sport->port.uartclk;
1468 tdiv64 *= num;
1469 do_div(tdiv64, denom * 16 * div);
1470 tty_termios_encode_baud_rate(termios,
1471 (speed_t)tdiv64, (speed_t)tdiv64);
1472
1473 num -= 1;
1474 denom -= 1;
1475
1476 ufcr = readl(sport->port.membase + UFCR);
1477 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1478 if (sport->dte_mode)
1479 ufcr |= UFCR_DCEDTE;
1480 writel(ufcr, sport->port.membase + UFCR);
1481
1482 writel(num, sport->port.membase + UBIR);
1483 writel(denom, sport->port.membase + UBMR);
1484
1485 if (!is_imx1_uart(sport))
1486 writel(sport->port.uartclk / div / 1000,
1487 sport->port.membase + IMX21_ONEMS);
1488
1489 writel(old_ucr1, sport->port.membase + UCR1);
1490
1491 /* set the parity, stop bits and data size */
1492 writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1493
1494 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1495 imx_enable_ms(&sport->port);
1496
1497 spin_unlock_irqrestore(&sport->port.lock, flags);
1498}
1499
1500static const char *imx_type(struct uart_port *port)
1501{
1502 struct imx_port *sport = (struct imx_port *)port;
1503
1504 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1505}
1506
1507/*
1508 * Configure/autoconfigure the port.
1509 */
1510static void imx_config_port(struct uart_port *port, int flags)
1511{
1512 struct imx_port *sport = (struct imx_port *)port;
1513
1514 if (flags & UART_CONFIG_TYPE)
1515 sport->port.type = PORT_IMX;
1516}
1517
1518/*
1519 * Verify the new serial_struct (for TIOCSSERIAL).
1520 * The only change we allow are to the flags and type, and
1521 * even then only between PORT_IMX and PORT_UNKNOWN
1522 */
1523static int
1524imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1525{
1526 struct imx_port *sport = (struct imx_port *)port;
1527 int ret = 0;
1528
1529 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1530 ret = -EINVAL;
1531 if (sport->port.irq != ser->irq)
1532 ret = -EINVAL;
1533 if (ser->io_type != UPIO_MEM)
1534 ret = -EINVAL;
1535 if (sport->port.uartclk / 16 != ser->baud_base)
1536 ret = -EINVAL;
1537 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1538 ret = -EINVAL;
1539 if (sport->port.iobase != ser->port)
1540 ret = -EINVAL;
1541 if (ser->hub6 != 0)
1542 ret = -EINVAL;
1543 return ret;
1544}
1545
1546#if defined(CONFIG_CONSOLE_POLL)
1547
1548static int imx_poll_init(struct uart_port *port)
1549{
1550 struct imx_port *sport = (struct imx_port *)port;
1551 unsigned long flags;
1552 unsigned long temp;
1553 int retval;
1554
1555 retval = clk_prepare_enable(sport->clk_ipg);
1556 if (retval)
1557 return retval;
1558 retval = clk_prepare_enable(sport->clk_per);
1559 if (retval)
1560 clk_disable_unprepare(sport->clk_ipg);
1561
1562 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1563
1564 spin_lock_irqsave(&sport->port.lock, flags);
1565
1566 temp = readl(sport->port.membase + UCR1);
1567 if (is_imx1_uart(sport))
1568 temp |= IMX1_UCR1_UARTCLKEN;
1569 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1570 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1571 writel(temp, sport->port.membase + UCR1);
1572
1573 temp = readl(sport->port.membase + UCR2);
1574 temp |= UCR2_RXEN;
1575 writel(temp, sport->port.membase + UCR2);
1576
1577 spin_unlock_irqrestore(&sport->port.lock, flags);
1578
1579 return 0;
1580}
1581
1582static int imx_poll_get_char(struct uart_port *port)
1583{
1584 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1585 return NO_POLL_CHAR;
1586
1587 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1588}
1589
1590static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1591{
1592 unsigned int status;
1593
1594 /* drain */
1595 do {
1596 status = readl_relaxed(port->membase + USR1);
1597 } while (~status & USR1_TRDY);
1598
1599 /* write */
1600 writel_relaxed(c, port->membase + URTX0);
1601
1602 /* flush */
1603 do {
1604 status = readl_relaxed(port->membase + USR2);
1605 } while (~status & USR2_TXDC);
1606}
1607#endif
1608
1609static int imx_rs485_config(struct uart_port *port,
1610 struct serial_rs485 *rs485conf)
1611{
1612 struct imx_port *sport = (struct imx_port *)port;
1613
1614 /* unimplemented */
1615 rs485conf->delay_rts_before_send = 0;
1616 rs485conf->delay_rts_after_send = 0;
1617 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1618
1619 /* RTS is required to control the transmitter */
1620 if (!sport->have_rtscts)
1621 rs485conf->flags &= ~SER_RS485_ENABLED;
1622
1623 if (rs485conf->flags & SER_RS485_ENABLED) {
1624 unsigned long temp;
1625
1626 /* disable transmitter */
1627 temp = readl(sport->port.membase + UCR2);
1628 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1629 imx_port_rts_inactive(sport, &temp);
1630 else
1631 imx_port_rts_active(sport, &temp);
1632 writel(temp, sport->port.membase + UCR2);
1633 }
1634
1635 port->rs485 = *rs485conf;
1636
1637 return 0;
1638}
1639
1640static struct uart_ops imx_pops = {
1641 .tx_empty = imx_tx_empty,
1642 .set_mctrl = imx_set_mctrl,
1643 .get_mctrl = imx_get_mctrl,
1644 .stop_tx = imx_stop_tx,
1645 .start_tx = imx_start_tx,
1646 .stop_rx = imx_stop_rx,
1647 .enable_ms = imx_enable_ms,
1648 .break_ctl = imx_break_ctl,
1649 .startup = imx_startup,
1650 .shutdown = imx_shutdown,
1651 .flush_buffer = imx_flush_buffer,
1652 .set_termios = imx_set_termios,
1653 .type = imx_type,
1654 .config_port = imx_config_port,
1655 .verify_port = imx_verify_port,
1656#if defined(CONFIG_CONSOLE_POLL)
1657 .poll_init = imx_poll_init,
1658 .poll_get_char = imx_poll_get_char,
1659 .poll_put_char = imx_poll_put_char,
1660#endif
1661};
1662
1663static struct imx_port *imx_ports[UART_NR];
1664
1665#ifdef CONFIG_SERIAL_IMX_CONSOLE
1666static void imx_console_putchar(struct uart_port *port, int ch)
1667{
1668 struct imx_port *sport = (struct imx_port *)port;
1669
1670 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1671 barrier();
1672
1673 writel(ch, sport->port.membase + URTX0);
1674}
1675
1676/*
1677 * Interrupts are disabled on entering
1678 */
1679static void
1680imx_console_write(struct console *co, const char *s, unsigned int count)
1681{
1682 struct imx_port *sport = imx_ports[co->index];
1683 struct imx_port_ucrs old_ucr;
1684 unsigned int ucr1;
1685 unsigned long flags = 0;
1686 int locked = 1;
1687 int retval;
1688
1689 retval = clk_enable(sport->clk_per);
1690 if (retval)
1691 return;
1692 retval = clk_enable(sport->clk_ipg);
1693 if (retval) {
1694 clk_disable(sport->clk_per);
1695 return;
1696 }
1697
1698 if (sport->port.sysrq)
1699 locked = 0;
1700 else if (oops_in_progress)
1701 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1702 else
1703 spin_lock_irqsave(&sport->port.lock, flags);
1704
1705 /*
1706 * First, save UCR1/2/3 and then disable interrupts
1707 */
1708 imx_port_ucrs_save(&sport->port, &old_ucr);
1709 ucr1 = old_ucr.ucr1;
1710
1711 if (is_imx1_uart(sport))
1712 ucr1 |= IMX1_UCR1_UARTCLKEN;
1713 ucr1 |= UCR1_UARTEN;
1714 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1715
1716 writel(ucr1, sport->port.membase + UCR1);
1717
1718 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1719
1720 uart_console_write(&sport->port, s, count, imx_console_putchar);
1721
1722 /*
1723 * Finally, wait for transmitter to become empty
1724 * and restore UCR1/2/3
1725 */
1726 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1727
1728 imx_port_ucrs_restore(&sport->port, &old_ucr);
1729
1730 if (locked)
1731 spin_unlock_irqrestore(&sport->port.lock, flags);
1732
1733 clk_disable(sport->clk_ipg);
1734 clk_disable(sport->clk_per);
1735}
1736
1737/*
1738 * If the port was already initialised (eg, by a boot loader),
1739 * try to determine the current setup.
1740 */
1741static void __init
1742imx_console_get_options(struct imx_port *sport, int *baud,
1743 int *parity, int *bits)
1744{
1745
1746 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1747 /* ok, the port was enabled */
1748 unsigned int ucr2, ubir, ubmr, uartclk;
1749 unsigned int baud_raw;
1750 unsigned int ucfr_rfdiv;
1751
1752 ucr2 = readl(sport->port.membase + UCR2);
1753
1754 *parity = 'n';
1755 if (ucr2 & UCR2_PREN) {
1756 if (ucr2 & UCR2_PROE)
1757 *parity = 'o';
1758 else
1759 *parity = 'e';
1760 }
1761
1762 if (ucr2 & UCR2_WS)
1763 *bits = 8;
1764 else
1765 *bits = 7;
1766
1767 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1768 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1769
1770 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1771 if (ucfr_rfdiv == 6)
1772 ucfr_rfdiv = 7;
1773 else
1774 ucfr_rfdiv = 6 - ucfr_rfdiv;
1775
1776 uartclk = clk_get_rate(sport->clk_per);
1777 uartclk /= ucfr_rfdiv;
1778
1779 { /*
1780 * The next code provides exact computation of
1781 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1782 * without need of float support or long long division,
1783 * which would be required to prevent 32bit arithmetic overflow
1784 */
1785 unsigned int mul = ubir + 1;
1786 unsigned int div = 16 * (ubmr + 1);
1787 unsigned int rem = uartclk % div;
1788
1789 baud_raw = (uartclk / div) * mul;
1790 baud_raw += (rem * mul + div / 2) / div;
1791 *baud = (baud_raw + 50) / 100 * 100;
1792 }
1793
1794 if (*baud != baud_raw)
1795 pr_info("Console IMX rounded baud rate from %d to %d\n",
1796 baud_raw, *baud);
1797 }
1798}
1799
1800static int __init
1801imx_console_setup(struct console *co, char *options)
1802{
1803 struct imx_port *sport;
1804 int baud = 9600;
1805 int bits = 8;
1806 int parity = 'n';
1807 int flow = 'n';
1808 int retval;
1809
1810 /*
1811 * Check whether an invalid uart number has been specified, and
1812 * if so, search for the first available port that does have
1813 * console support.
1814 */
1815 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1816 co->index = 0;
1817 sport = imx_ports[co->index];
1818 if (sport == NULL)
1819 return -ENODEV;
1820
1821 /* For setting the registers, we only need to enable the ipg clock. */
1822 retval = clk_prepare_enable(sport->clk_ipg);
1823 if (retval)
1824 goto error_console;
1825
1826 if (options)
1827 uart_parse_options(options, &baud, &parity, &bits, &flow);
1828 else
1829 imx_console_get_options(sport, &baud, &parity, &bits);
1830
1831 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1832
1833 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1834
1835 clk_disable(sport->clk_ipg);
1836 if (retval) {
1837 clk_unprepare(sport->clk_ipg);
1838 goto error_console;
1839 }
1840
1841 retval = clk_prepare(sport->clk_per);
1842 if (retval)
1843 clk_disable_unprepare(sport->clk_ipg);
1844
1845error_console:
1846 return retval;
1847}
1848
1849static struct uart_driver imx_reg;
1850static struct console imx_console = {
1851 .name = DEV_NAME,
1852 .write = imx_console_write,
1853 .device = uart_console_device,
1854 .setup = imx_console_setup,
1855 .flags = CON_PRINTBUFFER,
1856 .index = -1,
1857 .data = &imx_reg,
1858};
1859
1860#define IMX_CONSOLE &imx_console
1861
1862#ifdef CONFIG_OF
1863static void imx_console_early_putchar(struct uart_port *port, int ch)
1864{
1865 while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1866 cpu_relax();
1867
1868 writel_relaxed(ch, port->membase + URTX0);
1869}
1870
1871static void imx_console_early_write(struct console *con, const char *s,
1872 unsigned count)
1873{
1874 struct earlycon_device *dev = con->data;
1875
1876 uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1877}
1878
1879static int __init
1880imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1881{
1882 if (!dev->port.membase)
1883 return -ENODEV;
1884
1885 dev->con->write = imx_console_early_write;
1886
1887 return 0;
1888}
1889OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1890OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1891#endif
1892
1893#else
1894#define IMX_CONSOLE NULL
1895#endif
1896
1897static struct uart_driver imx_reg = {
1898 .owner = THIS_MODULE,
1899 .driver_name = DRIVER_NAME,
1900 .dev_name = DEV_NAME,
1901 .major = SERIAL_IMX_MAJOR,
1902 .minor = MINOR_START,
1903 .nr = ARRAY_SIZE(imx_ports),
1904 .cons = IMX_CONSOLE,
1905};
1906
1907#ifdef CONFIG_OF
1908/*
1909 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1910 * could successfully get all information from dt or a negative errno.
1911 */
1912static int serial_imx_probe_dt(struct imx_port *sport,
1913 struct platform_device *pdev)
1914{
1915 struct device_node *np = pdev->dev.of_node;
1916 int ret;
1917
1918 sport->devdata = of_device_get_match_data(&pdev->dev);
1919 if (!sport->devdata)
1920 /* no device tree device */
1921 return 1;
1922
1923 ret = of_alias_get_id(np, "serial");
1924 if (ret < 0) {
1925 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1926 return ret;
1927 }
1928 sport->port.line = ret;
1929
1930 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1931 sport->have_rtscts = 1;
1932
1933 if (of_get_property(np, "fsl,dte-mode", NULL))
1934 sport->dte_mode = 1;
1935
1936 return 0;
1937}
1938#else
1939static inline int serial_imx_probe_dt(struct imx_port *sport,
1940 struct platform_device *pdev)
1941{
1942 return 1;
1943}
1944#endif
1945
1946static void serial_imx_probe_pdata(struct imx_port *sport,
1947 struct platform_device *pdev)
1948{
1949 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1950
1951 sport->port.line = pdev->id;
1952 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1953
1954 if (!pdata)
1955 return;
1956
1957 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1958 sport->have_rtscts = 1;
1959}
1960
1961static int serial_imx_probe(struct platform_device *pdev)
1962{
1963 struct imx_port *sport;
1964 void __iomem *base;
1965 int ret = 0, reg;
1966 struct resource *res;
1967 int txirq, rxirq, rtsirq;
1968
1969 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1970 if (!sport)
1971 return -ENOMEM;
1972
1973 ret = serial_imx_probe_dt(sport, pdev);
1974 if (ret > 0)
1975 serial_imx_probe_pdata(sport, pdev);
1976 else if (ret < 0)
1977 return ret;
1978
1979 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1980 base = devm_ioremap_resource(&pdev->dev, res);
1981 if (IS_ERR(base))
1982 return PTR_ERR(base);
1983
1984 rxirq = platform_get_irq(pdev, 0);
1985 txirq = platform_get_irq(pdev, 1);
1986 rtsirq = platform_get_irq(pdev, 2);
1987
1988 sport->port.dev = &pdev->dev;
1989 sport->port.mapbase = res->start;
1990 sport->port.membase = base;
1991 sport->port.type = PORT_IMX,
1992 sport->port.iotype = UPIO_MEM;
1993 sport->port.irq = rxirq;
1994 sport->port.fifosize = 32;
1995 sport->port.ops = &imx_pops;
1996 sport->port.rs485_config = imx_rs485_config;
1997 sport->port.rs485.flags =
1998 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
1999 sport->port.flags = UPF_BOOT_AUTOCONF;
2000 init_timer(&sport->timer);
2001 sport->timer.function = imx_timeout;
2002 sport->timer.data = (unsigned long)sport;
2003
2004 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2005 if (IS_ERR(sport->gpios))
2006 return PTR_ERR(sport->gpios);
2007
2008 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2009 if (IS_ERR(sport->clk_ipg)) {
2010 ret = PTR_ERR(sport->clk_ipg);
2011 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2012 return ret;
2013 }
2014
2015 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2016 if (IS_ERR(sport->clk_per)) {
2017 ret = PTR_ERR(sport->clk_per);
2018 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2019 return ret;
2020 }
2021
2022 sport->port.uartclk = clk_get_rate(sport->clk_per);
2023
2024 /* For register access, we only need to enable the ipg clock. */
2025 ret = clk_prepare_enable(sport->clk_ipg);
2026 if (ret)
2027 return ret;
2028
2029 /* Disable interrupts before requesting them */
2030 reg = readl_relaxed(sport->port.membase + UCR1);
2031 reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2032 UCR1_TXMPTYEN | UCR1_RTSDEN);
2033 writel_relaxed(reg, sport->port.membase + UCR1);
2034
2035 clk_disable_unprepare(sport->clk_ipg);
2036
2037 /*
2038 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2039 * chips only have one interrupt.
2040 */
2041 if (txirq > 0) {
2042 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2043 dev_name(&pdev->dev), sport);
2044 if (ret)
2045 return ret;
2046
2047 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2048 dev_name(&pdev->dev), sport);
2049 if (ret)
2050 return ret;
2051 } else {
2052 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2053 dev_name(&pdev->dev), sport);
2054 if (ret)
2055 return ret;
2056 }
2057
2058 imx_ports[sport->port.line] = sport;
2059
2060 platform_set_drvdata(pdev, sport);
2061
2062 return uart_add_one_port(&imx_reg, &sport->port);
2063}
2064
2065static int serial_imx_remove(struct platform_device *pdev)
2066{
2067 struct imx_port *sport = platform_get_drvdata(pdev);
2068
2069 return uart_remove_one_port(&imx_reg, &sport->port);
2070}
2071
2072static void serial_imx_restore_context(struct imx_port *sport)
2073{
2074 if (!sport->context_saved)
2075 return;
2076
2077 writel(sport->saved_reg[4], sport->port.membase + UFCR);
2078 writel(sport->saved_reg[5], sport->port.membase + UESC);
2079 writel(sport->saved_reg[6], sport->port.membase + UTIM);
2080 writel(sport->saved_reg[7], sport->port.membase + UBIR);
2081 writel(sport->saved_reg[8], sport->port.membase + UBMR);
2082 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2083 writel(sport->saved_reg[0], sport->port.membase + UCR1);
2084 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2085 writel(sport->saved_reg[2], sport->port.membase + UCR3);
2086 writel(sport->saved_reg[3], sport->port.membase + UCR4);
2087 sport->context_saved = false;
2088}
2089
2090static void serial_imx_save_context(struct imx_port *sport)
2091{
2092 /* Save necessary regs */
2093 sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2094 sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2095 sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2096 sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2097 sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2098 sport->saved_reg[5] = readl(sport->port.membase + UESC);
2099 sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2100 sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2101 sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2102 sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2103 sport->context_saved = true;
2104}
2105
2106static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2107{
2108 unsigned int val;
2109
2110 val = readl(sport->port.membase + UCR3);
2111 if (on)
2112 val |= UCR3_AWAKEN;
2113 else
2114 val &= ~UCR3_AWAKEN;
2115 writel(val, sport->port.membase + UCR3);
2116
2117 val = readl(sport->port.membase + UCR1);
2118 if (on)
2119 val |= UCR1_RTSDEN;
2120 else
2121 val &= ~UCR1_RTSDEN;
2122 writel(val, sport->port.membase + UCR1);
2123}
2124
2125static int imx_serial_port_suspend_noirq(struct device *dev)
2126{
2127 struct platform_device *pdev = to_platform_device(dev);
2128 struct imx_port *sport = platform_get_drvdata(pdev);
2129 int ret;
2130
2131 ret = clk_enable(sport->clk_ipg);
2132 if (ret)
2133 return ret;
2134
2135 serial_imx_save_context(sport);
2136
2137 clk_disable(sport->clk_ipg);
2138
2139 return 0;
2140}
2141
2142static int imx_serial_port_resume_noirq(struct device *dev)
2143{
2144 struct platform_device *pdev = to_platform_device(dev);
2145 struct imx_port *sport = platform_get_drvdata(pdev);
2146 int ret;
2147
2148 ret = clk_enable(sport->clk_ipg);
2149 if (ret)
2150 return ret;
2151
2152 serial_imx_restore_context(sport);
2153
2154 clk_disable(sport->clk_ipg);
2155
2156 return 0;
2157}
2158
2159static int imx_serial_port_suspend(struct device *dev)
2160{
2161 struct platform_device *pdev = to_platform_device(dev);
2162 struct imx_port *sport = platform_get_drvdata(pdev);
2163
2164 /* enable wakeup from i.MX UART */
2165 serial_imx_enable_wakeup(sport, true);
2166
2167 uart_suspend_port(&imx_reg, &sport->port);
2168
2169 /* Needed to enable clock in suspend_noirq */
2170 return clk_prepare(sport->clk_ipg);
2171}
2172
2173static int imx_serial_port_resume(struct device *dev)
2174{
2175 struct platform_device *pdev = to_platform_device(dev);
2176 struct imx_port *sport = platform_get_drvdata(pdev);
2177
2178 /* disable wakeup from i.MX UART */
2179 serial_imx_enable_wakeup(sport, false);
2180
2181 uart_resume_port(&imx_reg, &sport->port);
2182
2183 clk_unprepare(sport->clk_ipg);
2184
2185 return 0;
2186}
2187
2188static const struct dev_pm_ops imx_serial_port_pm_ops = {
2189 .suspend_noirq = imx_serial_port_suspend_noirq,
2190 .resume_noirq = imx_serial_port_resume_noirq,
2191 .suspend = imx_serial_port_suspend,
2192 .resume = imx_serial_port_resume,
2193};
2194
2195static struct platform_driver serial_imx_driver = {
2196 .probe = serial_imx_probe,
2197 .remove = serial_imx_remove,
2198
2199 .id_table = imx_uart_devtype,
2200 .driver = {
2201 .name = "imx-uart",
2202 .of_match_table = imx_uart_dt_ids,
2203 .pm = &imx_serial_port_pm_ops,
2204 },
2205};
2206
2207static int __init imx_serial_init(void)
2208{
2209 int ret = uart_register_driver(&imx_reg);
2210
2211 if (ret)
2212 return ret;
2213
2214 ret = platform_driver_register(&serial_imx_driver);
2215 if (ret != 0)
2216 uart_unregister_driver(&imx_reg);
2217
2218 return ret;
2219}
2220
2221static void __exit imx_serial_exit(void)
2222{
2223 platform_driver_unregister(&serial_imx_driver);
2224 uart_unregister_driver(&imx_reg);
2225}
2226
2227module_init(imx_serial_init);
2228module_exit(imx_serial_exit);
2229
2230MODULE_AUTHOR("Sascha Hauer");
2231MODULE_DESCRIPTION("IMX generic serial port driver");
2232MODULE_LICENSE("GPL");
2233MODULE_ALIAS("platform:imx-uart");