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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4/* 82562G 10/100 Network Connection
5 * 82562G-2 10/100 Network Connection
6 * 82562GT 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
8 * 82562V 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
11 * 82566DC Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
13 * 82566DM Gigabit Network Connection
14 * 82566MC Gigabit Network Connection
15 * 82566MM Gigabit Network Connection
16 * 82567LM Gigabit Network Connection
17 * 82567LF Gigabit Network Connection
18 * 82567V Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
25 * 82577LM Gigabit Network Connection
26 * 82577LC Gigabit Network Connection
27 * 82578DM Gigabit Network Connection
28 * 82578DC Gigabit Network Connection
29 * 82579LM Gigabit Network Connection
30 * 82579V Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
39 */
40
41#include "e1000.h"
42
43/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44/* Offset 04h HSFSTS */
45union ich8_hws_flash_status {
46 struct ich8_hsfsts {
47 u16 flcdone:1; /* bit 0 Flash Cycle Done */
48 u16 flcerr:1; /* bit 1 Flash Cycle Error */
49 u16 dael:1; /* bit 2 Direct Access error Log */
50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52 u16 reserved1:2; /* bit 13:6 Reserved */
53 u16 reserved2:6; /* bit 13:6 Reserved */
54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
56 } hsf_status;
57 u16 regval;
58};
59
60/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61/* Offset 06h FLCTL */
62union ich8_hws_flash_ctrl {
63 struct ich8_hsflctl {
64 u16 flcgo:1; /* 0 Flash Cycle Go */
65 u16 flcycle:2; /* 2:1 Flash Cycle */
66 u16 reserved:5; /* 7:3 Reserved */
67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68 u16 flockdn:6; /* 15:10 Reserved */
69 } hsf_ctrl;
70 u16 regval;
71};
72
73/* ICH Flash Region Access Permissions */
74union ich8_hws_flash_regacc {
75 struct ich8_flracc {
76 u32 grra:8; /* 0:7 GbE region Read Access */
77 u32 grwa:8; /* 8:15 GbE region Write Access */
78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
80 } hsf_flregacc;
81 u16 regval;
82};
83
84/* ICH Flash Protected Region */
85union ich8_flash_protected_range {
86 struct ich8_pr {
87 u32 base:13; /* 0:12 Protected Range Base */
88 u32 reserved1:2; /* 13:14 Reserved */
89 u32 rpe:1; /* 15 Read Protection Enable */
90 u32 limit:13; /* 16:28 Protected Range Limit */
91 u32 reserved2:2; /* 29:30 Reserved */
92 u32 wpe:1; /* 31 Write Protection Enable */
93 } range;
94 u32 regval;
95};
96
97static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101 u32 offset, u8 byte);
102static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103 u8 *data);
104static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105 u16 *data);
106static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107 u8 size, u16 *data);
108static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109 u32 *data);
110static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111 u32 offset, u32 *data);
112static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113 u32 offset, u32 data);
114static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115 u32 offset, u32 dword);
116static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
140
141static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142{
143 return readw(hw->flash_address + reg);
144}
145
146static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147{
148 return readl(hw->flash_address + reg);
149}
150
151static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152{
153 writew(val, hw->flash_address + reg);
154}
155
156static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157{
158 writel(val, hw->flash_address + reg);
159}
160
161#define er16flash(reg) __er16flash(hw, (reg))
162#define er32flash(reg) __er32flash(hw, (reg))
163#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
165
166/**
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
169 *
170 * Test access to the PHY registers by reading the PHY ID registers. If
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
172 * otherwise assume the read PHY ID is correct if it is valid.
173 *
174 * Assumes the sw/fw/hw semaphore is already acquired.
175 **/
176static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
177{
178 u16 phy_reg = 0;
179 u32 phy_id = 0;
180 s32 ret_val = 0;
181 u16 retry_count;
182 u32 mac_reg = 0;
183
184 for (retry_count = 0; retry_count < 2; retry_count++) {
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 if (ret_val || (phy_reg == 0xFFFF))
187 continue;
188 phy_id = (u32)(phy_reg << 16);
189
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 if (ret_val || (phy_reg == 0xFFFF)) {
192 phy_id = 0;
193 continue;
194 }
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 break;
197 }
198
199 if (hw->phy.id) {
200 if (hw->phy.id == phy_id)
201 goto out;
202 } else if (phy_id) {
203 hw->phy.id = phy_id;
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
205 goto out;
206 }
207
208 /* In case the PHY needs to be in mdio slow mode,
209 * set slow mode and try to get the PHY id again.
210 */
211 if (hw->mac.type < e1000_pch_lpt) {
212 hw->phy.ops.release(hw);
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 if (!ret_val)
215 ret_val = e1000e_get_phy_id(hw);
216 hw->phy.ops.acquire(hw);
217 }
218
219 if (ret_val)
220 return false;
221out:
222 if (hw->mac.type >= e1000_pch_lpt) {
223 /* Only unforce SMBus if ME is not active */
224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225 /* Unforce SMBus mode in PHY */
226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
229
230 /* Unforce SMBus mode in MAC */
231 mac_reg = er32(CTRL_EXT);
232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
233 ew32(CTRL_EXT, mac_reg);
234 }
235 }
236
237 return true;
238}
239
240/**
241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242 * @hw: pointer to the HW structure
243 *
244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245 * used to reset the PHY to a quiescent state when necessary.
246 **/
247static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248{
249 u32 mac_reg;
250
251 /* Set Phy Config Counter to 50msec */
252 mac_reg = er32(FEXTNVM3);
253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
255 ew32(FEXTNVM3, mac_reg);
256
257 /* Toggle LANPHYPC Value bit */
258 mac_reg = er32(CTRL);
259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
261 ew32(CTRL, mac_reg);
262 e1e_flush();
263 usleep_range(10, 20);
264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
265 ew32(CTRL, mac_reg);
266 e1e_flush();
267
268 if (hw->mac.type < e1000_pch_lpt) {
269 msleep(50);
270 } else {
271 u16 count = 20;
272
273 do {
274 usleep_range(5000, 6000);
275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
276
277 msleep(30);
278 }
279}
280
281/**
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
284 *
285 * Workarounds/flow necessary for PHY initialization during driver load
286 * and resume paths.
287 **/
288static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
289{
290 struct e1000_adapter *adapter = hw->adapter;
291 u32 mac_reg, fwsm = er32(FWSM);
292 s32 ret_val;
293
294 /* Gate automatic PHY configuration by hardware on managed and
295 * non-managed 82579 and newer adapters.
296 */
297 e1000_gate_hw_phy_config_ich8lan(hw, true);
298
299 /* It is not possible to be certain of the current state of ULP
300 * so forcibly disable it.
301 */
302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
303 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
304 if (ret_val)
305 e_warn("Failed to disable ULP\n");
306
307 ret_val = hw->phy.ops.acquire(hw);
308 if (ret_val) {
309 e_dbg("Failed to initialize PHY flow\n");
310 goto out;
311 }
312
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
316 */
317 switch (hw->mac.type) {
318 case e1000_pch_lpt:
319 case e1000_pch_spt:
320 case e1000_pch_cnp:
321 case e1000_pch_tgp:
322 case e1000_pch_adp:
323 case e1000_pch_mtp:
324 case e1000_pch_lnp:
325 case e1000_pch_ptp:
326 case e1000_pch_nvp:
327 if (e1000_phy_is_accessible_pchlan(hw))
328 break;
329
330 /* Before toggling LANPHYPC, see if PHY is accessible by
331 * forcing MAC to SMBus mode first.
332 */
333 mac_reg = er32(CTRL_EXT);
334 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
335 ew32(CTRL_EXT, mac_reg);
336
337 /* Wait 50 milliseconds for MAC to finish any retries
338 * that it might be trying to perform from previous
339 * attempts to acknowledge any phy read requests.
340 */
341 msleep(50);
342
343 fallthrough;
344 case e1000_pch2lan:
345 if (e1000_phy_is_accessible_pchlan(hw))
346 break;
347
348 fallthrough;
349 case e1000_pchlan:
350 if ((hw->mac.type == e1000_pchlan) &&
351 (fwsm & E1000_ICH_FWSM_FW_VALID))
352 break;
353
354 if (hw->phy.ops.check_reset_block(hw)) {
355 e_dbg("Required LANPHYPC toggle blocked by ME\n");
356 ret_val = -E1000_ERR_PHY;
357 break;
358 }
359
360 /* Toggle LANPHYPC Value bit */
361 e1000_toggle_lanphypc_pch_lpt(hw);
362 if (hw->mac.type >= e1000_pch_lpt) {
363 if (e1000_phy_is_accessible_pchlan(hw))
364 break;
365
366 /* Toggling LANPHYPC brings the PHY out of SMBus mode
367 * so ensure that the MAC is also out of SMBus mode
368 */
369 mac_reg = er32(CTRL_EXT);
370 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
371 ew32(CTRL_EXT, mac_reg);
372
373 if (e1000_phy_is_accessible_pchlan(hw))
374 break;
375
376 ret_val = -E1000_ERR_PHY;
377 }
378 break;
379 default:
380 break;
381 }
382
383 hw->phy.ops.release(hw);
384 if (!ret_val) {
385
386 /* Check to see if able to reset PHY. Print error if not */
387 if (hw->phy.ops.check_reset_block(hw)) {
388 e_err("Reset blocked by ME\n");
389 goto out;
390 }
391
392 /* Reset the PHY before any access to it. Doing so, ensures
393 * that the PHY is in a known good state before we read/write
394 * PHY registers. The generic reset is sufficient here,
395 * because we haven't determined the PHY type yet.
396 */
397 ret_val = e1000e_phy_hw_reset_generic(hw);
398 if (ret_val)
399 goto out;
400
401 /* On a successful reset, possibly need to wait for the PHY
402 * to quiesce to an accessible state before returning control
403 * to the calling function. If the PHY does not quiesce, then
404 * return E1000E_BLK_PHY_RESET, as this is the condition that
405 * the PHY is in.
406 */
407 ret_val = hw->phy.ops.check_reset_block(hw);
408 if (ret_val)
409 e_err("ME blocked access to PHY after reset\n");
410 }
411
412out:
413 /* Ungate automatic PHY configuration on non-managed 82579 */
414 if ((hw->mac.type == e1000_pch2lan) &&
415 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
416 usleep_range(10000, 11000);
417 e1000_gate_hw_phy_config_ich8lan(hw, false);
418 }
419
420 return ret_val;
421}
422
423/**
424 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
425 * @hw: pointer to the HW structure
426 *
427 * Initialize family-specific PHY parameters and function pointers.
428 **/
429static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
430{
431 struct e1000_phy_info *phy = &hw->phy;
432 s32 ret_val;
433
434 phy->addr = 1;
435 phy->reset_delay_us = 100;
436
437 phy->ops.set_page = e1000_set_page_igp;
438 phy->ops.read_reg = e1000_read_phy_reg_hv;
439 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
440 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
441 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
442 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
443 phy->ops.write_reg = e1000_write_phy_reg_hv;
444 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
445 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
446 phy->ops.power_up = e1000_power_up_phy_copper;
447 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
448 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
449
450 phy->id = e1000_phy_unknown;
451
452 ret_val = e1000_init_phy_workarounds_pchlan(hw);
453 if (ret_val)
454 return ret_val;
455
456 if (phy->id == e1000_phy_unknown)
457 switch (hw->mac.type) {
458 default:
459 ret_val = e1000e_get_phy_id(hw);
460 if (ret_val)
461 return ret_val;
462 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
463 break;
464 fallthrough;
465 case e1000_pch2lan:
466 case e1000_pch_lpt:
467 case e1000_pch_spt:
468 case e1000_pch_cnp:
469 case e1000_pch_tgp:
470 case e1000_pch_adp:
471 case e1000_pch_mtp:
472 case e1000_pch_lnp:
473 case e1000_pch_ptp:
474 case e1000_pch_nvp:
475 /* In case the PHY needs to be in mdio slow mode,
476 * set slow mode and try to get the PHY id again.
477 */
478 ret_val = e1000_set_mdio_slow_mode_hv(hw);
479 if (ret_val)
480 return ret_val;
481 ret_val = e1000e_get_phy_id(hw);
482 if (ret_val)
483 return ret_val;
484 break;
485 }
486 phy->type = e1000e_get_phy_type_from_id(phy->id);
487
488 switch (phy->type) {
489 case e1000_phy_82577:
490 case e1000_phy_82579:
491 case e1000_phy_i217:
492 phy->ops.check_polarity = e1000_check_polarity_82577;
493 phy->ops.force_speed_duplex =
494 e1000_phy_force_speed_duplex_82577;
495 phy->ops.get_cable_length = e1000_get_cable_length_82577;
496 phy->ops.get_info = e1000_get_phy_info_82577;
497 phy->ops.commit = e1000e_phy_sw_reset;
498 break;
499 case e1000_phy_82578:
500 phy->ops.check_polarity = e1000_check_polarity_m88;
501 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
502 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
503 phy->ops.get_info = e1000e_get_phy_info_m88;
504 break;
505 default:
506 ret_val = -E1000_ERR_PHY;
507 break;
508 }
509
510 return ret_val;
511}
512
513/**
514 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
515 * @hw: pointer to the HW structure
516 *
517 * Initialize family-specific PHY parameters and function pointers.
518 **/
519static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
520{
521 struct e1000_phy_info *phy = &hw->phy;
522 s32 ret_val;
523 u16 i = 0;
524
525 phy->addr = 1;
526 phy->reset_delay_us = 100;
527
528 phy->ops.power_up = e1000_power_up_phy_copper;
529 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
530
531 /* We may need to do this twice - once for IGP and if that fails,
532 * we'll set BM func pointers and try again
533 */
534 ret_val = e1000e_determine_phy_address(hw);
535 if (ret_val) {
536 phy->ops.write_reg = e1000e_write_phy_reg_bm;
537 phy->ops.read_reg = e1000e_read_phy_reg_bm;
538 ret_val = e1000e_determine_phy_address(hw);
539 if (ret_val) {
540 e_dbg("Cannot determine PHY addr. Erroring out\n");
541 return ret_val;
542 }
543 }
544
545 phy->id = 0;
546 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
547 (i++ < 100)) {
548 usleep_range(1000, 1100);
549 ret_val = e1000e_get_phy_id(hw);
550 if (ret_val)
551 return ret_val;
552 }
553
554 /* Verify phy id */
555 switch (phy->id) {
556 case IGP03E1000_E_PHY_ID:
557 phy->type = e1000_phy_igp_3;
558 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
559 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
560 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
561 phy->ops.get_info = e1000e_get_phy_info_igp;
562 phy->ops.check_polarity = e1000_check_polarity_igp;
563 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
564 break;
565 case IFE_E_PHY_ID:
566 case IFE_PLUS_E_PHY_ID:
567 case IFE_C_E_PHY_ID:
568 phy->type = e1000_phy_ife;
569 phy->autoneg_mask = E1000_ALL_NOT_GIG;
570 phy->ops.get_info = e1000_get_phy_info_ife;
571 phy->ops.check_polarity = e1000_check_polarity_ife;
572 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
573 break;
574 case BME1000_E_PHY_ID:
575 phy->type = e1000_phy_bm;
576 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
577 phy->ops.read_reg = e1000e_read_phy_reg_bm;
578 phy->ops.write_reg = e1000e_write_phy_reg_bm;
579 phy->ops.commit = e1000e_phy_sw_reset;
580 phy->ops.get_info = e1000e_get_phy_info_m88;
581 phy->ops.check_polarity = e1000_check_polarity_m88;
582 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
583 break;
584 default:
585 return -E1000_ERR_PHY;
586 }
587
588 return 0;
589}
590
591/**
592 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
593 * @hw: pointer to the HW structure
594 *
595 * Initialize family-specific NVM parameters and function
596 * pointers.
597 **/
598static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
599{
600 struct e1000_nvm_info *nvm = &hw->nvm;
601 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
602 u32 gfpreg, sector_base_addr, sector_end_addr;
603 u16 i;
604 u32 nvm_size;
605
606 nvm->type = e1000_nvm_flash_sw;
607
608 if (hw->mac.type >= e1000_pch_spt) {
609 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
610 * STRAP register. This is because in SPT the GbE Flash region
611 * is no longer accessed through the flash registers. Instead,
612 * the mechanism has changed, and the Flash region access
613 * registers are now implemented in GbE memory space.
614 */
615 nvm->flash_base_addr = 0;
616 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
617 * NVM_SIZE_MULTIPLIER;
618 nvm->flash_bank_size = nvm_size / 2;
619 /* Adjust to word count */
620 nvm->flash_bank_size /= sizeof(u16);
621 /* Set the base address for flash register access */
622 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
623 } else {
624 /* Can't read flash registers if register set isn't mapped. */
625 if (!hw->flash_address) {
626 e_dbg("ERROR: Flash registers not mapped\n");
627 return -E1000_ERR_CONFIG;
628 }
629
630 gfpreg = er32flash(ICH_FLASH_GFPREG);
631
632 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
633 * Add 1 to sector_end_addr since this sector is included in
634 * the overall size.
635 */
636 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
637 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
638
639 /* flash_base_addr is byte-aligned */
640 nvm->flash_base_addr = sector_base_addr
641 << FLASH_SECTOR_ADDR_SHIFT;
642
643 /* find total size of the NVM, then cut in half since the total
644 * size represents two separate NVM banks.
645 */
646 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
647 << FLASH_SECTOR_ADDR_SHIFT);
648 nvm->flash_bank_size /= 2;
649 /* Adjust to word count */
650 nvm->flash_bank_size /= sizeof(u16);
651 }
652
653 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
654
655 /* Clear shadow ram */
656 for (i = 0; i < nvm->word_size; i++) {
657 dev_spec->shadow_ram[i].modified = false;
658 dev_spec->shadow_ram[i].value = 0xFFFF;
659 }
660
661 return 0;
662}
663
664/**
665 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
666 * @hw: pointer to the HW structure
667 *
668 * Initialize family-specific MAC parameters and function
669 * pointers.
670 **/
671static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
672{
673 struct e1000_mac_info *mac = &hw->mac;
674
675 /* Set media type function pointer */
676 hw->phy.media_type = e1000_media_type_copper;
677
678 /* Set mta register count */
679 mac->mta_reg_count = 32;
680 /* Set rar entry count */
681 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
682 if (mac->type == e1000_ich8lan)
683 mac->rar_entry_count--;
684 /* FWSM register */
685 mac->has_fwsm = true;
686 /* ARC subsystem not supported */
687 mac->arc_subsystem_valid = false;
688 /* Adaptive IFS supported */
689 mac->adaptive_ifs = true;
690
691 /* LED and other operations */
692 switch (mac->type) {
693 case e1000_ich8lan:
694 case e1000_ich9lan:
695 case e1000_ich10lan:
696 /* check management mode */
697 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
698 /* ID LED init */
699 mac->ops.id_led_init = e1000e_id_led_init_generic;
700 /* blink LED */
701 mac->ops.blink_led = e1000e_blink_led_generic;
702 /* setup LED */
703 mac->ops.setup_led = e1000e_setup_led_generic;
704 /* cleanup LED */
705 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
706 /* turn on/off LED */
707 mac->ops.led_on = e1000_led_on_ich8lan;
708 mac->ops.led_off = e1000_led_off_ich8lan;
709 break;
710 case e1000_pch2lan:
711 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
712 mac->ops.rar_set = e1000_rar_set_pch2lan;
713 fallthrough;
714 case e1000_pch_lpt:
715 case e1000_pch_spt:
716 case e1000_pch_cnp:
717 case e1000_pch_tgp:
718 case e1000_pch_adp:
719 case e1000_pch_mtp:
720 case e1000_pch_lnp:
721 case e1000_pch_ptp:
722 case e1000_pch_nvp:
723 case e1000_pchlan:
724 /* check management mode */
725 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
726 /* ID LED init */
727 mac->ops.id_led_init = e1000_id_led_init_pchlan;
728 /* setup LED */
729 mac->ops.setup_led = e1000_setup_led_pchlan;
730 /* cleanup LED */
731 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
732 /* turn on/off LED */
733 mac->ops.led_on = e1000_led_on_pchlan;
734 mac->ops.led_off = e1000_led_off_pchlan;
735 break;
736 default:
737 break;
738 }
739
740 if (mac->type >= e1000_pch_lpt) {
741 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
742 mac->ops.rar_set = e1000_rar_set_pch_lpt;
743 mac->ops.setup_physical_interface =
744 e1000_setup_copper_link_pch_lpt;
745 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
746 }
747
748 /* Enable PCS Lock-loss workaround for ICH8 */
749 if (mac->type == e1000_ich8lan)
750 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
751
752 return 0;
753}
754
755/**
756 * __e1000_access_emi_reg_locked - Read/write EMI register
757 * @hw: pointer to the HW structure
758 * @address: EMI address to program
759 * @data: pointer to value to read/write from/to the EMI address
760 * @read: boolean flag to indicate read or write
761 *
762 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
763 **/
764static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
765 u16 *data, bool read)
766{
767 s32 ret_val;
768
769 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
770 if (ret_val)
771 return ret_val;
772
773 if (read)
774 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
775 else
776 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
777
778 return ret_val;
779}
780
781/**
782 * e1000_read_emi_reg_locked - Read Extended Management Interface register
783 * @hw: pointer to the HW structure
784 * @addr: EMI address to program
785 * @data: value to be read from the EMI address
786 *
787 * Assumes the SW/FW/HW Semaphore is already acquired.
788 **/
789s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
790{
791 return __e1000_access_emi_reg_locked(hw, addr, data, true);
792}
793
794/**
795 * e1000_write_emi_reg_locked - Write Extended Management Interface register
796 * @hw: pointer to the HW structure
797 * @addr: EMI address to program
798 * @data: value to be written to the EMI address
799 *
800 * Assumes the SW/FW/HW Semaphore is already acquired.
801 **/
802s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
803{
804 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
805}
806
807/**
808 * e1000_set_eee_pchlan - Enable/disable EEE support
809 * @hw: pointer to the HW structure
810 *
811 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
812 * the link and the EEE capabilities of the link partner. The LPI Control
813 * register bits will remain set only if/when link is up.
814 *
815 * EEE LPI must not be asserted earlier than one second after link is up.
816 * On 82579, EEE LPI should not be enabled until such time otherwise there
817 * can be link issues with some switches. Other devices can have EEE LPI
818 * enabled immediately upon link up since they have a timer in hardware which
819 * prevents LPI from being asserted too early.
820 **/
821s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
822{
823 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
824 s32 ret_val;
825 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
826
827 switch (hw->phy.type) {
828 case e1000_phy_82579:
829 lpa = I82579_EEE_LP_ABILITY;
830 pcs_status = I82579_EEE_PCS_STATUS;
831 adv_addr = I82579_EEE_ADVERTISEMENT;
832 break;
833 case e1000_phy_i217:
834 lpa = I217_EEE_LP_ABILITY;
835 pcs_status = I217_EEE_PCS_STATUS;
836 adv_addr = I217_EEE_ADVERTISEMENT;
837 break;
838 default:
839 return 0;
840 }
841
842 ret_val = hw->phy.ops.acquire(hw);
843 if (ret_val)
844 return ret_val;
845
846 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
847 if (ret_val)
848 goto release;
849
850 /* Clear bits that enable EEE in various speeds */
851 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
852
853 /* Enable EEE if not disabled by user */
854 if (!dev_spec->eee_disable) {
855 /* Save off link partner's EEE ability */
856 ret_val = e1000_read_emi_reg_locked(hw, lpa,
857 &dev_spec->eee_lp_ability);
858 if (ret_val)
859 goto release;
860
861 /* Read EEE advertisement */
862 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
863 if (ret_val)
864 goto release;
865
866 /* Enable EEE only for speeds in which the link partner is
867 * EEE capable and for which we advertise EEE.
868 */
869 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
870 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
871
872 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
873 e1e_rphy_locked(hw, MII_LPA, &data);
874 if (data & LPA_100FULL)
875 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
876 else
877 /* EEE is not supported in 100Half, so ignore
878 * partner's EEE in 100 ability if full-duplex
879 * is not advertised.
880 */
881 dev_spec->eee_lp_ability &=
882 ~I82579_EEE_100_SUPPORTED;
883 }
884 }
885
886 if (hw->phy.type == e1000_phy_82579) {
887 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
888 &data);
889 if (ret_val)
890 goto release;
891
892 data &= ~I82579_LPI_100_PLL_SHUT;
893 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
894 data);
895 }
896
897 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
898 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
899 if (ret_val)
900 goto release;
901
902 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
903release:
904 hw->phy.ops.release(hw);
905
906 return ret_val;
907}
908
909/**
910 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
911 * @hw: pointer to the HW structure
912 * @link: link up bool flag
913 *
914 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
915 * preventing further DMA write requests. Workaround the issue by disabling
916 * the de-assertion of the clock request when in 1Gpbs mode.
917 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
918 * speeds in order to avoid Tx hangs.
919 **/
920static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
921{
922 u32 fextnvm6 = er32(FEXTNVM6);
923 u32 status = er32(STATUS);
924 s32 ret_val = 0;
925 u16 reg;
926
927 if (link && (status & E1000_STATUS_SPEED_1000)) {
928 ret_val = hw->phy.ops.acquire(hw);
929 if (ret_val)
930 return ret_val;
931
932 ret_val =
933 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
934 ®);
935 if (ret_val)
936 goto release;
937
938 ret_val =
939 e1000e_write_kmrn_reg_locked(hw,
940 E1000_KMRNCTRLSTA_K1_CONFIG,
941 reg &
942 ~E1000_KMRNCTRLSTA_K1_ENABLE);
943 if (ret_val)
944 goto release;
945
946 usleep_range(10, 20);
947
948 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
949
950 ret_val =
951 e1000e_write_kmrn_reg_locked(hw,
952 E1000_KMRNCTRLSTA_K1_CONFIG,
953 reg);
954release:
955 hw->phy.ops.release(hw);
956 } else {
957 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
958 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
959
960 if ((hw->phy.revision > 5) || !link ||
961 ((status & E1000_STATUS_SPEED_100) &&
962 (status & E1000_STATUS_FD)))
963 goto update_fextnvm6;
964
965 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
966 if (ret_val)
967 return ret_val;
968
969 /* Clear link status transmit timeout */
970 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
971
972 if (status & E1000_STATUS_SPEED_100) {
973 /* Set inband Tx timeout to 5x10us for 100Half */
974 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
975
976 /* Do not extend the K1 entry latency for 100Half */
977 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
978 } else {
979 /* Set inband Tx timeout to 50x10us for 10Full/Half */
980 reg |= 50 <<
981 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
982
983 /* Extend the K1 entry latency for 10 Mbps */
984 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
985 }
986
987 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
988 if (ret_val)
989 return ret_val;
990
991update_fextnvm6:
992 ew32(FEXTNVM6, fextnvm6);
993 }
994
995 return ret_val;
996}
997
998/**
999 * e1000_platform_pm_pch_lpt - Set platform power management values
1000 * @hw: pointer to the HW structure
1001 * @link: bool indicating link status
1002 *
1003 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
1004 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
1005 * when link is up (which must not exceed the maximum latency supported
1006 * by the platform), otherwise specify there is no LTR requirement.
1007 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
1008 * latencies in the LTR Extended Capability Structure in the PCIe Extended
1009 * Capability register set, on this device LTR is set by writing the
1010 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
1011 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1012 * message to the PMC.
1013 **/
1014static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1015{
1016 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1017 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1018 u32 max_ltr_enc_d = 0; /* maximum LTR decoded by platform */
1019 u32 lat_enc_d = 0; /* latency decoded */
1020 u16 lat_enc = 0; /* latency encoded */
1021
1022 if (link) {
1023 u16 speed, duplex, scale = 0;
1024 u16 max_snoop, max_nosnoop;
1025 u16 max_ltr_enc; /* max LTR latency encoded */
1026 u64 value;
1027 u32 rxa;
1028
1029 if (!hw->adapter->max_frame_size) {
1030 e_dbg("max_frame_size not set.\n");
1031 return -E1000_ERR_CONFIG;
1032 }
1033
1034 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1035 if (!speed) {
1036 e_dbg("Speed not set.\n");
1037 return -E1000_ERR_CONFIG;
1038 }
1039
1040 /* Rx Packet Buffer Allocation size (KB) */
1041 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1042
1043 /* Determine the maximum latency tolerated by the device.
1044 *
1045 * Per the PCIe spec, the tolerated latencies are encoded as
1046 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1047 * a 10-bit value (0-1023) to provide a range from 1 ns to
1048 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1049 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1050 */
1051 rxa *= 512;
1052 value = (rxa > hw->adapter->max_frame_size) ?
1053 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1054 0;
1055
1056 while (value > PCI_LTR_VALUE_MASK) {
1057 scale++;
1058 value = DIV_ROUND_UP(value, BIT(5));
1059 }
1060 if (scale > E1000_LTRV_SCALE_MAX) {
1061 e_dbg("Invalid LTR latency scale %d\n", scale);
1062 return -E1000_ERR_CONFIG;
1063 }
1064 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1065
1066 /* Determine the maximum latency tolerated by the platform */
1067 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1068 &max_snoop);
1069 pci_read_config_word(hw->adapter->pdev,
1070 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1071 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1072
1073 lat_enc_d = (lat_enc & E1000_LTRV_VALUE_MASK) *
1074 (1U << (E1000_LTRV_SCALE_FACTOR *
1075 FIELD_GET(E1000_LTRV_SCALE_MASK, lat_enc)));
1076
1077 max_ltr_enc_d = (max_ltr_enc & E1000_LTRV_VALUE_MASK) *
1078 (1U << (E1000_LTRV_SCALE_FACTOR *
1079 FIELD_GET(E1000_LTRV_SCALE_MASK, max_ltr_enc)));
1080
1081 if (lat_enc_d > max_ltr_enc_d)
1082 lat_enc = max_ltr_enc;
1083 }
1084
1085 /* Set Snoop and No-Snoop latencies the same */
1086 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1087 ew32(LTRV, reg);
1088
1089 return 0;
1090}
1091
1092/**
1093 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1094 * @hw: pointer to the HW structure
1095 * @to_sx: boolean indicating a system power state transition to Sx
1096 *
1097 * When link is down, configure ULP mode to significantly reduce the power
1098 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1099 * ME firmware to start the ULP configuration. If not on an ME enabled
1100 * system, configure the ULP mode by software.
1101 */
1102s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1103{
1104 u32 mac_reg;
1105 s32 ret_val = 0;
1106 u16 phy_reg;
1107 u16 oem_reg = 0;
1108
1109 if ((hw->mac.type < e1000_pch_lpt) ||
1110 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1111 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1112 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1113 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1114 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1115 return 0;
1116
1117 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1118 /* Request ME configure ULP mode in the PHY */
1119 mac_reg = er32(H2ME);
1120 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1121 ew32(H2ME, mac_reg);
1122
1123 goto out;
1124 }
1125
1126 if (!to_sx) {
1127 int i = 0;
1128
1129 /* Poll up to 5 seconds for Cable Disconnected indication */
1130 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1131 /* Bail if link is re-acquired */
1132 if (er32(STATUS) & E1000_STATUS_LU)
1133 return -E1000_ERR_PHY;
1134
1135 if (i++ == 100)
1136 break;
1137
1138 msleep(50);
1139 }
1140 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1141 (er32(FEXT) &
1142 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1143 }
1144
1145 ret_val = hw->phy.ops.acquire(hw);
1146 if (ret_val)
1147 goto out;
1148
1149 /* Force SMBus mode in PHY */
1150 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1151 if (ret_val)
1152 goto release;
1153 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1154 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1155
1156 /* Force SMBus mode in MAC */
1157 mac_reg = er32(CTRL_EXT);
1158 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1159 ew32(CTRL_EXT, mac_reg);
1160
1161 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1162 * LPLU and disable Gig speed when entering ULP
1163 */
1164 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1165 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1166 &oem_reg);
1167 if (ret_val)
1168 goto release;
1169
1170 phy_reg = oem_reg;
1171 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1172
1173 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1174 phy_reg);
1175
1176 if (ret_val)
1177 goto release;
1178 }
1179
1180 /* Set Inband ULP Exit, Reset to SMBus mode and
1181 * Disable SMBus Release on PERST# in PHY
1182 */
1183 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1184 if (ret_val)
1185 goto release;
1186 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1187 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1188 if (to_sx) {
1189 if (er32(WUFC) & E1000_WUFC_LNKC)
1190 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1191 else
1192 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1193
1194 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1195 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1196 } else {
1197 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1198 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1199 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1200 }
1201 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1202
1203 /* Set Disable SMBus Release on PERST# in MAC */
1204 mac_reg = er32(FEXTNVM7);
1205 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1206 ew32(FEXTNVM7, mac_reg);
1207
1208 /* Commit ULP changes in PHY by starting auto ULP configuration */
1209 phy_reg |= I218_ULP_CONFIG1_START;
1210 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1211
1212 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1213 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1214 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1215 oem_reg);
1216 if (ret_val)
1217 goto release;
1218 }
1219
1220release:
1221 hw->phy.ops.release(hw);
1222out:
1223 if (ret_val)
1224 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1225 else
1226 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1227
1228 return ret_val;
1229}
1230
1231/**
1232 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1233 * @hw: pointer to the HW structure
1234 * @force: boolean indicating whether or not to force disabling ULP
1235 *
1236 * Un-configure ULP mode when link is up, the system is transitioned from
1237 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1238 * system, poll for an indication from ME that ULP has been un-configured.
1239 * If not on an ME enabled system, un-configure the ULP mode by software.
1240 *
1241 * During nominal operation, this function is called when link is acquired
1242 * to disable ULP mode (force=false); otherwise, for example when unloading
1243 * the driver or during Sx->S0 transitions, this is called with force=true
1244 * to forcibly disable ULP.
1245 */
1246static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1247{
1248 s32 ret_val = 0;
1249 u32 mac_reg;
1250 u16 phy_reg;
1251 int i = 0;
1252
1253 if ((hw->mac.type < e1000_pch_lpt) ||
1254 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1255 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1256 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1257 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1258 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1259 return 0;
1260
1261 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1262 struct e1000_adapter *adapter = hw->adapter;
1263 bool firmware_bug = false;
1264
1265 if (force) {
1266 /* Request ME un-configure ULP mode in the PHY */
1267 mac_reg = er32(H2ME);
1268 mac_reg &= ~E1000_H2ME_ULP;
1269 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1270 ew32(H2ME, mac_reg);
1271 }
1272
1273 /* Poll up to 2.5 seconds for ME to clear ULP_CFG_DONE.
1274 * If this takes more than 1 second, show a warning indicating a
1275 * firmware bug
1276 */
1277 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1278 if (i++ == 250) {
1279 ret_val = -E1000_ERR_PHY;
1280 goto out;
1281 }
1282 if (i > 100 && !firmware_bug)
1283 firmware_bug = true;
1284
1285 usleep_range(10000, 11000);
1286 }
1287 if (firmware_bug)
1288 e_warn("ULP_CONFIG_DONE took %d msec. This is a firmware bug\n",
1289 i * 10);
1290 else
1291 e_dbg("ULP_CONFIG_DONE cleared after %d msec\n",
1292 i * 10);
1293
1294 if (force) {
1295 mac_reg = er32(H2ME);
1296 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1297 ew32(H2ME, mac_reg);
1298 } else {
1299 /* Clear H2ME.ULP after ME ULP configuration */
1300 mac_reg = er32(H2ME);
1301 mac_reg &= ~E1000_H2ME_ULP;
1302 ew32(H2ME, mac_reg);
1303 }
1304
1305 goto out;
1306 }
1307
1308 ret_val = hw->phy.ops.acquire(hw);
1309 if (ret_val)
1310 goto out;
1311
1312 if (force)
1313 /* Toggle LANPHYPC Value bit */
1314 e1000_toggle_lanphypc_pch_lpt(hw);
1315
1316 /* Unforce SMBus mode in PHY */
1317 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1318 if (ret_val) {
1319 /* The MAC might be in PCIe mode, so temporarily force to
1320 * SMBus mode in order to access the PHY.
1321 */
1322 mac_reg = er32(CTRL_EXT);
1323 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1324 ew32(CTRL_EXT, mac_reg);
1325
1326 msleep(50);
1327
1328 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1329 &phy_reg);
1330 if (ret_val)
1331 goto release;
1332 }
1333 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1334 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1335
1336 /* Unforce SMBus mode in MAC */
1337 mac_reg = er32(CTRL_EXT);
1338 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1339 ew32(CTRL_EXT, mac_reg);
1340
1341 /* When ULP mode was previously entered, K1 was disabled by the
1342 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1343 */
1344 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1345 if (ret_val)
1346 goto release;
1347 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1348 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1349
1350 /* Clear ULP enabled configuration */
1351 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1352 if (ret_val)
1353 goto release;
1354 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1355 I218_ULP_CONFIG1_STICKY_ULP |
1356 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1357 I218_ULP_CONFIG1_WOL_HOST |
1358 I218_ULP_CONFIG1_INBAND_EXIT |
1359 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1360 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1361 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1362 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1363
1364 /* Commit ULP changes by starting auto ULP configuration */
1365 phy_reg |= I218_ULP_CONFIG1_START;
1366 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1367
1368 /* Clear Disable SMBus Release on PERST# in MAC */
1369 mac_reg = er32(FEXTNVM7);
1370 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1371 ew32(FEXTNVM7, mac_reg);
1372
1373release:
1374 hw->phy.ops.release(hw);
1375 if (force) {
1376 e1000_phy_hw_reset(hw);
1377 msleep(50);
1378 }
1379out:
1380 if (ret_val)
1381 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1382 else
1383 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1384
1385 return ret_val;
1386}
1387
1388/**
1389 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1390 * @hw: pointer to the HW structure
1391 *
1392 * Checks to see of the link status of the hardware has changed. If a
1393 * change in link status has been detected, then we read the PHY registers
1394 * to get the current speed/duplex if link exists.
1395 **/
1396static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1397{
1398 struct e1000_mac_info *mac = &hw->mac;
1399 s32 ret_val, tipg_reg = 0;
1400 u16 emi_addr, emi_val = 0;
1401 bool link;
1402 u16 phy_reg;
1403
1404 /* We only want to go out to the PHY registers to see if Auto-Neg
1405 * has completed and/or if our link status has changed. The
1406 * get_link_status flag is set upon receiving a Link Status
1407 * Change or Rx Sequence Error interrupt.
1408 */
1409 if (!mac->get_link_status)
1410 return 0;
1411 mac->get_link_status = false;
1412
1413 /* First we want to see if the MII Status Register reports
1414 * link. If so, then we want to get the current speed/duplex
1415 * of the PHY.
1416 */
1417 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1418 if (ret_val)
1419 goto out;
1420
1421 if (hw->mac.type == e1000_pchlan) {
1422 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1423 if (ret_val)
1424 goto out;
1425 }
1426
1427 /* When connected at 10Mbps half-duplex, some parts are excessively
1428 * aggressive resulting in many collisions. To avoid this, increase
1429 * the IPG and reduce Rx latency in the PHY.
1430 */
1431 if ((hw->mac.type >= e1000_pch2lan) && link) {
1432 u16 speed, duplex;
1433
1434 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1435 tipg_reg = er32(TIPG);
1436 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1437
1438 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1439 tipg_reg |= 0xFF;
1440 /* Reduce Rx latency in analog PHY */
1441 emi_val = 0;
1442 } else if (hw->mac.type >= e1000_pch_spt &&
1443 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1444 tipg_reg |= 0xC;
1445 emi_val = 1;
1446 } else {
1447
1448 /* Roll back the default values */
1449 tipg_reg |= 0x08;
1450 emi_val = 1;
1451 }
1452
1453 ew32(TIPG, tipg_reg);
1454
1455 ret_val = hw->phy.ops.acquire(hw);
1456 if (ret_val)
1457 goto out;
1458
1459 if (hw->mac.type == e1000_pch2lan)
1460 emi_addr = I82579_RX_CONFIG;
1461 else
1462 emi_addr = I217_RX_CONFIG;
1463 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1464
1465 if (hw->mac.type >= e1000_pch_lpt) {
1466 u16 phy_reg;
1467
1468 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1469 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1470 if (speed == SPEED_100 || speed == SPEED_10)
1471 phy_reg |= 0x3E8;
1472 else
1473 phy_reg |= 0xFA;
1474 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1475
1476 if (speed == SPEED_1000) {
1477 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1478 &phy_reg);
1479
1480 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1481
1482 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1483 phy_reg);
1484 }
1485 }
1486 hw->phy.ops.release(hw);
1487
1488 if (ret_val)
1489 goto out;
1490
1491 if (hw->mac.type >= e1000_pch_spt) {
1492 u16 data;
1493 u16 ptr_gap;
1494
1495 if (speed == SPEED_1000) {
1496 ret_val = hw->phy.ops.acquire(hw);
1497 if (ret_val)
1498 goto out;
1499
1500 ret_val = e1e_rphy_locked(hw,
1501 PHY_REG(776, 20),
1502 &data);
1503 if (ret_val) {
1504 hw->phy.ops.release(hw);
1505 goto out;
1506 }
1507
1508 ptr_gap = (data & (0x3FF << 2)) >> 2;
1509 if (ptr_gap < 0x18) {
1510 data &= ~(0x3FF << 2);
1511 data |= (0x18 << 2);
1512 ret_val =
1513 e1e_wphy_locked(hw,
1514 PHY_REG(776, 20),
1515 data);
1516 }
1517 hw->phy.ops.release(hw);
1518 if (ret_val)
1519 goto out;
1520 } else {
1521 ret_val = hw->phy.ops.acquire(hw);
1522 if (ret_val)
1523 goto out;
1524
1525 ret_val = e1e_wphy_locked(hw,
1526 PHY_REG(776, 20),
1527 0xC023);
1528 hw->phy.ops.release(hw);
1529 if (ret_val)
1530 goto out;
1531
1532 }
1533 }
1534 }
1535
1536 /* I217 Packet Loss issue:
1537 * ensure that FEXTNVM4 Beacon Duration is set correctly
1538 * on power up.
1539 * Set the Beacon Duration for I217 to 8 usec
1540 */
1541 if (hw->mac.type >= e1000_pch_lpt) {
1542 u32 mac_reg;
1543
1544 mac_reg = er32(FEXTNVM4);
1545 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1546 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1547 ew32(FEXTNVM4, mac_reg);
1548 }
1549
1550 /* Work-around I218 hang issue */
1551 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1552 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1553 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1554 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1555 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1556 if (ret_val)
1557 goto out;
1558 }
1559 if (hw->mac.type >= e1000_pch_lpt) {
1560 /* Set platform power management values for
1561 * Latency Tolerance Reporting (LTR)
1562 */
1563 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1564 if (ret_val)
1565 goto out;
1566 }
1567
1568 /* Clear link partner's EEE ability */
1569 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1570
1571 if (hw->mac.type >= e1000_pch_lpt) {
1572 u32 fextnvm6 = er32(FEXTNVM6);
1573
1574 if (hw->mac.type == e1000_pch_spt) {
1575 /* FEXTNVM6 K1-off workaround - for SPT only */
1576 u32 pcieanacfg = er32(PCIEANACFG);
1577
1578 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1579 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1580 else
1581 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1582 }
1583
1584 ew32(FEXTNVM6, fextnvm6);
1585 }
1586
1587 if (!link)
1588 goto out;
1589
1590 switch (hw->mac.type) {
1591 case e1000_pch2lan:
1592 ret_val = e1000_k1_workaround_lv(hw);
1593 if (ret_val)
1594 return ret_val;
1595 fallthrough;
1596 case e1000_pchlan:
1597 if (hw->phy.type == e1000_phy_82578) {
1598 ret_val = e1000_link_stall_workaround_hv(hw);
1599 if (ret_val)
1600 return ret_val;
1601 }
1602
1603 /* Workaround for PCHx parts in half-duplex:
1604 * Set the number of preambles removed from the packet
1605 * when it is passed from the PHY to the MAC to prevent
1606 * the MAC from misinterpreting the packet type.
1607 */
1608 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1609 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1610
1611 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1612 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1613
1614 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1615 break;
1616 default:
1617 break;
1618 }
1619
1620 /* Check if there was DownShift, must be checked
1621 * immediately after link-up
1622 */
1623 e1000e_check_downshift(hw);
1624
1625 /* Enable/Disable EEE after link up */
1626 if (hw->phy.type > e1000_phy_82579) {
1627 ret_val = e1000_set_eee_pchlan(hw);
1628 if (ret_val)
1629 return ret_val;
1630 }
1631
1632 /* If we are forcing speed/duplex, then we simply return since
1633 * we have already determined whether we have link or not.
1634 */
1635 if (!mac->autoneg)
1636 return -E1000_ERR_CONFIG;
1637
1638 /* Auto-Neg is enabled. Auto Speed Detection takes care
1639 * of MAC speed/duplex configuration. So we only need to
1640 * configure Collision Distance in the MAC.
1641 */
1642 mac->ops.config_collision_dist(hw);
1643
1644 /* Configure Flow Control now that Auto-Neg has completed.
1645 * First, we need to restore the desired flow control
1646 * settings because we may have had to re-autoneg with a
1647 * different link partner.
1648 */
1649 ret_val = e1000e_config_fc_after_link_up(hw);
1650 if (ret_val)
1651 e_dbg("Error configuring flow control\n");
1652
1653 return ret_val;
1654
1655out:
1656 mac->get_link_status = true;
1657 return ret_val;
1658}
1659
1660static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1661{
1662 struct e1000_hw *hw = &adapter->hw;
1663 s32 rc;
1664
1665 rc = e1000_init_mac_params_ich8lan(hw);
1666 if (rc)
1667 return rc;
1668
1669 rc = e1000_init_nvm_params_ich8lan(hw);
1670 if (rc)
1671 return rc;
1672
1673 switch (hw->mac.type) {
1674 case e1000_ich8lan:
1675 case e1000_ich9lan:
1676 case e1000_ich10lan:
1677 rc = e1000_init_phy_params_ich8lan(hw);
1678 break;
1679 case e1000_pchlan:
1680 case e1000_pch2lan:
1681 case e1000_pch_lpt:
1682 case e1000_pch_spt:
1683 case e1000_pch_cnp:
1684 case e1000_pch_tgp:
1685 case e1000_pch_adp:
1686 case e1000_pch_mtp:
1687 case e1000_pch_lnp:
1688 case e1000_pch_ptp:
1689 case e1000_pch_nvp:
1690 rc = e1000_init_phy_params_pchlan(hw);
1691 break;
1692 default:
1693 break;
1694 }
1695 if (rc)
1696 return rc;
1697
1698 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1699 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1700 */
1701 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1702 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1703 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1704 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1705 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1706
1707 hw->mac.ops.blink_led = NULL;
1708 }
1709
1710 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1711 (adapter->hw.phy.type != e1000_phy_ife))
1712 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1713
1714 /* Enable workaround for 82579 w/ ME enabled */
1715 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1716 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1717 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1718
1719 return 0;
1720}
1721
1722static DEFINE_MUTEX(nvm_mutex);
1723
1724/**
1725 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1726 * @hw: pointer to the HW structure
1727 *
1728 * Acquires the mutex for performing NVM operations.
1729 **/
1730static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1731{
1732 mutex_lock(&nvm_mutex);
1733
1734 return 0;
1735}
1736
1737/**
1738 * e1000_release_nvm_ich8lan - Release NVM mutex
1739 * @hw: pointer to the HW structure
1740 *
1741 * Releases the mutex used while performing NVM operations.
1742 **/
1743static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1744{
1745 mutex_unlock(&nvm_mutex);
1746}
1747
1748/**
1749 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1750 * @hw: pointer to the HW structure
1751 *
1752 * Acquires the software control flag for performing PHY and select
1753 * MAC CSR accesses.
1754 **/
1755static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1756{
1757 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1758 s32 ret_val = 0;
1759
1760 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1761 &hw->adapter->state)) {
1762 e_dbg("contention for Phy access\n");
1763 return -E1000_ERR_PHY;
1764 }
1765
1766 while (timeout) {
1767 extcnf_ctrl = er32(EXTCNF_CTRL);
1768 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1769 break;
1770
1771 mdelay(1);
1772 timeout--;
1773 }
1774
1775 if (!timeout) {
1776 e_dbg("SW has already locked the resource.\n");
1777 ret_val = -E1000_ERR_CONFIG;
1778 goto out;
1779 }
1780
1781 timeout = SW_FLAG_TIMEOUT;
1782
1783 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1784 ew32(EXTCNF_CTRL, extcnf_ctrl);
1785
1786 while (timeout) {
1787 extcnf_ctrl = er32(EXTCNF_CTRL);
1788 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1789 break;
1790
1791 mdelay(1);
1792 timeout--;
1793 }
1794
1795 if (!timeout) {
1796 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1797 er32(FWSM), extcnf_ctrl);
1798 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1799 ew32(EXTCNF_CTRL, extcnf_ctrl);
1800 ret_val = -E1000_ERR_CONFIG;
1801 goto out;
1802 }
1803
1804out:
1805 if (ret_val)
1806 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1807
1808 return ret_val;
1809}
1810
1811/**
1812 * e1000_release_swflag_ich8lan - Release software control flag
1813 * @hw: pointer to the HW structure
1814 *
1815 * Releases the software control flag for performing PHY and select
1816 * MAC CSR accesses.
1817 **/
1818static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1819{
1820 u32 extcnf_ctrl;
1821
1822 extcnf_ctrl = er32(EXTCNF_CTRL);
1823
1824 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1825 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1826 ew32(EXTCNF_CTRL, extcnf_ctrl);
1827 } else {
1828 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1829 }
1830
1831 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1832}
1833
1834/**
1835 * e1000_check_mng_mode_ich8lan - Checks management mode
1836 * @hw: pointer to the HW structure
1837 *
1838 * This checks if the adapter has any manageability enabled.
1839 * This is a function pointer entry point only called by read/write
1840 * routines for the PHY and NVM parts.
1841 **/
1842static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1843{
1844 u32 fwsm;
1845
1846 fwsm = er32(FWSM);
1847 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1848 ((fwsm & E1000_FWSM_MODE_MASK) ==
1849 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1850}
1851
1852/**
1853 * e1000_check_mng_mode_pchlan - Checks management mode
1854 * @hw: pointer to the HW structure
1855 *
1856 * This checks if the adapter has iAMT enabled.
1857 * This is a function pointer entry point only called by read/write
1858 * routines for the PHY and NVM parts.
1859 **/
1860static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1861{
1862 u32 fwsm;
1863
1864 fwsm = er32(FWSM);
1865 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1866 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1867}
1868
1869/**
1870 * e1000_rar_set_pch2lan - Set receive address register
1871 * @hw: pointer to the HW structure
1872 * @addr: pointer to the receive address
1873 * @index: receive address array register
1874 *
1875 * Sets the receive address array register at index to the address passed
1876 * in by addr. For 82579, RAR[0] is the base address register that is to
1877 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1878 * Use SHRA[0-3] in place of those reserved for ME.
1879 **/
1880static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1881{
1882 u32 rar_low, rar_high;
1883
1884 /* HW expects these in little endian so we reverse the byte order
1885 * from network order (big endian) to little endian
1886 */
1887 rar_low = ((u32)addr[0] |
1888 ((u32)addr[1] << 8) |
1889 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1890
1891 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1892
1893 /* If MAC address zero, no need to set the AV bit */
1894 if (rar_low || rar_high)
1895 rar_high |= E1000_RAH_AV;
1896
1897 if (index == 0) {
1898 ew32(RAL(index), rar_low);
1899 e1e_flush();
1900 ew32(RAH(index), rar_high);
1901 e1e_flush();
1902 return 0;
1903 }
1904
1905 /* RAR[1-6] are owned by manageability. Skip those and program the
1906 * next address into the SHRA register array.
1907 */
1908 if (index < (u32)(hw->mac.rar_entry_count)) {
1909 s32 ret_val;
1910
1911 ret_val = e1000_acquire_swflag_ich8lan(hw);
1912 if (ret_val)
1913 goto out;
1914
1915 ew32(SHRAL(index - 1), rar_low);
1916 e1e_flush();
1917 ew32(SHRAH(index - 1), rar_high);
1918 e1e_flush();
1919
1920 e1000_release_swflag_ich8lan(hw);
1921
1922 /* verify the register updates */
1923 if ((er32(SHRAL(index - 1)) == rar_low) &&
1924 (er32(SHRAH(index - 1)) == rar_high))
1925 return 0;
1926
1927 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1928 (index - 1), er32(FWSM));
1929 }
1930
1931out:
1932 e_dbg("Failed to write receive address at index %d\n", index);
1933 return -E1000_ERR_CONFIG;
1934}
1935
1936/**
1937 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1938 * @hw: pointer to the HW structure
1939 *
1940 * Get the number of available receive registers that the Host can
1941 * program. SHRA[0-10] are the shared receive address registers
1942 * that are shared between the Host and manageability engine (ME).
1943 * ME can reserve any number of addresses and the host needs to be
1944 * able to tell how many available registers it has access to.
1945 **/
1946static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1947{
1948 u32 wlock_mac;
1949 u32 num_entries;
1950
1951 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1952 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1953
1954 switch (wlock_mac) {
1955 case 0:
1956 /* All SHRA[0..10] and RAR[0] available */
1957 num_entries = hw->mac.rar_entry_count;
1958 break;
1959 case 1:
1960 /* Only RAR[0] available */
1961 num_entries = 1;
1962 break;
1963 default:
1964 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1965 num_entries = wlock_mac + 1;
1966 break;
1967 }
1968
1969 return num_entries;
1970}
1971
1972/**
1973 * e1000_rar_set_pch_lpt - Set receive address registers
1974 * @hw: pointer to the HW structure
1975 * @addr: pointer to the receive address
1976 * @index: receive address array register
1977 *
1978 * Sets the receive address register array at index to the address passed
1979 * in by addr. For LPT, RAR[0] is the base address register that is to
1980 * contain the MAC address. SHRA[0-10] are the shared receive address
1981 * registers that are shared between the Host and manageability engine (ME).
1982 **/
1983static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1984{
1985 u32 rar_low, rar_high;
1986 u32 wlock_mac;
1987
1988 /* HW expects these in little endian so we reverse the byte order
1989 * from network order (big endian) to little endian
1990 */
1991 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1992 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1993
1994 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1995
1996 /* If MAC address zero, no need to set the AV bit */
1997 if (rar_low || rar_high)
1998 rar_high |= E1000_RAH_AV;
1999
2000 if (index == 0) {
2001 ew32(RAL(index), rar_low);
2002 e1e_flush();
2003 ew32(RAH(index), rar_high);
2004 e1e_flush();
2005 return 0;
2006 }
2007
2008 /* The manageability engine (ME) can lock certain SHRAR registers that
2009 * it is using - those registers are unavailable for use.
2010 */
2011 if (index < hw->mac.rar_entry_count) {
2012 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
2013 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
2014
2015 /* Check if all SHRAR registers are locked */
2016 if (wlock_mac == 1)
2017 goto out;
2018
2019 if ((wlock_mac == 0) || (index <= wlock_mac)) {
2020 s32 ret_val;
2021
2022 ret_val = e1000_acquire_swflag_ich8lan(hw);
2023
2024 if (ret_val)
2025 goto out;
2026
2027 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
2028 e1e_flush();
2029 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
2030 e1e_flush();
2031
2032 e1000_release_swflag_ich8lan(hw);
2033
2034 /* verify the register updates */
2035 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
2036 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
2037 return 0;
2038 }
2039 }
2040
2041out:
2042 e_dbg("Failed to write receive address at index %d\n", index);
2043 return -E1000_ERR_CONFIG;
2044}
2045
2046/**
2047 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2048 * @hw: pointer to the HW structure
2049 *
2050 * Checks if firmware is blocking the reset of the PHY.
2051 * This is a function pointer entry point only called by
2052 * reset routines.
2053 **/
2054static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2055{
2056 bool blocked = false;
2057 int i = 0;
2058
2059 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2060 (i++ < 30))
2061 usleep_range(10000, 11000);
2062 return blocked ? E1000_BLK_PHY_RESET : 0;
2063}
2064
2065/**
2066 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2067 * @hw: pointer to the HW structure
2068 *
2069 * Assumes semaphore already acquired.
2070 *
2071 **/
2072static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2073{
2074 u16 phy_data;
2075 u32 strap = er32(STRAP);
2076 u32 freq = FIELD_GET(E1000_STRAP_SMT_FREQ_MASK, strap);
2077 s32 ret_val;
2078
2079 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2080
2081 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2082 if (ret_val)
2083 return ret_val;
2084
2085 phy_data &= ~HV_SMB_ADDR_MASK;
2086 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2087 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2088
2089 if (hw->phy.type == e1000_phy_i217) {
2090 /* Restore SMBus frequency */
2091 if (freq--) {
2092 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2093 phy_data |= (freq & BIT(0)) <<
2094 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2095 phy_data |= (freq & BIT(1)) <<
2096 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2097 } else {
2098 e_dbg("Unsupported SMB frequency in PHY\n");
2099 }
2100 }
2101
2102 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2103}
2104
2105/**
2106 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2107 * @hw: pointer to the HW structure
2108 *
2109 * SW should configure the LCD from the NVM extended configuration region
2110 * as a workaround for certain parts.
2111 **/
2112static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2113{
2114 struct e1000_phy_info *phy = &hw->phy;
2115 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2116 s32 ret_val = 0;
2117 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2118
2119 /* Initialize the PHY from the NVM on ICH platforms. This
2120 * is needed due to an issue where the NVM configuration is
2121 * not properly autoloaded after power transitions.
2122 * Therefore, after each PHY reset, we will load the
2123 * configuration data out of the NVM manually.
2124 */
2125 switch (hw->mac.type) {
2126 case e1000_ich8lan:
2127 if (phy->type != e1000_phy_igp_3)
2128 return ret_val;
2129
2130 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2131 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2132 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2133 break;
2134 }
2135 fallthrough;
2136 case e1000_pchlan:
2137 case e1000_pch2lan:
2138 case e1000_pch_lpt:
2139 case e1000_pch_spt:
2140 case e1000_pch_cnp:
2141 case e1000_pch_tgp:
2142 case e1000_pch_adp:
2143 case e1000_pch_mtp:
2144 case e1000_pch_lnp:
2145 case e1000_pch_ptp:
2146 case e1000_pch_nvp:
2147 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2148 break;
2149 default:
2150 return ret_val;
2151 }
2152
2153 ret_val = hw->phy.ops.acquire(hw);
2154 if (ret_val)
2155 return ret_val;
2156
2157 data = er32(FEXTNVM);
2158 if (!(data & sw_cfg_mask))
2159 goto release;
2160
2161 /* Make sure HW does not configure LCD from PHY
2162 * extended configuration before SW configuration
2163 */
2164 data = er32(EXTCNF_CTRL);
2165 if ((hw->mac.type < e1000_pch2lan) &&
2166 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2167 goto release;
2168
2169 cnf_size = er32(EXTCNF_SIZE);
2170 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2171 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2172 if (!cnf_size)
2173 goto release;
2174
2175 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2176 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2177
2178 if (((hw->mac.type == e1000_pchlan) &&
2179 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2180 (hw->mac.type > e1000_pchlan)) {
2181 /* HW configures the SMBus address and LEDs when the
2182 * OEM and LCD Write Enable bits are set in the NVM.
2183 * When both NVM bits are cleared, SW will configure
2184 * them instead.
2185 */
2186 ret_val = e1000_write_smbus_addr(hw);
2187 if (ret_val)
2188 goto release;
2189
2190 data = er32(LEDCTL);
2191 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2192 (u16)data);
2193 if (ret_val)
2194 goto release;
2195 }
2196
2197 /* Configure LCD from extended configuration region. */
2198
2199 /* cnf_base_addr is in DWORD */
2200 word_addr = (u16)(cnf_base_addr << 1);
2201
2202 for (i = 0; i < cnf_size; i++) {
2203 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
2204 if (ret_val)
2205 goto release;
2206
2207 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2208 1, ®_addr);
2209 if (ret_val)
2210 goto release;
2211
2212 /* Save off the PHY page for future writes. */
2213 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2214 phy_page = reg_data;
2215 continue;
2216 }
2217
2218 reg_addr &= PHY_REG_MASK;
2219 reg_addr |= phy_page;
2220
2221 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2222 if (ret_val)
2223 goto release;
2224 }
2225
2226release:
2227 hw->phy.ops.release(hw);
2228 return ret_val;
2229}
2230
2231/**
2232 * e1000_k1_gig_workaround_hv - K1 Si workaround
2233 * @hw: pointer to the HW structure
2234 * @link: link up bool flag
2235 *
2236 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2237 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2238 * If link is down, the function will restore the default K1 setting located
2239 * in the NVM.
2240 **/
2241static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2242{
2243 s32 ret_val = 0;
2244 u16 status_reg = 0;
2245 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2246
2247 if (hw->mac.type != e1000_pchlan)
2248 return 0;
2249
2250 /* Wrap the whole flow with the sw flag */
2251 ret_val = hw->phy.ops.acquire(hw);
2252 if (ret_val)
2253 return ret_val;
2254
2255 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2256 if (link) {
2257 if (hw->phy.type == e1000_phy_82578) {
2258 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2259 &status_reg);
2260 if (ret_val)
2261 goto release;
2262
2263 status_reg &= (BM_CS_STATUS_LINK_UP |
2264 BM_CS_STATUS_RESOLVED |
2265 BM_CS_STATUS_SPEED_MASK);
2266
2267 if (status_reg == (BM_CS_STATUS_LINK_UP |
2268 BM_CS_STATUS_RESOLVED |
2269 BM_CS_STATUS_SPEED_1000))
2270 k1_enable = false;
2271 }
2272
2273 if (hw->phy.type == e1000_phy_82577) {
2274 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2275 if (ret_val)
2276 goto release;
2277
2278 status_reg &= (HV_M_STATUS_LINK_UP |
2279 HV_M_STATUS_AUTONEG_COMPLETE |
2280 HV_M_STATUS_SPEED_MASK);
2281
2282 if (status_reg == (HV_M_STATUS_LINK_UP |
2283 HV_M_STATUS_AUTONEG_COMPLETE |
2284 HV_M_STATUS_SPEED_1000))
2285 k1_enable = false;
2286 }
2287
2288 /* Link stall fix for link up */
2289 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2290 if (ret_val)
2291 goto release;
2292
2293 } else {
2294 /* Link stall fix for link down */
2295 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2296 if (ret_val)
2297 goto release;
2298 }
2299
2300 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2301
2302release:
2303 hw->phy.ops.release(hw);
2304
2305 return ret_val;
2306}
2307
2308/**
2309 * e1000_configure_k1_ich8lan - Configure K1 power state
2310 * @hw: pointer to the HW structure
2311 * @k1_enable: K1 state to configure
2312 *
2313 * Configure the K1 power state based on the provided parameter.
2314 * Assumes semaphore already acquired.
2315 *
2316 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2317 **/
2318s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2319{
2320 s32 ret_val;
2321 u32 ctrl_reg = 0;
2322 u32 ctrl_ext = 0;
2323 u32 reg = 0;
2324 u16 kmrn_reg = 0;
2325
2326 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2327 &kmrn_reg);
2328 if (ret_val)
2329 return ret_val;
2330
2331 if (k1_enable)
2332 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2333 else
2334 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2335
2336 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2337 kmrn_reg);
2338 if (ret_val)
2339 return ret_val;
2340
2341 usleep_range(20, 40);
2342 ctrl_ext = er32(CTRL_EXT);
2343 ctrl_reg = er32(CTRL);
2344
2345 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2346 reg |= E1000_CTRL_FRCSPD;
2347 ew32(CTRL, reg);
2348
2349 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2350 e1e_flush();
2351 usleep_range(20, 40);
2352 ew32(CTRL, ctrl_reg);
2353 ew32(CTRL_EXT, ctrl_ext);
2354 e1e_flush();
2355 usleep_range(20, 40);
2356
2357 return 0;
2358}
2359
2360/**
2361 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2362 * @hw: pointer to the HW structure
2363 * @d0_state: boolean if entering d0 or d3 device state
2364 *
2365 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2366 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2367 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2368 **/
2369static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2370{
2371 s32 ret_val = 0;
2372 u32 mac_reg;
2373 u16 oem_reg;
2374
2375 if (hw->mac.type < e1000_pchlan)
2376 return ret_val;
2377
2378 ret_val = hw->phy.ops.acquire(hw);
2379 if (ret_val)
2380 return ret_val;
2381
2382 if (hw->mac.type == e1000_pchlan) {
2383 mac_reg = er32(EXTCNF_CTRL);
2384 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2385 goto release;
2386 }
2387
2388 mac_reg = er32(FEXTNVM);
2389 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2390 goto release;
2391
2392 mac_reg = er32(PHY_CTRL);
2393
2394 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2395 if (ret_val)
2396 goto release;
2397
2398 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2399
2400 if (d0_state) {
2401 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2402 oem_reg |= HV_OEM_BITS_GBE_DIS;
2403
2404 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2405 oem_reg |= HV_OEM_BITS_LPLU;
2406 } else {
2407 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2408 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2409 oem_reg |= HV_OEM_BITS_GBE_DIS;
2410
2411 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2412 E1000_PHY_CTRL_NOND0A_LPLU))
2413 oem_reg |= HV_OEM_BITS_LPLU;
2414 }
2415
2416 /* Set Restart auto-neg to activate the bits */
2417 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2418 !hw->phy.ops.check_reset_block(hw))
2419 oem_reg |= HV_OEM_BITS_RESTART_AN;
2420
2421 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2422
2423release:
2424 hw->phy.ops.release(hw);
2425
2426 return ret_val;
2427}
2428
2429/**
2430 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2431 * @hw: pointer to the HW structure
2432 **/
2433static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2434{
2435 s32 ret_val;
2436 u16 data;
2437
2438 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2439 if (ret_val)
2440 return ret_val;
2441
2442 data |= HV_KMRN_MDIO_SLOW;
2443
2444 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2445
2446 return ret_val;
2447}
2448
2449/**
2450 * e1000_hv_phy_workarounds_ich8lan - apply PHY workarounds
2451 * @hw: pointer to the HW structure
2452 *
2453 * A series of PHY workarounds to be done after every PHY reset.
2454 **/
2455static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2456{
2457 s32 ret_val = 0;
2458 u16 phy_data;
2459
2460 if (hw->mac.type != e1000_pchlan)
2461 return 0;
2462
2463 /* Set MDIO slow mode before any other MDIO access */
2464 if (hw->phy.type == e1000_phy_82577) {
2465 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2466 if (ret_val)
2467 return ret_val;
2468 }
2469
2470 if (((hw->phy.type == e1000_phy_82577) &&
2471 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2472 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2473 /* Disable generation of early preamble */
2474 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2475 if (ret_val)
2476 return ret_val;
2477
2478 /* Preamble tuning for SSC */
2479 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2480 if (ret_val)
2481 return ret_val;
2482 }
2483
2484 if (hw->phy.type == e1000_phy_82578) {
2485 /* Return registers to default by doing a soft reset then
2486 * writing 0x3140 to the control register.
2487 */
2488 if (hw->phy.revision < 2) {
2489 e1000e_phy_sw_reset(hw);
2490 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2491 if (ret_val)
2492 return ret_val;
2493 }
2494 }
2495
2496 /* Select page 0 */
2497 ret_val = hw->phy.ops.acquire(hw);
2498 if (ret_val)
2499 return ret_val;
2500
2501 hw->phy.addr = 1;
2502 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2503 hw->phy.ops.release(hw);
2504 if (ret_val)
2505 return ret_val;
2506
2507 /* Configure the K1 Si workaround during phy reset assuming there is
2508 * link so that it disables K1 if link is in 1Gbps.
2509 */
2510 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2511 if (ret_val)
2512 return ret_val;
2513
2514 /* Workaround for link disconnects on a busy hub in half duplex */
2515 ret_val = hw->phy.ops.acquire(hw);
2516 if (ret_val)
2517 return ret_val;
2518 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2519 if (ret_val)
2520 goto release;
2521 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2522 if (ret_val)
2523 goto release;
2524
2525 /* set MSE higher to enable link to stay up when noise is high */
2526 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2527release:
2528 hw->phy.ops.release(hw);
2529
2530 return ret_val;
2531}
2532
2533/**
2534 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2535 * @hw: pointer to the HW structure
2536 **/
2537void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2538{
2539 u32 mac_reg;
2540 u16 i, phy_reg = 0;
2541 s32 ret_val;
2542
2543 ret_val = hw->phy.ops.acquire(hw);
2544 if (ret_val)
2545 return;
2546 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2547 if (ret_val)
2548 goto release;
2549
2550 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2551 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2552 mac_reg = er32(RAL(i));
2553 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2554 (u16)(mac_reg & 0xFFFF));
2555 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2556 (u16)((mac_reg >> 16) & 0xFFFF));
2557
2558 mac_reg = er32(RAH(i));
2559 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2560 (u16)(mac_reg & 0xFFFF));
2561 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2562 (u16)((mac_reg & E1000_RAH_AV) >> 16));
2563 }
2564
2565 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2566
2567release:
2568 hw->phy.ops.release(hw);
2569}
2570
2571/**
2572 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2573 * with 82579 PHY
2574 * @hw: pointer to the HW structure
2575 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2576 **/
2577s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2578{
2579 s32 ret_val = 0;
2580 u16 phy_reg, data;
2581 u32 mac_reg;
2582 u16 i;
2583
2584 if (hw->mac.type < e1000_pch2lan)
2585 return 0;
2586
2587 /* disable Rx path while enabling/disabling workaround */
2588 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2589 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2590 if (ret_val)
2591 return ret_val;
2592
2593 if (enable) {
2594 /* Write Rx addresses (rar_entry_count for RAL/H, and
2595 * SHRAL/H) and initial CRC values to the MAC
2596 */
2597 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2598 u8 mac_addr[ETH_ALEN] = { 0 };
2599 u32 addr_high, addr_low;
2600
2601 addr_high = er32(RAH(i));
2602 if (!(addr_high & E1000_RAH_AV))
2603 continue;
2604 addr_low = er32(RAL(i));
2605 mac_addr[0] = (addr_low & 0xFF);
2606 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2607 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2608 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2609 mac_addr[4] = (addr_high & 0xFF);
2610 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2611
2612 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2613 }
2614
2615 /* Write Rx addresses to the PHY */
2616 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2617
2618 /* Enable jumbo frame workaround in the MAC */
2619 mac_reg = er32(FFLT_DBG);
2620 mac_reg &= ~BIT(14);
2621 mac_reg |= (7 << 15);
2622 ew32(FFLT_DBG, mac_reg);
2623
2624 mac_reg = er32(RCTL);
2625 mac_reg |= E1000_RCTL_SECRC;
2626 ew32(RCTL, mac_reg);
2627
2628 ret_val = e1000e_read_kmrn_reg(hw,
2629 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2630 &data);
2631 if (ret_val)
2632 return ret_val;
2633 ret_val = e1000e_write_kmrn_reg(hw,
2634 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2635 data | BIT(0));
2636 if (ret_val)
2637 return ret_val;
2638 ret_val = e1000e_read_kmrn_reg(hw,
2639 E1000_KMRNCTRLSTA_HD_CTRL,
2640 &data);
2641 if (ret_val)
2642 return ret_val;
2643 data &= ~(0xF << 8);
2644 data |= (0xB << 8);
2645 ret_val = e1000e_write_kmrn_reg(hw,
2646 E1000_KMRNCTRLSTA_HD_CTRL,
2647 data);
2648 if (ret_val)
2649 return ret_val;
2650
2651 /* Enable jumbo frame workaround in the PHY */
2652 e1e_rphy(hw, PHY_REG(769, 23), &data);
2653 data &= ~(0x7F << 5);
2654 data |= (0x37 << 5);
2655 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2656 if (ret_val)
2657 return ret_val;
2658 e1e_rphy(hw, PHY_REG(769, 16), &data);
2659 data &= ~BIT(13);
2660 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2661 if (ret_val)
2662 return ret_val;
2663 e1e_rphy(hw, PHY_REG(776, 20), &data);
2664 data &= ~(0x3FF << 2);
2665 data |= (E1000_TX_PTR_GAP << 2);
2666 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2667 if (ret_val)
2668 return ret_val;
2669 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2670 if (ret_val)
2671 return ret_val;
2672 e1e_rphy(hw, HV_PM_CTRL, &data);
2673 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2674 if (ret_val)
2675 return ret_val;
2676 } else {
2677 /* Write MAC register values back to h/w defaults */
2678 mac_reg = er32(FFLT_DBG);
2679 mac_reg &= ~(0xF << 14);
2680 ew32(FFLT_DBG, mac_reg);
2681
2682 mac_reg = er32(RCTL);
2683 mac_reg &= ~E1000_RCTL_SECRC;
2684 ew32(RCTL, mac_reg);
2685
2686 ret_val = e1000e_read_kmrn_reg(hw,
2687 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2688 &data);
2689 if (ret_val)
2690 return ret_val;
2691 ret_val = e1000e_write_kmrn_reg(hw,
2692 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2693 data & ~BIT(0));
2694 if (ret_val)
2695 return ret_val;
2696 ret_val = e1000e_read_kmrn_reg(hw,
2697 E1000_KMRNCTRLSTA_HD_CTRL,
2698 &data);
2699 if (ret_val)
2700 return ret_val;
2701 data &= ~(0xF << 8);
2702 data |= (0xB << 8);
2703 ret_val = e1000e_write_kmrn_reg(hw,
2704 E1000_KMRNCTRLSTA_HD_CTRL,
2705 data);
2706 if (ret_val)
2707 return ret_val;
2708
2709 /* Write PHY register values back to h/w defaults */
2710 e1e_rphy(hw, PHY_REG(769, 23), &data);
2711 data &= ~(0x7F << 5);
2712 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2713 if (ret_val)
2714 return ret_val;
2715 e1e_rphy(hw, PHY_REG(769, 16), &data);
2716 data |= BIT(13);
2717 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2718 if (ret_val)
2719 return ret_val;
2720 e1e_rphy(hw, PHY_REG(776, 20), &data);
2721 data &= ~(0x3FF << 2);
2722 data |= (0x8 << 2);
2723 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2724 if (ret_val)
2725 return ret_val;
2726 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2727 if (ret_val)
2728 return ret_val;
2729 e1e_rphy(hw, HV_PM_CTRL, &data);
2730 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2731 if (ret_val)
2732 return ret_val;
2733 }
2734
2735 /* re-enable Rx path after enabling/disabling workaround */
2736 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2737}
2738
2739/**
2740 * e1000_lv_phy_workarounds_ich8lan - apply ich8 specific workarounds
2741 * @hw: pointer to the HW structure
2742 *
2743 * A series of PHY workarounds to be done after every PHY reset.
2744 **/
2745static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2746{
2747 s32 ret_val = 0;
2748
2749 if (hw->mac.type != e1000_pch2lan)
2750 return 0;
2751
2752 /* Set MDIO slow mode before any other MDIO access */
2753 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2754 if (ret_val)
2755 return ret_val;
2756
2757 ret_val = hw->phy.ops.acquire(hw);
2758 if (ret_val)
2759 return ret_val;
2760 /* set MSE higher to enable link to stay up when noise is high */
2761 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2762 if (ret_val)
2763 goto release;
2764 /* drop link after 5 times MSE threshold was reached */
2765 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2766release:
2767 hw->phy.ops.release(hw);
2768
2769 return ret_val;
2770}
2771
2772/**
2773 * e1000_k1_workaround_lv - K1 Si workaround
2774 * @hw: pointer to the HW structure
2775 *
2776 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2777 * Disable K1 in 1000Mbps and 100Mbps
2778 **/
2779static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2780{
2781 s32 ret_val = 0;
2782 u16 status_reg = 0;
2783
2784 if (hw->mac.type != e1000_pch2lan)
2785 return 0;
2786
2787 /* Set K1 beacon duration based on 10Mbs speed */
2788 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2789 if (ret_val)
2790 return ret_val;
2791
2792 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2793 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2794 if (status_reg &
2795 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2796 u16 pm_phy_reg;
2797
2798 /* LV 1G/100 Packet drop issue wa */
2799 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2800 if (ret_val)
2801 return ret_val;
2802 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2803 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2804 if (ret_val)
2805 return ret_val;
2806 } else {
2807 u32 mac_reg;
2808
2809 mac_reg = er32(FEXTNVM4);
2810 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2811 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2812 ew32(FEXTNVM4, mac_reg);
2813 }
2814 }
2815
2816 return ret_val;
2817}
2818
2819/**
2820 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2821 * @hw: pointer to the HW structure
2822 * @gate: boolean set to true to gate, false to ungate
2823 *
2824 * Gate/ungate the automatic PHY configuration via hardware; perform
2825 * the configuration via software instead.
2826 **/
2827static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2828{
2829 u32 extcnf_ctrl;
2830
2831 if (hw->mac.type < e1000_pch2lan)
2832 return;
2833
2834 extcnf_ctrl = er32(EXTCNF_CTRL);
2835
2836 if (gate)
2837 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2838 else
2839 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2840
2841 ew32(EXTCNF_CTRL, extcnf_ctrl);
2842}
2843
2844/**
2845 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2846 * @hw: pointer to the HW structure
2847 *
2848 * Check the appropriate indication the MAC has finished configuring the
2849 * PHY after a software reset.
2850 **/
2851static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2852{
2853 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2854
2855 /* Wait for basic configuration completes before proceeding */
2856 do {
2857 data = er32(STATUS);
2858 data &= E1000_STATUS_LAN_INIT_DONE;
2859 usleep_range(100, 200);
2860 } while ((!data) && --loop);
2861
2862 /* If basic configuration is incomplete before the above loop
2863 * count reaches 0, loading the configuration from NVM will
2864 * leave the PHY in a bad state possibly resulting in no link.
2865 */
2866 if (loop == 0)
2867 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2868
2869 /* Clear the Init Done bit for the next init event */
2870 data = er32(STATUS);
2871 data &= ~E1000_STATUS_LAN_INIT_DONE;
2872 ew32(STATUS, data);
2873}
2874
2875/**
2876 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2877 * @hw: pointer to the HW structure
2878 **/
2879static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2880{
2881 s32 ret_val = 0;
2882 u16 reg;
2883
2884 if (hw->phy.ops.check_reset_block(hw))
2885 return 0;
2886
2887 /* Allow time for h/w to get to quiescent state after reset */
2888 usleep_range(10000, 11000);
2889
2890 /* Perform any necessary post-reset workarounds */
2891 switch (hw->mac.type) {
2892 case e1000_pchlan:
2893 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2894 if (ret_val)
2895 return ret_val;
2896 break;
2897 case e1000_pch2lan:
2898 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2899 if (ret_val)
2900 return ret_val;
2901 break;
2902 default:
2903 break;
2904 }
2905
2906 /* Clear the host wakeup bit after lcd reset */
2907 if (hw->mac.type >= e1000_pchlan) {
2908 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
2909 reg &= ~BM_WUC_HOST_WU_BIT;
2910 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2911 }
2912
2913 /* Configure the LCD with the extended configuration region in NVM */
2914 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2915 if (ret_val)
2916 return ret_val;
2917
2918 /* Configure the LCD with the OEM bits in NVM */
2919 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2920
2921 if (hw->mac.type == e1000_pch2lan) {
2922 /* Ungate automatic PHY configuration on non-managed 82579 */
2923 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2924 usleep_range(10000, 11000);
2925 e1000_gate_hw_phy_config_ich8lan(hw, false);
2926 }
2927
2928 /* Set EEE LPI Update Timer to 200usec */
2929 ret_val = hw->phy.ops.acquire(hw);
2930 if (ret_val)
2931 return ret_val;
2932 ret_val = e1000_write_emi_reg_locked(hw,
2933 I82579_LPI_UPDATE_TIMER,
2934 0x1387);
2935 hw->phy.ops.release(hw);
2936 }
2937
2938 return ret_val;
2939}
2940
2941/**
2942 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2943 * @hw: pointer to the HW structure
2944 *
2945 * Resets the PHY
2946 * This is a function pointer entry point called by drivers
2947 * or other shared routines.
2948 **/
2949static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2950{
2951 s32 ret_val = 0;
2952
2953 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2954 if ((hw->mac.type == e1000_pch2lan) &&
2955 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2956 e1000_gate_hw_phy_config_ich8lan(hw, true);
2957
2958 ret_val = e1000e_phy_hw_reset_generic(hw);
2959 if (ret_val)
2960 return ret_val;
2961
2962 return e1000_post_phy_reset_ich8lan(hw);
2963}
2964
2965/**
2966 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2967 * @hw: pointer to the HW structure
2968 * @active: true to enable LPLU, false to disable
2969 *
2970 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2971 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2972 * the phy speed. This function will manually set the LPLU bit and restart
2973 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2974 * since it configures the same bit.
2975 **/
2976static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2977{
2978 s32 ret_val;
2979 u16 oem_reg;
2980
2981 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2982 if (ret_val)
2983 return ret_val;
2984
2985 if (active)
2986 oem_reg |= HV_OEM_BITS_LPLU;
2987 else
2988 oem_reg &= ~HV_OEM_BITS_LPLU;
2989
2990 if (!hw->phy.ops.check_reset_block(hw))
2991 oem_reg |= HV_OEM_BITS_RESTART_AN;
2992
2993 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2994}
2995
2996/**
2997 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2998 * @hw: pointer to the HW structure
2999 * @active: true to enable LPLU, false to disable
3000 *
3001 * Sets the LPLU D0 state according to the active flag. When
3002 * activating LPLU this function also disables smart speed
3003 * and vice versa. LPLU will not be activated unless the
3004 * device autonegotiation advertisement meets standards of
3005 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3006 * This is a function pointer entry point only called by
3007 * PHY setup routines.
3008 **/
3009static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3010{
3011 struct e1000_phy_info *phy = &hw->phy;
3012 u32 phy_ctrl;
3013 s32 ret_val = 0;
3014 u16 data;
3015
3016 if (phy->type == e1000_phy_ife)
3017 return 0;
3018
3019 phy_ctrl = er32(PHY_CTRL);
3020
3021 if (active) {
3022 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
3023 ew32(PHY_CTRL, phy_ctrl);
3024
3025 if (phy->type != e1000_phy_igp_3)
3026 return 0;
3027
3028 /* Call gig speed drop workaround on LPLU before accessing
3029 * any PHY registers
3030 */
3031 if (hw->mac.type == e1000_ich8lan)
3032 e1000e_gig_downshift_workaround_ich8lan(hw);
3033
3034 /* When LPLU is enabled, we should disable SmartSpeed */
3035 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3036 if (ret_val)
3037 return ret_val;
3038 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3039 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3040 if (ret_val)
3041 return ret_val;
3042 } else {
3043 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
3044 ew32(PHY_CTRL, phy_ctrl);
3045
3046 if (phy->type != e1000_phy_igp_3)
3047 return 0;
3048
3049 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3050 * during Dx states where the power conservation is most
3051 * important. During driver activity we should enable
3052 * SmartSpeed, so performance is maintained.
3053 */
3054 if (phy->smart_speed == e1000_smart_speed_on) {
3055 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3056 &data);
3057 if (ret_val)
3058 return ret_val;
3059
3060 data |= IGP01E1000_PSCFR_SMART_SPEED;
3061 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3062 data);
3063 if (ret_val)
3064 return ret_val;
3065 } else if (phy->smart_speed == e1000_smart_speed_off) {
3066 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3067 &data);
3068 if (ret_val)
3069 return ret_val;
3070
3071 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3072 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3073 data);
3074 if (ret_val)
3075 return ret_val;
3076 }
3077 }
3078
3079 return 0;
3080}
3081
3082/**
3083 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3084 * @hw: pointer to the HW structure
3085 * @active: true to enable LPLU, false to disable
3086 *
3087 * Sets the LPLU D3 state according to the active flag. When
3088 * activating LPLU this function also disables smart speed
3089 * and vice versa. LPLU will not be activated unless the
3090 * device autonegotiation advertisement meets standards of
3091 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3092 * This is a function pointer entry point only called by
3093 * PHY setup routines.
3094 **/
3095static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3096{
3097 struct e1000_phy_info *phy = &hw->phy;
3098 u32 phy_ctrl;
3099 s32 ret_val = 0;
3100 u16 data;
3101
3102 phy_ctrl = er32(PHY_CTRL);
3103
3104 if (!active) {
3105 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3106 ew32(PHY_CTRL, phy_ctrl);
3107
3108 if (phy->type != e1000_phy_igp_3)
3109 return 0;
3110
3111 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3112 * during Dx states where the power conservation is most
3113 * important. During driver activity we should enable
3114 * SmartSpeed, so performance is maintained.
3115 */
3116 if (phy->smart_speed == e1000_smart_speed_on) {
3117 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3118 &data);
3119 if (ret_val)
3120 return ret_val;
3121
3122 data |= IGP01E1000_PSCFR_SMART_SPEED;
3123 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3124 data);
3125 if (ret_val)
3126 return ret_val;
3127 } else if (phy->smart_speed == e1000_smart_speed_off) {
3128 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3129 &data);
3130 if (ret_val)
3131 return ret_val;
3132
3133 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3134 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3135 data);
3136 if (ret_val)
3137 return ret_val;
3138 }
3139 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3140 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3141 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3142 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3143 ew32(PHY_CTRL, phy_ctrl);
3144
3145 if (phy->type != e1000_phy_igp_3)
3146 return 0;
3147
3148 /* Call gig speed drop workaround on LPLU before accessing
3149 * any PHY registers
3150 */
3151 if (hw->mac.type == e1000_ich8lan)
3152 e1000e_gig_downshift_workaround_ich8lan(hw);
3153
3154 /* When LPLU is enabled, we should disable SmartSpeed */
3155 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3156 if (ret_val)
3157 return ret_val;
3158
3159 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3160 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3161 }
3162
3163 return ret_val;
3164}
3165
3166/**
3167 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3168 * @hw: pointer to the HW structure
3169 * @bank: pointer to the variable that returns the active bank
3170 *
3171 * Reads signature byte from the NVM using the flash access registers.
3172 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3173 **/
3174static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3175{
3176 u32 eecd;
3177 struct e1000_nvm_info *nvm = &hw->nvm;
3178 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3179 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3180 u32 nvm_dword = 0;
3181 u8 sig_byte = 0;
3182 s32 ret_val;
3183
3184 switch (hw->mac.type) {
3185 case e1000_pch_spt:
3186 case e1000_pch_cnp:
3187 case e1000_pch_tgp:
3188 case e1000_pch_adp:
3189 case e1000_pch_mtp:
3190 case e1000_pch_lnp:
3191 case e1000_pch_ptp:
3192 case e1000_pch_nvp:
3193 bank1_offset = nvm->flash_bank_size;
3194 act_offset = E1000_ICH_NVM_SIG_WORD;
3195
3196 /* set bank to 0 in case flash read fails */
3197 *bank = 0;
3198
3199 /* Check bank 0 */
3200 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3201 &nvm_dword);
3202 if (ret_val)
3203 return ret_val;
3204 sig_byte = FIELD_GET(0xFF00, nvm_dword);
3205 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3206 E1000_ICH_NVM_SIG_VALUE) {
3207 *bank = 0;
3208 return 0;
3209 }
3210
3211 /* Check bank 1 */
3212 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3213 bank1_offset,
3214 &nvm_dword);
3215 if (ret_val)
3216 return ret_val;
3217 sig_byte = FIELD_GET(0xFF00, nvm_dword);
3218 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3219 E1000_ICH_NVM_SIG_VALUE) {
3220 *bank = 1;
3221 return 0;
3222 }
3223
3224 e_dbg("ERROR: No valid NVM bank present\n");
3225 return -E1000_ERR_NVM;
3226 case e1000_ich8lan:
3227 case e1000_ich9lan:
3228 eecd = er32(EECD);
3229 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3230 E1000_EECD_SEC1VAL_VALID_MASK) {
3231 if (eecd & E1000_EECD_SEC1VAL)
3232 *bank = 1;
3233 else
3234 *bank = 0;
3235
3236 return 0;
3237 }
3238 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3239 fallthrough;
3240 default:
3241 /* set bank to 0 in case flash read fails */
3242 *bank = 0;
3243
3244 /* Check bank 0 */
3245 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3246 &sig_byte);
3247 if (ret_val)
3248 return ret_val;
3249 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3250 E1000_ICH_NVM_SIG_VALUE) {
3251 *bank = 0;
3252 return 0;
3253 }
3254
3255 /* Check bank 1 */
3256 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3257 bank1_offset,
3258 &sig_byte);
3259 if (ret_val)
3260 return ret_val;
3261 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3262 E1000_ICH_NVM_SIG_VALUE) {
3263 *bank = 1;
3264 return 0;
3265 }
3266
3267 e_dbg("ERROR: No valid NVM bank present\n");
3268 return -E1000_ERR_NVM;
3269 }
3270}
3271
3272/**
3273 * e1000_read_nvm_spt - NVM access for SPT
3274 * @hw: pointer to the HW structure
3275 * @offset: The offset (in bytes) of the word(s) to read.
3276 * @words: Size of data to read in words.
3277 * @data: pointer to the word(s) to read at offset.
3278 *
3279 * Reads a word(s) from the NVM
3280 **/
3281static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3282 u16 *data)
3283{
3284 struct e1000_nvm_info *nvm = &hw->nvm;
3285 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3286 u32 act_offset;
3287 s32 ret_val = 0;
3288 u32 bank = 0;
3289 u32 dword = 0;
3290 u16 offset_to_read;
3291 u16 i;
3292
3293 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3294 (words == 0)) {
3295 e_dbg("nvm parameter(s) out of bounds\n");
3296 ret_val = -E1000_ERR_NVM;
3297 goto out;
3298 }
3299
3300 nvm->ops.acquire(hw);
3301
3302 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3303 if (ret_val) {
3304 e_dbg("Could not detect valid bank, assuming bank 0\n");
3305 bank = 0;
3306 }
3307
3308 act_offset = (bank) ? nvm->flash_bank_size : 0;
3309 act_offset += offset;
3310
3311 ret_val = 0;
3312
3313 for (i = 0; i < words; i += 2) {
3314 if (words - i == 1) {
3315 if (dev_spec->shadow_ram[offset + i].modified) {
3316 data[i] =
3317 dev_spec->shadow_ram[offset + i].value;
3318 } else {
3319 offset_to_read = act_offset + i -
3320 ((act_offset + i) % 2);
3321 ret_val =
3322 e1000_read_flash_dword_ich8lan(hw,
3323 offset_to_read,
3324 &dword);
3325 if (ret_val)
3326 break;
3327 if ((act_offset + i) % 2 == 0)
3328 data[i] = (u16)(dword & 0xFFFF);
3329 else
3330 data[i] = (u16)((dword >> 16) & 0xFFFF);
3331 }
3332 } else {
3333 offset_to_read = act_offset + i;
3334 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3335 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3336 ret_val =
3337 e1000_read_flash_dword_ich8lan(hw,
3338 offset_to_read,
3339 &dword);
3340 if (ret_val)
3341 break;
3342 }
3343 if (dev_spec->shadow_ram[offset + i].modified)
3344 data[i] =
3345 dev_spec->shadow_ram[offset + i].value;
3346 else
3347 data[i] = (u16)(dword & 0xFFFF);
3348 if (dev_spec->shadow_ram[offset + i].modified)
3349 data[i + 1] =
3350 dev_spec->shadow_ram[offset + i + 1].value;
3351 else
3352 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3353 }
3354 }
3355
3356 nvm->ops.release(hw);
3357
3358out:
3359 if (ret_val)
3360 e_dbg("NVM read error: %d\n", ret_val);
3361
3362 return ret_val;
3363}
3364
3365/**
3366 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3367 * @hw: pointer to the HW structure
3368 * @offset: The offset (in bytes) of the word(s) to read.
3369 * @words: Size of data to read in words
3370 * @data: Pointer to the word(s) to read at offset.
3371 *
3372 * Reads a word(s) from the NVM using the flash access registers.
3373 **/
3374static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3375 u16 *data)
3376{
3377 struct e1000_nvm_info *nvm = &hw->nvm;
3378 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3379 u32 act_offset;
3380 s32 ret_val = 0;
3381 u32 bank = 0;
3382 u16 i, word;
3383
3384 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3385 (words == 0)) {
3386 e_dbg("nvm parameter(s) out of bounds\n");
3387 ret_val = -E1000_ERR_NVM;
3388 goto out;
3389 }
3390
3391 nvm->ops.acquire(hw);
3392
3393 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3394 if (ret_val) {
3395 e_dbg("Could not detect valid bank, assuming bank 0\n");
3396 bank = 0;
3397 }
3398
3399 act_offset = (bank) ? nvm->flash_bank_size : 0;
3400 act_offset += offset;
3401
3402 ret_val = 0;
3403 for (i = 0; i < words; i++) {
3404 if (dev_spec->shadow_ram[offset + i].modified) {
3405 data[i] = dev_spec->shadow_ram[offset + i].value;
3406 } else {
3407 ret_val = e1000_read_flash_word_ich8lan(hw,
3408 act_offset + i,
3409 &word);
3410 if (ret_val)
3411 break;
3412 data[i] = word;
3413 }
3414 }
3415
3416 nvm->ops.release(hw);
3417
3418out:
3419 if (ret_val)
3420 e_dbg("NVM read error: %d\n", ret_val);
3421
3422 return ret_val;
3423}
3424
3425/**
3426 * e1000_flash_cycle_init_ich8lan - Initialize flash
3427 * @hw: pointer to the HW structure
3428 *
3429 * This function does initial flash setup so that a new read/write/erase cycle
3430 * can be started.
3431 **/
3432static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3433{
3434 union ich8_hws_flash_status hsfsts;
3435 s32 ret_val = -E1000_ERR_NVM;
3436
3437 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3438
3439 /* Check if the flash descriptor is valid */
3440 if (!hsfsts.hsf_status.fldesvalid) {
3441 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3442 return -E1000_ERR_NVM;
3443 }
3444
3445 /* Clear FCERR and DAEL in hw status by writing 1 */
3446 hsfsts.hsf_status.flcerr = 1;
3447 hsfsts.hsf_status.dael = 1;
3448 if (hw->mac.type >= e1000_pch_spt)
3449 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3450 else
3451 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3452
3453 /* Either we should have a hardware SPI cycle in progress
3454 * bit to check against, in order to start a new cycle or
3455 * FDONE bit should be changed in the hardware so that it
3456 * is 1 after hardware reset, which can then be used as an
3457 * indication whether a cycle is in progress or has been
3458 * completed.
3459 */
3460
3461 if (!hsfsts.hsf_status.flcinprog) {
3462 /* There is no cycle running at present,
3463 * so we can start a cycle.
3464 * Begin by setting Flash Cycle Done.
3465 */
3466 hsfsts.hsf_status.flcdone = 1;
3467 if (hw->mac.type >= e1000_pch_spt)
3468 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3469 else
3470 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3471 ret_val = 0;
3472 } else {
3473 s32 i;
3474
3475 /* Otherwise poll for sometime so the current
3476 * cycle has a chance to end before giving up.
3477 */
3478 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3479 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3480 if (!hsfsts.hsf_status.flcinprog) {
3481 ret_val = 0;
3482 break;
3483 }
3484 udelay(1);
3485 }
3486 if (!ret_val) {
3487 /* Successful in waiting for previous cycle to timeout,
3488 * now set the Flash Cycle Done.
3489 */
3490 hsfsts.hsf_status.flcdone = 1;
3491 if (hw->mac.type >= e1000_pch_spt)
3492 ew32flash(ICH_FLASH_HSFSTS,
3493 hsfsts.regval & 0xFFFF);
3494 else
3495 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3496 } else {
3497 e_dbg("Flash controller busy, cannot get access\n");
3498 }
3499 }
3500
3501 return ret_val;
3502}
3503
3504/**
3505 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3506 * @hw: pointer to the HW structure
3507 * @timeout: maximum time to wait for completion
3508 *
3509 * This function starts a flash cycle and waits for its completion.
3510 **/
3511static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3512{
3513 union ich8_hws_flash_ctrl hsflctl;
3514 union ich8_hws_flash_status hsfsts;
3515 u32 i = 0;
3516
3517 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3518 if (hw->mac.type >= e1000_pch_spt)
3519 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3520 else
3521 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3522 hsflctl.hsf_ctrl.flcgo = 1;
3523
3524 if (hw->mac.type >= e1000_pch_spt)
3525 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3526 else
3527 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3528
3529 /* wait till FDONE bit is set to 1 */
3530 do {
3531 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3532 if (hsfsts.hsf_status.flcdone)
3533 break;
3534 udelay(1);
3535 } while (i++ < timeout);
3536
3537 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3538 return 0;
3539
3540 return -E1000_ERR_NVM;
3541}
3542
3543/**
3544 * e1000_read_flash_dword_ich8lan - Read dword from flash
3545 * @hw: pointer to the HW structure
3546 * @offset: offset to data location
3547 * @data: pointer to the location for storing the data
3548 *
3549 * Reads the flash dword at offset into data. Offset is converted
3550 * to bytes before read.
3551 **/
3552static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3553 u32 *data)
3554{
3555 /* Must convert word offset into bytes. */
3556 offset <<= 1;
3557 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3558}
3559
3560/**
3561 * e1000_read_flash_word_ich8lan - Read word from flash
3562 * @hw: pointer to the HW structure
3563 * @offset: offset to data location
3564 * @data: pointer to the location for storing the data
3565 *
3566 * Reads the flash word at offset into data. Offset is converted
3567 * to bytes before read.
3568 **/
3569static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3570 u16 *data)
3571{
3572 /* Must convert offset into bytes. */
3573 offset <<= 1;
3574
3575 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3576}
3577
3578/**
3579 * e1000_read_flash_byte_ich8lan - Read byte from flash
3580 * @hw: pointer to the HW structure
3581 * @offset: The offset of the byte to read.
3582 * @data: Pointer to a byte to store the value read.
3583 *
3584 * Reads a single byte from the NVM using the flash access registers.
3585 **/
3586static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3587 u8 *data)
3588{
3589 s32 ret_val;
3590 u16 word = 0;
3591
3592 /* In SPT, only 32 bits access is supported,
3593 * so this function should not be called.
3594 */
3595 if (hw->mac.type >= e1000_pch_spt)
3596 return -E1000_ERR_NVM;
3597 else
3598 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3599
3600 if (ret_val)
3601 return ret_val;
3602
3603 *data = (u8)word;
3604
3605 return 0;
3606}
3607
3608/**
3609 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3610 * @hw: pointer to the HW structure
3611 * @offset: The offset (in bytes) of the byte or word to read.
3612 * @size: Size of data to read, 1=byte 2=word
3613 * @data: Pointer to the word to store the value read.
3614 *
3615 * Reads a byte or word from the NVM using the flash access registers.
3616 **/
3617static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3618 u8 size, u16 *data)
3619{
3620 union ich8_hws_flash_status hsfsts;
3621 union ich8_hws_flash_ctrl hsflctl;
3622 u32 flash_linear_addr;
3623 u32 flash_data = 0;
3624 s32 ret_val = -E1000_ERR_NVM;
3625 u8 count = 0;
3626
3627 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3628 return -E1000_ERR_NVM;
3629
3630 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3631 hw->nvm.flash_base_addr);
3632
3633 do {
3634 udelay(1);
3635 /* Steps */
3636 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3637 if (ret_val)
3638 break;
3639
3640 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3641 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3642 hsflctl.hsf_ctrl.fldbcount = size - 1;
3643 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3644 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3645
3646 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3647
3648 ret_val =
3649 e1000_flash_cycle_ich8lan(hw,
3650 ICH_FLASH_READ_COMMAND_TIMEOUT);
3651
3652 /* Check if FCERR is set to 1, if set to 1, clear it
3653 * and try the whole sequence a few more times, else
3654 * read in (shift in) the Flash Data0, the order is
3655 * least significant byte first msb to lsb
3656 */
3657 if (!ret_val) {
3658 flash_data = er32flash(ICH_FLASH_FDATA0);
3659 if (size == 1)
3660 *data = (u8)(flash_data & 0x000000FF);
3661 else if (size == 2)
3662 *data = (u16)(flash_data & 0x0000FFFF);
3663 break;
3664 } else {
3665 /* If we've gotten here, then things are probably
3666 * completely hosed, but if the error condition is
3667 * detected, it won't hurt to give it another try...
3668 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3669 */
3670 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3671 if (hsfsts.hsf_status.flcerr) {
3672 /* Repeat for some time before giving up. */
3673 continue;
3674 } else if (!hsfsts.hsf_status.flcdone) {
3675 e_dbg("Timeout error - flash cycle did not complete.\n");
3676 break;
3677 }
3678 }
3679 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3680
3681 return ret_val;
3682}
3683
3684/**
3685 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3686 * @hw: pointer to the HW structure
3687 * @offset: The offset (in bytes) of the dword to read.
3688 * @data: Pointer to the dword to store the value read.
3689 *
3690 * Reads a byte or word from the NVM using the flash access registers.
3691 **/
3692
3693static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3694 u32 *data)
3695{
3696 union ich8_hws_flash_status hsfsts;
3697 union ich8_hws_flash_ctrl hsflctl;
3698 u32 flash_linear_addr;
3699 s32 ret_val = -E1000_ERR_NVM;
3700 u8 count = 0;
3701
3702 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3703 return -E1000_ERR_NVM;
3704 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3705 hw->nvm.flash_base_addr);
3706
3707 do {
3708 udelay(1);
3709 /* Steps */
3710 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3711 if (ret_val)
3712 break;
3713 /* In SPT, This register is in Lan memory space, not flash.
3714 * Therefore, only 32 bit access is supported
3715 */
3716 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3717
3718 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3719 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3720 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3721 /* In SPT, This register is in Lan memory space, not flash.
3722 * Therefore, only 32 bit access is supported
3723 */
3724 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3725 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3726
3727 ret_val =
3728 e1000_flash_cycle_ich8lan(hw,
3729 ICH_FLASH_READ_COMMAND_TIMEOUT);
3730
3731 /* Check if FCERR is set to 1, if set to 1, clear it
3732 * and try the whole sequence a few more times, else
3733 * read in (shift in) the Flash Data0, the order is
3734 * least significant byte first msb to lsb
3735 */
3736 if (!ret_val) {
3737 *data = er32flash(ICH_FLASH_FDATA0);
3738 break;
3739 } else {
3740 /* If we've gotten here, then things are probably
3741 * completely hosed, but if the error condition is
3742 * detected, it won't hurt to give it another try...
3743 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3744 */
3745 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3746 if (hsfsts.hsf_status.flcerr) {
3747 /* Repeat for some time before giving up. */
3748 continue;
3749 } else if (!hsfsts.hsf_status.flcdone) {
3750 e_dbg("Timeout error - flash cycle did not complete.\n");
3751 break;
3752 }
3753 }
3754 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3755
3756 return ret_val;
3757}
3758
3759/**
3760 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3761 * @hw: pointer to the HW structure
3762 * @offset: The offset (in bytes) of the word(s) to write.
3763 * @words: Size of data to write in words
3764 * @data: Pointer to the word(s) to write at offset.
3765 *
3766 * Writes a byte or word to the NVM using the flash access registers.
3767 **/
3768static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3769 u16 *data)
3770{
3771 struct e1000_nvm_info *nvm = &hw->nvm;
3772 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3773 u16 i;
3774
3775 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3776 (words == 0)) {
3777 e_dbg("nvm parameter(s) out of bounds\n");
3778 return -E1000_ERR_NVM;
3779 }
3780
3781 nvm->ops.acquire(hw);
3782
3783 for (i = 0; i < words; i++) {
3784 dev_spec->shadow_ram[offset + i].modified = true;
3785 dev_spec->shadow_ram[offset + i].value = data[i];
3786 }
3787
3788 nvm->ops.release(hw);
3789
3790 return 0;
3791}
3792
3793/**
3794 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3795 * @hw: pointer to the HW structure
3796 *
3797 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3798 * which writes the checksum to the shadow ram. The changes in the shadow
3799 * ram are then committed to the EEPROM by processing each bank at a time
3800 * checking for the modified bit and writing only the pending changes.
3801 * After a successful commit, the shadow ram is cleared and is ready for
3802 * future writes.
3803 **/
3804static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3805{
3806 struct e1000_nvm_info *nvm = &hw->nvm;
3807 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3808 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3809 s32 ret_val;
3810 u32 dword = 0;
3811
3812 ret_val = e1000e_update_nvm_checksum_generic(hw);
3813 if (ret_val)
3814 goto out;
3815
3816 if (nvm->type != e1000_nvm_flash_sw)
3817 goto out;
3818
3819 nvm->ops.acquire(hw);
3820
3821 /* We're writing to the opposite bank so if we're on bank 1,
3822 * write to bank 0 etc. We also need to erase the segment that
3823 * is going to be written
3824 */
3825 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3826 if (ret_val) {
3827 e_dbg("Could not detect valid bank, assuming bank 0\n");
3828 bank = 0;
3829 }
3830
3831 if (bank == 0) {
3832 new_bank_offset = nvm->flash_bank_size;
3833 old_bank_offset = 0;
3834 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3835 if (ret_val)
3836 goto release;
3837 } else {
3838 old_bank_offset = nvm->flash_bank_size;
3839 new_bank_offset = 0;
3840 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3841 if (ret_val)
3842 goto release;
3843 }
3844 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3845 /* Determine whether to write the value stored
3846 * in the other NVM bank or a modified value stored
3847 * in the shadow RAM
3848 */
3849 ret_val = e1000_read_flash_dword_ich8lan(hw,
3850 i + old_bank_offset,
3851 &dword);
3852
3853 if (dev_spec->shadow_ram[i].modified) {
3854 dword &= 0xffff0000;
3855 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3856 }
3857 if (dev_spec->shadow_ram[i + 1].modified) {
3858 dword &= 0x0000ffff;
3859 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3860 << 16);
3861 }
3862 if (ret_val)
3863 break;
3864
3865 /* If the word is 0x13, then make sure the signature bits
3866 * (15:14) are 11b until the commit has completed.
3867 * This will allow us to write 10b which indicates the
3868 * signature is valid. We want to do this after the write
3869 * has completed so that we don't mark the segment valid
3870 * while the write is still in progress
3871 */
3872 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3873 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3874
3875 /* Convert offset to bytes. */
3876 act_offset = (i + new_bank_offset) << 1;
3877
3878 usleep_range(100, 200);
3879
3880 /* Write the data to the new bank. Offset in words */
3881 act_offset = i + new_bank_offset;
3882 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3883 dword);
3884 if (ret_val)
3885 break;
3886 }
3887
3888 /* Don't bother writing the segment valid bits if sector
3889 * programming failed.
3890 */
3891 if (ret_val) {
3892 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3893 e_dbg("Flash commit failed.\n");
3894 goto release;
3895 }
3896
3897 /* Finally validate the new segment by setting bit 15:14
3898 * to 10b in word 0x13 , this can be done without an
3899 * erase as well since these bits are 11 to start with
3900 * and we need to change bit 14 to 0b
3901 */
3902 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3903
3904 /*offset in words but we read dword */
3905 --act_offset;
3906 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3907
3908 if (ret_val)
3909 goto release;
3910
3911 dword &= 0xBFFFFFFF;
3912 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3913
3914 if (ret_val)
3915 goto release;
3916
3917 /* offset in words but we read dword */
3918 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3919 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3920
3921 if (ret_val)
3922 goto release;
3923
3924 dword &= 0x00FFFFFF;
3925 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3926
3927 if (ret_val)
3928 goto release;
3929
3930 /* Great! Everything worked, we can now clear the cached entries. */
3931 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3932 dev_spec->shadow_ram[i].modified = false;
3933 dev_spec->shadow_ram[i].value = 0xFFFF;
3934 }
3935
3936release:
3937 nvm->ops.release(hw);
3938
3939 /* Reload the EEPROM, or else modifications will not appear
3940 * until after the next adapter reset.
3941 */
3942 if (!ret_val) {
3943 nvm->ops.reload(hw);
3944 usleep_range(10000, 11000);
3945 }
3946
3947out:
3948 if (ret_val)
3949 e_dbg("NVM update error: %d\n", ret_val);
3950
3951 return ret_val;
3952}
3953
3954/**
3955 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3956 * @hw: pointer to the HW structure
3957 *
3958 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3959 * which writes the checksum to the shadow ram. The changes in the shadow
3960 * ram are then committed to the EEPROM by processing each bank at a time
3961 * checking for the modified bit and writing only the pending changes.
3962 * After a successful commit, the shadow ram is cleared and is ready for
3963 * future writes.
3964 **/
3965static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3966{
3967 struct e1000_nvm_info *nvm = &hw->nvm;
3968 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3969 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3970 s32 ret_val;
3971 u16 data = 0;
3972
3973 ret_val = e1000e_update_nvm_checksum_generic(hw);
3974 if (ret_val)
3975 goto out;
3976
3977 if (nvm->type != e1000_nvm_flash_sw)
3978 goto out;
3979
3980 nvm->ops.acquire(hw);
3981
3982 /* We're writing to the opposite bank so if we're on bank 1,
3983 * write to bank 0 etc. We also need to erase the segment that
3984 * is going to be written
3985 */
3986 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3987 if (ret_val) {
3988 e_dbg("Could not detect valid bank, assuming bank 0\n");
3989 bank = 0;
3990 }
3991
3992 if (bank == 0) {
3993 new_bank_offset = nvm->flash_bank_size;
3994 old_bank_offset = 0;
3995 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3996 if (ret_val)
3997 goto release;
3998 } else {
3999 old_bank_offset = nvm->flash_bank_size;
4000 new_bank_offset = 0;
4001 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
4002 if (ret_val)
4003 goto release;
4004 }
4005 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4006 if (dev_spec->shadow_ram[i].modified) {
4007 data = dev_spec->shadow_ram[i].value;
4008 } else {
4009 ret_val = e1000_read_flash_word_ich8lan(hw, i +
4010 old_bank_offset,
4011 &data);
4012 if (ret_val)
4013 break;
4014 }
4015
4016 /* If the word is 0x13, then make sure the signature bits
4017 * (15:14) are 11b until the commit has completed.
4018 * This will allow us to write 10b which indicates the
4019 * signature is valid. We want to do this after the write
4020 * has completed so that we don't mark the segment valid
4021 * while the write is still in progress
4022 */
4023 if (i == E1000_ICH_NVM_SIG_WORD)
4024 data |= E1000_ICH_NVM_SIG_MASK;
4025
4026 /* Convert offset to bytes. */
4027 act_offset = (i + new_bank_offset) << 1;
4028
4029 usleep_range(100, 200);
4030 /* Write the bytes to the new bank. */
4031 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4032 act_offset,
4033 (u8)data);
4034 if (ret_val)
4035 break;
4036
4037 usleep_range(100, 200);
4038 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4039 act_offset + 1,
4040 (u8)(data >> 8));
4041 if (ret_val)
4042 break;
4043 }
4044
4045 /* Don't bother writing the segment valid bits if sector
4046 * programming failed.
4047 */
4048 if (ret_val) {
4049 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4050 e_dbg("Flash commit failed.\n");
4051 goto release;
4052 }
4053
4054 /* Finally validate the new segment by setting bit 15:14
4055 * to 10b in word 0x13 , this can be done without an
4056 * erase as well since these bits are 11 to start with
4057 * and we need to change bit 14 to 0b
4058 */
4059 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4060 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4061 if (ret_val)
4062 goto release;
4063
4064 data &= 0xBFFF;
4065 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4066 act_offset * 2 + 1,
4067 (u8)(data >> 8));
4068 if (ret_val)
4069 goto release;
4070
4071 /* And invalidate the previously valid segment by setting
4072 * its signature word (0x13) high_byte to 0b. This can be
4073 * done without an erase because flash erase sets all bits
4074 * to 1's. We can write 1's to 0's without an erase
4075 */
4076 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4077 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4078 if (ret_val)
4079 goto release;
4080
4081 /* Great! Everything worked, we can now clear the cached entries. */
4082 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4083 dev_spec->shadow_ram[i].modified = false;
4084 dev_spec->shadow_ram[i].value = 0xFFFF;
4085 }
4086
4087release:
4088 nvm->ops.release(hw);
4089
4090 /* Reload the EEPROM, or else modifications will not appear
4091 * until after the next adapter reset.
4092 */
4093 if (!ret_val) {
4094 nvm->ops.reload(hw);
4095 usleep_range(10000, 11000);
4096 }
4097
4098out:
4099 if (ret_val)
4100 e_dbg("NVM update error: %d\n", ret_val);
4101
4102 return ret_val;
4103}
4104
4105/**
4106 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4107 * @hw: pointer to the HW structure
4108 *
4109 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4110 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4111 * calculated, in which case we need to calculate the checksum and set bit 6.
4112 **/
4113static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4114{
4115 s32 ret_val;
4116 u16 data;
4117 u16 word;
4118 u16 valid_csum_mask;
4119
4120 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4121 * the checksum needs to be fixed. This bit is an indication that
4122 * the NVM was prepared by OEM software and did not calculate
4123 * the checksum...a likely scenario.
4124 */
4125 switch (hw->mac.type) {
4126 case e1000_pch_lpt:
4127 case e1000_pch_spt:
4128 case e1000_pch_cnp:
4129 case e1000_pch_tgp:
4130 case e1000_pch_adp:
4131 case e1000_pch_mtp:
4132 case e1000_pch_lnp:
4133 case e1000_pch_ptp:
4134 case e1000_pch_nvp:
4135 word = NVM_COMPAT;
4136 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4137 break;
4138 default:
4139 word = NVM_FUTURE_INIT_WORD1;
4140 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4141 break;
4142 }
4143
4144 ret_val = e1000_read_nvm(hw, word, 1, &data);
4145 if (ret_val)
4146 return ret_val;
4147
4148 if (!(data & valid_csum_mask)) {
4149 e_dbg("NVM Checksum valid bit not set\n");
4150
4151 if (hw->mac.type < e1000_pch_tgp) {
4152 data |= valid_csum_mask;
4153 ret_val = e1000_write_nvm(hw, word, 1, &data);
4154 if (ret_val)
4155 return ret_val;
4156 ret_val = e1000e_update_nvm_checksum(hw);
4157 if (ret_val)
4158 return ret_val;
4159 }
4160 }
4161
4162 return e1000e_validate_nvm_checksum_generic(hw);
4163}
4164
4165/**
4166 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4167 * @hw: pointer to the HW structure
4168 *
4169 * To prevent malicious write/erase of the NVM, set it to be read-only
4170 * so that the hardware ignores all write/erase cycles of the NVM via
4171 * the flash control registers. The shadow-ram copy of the NVM will
4172 * still be updated, however any updates to this copy will not stick
4173 * across driver reloads.
4174 **/
4175void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4176{
4177 struct e1000_nvm_info *nvm = &hw->nvm;
4178 union ich8_flash_protected_range pr0;
4179 union ich8_hws_flash_status hsfsts;
4180 u32 gfpreg;
4181
4182 nvm->ops.acquire(hw);
4183
4184 gfpreg = er32flash(ICH_FLASH_GFPREG);
4185
4186 /* Write-protect GbE Sector of NVM */
4187 pr0.regval = er32flash(ICH_FLASH_PR0);
4188 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4189 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4190 pr0.range.wpe = true;
4191 ew32flash(ICH_FLASH_PR0, pr0.regval);
4192
4193 /* Lock down a subset of GbE Flash Control Registers, e.g.
4194 * PR0 to prevent the write-protection from being lifted.
4195 * Once FLOCKDN is set, the registers protected by it cannot
4196 * be written until FLOCKDN is cleared by a hardware reset.
4197 */
4198 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4199 hsfsts.hsf_status.flockdn = true;
4200 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4201
4202 nvm->ops.release(hw);
4203}
4204
4205/**
4206 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4207 * @hw: pointer to the HW structure
4208 * @offset: The offset (in bytes) of the byte/word to read.
4209 * @size: Size of data to read, 1=byte 2=word
4210 * @data: The byte(s) to write to the NVM.
4211 *
4212 * Writes one/two bytes to the NVM using the flash access registers.
4213 **/
4214static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4215 u8 size, u16 data)
4216{
4217 union ich8_hws_flash_status hsfsts;
4218 union ich8_hws_flash_ctrl hsflctl;
4219 u32 flash_linear_addr;
4220 u32 flash_data = 0;
4221 s32 ret_val;
4222 u8 count = 0;
4223
4224 if (hw->mac.type >= e1000_pch_spt) {
4225 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4226 return -E1000_ERR_NVM;
4227 } else {
4228 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4229 return -E1000_ERR_NVM;
4230 }
4231
4232 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4233 hw->nvm.flash_base_addr);
4234
4235 do {
4236 udelay(1);
4237 /* Steps */
4238 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4239 if (ret_val)
4240 break;
4241 /* In SPT, This register is in Lan memory space, not
4242 * flash. Therefore, only 32 bit access is supported
4243 */
4244 if (hw->mac.type >= e1000_pch_spt)
4245 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4246 else
4247 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4248
4249 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4250 hsflctl.hsf_ctrl.fldbcount = size - 1;
4251 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4252 /* In SPT, This register is in Lan memory space,
4253 * not flash. Therefore, only 32 bit access is
4254 * supported
4255 */
4256 if (hw->mac.type >= e1000_pch_spt)
4257 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4258 else
4259 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4260
4261 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4262
4263 if (size == 1)
4264 flash_data = (u32)data & 0x00FF;
4265 else
4266 flash_data = (u32)data;
4267
4268 ew32flash(ICH_FLASH_FDATA0, flash_data);
4269
4270 /* check if FCERR is set to 1 , if set to 1, clear it
4271 * and try the whole sequence a few more times else done
4272 */
4273 ret_val =
4274 e1000_flash_cycle_ich8lan(hw,
4275 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4276 if (!ret_val)
4277 break;
4278
4279 /* If we're here, then things are most likely
4280 * completely hosed, but if the error condition
4281 * is detected, it won't hurt to give it another
4282 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4283 */
4284 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4285 if (hsfsts.hsf_status.flcerr)
4286 /* Repeat for some time before giving up. */
4287 continue;
4288 if (!hsfsts.hsf_status.flcdone) {
4289 e_dbg("Timeout error - flash cycle did not complete.\n");
4290 break;
4291 }
4292 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4293
4294 return ret_val;
4295}
4296
4297/**
4298* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4299* @hw: pointer to the HW structure
4300* @offset: The offset (in bytes) of the dwords to read.
4301* @data: The 4 bytes to write to the NVM.
4302*
4303* Writes one/two/four bytes to the NVM using the flash access registers.
4304**/
4305static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4306 u32 data)
4307{
4308 union ich8_hws_flash_status hsfsts;
4309 union ich8_hws_flash_ctrl hsflctl;
4310 u32 flash_linear_addr;
4311 s32 ret_val;
4312 u8 count = 0;
4313
4314 if (hw->mac.type >= e1000_pch_spt) {
4315 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4316 return -E1000_ERR_NVM;
4317 }
4318 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4319 hw->nvm.flash_base_addr);
4320 do {
4321 udelay(1);
4322 /* Steps */
4323 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4324 if (ret_val)
4325 break;
4326
4327 /* In SPT, This register is in Lan memory space, not
4328 * flash. Therefore, only 32 bit access is supported
4329 */
4330 if (hw->mac.type >= e1000_pch_spt)
4331 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4332 >> 16;
4333 else
4334 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4335
4336 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4337 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4338
4339 /* In SPT, This register is in Lan memory space,
4340 * not flash. Therefore, only 32 bit access is
4341 * supported
4342 */
4343 if (hw->mac.type >= e1000_pch_spt)
4344 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4345 else
4346 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4347
4348 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4349
4350 ew32flash(ICH_FLASH_FDATA0, data);
4351
4352 /* check if FCERR is set to 1 , if set to 1, clear it
4353 * and try the whole sequence a few more times else done
4354 */
4355 ret_val =
4356 e1000_flash_cycle_ich8lan(hw,
4357 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4358
4359 if (!ret_val)
4360 break;
4361
4362 /* If we're here, then things are most likely
4363 * completely hosed, but if the error condition
4364 * is detected, it won't hurt to give it another
4365 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4366 */
4367 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4368
4369 if (hsfsts.hsf_status.flcerr)
4370 /* Repeat for some time before giving up. */
4371 continue;
4372 if (!hsfsts.hsf_status.flcdone) {
4373 e_dbg("Timeout error - flash cycle did not complete.\n");
4374 break;
4375 }
4376 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4377
4378 return ret_val;
4379}
4380
4381/**
4382 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4383 * @hw: pointer to the HW structure
4384 * @offset: The index of the byte to read.
4385 * @data: The byte to write to the NVM.
4386 *
4387 * Writes a single byte to the NVM using the flash access registers.
4388 **/
4389static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4390 u8 data)
4391{
4392 u16 word = (u16)data;
4393
4394 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4395}
4396
4397/**
4398* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4399* @hw: pointer to the HW structure
4400* @offset: The offset of the word to write.
4401* @dword: The dword to write to the NVM.
4402*
4403* Writes a single dword to the NVM using the flash access registers.
4404* Goes through a retry algorithm before giving up.
4405**/
4406static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4407 u32 offset, u32 dword)
4408{
4409 s32 ret_val;
4410 u16 program_retries;
4411
4412 /* Must convert word offset into bytes. */
4413 offset <<= 1;
4414 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4415
4416 if (!ret_val)
4417 return ret_val;
4418 for (program_retries = 0; program_retries < 100; program_retries++) {
4419 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4420 usleep_range(100, 200);
4421 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4422 if (!ret_val)
4423 break;
4424 }
4425 if (program_retries == 100)
4426 return -E1000_ERR_NVM;
4427
4428 return 0;
4429}
4430
4431/**
4432 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4433 * @hw: pointer to the HW structure
4434 * @offset: The offset of the byte to write.
4435 * @byte: The byte to write to the NVM.
4436 *
4437 * Writes a single byte to the NVM using the flash access registers.
4438 * Goes through a retry algorithm before giving up.
4439 **/
4440static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4441 u32 offset, u8 byte)
4442{
4443 s32 ret_val;
4444 u16 program_retries;
4445
4446 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4447 if (!ret_val)
4448 return ret_val;
4449
4450 for (program_retries = 0; program_retries < 100; program_retries++) {
4451 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4452 usleep_range(100, 200);
4453 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4454 if (!ret_val)
4455 break;
4456 }
4457 if (program_retries == 100)
4458 return -E1000_ERR_NVM;
4459
4460 return 0;
4461}
4462
4463/**
4464 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4465 * @hw: pointer to the HW structure
4466 * @bank: 0 for first bank, 1 for second bank, etc.
4467 *
4468 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4469 * bank N is 4096 * N + flash_reg_addr.
4470 **/
4471static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4472{
4473 struct e1000_nvm_info *nvm = &hw->nvm;
4474 union ich8_hws_flash_status hsfsts;
4475 union ich8_hws_flash_ctrl hsflctl;
4476 u32 flash_linear_addr;
4477 /* bank size is in 16bit words - adjust to bytes */
4478 u32 flash_bank_size = nvm->flash_bank_size * 2;
4479 s32 ret_val;
4480 s32 count = 0;
4481 s32 j, iteration, sector_size;
4482
4483 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4484
4485 /* Determine HW Sector size: Read BERASE bits of hw flash status
4486 * register
4487 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4488 * consecutive sectors. The start index for the nth Hw sector
4489 * can be calculated as = bank * 4096 + n * 256
4490 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4491 * The start index for the nth Hw sector can be calculated
4492 * as = bank * 4096
4493 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4494 * (ich9 only, otherwise error condition)
4495 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4496 */
4497 switch (hsfsts.hsf_status.berasesz) {
4498 case 0:
4499 /* Hw sector size 256 */
4500 sector_size = ICH_FLASH_SEG_SIZE_256;
4501 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4502 break;
4503 case 1:
4504 sector_size = ICH_FLASH_SEG_SIZE_4K;
4505 iteration = 1;
4506 break;
4507 case 2:
4508 sector_size = ICH_FLASH_SEG_SIZE_8K;
4509 iteration = 1;
4510 break;
4511 case 3:
4512 sector_size = ICH_FLASH_SEG_SIZE_64K;
4513 iteration = 1;
4514 break;
4515 default:
4516 return -E1000_ERR_NVM;
4517 }
4518
4519 /* Start with the base address, then add the sector offset. */
4520 flash_linear_addr = hw->nvm.flash_base_addr;
4521 flash_linear_addr += (bank) ? flash_bank_size : 0;
4522
4523 for (j = 0; j < iteration; j++) {
4524 do {
4525 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4526
4527 /* Steps */
4528 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4529 if (ret_val)
4530 return ret_val;
4531
4532 /* Write a value 11 (block Erase) in Flash
4533 * Cycle field in hw flash control
4534 */
4535 if (hw->mac.type >= e1000_pch_spt)
4536 hsflctl.regval =
4537 er32flash(ICH_FLASH_HSFSTS) >> 16;
4538 else
4539 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4540
4541 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4542 if (hw->mac.type >= e1000_pch_spt)
4543 ew32flash(ICH_FLASH_HSFSTS,
4544 hsflctl.regval << 16);
4545 else
4546 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4547
4548 /* Write the last 24 bits of an index within the
4549 * block into Flash Linear address field in Flash
4550 * Address.
4551 */
4552 flash_linear_addr += (j * sector_size);
4553 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4554
4555 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4556 if (!ret_val)
4557 break;
4558
4559 /* Check if FCERR is set to 1. If 1,
4560 * clear it and try the whole sequence
4561 * a few more times else Done
4562 */
4563 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4564 if (hsfsts.hsf_status.flcerr)
4565 /* repeat for some time before giving up */
4566 continue;
4567 else if (!hsfsts.hsf_status.flcdone)
4568 return ret_val;
4569 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4570 }
4571
4572 return 0;
4573}
4574
4575/**
4576 * e1000_valid_led_default_ich8lan - Set the default LED settings
4577 * @hw: pointer to the HW structure
4578 * @data: Pointer to the LED settings
4579 *
4580 * Reads the LED default settings from the NVM to data. If the NVM LED
4581 * settings is all 0's or F's, set the LED default to a valid LED default
4582 * setting.
4583 **/
4584static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4585{
4586 s32 ret_val;
4587
4588 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4589 if (ret_val) {
4590 e_dbg("NVM Read Error\n");
4591 return ret_val;
4592 }
4593
4594 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4595 *data = ID_LED_DEFAULT_ICH8LAN;
4596
4597 return 0;
4598}
4599
4600/**
4601 * e1000_id_led_init_pchlan - store LED configurations
4602 * @hw: pointer to the HW structure
4603 *
4604 * PCH does not control LEDs via the LEDCTL register, rather it uses
4605 * the PHY LED configuration register.
4606 *
4607 * PCH also does not have an "always on" or "always off" mode which
4608 * complicates the ID feature. Instead of using the "on" mode to indicate
4609 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4610 * use "link_up" mode. The LEDs will still ID on request if there is no
4611 * link based on logic in e1000_led_[on|off]_pchlan().
4612 **/
4613static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4614{
4615 struct e1000_mac_info *mac = &hw->mac;
4616 s32 ret_val;
4617 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4618 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4619 u16 data, i, temp, shift;
4620
4621 /* Get default ID LED modes */
4622 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4623 if (ret_val)
4624 return ret_val;
4625
4626 mac->ledctl_default = er32(LEDCTL);
4627 mac->ledctl_mode1 = mac->ledctl_default;
4628 mac->ledctl_mode2 = mac->ledctl_default;
4629
4630 for (i = 0; i < 4; i++) {
4631 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4632 shift = (i * 5);
4633 switch (temp) {
4634 case ID_LED_ON1_DEF2:
4635 case ID_LED_ON1_ON2:
4636 case ID_LED_ON1_OFF2:
4637 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4638 mac->ledctl_mode1 |= (ledctl_on << shift);
4639 break;
4640 case ID_LED_OFF1_DEF2:
4641 case ID_LED_OFF1_ON2:
4642 case ID_LED_OFF1_OFF2:
4643 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4644 mac->ledctl_mode1 |= (ledctl_off << shift);
4645 break;
4646 default:
4647 /* Do nothing */
4648 break;
4649 }
4650 switch (temp) {
4651 case ID_LED_DEF1_ON2:
4652 case ID_LED_ON1_ON2:
4653 case ID_LED_OFF1_ON2:
4654 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4655 mac->ledctl_mode2 |= (ledctl_on << shift);
4656 break;
4657 case ID_LED_DEF1_OFF2:
4658 case ID_LED_ON1_OFF2:
4659 case ID_LED_OFF1_OFF2:
4660 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4661 mac->ledctl_mode2 |= (ledctl_off << shift);
4662 break;
4663 default:
4664 /* Do nothing */
4665 break;
4666 }
4667 }
4668
4669 return 0;
4670}
4671
4672/**
4673 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4674 * @hw: pointer to the HW structure
4675 *
4676 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4677 * register, so the bus width is hard coded.
4678 **/
4679static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4680{
4681 struct e1000_bus_info *bus = &hw->bus;
4682 s32 ret_val;
4683
4684 ret_val = e1000e_get_bus_info_pcie(hw);
4685
4686 /* ICH devices are "PCI Express"-ish. They have
4687 * a configuration space, but do not contain
4688 * PCI Express Capability registers, so bus width
4689 * must be hardcoded.
4690 */
4691 if (bus->width == e1000_bus_width_unknown)
4692 bus->width = e1000_bus_width_pcie_x1;
4693
4694 return ret_val;
4695}
4696
4697/**
4698 * e1000_reset_hw_ich8lan - Reset the hardware
4699 * @hw: pointer to the HW structure
4700 *
4701 * Does a full reset of the hardware which includes a reset of the PHY and
4702 * MAC.
4703 **/
4704static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4705{
4706 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4707 u16 kum_cfg;
4708 u32 ctrl, reg;
4709 s32 ret_val;
4710
4711 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4712 * on the last TLP read/write transaction when MAC is reset.
4713 */
4714 ret_val = e1000e_disable_pcie_master(hw);
4715 if (ret_val)
4716 e_dbg("PCI-E Master disable polling has failed.\n");
4717
4718 e_dbg("Masking off all interrupts\n");
4719 ew32(IMC, 0xffffffff);
4720
4721 /* Disable the Transmit and Receive units. Then delay to allow
4722 * any pending transactions to complete before we hit the MAC
4723 * with the global reset.
4724 */
4725 ew32(RCTL, 0);
4726 ew32(TCTL, E1000_TCTL_PSP);
4727 e1e_flush();
4728
4729 usleep_range(10000, 11000);
4730
4731 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4732 if (hw->mac.type == e1000_ich8lan) {
4733 /* Set Tx and Rx buffer allocation to 8k apiece. */
4734 ew32(PBA, E1000_PBA_8K);
4735 /* Set Packet Buffer Size to 16k. */
4736 ew32(PBS, E1000_PBS_16K);
4737 }
4738
4739 if (hw->mac.type == e1000_pchlan) {
4740 /* Save the NVM K1 bit setting */
4741 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4742 if (ret_val)
4743 return ret_val;
4744
4745 if (kum_cfg & E1000_NVM_K1_ENABLE)
4746 dev_spec->nvm_k1_enabled = true;
4747 else
4748 dev_spec->nvm_k1_enabled = false;
4749 }
4750
4751 ctrl = er32(CTRL);
4752
4753 if (!hw->phy.ops.check_reset_block(hw)) {
4754 /* Full-chip reset requires MAC and PHY reset at the same
4755 * time to make sure the interface between MAC and the
4756 * external PHY is reset.
4757 */
4758 ctrl |= E1000_CTRL_PHY_RST;
4759
4760 /* Gate automatic PHY configuration by hardware on
4761 * non-managed 82579
4762 */
4763 if ((hw->mac.type == e1000_pch2lan) &&
4764 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4765 e1000_gate_hw_phy_config_ich8lan(hw, true);
4766 }
4767 ret_val = e1000_acquire_swflag_ich8lan(hw);
4768 e_dbg("Issuing a global reset to ich8lan\n");
4769 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4770 /* cannot issue a flush here because it hangs the hardware */
4771 msleep(20);
4772
4773 /* Set Phy Config Counter to 50msec */
4774 if (hw->mac.type == e1000_pch2lan) {
4775 reg = er32(FEXTNVM3);
4776 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4777 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4778 ew32(FEXTNVM3, reg);
4779 }
4780
4781 if (!ret_val)
4782 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4783
4784 if (ctrl & E1000_CTRL_PHY_RST) {
4785 ret_val = hw->phy.ops.get_cfg_done(hw);
4786 if (ret_val)
4787 return ret_val;
4788
4789 ret_val = e1000_post_phy_reset_ich8lan(hw);
4790 if (ret_val)
4791 return ret_val;
4792 }
4793
4794 /* For PCH, this write will make sure that any noise
4795 * will be detected as a CRC error and be dropped rather than show up
4796 * as a bad packet to the DMA engine.
4797 */
4798 if (hw->mac.type == e1000_pchlan)
4799 ew32(CRC_OFFSET, 0x65656565);
4800
4801 ew32(IMC, 0xffffffff);
4802 er32(ICR);
4803
4804 reg = er32(KABGTXD);
4805 reg |= E1000_KABGTXD_BGSQLBIAS;
4806 ew32(KABGTXD, reg);
4807
4808 return 0;
4809}
4810
4811/**
4812 * e1000_init_hw_ich8lan - Initialize the hardware
4813 * @hw: pointer to the HW structure
4814 *
4815 * Prepares the hardware for transmit and receive by doing the following:
4816 * - initialize hardware bits
4817 * - initialize LED identification
4818 * - setup receive address registers
4819 * - setup flow control
4820 * - setup transmit descriptors
4821 * - clear statistics
4822 **/
4823static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4824{
4825 struct e1000_mac_info *mac = &hw->mac;
4826 u32 ctrl_ext, txdctl, snoop, fflt_dbg;
4827 s32 ret_val;
4828 u16 i;
4829
4830 e1000_initialize_hw_bits_ich8lan(hw);
4831
4832 /* Initialize identification LED */
4833 ret_val = mac->ops.id_led_init(hw);
4834 /* An error is not fatal and we should not stop init due to this */
4835 if (ret_val)
4836 e_dbg("Error initializing identification LED\n");
4837
4838 /* Setup the receive address. */
4839 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4840
4841 /* Zero out the Multicast HASH table */
4842 e_dbg("Zeroing the MTA\n");
4843 for (i = 0; i < mac->mta_reg_count; i++)
4844 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4845
4846 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4847 * the ME. Disable wakeup by clearing the host wakeup bit.
4848 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4849 */
4850 if (hw->phy.type == e1000_phy_82578) {
4851 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4852 i &= ~BM_WUC_HOST_WU_BIT;
4853 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4854 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4855 if (ret_val)
4856 return ret_val;
4857 }
4858
4859 /* Setup link and flow control */
4860 ret_val = mac->ops.setup_link(hw);
4861
4862 /* Set the transmit descriptor write-back policy for both queues */
4863 txdctl = er32(TXDCTL(0));
4864 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4865 E1000_TXDCTL_FULL_TX_DESC_WB);
4866 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4867 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4868 ew32(TXDCTL(0), txdctl);
4869 txdctl = er32(TXDCTL(1));
4870 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4871 E1000_TXDCTL_FULL_TX_DESC_WB);
4872 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4873 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4874 ew32(TXDCTL(1), txdctl);
4875
4876 /* ICH8 has opposite polarity of no_snoop bits.
4877 * By default, we should use snoop behavior.
4878 */
4879 if (mac->type == e1000_ich8lan)
4880 snoop = PCIE_ICH8_SNOOP_ALL;
4881 else
4882 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4883 e1000e_set_pcie_no_snoop(hw, snoop);
4884
4885 /* Enable workaround for packet loss issue on TGP PCH
4886 * Do not gate DMA clock from the modPHY block
4887 */
4888 if (mac->type >= e1000_pch_tgp) {
4889 fflt_dbg = er32(FFLT_DBG);
4890 fflt_dbg |= E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK;
4891 ew32(FFLT_DBG, fflt_dbg);
4892 }
4893
4894 ctrl_ext = er32(CTRL_EXT);
4895 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4896 ew32(CTRL_EXT, ctrl_ext);
4897
4898 /* Clear all of the statistics registers (clear on read). It is
4899 * important that we do this after we have tried to establish link
4900 * because the symbol error count will increment wildly if there
4901 * is no link.
4902 */
4903 e1000_clear_hw_cntrs_ich8lan(hw);
4904
4905 return ret_val;
4906}
4907
4908/**
4909 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4910 * @hw: pointer to the HW structure
4911 *
4912 * Sets/Clears required hardware bits necessary for correctly setting up the
4913 * hardware for transmit and receive.
4914 **/
4915static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4916{
4917 u32 reg;
4918
4919 /* Extended Device Control */
4920 reg = er32(CTRL_EXT);
4921 reg |= BIT(22);
4922 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4923 if (hw->mac.type >= e1000_pchlan)
4924 reg |= E1000_CTRL_EXT_PHYPDEN;
4925 ew32(CTRL_EXT, reg);
4926
4927 /* Transmit Descriptor Control 0 */
4928 reg = er32(TXDCTL(0));
4929 reg |= BIT(22);
4930 ew32(TXDCTL(0), reg);
4931
4932 /* Transmit Descriptor Control 1 */
4933 reg = er32(TXDCTL(1));
4934 reg |= BIT(22);
4935 ew32(TXDCTL(1), reg);
4936
4937 /* Transmit Arbitration Control 0 */
4938 reg = er32(TARC(0));
4939 if (hw->mac.type == e1000_ich8lan)
4940 reg |= BIT(28) | BIT(29);
4941 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4942 ew32(TARC(0), reg);
4943
4944 /* Transmit Arbitration Control 1 */
4945 reg = er32(TARC(1));
4946 if (er32(TCTL) & E1000_TCTL_MULR)
4947 reg &= ~BIT(28);
4948 else
4949 reg |= BIT(28);
4950 reg |= BIT(24) | BIT(26) | BIT(30);
4951 ew32(TARC(1), reg);
4952
4953 /* Device Status */
4954 if (hw->mac.type == e1000_ich8lan) {
4955 reg = er32(STATUS);
4956 reg &= ~BIT(31);
4957 ew32(STATUS, reg);
4958 }
4959
4960 /* work-around descriptor data corruption issue during nfs v2 udp
4961 * traffic, just disable the nfs filtering capability
4962 */
4963 reg = er32(RFCTL);
4964 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4965
4966 /* Disable IPv6 extension header parsing because some malformed
4967 * IPv6 headers can hang the Rx.
4968 */
4969 if (hw->mac.type == e1000_ich8lan)
4970 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4971 ew32(RFCTL, reg);
4972
4973 /* Enable ECC on Lynxpoint */
4974 if (hw->mac.type >= e1000_pch_lpt) {
4975 reg = er32(PBECCSTS);
4976 reg |= E1000_PBECCSTS_ECC_ENABLE;
4977 ew32(PBECCSTS, reg);
4978
4979 reg = er32(CTRL);
4980 reg |= E1000_CTRL_MEHE;
4981 ew32(CTRL, reg);
4982 }
4983}
4984
4985/**
4986 * e1000_setup_link_ich8lan - Setup flow control and link settings
4987 * @hw: pointer to the HW structure
4988 *
4989 * Determines which flow control settings to use, then configures flow
4990 * control. Calls the appropriate media-specific link configuration
4991 * function. Assuming the adapter has a valid link partner, a valid link
4992 * should be established. Assumes the hardware has previously been reset
4993 * and the transmitter and receiver are not enabled.
4994 **/
4995static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4996{
4997 s32 ret_val;
4998
4999 if (hw->phy.ops.check_reset_block(hw))
5000 return 0;
5001
5002 /* ICH parts do not have a word in the NVM to determine
5003 * the default flow control setting, so we explicitly
5004 * set it to full.
5005 */
5006 if (hw->fc.requested_mode == e1000_fc_default) {
5007 /* Workaround h/w hang when Tx flow control enabled */
5008 if (hw->mac.type == e1000_pchlan)
5009 hw->fc.requested_mode = e1000_fc_rx_pause;
5010 else
5011 hw->fc.requested_mode = e1000_fc_full;
5012 }
5013
5014 /* Save off the requested flow control mode for use later. Depending
5015 * on the link partner's capabilities, we may or may not use this mode.
5016 */
5017 hw->fc.current_mode = hw->fc.requested_mode;
5018
5019 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
5020
5021 /* Continue to configure the copper link. */
5022 ret_val = hw->mac.ops.setup_physical_interface(hw);
5023 if (ret_val)
5024 return ret_val;
5025
5026 ew32(FCTTV, hw->fc.pause_time);
5027 if ((hw->phy.type == e1000_phy_82578) ||
5028 (hw->phy.type == e1000_phy_82579) ||
5029 (hw->phy.type == e1000_phy_i217) ||
5030 (hw->phy.type == e1000_phy_82577)) {
5031 ew32(FCRTV_PCH, hw->fc.refresh_time);
5032
5033 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
5034 hw->fc.pause_time);
5035 if (ret_val)
5036 return ret_val;
5037 }
5038
5039 return e1000e_set_fc_watermarks(hw);
5040}
5041
5042/**
5043 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
5044 * @hw: pointer to the HW structure
5045 *
5046 * Configures the kumeran interface to the PHY to wait the appropriate time
5047 * when polling the PHY, then call the generic setup_copper_link to finish
5048 * configuring the copper link.
5049 **/
5050static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
5051{
5052 u32 ctrl;
5053 s32 ret_val;
5054 u16 reg_data;
5055
5056 ctrl = er32(CTRL);
5057 ctrl |= E1000_CTRL_SLU;
5058 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5059 ew32(CTRL, ctrl);
5060
5061 /* Set the mac to wait the maximum time between each iteration
5062 * and increase the max iterations when polling the phy;
5063 * this fixes erroneous timeouts at 10Mbps.
5064 */
5065 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5066 if (ret_val)
5067 return ret_val;
5068 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5069 ®_data);
5070 if (ret_val)
5071 return ret_val;
5072 reg_data |= 0x3F;
5073 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5074 reg_data);
5075 if (ret_val)
5076 return ret_val;
5077
5078 switch (hw->phy.type) {
5079 case e1000_phy_igp_3:
5080 ret_val = e1000e_copper_link_setup_igp(hw);
5081 if (ret_val)
5082 return ret_val;
5083 break;
5084 case e1000_phy_bm:
5085 case e1000_phy_82578:
5086 ret_val = e1000e_copper_link_setup_m88(hw);
5087 if (ret_val)
5088 return ret_val;
5089 break;
5090 case e1000_phy_82577:
5091 case e1000_phy_82579:
5092 ret_val = e1000_copper_link_setup_82577(hw);
5093 if (ret_val)
5094 return ret_val;
5095 break;
5096 case e1000_phy_ife:
5097 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
5098 if (ret_val)
5099 return ret_val;
5100
5101 reg_data &= ~IFE_PMC_AUTO_MDIX;
5102
5103 switch (hw->phy.mdix) {
5104 case 1:
5105 reg_data &= ~IFE_PMC_FORCE_MDIX;
5106 break;
5107 case 2:
5108 reg_data |= IFE_PMC_FORCE_MDIX;
5109 break;
5110 case 0:
5111 default:
5112 reg_data |= IFE_PMC_AUTO_MDIX;
5113 break;
5114 }
5115 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5116 if (ret_val)
5117 return ret_val;
5118 break;
5119 default:
5120 break;
5121 }
5122
5123 return e1000e_setup_copper_link(hw);
5124}
5125
5126/**
5127 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5128 * @hw: pointer to the HW structure
5129 *
5130 * Calls the PHY specific link setup function and then calls the
5131 * generic setup_copper_link to finish configuring the link for
5132 * Lynxpoint PCH devices
5133 **/
5134static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5135{
5136 u32 ctrl;
5137 s32 ret_val;
5138
5139 ctrl = er32(CTRL);
5140 ctrl |= E1000_CTRL_SLU;
5141 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5142 ew32(CTRL, ctrl);
5143
5144 ret_val = e1000_copper_link_setup_82577(hw);
5145 if (ret_val)
5146 return ret_val;
5147
5148 return e1000e_setup_copper_link(hw);
5149}
5150
5151/**
5152 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5153 * @hw: pointer to the HW structure
5154 * @speed: pointer to store current link speed
5155 * @duplex: pointer to store the current link duplex
5156 *
5157 * Calls the generic get_speed_and_duplex to retrieve the current link
5158 * information and then calls the Kumeran lock loss workaround for links at
5159 * gigabit speeds.
5160 **/
5161static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5162 u16 *duplex)
5163{
5164 s32 ret_val;
5165
5166 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5167 if (ret_val)
5168 return ret_val;
5169
5170 if ((hw->mac.type == e1000_ich8lan) &&
5171 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5172 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5173 }
5174
5175 return ret_val;
5176}
5177
5178/**
5179 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5180 * @hw: pointer to the HW structure
5181 *
5182 * Work-around for 82566 Kumeran PCS lock loss:
5183 * On link status change (i.e. PCI reset, speed change) and link is up and
5184 * speed is gigabit-
5185 * 0) if workaround is optionally disabled do nothing
5186 * 1) wait 1ms for Kumeran link to come up
5187 * 2) check Kumeran Diagnostic register PCS lock loss bit
5188 * 3) if not set the link is locked (all is good), otherwise...
5189 * 4) reset the PHY
5190 * 5) repeat up to 10 times
5191 * Note: this is only called for IGP3 copper when speed is 1gb.
5192 **/
5193static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5194{
5195 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5196 u32 phy_ctrl;
5197 s32 ret_val;
5198 u16 i, data;
5199 bool link;
5200
5201 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5202 return 0;
5203
5204 /* Make sure link is up before proceeding. If not just return.
5205 * Attempting this while link is negotiating fouled up link
5206 * stability
5207 */
5208 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5209 if (!link)
5210 return 0;
5211
5212 for (i = 0; i < 10; i++) {
5213 /* read once to clear */
5214 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5215 if (ret_val)
5216 return ret_val;
5217 /* and again to get new status */
5218 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5219 if (ret_val)
5220 return ret_val;
5221
5222 /* check for PCS lock */
5223 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5224 return 0;
5225
5226 /* Issue PHY reset */
5227 e1000_phy_hw_reset(hw);
5228 mdelay(5);
5229 }
5230 /* Disable GigE link negotiation */
5231 phy_ctrl = er32(PHY_CTRL);
5232 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5233 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5234 ew32(PHY_CTRL, phy_ctrl);
5235
5236 /* Call gig speed drop workaround on Gig disable before accessing
5237 * any PHY registers
5238 */
5239 e1000e_gig_downshift_workaround_ich8lan(hw);
5240
5241 /* unable to acquire PCS lock */
5242 return -E1000_ERR_PHY;
5243}
5244
5245/**
5246 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5247 * @hw: pointer to the HW structure
5248 * @state: boolean value used to set the current Kumeran workaround state
5249 *
5250 * If ICH8, set the current Kumeran workaround state (enabled - true
5251 * /disabled - false).
5252 **/
5253void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5254 bool state)
5255{
5256 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5257
5258 if (hw->mac.type != e1000_ich8lan) {
5259 e_dbg("Workaround applies to ICH8 only.\n");
5260 return;
5261 }
5262
5263 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5264}
5265
5266/**
5267 * e1000e_igp3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5268 * @hw: pointer to the HW structure
5269 *
5270 * Workaround for 82566 power-down on D3 entry:
5271 * 1) disable gigabit link
5272 * 2) write VR power-down enable
5273 * 3) read it back
5274 * Continue if successful, else issue LCD reset and repeat
5275 **/
5276void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5277{
5278 u32 reg;
5279 u16 data;
5280 u8 retry = 0;
5281
5282 if (hw->phy.type != e1000_phy_igp_3)
5283 return;
5284
5285 /* Try the workaround twice (if needed) */
5286 do {
5287 /* Disable link */
5288 reg = er32(PHY_CTRL);
5289 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5290 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5291 ew32(PHY_CTRL, reg);
5292
5293 /* Call gig speed drop workaround on Gig disable before
5294 * accessing any PHY registers
5295 */
5296 if (hw->mac.type == e1000_ich8lan)
5297 e1000e_gig_downshift_workaround_ich8lan(hw);
5298
5299 /* Write VR power-down enable */
5300 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5301 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5302 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5303
5304 /* Read it back and test */
5305 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5306 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5307 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5308 break;
5309
5310 /* Issue PHY reset and repeat at most one more time */
5311 reg = er32(CTRL);
5312 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5313 retry++;
5314 } while (retry);
5315}
5316
5317/**
5318 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5319 * @hw: pointer to the HW structure
5320 *
5321 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5322 * LPLU, Gig disable, MDIC PHY reset):
5323 * 1) Set Kumeran Near-end loopback
5324 * 2) Clear Kumeran Near-end loopback
5325 * Should only be called for ICH8[m] devices with any 1G Phy.
5326 **/
5327void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5328{
5329 s32 ret_val;
5330 u16 reg_data;
5331
5332 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5333 return;
5334
5335 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5336 ®_data);
5337 if (ret_val)
5338 return;
5339 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5340 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5341 reg_data);
5342 if (ret_val)
5343 return;
5344 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5345 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5346}
5347
5348/**
5349 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5350 * @hw: pointer to the HW structure
5351 *
5352 * During S0 to Sx transition, it is possible the link remains at gig
5353 * instead of negotiating to a lower speed. Before going to Sx, set
5354 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5355 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5356 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5357 * needs to be written.
5358 * Parts that support (and are linked to a partner which support) EEE in
5359 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5360 * than 10Mbps w/o EEE.
5361 **/
5362void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5363{
5364 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5365 u32 phy_ctrl;
5366 s32 ret_val;
5367
5368 phy_ctrl = er32(PHY_CTRL);
5369 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5370
5371 if (hw->phy.type == e1000_phy_i217) {
5372 u16 phy_reg, device_id = hw->adapter->pdev->device;
5373
5374 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5375 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5376 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5377 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5378 (hw->mac.type >= e1000_pch_spt)) {
5379 u32 fextnvm6 = er32(FEXTNVM6);
5380
5381 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5382 }
5383
5384 ret_val = hw->phy.ops.acquire(hw);
5385 if (ret_val)
5386 goto out;
5387
5388 if (!dev_spec->eee_disable) {
5389 u16 eee_advert;
5390
5391 ret_val =
5392 e1000_read_emi_reg_locked(hw,
5393 I217_EEE_ADVERTISEMENT,
5394 &eee_advert);
5395 if (ret_val)
5396 goto release;
5397
5398 /* Disable LPLU if both link partners support 100BaseT
5399 * EEE and 100Full is advertised on both ends of the
5400 * link, and enable Auto Enable LPI since there will
5401 * be no driver to enable LPI while in Sx.
5402 */
5403 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5404 (dev_spec->eee_lp_ability &
5405 I82579_EEE_100_SUPPORTED) &&
5406 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5407 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5408 E1000_PHY_CTRL_NOND0A_LPLU);
5409
5410 /* Set Auto Enable LPI after link up */
5411 e1e_rphy_locked(hw,
5412 I217_LPI_GPIO_CTRL, &phy_reg);
5413 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5414 e1e_wphy_locked(hw,
5415 I217_LPI_GPIO_CTRL, phy_reg);
5416 }
5417 }
5418
5419 /* For i217 Intel Rapid Start Technology support,
5420 * when the system is going into Sx and no manageability engine
5421 * is present, the driver must configure proxy to reset only on
5422 * power good. LPI (Low Power Idle) state must also reset only
5423 * on power good, as well as the MTA (Multicast table array).
5424 * The SMBus release must also be disabled on LCD reset.
5425 */
5426 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5427 /* Enable proxy to reset only on power good. */
5428 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5429 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5430 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5431
5432 /* Set bit enable LPI (EEE) to reset only on
5433 * power good.
5434 */
5435 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5436 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5437 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5438
5439 /* Disable the SMB release on LCD reset. */
5440 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5441 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5442 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5443 }
5444
5445 /* Enable MTA to reset for Intel Rapid Start Technology
5446 * Support
5447 */
5448 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5449 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5450 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5451
5452release:
5453 hw->phy.ops.release(hw);
5454 }
5455out:
5456 ew32(PHY_CTRL, phy_ctrl);
5457
5458 if (hw->mac.type == e1000_ich8lan)
5459 e1000e_gig_downshift_workaround_ich8lan(hw);
5460
5461 if (hw->mac.type >= e1000_pchlan) {
5462 e1000_oem_bits_config_ich8lan(hw, false);
5463
5464 /* Reset PHY to activate OEM bits on 82577/8 */
5465 if (hw->mac.type == e1000_pchlan)
5466 e1000e_phy_hw_reset_generic(hw);
5467
5468 ret_val = hw->phy.ops.acquire(hw);
5469 if (ret_val)
5470 return;
5471 e1000_write_smbus_addr(hw);
5472 hw->phy.ops.release(hw);
5473 }
5474}
5475
5476/**
5477 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5478 * @hw: pointer to the HW structure
5479 *
5480 * During Sx to S0 transitions on non-managed devices or managed devices
5481 * on which PHY resets are not blocked, if the PHY registers cannot be
5482 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5483 * the PHY.
5484 * On i217, setup Intel Rapid Start Technology.
5485 **/
5486void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5487{
5488 s32 ret_val;
5489
5490 if (hw->mac.type < e1000_pch2lan)
5491 return;
5492
5493 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5494 if (ret_val) {
5495 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5496 return;
5497 }
5498
5499 /* For i217 Intel Rapid Start Technology support when the system
5500 * is transitioning from Sx and no manageability engine is present
5501 * configure SMBus to restore on reset, disable proxy, and enable
5502 * the reset on MTA (Multicast table array).
5503 */
5504 if (hw->phy.type == e1000_phy_i217) {
5505 u16 phy_reg;
5506
5507 ret_val = hw->phy.ops.acquire(hw);
5508 if (ret_val) {
5509 e_dbg("Failed to setup iRST\n");
5510 return;
5511 }
5512
5513 /* Clear Auto Enable LPI after link up */
5514 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5515 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5516 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5517
5518 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5519 /* Restore clear on SMB if no manageability engine
5520 * is present
5521 */
5522 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5523 if (ret_val)
5524 goto release;
5525 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5526 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5527
5528 /* Disable Proxy */
5529 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5530 }
5531 /* Enable reset on MTA */
5532 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5533 if (ret_val)
5534 goto release;
5535 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5536 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5537release:
5538 if (ret_val)
5539 e_dbg("Error %d in resume workarounds\n", ret_val);
5540 hw->phy.ops.release(hw);
5541 }
5542}
5543
5544/**
5545 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5546 * @hw: pointer to the HW structure
5547 *
5548 * Return the LED back to the default configuration.
5549 **/
5550static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5551{
5552 if (hw->phy.type == e1000_phy_ife)
5553 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5554
5555 ew32(LEDCTL, hw->mac.ledctl_default);
5556 return 0;
5557}
5558
5559/**
5560 * e1000_led_on_ich8lan - Turn LEDs on
5561 * @hw: pointer to the HW structure
5562 *
5563 * Turn on the LEDs.
5564 **/
5565static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5566{
5567 if (hw->phy.type == e1000_phy_ife)
5568 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5569 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5570
5571 ew32(LEDCTL, hw->mac.ledctl_mode2);
5572 return 0;
5573}
5574
5575/**
5576 * e1000_led_off_ich8lan - Turn LEDs off
5577 * @hw: pointer to the HW structure
5578 *
5579 * Turn off the LEDs.
5580 **/
5581static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5582{
5583 if (hw->phy.type == e1000_phy_ife)
5584 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5585 (IFE_PSCL_PROBE_MODE |
5586 IFE_PSCL_PROBE_LEDS_OFF));
5587
5588 ew32(LEDCTL, hw->mac.ledctl_mode1);
5589 return 0;
5590}
5591
5592/**
5593 * e1000_setup_led_pchlan - Configures SW controllable LED
5594 * @hw: pointer to the HW structure
5595 *
5596 * This prepares the SW controllable LED for use.
5597 **/
5598static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5599{
5600 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5601}
5602
5603/**
5604 * e1000_cleanup_led_pchlan - Restore the default LED operation
5605 * @hw: pointer to the HW structure
5606 *
5607 * Return the LED back to the default configuration.
5608 **/
5609static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5610{
5611 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5612}
5613
5614/**
5615 * e1000_led_on_pchlan - Turn LEDs on
5616 * @hw: pointer to the HW structure
5617 *
5618 * Turn on the LEDs.
5619 **/
5620static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5621{
5622 u16 data = (u16)hw->mac.ledctl_mode2;
5623 u32 i, led;
5624
5625 /* If no link, then turn LED on by setting the invert bit
5626 * for each LED that's mode is "link_up" in ledctl_mode2.
5627 */
5628 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5629 for (i = 0; i < 3; i++) {
5630 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5631 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5632 E1000_LEDCTL_MODE_LINK_UP)
5633 continue;
5634 if (led & E1000_PHY_LED0_IVRT)
5635 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5636 else
5637 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5638 }
5639 }
5640
5641 return e1e_wphy(hw, HV_LED_CONFIG, data);
5642}
5643
5644/**
5645 * e1000_led_off_pchlan - Turn LEDs off
5646 * @hw: pointer to the HW structure
5647 *
5648 * Turn off the LEDs.
5649 **/
5650static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5651{
5652 u16 data = (u16)hw->mac.ledctl_mode1;
5653 u32 i, led;
5654
5655 /* If no link, then turn LED off by clearing the invert bit
5656 * for each LED that's mode is "link_up" in ledctl_mode1.
5657 */
5658 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5659 for (i = 0; i < 3; i++) {
5660 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5661 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5662 E1000_LEDCTL_MODE_LINK_UP)
5663 continue;
5664 if (led & E1000_PHY_LED0_IVRT)
5665 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5666 else
5667 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5668 }
5669 }
5670
5671 return e1e_wphy(hw, HV_LED_CONFIG, data);
5672}
5673
5674/**
5675 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5676 * @hw: pointer to the HW structure
5677 *
5678 * Read appropriate register for the config done bit for completion status
5679 * and configure the PHY through s/w for EEPROM-less parts.
5680 *
5681 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5682 * config done bit, so only an error is logged and continues. If we were
5683 * to return with error, EEPROM-less silicon would not be able to be reset
5684 * or change link.
5685 **/
5686static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5687{
5688 s32 ret_val = 0;
5689 u32 bank = 0;
5690 u32 status;
5691
5692 e1000e_get_cfg_done_generic(hw);
5693
5694 /* Wait for indication from h/w that it has completed basic config */
5695 if (hw->mac.type >= e1000_ich10lan) {
5696 e1000_lan_init_done_ich8lan(hw);
5697 } else {
5698 ret_val = e1000e_get_auto_rd_done(hw);
5699 if (ret_val) {
5700 /* When auto config read does not complete, do not
5701 * return with an error. This can happen in situations
5702 * where there is no eeprom and prevents getting link.
5703 */
5704 e_dbg("Auto Read Done did not complete\n");
5705 ret_val = 0;
5706 }
5707 }
5708
5709 /* Clear PHY Reset Asserted bit */
5710 status = er32(STATUS);
5711 if (status & E1000_STATUS_PHYRA)
5712 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5713 else
5714 e_dbg("PHY Reset Asserted not set - needs delay\n");
5715
5716 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5717 if (hw->mac.type <= e1000_ich9lan) {
5718 if (!(er32(EECD) & E1000_EECD_PRES) &&
5719 (hw->phy.type == e1000_phy_igp_3)) {
5720 e1000e_phy_init_script_igp3(hw);
5721 }
5722 } else {
5723 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5724 /* Maybe we should do a basic PHY config */
5725 e_dbg("EEPROM not present\n");
5726 ret_val = -E1000_ERR_CONFIG;
5727 }
5728 }
5729
5730 return ret_val;
5731}
5732
5733/**
5734 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5735 * @hw: pointer to the HW structure
5736 *
5737 * In the case of a PHY power down to save power, or to turn off link during a
5738 * driver unload, or wake on lan is not enabled, remove the link.
5739 **/
5740static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5741{
5742 /* If the management interface is not enabled, then power down */
5743 if (!(hw->mac.ops.check_mng_mode(hw) ||
5744 hw->phy.ops.check_reset_block(hw)))
5745 e1000_power_down_phy_copper(hw);
5746}
5747
5748/**
5749 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5750 * @hw: pointer to the HW structure
5751 *
5752 * Clears hardware counters specific to the silicon family and calls
5753 * clear_hw_cntrs_generic to clear all general purpose counters.
5754 **/
5755static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5756{
5757 u16 phy_data;
5758 s32 ret_val;
5759
5760 e1000e_clear_hw_cntrs_base(hw);
5761
5762 er32(ALGNERRC);
5763 er32(RXERRC);
5764 er32(TNCRS);
5765 er32(CEXTERR);
5766 er32(TSCTC);
5767 er32(TSCTFC);
5768
5769 er32(MGTPRC);
5770 er32(MGTPDC);
5771 er32(MGTPTC);
5772
5773 er32(IAC);
5774 er32(ICRXOC);
5775
5776 /* Clear PHY statistics registers */
5777 if ((hw->phy.type == e1000_phy_82578) ||
5778 (hw->phy.type == e1000_phy_82579) ||
5779 (hw->phy.type == e1000_phy_i217) ||
5780 (hw->phy.type == e1000_phy_82577)) {
5781 ret_val = hw->phy.ops.acquire(hw);
5782 if (ret_val)
5783 return;
5784 ret_val = hw->phy.ops.set_page(hw,
5785 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5786 if (ret_val)
5787 goto release;
5788 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5789 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5790 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5791 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5792 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5793 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5794 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5795 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5796 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5797 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5798 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5799 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5800 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5801 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5802release:
5803 hw->phy.ops.release(hw);
5804 }
5805}
5806
5807static const struct e1000_mac_operations ich8_mac_ops = {
5808 /* check_mng_mode dependent on mac type */
5809 .check_for_link = e1000_check_for_copper_link_ich8lan,
5810 /* cleanup_led dependent on mac type */
5811 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5812 .get_bus_info = e1000_get_bus_info_ich8lan,
5813 .set_lan_id = e1000_set_lan_id_single_port,
5814 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5815 /* led_on dependent on mac type */
5816 /* led_off dependent on mac type */
5817 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5818 .reset_hw = e1000_reset_hw_ich8lan,
5819 .init_hw = e1000_init_hw_ich8lan,
5820 .setup_link = e1000_setup_link_ich8lan,
5821 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5822 /* id_led_init dependent on mac type */
5823 .config_collision_dist = e1000e_config_collision_dist_generic,
5824 .rar_set = e1000e_rar_set_generic,
5825 .rar_get_count = e1000e_rar_get_count_generic,
5826};
5827
5828static const struct e1000_phy_operations ich8_phy_ops = {
5829 .acquire = e1000_acquire_swflag_ich8lan,
5830 .check_reset_block = e1000_check_reset_block_ich8lan,
5831 .commit = NULL,
5832 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5833 .get_cable_length = e1000e_get_cable_length_igp_2,
5834 .read_reg = e1000e_read_phy_reg_igp,
5835 .release = e1000_release_swflag_ich8lan,
5836 .reset = e1000_phy_hw_reset_ich8lan,
5837 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5838 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5839 .write_reg = e1000e_write_phy_reg_igp,
5840};
5841
5842static const struct e1000_nvm_operations ich8_nvm_ops = {
5843 .acquire = e1000_acquire_nvm_ich8lan,
5844 .read = e1000_read_nvm_ich8lan,
5845 .release = e1000_release_nvm_ich8lan,
5846 .reload = e1000e_reload_nvm_generic,
5847 .update = e1000_update_nvm_checksum_ich8lan,
5848 .valid_led_default = e1000_valid_led_default_ich8lan,
5849 .validate = e1000_validate_nvm_checksum_ich8lan,
5850 .write = e1000_write_nvm_ich8lan,
5851};
5852
5853static const struct e1000_nvm_operations spt_nvm_ops = {
5854 .acquire = e1000_acquire_nvm_ich8lan,
5855 .release = e1000_release_nvm_ich8lan,
5856 .read = e1000_read_nvm_spt,
5857 .update = e1000_update_nvm_checksum_spt,
5858 .reload = e1000e_reload_nvm_generic,
5859 .valid_led_default = e1000_valid_led_default_ich8lan,
5860 .validate = e1000_validate_nvm_checksum_ich8lan,
5861 .write = e1000_write_nvm_ich8lan,
5862};
5863
5864const struct e1000_info e1000_ich8_info = {
5865 .mac = e1000_ich8lan,
5866 .flags = FLAG_HAS_WOL
5867 | FLAG_IS_ICH
5868 | FLAG_HAS_CTRLEXT_ON_LOAD
5869 | FLAG_HAS_AMT
5870 | FLAG_HAS_FLASH
5871 | FLAG_APME_IN_WUC,
5872 .pba = 8,
5873 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5874 .get_variants = e1000_get_variants_ich8lan,
5875 .mac_ops = &ich8_mac_ops,
5876 .phy_ops = &ich8_phy_ops,
5877 .nvm_ops = &ich8_nvm_ops,
5878};
5879
5880const struct e1000_info e1000_ich9_info = {
5881 .mac = e1000_ich9lan,
5882 .flags = FLAG_HAS_JUMBO_FRAMES
5883 | FLAG_IS_ICH
5884 | FLAG_HAS_WOL
5885 | FLAG_HAS_CTRLEXT_ON_LOAD
5886 | FLAG_HAS_AMT
5887 | FLAG_HAS_FLASH
5888 | FLAG_APME_IN_WUC,
5889 .pba = 18,
5890 .max_hw_frame_size = DEFAULT_JUMBO,
5891 .get_variants = e1000_get_variants_ich8lan,
5892 .mac_ops = &ich8_mac_ops,
5893 .phy_ops = &ich8_phy_ops,
5894 .nvm_ops = &ich8_nvm_ops,
5895};
5896
5897const struct e1000_info e1000_ich10_info = {
5898 .mac = e1000_ich10lan,
5899 .flags = FLAG_HAS_JUMBO_FRAMES
5900 | FLAG_IS_ICH
5901 | FLAG_HAS_WOL
5902 | FLAG_HAS_CTRLEXT_ON_LOAD
5903 | FLAG_HAS_AMT
5904 | FLAG_HAS_FLASH
5905 | FLAG_APME_IN_WUC,
5906 .pba = 18,
5907 .max_hw_frame_size = DEFAULT_JUMBO,
5908 .get_variants = e1000_get_variants_ich8lan,
5909 .mac_ops = &ich8_mac_ops,
5910 .phy_ops = &ich8_phy_ops,
5911 .nvm_ops = &ich8_nvm_ops,
5912};
5913
5914const struct e1000_info e1000_pch_info = {
5915 .mac = e1000_pchlan,
5916 .flags = FLAG_IS_ICH
5917 | FLAG_HAS_WOL
5918 | FLAG_HAS_CTRLEXT_ON_LOAD
5919 | FLAG_HAS_AMT
5920 | FLAG_HAS_FLASH
5921 | FLAG_HAS_JUMBO_FRAMES
5922 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5923 | FLAG_APME_IN_WUC,
5924 .flags2 = FLAG2_HAS_PHY_STATS,
5925 .pba = 26,
5926 .max_hw_frame_size = 4096,
5927 .get_variants = e1000_get_variants_ich8lan,
5928 .mac_ops = &ich8_mac_ops,
5929 .phy_ops = &ich8_phy_ops,
5930 .nvm_ops = &ich8_nvm_ops,
5931};
5932
5933const struct e1000_info e1000_pch2_info = {
5934 .mac = e1000_pch2lan,
5935 .flags = FLAG_IS_ICH
5936 | FLAG_HAS_WOL
5937 | FLAG_HAS_HW_TIMESTAMP
5938 | FLAG_HAS_CTRLEXT_ON_LOAD
5939 | FLAG_HAS_AMT
5940 | FLAG_HAS_FLASH
5941 | FLAG_HAS_JUMBO_FRAMES
5942 | FLAG_APME_IN_WUC,
5943 .flags2 = FLAG2_HAS_PHY_STATS
5944 | FLAG2_HAS_EEE
5945 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5946 .pba = 26,
5947 .max_hw_frame_size = 9022,
5948 .get_variants = e1000_get_variants_ich8lan,
5949 .mac_ops = &ich8_mac_ops,
5950 .phy_ops = &ich8_phy_ops,
5951 .nvm_ops = &ich8_nvm_ops,
5952};
5953
5954const struct e1000_info e1000_pch_lpt_info = {
5955 .mac = e1000_pch_lpt,
5956 .flags = FLAG_IS_ICH
5957 | FLAG_HAS_WOL
5958 | FLAG_HAS_HW_TIMESTAMP
5959 | FLAG_HAS_CTRLEXT_ON_LOAD
5960 | FLAG_HAS_AMT
5961 | FLAG_HAS_FLASH
5962 | FLAG_HAS_JUMBO_FRAMES
5963 | FLAG_APME_IN_WUC,
5964 .flags2 = FLAG2_HAS_PHY_STATS
5965 | FLAG2_HAS_EEE
5966 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5967 .pba = 26,
5968 .max_hw_frame_size = 9022,
5969 .get_variants = e1000_get_variants_ich8lan,
5970 .mac_ops = &ich8_mac_ops,
5971 .phy_ops = &ich8_phy_ops,
5972 .nvm_ops = &ich8_nvm_ops,
5973};
5974
5975const struct e1000_info e1000_pch_spt_info = {
5976 .mac = e1000_pch_spt,
5977 .flags = FLAG_IS_ICH
5978 | FLAG_HAS_WOL
5979 | FLAG_HAS_HW_TIMESTAMP
5980 | FLAG_HAS_CTRLEXT_ON_LOAD
5981 | FLAG_HAS_AMT
5982 | FLAG_HAS_FLASH
5983 | FLAG_HAS_JUMBO_FRAMES
5984 | FLAG_APME_IN_WUC,
5985 .flags2 = FLAG2_HAS_PHY_STATS
5986 | FLAG2_HAS_EEE,
5987 .pba = 26,
5988 .max_hw_frame_size = 9022,
5989 .get_variants = e1000_get_variants_ich8lan,
5990 .mac_ops = &ich8_mac_ops,
5991 .phy_ops = &ich8_phy_ops,
5992 .nvm_ops = &spt_nvm_ops,
5993};
5994
5995const struct e1000_info e1000_pch_cnp_info = {
5996 .mac = e1000_pch_cnp,
5997 .flags = FLAG_IS_ICH
5998 | FLAG_HAS_WOL
5999 | FLAG_HAS_HW_TIMESTAMP
6000 | FLAG_HAS_CTRLEXT_ON_LOAD
6001 | FLAG_HAS_AMT
6002 | FLAG_HAS_FLASH
6003 | FLAG_HAS_JUMBO_FRAMES
6004 | FLAG_APME_IN_WUC,
6005 .flags2 = FLAG2_HAS_PHY_STATS
6006 | FLAG2_HAS_EEE,
6007 .pba = 26,
6008 .max_hw_frame_size = 9022,
6009 .get_variants = e1000_get_variants_ich8lan,
6010 .mac_ops = &ich8_mac_ops,
6011 .phy_ops = &ich8_phy_ops,
6012 .nvm_ops = &spt_nvm_ops,
6013};
6014
6015const struct e1000_info e1000_pch_tgp_info = {
6016 .mac = e1000_pch_tgp,
6017 .flags = FLAG_IS_ICH
6018 | FLAG_HAS_WOL
6019 | FLAG_HAS_HW_TIMESTAMP
6020 | FLAG_HAS_CTRLEXT_ON_LOAD
6021 | FLAG_HAS_AMT
6022 | FLAG_HAS_FLASH
6023 | FLAG_HAS_JUMBO_FRAMES
6024 | FLAG_APME_IN_WUC,
6025 .flags2 = FLAG2_HAS_PHY_STATS
6026 | FLAG2_HAS_EEE,
6027 .pba = 26,
6028 .max_hw_frame_size = 9022,
6029 .get_variants = e1000_get_variants_ich8lan,
6030 .mac_ops = &ich8_mac_ops,
6031 .phy_ops = &ich8_phy_ops,
6032 .nvm_ops = &spt_nvm_ops,
6033};
6034
6035const struct e1000_info e1000_pch_adp_info = {
6036 .mac = e1000_pch_adp,
6037 .flags = FLAG_IS_ICH
6038 | FLAG_HAS_WOL
6039 | FLAG_HAS_HW_TIMESTAMP
6040 | FLAG_HAS_CTRLEXT_ON_LOAD
6041 | FLAG_HAS_AMT
6042 | FLAG_HAS_FLASH
6043 | FLAG_HAS_JUMBO_FRAMES
6044 | FLAG_APME_IN_WUC,
6045 .flags2 = FLAG2_HAS_PHY_STATS
6046 | FLAG2_HAS_EEE,
6047 .pba = 26,
6048 .max_hw_frame_size = 9022,
6049 .get_variants = e1000_get_variants_ich8lan,
6050 .mac_ops = &ich8_mac_ops,
6051 .phy_ops = &ich8_phy_ops,
6052 .nvm_ops = &spt_nvm_ops,
6053};
6054
6055const struct e1000_info e1000_pch_mtp_info = {
6056 .mac = e1000_pch_mtp,
6057 .flags = FLAG_IS_ICH
6058 | FLAG_HAS_WOL
6059 | FLAG_HAS_HW_TIMESTAMP
6060 | FLAG_HAS_CTRLEXT_ON_LOAD
6061 | FLAG_HAS_AMT
6062 | FLAG_HAS_FLASH
6063 | FLAG_HAS_JUMBO_FRAMES
6064 | FLAG_APME_IN_WUC,
6065 .flags2 = FLAG2_HAS_PHY_STATS
6066 | FLAG2_HAS_EEE,
6067 .pba = 26,
6068 .max_hw_frame_size = 9022,
6069 .get_variants = e1000_get_variants_ich8lan,
6070 .mac_ops = &ich8_mac_ops,
6071 .phy_ops = &ich8_phy_ops,
6072 .nvm_ops = &spt_nvm_ops,
6073};
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4/* 82562G 10/100 Network Connection
5 * 82562G-2 10/100 Network Connection
6 * 82562GT 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
8 * 82562V 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
11 * 82566DC Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
13 * 82566DM Gigabit Network Connection
14 * 82566MC Gigabit Network Connection
15 * 82566MM Gigabit Network Connection
16 * 82567LM Gigabit Network Connection
17 * 82567LF Gigabit Network Connection
18 * 82567V Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
22 * 82567LF-3 Gigabit Network Connection
23 * 82567LM-3 Gigabit Network Connection
24 * 82567LM-4 Gigabit Network Connection
25 * 82577LM Gigabit Network Connection
26 * 82577LC Gigabit Network Connection
27 * 82578DM Gigabit Network Connection
28 * 82578DC Gigabit Network Connection
29 * 82579LM Gigabit Network Connection
30 * 82579V Gigabit Network Connection
31 * Ethernet Connection I217-LM
32 * Ethernet Connection I217-V
33 * Ethernet Connection I218-V
34 * Ethernet Connection I218-LM
35 * Ethernet Connection (2) I218-LM
36 * Ethernet Connection (2) I218-V
37 * Ethernet Connection (3) I218-LM
38 * Ethernet Connection (3) I218-V
39 */
40
41#include "e1000.h"
42
43/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
44/* Offset 04h HSFSTS */
45union ich8_hws_flash_status {
46 struct ich8_hsfsts {
47 u16 flcdone:1; /* bit 0 Flash Cycle Done */
48 u16 flcerr:1; /* bit 1 Flash Cycle Error */
49 u16 dael:1; /* bit 2 Direct Access error Log */
50 u16 berasesz:2; /* bit 4:3 Sector Erase Size */
51 u16 flcinprog:1; /* bit 5 flash cycle in Progress */
52 u16 reserved1:2; /* bit 13:6 Reserved */
53 u16 reserved2:6; /* bit 13:6 Reserved */
54 u16 fldesvalid:1; /* bit 14 Flash Descriptor Valid */
55 u16 flockdn:1; /* bit 15 Flash Config Lock-Down */
56 } hsf_status;
57 u16 regval;
58};
59
60/* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
61/* Offset 06h FLCTL */
62union ich8_hws_flash_ctrl {
63 struct ich8_hsflctl {
64 u16 flcgo:1; /* 0 Flash Cycle Go */
65 u16 flcycle:2; /* 2:1 Flash Cycle */
66 u16 reserved:5; /* 7:3 Reserved */
67 u16 fldbcount:2; /* 9:8 Flash Data Byte Count */
68 u16 flockdn:6; /* 15:10 Reserved */
69 } hsf_ctrl;
70 u16 regval;
71};
72
73/* ICH Flash Region Access Permissions */
74union ich8_hws_flash_regacc {
75 struct ich8_flracc {
76 u32 grra:8; /* 0:7 GbE region Read Access */
77 u32 grwa:8; /* 8:15 GbE region Write Access */
78 u32 gmrag:8; /* 23:16 GbE Master Read Access Grant */
79 u32 gmwag:8; /* 31:24 GbE Master Write Access Grant */
80 } hsf_flregacc;
81 u16 regval;
82};
83
84/* ICH Flash Protected Region */
85union ich8_flash_protected_range {
86 struct ich8_pr {
87 u32 base:13; /* 0:12 Protected Range Base */
88 u32 reserved1:2; /* 13:14 Reserved */
89 u32 rpe:1; /* 15 Read Protection Enable */
90 u32 limit:13; /* 16:28 Protected Range Limit */
91 u32 reserved2:2; /* 29:30 Reserved */
92 u32 wpe:1; /* 31 Write Protection Enable */
93 } range;
94 u32 regval;
95};
96
97static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
98static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
99static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
100static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
101 u32 offset, u8 byte);
102static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
103 u8 *data);
104static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
105 u16 *data);
106static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
107 u8 size, u16 *data);
108static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
109 u32 *data);
110static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw,
111 u32 offset, u32 *data);
112static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw,
113 u32 offset, u32 data);
114static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
115 u32 offset, u32 dword);
116static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
117static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
118static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
119static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
120static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
121static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
122static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
123static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
124static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
125static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
126static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
127static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
128static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
129static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
130static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
131static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
132static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index);
133static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index);
134static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw);
135static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
136static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
137static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force);
138static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw);
139static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state);
140
141static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
142{
143 return readw(hw->flash_address + reg);
144}
145
146static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
147{
148 return readl(hw->flash_address + reg);
149}
150
151static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
152{
153 writew(val, hw->flash_address + reg);
154}
155
156static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
157{
158 writel(val, hw->flash_address + reg);
159}
160
161#define er16flash(reg) __er16flash(hw, (reg))
162#define er32flash(reg) __er32flash(hw, (reg))
163#define ew16flash(reg, val) __ew16flash(hw, (reg), (val))
164#define ew32flash(reg, val) __ew32flash(hw, (reg), (val))
165
166/**
167 * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers
168 * @hw: pointer to the HW structure
169 *
170 * Test access to the PHY registers by reading the PHY ID registers. If
171 * the PHY ID is already known (e.g. resume path) compare it with known ID,
172 * otherwise assume the read PHY ID is correct if it is valid.
173 *
174 * Assumes the sw/fw/hw semaphore is already acquired.
175 **/
176static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw)
177{
178 u16 phy_reg = 0;
179 u32 phy_id = 0;
180 s32 ret_val = 0;
181 u16 retry_count;
182 u32 mac_reg = 0;
183
184 for (retry_count = 0; retry_count < 2; retry_count++) {
185 ret_val = e1e_rphy_locked(hw, MII_PHYSID1, &phy_reg);
186 if (ret_val || (phy_reg == 0xFFFF))
187 continue;
188 phy_id = (u32)(phy_reg << 16);
189
190 ret_val = e1e_rphy_locked(hw, MII_PHYSID2, &phy_reg);
191 if (ret_val || (phy_reg == 0xFFFF)) {
192 phy_id = 0;
193 continue;
194 }
195 phy_id |= (u32)(phy_reg & PHY_REVISION_MASK);
196 break;
197 }
198
199 if (hw->phy.id) {
200 if (hw->phy.id == phy_id)
201 goto out;
202 } else if (phy_id) {
203 hw->phy.id = phy_id;
204 hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK);
205 goto out;
206 }
207
208 /* In case the PHY needs to be in mdio slow mode,
209 * set slow mode and try to get the PHY id again.
210 */
211 if (hw->mac.type < e1000_pch_lpt) {
212 hw->phy.ops.release(hw);
213 ret_val = e1000_set_mdio_slow_mode_hv(hw);
214 if (!ret_val)
215 ret_val = e1000e_get_phy_id(hw);
216 hw->phy.ops.acquire(hw);
217 }
218
219 if (ret_val)
220 return false;
221out:
222 if (hw->mac.type >= e1000_pch_lpt) {
223 /* Only unforce SMBus if ME is not active */
224 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
225 /* Unforce SMBus mode in PHY */
226 e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg);
227 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
228 e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg);
229
230 /* Unforce SMBus mode in MAC */
231 mac_reg = er32(CTRL_EXT);
232 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
233 ew32(CTRL_EXT, mac_reg);
234 }
235 }
236
237 return true;
238}
239
240/**
241 * e1000_toggle_lanphypc_pch_lpt - toggle the LANPHYPC pin value
242 * @hw: pointer to the HW structure
243 *
244 * Toggling the LANPHYPC pin value fully power-cycles the PHY and is
245 * used to reset the PHY to a quiescent state when necessary.
246 **/
247static void e1000_toggle_lanphypc_pch_lpt(struct e1000_hw *hw)
248{
249 u32 mac_reg;
250
251 /* Set Phy Config Counter to 50msec */
252 mac_reg = er32(FEXTNVM3);
253 mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
254 mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
255 ew32(FEXTNVM3, mac_reg);
256
257 /* Toggle LANPHYPC Value bit */
258 mac_reg = er32(CTRL);
259 mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE;
260 mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE;
261 ew32(CTRL, mac_reg);
262 e1e_flush();
263 usleep_range(10, 20);
264 mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
265 ew32(CTRL, mac_reg);
266 e1e_flush();
267
268 if (hw->mac.type < e1000_pch_lpt) {
269 msleep(50);
270 } else {
271 u16 count = 20;
272
273 do {
274 usleep_range(5000, 6000);
275 } while (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LPCD) && count--);
276
277 msleep(30);
278 }
279}
280
281/**
282 * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds
283 * @hw: pointer to the HW structure
284 *
285 * Workarounds/flow necessary for PHY initialization during driver load
286 * and resume paths.
287 **/
288static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw)
289{
290 struct e1000_adapter *adapter = hw->adapter;
291 u32 mac_reg, fwsm = er32(FWSM);
292 s32 ret_val;
293
294 /* Gate automatic PHY configuration by hardware on managed and
295 * non-managed 82579 and newer adapters.
296 */
297 e1000_gate_hw_phy_config_ich8lan(hw, true);
298
299 /* It is not possible to be certain of the current state of ULP
300 * so forcibly disable it.
301 */
302 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown;
303 ret_val = e1000_disable_ulp_lpt_lp(hw, true);
304 if (ret_val)
305 e_warn("Failed to disable ULP\n");
306
307 ret_val = hw->phy.ops.acquire(hw);
308 if (ret_val) {
309 e_dbg("Failed to initialize PHY flow\n");
310 goto out;
311 }
312
313 /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is
314 * inaccessible and resetting the PHY is not blocked, toggle the
315 * LANPHYPC Value bit to force the interconnect to PCIe mode.
316 */
317 switch (hw->mac.type) {
318 case e1000_pch_lpt:
319 case e1000_pch_spt:
320 case e1000_pch_cnp:
321 case e1000_pch_tgp:
322 case e1000_pch_adp:
323 if (e1000_phy_is_accessible_pchlan(hw))
324 break;
325
326 /* Before toggling LANPHYPC, see if PHY is accessible by
327 * forcing MAC to SMBus mode first.
328 */
329 mac_reg = er32(CTRL_EXT);
330 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
331 ew32(CTRL_EXT, mac_reg);
332
333 /* Wait 50 milliseconds for MAC to finish any retries
334 * that it might be trying to perform from previous
335 * attempts to acknowledge any phy read requests.
336 */
337 msleep(50);
338
339 fallthrough;
340 case e1000_pch2lan:
341 if (e1000_phy_is_accessible_pchlan(hw))
342 break;
343
344 fallthrough;
345 case e1000_pchlan:
346 if ((hw->mac.type == e1000_pchlan) &&
347 (fwsm & E1000_ICH_FWSM_FW_VALID))
348 break;
349
350 if (hw->phy.ops.check_reset_block(hw)) {
351 e_dbg("Required LANPHYPC toggle blocked by ME\n");
352 ret_val = -E1000_ERR_PHY;
353 break;
354 }
355
356 /* Toggle LANPHYPC Value bit */
357 e1000_toggle_lanphypc_pch_lpt(hw);
358 if (hw->mac.type >= e1000_pch_lpt) {
359 if (e1000_phy_is_accessible_pchlan(hw))
360 break;
361
362 /* Toggling LANPHYPC brings the PHY out of SMBus mode
363 * so ensure that the MAC is also out of SMBus mode
364 */
365 mac_reg = er32(CTRL_EXT);
366 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
367 ew32(CTRL_EXT, mac_reg);
368
369 if (e1000_phy_is_accessible_pchlan(hw))
370 break;
371
372 ret_val = -E1000_ERR_PHY;
373 }
374 break;
375 default:
376 break;
377 }
378
379 hw->phy.ops.release(hw);
380 if (!ret_val) {
381
382 /* Check to see if able to reset PHY. Print error if not */
383 if (hw->phy.ops.check_reset_block(hw)) {
384 e_err("Reset blocked by ME\n");
385 goto out;
386 }
387
388 /* Reset the PHY before any access to it. Doing so, ensures
389 * that the PHY is in a known good state before we read/write
390 * PHY registers. The generic reset is sufficient here,
391 * because we haven't determined the PHY type yet.
392 */
393 ret_val = e1000e_phy_hw_reset_generic(hw);
394 if (ret_val)
395 goto out;
396
397 /* On a successful reset, possibly need to wait for the PHY
398 * to quiesce to an accessible state before returning control
399 * to the calling function. If the PHY does not quiesce, then
400 * return E1000E_BLK_PHY_RESET, as this is the condition that
401 * the PHY is in.
402 */
403 ret_val = hw->phy.ops.check_reset_block(hw);
404 if (ret_val)
405 e_err("ME blocked access to PHY after reset\n");
406 }
407
408out:
409 /* Ungate automatic PHY configuration on non-managed 82579 */
410 if ((hw->mac.type == e1000_pch2lan) &&
411 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
412 usleep_range(10000, 11000);
413 e1000_gate_hw_phy_config_ich8lan(hw, false);
414 }
415
416 return ret_val;
417}
418
419/**
420 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
421 * @hw: pointer to the HW structure
422 *
423 * Initialize family-specific PHY parameters and function pointers.
424 **/
425static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
426{
427 struct e1000_phy_info *phy = &hw->phy;
428 s32 ret_val;
429
430 phy->addr = 1;
431 phy->reset_delay_us = 100;
432
433 phy->ops.set_page = e1000_set_page_igp;
434 phy->ops.read_reg = e1000_read_phy_reg_hv;
435 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
436 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
437 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
438 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
439 phy->ops.write_reg = e1000_write_phy_reg_hv;
440 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
441 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
442 phy->ops.power_up = e1000_power_up_phy_copper;
443 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
444 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
445
446 phy->id = e1000_phy_unknown;
447
448 ret_val = e1000_init_phy_workarounds_pchlan(hw);
449 if (ret_val)
450 return ret_val;
451
452 if (phy->id == e1000_phy_unknown)
453 switch (hw->mac.type) {
454 default:
455 ret_val = e1000e_get_phy_id(hw);
456 if (ret_val)
457 return ret_val;
458 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
459 break;
460 fallthrough;
461 case e1000_pch2lan:
462 case e1000_pch_lpt:
463 case e1000_pch_spt:
464 case e1000_pch_cnp:
465 case e1000_pch_tgp:
466 case e1000_pch_adp:
467 /* In case the PHY needs to be in mdio slow mode,
468 * set slow mode and try to get the PHY id again.
469 */
470 ret_val = e1000_set_mdio_slow_mode_hv(hw);
471 if (ret_val)
472 return ret_val;
473 ret_val = e1000e_get_phy_id(hw);
474 if (ret_val)
475 return ret_val;
476 break;
477 }
478 phy->type = e1000e_get_phy_type_from_id(phy->id);
479
480 switch (phy->type) {
481 case e1000_phy_82577:
482 case e1000_phy_82579:
483 case e1000_phy_i217:
484 phy->ops.check_polarity = e1000_check_polarity_82577;
485 phy->ops.force_speed_duplex =
486 e1000_phy_force_speed_duplex_82577;
487 phy->ops.get_cable_length = e1000_get_cable_length_82577;
488 phy->ops.get_info = e1000_get_phy_info_82577;
489 phy->ops.commit = e1000e_phy_sw_reset;
490 break;
491 case e1000_phy_82578:
492 phy->ops.check_polarity = e1000_check_polarity_m88;
493 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
494 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
495 phy->ops.get_info = e1000e_get_phy_info_m88;
496 break;
497 default:
498 ret_val = -E1000_ERR_PHY;
499 break;
500 }
501
502 return ret_val;
503}
504
505/**
506 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
507 * @hw: pointer to the HW structure
508 *
509 * Initialize family-specific PHY parameters and function pointers.
510 **/
511static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
512{
513 struct e1000_phy_info *phy = &hw->phy;
514 s32 ret_val;
515 u16 i = 0;
516
517 phy->addr = 1;
518 phy->reset_delay_us = 100;
519
520 phy->ops.power_up = e1000_power_up_phy_copper;
521 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
522
523 /* We may need to do this twice - once for IGP and if that fails,
524 * we'll set BM func pointers and try again
525 */
526 ret_val = e1000e_determine_phy_address(hw);
527 if (ret_val) {
528 phy->ops.write_reg = e1000e_write_phy_reg_bm;
529 phy->ops.read_reg = e1000e_read_phy_reg_bm;
530 ret_val = e1000e_determine_phy_address(hw);
531 if (ret_val) {
532 e_dbg("Cannot determine PHY addr. Erroring out\n");
533 return ret_val;
534 }
535 }
536
537 phy->id = 0;
538 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
539 (i++ < 100)) {
540 usleep_range(1000, 1100);
541 ret_val = e1000e_get_phy_id(hw);
542 if (ret_val)
543 return ret_val;
544 }
545
546 /* Verify phy id */
547 switch (phy->id) {
548 case IGP03E1000_E_PHY_ID:
549 phy->type = e1000_phy_igp_3;
550 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
551 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
552 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
553 phy->ops.get_info = e1000e_get_phy_info_igp;
554 phy->ops.check_polarity = e1000_check_polarity_igp;
555 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
556 break;
557 case IFE_E_PHY_ID:
558 case IFE_PLUS_E_PHY_ID:
559 case IFE_C_E_PHY_ID:
560 phy->type = e1000_phy_ife;
561 phy->autoneg_mask = E1000_ALL_NOT_GIG;
562 phy->ops.get_info = e1000_get_phy_info_ife;
563 phy->ops.check_polarity = e1000_check_polarity_ife;
564 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
565 break;
566 case BME1000_E_PHY_ID:
567 phy->type = e1000_phy_bm;
568 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
569 phy->ops.read_reg = e1000e_read_phy_reg_bm;
570 phy->ops.write_reg = e1000e_write_phy_reg_bm;
571 phy->ops.commit = e1000e_phy_sw_reset;
572 phy->ops.get_info = e1000e_get_phy_info_m88;
573 phy->ops.check_polarity = e1000_check_polarity_m88;
574 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
575 break;
576 default:
577 return -E1000_ERR_PHY;
578 }
579
580 return 0;
581}
582
583/**
584 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
585 * @hw: pointer to the HW structure
586 *
587 * Initialize family-specific NVM parameters and function
588 * pointers.
589 **/
590static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
591{
592 struct e1000_nvm_info *nvm = &hw->nvm;
593 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
594 u32 gfpreg, sector_base_addr, sector_end_addr;
595 u16 i;
596 u32 nvm_size;
597
598 nvm->type = e1000_nvm_flash_sw;
599
600 if (hw->mac.type >= e1000_pch_spt) {
601 /* in SPT, gfpreg doesn't exist. NVM size is taken from the
602 * STRAP register. This is because in SPT the GbE Flash region
603 * is no longer accessed through the flash registers. Instead,
604 * the mechanism has changed, and the Flash region access
605 * registers are now implemented in GbE memory space.
606 */
607 nvm->flash_base_addr = 0;
608 nvm_size = (((er32(STRAP) >> 1) & 0x1F) + 1)
609 * NVM_SIZE_MULTIPLIER;
610 nvm->flash_bank_size = nvm_size / 2;
611 /* Adjust to word count */
612 nvm->flash_bank_size /= sizeof(u16);
613 /* Set the base address for flash register access */
614 hw->flash_address = hw->hw_addr + E1000_FLASH_BASE_ADDR;
615 } else {
616 /* Can't read flash registers if register set isn't mapped. */
617 if (!hw->flash_address) {
618 e_dbg("ERROR: Flash registers not mapped\n");
619 return -E1000_ERR_CONFIG;
620 }
621
622 gfpreg = er32flash(ICH_FLASH_GFPREG);
623
624 /* sector_X_addr is a "sector"-aligned address (4096 bytes)
625 * Add 1 to sector_end_addr since this sector is included in
626 * the overall size.
627 */
628 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
629 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
630
631 /* flash_base_addr is byte-aligned */
632 nvm->flash_base_addr = sector_base_addr
633 << FLASH_SECTOR_ADDR_SHIFT;
634
635 /* find total size of the NVM, then cut in half since the total
636 * size represents two separate NVM banks.
637 */
638 nvm->flash_bank_size = ((sector_end_addr - sector_base_addr)
639 << FLASH_SECTOR_ADDR_SHIFT);
640 nvm->flash_bank_size /= 2;
641 /* Adjust to word count */
642 nvm->flash_bank_size /= sizeof(u16);
643 }
644
645 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
646
647 /* Clear shadow ram */
648 for (i = 0; i < nvm->word_size; i++) {
649 dev_spec->shadow_ram[i].modified = false;
650 dev_spec->shadow_ram[i].value = 0xFFFF;
651 }
652
653 return 0;
654}
655
656/**
657 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
658 * @hw: pointer to the HW structure
659 *
660 * Initialize family-specific MAC parameters and function
661 * pointers.
662 **/
663static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw)
664{
665 struct e1000_mac_info *mac = &hw->mac;
666
667 /* Set media type function pointer */
668 hw->phy.media_type = e1000_media_type_copper;
669
670 /* Set mta register count */
671 mac->mta_reg_count = 32;
672 /* Set rar entry count */
673 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
674 if (mac->type == e1000_ich8lan)
675 mac->rar_entry_count--;
676 /* FWSM register */
677 mac->has_fwsm = true;
678 /* ARC subsystem not supported */
679 mac->arc_subsystem_valid = false;
680 /* Adaptive IFS supported */
681 mac->adaptive_ifs = true;
682
683 /* LED and other operations */
684 switch (mac->type) {
685 case e1000_ich8lan:
686 case e1000_ich9lan:
687 case e1000_ich10lan:
688 /* check management mode */
689 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
690 /* ID LED init */
691 mac->ops.id_led_init = e1000e_id_led_init_generic;
692 /* blink LED */
693 mac->ops.blink_led = e1000e_blink_led_generic;
694 /* setup LED */
695 mac->ops.setup_led = e1000e_setup_led_generic;
696 /* cleanup LED */
697 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
698 /* turn on/off LED */
699 mac->ops.led_on = e1000_led_on_ich8lan;
700 mac->ops.led_off = e1000_led_off_ich8lan;
701 break;
702 case e1000_pch2lan:
703 mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES;
704 mac->ops.rar_set = e1000_rar_set_pch2lan;
705 fallthrough;
706 case e1000_pch_lpt:
707 case e1000_pch_spt:
708 case e1000_pch_cnp:
709 case e1000_pch_tgp:
710 case e1000_pch_adp:
711 case e1000_pchlan:
712 /* check management mode */
713 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
714 /* ID LED init */
715 mac->ops.id_led_init = e1000_id_led_init_pchlan;
716 /* setup LED */
717 mac->ops.setup_led = e1000_setup_led_pchlan;
718 /* cleanup LED */
719 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
720 /* turn on/off LED */
721 mac->ops.led_on = e1000_led_on_pchlan;
722 mac->ops.led_off = e1000_led_off_pchlan;
723 break;
724 default:
725 break;
726 }
727
728 if (mac->type >= e1000_pch_lpt) {
729 mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES;
730 mac->ops.rar_set = e1000_rar_set_pch_lpt;
731 mac->ops.setup_physical_interface =
732 e1000_setup_copper_link_pch_lpt;
733 mac->ops.rar_get_count = e1000_rar_get_count_pch_lpt;
734 }
735
736 /* Enable PCS Lock-loss workaround for ICH8 */
737 if (mac->type == e1000_ich8lan)
738 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
739
740 return 0;
741}
742
743/**
744 * __e1000_access_emi_reg_locked - Read/write EMI register
745 * @hw: pointer to the HW structure
746 * @addr: EMI address to program
747 * @data: pointer to value to read/write from/to the EMI address
748 * @read: boolean flag to indicate read or write
749 *
750 * This helper function assumes the SW/FW/HW Semaphore is already acquired.
751 **/
752static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address,
753 u16 *data, bool read)
754{
755 s32 ret_val;
756
757 ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address);
758 if (ret_val)
759 return ret_val;
760
761 if (read)
762 ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data);
763 else
764 ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data);
765
766 return ret_val;
767}
768
769/**
770 * e1000_read_emi_reg_locked - Read Extended Management Interface register
771 * @hw: pointer to the HW structure
772 * @addr: EMI address to program
773 * @data: value to be read from the EMI address
774 *
775 * Assumes the SW/FW/HW Semaphore is already acquired.
776 **/
777s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data)
778{
779 return __e1000_access_emi_reg_locked(hw, addr, data, true);
780}
781
782/**
783 * e1000_write_emi_reg_locked - Write Extended Management Interface register
784 * @hw: pointer to the HW structure
785 * @addr: EMI address to program
786 * @data: value to be written to the EMI address
787 *
788 * Assumes the SW/FW/HW Semaphore is already acquired.
789 **/
790s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data)
791{
792 return __e1000_access_emi_reg_locked(hw, addr, &data, false);
793}
794
795/**
796 * e1000_set_eee_pchlan - Enable/disable EEE support
797 * @hw: pointer to the HW structure
798 *
799 * Enable/disable EEE based on setting in dev_spec structure, the duplex of
800 * the link and the EEE capabilities of the link partner. The LPI Control
801 * register bits will remain set only if/when link is up.
802 *
803 * EEE LPI must not be asserted earlier than one second after link is up.
804 * On 82579, EEE LPI should not be enabled until such time otherwise there
805 * can be link issues with some switches. Other devices can have EEE LPI
806 * enabled immediately upon link up since they have a timer in hardware which
807 * prevents LPI from being asserted too early.
808 **/
809s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
810{
811 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
812 s32 ret_val;
813 u16 lpa, pcs_status, adv, adv_addr, lpi_ctrl, data;
814
815 switch (hw->phy.type) {
816 case e1000_phy_82579:
817 lpa = I82579_EEE_LP_ABILITY;
818 pcs_status = I82579_EEE_PCS_STATUS;
819 adv_addr = I82579_EEE_ADVERTISEMENT;
820 break;
821 case e1000_phy_i217:
822 lpa = I217_EEE_LP_ABILITY;
823 pcs_status = I217_EEE_PCS_STATUS;
824 adv_addr = I217_EEE_ADVERTISEMENT;
825 break;
826 default:
827 return 0;
828 }
829
830 ret_val = hw->phy.ops.acquire(hw);
831 if (ret_val)
832 return ret_val;
833
834 ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl);
835 if (ret_val)
836 goto release;
837
838 /* Clear bits that enable EEE in various speeds */
839 lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK;
840
841 /* Enable EEE if not disabled by user */
842 if (!dev_spec->eee_disable) {
843 /* Save off link partner's EEE ability */
844 ret_val = e1000_read_emi_reg_locked(hw, lpa,
845 &dev_spec->eee_lp_ability);
846 if (ret_val)
847 goto release;
848
849 /* Read EEE advertisement */
850 ret_val = e1000_read_emi_reg_locked(hw, adv_addr, &adv);
851 if (ret_val)
852 goto release;
853
854 /* Enable EEE only for speeds in which the link partner is
855 * EEE capable and for which we advertise EEE.
856 */
857 if (adv & dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED)
858 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
859
860 if (adv & dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) {
861 e1e_rphy_locked(hw, MII_LPA, &data);
862 if (data & LPA_100FULL)
863 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
864 else
865 /* EEE is not supported in 100Half, so ignore
866 * partner's EEE in 100 ability if full-duplex
867 * is not advertised.
868 */
869 dev_spec->eee_lp_ability &=
870 ~I82579_EEE_100_SUPPORTED;
871 }
872 }
873
874 if (hw->phy.type == e1000_phy_82579) {
875 ret_val = e1000_read_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
876 &data);
877 if (ret_val)
878 goto release;
879
880 data &= ~I82579_LPI_100_PLL_SHUT;
881 ret_val = e1000_write_emi_reg_locked(hw, I82579_LPI_PLL_SHUT,
882 data);
883 }
884
885 /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */
886 ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data);
887 if (ret_val)
888 goto release;
889
890 ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl);
891release:
892 hw->phy.ops.release(hw);
893
894 return ret_val;
895}
896
897/**
898 * e1000_k1_workaround_lpt_lp - K1 workaround on Lynxpoint-LP
899 * @hw: pointer to the HW structure
900 * @link: link up bool flag
901 *
902 * When K1 is enabled for 1Gbps, the MAC can miss 2 DMA completion indications
903 * preventing further DMA write requests. Workaround the issue by disabling
904 * the de-assertion of the clock request when in 1Gpbs mode.
905 * Also, set appropriate Tx re-transmission timeouts for 10 and 100Half link
906 * speeds in order to avoid Tx hangs.
907 **/
908static s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link)
909{
910 u32 fextnvm6 = er32(FEXTNVM6);
911 u32 status = er32(STATUS);
912 s32 ret_val = 0;
913 u16 reg;
914
915 if (link && (status & E1000_STATUS_SPEED_1000)) {
916 ret_val = hw->phy.ops.acquire(hw);
917 if (ret_val)
918 return ret_val;
919
920 ret_val =
921 e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
922 ®);
923 if (ret_val)
924 goto release;
925
926 ret_val =
927 e1000e_write_kmrn_reg_locked(hw,
928 E1000_KMRNCTRLSTA_K1_CONFIG,
929 reg &
930 ~E1000_KMRNCTRLSTA_K1_ENABLE);
931 if (ret_val)
932 goto release;
933
934 usleep_range(10, 20);
935
936 ew32(FEXTNVM6, fextnvm6 | E1000_FEXTNVM6_REQ_PLL_CLK);
937
938 ret_val =
939 e1000e_write_kmrn_reg_locked(hw,
940 E1000_KMRNCTRLSTA_K1_CONFIG,
941 reg);
942release:
943 hw->phy.ops.release(hw);
944 } else {
945 /* clear FEXTNVM6 bit 8 on link down or 10/100 */
946 fextnvm6 &= ~E1000_FEXTNVM6_REQ_PLL_CLK;
947
948 if ((hw->phy.revision > 5) || !link ||
949 ((status & E1000_STATUS_SPEED_100) &&
950 (status & E1000_STATUS_FD)))
951 goto update_fextnvm6;
952
953 ret_val = e1e_rphy(hw, I217_INBAND_CTRL, ®);
954 if (ret_val)
955 return ret_val;
956
957 /* Clear link status transmit timeout */
958 reg &= ~I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK;
959
960 if (status & E1000_STATUS_SPEED_100) {
961 /* Set inband Tx timeout to 5x10us for 100Half */
962 reg |= 5 << I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
963
964 /* Do not extend the K1 entry latency for 100Half */
965 fextnvm6 &= ~E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
966 } else {
967 /* Set inband Tx timeout to 50x10us for 10Full/Half */
968 reg |= 50 <<
969 I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT;
970
971 /* Extend the K1 entry latency for 10 Mbps */
972 fextnvm6 |= E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION;
973 }
974
975 ret_val = e1e_wphy(hw, I217_INBAND_CTRL, reg);
976 if (ret_val)
977 return ret_val;
978
979update_fextnvm6:
980 ew32(FEXTNVM6, fextnvm6);
981 }
982
983 return ret_val;
984}
985
986/**
987 * e1000_platform_pm_pch_lpt - Set platform power management values
988 * @hw: pointer to the HW structure
989 * @link: bool indicating link status
990 *
991 * Set the Latency Tolerance Reporting (LTR) values for the "PCIe-like"
992 * GbE MAC in the Lynx Point PCH based on Rx buffer size and link speed
993 * when link is up (which must not exceed the maximum latency supported
994 * by the platform), otherwise specify there is no LTR requirement.
995 * Unlike true-PCIe devices which set the LTR maximum snoop/no-snoop
996 * latencies in the LTR Extended Capability Structure in the PCIe Extended
997 * Capability register set, on this device LTR is set by writing the
998 * equivalent snoop/no-snoop latencies in the LTRV register in the MAC and
999 * set the SEND bit to send an Intel On-chip System Fabric sideband (IOSF-SB)
1000 * message to the PMC.
1001 **/
1002static s32 e1000_platform_pm_pch_lpt(struct e1000_hw *hw, bool link)
1003{
1004 u32 reg = link << (E1000_LTRV_REQ_SHIFT + E1000_LTRV_NOSNOOP_SHIFT) |
1005 link << E1000_LTRV_REQ_SHIFT | E1000_LTRV_SEND;
1006 u16 lat_enc = 0; /* latency encoded */
1007
1008 if (link) {
1009 u16 speed, duplex, scale = 0;
1010 u16 max_snoop, max_nosnoop;
1011 u16 max_ltr_enc; /* max LTR latency encoded */
1012 u64 value;
1013 u32 rxa;
1014
1015 if (!hw->adapter->max_frame_size) {
1016 e_dbg("max_frame_size not set.\n");
1017 return -E1000_ERR_CONFIG;
1018 }
1019
1020 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
1021 if (!speed) {
1022 e_dbg("Speed not set.\n");
1023 return -E1000_ERR_CONFIG;
1024 }
1025
1026 /* Rx Packet Buffer Allocation size (KB) */
1027 rxa = er32(PBA) & E1000_PBA_RXA_MASK;
1028
1029 /* Determine the maximum latency tolerated by the device.
1030 *
1031 * Per the PCIe spec, the tolerated latencies are encoded as
1032 * a 3-bit encoded scale (only 0-5 are valid) multiplied by
1033 * a 10-bit value (0-1023) to provide a range from 1 ns to
1034 * 2^25*(2^10-1) ns. The scale is encoded as 0=2^0ns,
1035 * 1=2^5ns, 2=2^10ns,...5=2^25ns.
1036 */
1037 rxa *= 512;
1038 value = (rxa > hw->adapter->max_frame_size) ?
1039 (rxa - hw->adapter->max_frame_size) * (16000 / speed) :
1040 0;
1041
1042 while (value > PCI_LTR_VALUE_MASK) {
1043 scale++;
1044 value = DIV_ROUND_UP(value, BIT(5));
1045 }
1046 if (scale > E1000_LTRV_SCALE_MAX) {
1047 e_dbg("Invalid LTR latency scale %d\n", scale);
1048 return -E1000_ERR_CONFIG;
1049 }
1050 lat_enc = (u16)((scale << PCI_LTR_SCALE_SHIFT) | value);
1051
1052 /* Determine the maximum latency tolerated by the platform */
1053 pci_read_config_word(hw->adapter->pdev, E1000_PCI_LTR_CAP_LPT,
1054 &max_snoop);
1055 pci_read_config_word(hw->adapter->pdev,
1056 E1000_PCI_LTR_CAP_LPT + 2, &max_nosnoop);
1057 max_ltr_enc = max_t(u16, max_snoop, max_nosnoop);
1058
1059 if (lat_enc > max_ltr_enc)
1060 lat_enc = max_ltr_enc;
1061 }
1062
1063 /* Set Snoop and No-Snoop latencies the same */
1064 reg |= lat_enc | (lat_enc << E1000_LTRV_NOSNOOP_SHIFT);
1065 ew32(LTRV, reg);
1066
1067 return 0;
1068}
1069
1070/**
1071 * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP
1072 * @hw: pointer to the HW structure
1073 * @to_sx: boolean indicating a system power state transition to Sx
1074 *
1075 * When link is down, configure ULP mode to significantly reduce the power
1076 * to the PHY. If on a Manageability Engine (ME) enabled system, tell the
1077 * ME firmware to start the ULP configuration. If not on an ME enabled
1078 * system, configure the ULP mode by software.
1079 */
1080s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx)
1081{
1082 u32 mac_reg;
1083 s32 ret_val = 0;
1084 u16 phy_reg;
1085 u16 oem_reg = 0;
1086
1087 if ((hw->mac.type < e1000_pch_lpt) ||
1088 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1089 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1090 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1091 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1092 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_on))
1093 return 0;
1094
1095 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1096 /* Request ME configure ULP mode in the PHY */
1097 mac_reg = er32(H2ME);
1098 mac_reg |= E1000_H2ME_ULP | E1000_H2ME_ENFORCE_SETTINGS;
1099 ew32(H2ME, mac_reg);
1100
1101 goto out;
1102 }
1103
1104 if (!to_sx) {
1105 int i = 0;
1106
1107 /* Poll up to 5 seconds for Cable Disconnected indication */
1108 while (!(er32(FEXT) & E1000_FEXT_PHY_CABLE_DISCONNECTED)) {
1109 /* Bail if link is re-acquired */
1110 if (er32(STATUS) & E1000_STATUS_LU)
1111 return -E1000_ERR_PHY;
1112
1113 if (i++ == 100)
1114 break;
1115
1116 msleep(50);
1117 }
1118 e_dbg("CABLE_DISCONNECTED %s set after %dmsec\n",
1119 (er32(FEXT) &
1120 E1000_FEXT_PHY_CABLE_DISCONNECTED) ? "" : "not", i * 50);
1121 }
1122
1123 ret_val = hw->phy.ops.acquire(hw);
1124 if (ret_val)
1125 goto out;
1126
1127 /* Force SMBus mode in PHY */
1128 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1129 if (ret_val)
1130 goto release;
1131 phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
1132 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1133
1134 /* Force SMBus mode in MAC */
1135 mac_reg = er32(CTRL_EXT);
1136 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1137 ew32(CTRL_EXT, mac_reg);
1138
1139 /* Si workaround for ULP entry flow on i127/rev6 h/w. Enable
1140 * LPLU and disable Gig speed when entering ULP
1141 */
1142 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6)) {
1143 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_OEM_BITS,
1144 &oem_reg);
1145 if (ret_val)
1146 goto release;
1147
1148 phy_reg = oem_reg;
1149 phy_reg |= HV_OEM_BITS_LPLU | HV_OEM_BITS_GBE_DIS;
1150
1151 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1152 phy_reg);
1153
1154 if (ret_val)
1155 goto release;
1156 }
1157
1158 /* Set Inband ULP Exit, Reset to SMBus mode and
1159 * Disable SMBus Release on PERST# in PHY
1160 */
1161 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1162 if (ret_val)
1163 goto release;
1164 phy_reg |= (I218_ULP_CONFIG1_RESET_TO_SMBUS |
1165 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1166 if (to_sx) {
1167 if (er32(WUFC) & E1000_WUFC_LNKC)
1168 phy_reg |= I218_ULP_CONFIG1_WOL_HOST;
1169 else
1170 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1171
1172 phy_reg |= I218_ULP_CONFIG1_STICKY_ULP;
1173 phy_reg &= ~I218_ULP_CONFIG1_INBAND_EXIT;
1174 } else {
1175 phy_reg |= I218_ULP_CONFIG1_INBAND_EXIT;
1176 phy_reg &= ~I218_ULP_CONFIG1_STICKY_ULP;
1177 phy_reg &= ~I218_ULP_CONFIG1_WOL_HOST;
1178 }
1179 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1180
1181 /* Set Disable SMBus Release on PERST# in MAC */
1182 mac_reg = er32(FEXTNVM7);
1183 mac_reg |= E1000_FEXTNVM7_DISABLE_SMB_PERST;
1184 ew32(FEXTNVM7, mac_reg);
1185
1186 /* Commit ULP changes in PHY by starting auto ULP configuration */
1187 phy_reg |= I218_ULP_CONFIG1_START;
1188 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1189
1190 if ((hw->phy.type == e1000_phy_i217) && (hw->phy.revision == 6) &&
1191 to_sx && (er32(STATUS) & E1000_STATUS_LU)) {
1192 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_OEM_BITS,
1193 oem_reg);
1194 if (ret_val)
1195 goto release;
1196 }
1197
1198release:
1199 hw->phy.ops.release(hw);
1200out:
1201 if (ret_val)
1202 e_dbg("Error in ULP enable flow: %d\n", ret_val);
1203 else
1204 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_on;
1205
1206 return ret_val;
1207}
1208
1209/**
1210 * e1000_disable_ulp_lpt_lp - unconfigure Ultra Low Power mode for LynxPoint-LP
1211 * @hw: pointer to the HW structure
1212 * @force: boolean indicating whether or not to force disabling ULP
1213 *
1214 * Un-configure ULP mode when link is up, the system is transitioned from
1215 * Sx or the driver is unloaded. If on a Manageability Engine (ME) enabled
1216 * system, poll for an indication from ME that ULP has been un-configured.
1217 * If not on an ME enabled system, un-configure the ULP mode by software.
1218 *
1219 * During nominal operation, this function is called when link is acquired
1220 * to disable ULP mode (force=false); otherwise, for example when unloading
1221 * the driver or during Sx->S0 transitions, this is called with force=true
1222 * to forcibly disable ULP.
1223 */
1224static s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force)
1225{
1226 s32 ret_val = 0;
1227 u32 mac_reg;
1228 u16 phy_reg;
1229 int i = 0;
1230
1231 if ((hw->mac.type < e1000_pch_lpt) ||
1232 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_LM) ||
1233 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPT_I217_V) ||
1234 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM2) ||
1235 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V2) ||
1236 (hw->dev_spec.ich8lan.ulp_state == e1000_ulp_state_off))
1237 return 0;
1238
1239 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
1240 if (force) {
1241 /* Request ME un-configure ULP mode in the PHY */
1242 mac_reg = er32(H2ME);
1243 mac_reg &= ~E1000_H2ME_ULP;
1244 mac_reg |= E1000_H2ME_ENFORCE_SETTINGS;
1245 ew32(H2ME, mac_reg);
1246 }
1247
1248 /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */
1249 while (er32(FWSM) & E1000_FWSM_ULP_CFG_DONE) {
1250 if (i++ == 30) {
1251 ret_val = -E1000_ERR_PHY;
1252 goto out;
1253 }
1254
1255 usleep_range(10000, 11000);
1256 }
1257 e_dbg("ULP_CONFIG_DONE cleared after %dmsec\n", i * 10);
1258
1259 if (force) {
1260 mac_reg = er32(H2ME);
1261 mac_reg &= ~E1000_H2ME_ENFORCE_SETTINGS;
1262 ew32(H2ME, mac_reg);
1263 } else {
1264 /* Clear H2ME.ULP after ME ULP configuration */
1265 mac_reg = er32(H2ME);
1266 mac_reg &= ~E1000_H2ME_ULP;
1267 ew32(H2ME, mac_reg);
1268 }
1269
1270 goto out;
1271 }
1272
1273 ret_val = hw->phy.ops.acquire(hw);
1274 if (ret_val)
1275 goto out;
1276
1277 if (force)
1278 /* Toggle LANPHYPC Value bit */
1279 e1000_toggle_lanphypc_pch_lpt(hw);
1280
1281 /* Unforce SMBus mode in PHY */
1282 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
1283 if (ret_val) {
1284 /* The MAC might be in PCIe mode, so temporarily force to
1285 * SMBus mode in order to access the PHY.
1286 */
1287 mac_reg = er32(CTRL_EXT);
1288 mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
1289 ew32(CTRL_EXT, mac_reg);
1290
1291 msleep(50);
1292
1293 ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
1294 &phy_reg);
1295 if (ret_val)
1296 goto release;
1297 }
1298 phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS;
1299 e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
1300
1301 /* Unforce SMBus mode in MAC */
1302 mac_reg = er32(CTRL_EXT);
1303 mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS;
1304 ew32(CTRL_EXT, mac_reg);
1305
1306 /* When ULP mode was previously entered, K1 was disabled by the
1307 * hardware. Re-Enable K1 in the PHY when exiting ULP.
1308 */
1309 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_PM_CTRL, &phy_reg);
1310 if (ret_val)
1311 goto release;
1312 phy_reg |= HV_PM_CTRL_K1_ENABLE;
1313 e1000_write_phy_reg_hv_locked(hw, HV_PM_CTRL, phy_reg);
1314
1315 /* Clear ULP enabled configuration */
1316 ret_val = e1000_read_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, &phy_reg);
1317 if (ret_val)
1318 goto release;
1319 phy_reg &= ~(I218_ULP_CONFIG1_IND |
1320 I218_ULP_CONFIG1_STICKY_ULP |
1321 I218_ULP_CONFIG1_RESET_TO_SMBUS |
1322 I218_ULP_CONFIG1_WOL_HOST |
1323 I218_ULP_CONFIG1_INBAND_EXIT |
1324 I218_ULP_CONFIG1_EN_ULP_LANPHYPC |
1325 I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST |
1326 I218_ULP_CONFIG1_DISABLE_SMB_PERST);
1327 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1328
1329 /* Commit ULP changes by starting auto ULP configuration */
1330 phy_reg |= I218_ULP_CONFIG1_START;
1331 e1000_write_phy_reg_hv_locked(hw, I218_ULP_CONFIG1, phy_reg);
1332
1333 /* Clear Disable SMBus Release on PERST# in MAC */
1334 mac_reg = er32(FEXTNVM7);
1335 mac_reg &= ~E1000_FEXTNVM7_DISABLE_SMB_PERST;
1336 ew32(FEXTNVM7, mac_reg);
1337
1338release:
1339 hw->phy.ops.release(hw);
1340 if (force) {
1341 e1000_phy_hw_reset(hw);
1342 msleep(50);
1343 }
1344out:
1345 if (ret_val)
1346 e_dbg("Error in ULP disable flow: %d\n", ret_val);
1347 else
1348 hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_off;
1349
1350 return ret_val;
1351}
1352
1353/**
1354 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
1355 * @hw: pointer to the HW structure
1356 *
1357 * Checks to see of the link status of the hardware has changed. If a
1358 * change in link status has been detected, then we read the PHY registers
1359 * to get the current speed/duplex if link exists.
1360 **/
1361static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
1362{
1363 struct e1000_mac_info *mac = &hw->mac;
1364 s32 ret_val, tipg_reg = 0;
1365 u16 emi_addr, emi_val = 0;
1366 bool link;
1367 u16 phy_reg;
1368
1369 /* We only want to go out to the PHY registers to see if Auto-Neg
1370 * has completed and/or if our link status has changed. The
1371 * get_link_status flag is set upon receiving a Link Status
1372 * Change or Rx Sequence Error interrupt.
1373 */
1374 if (!mac->get_link_status)
1375 return 0;
1376 mac->get_link_status = false;
1377
1378 /* First we want to see if the MII Status Register reports
1379 * link. If so, then we want to get the current speed/duplex
1380 * of the PHY.
1381 */
1382 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1383 if (ret_val)
1384 goto out;
1385
1386 if (hw->mac.type == e1000_pchlan) {
1387 ret_val = e1000_k1_gig_workaround_hv(hw, link);
1388 if (ret_val)
1389 goto out;
1390 }
1391
1392 /* When connected at 10Mbps half-duplex, some parts are excessively
1393 * aggressive resulting in many collisions. To avoid this, increase
1394 * the IPG and reduce Rx latency in the PHY.
1395 */
1396 if ((hw->mac.type >= e1000_pch2lan) && link) {
1397 u16 speed, duplex;
1398
1399 e1000e_get_speed_and_duplex_copper(hw, &speed, &duplex);
1400 tipg_reg = er32(TIPG);
1401 tipg_reg &= ~E1000_TIPG_IPGT_MASK;
1402
1403 if (duplex == HALF_DUPLEX && speed == SPEED_10) {
1404 tipg_reg |= 0xFF;
1405 /* Reduce Rx latency in analog PHY */
1406 emi_val = 0;
1407 } else if (hw->mac.type >= e1000_pch_spt &&
1408 duplex == FULL_DUPLEX && speed != SPEED_1000) {
1409 tipg_reg |= 0xC;
1410 emi_val = 1;
1411 } else {
1412
1413 /* Roll back the default values */
1414 tipg_reg |= 0x08;
1415 emi_val = 1;
1416 }
1417
1418 ew32(TIPG, tipg_reg);
1419
1420 ret_val = hw->phy.ops.acquire(hw);
1421 if (ret_val)
1422 goto out;
1423
1424 if (hw->mac.type == e1000_pch2lan)
1425 emi_addr = I82579_RX_CONFIG;
1426 else
1427 emi_addr = I217_RX_CONFIG;
1428 ret_val = e1000_write_emi_reg_locked(hw, emi_addr, emi_val);
1429
1430 if (hw->mac.type >= e1000_pch_lpt) {
1431 u16 phy_reg;
1432
1433 e1e_rphy_locked(hw, I217_PLL_CLOCK_GATE_REG, &phy_reg);
1434 phy_reg &= ~I217_PLL_CLOCK_GATE_MASK;
1435 if (speed == SPEED_100 || speed == SPEED_10)
1436 phy_reg |= 0x3E8;
1437 else
1438 phy_reg |= 0xFA;
1439 e1e_wphy_locked(hw, I217_PLL_CLOCK_GATE_REG, phy_reg);
1440
1441 if (speed == SPEED_1000) {
1442 hw->phy.ops.read_reg_locked(hw, HV_PM_CTRL,
1443 &phy_reg);
1444
1445 phy_reg |= HV_PM_CTRL_K1_CLK_REQ;
1446
1447 hw->phy.ops.write_reg_locked(hw, HV_PM_CTRL,
1448 phy_reg);
1449 }
1450 }
1451 hw->phy.ops.release(hw);
1452
1453 if (ret_val)
1454 goto out;
1455
1456 if (hw->mac.type >= e1000_pch_spt) {
1457 u16 data;
1458 u16 ptr_gap;
1459
1460 if (speed == SPEED_1000) {
1461 ret_val = hw->phy.ops.acquire(hw);
1462 if (ret_val)
1463 goto out;
1464
1465 ret_val = e1e_rphy_locked(hw,
1466 PHY_REG(776, 20),
1467 &data);
1468 if (ret_val) {
1469 hw->phy.ops.release(hw);
1470 goto out;
1471 }
1472
1473 ptr_gap = (data & (0x3FF << 2)) >> 2;
1474 if (ptr_gap < 0x18) {
1475 data &= ~(0x3FF << 2);
1476 data |= (0x18 << 2);
1477 ret_val =
1478 e1e_wphy_locked(hw,
1479 PHY_REG(776, 20),
1480 data);
1481 }
1482 hw->phy.ops.release(hw);
1483 if (ret_val)
1484 goto out;
1485 } else {
1486 ret_val = hw->phy.ops.acquire(hw);
1487 if (ret_val)
1488 goto out;
1489
1490 ret_val = e1e_wphy_locked(hw,
1491 PHY_REG(776, 20),
1492 0xC023);
1493 hw->phy.ops.release(hw);
1494 if (ret_val)
1495 goto out;
1496
1497 }
1498 }
1499 }
1500
1501 /* I217 Packet Loss issue:
1502 * ensure that FEXTNVM4 Beacon Duration is set correctly
1503 * on power up.
1504 * Set the Beacon Duration for I217 to 8 usec
1505 */
1506 if (hw->mac.type >= e1000_pch_lpt) {
1507 u32 mac_reg;
1508
1509 mac_reg = er32(FEXTNVM4);
1510 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1511 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1512 ew32(FEXTNVM4, mac_reg);
1513 }
1514
1515 /* Work-around I218 hang issue */
1516 if ((hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
1517 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
1518 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_LM3) ||
1519 (hw->adapter->pdev->device == E1000_DEV_ID_PCH_I218_V3)) {
1520 ret_val = e1000_k1_workaround_lpt_lp(hw, link);
1521 if (ret_val)
1522 goto out;
1523 }
1524 if (hw->mac.type >= e1000_pch_lpt) {
1525 /* Set platform power management values for
1526 * Latency Tolerance Reporting (LTR)
1527 */
1528 ret_val = e1000_platform_pm_pch_lpt(hw, link);
1529 if (ret_val)
1530 goto out;
1531 }
1532
1533 /* Clear link partner's EEE ability */
1534 hw->dev_spec.ich8lan.eee_lp_ability = 0;
1535
1536 if (hw->mac.type >= e1000_pch_lpt) {
1537 u32 fextnvm6 = er32(FEXTNVM6);
1538
1539 if (hw->mac.type == e1000_pch_spt) {
1540 /* FEXTNVM6 K1-off workaround - for SPT only */
1541 u32 pcieanacfg = er32(PCIEANACFG);
1542
1543 if (pcieanacfg & E1000_FEXTNVM6_K1_OFF_ENABLE)
1544 fextnvm6 |= E1000_FEXTNVM6_K1_OFF_ENABLE;
1545 else
1546 fextnvm6 &= ~E1000_FEXTNVM6_K1_OFF_ENABLE;
1547 }
1548
1549 ew32(FEXTNVM6, fextnvm6);
1550 }
1551
1552 if (!link)
1553 goto out;
1554
1555 switch (hw->mac.type) {
1556 case e1000_pch2lan:
1557 ret_val = e1000_k1_workaround_lv(hw);
1558 if (ret_val)
1559 return ret_val;
1560 fallthrough;
1561 case e1000_pchlan:
1562 if (hw->phy.type == e1000_phy_82578) {
1563 ret_val = e1000_link_stall_workaround_hv(hw);
1564 if (ret_val)
1565 return ret_val;
1566 }
1567
1568 /* Workaround for PCHx parts in half-duplex:
1569 * Set the number of preambles removed from the packet
1570 * when it is passed from the PHY to the MAC to prevent
1571 * the MAC from misinterpreting the packet type.
1572 */
1573 e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg);
1574 phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK;
1575
1576 if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD)
1577 phy_reg |= BIT(HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT);
1578
1579 e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg);
1580 break;
1581 default:
1582 break;
1583 }
1584
1585 /* Check if there was DownShift, must be checked
1586 * immediately after link-up
1587 */
1588 e1000e_check_downshift(hw);
1589
1590 /* Enable/Disable EEE after link up */
1591 if (hw->phy.type > e1000_phy_82579) {
1592 ret_val = e1000_set_eee_pchlan(hw);
1593 if (ret_val)
1594 return ret_val;
1595 }
1596
1597 /* If we are forcing speed/duplex, then we simply return since
1598 * we have already determined whether we have link or not.
1599 */
1600 if (!mac->autoneg)
1601 return -E1000_ERR_CONFIG;
1602
1603 /* Auto-Neg is enabled. Auto Speed Detection takes care
1604 * of MAC speed/duplex configuration. So we only need to
1605 * configure Collision Distance in the MAC.
1606 */
1607 mac->ops.config_collision_dist(hw);
1608
1609 /* Configure Flow Control now that Auto-Neg has completed.
1610 * First, we need to restore the desired flow control
1611 * settings because we may have had to re-autoneg with a
1612 * different link partner.
1613 */
1614 ret_val = e1000e_config_fc_after_link_up(hw);
1615 if (ret_val)
1616 e_dbg("Error configuring flow control\n");
1617
1618 return ret_val;
1619
1620out:
1621 mac->get_link_status = true;
1622 return ret_val;
1623}
1624
1625static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
1626{
1627 struct e1000_hw *hw = &adapter->hw;
1628 s32 rc;
1629
1630 rc = e1000_init_mac_params_ich8lan(hw);
1631 if (rc)
1632 return rc;
1633
1634 rc = e1000_init_nvm_params_ich8lan(hw);
1635 if (rc)
1636 return rc;
1637
1638 switch (hw->mac.type) {
1639 case e1000_ich8lan:
1640 case e1000_ich9lan:
1641 case e1000_ich10lan:
1642 rc = e1000_init_phy_params_ich8lan(hw);
1643 break;
1644 case e1000_pchlan:
1645 case e1000_pch2lan:
1646 case e1000_pch_lpt:
1647 case e1000_pch_spt:
1648 case e1000_pch_cnp:
1649 case e1000_pch_tgp:
1650 case e1000_pch_adp:
1651 rc = e1000_init_phy_params_pchlan(hw);
1652 break;
1653 default:
1654 break;
1655 }
1656 if (rc)
1657 return rc;
1658
1659 /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or
1660 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
1661 */
1662 if ((adapter->hw.phy.type == e1000_phy_ife) ||
1663 ((adapter->hw.mac.type >= e1000_pch2lan) &&
1664 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
1665 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
1666 adapter->max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
1667
1668 hw->mac.ops.blink_led = NULL;
1669 }
1670
1671 if ((adapter->hw.mac.type == e1000_ich8lan) &&
1672 (adapter->hw.phy.type != e1000_phy_ife))
1673 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
1674
1675 /* Enable workaround for 82579 w/ ME enabled */
1676 if ((adapter->hw.mac.type == e1000_pch2lan) &&
1677 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1678 adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA;
1679
1680 return 0;
1681}
1682
1683static DEFINE_MUTEX(nvm_mutex);
1684
1685/**
1686 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
1687 * @hw: pointer to the HW structure
1688 *
1689 * Acquires the mutex for performing NVM operations.
1690 **/
1691static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1692{
1693 mutex_lock(&nvm_mutex);
1694
1695 return 0;
1696}
1697
1698/**
1699 * e1000_release_nvm_ich8lan - Release NVM mutex
1700 * @hw: pointer to the HW structure
1701 *
1702 * Releases the mutex used while performing NVM operations.
1703 **/
1704static void e1000_release_nvm_ich8lan(struct e1000_hw __always_unused *hw)
1705{
1706 mutex_unlock(&nvm_mutex);
1707}
1708
1709/**
1710 * e1000_acquire_swflag_ich8lan - Acquire software control flag
1711 * @hw: pointer to the HW structure
1712 *
1713 * Acquires the software control flag for performing PHY and select
1714 * MAC CSR accesses.
1715 **/
1716static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
1717{
1718 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
1719 s32 ret_val = 0;
1720
1721 if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE,
1722 &hw->adapter->state)) {
1723 e_dbg("contention for Phy access\n");
1724 return -E1000_ERR_PHY;
1725 }
1726
1727 while (timeout) {
1728 extcnf_ctrl = er32(EXTCNF_CTRL);
1729 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
1730 break;
1731
1732 mdelay(1);
1733 timeout--;
1734 }
1735
1736 if (!timeout) {
1737 e_dbg("SW has already locked the resource.\n");
1738 ret_val = -E1000_ERR_CONFIG;
1739 goto out;
1740 }
1741
1742 timeout = SW_FLAG_TIMEOUT;
1743
1744 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
1745 ew32(EXTCNF_CTRL, extcnf_ctrl);
1746
1747 while (timeout) {
1748 extcnf_ctrl = er32(EXTCNF_CTRL);
1749 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
1750 break;
1751
1752 mdelay(1);
1753 timeout--;
1754 }
1755
1756 if (!timeout) {
1757 e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n",
1758 er32(FWSM), extcnf_ctrl);
1759 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1760 ew32(EXTCNF_CTRL, extcnf_ctrl);
1761 ret_val = -E1000_ERR_CONFIG;
1762 goto out;
1763 }
1764
1765out:
1766 if (ret_val)
1767 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1768
1769 return ret_val;
1770}
1771
1772/**
1773 * e1000_release_swflag_ich8lan - Release software control flag
1774 * @hw: pointer to the HW structure
1775 *
1776 * Releases the software control flag for performing PHY and select
1777 * MAC CSR accesses.
1778 **/
1779static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
1780{
1781 u32 extcnf_ctrl;
1782
1783 extcnf_ctrl = er32(EXTCNF_CTRL);
1784
1785 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
1786 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
1787 ew32(EXTCNF_CTRL, extcnf_ctrl);
1788 } else {
1789 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
1790 }
1791
1792 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
1793}
1794
1795/**
1796 * e1000_check_mng_mode_ich8lan - Checks management mode
1797 * @hw: pointer to the HW structure
1798 *
1799 * This checks if the adapter has any manageability enabled.
1800 * This is a function pointer entry point only called by read/write
1801 * routines for the PHY and NVM parts.
1802 **/
1803static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
1804{
1805 u32 fwsm;
1806
1807 fwsm = er32(FWSM);
1808 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1809 ((fwsm & E1000_FWSM_MODE_MASK) ==
1810 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1811}
1812
1813/**
1814 * e1000_check_mng_mode_pchlan - Checks management mode
1815 * @hw: pointer to the HW structure
1816 *
1817 * This checks if the adapter has iAMT enabled.
1818 * This is a function pointer entry point only called by read/write
1819 * routines for the PHY and NVM parts.
1820 **/
1821static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
1822{
1823 u32 fwsm;
1824
1825 fwsm = er32(FWSM);
1826 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
1827 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
1828}
1829
1830/**
1831 * e1000_rar_set_pch2lan - Set receive address register
1832 * @hw: pointer to the HW structure
1833 * @addr: pointer to the receive address
1834 * @index: receive address array register
1835 *
1836 * Sets the receive address array register at index to the address passed
1837 * in by addr. For 82579, RAR[0] is the base address register that is to
1838 * contain the MAC address but RAR[1-6] are reserved for manageability (ME).
1839 * Use SHRA[0-3] in place of those reserved for ME.
1840 **/
1841static int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index)
1842{
1843 u32 rar_low, rar_high;
1844
1845 /* HW expects these in little endian so we reverse the byte order
1846 * from network order (big endian) to little endian
1847 */
1848 rar_low = ((u32)addr[0] |
1849 ((u32)addr[1] << 8) |
1850 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1851
1852 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1853
1854 /* If MAC address zero, no need to set the AV bit */
1855 if (rar_low || rar_high)
1856 rar_high |= E1000_RAH_AV;
1857
1858 if (index == 0) {
1859 ew32(RAL(index), rar_low);
1860 e1e_flush();
1861 ew32(RAH(index), rar_high);
1862 e1e_flush();
1863 return 0;
1864 }
1865
1866 /* RAR[1-6] are owned by manageability. Skip those and program the
1867 * next address into the SHRA register array.
1868 */
1869 if (index < (u32)(hw->mac.rar_entry_count)) {
1870 s32 ret_val;
1871
1872 ret_val = e1000_acquire_swflag_ich8lan(hw);
1873 if (ret_val)
1874 goto out;
1875
1876 ew32(SHRAL(index - 1), rar_low);
1877 e1e_flush();
1878 ew32(SHRAH(index - 1), rar_high);
1879 e1e_flush();
1880
1881 e1000_release_swflag_ich8lan(hw);
1882
1883 /* verify the register updates */
1884 if ((er32(SHRAL(index - 1)) == rar_low) &&
1885 (er32(SHRAH(index - 1)) == rar_high))
1886 return 0;
1887
1888 e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n",
1889 (index - 1), er32(FWSM));
1890 }
1891
1892out:
1893 e_dbg("Failed to write receive address at index %d\n", index);
1894 return -E1000_ERR_CONFIG;
1895}
1896
1897/**
1898 * e1000_rar_get_count_pch_lpt - Get the number of available SHRA
1899 * @hw: pointer to the HW structure
1900 *
1901 * Get the number of available receive registers that the Host can
1902 * program. SHRA[0-10] are the shared receive address registers
1903 * that are shared between the Host and manageability engine (ME).
1904 * ME can reserve any number of addresses and the host needs to be
1905 * able to tell how many available registers it has access to.
1906 **/
1907static u32 e1000_rar_get_count_pch_lpt(struct e1000_hw *hw)
1908{
1909 u32 wlock_mac;
1910 u32 num_entries;
1911
1912 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1913 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1914
1915 switch (wlock_mac) {
1916 case 0:
1917 /* All SHRA[0..10] and RAR[0] available */
1918 num_entries = hw->mac.rar_entry_count;
1919 break;
1920 case 1:
1921 /* Only RAR[0] available */
1922 num_entries = 1;
1923 break;
1924 default:
1925 /* SHRA[0..(wlock_mac - 1)] available + RAR[0] */
1926 num_entries = wlock_mac + 1;
1927 break;
1928 }
1929
1930 return num_entries;
1931}
1932
1933/**
1934 * e1000_rar_set_pch_lpt - Set receive address registers
1935 * @hw: pointer to the HW structure
1936 * @addr: pointer to the receive address
1937 * @index: receive address array register
1938 *
1939 * Sets the receive address register array at index to the address passed
1940 * in by addr. For LPT, RAR[0] is the base address register that is to
1941 * contain the MAC address. SHRA[0-10] are the shared receive address
1942 * registers that are shared between the Host and manageability engine (ME).
1943 **/
1944static int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index)
1945{
1946 u32 rar_low, rar_high;
1947 u32 wlock_mac;
1948
1949 /* HW expects these in little endian so we reverse the byte order
1950 * from network order (big endian) to little endian
1951 */
1952 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
1953 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
1954
1955 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
1956
1957 /* If MAC address zero, no need to set the AV bit */
1958 if (rar_low || rar_high)
1959 rar_high |= E1000_RAH_AV;
1960
1961 if (index == 0) {
1962 ew32(RAL(index), rar_low);
1963 e1e_flush();
1964 ew32(RAH(index), rar_high);
1965 e1e_flush();
1966 return 0;
1967 }
1968
1969 /* The manageability engine (ME) can lock certain SHRAR registers that
1970 * it is using - those registers are unavailable for use.
1971 */
1972 if (index < hw->mac.rar_entry_count) {
1973 wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK;
1974 wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT;
1975
1976 /* Check if all SHRAR registers are locked */
1977 if (wlock_mac == 1)
1978 goto out;
1979
1980 if ((wlock_mac == 0) || (index <= wlock_mac)) {
1981 s32 ret_val;
1982
1983 ret_val = e1000_acquire_swflag_ich8lan(hw);
1984
1985 if (ret_val)
1986 goto out;
1987
1988 ew32(SHRAL_PCH_LPT(index - 1), rar_low);
1989 e1e_flush();
1990 ew32(SHRAH_PCH_LPT(index - 1), rar_high);
1991 e1e_flush();
1992
1993 e1000_release_swflag_ich8lan(hw);
1994
1995 /* verify the register updates */
1996 if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) &&
1997 (er32(SHRAH_PCH_LPT(index - 1)) == rar_high))
1998 return 0;
1999 }
2000 }
2001
2002out:
2003 e_dbg("Failed to write receive address at index %d\n", index);
2004 return -E1000_ERR_CONFIG;
2005}
2006
2007/**
2008 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
2009 * @hw: pointer to the HW structure
2010 *
2011 * Checks if firmware is blocking the reset of the PHY.
2012 * This is a function pointer entry point only called by
2013 * reset routines.
2014 **/
2015static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
2016{
2017 bool blocked = false;
2018 int i = 0;
2019
2020 while ((blocked = !(er32(FWSM) & E1000_ICH_FWSM_RSPCIPHY)) &&
2021 (i++ < 30))
2022 usleep_range(10000, 11000);
2023 return blocked ? E1000_BLK_PHY_RESET : 0;
2024}
2025
2026/**
2027 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
2028 * @hw: pointer to the HW structure
2029 *
2030 * Assumes semaphore already acquired.
2031 *
2032 **/
2033static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
2034{
2035 u16 phy_data;
2036 u32 strap = er32(STRAP);
2037 u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >>
2038 E1000_STRAP_SMT_FREQ_SHIFT;
2039 s32 ret_val;
2040
2041 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
2042
2043 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
2044 if (ret_val)
2045 return ret_val;
2046
2047 phy_data &= ~HV_SMB_ADDR_MASK;
2048 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
2049 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
2050
2051 if (hw->phy.type == e1000_phy_i217) {
2052 /* Restore SMBus frequency */
2053 if (freq--) {
2054 phy_data &= ~HV_SMB_ADDR_FREQ_MASK;
2055 phy_data |= (freq & BIT(0)) <<
2056 HV_SMB_ADDR_FREQ_LOW_SHIFT;
2057 phy_data |= (freq & BIT(1)) <<
2058 (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1);
2059 } else {
2060 e_dbg("Unsupported SMB frequency in PHY\n");
2061 }
2062 }
2063
2064 return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
2065}
2066
2067/**
2068 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
2069 * @hw: pointer to the HW structure
2070 *
2071 * SW should configure the LCD from the NVM extended configuration region
2072 * as a workaround for certain parts.
2073 **/
2074static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
2075{
2076 struct e1000_phy_info *phy = &hw->phy;
2077 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
2078 s32 ret_val = 0;
2079 u16 word_addr, reg_data, reg_addr, phy_page = 0;
2080
2081 /* Initialize the PHY from the NVM on ICH platforms. This
2082 * is needed due to an issue where the NVM configuration is
2083 * not properly autoloaded after power transitions.
2084 * Therefore, after each PHY reset, we will load the
2085 * configuration data out of the NVM manually.
2086 */
2087 switch (hw->mac.type) {
2088 case e1000_ich8lan:
2089 if (phy->type != e1000_phy_igp_3)
2090 return ret_val;
2091
2092 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
2093 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
2094 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
2095 break;
2096 }
2097 fallthrough;
2098 case e1000_pchlan:
2099 case e1000_pch2lan:
2100 case e1000_pch_lpt:
2101 case e1000_pch_spt:
2102 case e1000_pch_cnp:
2103 case e1000_pch_tgp:
2104 case e1000_pch_adp:
2105 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
2106 break;
2107 default:
2108 return ret_val;
2109 }
2110
2111 ret_val = hw->phy.ops.acquire(hw);
2112 if (ret_val)
2113 return ret_val;
2114
2115 data = er32(FEXTNVM);
2116 if (!(data & sw_cfg_mask))
2117 goto release;
2118
2119 /* Make sure HW does not configure LCD from PHY
2120 * extended configuration before SW configuration
2121 */
2122 data = er32(EXTCNF_CTRL);
2123 if ((hw->mac.type < e1000_pch2lan) &&
2124 (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE))
2125 goto release;
2126
2127 cnf_size = er32(EXTCNF_SIZE);
2128 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
2129 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
2130 if (!cnf_size)
2131 goto release;
2132
2133 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
2134 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
2135
2136 if (((hw->mac.type == e1000_pchlan) &&
2137 !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) ||
2138 (hw->mac.type > e1000_pchlan)) {
2139 /* HW configures the SMBus address and LEDs when the
2140 * OEM and LCD Write Enable bits are set in the NVM.
2141 * When both NVM bits are cleared, SW will configure
2142 * them instead.
2143 */
2144 ret_val = e1000_write_smbus_addr(hw);
2145 if (ret_val)
2146 goto release;
2147
2148 data = er32(LEDCTL);
2149 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
2150 (u16)data);
2151 if (ret_val)
2152 goto release;
2153 }
2154
2155 /* Configure LCD from extended configuration region. */
2156
2157 /* cnf_base_addr is in DWORD */
2158 word_addr = (u16)(cnf_base_addr << 1);
2159
2160 for (i = 0; i < cnf_size; i++) {
2161 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, ®_data);
2162 if (ret_val)
2163 goto release;
2164
2165 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
2166 1, ®_addr);
2167 if (ret_val)
2168 goto release;
2169
2170 /* Save off the PHY page for future writes. */
2171 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
2172 phy_page = reg_data;
2173 continue;
2174 }
2175
2176 reg_addr &= PHY_REG_MASK;
2177 reg_addr |= phy_page;
2178
2179 ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data);
2180 if (ret_val)
2181 goto release;
2182 }
2183
2184release:
2185 hw->phy.ops.release(hw);
2186 return ret_val;
2187}
2188
2189/**
2190 * e1000_k1_gig_workaround_hv - K1 Si workaround
2191 * @hw: pointer to the HW structure
2192 * @link: link up bool flag
2193 *
2194 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
2195 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
2196 * If link is down, the function will restore the default K1 setting located
2197 * in the NVM.
2198 **/
2199static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
2200{
2201 s32 ret_val = 0;
2202 u16 status_reg = 0;
2203 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
2204
2205 if (hw->mac.type != e1000_pchlan)
2206 return 0;
2207
2208 /* Wrap the whole flow with the sw flag */
2209 ret_val = hw->phy.ops.acquire(hw);
2210 if (ret_val)
2211 return ret_val;
2212
2213 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
2214 if (link) {
2215 if (hw->phy.type == e1000_phy_82578) {
2216 ret_val = e1e_rphy_locked(hw, BM_CS_STATUS,
2217 &status_reg);
2218 if (ret_val)
2219 goto release;
2220
2221 status_reg &= (BM_CS_STATUS_LINK_UP |
2222 BM_CS_STATUS_RESOLVED |
2223 BM_CS_STATUS_SPEED_MASK);
2224
2225 if (status_reg == (BM_CS_STATUS_LINK_UP |
2226 BM_CS_STATUS_RESOLVED |
2227 BM_CS_STATUS_SPEED_1000))
2228 k1_enable = false;
2229 }
2230
2231 if (hw->phy.type == e1000_phy_82577) {
2232 ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg);
2233 if (ret_val)
2234 goto release;
2235
2236 status_reg &= (HV_M_STATUS_LINK_UP |
2237 HV_M_STATUS_AUTONEG_COMPLETE |
2238 HV_M_STATUS_SPEED_MASK);
2239
2240 if (status_reg == (HV_M_STATUS_LINK_UP |
2241 HV_M_STATUS_AUTONEG_COMPLETE |
2242 HV_M_STATUS_SPEED_1000))
2243 k1_enable = false;
2244 }
2245
2246 /* Link stall fix for link up */
2247 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100);
2248 if (ret_val)
2249 goto release;
2250
2251 } else {
2252 /* Link stall fix for link down */
2253 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100);
2254 if (ret_val)
2255 goto release;
2256 }
2257
2258 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
2259
2260release:
2261 hw->phy.ops.release(hw);
2262
2263 return ret_val;
2264}
2265
2266/**
2267 * e1000_configure_k1_ich8lan - Configure K1 power state
2268 * @hw: pointer to the HW structure
2269 * @enable: K1 state to configure
2270 *
2271 * Configure the K1 power state based on the provided parameter.
2272 * Assumes semaphore already acquired.
2273 *
2274 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2275 **/
2276s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
2277{
2278 s32 ret_val;
2279 u32 ctrl_reg = 0;
2280 u32 ctrl_ext = 0;
2281 u32 reg = 0;
2282 u16 kmrn_reg = 0;
2283
2284 ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2285 &kmrn_reg);
2286 if (ret_val)
2287 return ret_val;
2288
2289 if (k1_enable)
2290 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
2291 else
2292 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
2293
2294 ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG,
2295 kmrn_reg);
2296 if (ret_val)
2297 return ret_val;
2298
2299 usleep_range(20, 40);
2300 ctrl_ext = er32(CTRL_EXT);
2301 ctrl_reg = er32(CTRL);
2302
2303 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
2304 reg |= E1000_CTRL_FRCSPD;
2305 ew32(CTRL, reg);
2306
2307 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
2308 e1e_flush();
2309 usleep_range(20, 40);
2310 ew32(CTRL, ctrl_reg);
2311 ew32(CTRL_EXT, ctrl_ext);
2312 e1e_flush();
2313 usleep_range(20, 40);
2314
2315 return 0;
2316}
2317
2318/**
2319 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
2320 * @hw: pointer to the HW structure
2321 * @d0_state: boolean if entering d0 or d3 device state
2322 *
2323 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
2324 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
2325 * in NVM determines whether HW should configure LPLU and Gbe Disable.
2326 **/
2327static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
2328{
2329 s32 ret_val = 0;
2330 u32 mac_reg;
2331 u16 oem_reg;
2332
2333 if (hw->mac.type < e1000_pchlan)
2334 return ret_val;
2335
2336 ret_val = hw->phy.ops.acquire(hw);
2337 if (ret_val)
2338 return ret_val;
2339
2340 if (hw->mac.type == e1000_pchlan) {
2341 mac_reg = er32(EXTCNF_CTRL);
2342 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
2343 goto release;
2344 }
2345
2346 mac_reg = er32(FEXTNVM);
2347 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
2348 goto release;
2349
2350 mac_reg = er32(PHY_CTRL);
2351
2352 ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg);
2353 if (ret_val)
2354 goto release;
2355
2356 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
2357
2358 if (d0_state) {
2359 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
2360 oem_reg |= HV_OEM_BITS_GBE_DIS;
2361
2362 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
2363 oem_reg |= HV_OEM_BITS_LPLU;
2364 } else {
2365 if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE |
2366 E1000_PHY_CTRL_NOND0A_GBE_DISABLE))
2367 oem_reg |= HV_OEM_BITS_GBE_DIS;
2368
2369 if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU |
2370 E1000_PHY_CTRL_NOND0A_LPLU))
2371 oem_reg |= HV_OEM_BITS_LPLU;
2372 }
2373
2374 /* Set Restart auto-neg to activate the bits */
2375 if ((d0_state || (hw->mac.type != e1000_pchlan)) &&
2376 !hw->phy.ops.check_reset_block(hw))
2377 oem_reg |= HV_OEM_BITS_RESTART_AN;
2378
2379 ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg);
2380
2381release:
2382 hw->phy.ops.release(hw);
2383
2384 return ret_val;
2385}
2386
2387/**
2388 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
2389 * @hw: pointer to the HW structure
2390 **/
2391static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
2392{
2393 s32 ret_val;
2394 u16 data;
2395
2396 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
2397 if (ret_val)
2398 return ret_val;
2399
2400 data |= HV_KMRN_MDIO_SLOW;
2401
2402 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
2403
2404 return ret_val;
2405}
2406
2407/**
2408 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2409 * done after every PHY reset.
2410 **/
2411static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2412{
2413 s32 ret_val = 0;
2414 u16 phy_data;
2415
2416 if (hw->mac.type != e1000_pchlan)
2417 return 0;
2418
2419 /* Set MDIO slow mode before any other MDIO access */
2420 if (hw->phy.type == e1000_phy_82577) {
2421 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2422 if (ret_val)
2423 return ret_val;
2424 }
2425
2426 if (((hw->phy.type == e1000_phy_82577) &&
2427 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
2428 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
2429 /* Disable generation of early preamble */
2430 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
2431 if (ret_val)
2432 return ret_val;
2433
2434 /* Preamble tuning for SSC */
2435 ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204);
2436 if (ret_val)
2437 return ret_val;
2438 }
2439
2440 if (hw->phy.type == e1000_phy_82578) {
2441 /* Return registers to default by doing a soft reset then
2442 * writing 0x3140 to the control register.
2443 */
2444 if (hw->phy.revision < 2) {
2445 e1000e_phy_sw_reset(hw);
2446 ret_val = e1e_wphy(hw, MII_BMCR, 0x3140);
2447 if (ret_val)
2448 return ret_val;
2449 }
2450 }
2451
2452 /* Select page 0 */
2453 ret_val = hw->phy.ops.acquire(hw);
2454 if (ret_val)
2455 return ret_val;
2456
2457 hw->phy.addr = 1;
2458 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
2459 hw->phy.ops.release(hw);
2460 if (ret_val)
2461 return ret_val;
2462
2463 /* Configure the K1 Si workaround during phy reset assuming there is
2464 * link so that it disables K1 if link is in 1Gbps.
2465 */
2466 ret_val = e1000_k1_gig_workaround_hv(hw, true);
2467 if (ret_val)
2468 return ret_val;
2469
2470 /* Workaround for link disconnects on a busy hub in half duplex */
2471 ret_val = hw->phy.ops.acquire(hw);
2472 if (ret_val)
2473 return ret_val;
2474 ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data);
2475 if (ret_val)
2476 goto release;
2477 ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF);
2478 if (ret_val)
2479 goto release;
2480
2481 /* set MSE higher to enable link to stay up when noise is high */
2482 ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034);
2483release:
2484 hw->phy.ops.release(hw);
2485
2486 return ret_val;
2487}
2488
2489/**
2490 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
2491 * @hw: pointer to the HW structure
2492 **/
2493void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
2494{
2495 u32 mac_reg;
2496 u16 i, phy_reg = 0;
2497 s32 ret_val;
2498
2499 ret_val = hw->phy.ops.acquire(hw);
2500 if (ret_val)
2501 return;
2502 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2503 if (ret_val)
2504 goto release;
2505
2506 /* Copy both RAL/H (rar_entry_count) and SHRAL/H to PHY */
2507 for (i = 0; i < (hw->mac.rar_entry_count); i++) {
2508 mac_reg = er32(RAL(i));
2509 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
2510 (u16)(mac_reg & 0xFFFF));
2511 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
2512 (u16)((mac_reg >> 16) & 0xFFFF));
2513
2514 mac_reg = er32(RAH(i));
2515 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
2516 (u16)(mac_reg & 0xFFFF));
2517 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
2518 (u16)((mac_reg & E1000_RAH_AV)
2519 >> 16));
2520 }
2521
2522 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2523
2524release:
2525 hw->phy.ops.release(hw);
2526}
2527
2528/**
2529 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
2530 * with 82579 PHY
2531 * @hw: pointer to the HW structure
2532 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
2533 **/
2534s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
2535{
2536 s32 ret_val = 0;
2537 u16 phy_reg, data;
2538 u32 mac_reg;
2539 u16 i;
2540
2541 if (hw->mac.type < e1000_pch2lan)
2542 return 0;
2543
2544 /* disable Rx path while enabling/disabling workaround */
2545 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
2546 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14));
2547 if (ret_val)
2548 return ret_val;
2549
2550 if (enable) {
2551 /* Write Rx addresses (rar_entry_count for RAL/H, and
2552 * SHRAL/H) and initial CRC values to the MAC
2553 */
2554 for (i = 0; i < hw->mac.rar_entry_count; i++) {
2555 u8 mac_addr[ETH_ALEN] = { 0 };
2556 u32 addr_high, addr_low;
2557
2558 addr_high = er32(RAH(i));
2559 if (!(addr_high & E1000_RAH_AV))
2560 continue;
2561 addr_low = er32(RAL(i));
2562 mac_addr[0] = (addr_low & 0xFF);
2563 mac_addr[1] = ((addr_low >> 8) & 0xFF);
2564 mac_addr[2] = ((addr_low >> 16) & 0xFF);
2565 mac_addr[3] = ((addr_low >> 24) & 0xFF);
2566 mac_addr[4] = (addr_high & 0xFF);
2567 mac_addr[5] = ((addr_high >> 8) & 0xFF);
2568
2569 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
2570 }
2571
2572 /* Write Rx addresses to the PHY */
2573 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
2574
2575 /* Enable jumbo frame workaround in the MAC */
2576 mac_reg = er32(FFLT_DBG);
2577 mac_reg &= ~BIT(14);
2578 mac_reg |= (7 << 15);
2579 ew32(FFLT_DBG, mac_reg);
2580
2581 mac_reg = er32(RCTL);
2582 mac_reg |= E1000_RCTL_SECRC;
2583 ew32(RCTL, mac_reg);
2584
2585 ret_val = e1000e_read_kmrn_reg(hw,
2586 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2587 &data);
2588 if (ret_val)
2589 return ret_val;
2590 ret_val = e1000e_write_kmrn_reg(hw,
2591 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2592 data | BIT(0));
2593 if (ret_val)
2594 return ret_val;
2595 ret_val = e1000e_read_kmrn_reg(hw,
2596 E1000_KMRNCTRLSTA_HD_CTRL,
2597 &data);
2598 if (ret_val)
2599 return ret_val;
2600 data &= ~(0xF << 8);
2601 data |= (0xB << 8);
2602 ret_val = e1000e_write_kmrn_reg(hw,
2603 E1000_KMRNCTRLSTA_HD_CTRL,
2604 data);
2605 if (ret_val)
2606 return ret_val;
2607
2608 /* Enable jumbo frame workaround in the PHY */
2609 e1e_rphy(hw, PHY_REG(769, 23), &data);
2610 data &= ~(0x7F << 5);
2611 data |= (0x37 << 5);
2612 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2613 if (ret_val)
2614 return ret_val;
2615 e1e_rphy(hw, PHY_REG(769, 16), &data);
2616 data &= ~BIT(13);
2617 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2618 if (ret_val)
2619 return ret_val;
2620 e1e_rphy(hw, PHY_REG(776, 20), &data);
2621 data &= ~(0x3FF << 2);
2622 data |= (E1000_TX_PTR_GAP << 2);
2623 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2624 if (ret_val)
2625 return ret_val;
2626 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100);
2627 if (ret_val)
2628 return ret_val;
2629 e1e_rphy(hw, HV_PM_CTRL, &data);
2630 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | BIT(10));
2631 if (ret_val)
2632 return ret_val;
2633 } else {
2634 /* Write MAC register values back to h/w defaults */
2635 mac_reg = er32(FFLT_DBG);
2636 mac_reg &= ~(0xF << 14);
2637 ew32(FFLT_DBG, mac_reg);
2638
2639 mac_reg = er32(RCTL);
2640 mac_reg &= ~E1000_RCTL_SECRC;
2641 ew32(RCTL, mac_reg);
2642
2643 ret_val = e1000e_read_kmrn_reg(hw,
2644 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2645 &data);
2646 if (ret_val)
2647 return ret_val;
2648 ret_val = e1000e_write_kmrn_reg(hw,
2649 E1000_KMRNCTRLSTA_CTRL_OFFSET,
2650 data & ~BIT(0));
2651 if (ret_val)
2652 return ret_val;
2653 ret_val = e1000e_read_kmrn_reg(hw,
2654 E1000_KMRNCTRLSTA_HD_CTRL,
2655 &data);
2656 if (ret_val)
2657 return ret_val;
2658 data &= ~(0xF << 8);
2659 data |= (0xB << 8);
2660 ret_val = e1000e_write_kmrn_reg(hw,
2661 E1000_KMRNCTRLSTA_HD_CTRL,
2662 data);
2663 if (ret_val)
2664 return ret_val;
2665
2666 /* Write PHY register values back to h/w defaults */
2667 e1e_rphy(hw, PHY_REG(769, 23), &data);
2668 data &= ~(0x7F << 5);
2669 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
2670 if (ret_val)
2671 return ret_val;
2672 e1e_rphy(hw, PHY_REG(769, 16), &data);
2673 data |= BIT(13);
2674 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
2675 if (ret_val)
2676 return ret_val;
2677 e1e_rphy(hw, PHY_REG(776, 20), &data);
2678 data &= ~(0x3FF << 2);
2679 data |= (0x8 << 2);
2680 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
2681 if (ret_val)
2682 return ret_val;
2683 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
2684 if (ret_val)
2685 return ret_val;
2686 e1e_rphy(hw, HV_PM_CTRL, &data);
2687 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~BIT(10));
2688 if (ret_val)
2689 return ret_val;
2690 }
2691
2692 /* re-enable Rx path after enabling/disabling workaround */
2693 return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~BIT(14));
2694}
2695
2696/**
2697 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
2698 * done after every PHY reset.
2699 **/
2700static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
2701{
2702 s32 ret_val = 0;
2703
2704 if (hw->mac.type != e1000_pch2lan)
2705 return 0;
2706
2707 /* Set MDIO slow mode before any other MDIO access */
2708 ret_val = e1000_set_mdio_slow_mode_hv(hw);
2709 if (ret_val)
2710 return ret_val;
2711
2712 ret_val = hw->phy.ops.acquire(hw);
2713 if (ret_val)
2714 return ret_val;
2715 /* set MSE higher to enable link to stay up when noise is high */
2716 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034);
2717 if (ret_val)
2718 goto release;
2719 /* drop link after 5 times MSE threshold was reached */
2720 ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005);
2721release:
2722 hw->phy.ops.release(hw);
2723
2724 return ret_val;
2725}
2726
2727/**
2728 * e1000_k1_gig_workaround_lv - K1 Si workaround
2729 * @hw: pointer to the HW structure
2730 *
2731 * Workaround to set the K1 beacon duration for 82579 parts in 10Mbps
2732 * Disable K1 in 1000Mbps and 100Mbps
2733 **/
2734static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
2735{
2736 s32 ret_val = 0;
2737 u16 status_reg = 0;
2738
2739 if (hw->mac.type != e1000_pch2lan)
2740 return 0;
2741
2742 /* Set K1 beacon duration based on 10Mbs speed */
2743 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
2744 if (ret_val)
2745 return ret_val;
2746
2747 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
2748 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
2749 if (status_reg &
2750 (HV_M_STATUS_SPEED_1000 | HV_M_STATUS_SPEED_100)) {
2751 u16 pm_phy_reg;
2752
2753 /* LV 1G/100 Packet drop issue wa */
2754 ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg);
2755 if (ret_val)
2756 return ret_val;
2757 pm_phy_reg &= ~HV_PM_CTRL_K1_ENABLE;
2758 ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg);
2759 if (ret_val)
2760 return ret_val;
2761 } else {
2762 u32 mac_reg;
2763
2764 mac_reg = er32(FEXTNVM4);
2765 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
2766 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
2767 ew32(FEXTNVM4, mac_reg);
2768 }
2769 }
2770
2771 return ret_val;
2772}
2773
2774/**
2775 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
2776 * @hw: pointer to the HW structure
2777 * @gate: boolean set to true to gate, false to ungate
2778 *
2779 * Gate/ungate the automatic PHY configuration via hardware; perform
2780 * the configuration via software instead.
2781 **/
2782static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
2783{
2784 u32 extcnf_ctrl;
2785
2786 if (hw->mac.type < e1000_pch2lan)
2787 return;
2788
2789 extcnf_ctrl = er32(EXTCNF_CTRL);
2790
2791 if (gate)
2792 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2793 else
2794 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
2795
2796 ew32(EXTCNF_CTRL, extcnf_ctrl);
2797}
2798
2799/**
2800 * e1000_lan_init_done_ich8lan - Check for PHY config completion
2801 * @hw: pointer to the HW structure
2802 *
2803 * Check the appropriate indication the MAC has finished configuring the
2804 * PHY after a software reset.
2805 **/
2806static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
2807{
2808 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
2809
2810 /* Wait for basic configuration completes before proceeding */
2811 do {
2812 data = er32(STATUS);
2813 data &= E1000_STATUS_LAN_INIT_DONE;
2814 usleep_range(100, 200);
2815 } while ((!data) && --loop);
2816
2817 /* If basic configuration is incomplete before the above loop
2818 * count reaches 0, loading the configuration from NVM will
2819 * leave the PHY in a bad state possibly resulting in no link.
2820 */
2821 if (loop == 0)
2822 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
2823
2824 /* Clear the Init Done bit for the next init event */
2825 data = er32(STATUS);
2826 data &= ~E1000_STATUS_LAN_INIT_DONE;
2827 ew32(STATUS, data);
2828}
2829
2830/**
2831 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
2832 * @hw: pointer to the HW structure
2833 **/
2834static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
2835{
2836 s32 ret_val = 0;
2837 u16 reg;
2838
2839 if (hw->phy.ops.check_reset_block(hw))
2840 return 0;
2841
2842 /* Allow time for h/w to get to quiescent state after reset */
2843 usleep_range(10000, 11000);
2844
2845 /* Perform any necessary post-reset workarounds */
2846 switch (hw->mac.type) {
2847 case e1000_pchlan:
2848 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
2849 if (ret_val)
2850 return ret_val;
2851 break;
2852 case e1000_pch2lan:
2853 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
2854 if (ret_val)
2855 return ret_val;
2856 break;
2857 default:
2858 break;
2859 }
2860
2861 /* Clear the host wakeup bit after lcd reset */
2862 if (hw->mac.type >= e1000_pchlan) {
2863 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
2864 reg &= ~BM_WUC_HOST_WU_BIT;
2865 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
2866 }
2867
2868 /* Configure the LCD with the extended configuration region in NVM */
2869 ret_val = e1000_sw_lcd_config_ich8lan(hw);
2870 if (ret_val)
2871 return ret_val;
2872
2873 /* Configure the LCD with the OEM bits in NVM */
2874 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
2875
2876 if (hw->mac.type == e1000_pch2lan) {
2877 /* Ungate automatic PHY configuration on non-managed 82579 */
2878 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
2879 usleep_range(10000, 11000);
2880 e1000_gate_hw_phy_config_ich8lan(hw, false);
2881 }
2882
2883 /* Set EEE LPI Update Timer to 200usec */
2884 ret_val = hw->phy.ops.acquire(hw);
2885 if (ret_val)
2886 return ret_val;
2887 ret_val = e1000_write_emi_reg_locked(hw,
2888 I82579_LPI_UPDATE_TIMER,
2889 0x1387);
2890 hw->phy.ops.release(hw);
2891 }
2892
2893 return ret_val;
2894}
2895
2896/**
2897 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
2898 * @hw: pointer to the HW structure
2899 *
2900 * Resets the PHY
2901 * This is a function pointer entry point called by drivers
2902 * or other shared routines.
2903 **/
2904static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
2905{
2906 s32 ret_val = 0;
2907
2908 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
2909 if ((hw->mac.type == e1000_pch2lan) &&
2910 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
2911 e1000_gate_hw_phy_config_ich8lan(hw, true);
2912
2913 ret_val = e1000e_phy_hw_reset_generic(hw);
2914 if (ret_val)
2915 return ret_val;
2916
2917 return e1000_post_phy_reset_ich8lan(hw);
2918}
2919
2920/**
2921 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
2922 * @hw: pointer to the HW structure
2923 * @active: true to enable LPLU, false to disable
2924 *
2925 * Sets the LPLU state according to the active flag. For PCH, if OEM write
2926 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
2927 * the phy speed. This function will manually set the LPLU bit and restart
2928 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
2929 * since it configures the same bit.
2930 **/
2931static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
2932{
2933 s32 ret_val;
2934 u16 oem_reg;
2935
2936 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
2937 if (ret_val)
2938 return ret_val;
2939
2940 if (active)
2941 oem_reg |= HV_OEM_BITS_LPLU;
2942 else
2943 oem_reg &= ~HV_OEM_BITS_LPLU;
2944
2945 if (!hw->phy.ops.check_reset_block(hw))
2946 oem_reg |= HV_OEM_BITS_RESTART_AN;
2947
2948 return e1e_wphy(hw, HV_OEM_BITS, oem_reg);
2949}
2950
2951/**
2952 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
2953 * @hw: pointer to the HW structure
2954 * @active: true to enable LPLU, false to disable
2955 *
2956 * Sets the LPLU D0 state according to the active flag. When
2957 * activating LPLU this function also disables smart speed
2958 * and vice versa. LPLU will not be activated unless the
2959 * device autonegotiation advertisement meets standards of
2960 * either 10 or 10/100 or 10/100/1000 at all duplexes.
2961 * This is a function pointer entry point only called by
2962 * PHY setup routines.
2963 **/
2964static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
2965{
2966 struct e1000_phy_info *phy = &hw->phy;
2967 u32 phy_ctrl;
2968 s32 ret_val = 0;
2969 u16 data;
2970
2971 if (phy->type == e1000_phy_ife)
2972 return 0;
2973
2974 phy_ctrl = er32(PHY_CTRL);
2975
2976 if (active) {
2977 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
2978 ew32(PHY_CTRL, phy_ctrl);
2979
2980 if (phy->type != e1000_phy_igp_3)
2981 return 0;
2982
2983 /* Call gig speed drop workaround on LPLU before accessing
2984 * any PHY registers
2985 */
2986 if (hw->mac.type == e1000_ich8lan)
2987 e1000e_gig_downshift_workaround_ich8lan(hw);
2988
2989 /* When LPLU is enabled, we should disable SmartSpeed */
2990 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2991 if (ret_val)
2992 return ret_val;
2993 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2994 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2995 if (ret_val)
2996 return ret_val;
2997 } else {
2998 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
2999 ew32(PHY_CTRL, phy_ctrl);
3000
3001 if (phy->type != e1000_phy_igp_3)
3002 return 0;
3003
3004 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3005 * during Dx states where the power conservation is most
3006 * important. During driver activity we should enable
3007 * SmartSpeed, so performance is maintained.
3008 */
3009 if (phy->smart_speed == e1000_smart_speed_on) {
3010 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3011 &data);
3012 if (ret_val)
3013 return ret_val;
3014
3015 data |= IGP01E1000_PSCFR_SMART_SPEED;
3016 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3017 data);
3018 if (ret_val)
3019 return ret_val;
3020 } else if (phy->smart_speed == e1000_smart_speed_off) {
3021 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3022 &data);
3023 if (ret_val)
3024 return ret_val;
3025
3026 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3027 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3028 data);
3029 if (ret_val)
3030 return ret_val;
3031 }
3032 }
3033
3034 return 0;
3035}
3036
3037/**
3038 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
3039 * @hw: pointer to the HW structure
3040 * @active: true to enable LPLU, false to disable
3041 *
3042 * Sets the LPLU D3 state according to the active flag. When
3043 * activating LPLU this function also disables smart speed
3044 * and vice versa. LPLU will not be activated unless the
3045 * device autonegotiation advertisement meets standards of
3046 * either 10 or 10/100 or 10/100/1000 at all duplexes.
3047 * This is a function pointer entry point only called by
3048 * PHY setup routines.
3049 **/
3050static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
3051{
3052 struct e1000_phy_info *phy = &hw->phy;
3053 u32 phy_ctrl;
3054 s32 ret_val = 0;
3055 u16 data;
3056
3057 phy_ctrl = er32(PHY_CTRL);
3058
3059 if (!active) {
3060 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
3061 ew32(PHY_CTRL, phy_ctrl);
3062
3063 if (phy->type != e1000_phy_igp_3)
3064 return 0;
3065
3066 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
3067 * during Dx states where the power conservation is most
3068 * important. During driver activity we should enable
3069 * SmartSpeed, so performance is maintained.
3070 */
3071 if (phy->smart_speed == e1000_smart_speed_on) {
3072 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3073 &data);
3074 if (ret_val)
3075 return ret_val;
3076
3077 data |= IGP01E1000_PSCFR_SMART_SPEED;
3078 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3079 data);
3080 if (ret_val)
3081 return ret_val;
3082 } else if (phy->smart_speed == e1000_smart_speed_off) {
3083 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3084 &data);
3085 if (ret_val)
3086 return ret_val;
3087
3088 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3089 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
3090 data);
3091 if (ret_val)
3092 return ret_val;
3093 }
3094 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
3095 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
3096 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
3097 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
3098 ew32(PHY_CTRL, phy_ctrl);
3099
3100 if (phy->type != e1000_phy_igp_3)
3101 return 0;
3102
3103 /* Call gig speed drop workaround on LPLU before accessing
3104 * any PHY registers
3105 */
3106 if (hw->mac.type == e1000_ich8lan)
3107 e1000e_gig_downshift_workaround_ich8lan(hw);
3108
3109 /* When LPLU is enabled, we should disable SmartSpeed */
3110 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
3111 if (ret_val)
3112 return ret_val;
3113
3114 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
3115 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
3116 }
3117
3118 return ret_val;
3119}
3120
3121/**
3122 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
3123 * @hw: pointer to the HW structure
3124 * @bank: pointer to the variable that returns the active bank
3125 *
3126 * Reads signature byte from the NVM using the flash access registers.
3127 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
3128 **/
3129static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
3130{
3131 u32 eecd;
3132 struct e1000_nvm_info *nvm = &hw->nvm;
3133 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
3134 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
3135 u32 nvm_dword = 0;
3136 u8 sig_byte = 0;
3137 s32 ret_val;
3138
3139 switch (hw->mac.type) {
3140 case e1000_pch_spt:
3141 case e1000_pch_cnp:
3142 case e1000_pch_tgp:
3143 case e1000_pch_adp:
3144 bank1_offset = nvm->flash_bank_size;
3145 act_offset = E1000_ICH_NVM_SIG_WORD;
3146
3147 /* set bank to 0 in case flash read fails */
3148 *bank = 0;
3149
3150 /* Check bank 0 */
3151 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset,
3152 &nvm_dword);
3153 if (ret_val)
3154 return ret_val;
3155 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3156 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3157 E1000_ICH_NVM_SIG_VALUE) {
3158 *bank = 0;
3159 return 0;
3160 }
3161
3162 /* Check bank 1 */
3163 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset +
3164 bank1_offset,
3165 &nvm_dword);
3166 if (ret_val)
3167 return ret_val;
3168 sig_byte = (u8)((nvm_dword & 0xFF00) >> 8);
3169 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3170 E1000_ICH_NVM_SIG_VALUE) {
3171 *bank = 1;
3172 return 0;
3173 }
3174
3175 e_dbg("ERROR: No valid NVM bank present\n");
3176 return -E1000_ERR_NVM;
3177 case e1000_ich8lan:
3178 case e1000_ich9lan:
3179 eecd = er32(EECD);
3180 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
3181 E1000_EECD_SEC1VAL_VALID_MASK) {
3182 if (eecd & E1000_EECD_SEC1VAL)
3183 *bank = 1;
3184 else
3185 *bank = 0;
3186
3187 return 0;
3188 }
3189 e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n");
3190 fallthrough;
3191 default:
3192 /* set bank to 0 in case flash read fails */
3193 *bank = 0;
3194
3195 /* Check bank 0 */
3196 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
3197 &sig_byte);
3198 if (ret_val)
3199 return ret_val;
3200 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3201 E1000_ICH_NVM_SIG_VALUE) {
3202 *bank = 0;
3203 return 0;
3204 }
3205
3206 /* Check bank 1 */
3207 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
3208 bank1_offset,
3209 &sig_byte);
3210 if (ret_val)
3211 return ret_val;
3212 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
3213 E1000_ICH_NVM_SIG_VALUE) {
3214 *bank = 1;
3215 return 0;
3216 }
3217
3218 e_dbg("ERROR: No valid NVM bank present\n");
3219 return -E1000_ERR_NVM;
3220 }
3221}
3222
3223/**
3224 * e1000_read_nvm_spt - NVM access for SPT
3225 * @hw: pointer to the HW structure
3226 * @offset: The offset (in bytes) of the word(s) to read.
3227 * @words: Size of data to read in words.
3228 * @data: pointer to the word(s) to read at offset.
3229 *
3230 * Reads a word(s) from the NVM
3231 **/
3232static s32 e1000_read_nvm_spt(struct e1000_hw *hw, u16 offset, u16 words,
3233 u16 *data)
3234{
3235 struct e1000_nvm_info *nvm = &hw->nvm;
3236 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3237 u32 act_offset;
3238 s32 ret_val = 0;
3239 u32 bank = 0;
3240 u32 dword = 0;
3241 u16 offset_to_read;
3242 u16 i;
3243
3244 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3245 (words == 0)) {
3246 e_dbg("nvm parameter(s) out of bounds\n");
3247 ret_val = -E1000_ERR_NVM;
3248 goto out;
3249 }
3250
3251 nvm->ops.acquire(hw);
3252
3253 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3254 if (ret_val) {
3255 e_dbg("Could not detect valid bank, assuming bank 0\n");
3256 bank = 0;
3257 }
3258
3259 act_offset = (bank) ? nvm->flash_bank_size : 0;
3260 act_offset += offset;
3261
3262 ret_val = 0;
3263
3264 for (i = 0; i < words; i += 2) {
3265 if (words - i == 1) {
3266 if (dev_spec->shadow_ram[offset + i].modified) {
3267 data[i] =
3268 dev_spec->shadow_ram[offset + i].value;
3269 } else {
3270 offset_to_read = act_offset + i -
3271 ((act_offset + i) % 2);
3272 ret_val =
3273 e1000_read_flash_dword_ich8lan(hw,
3274 offset_to_read,
3275 &dword);
3276 if (ret_val)
3277 break;
3278 if ((act_offset + i) % 2 == 0)
3279 data[i] = (u16)(dword & 0xFFFF);
3280 else
3281 data[i] = (u16)((dword >> 16) & 0xFFFF);
3282 }
3283 } else {
3284 offset_to_read = act_offset + i;
3285 if (!(dev_spec->shadow_ram[offset + i].modified) ||
3286 !(dev_spec->shadow_ram[offset + i + 1].modified)) {
3287 ret_val =
3288 e1000_read_flash_dword_ich8lan(hw,
3289 offset_to_read,
3290 &dword);
3291 if (ret_val)
3292 break;
3293 }
3294 if (dev_spec->shadow_ram[offset + i].modified)
3295 data[i] =
3296 dev_spec->shadow_ram[offset + i].value;
3297 else
3298 data[i] = (u16)(dword & 0xFFFF);
3299 if (dev_spec->shadow_ram[offset + i].modified)
3300 data[i + 1] =
3301 dev_spec->shadow_ram[offset + i + 1].value;
3302 else
3303 data[i + 1] = (u16)(dword >> 16 & 0xFFFF);
3304 }
3305 }
3306
3307 nvm->ops.release(hw);
3308
3309out:
3310 if (ret_val)
3311 e_dbg("NVM read error: %d\n", ret_val);
3312
3313 return ret_val;
3314}
3315
3316/**
3317 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
3318 * @hw: pointer to the HW structure
3319 * @offset: The offset (in bytes) of the word(s) to read.
3320 * @words: Size of data to read in words
3321 * @data: Pointer to the word(s) to read at offset.
3322 *
3323 * Reads a word(s) from the NVM using the flash access registers.
3324 **/
3325static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3326 u16 *data)
3327{
3328 struct e1000_nvm_info *nvm = &hw->nvm;
3329 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3330 u32 act_offset;
3331 s32 ret_val = 0;
3332 u32 bank = 0;
3333 u16 i, word;
3334
3335 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3336 (words == 0)) {
3337 e_dbg("nvm parameter(s) out of bounds\n");
3338 ret_val = -E1000_ERR_NVM;
3339 goto out;
3340 }
3341
3342 nvm->ops.acquire(hw);
3343
3344 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3345 if (ret_val) {
3346 e_dbg("Could not detect valid bank, assuming bank 0\n");
3347 bank = 0;
3348 }
3349
3350 act_offset = (bank) ? nvm->flash_bank_size : 0;
3351 act_offset += offset;
3352
3353 ret_val = 0;
3354 for (i = 0; i < words; i++) {
3355 if (dev_spec->shadow_ram[offset + i].modified) {
3356 data[i] = dev_spec->shadow_ram[offset + i].value;
3357 } else {
3358 ret_val = e1000_read_flash_word_ich8lan(hw,
3359 act_offset + i,
3360 &word);
3361 if (ret_val)
3362 break;
3363 data[i] = word;
3364 }
3365 }
3366
3367 nvm->ops.release(hw);
3368
3369out:
3370 if (ret_val)
3371 e_dbg("NVM read error: %d\n", ret_val);
3372
3373 return ret_val;
3374}
3375
3376/**
3377 * e1000_flash_cycle_init_ich8lan - Initialize flash
3378 * @hw: pointer to the HW structure
3379 *
3380 * This function does initial flash setup so that a new read/write/erase cycle
3381 * can be started.
3382 **/
3383static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
3384{
3385 union ich8_hws_flash_status hsfsts;
3386 s32 ret_val = -E1000_ERR_NVM;
3387
3388 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3389
3390 /* Check if the flash descriptor is valid */
3391 if (!hsfsts.hsf_status.fldesvalid) {
3392 e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n");
3393 return -E1000_ERR_NVM;
3394 }
3395
3396 /* Clear FCERR and DAEL in hw status by writing 1 */
3397 hsfsts.hsf_status.flcerr = 1;
3398 hsfsts.hsf_status.dael = 1;
3399 if (hw->mac.type >= e1000_pch_spt)
3400 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3401 else
3402 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3403
3404 /* Either we should have a hardware SPI cycle in progress
3405 * bit to check against, in order to start a new cycle or
3406 * FDONE bit should be changed in the hardware so that it
3407 * is 1 after hardware reset, which can then be used as an
3408 * indication whether a cycle is in progress or has been
3409 * completed.
3410 */
3411
3412 if (!hsfsts.hsf_status.flcinprog) {
3413 /* There is no cycle running at present,
3414 * so we can start a cycle.
3415 * Begin by setting Flash Cycle Done.
3416 */
3417 hsfsts.hsf_status.flcdone = 1;
3418 if (hw->mac.type >= e1000_pch_spt)
3419 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval & 0xFFFF);
3420 else
3421 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3422 ret_val = 0;
3423 } else {
3424 s32 i;
3425
3426 /* Otherwise poll for sometime so the current
3427 * cycle has a chance to end before giving up.
3428 */
3429 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
3430 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3431 if (!hsfsts.hsf_status.flcinprog) {
3432 ret_val = 0;
3433 break;
3434 }
3435 udelay(1);
3436 }
3437 if (!ret_val) {
3438 /* Successful in waiting for previous cycle to timeout,
3439 * now set the Flash Cycle Done.
3440 */
3441 hsfsts.hsf_status.flcdone = 1;
3442 if (hw->mac.type >= e1000_pch_spt)
3443 ew32flash(ICH_FLASH_HSFSTS,
3444 hsfsts.regval & 0xFFFF);
3445 else
3446 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
3447 } else {
3448 e_dbg("Flash controller busy, cannot get access\n");
3449 }
3450 }
3451
3452 return ret_val;
3453}
3454
3455/**
3456 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
3457 * @hw: pointer to the HW structure
3458 * @timeout: maximum time to wait for completion
3459 *
3460 * This function starts a flash cycle and waits for its completion.
3461 **/
3462static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
3463{
3464 union ich8_hws_flash_ctrl hsflctl;
3465 union ich8_hws_flash_status hsfsts;
3466 u32 i = 0;
3467
3468 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
3469 if (hw->mac.type >= e1000_pch_spt)
3470 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3471 else
3472 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3473 hsflctl.hsf_ctrl.flcgo = 1;
3474
3475 if (hw->mac.type >= e1000_pch_spt)
3476 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
3477 else
3478 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3479
3480 /* wait till FDONE bit is set to 1 */
3481 do {
3482 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3483 if (hsfsts.hsf_status.flcdone)
3484 break;
3485 udelay(1);
3486 } while (i++ < timeout);
3487
3488 if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr)
3489 return 0;
3490
3491 return -E1000_ERR_NVM;
3492}
3493
3494/**
3495 * e1000_read_flash_dword_ich8lan - Read dword from flash
3496 * @hw: pointer to the HW structure
3497 * @offset: offset to data location
3498 * @data: pointer to the location for storing the data
3499 *
3500 * Reads the flash dword at offset into data. Offset is converted
3501 * to bytes before read.
3502 **/
3503static s32 e1000_read_flash_dword_ich8lan(struct e1000_hw *hw, u32 offset,
3504 u32 *data)
3505{
3506 /* Must convert word offset into bytes. */
3507 offset <<= 1;
3508 return e1000_read_flash_data32_ich8lan(hw, offset, data);
3509}
3510
3511/**
3512 * e1000_read_flash_word_ich8lan - Read word from flash
3513 * @hw: pointer to the HW structure
3514 * @offset: offset to data location
3515 * @data: pointer to the location for storing the data
3516 *
3517 * Reads the flash word at offset into data. Offset is converted
3518 * to bytes before read.
3519 **/
3520static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
3521 u16 *data)
3522{
3523 /* Must convert offset into bytes. */
3524 offset <<= 1;
3525
3526 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
3527}
3528
3529/**
3530 * e1000_read_flash_byte_ich8lan - Read byte from flash
3531 * @hw: pointer to the HW structure
3532 * @offset: The offset of the byte to read.
3533 * @data: Pointer to a byte to store the value read.
3534 *
3535 * Reads a single byte from the NVM using the flash access registers.
3536 **/
3537static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
3538 u8 *data)
3539{
3540 s32 ret_val;
3541 u16 word = 0;
3542
3543 /* In SPT, only 32 bits access is supported,
3544 * so this function should not be called.
3545 */
3546 if (hw->mac.type >= e1000_pch_spt)
3547 return -E1000_ERR_NVM;
3548 else
3549 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
3550
3551 if (ret_val)
3552 return ret_val;
3553
3554 *data = (u8)word;
3555
3556 return 0;
3557}
3558
3559/**
3560 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
3561 * @hw: pointer to the HW structure
3562 * @offset: The offset (in bytes) of the byte or word to read.
3563 * @size: Size of data to read, 1=byte 2=word
3564 * @data: Pointer to the word to store the value read.
3565 *
3566 * Reads a byte or word from the NVM using the flash access registers.
3567 **/
3568static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
3569 u8 size, u16 *data)
3570{
3571 union ich8_hws_flash_status hsfsts;
3572 union ich8_hws_flash_ctrl hsflctl;
3573 u32 flash_linear_addr;
3574 u32 flash_data = 0;
3575 s32 ret_val = -E1000_ERR_NVM;
3576 u8 count = 0;
3577
3578 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
3579 return -E1000_ERR_NVM;
3580
3581 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3582 hw->nvm.flash_base_addr);
3583
3584 do {
3585 udelay(1);
3586 /* Steps */
3587 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3588 if (ret_val)
3589 break;
3590
3591 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
3592 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3593 hsflctl.hsf_ctrl.fldbcount = size - 1;
3594 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3595 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
3596
3597 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3598
3599 ret_val =
3600 e1000_flash_cycle_ich8lan(hw,
3601 ICH_FLASH_READ_COMMAND_TIMEOUT);
3602
3603 /* Check if FCERR is set to 1, if set to 1, clear it
3604 * and try the whole sequence a few more times, else
3605 * read in (shift in) the Flash Data0, the order is
3606 * least significant byte first msb to lsb
3607 */
3608 if (!ret_val) {
3609 flash_data = er32flash(ICH_FLASH_FDATA0);
3610 if (size == 1)
3611 *data = (u8)(flash_data & 0x000000FF);
3612 else if (size == 2)
3613 *data = (u16)(flash_data & 0x0000FFFF);
3614 break;
3615 } else {
3616 /* If we've gotten here, then things are probably
3617 * completely hosed, but if the error condition is
3618 * detected, it won't hurt to give it another try...
3619 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3620 */
3621 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3622 if (hsfsts.hsf_status.flcerr) {
3623 /* Repeat for some time before giving up. */
3624 continue;
3625 } else if (!hsfsts.hsf_status.flcdone) {
3626 e_dbg("Timeout error - flash cycle did not complete.\n");
3627 break;
3628 }
3629 }
3630 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3631
3632 return ret_val;
3633}
3634
3635/**
3636 * e1000_read_flash_data32_ich8lan - Read dword from NVM
3637 * @hw: pointer to the HW structure
3638 * @offset: The offset (in bytes) of the dword to read.
3639 * @data: Pointer to the dword to store the value read.
3640 *
3641 * Reads a byte or word from the NVM using the flash access registers.
3642 **/
3643
3644static s32 e1000_read_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
3645 u32 *data)
3646{
3647 union ich8_hws_flash_status hsfsts;
3648 union ich8_hws_flash_ctrl hsflctl;
3649 u32 flash_linear_addr;
3650 s32 ret_val = -E1000_ERR_NVM;
3651 u8 count = 0;
3652
3653 if (offset > ICH_FLASH_LINEAR_ADDR_MASK || hw->mac.type < e1000_pch_spt)
3654 return -E1000_ERR_NVM;
3655 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
3656 hw->nvm.flash_base_addr);
3657
3658 do {
3659 udelay(1);
3660 /* Steps */
3661 ret_val = e1000_flash_cycle_init_ich8lan(hw);
3662 if (ret_val)
3663 break;
3664 /* In SPT, This register is in Lan memory space, not flash.
3665 * Therefore, only 32 bit access is supported
3666 */
3667 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
3668
3669 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
3670 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
3671 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
3672 /* In SPT, This register is in Lan memory space, not flash.
3673 * Therefore, only 32 bit access is supported
3674 */
3675 ew32flash(ICH_FLASH_HSFSTS, (u32)hsflctl.regval << 16);
3676 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
3677
3678 ret_val =
3679 e1000_flash_cycle_ich8lan(hw,
3680 ICH_FLASH_READ_COMMAND_TIMEOUT);
3681
3682 /* Check if FCERR is set to 1, if set to 1, clear it
3683 * and try the whole sequence a few more times, else
3684 * read in (shift in) the Flash Data0, the order is
3685 * least significant byte first msb to lsb
3686 */
3687 if (!ret_val) {
3688 *data = er32flash(ICH_FLASH_FDATA0);
3689 break;
3690 } else {
3691 /* If we've gotten here, then things are probably
3692 * completely hosed, but if the error condition is
3693 * detected, it won't hurt to give it another try...
3694 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
3695 */
3696 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
3697 if (hsfsts.hsf_status.flcerr) {
3698 /* Repeat for some time before giving up. */
3699 continue;
3700 } else if (!hsfsts.hsf_status.flcdone) {
3701 e_dbg("Timeout error - flash cycle did not complete.\n");
3702 break;
3703 }
3704 }
3705 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
3706
3707 return ret_val;
3708}
3709
3710/**
3711 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
3712 * @hw: pointer to the HW structure
3713 * @offset: The offset (in bytes) of the word(s) to write.
3714 * @words: Size of data to write in words
3715 * @data: Pointer to the word(s) to write at offset.
3716 *
3717 * Writes a byte or word to the NVM using the flash access registers.
3718 **/
3719static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
3720 u16 *data)
3721{
3722 struct e1000_nvm_info *nvm = &hw->nvm;
3723 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3724 u16 i;
3725
3726 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
3727 (words == 0)) {
3728 e_dbg("nvm parameter(s) out of bounds\n");
3729 return -E1000_ERR_NVM;
3730 }
3731
3732 nvm->ops.acquire(hw);
3733
3734 for (i = 0; i < words; i++) {
3735 dev_spec->shadow_ram[offset + i].modified = true;
3736 dev_spec->shadow_ram[offset + i].value = data[i];
3737 }
3738
3739 nvm->ops.release(hw);
3740
3741 return 0;
3742}
3743
3744/**
3745 * e1000_update_nvm_checksum_spt - Update the checksum for NVM
3746 * @hw: pointer to the HW structure
3747 *
3748 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3749 * which writes the checksum to the shadow ram. The changes in the shadow
3750 * ram are then committed to the EEPROM by processing each bank at a time
3751 * checking for the modified bit and writing only the pending changes.
3752 * After a successful commit, the shadow ram is cleared and is ready for
3753 * future writes.
3754 **/
3755static s32 e1000_update_nvm_checksum_spt(struct e1000_hw *hw)
3756{
3757 struct e1000_nvm_info *nvm = &hw->nvm;
3758 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3759 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3760 s32 ret_val;
3761 u32 dword = 0;
3762
3763 ret_val = e1000e_update_nvm_checksum_generic(hw);
3764 if (ret_val)
3765 goto out;
3766
3767 if (nvm->type != e1000_nvm_flash_sw)
3768 goto out;
3769
3770 nvm->ops.acquire(hw);
3771
3772 /* We're writing to the opposite bank so if we're on bank 1,
3773 * write to bank 0 etc. We also need to erase the segment that
3774 * is going to be written
3775 */
3776 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3777 if (ret_val) {
3778 e_dbg("Could not detect valid bank, assuming bank 0\n");
3779 bank = 0;
3780 }
3781
3782 if (bank == 0) {
3783 new_bank_offset = nvm->flash_bank_size;
3784 old_bank_offset = 0;
3785 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3786 if (ret_val)
3787 goto release;
3788 } else {
3789 old_bank_offset = nvm->flash_bank_size;
3790 new_bank_offset = 0;
3791 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3792 if (ret_val)
3793 goto release;
3794 }
3795 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i += 2) {
3796 /* Determine whether to write the value stored
3797 * in the other NVM bank or a modified value stored
3798 * in the shadow RAM
3799 */
3800 ret_val = e1000_read_flash_dword_ich8lan(hw,
3801 i + old_bank_offset,
3802 &dword);
3803
3804 if (dev_spec->shadow_ram[i].modified) {
3805 dword &= 0xffff0000;
3806 dword |= (dev_spec->shadow_ram[i].value & 0xffff);
3807 }
3808 if (dev_spec->shadow_ram[i + 1].modified) {
3809 dword &= 0x0000ffff;
3810 dword |= ((dev_spec->shadow_ram[i + 1].value & 0xffff)
3811 << 16);
3812 }
3813 if (ret_val)
3814 break;
3815
3816 /* If the word is 0x13, then make sure the signature bits
3817 * (15:14) are 11b until the commit has completed.
3818 * This will allow us to write 10b which indicates the
3819 * signature is valid. We want to do this after the write
3820 * has completed so that we don't mark the segment valid
3821 * while the write is still in progress
3822 */
3823 if (i == E1000_ICH_NVM_SIG_WORD - 1)
3824 dword |= E1000_ICH_NVM_SIG_MASK << 16;
3825
3826 /* Convert offset to bytes. */
3827 act_offset = (i + new_bank_offset) << 1;
3828
3829 usleep_range(100, 200);
3830
3831 /* Write the data to the new bank. Offset in words */
3832 act_offset = i + new_bank_offset;
3833 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset,
3834 dword);
3835 if (ret_val)
3836 break;
3837 }
3838
3839 /* Don't bother writing the segment valid bits if sector
3840 * programming failed.
3841 */
3842 if (ret_val) {
3843 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
3844 e_dbg("Flash commit failed.\n");
3845 goto release;
3846 }
3847
3848 /* Finally validate the new segment by setting bit 15:14
3849 * to 10b in word 0x13 , this can be done without an
3850 * erase as well since these bits are 11 to start with
3851 * and we need to change bit 14 to 0b
3852 */
3853 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
3854
3855 /*offset in words but we read dword */
3856 --act_offset;
3857 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3858
3859 if (ret_val)
3860 goto release;
3861
3862 dword &= 0xBFFFFFFF;
3863 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3864
3865 if (ret_val)
3866 goto release;
3867
3868 /* And invalidate the previously valid segment by setting
3869 * its signature word (0x13) high_byte to 0b. This can be
3870 * done without an erase because flash erase sets all bits
3871 * to 1's. We can write 1's to 0's without an erase
3872 */
3873 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
3874
3875 /* offset in words but we read dword */
3876 act_offset = old_bank_offset + E1000_ICH_NVM_SIG_WORD - 1;
3877 ret_val = e1000_read_flash_dword_ich8lan(hw, act_offset, &dword);
3878
3879 if (ret_val)
3880 goto release;
3881
3882 dword &= 0x00FFFFFF;
3883 ret_val = e1000_retry_write_flash_dword_ich8lan(hw, act_offset, dword);
3884
3885 if (ret_val)
3886 goto release;
3887
3888 /* Great! Everything worked, we can now clear the cached entries. */
3889 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3890 dev_spec->shadow_ram[i].modified = false;
3891 dev_spec->shadow_ram[i].value = 0xFFFF;
3892 }
3893
3894release:
3895 nvm->ops.release(hw);
3896
3897 /* Reload the EEPROM, or else modifications will not appear
3898 * until after the next adapter reset.
3899 */
3900 if (!ret_val) {
3901 nvm->ops.reload(hw);
3902 usleep_range(10000, 11000);
3903 }
3904
3905out:
3906 if (ret_val)
3907 e_dbg("NVM update error: %d\n", ret_val);
3908
3909 return ret_val;
3910}
3911
3912/**
3913 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
3914 * @hw: pointer to the HW structure
3915 *
3916 * The NVM checksum is updated by calling the generic update_nvm_checksum,
3917 * which writes the checksum to the shadow ram. The changes in the shadow
3918 * ram are then committed to the EEPROM by processing each bank at a time
3919 * checking for the modified bit and writing only the pending changes.
3920 * After a successful commit, the shadow ram is cleared and is ready for
3921 * future writes.
3922 **/
3923static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
3924{
3925 struct e1000_nvm_info *nvm = &hw->nvm;
3926 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3927 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
3928 s32 ret_val;
3929 u16 data = 0;
3930
3931 ret_val = e1000e_update_nvm_checksum_generic(hw);
3932 if (ret_val)
3933 goto out;
3934
3935 if (nvm->type != e1000_nvm_flash_sw)
3936 goto out;
3937
3938 nvm->ops.acquire(hw);
3939
3940 /* We're writing to the opposite bank so if we're on bank 1,
3941 * write to bank 0 etc. We also need to erase the segment that
3942 * is going to be written
3943 */
3944 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
3945 if (ret_val) {
3946 e_dbg("Could not detect valid bank, assuming bank 0\n");
3947 bank = 0;
3948 }
3949
3950 if (bank == 0) {
3951 new_bank_offset = nvm->flash_bank_size;
3952 old_bank_offset = 0;
3953 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
3954 if (ret_val)
3955 goto release;
3956 } else {
3957 old_bank_offset = nvm->flash_bank_size;
3958 new_bank_offset = 0;
3959 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
3960 if (ret_val)
3961 goto release;
3962 }
3963 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
3964 if (dev_spec->shadow_ram[i].modified) {
3965 data = dev_spec->shadow_ram[i].value;
3966 } else {
3967 ret_val = e1000_read_flash_word_ich8lan(hw, i +
3968 old_bank_offset,
3969 &data);
3970 if (ret_val)
3971 break;
3972 }
3973
3974 /* If the word is 0x13, then make sure the signature bits
3975 * (15:14) are 11b until the commit has completed.
3976 * This will allow us to write 10b which indicates the
3977 * signature is valid. We want to do this after the write
3978 * has completed so that we don't mark the segment valid
3979 * while the write is still in progress
3980 */
3981 if (i == E1000_ICH_NVM_SIG_WORD)
3982 data |= E1000_ICH_NVM_SIG_MASK;
3983
3984 /* Convert offset to bytes. */
3985 act_offset = (i + new_bank_offset) << 1;
3986
3987 usleep_range(100, 200);
3988 /* Write the bytes to the new bank. */
3989 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3990 act_offset,
3991 (u8)data);
3992 if (ret_val)
3993 break;
3994
3995 usleep_range(100, 200);
3996 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
3997 act_offset + 1,
3998 (u8)(data >> 8));
3999 if (ret_val)
4000 break;
4001 }
4002
4003 /* Don't bother writing the segment valid bits if sector
4004 * programming failed.
4005 */
4006 if (ret_val) {
4007 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
4008 e_dbg("Flash commit failed.\n");
4009 goto release;
4010 }
4011
4012 /* Finally validate the new segment by setting bit 15:14
4013 * to 10b in word 0x13 , this can be done without an
4014 * erase as well since these bits are 11 to start with
4015 * and we need to change bit 14 to 0b
4016 */
4017 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
4018 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
4019 if (ret_val)
4020 goto release;
4021
4022 data &= 0xBFFF;
4023 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
4024 act_offset * 2 + 1,
4025 (u8)(data >> 8));
4026 if (ret_val)
4027 goto release;
4028
4029 /* And invalidate the previously valid segment by setting
4030 * its signature word (0x13) high_byte to 0b. This can be
4031 * done without an erase because flash erase sets all bits
4032 * to 1's. We can write 1's to 0's without an erase
4033 */
4034 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
4035 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
4036 if (ret_val)
4037 goto release;
4038
4039 /* Great! Everything worked, we can now clear the cached entries. */
4040 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
4041 dev_spec->shadow_ram[i].modified = false;
4042 dev_spec->shadow_ram[i].value = 0xFFFF;
4043 }
4044
4045release:
4046 nvm->ops.release(hw);
4047
4048 /* Reload the EEPROM, or else modifications will not appear
4049 * until after the next adapter reset.
4050 */
4051 if (!ret_val) {
4052 nvm->ops.reload(hw);
4053 usleep_range(10000, 11000);
4054 }
4055
4056out:
4057 if (ret_val)
4058 e_dbg("NVM update error: %d\n", ret_val);
4059
4060 return ret_val;
4061}
4062
4063/**
4064 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
4065 * @hw: pointer to the HW structure
4066 *
4067 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
4068 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
4069 * calculated, in which case we need to calculate the checksum and set bit 6.
4070 **/
4071static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
4072{
4073 s32 ret_val;
4074 u16 data;
4075 u16 word;
4076 u16 valid_csum_mask;
4077
4078 /* Read NVM and check Invalid Image CSUM bit. If this bit is 0,
4079 * the checksum needs to be fixed. This bit is an indication that
4080 * the NVM was prepared by OEM software and did not calculate
4081 * the checksum...a likely scenario.
4082 */
4083 switch (hw->mac.type) {
4084 case e1000_pch_lpt:
4085 case e1000_pch_spt:
4086 case e1000_pch_cnp:
4087 case e1000_pch_tgp:
4088 case e1000_pch_adp:
4089 word = NVM_COMPAT;
4090 valid_csum_mask = NVM_COMPAT_VALID_CSUM;
4091 break;
4092 default:
4093 word = NVM_FUTURE_INIT_WORD1;
4094 valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM;
4095 break;
4096 }
4097
4098 ret_val = e1000_read_nvm(hw, word, 1, &data);
4099 if (ret_val)
4100 return ret_val;
4101
4102 if (!(data & valid_csum_mask)) {
4103 data |= valid_csum_mask;
4104 ret_val = e1000_write_nvm(hw, word, 1, &data);
4105 if (ret_val)
4106 return ret_val;
4107 ret_val = e1000e_update_nvm_checksum(hw);
4108 if (ret_val)
4109 return ret_val;
4110 }
4111
4112 return e1000e_validate_nvm_checksum_generic(hw);
4113}
4114
4115/**
4116 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
4117 * @hw: pointer to the HW structure
4118 *
4119 * To prevent malicious write/erase of the NVM, set it to be read-only
4120 * so that the hardware ignores all write/erase cycles of the NVM via
4121 * the flash control registers. The shadow-ram copy of the NVM will
4122 * still be updated, however any updates to this copy will not stick
4123 * across driver reloads.
4124 **/
4125void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
4126{
4127 struct e1000_nvm_info *nvm = &hw->nvm;
4128 union ich8_flash_protected_range pr0;
4129 union ich8_hws_flash_status hsfsts;
4130 u32 gfpreg;
4131
4132 nvm->ops.acquire(hw);
4133
4134 gfpreg = er32flash(ICH_FLASH_GFPREG);
4135
4136 /* Write-protect GbE Sector of NVM */
4137 pr0.regval = er32flash(ICH_FLASH_PR0);
4138 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
4139 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
4140 pr0.range.wpe = true;
4141 ew32flash(ICH_FLASH_PR0, pr0.regval);
4142
4143 /* Lock down a subset of GbE Flash Control Registers, e.g.
4144 * PR0 to prevent the write-protection from being lifted.
4145 * Once FLOCKDN is set, the registers protected by it cannot
4146 * be written until FLOCKDN is cleared by a hardware reset.
4147 */
4148 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4149 hsfsts.hsf_status.flockdn = true;
4150 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
4151
4152 nvm->ops.release(hw);
4153}
4154
4155/**
4156 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
4157 * @hw: pointer to the HW structure
4158 * @offset: The offset (in bytes) of the byte/word to read.
4159 * @size: Size of data to read, 1=byte 2=word
4160 * @data: The byte(s) to write to the NVM.
4161 *
4162 * Writes one/two bytes to the NVM using the flash access registers.
4163 **/
4164static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
4165 u8 size, u16 data)
4166{
4167 union ich8_hws_flash_status hsfsts;
4168 union ich8_hws_flash_ctrl hsflctl;
4169 u32 flash_linear_addr;
4170 u32 flash_data = 0;
4171 s32 ret_val;
4172 u8 count = 0;
4173
4174 if (hw->mac.type >= e1000_pch_spt) {
4175 if (size != 4 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4176 return -E1000_ERR_NVM;
4177 } else {
4178 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
4179 return -E1000_ERR_NVM;
4180 }
4181
4182 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4183 hw->nvm.flash_base_addr);
4184
4185 do {
4186 udelay(1);
4187 /* Steps */
4188 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4189 if (ret_val)
4190 break;
4191 /* In SPT, This register is in Lan memory space, not
4192 * flash. Therefore, only 32 bit access is supported
4193 */
4194 if (hw->mac.type >= e1000_pch_spt)
4195 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS) >> 16;
4196 else
4197 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4198
4199 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
4200 hsflctl.hsf_ctrl.fldbcount = size - 1;
4201 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4202 /* In SPT, This register is in Lan memory space,
4203 * not flash. Therefore, only 32 bit access is
4204 * supported
4205 */
4206 if (hw->mac.type >= e1000_pch_spt)
4207 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4208 else
4209 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4210
4211 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4212
4213 if (size == 1)
4214 flash_data = (u32)data & 0x00FF;
4215 else
4216 flash_data = (u32)data;
4217
4218 ew32flash(ICH_FLASH_FDATA0, flash_data);
4219
4220 /* check if FCERR is set to 1 , if set to 1, clear it
4221 * and try the whole sequence a few more times else done
4222 */
4223 ret_val =
4224 e1000_flash_cycle_ich8lan(hw,
4225 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4226 if (!ret_val)
4227 break;
4228
4229 /* If we're here, then things are most likely
4230 * completely hosed, but if the error condition
4231 * is detected, it won't hurt to give it another
4232 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4233 */
4234 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4235 if (hsfsts.hsf_status.flcerr)
4236 /* Repeat for some time before giving up. */
4237 continue;
4238 if (!hsfsts.hsf_status.flcdone) {
4239 e_dbg("Timeout error - flash cycle did not complete.\n");
4240 break;
4241 }
4242 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4243
4244 return ret_val;
4245}
4246
4247/**
4248* e1000_write_flash_data32_ich8lan - Writes 4 bytes to the NVM
4249* @hw: pointer to the HW structure
4250* @offset: The offset (in bytes) of the dwords to read.
4251* @data: The 4 bytes to write to the NVM.
4252*
4253* Writes one/two/four bytes to the NVM using the flash access registers.
4254**/
4255static s32 e1000_write_flash_data32_ich8lan(struct e1000_hw *hw, u32 offset,
4256 u32 data)
4257{
4258 union ich8_hws_flash_status hsfsts;
4259 union ich8_hws_flash_ctrl hsflctl;
4260 u32 flash_linear_addr;
4261 s32 ret_val;
4262 u8 count = 0;
4263
4264 if (hw->mac.type >= e1000_pch_spt) {
4265 if (offset > ICH_FLASH_LINEAR_ADDR_MASK)
4266 return -E1000_ERR_NVM;
4267 }
4268 flash_linear_addr = ((ICH_FLASH_LINEAR_ADDR_MASK & offset) +
4269 hw->nvm.flash_base_addr);
4270 do {
4271 udelay(1);
4272 /* Steps */
4273 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4274 if (ret_val)
4275 break;
4276
4277 /* In SPT, This register is in Lan memory space, not
4278 * flash. Therefore, only 32 bit access is supported
4279 */
4280 if (hw->mac.type >= e1000_pch_spt)
4281 hsflctl.regval = er32flash(ICH_FLASH_HSFSTS)
4282 >> 16;
4283 else
4284 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4285
4286 hsflctl.hsf_ctrl.fldbcount = sizeof(u32) - 1;
4287 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
4288
4289 /* In SPT, This register is in Lan memory space,
4290 * not flash. Therefore, only 32 bit access is
4291 * supported
4292 */
4293 if (hw->mac.type >= e1000_pch_spt)
4294 ew32flash(ICH_FLASH_HSFSTS, hsflctl.regval << 16);
4295 else
4296 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4297
4298 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4299
4300 ew32flash(ICH_FLASH_FDATA0, data);
4301
4302 /* check if FCERR is set to 1 , if set to 1, clear it
4303 * and try the whole sequence a few more times else done
4304 */
4305 ret_val =
4306 e1000_flash_cycle_ich8lan(hw,
4307 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
4308
4309 if (!ret_val)
4310 break;
4311
4312 /* If we're here, then things are most likely
4313 * completely hosed, but if the error condition
4314 * is detected, it won't hurt to give it another
4315 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
4316 */
4317 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4318
4319 if (hsfsts.hsf_status.flcerr)
4320 /* Repeat for some time before giving up. */
4321 continue;
4322 if (!hsfsts.hsf_status.flcdone) {
4323 e_dbg("Timeout error - flash cycle did not complete.\n");
4324 break;
4325 }
4326 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
4327
4328 return ret_val;
4329}
4330
4331/**
4332 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
4333 * @hw: pointer to the HW structure
4334 * @offset: The index of the byte to read.
4335 * @data: The byte to write to the NVM.
4336 *
4337 * Writes a single byte to the NVM using the flash access registers.
4338 **/
4339static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
4340 u8 data)
4341{
4342 u16 word = (u16)data;
4343
4344 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
4345}
4346
4347/**
4348* e1000_retry_write_flash_dword_ich8lan - Writes a dword to NVM
4349* @hw: pointer to the HW structure
4350* @offset: The offset of the word to write.
4351* @dword: The dword to write to the NVM.
4352*
4353* Writes a single dword to the NVM using the flash access registers.
4354* Goes through a retry algorithm before giving up.
4355**/
4356static s32 e1000_retry_write_flash_dword_ich8lan(struct e1000_hw *hw,
4357 u32 offset, u32 dword)
4358{
4359 s32 ret_val;
4360 u16 program_retries;
4361
4362 /* Must convert word offset into bytes. */
4363 offset <<= 1;
4364 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4365
4366 if (!ret_val)
4367 return ret_val;
4368 for (program_retries = 0; program_retries < 100; program_retries++) {
4369 e_dbg("Retrying Byte %8.8X at offset %u\n", dword, offset);
4370 usleep_range(100, 200);
4371 ret_val = e1000_write_flash_data32_ich8lan(hw, offset, dword);
4372 if (!ret_val)
4373 break;
4374 }
4375 if (program_retries == 100)
4376 return -E1000_ERR_NVM;
4377
4378 return 0;
4379}
4380
4381/**
4382 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
4383 * @hw: pointer to the HW structure
4384 * @offset: The offset of the byte to write.
4385 * @byte: The byte to write to the NVM.
4386 *
4387 * Writes a single byte to the NVM using the flash access registers.
4388 * Goes through a retry algorithm before giving up.
4389 **/
4390static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
4391 u32 offset, u8 byte)
4392{
4393 s32 ret_val;
4394 u16 program_retries;
4395
4396 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4397 if (!ret_val)
4398 return ret_val;
4399
4400 for (program_retries = 0; program_retries < 100; program_retries++) {
4401 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
4402 usleep_range(100, 200);
4403 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
4404 if (!ret_val)
4405 break;
4406 }
4407 if (program_retries == 100)
4408 return -E1000_ERR_NVM;
4409
4410 return 0;
4411}
4412
4413/**
4414 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
4415 * @hw: pointer to the HW structure
4416 * @bank: 0 for first bank, 1 for second bank, etc.
4417 *
4418 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
4419 * bank N is 4096 * N + flash_reg_addr.
4420 **/
4421static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
4422{
4423 struct e1000_nvm_info *nvm = &hw->nvm;
4424 union ich8_hws_flash_status hsfsts;
4425 union ich8_hws_flash_ctrl hsflctl;
4426 u32 flash_linear_addr;
4427 /* bank size is in 16bit words - adjust to bytes */
4428 u32 flash_bank_size = nvm->flash_bank_size * 2;
4429 s32 ret_val;
4430 s32 count = 0;
4431 s32 j, iteration, sector_size;
4432
4433 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4434
4435 /* Determine HW Sector size: Read BERASE bits of hw flash status
4436 * register
4437 * 00: The Hw sector is 256 bytes, hence we need to erase 16
4438 * consecutive sectors. The start index for the nth Hw sector
4439 * can be calculated as = bank * 4096 + n * 256
4440 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
4441 * The start index for the nth Hw sector can be calculated
4442 * as = bank * 4096
4443 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
4444 * (ich9 only, otherwise error condition)
4445 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
4446 */
4447 switch (hsfsts.hsf_status.berasesz) {
4448 case 0:
4449 /* Hw sector size 256 */
4450 sector_size = ICH_FLASH_SEG_SIZE_256;
4451 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
4452 break;
4453 case 1:
4454 sector_size = ICH_FLASH_SEG_SIZE_4K;
4455 iteration = 1;
4456 break;
4457 case 2:
4458 sector_size = ICH_FLASH_SEG_SIZE_8K;
4459 iteration = 1;
4460 break;
4461 case 3:
4462 sector_size = ICH_FLASH_SEG_SIZE_64K;
4463 iteration = 1;
4464 break;
4465 default:
4466 return -E1000_ERR_NVM;
4467 }
4468
4469 /* Start with the base address, then add the sector offset. */
4470 flash_linear_addr = hw->nvm.flash_base_addr;
4471 flash_linear_addr += (bank) ? flash_bank_size : 0;
4472
4473 for (j = 0; j < iteration; j++) {
4474 do {
4475 u32 timeout = ICH_FLASH_ERASE_COMMAND_TIMEOUT;
4476
4477 /* Steps */
4478 ret_val = e1000_flash_cycle_init_ich8lan(hw);
4479 if (ret_val)
4480 return ret_val;
4481
4482 /* Write a value 11 (block Erase) in Flash
4483 * Cycle field in hw flash control
4484 */
4485 if (hw->mac.type >= e1000_pch_spt)
4486 hsflctl.regval =
4487 er32flash(ICH_FLASH_HSFSTS) >> 16;
4488 else
4489 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
4490
4491 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
4492 if (hw->mac.type >= e1000_pch_spt)
4493 ew32flash(ICH_FLASH_HSFSTS,
4494 hsflctl.regval << 16);
4495 else
4496 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
4497
4498 /* Write the last 24 bits of an index within the
4499 * block into Flash Linear address field in Flash
4500 * Address.
4501 */
4502 flash_linear_addr += (j * sector_size);
4503 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
4504
4505 ret_val = e1000_flash_cycle_ich8lan(hw, timeout);
4506 if (!ret_val)
4507 break;
4508
4509 /* Check if FCERR is set to 1. If 1,
4510 * clear it and try the whole sequence
4511 * a few more times else Done
4512 */
4513 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
4514 if (hsfsts.hsf_status.flcerr)
4515 /* repeat for some time before giving up */
4516 continue;
4517 else if (!hsfsts.hsf_status.flcdone)
4518 return ret_val;
4519 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
4520 }
4521
4522 return 0;
4523}
4524
4525/**
4526 * e1000_valid_led_default_ich8lan - Set the default LED settings
4527 * @hw: pointer to the HW structure
4528 * @data: Pointer to the LED settings
4529 *
4530 * Reads the LED default settings from the NVM to data. If the NVM LED
4531 * settings is all 0's or F's, set the LED default to a valid LED default
4532 * setting.
4533 **/
4534static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
4535{
4536 s32 ret_val;
4537
4538 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
4539 if (ret_val) {
4540 e_dbg("NVM Read Error\n");
4541 return ret_val;
4542 }
4543
4544 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
4545 *data = ID_LED_DEFAULT_ICH8LAN;
4546
4547 return 0;
4548}
4549
4550/**
4551 * e1000_id_led_init_pchlan - store LED configurations
4552 * @hw: pointer to the HW structure
4553 *
4554 * PCH does not control LEDs via the LEDCTL register, rather it uses
4555 * the PHY LED configuration register.
4556 *
4557 * PCH also does not have an "always on" or "always off" mode which
4558 * complicates the ID feature. Instead of using the "on" mode to indicate
4559 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()),
4560 * use "link_up" mode. The LEDs will still ID on request if there is no
4561 * link based on logic in e1000_led_[on|off]_pchlan().
4562 **/
4563static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
4564{
4565 struct e1000_mac_info *mac = &hw->mac;
4566 s32 ret_val;
4567 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
4568 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
4569 u16 data, i, temp, shift;
4570
4571 /* Get default ID LED modes */
4572 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
4573 if (ret_val)
4574 return ret_val;
4575
4576 mac->ledctl_default = er32(LEDCTL);
4577 mac->ledctl_mode1 = mac->ledctl_default;
4578 mac->ledctl_mode2 = mac->ledctl_default;
4579
4580 for (i = 0; i < 4; i++) {
4581 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
4582 shift = (i * 5);
4583 switch (temp) {
4584 case ID_LED_ON1_DEF2:
4585 case ID_LED_ON1_ON2:
4586 case ID_LED_ON1_OFF2:
4587 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4588 mac->ledctl_mode1 |= (ledctl_on << shift);
4589 break;
4590 case ID_LED_OFF1_DEF2:
4591 case ID_LED_OFF1_ON2:
4592 case ID_LED_OFF1_OFF2:
4593 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
4594 mac->ledctl_mode1 |= (ledctl_off << shift);
4595 break;
4596 default:
4597 /* Do nothing */
4598 break;
4599 }
4600 switch (temp) {
4601 case ID_LED_DEF1_ON2:
4602 case ID_LED_ON1_ON2:
4603 case ID_LED_OFF1_ON2:
4604 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4605 mac->ledctl_mode2 |= (ledctl_on << shift);
4606 break;
4607 case ID_LED_DEF1_OFF2:
4608 case ID_LED_ON1_OFF2:
4609 case ID_LED_OFF1_OFF2:
4610 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
4611 mac->ledctl_mode2 |= (ledctl_off << shift);
4612 break;
4613 default:
4614 /* Do nothing */
4615 break;
4616 }
4617 }
4618
4619 return 0;
4620}
4621
4622/**
4623 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
4624 * @hw: pointer to the HW structure
4625 *
4626 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
4627 * register, so the the bus width is hard coded.
4628 **/
4629static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
4630{
4631 struct e1000_bus_info *bus = &hw->bus;
4632 s32 ret_val;
4633
4634 ret_val = e1000e_get_bus_info_pcie(hw);
4635
4636 /* ICH devices are "PCI Express"-ish. They have
4637 * a configuration space, but do not contain
4638 * PCI Express Capability registers, so bus width
4639 * must be hardcoded.
4640 */
4641 if (bus->width == e1000_bus_width_unknown)
4642 bus->width = e1000_bus_width_pcie_x1;
4643
4644 return ret_val;
4645}
4646
4647/**
4648 * e1000_reset_hw_ich8lan - Reset the hardware
4649 * @hw: pointer to the HW structure
4650 *
4651 * Does a full reset of the hardware which includes a reset of the PHY and
4652 * MAC.
4653 **/
4654static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
4655{
4656 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
4657 u16 kum_cfg;
4658 u32 ctrl, reg;
4659 s32 ret_val;
4660
4661 /* Prevent the PCI-E bus from sticking if there is no TLP connection
4662 * on the last TLP read/write transaction when MAC is reset.
4663 */
4664 ret_val = e1000e_disable_pcie_master(hw);
4665 if (ret_val)
4666 e_dbg("PCI-E Master disable polling has failed.\n");
4667
4668 e_dbg("Masking off all interrupts\n");
4669 ew32(IMC, 0xffffffff);
4670
4671 /* Disable the Transmit and Receive units. Then delay to allow
4672 * any pending transactions to complete before we hit the MAC
4673 * with the global reset.
4674 */
4675 ew32(RCTL, 0);
4676 ew32(TCTL, E1000_TCTL_PSP);
4677 e1e_flush();
4678
4679 usleep_range(10000, 11000);
4680
4681 /* Workaround for ICH8 bit corruption issue in FIFO memory */
4682 if (hw->mac.type == e1000_ich8lan) {
4683 /* Set Tx and Rx buffer allocation to 8k apiece. */
4684 ew32(PBA, E1000_PBA_8K);
4685 /* Set Packet Buffer Size to 16k. */
4686 ew32(PBS, E1000_PBS_16K);
4687 }
4688
4689 if (hw->mac.type == e1000_pchlan) {
4690 /* Save the NVM K1 bit setting */
4691 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg);
4692 if (ret_val)
4693 return ret_val;
4694
4695 if (kum_cfg & E1000_NVM_K1_ENABLE)
4696 dev_spec->nvm_k1_enabled = true;
4697 else
4698 dev_spec->nvm_k1_enabled = false;
4699 }
4700
4701 ctrl = er32(CTRL);
4702
4703 if (!hw->phy.ops.check_reset_block(hw)) {
4704 /* Full-chip reset requires MAC and PHY reset at the same
4705 * time to make sure the interface between MAC and the
4706 * external PHY is reset.
4707 */
4708 ctrl |= E1000_CTRL_PHY_RST;
4709
4710 /* Gate automatic PHY configuration by hardware on
4711 * non-managed 82579
4712 */
4713 if ((hw->mac.type == e1000_pch2lan) &&
4714 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
4715 e1000_gate_hw_phy_config_ich8lan(hw, true);
4716 }
4717 ret_val = e1000_acquire_swflag_ich8lan(hw);
4718 e_dbg("Issuing a global reset to ich8lan\n");
4719 ew32(CTRL, (ctrl | E1000_CTRL_RST));
4720 /* cannot issue a flush here because it hangs the hardware */
4721 msleep(20);
4722
4723 /* Set Phy Config Counter to 50msec */
4724 if (hw->mac.type == e1000_pch2lan) {
4725 reg = er32(FEXTNVM3);
4726 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK;
4727 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC;
4728 ew32(FEXTNVM3, reg);
4729 }
4730
4731 if (!ret_val)
4732 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state);
4733
4734 if (ctrl & E1000_CTRL_PHY_RST) {
4735 ret_val = hw->phy.ops.get_cfg_done(hw);
4736 if (ret_val)
4737 return ret_val;
4738
4739 ret_val = e1000_post_phy_reset_ich8lan(hw);
4740 if (ret_val)
4741 return ret_val;
4742 }
4743
4744 /* For PCH, this write will make sure that any noise
4745 * will be detected as a CRC error and be dropped rather than show up
4746 * as a bad packet to the DMA engine.
4747 */
4748 if (hw->mac.type == e1000_pchlan)
4749 ew32(CRC_OFFSET, 0x65656565);
4750
4751 ew32(IMC, 0xffffffff);
4752 er32(ICR);
4753
4754 reg = er32(KABGTXD);
4755 reg |= E1000_KABGTXD_BGSQLBIAS;
4756 ew32(KABGTXD, reg);
4757
4758 return 0;
4759}
4760
4761/**
4762 * e1000_init_hw_ich8lan - Initialize the hardware
4763 * @hw: pointer to the HW structure
4764 *
4765 * Prepares the hardware for transmit and receive by doing the following:
4766 * - initialize hardware bits
4767 * - initialize LED identification
4768 * - setup receive address registers
4769 * - setup flow control
4770 * - setup transmit descriptors
4771 * - clear statistics
4772 **/
4773static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
4774{
4775 struct e1000_mac_info *mac = &hw->mac;
4776 u32 ctrl_ext, txdctl, snoop;
4777 s32 ret_val;
4778 u16 i;
4779
4780 e1000_initialize_hw_bits_ich8lan(hw);
4781
4782 /* Initialize identification LED */
4783 ret_val = mac->ops.id_led_init(hw);
4784 /* An error is not fatal and we should not stop init due to this */
4785 if (ret_val)
4786 e_dbg("Error initializing identification LED\n");
4787
4788 /* Setup the receive address. */
4789 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
4790
4791 /* Zero out the Multicast HASH table */
4792 e_dbg("Zeroing the MTA\n");
4793 for (i = 0; i < mac->mta_reg_count; i++)
4794 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
4795
4796 /* The 82578 Rx buffer will stall if wakeup is enabled in host and
4797 * the ME. Disable wakeup by clearing the host wakeup bit.
4798 * Reset the phy after disabling host wakeup to reset the Rx buffer.
4799 */
4800 if (hw->phy.type == e1000_phy_82578) {
4801 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
4802 i &= ~BM_WUC_HOST_WU_BIT;
4803 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
4804 ret_val = e1000_phy_hw_reset_ich8lan(hw);
4805 if (ret_val)
4806 return ret_val;
4807 }
4808
4809 /* Setup link and flow control */
4810 ret_val = mac->ops.setup_link(hw);
4811
4812 /* Set the transmit descriptor write-back policy for both queues */
4813 txdctl = er32(TXDCTL(0));
4814 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4815 E1000_TXDCTL_FULL_TX_DESC_WB);
4816 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4817 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4818 ew32(TXDCTL(0), txdctl);
4819 txdctl = er32(TXDCTL(1));
4820 txdctl = ((txdctl & ~E1000_TXDCTL_WTHRESH) |
4821 E1000_TXDCTL_FULL_TX_DESC_WB);
4822 txdctl = ((txdctl & ~E1000_TXDCTL_PTHRESH) |
4823 E1000_TXDCTL_MAX_TX_DESC_PREFETCH);
4824 ew32(TXDCTL(1), txdctl);
4825
4826 /* ICH8 has opposite polarity of no_snoop bits.
4827 * By default, we should use snoop behavior.
4828 */
4829 if (mac->type == e1000_ich8lan)
4830 snoop = PCIE_ICH8_SNOOP_ALL;
4831 else
4832 snoop = (u32)~(PCIE_NO_SNOOP_ALL);
4833 e1000e_set_pcie_no_snoop(hw, snoop);
4834
4835 ctrl_ext = er32(CTRL_EXT);
4836 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
4837 ew32(CTRL_EXT, ctrl_ext);
4838
4839 /* Clear all of the statistics registers (clear on read). It is
4840 * important that we do this after we have tried to establish link
4841 * because the symbol error count will increment wildly if there
4842 * is no link.
4843 */
4844 e1000_clear_hw_cntrs_ich8lan(hw);
4845
4846 return ret_val;
4847}
4848
4849/**
4850 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
4851 * @hw: pointer to the HW structure
4852 *
4853 * Sets/Clears required hardware bits necessary for correctly setting up the
4854 * hardware for transmit and receive.
4855 **/
4856static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
4857{
4858 u32 reg;
4859
4860 /* Extended Device Control */
4861 reg = er32(CTRL_EXT);
4862 reg |= BIT(22);
4863 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
4864 if (hw->mac.type >= e1000_pchlan)
4865 reg |= E1000_CTRL_EXT_PHYPDEN;
4866 ew32(CTRL_EXT, reg);
4867
4868 /* Transmit Descriptor Control 0 */
4869 reg = er32(TXDCTL(0));
4870 reg |= BIT(22);
4871 ew32(TXDCTL(0), reg);
4872
4873 /* Transmit Descriptor Control 1 */
4874 reg = er32(TXDCTL(1));
4875 reg |= BIT(22);
4876 ew32(TXDCTL(1), reg);
4877
4878 /* Transmit Arbitration Control 0 */
4879 reg = er32(TARC(0));
4880 if (hw->mac.type == e1000_ich8lan)
4881 reg |= BIT(28) | BIT(29);
4882 reg |= BIT(23) | BIT(24) | BIT(26) | BIT(27);
4883 ew32(TARC(0), reg);
4884
4885 /* Transmit Arbitration Control 1 */
4886 reg = er32(TARC(1));
4887 if (er32(TCTL) & E1000_TCTL_MULR)
4888 reg &= ~BIT(28);
4889 else
4890 reg |= BIT(28);
4891 reg |= BIT(24) | BIT(26) | BIT(30);
4892 ew32(TARC(1), reg);
4893
4894 /* Device Status */
4895 if (hw->mac.type == e1000_ich8lan) {
4896 reg = er32(STATUS);
4897 reg &= ~BIT(31);
4898 ew32(STATUS, reg);
4899 }
4900
4901 /* work-around descriptor data corruption issue during nfs v2 udp
4902 * traffic, just disable the nfs filtering capability
4903 */
4904 reg = er32(RFCTL);
4905 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
4906
4907 /* Disable IPv6 extension header parsing because some malformed
4908 * IPv6 headers can hang the Rx.
4909 */
4910 if (hw->mac.type == e1000_ich8lan)
4911 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
4912 ew32(RFCTL, reg);
4913
4914 /* Enable ECC on Lynxpoint */
4915 if (hw->mac.type >= e1000_pch_lpt) {
4916 reg = er32(PBECCSTS);
4917 reg |= E1000_PBECCSTS_ECC_ENABLE;
4918 ew32(PBECCSTS, reg);
4919
4920 reg = er32(CTRL);
4921 reg |= E1000_CTRL_MEHE;
4922 ew32(CTRL, reg);
4923 }
4924}
4925
4926/**
4927 * e1000_setup_link_ich8lan - Setup flow control and link settings
4928 * @hw: pointer to the HW structure
4929 *
4930 * Determines which flow control settings to use, then configures flow
4931 * control. Calls the appropriate media-specific link configuration
4932 * function. Assuming the adapter has a valid link partner, a valid link
4933 * should be established. Assumes the hardware has previously been reset
4934 * and the transmitter and receiver are not enabled.
4935 **/
4936static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
4937{
4938 s32 ret_val;
4939
4940 if (hw->phy.ops.check_reset_block(hw))
4941 return 0;
4942
4943 /* ICH parts do not have a word in the NVM to determine
4944 * the default flow control setting, so we explicitly
4945 * set it to full.
4946 */
4947 if (hw->fc.requested_mode == e1000_fc_default) {
4948 /* Workaround h/w hang when Tx flow control enabled */
4949 if (hw->mac.type == e1000_pchlan)
4950 hw->fc.requested_mode = e1000_fc_rx_pause;
4951 else
4952 hw->fc.requested_mode = e1000_fc_full;
4953 }
4954
4955 /* Save off the requested flow control mode for use later. Depending
4956 * on the link partner's capabilities, we may or may not use this mode.
4957 */
4958 hw->fc.current_mode = hw->fc.requested_mode;
4959
4960 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
4961
4962 /* Continue to configure the copper link. */
4963 ret_val = hw->mac.ops.setup_physical_interface(hw);
4964 if (ret_val)
4965 return ret_val;
4966
4967 ew32(FCTTV, hw->fc.pause_time);
4968 if ((hw->phy.type == e1000_phy_82578) ||
4969 (hw->phy.type == e1000_phy_82579) ||
4970 (hw->phy.type == e1000_phy_i217) ||
4971 (hw->phy.type == e1000_phy_82577)) {
4972 ew32(FCRTV_PCH, hw->fc.refresh_time);
4973
4974 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
4975 hw->fc.pause_time);
4976 if (ret_val)
4977 return ret_val;
4978 }
4979
4980 return e1000e_set_fc_watermarks(hw);
4981}
4982
4983/**
4984 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
4985 * @hw: pointer to the HW structure
4986 *
4987 * Configures the kumeran interface to the PHY to wait the appropriate time
4988 * when polling the PHY, then call the generic setup_copper_link to finish
4989 * configuring the copper link.
4990 **/
4991static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
4992{
4993 u32 ctrl;
4994 s32 ret_val;
4995 u16 reg_data;
4996
4997 ctrl = er32(CTRL);
4998 ctrl |= E1000_CTRL_SLU;
4999 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5000 ew32(CTRL, ctrl);
5001
5002 /* Set the mac to wait the maximum time between each iteration
5003 * and increase the max iterations when polling the phy;
5004 * this fixes erroneous timeouts at 10Mbps.
5005 */
5006 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
5007 if (ret_val)
5008 return ret_val;
5009 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5010 ®_data);
5011 if (ret_val)
5012 return ret_val;
5013 reg_data |= 0x3F;
5014 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
5015 reg_data);
5016 if (ret_val)
5017 return ret_val;
5018
5019 switch (hw->phy.type) {
5020 case e1000_phy_igp_3:
5021 ret_val = e1000e_copper_link_setup_igp(hw);
5022 if (ret_val)
5023 return ret_val;
5024 break;
5025 case e1000_phy_bm:
5026 case e1000_phy_82578:
5027 ret_val = e1000e_copper_link_setup_m88(hw);
5028 if (ret_val)
5029 return ret_val;
5030 break;
5031 case e1000_phy_82577:
5032 case e1000_phy_82579:
5033 ret_val = e1000_copper_link_setup_82577(hw);
5034 if (ret_val)
5035 return ret_val;
5036 break;
5037 case e1000_phy_ife:
5038 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
5039 if (ret_val)
5040 return ret_val;
5041
5042 reg_data &= ~IFE_PMC_AUTO_MDIX;
5043
5044 switch (hw->phy.mdix) {
5045 case 1:
5046 reg_data &= ~IFE_PMC_FORCE_MDIX;
5047 break;
5048 case 2:
5049 reg_data |= IFE_PMC_FORCE_MDIX;
5050 break;
5051 case 0:
5052 default:
5053 reg_data |= IFE_PMC_AUTO_MDIX;
5054 break;
5055 }
5056 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
5057 if (ret_val)
5058 return ret_val;
5059 break;
5060 default:
5061 break;
5062 }
5063
5064 return e1000e_setup_copper_link(hw);
5065}
5066
5067/**
5068 * e1000_setup_copper_link_pch_lpt - Configure MAC/PHY interface
5069 * @hw: pointer to the HW structure
5070 *
5071 * Calls the PHY specific link setup function and then calls the
5072 * generic setup_copper_link to finish configuring the link for
5073 * Lynxpoint PCH devices
5074 **/
5075static s32 e1000_setup_copper_link_pch_lpt(struct e1000_hw *hw)
5076{
5077 u32 ctrl;
5078 s32 ret_val;
5079
5080 ctrl = er32(CTRL);
5081 ctrl |= E1000_CTRL_SLU;
5082 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
5083 ew32(CTRL, ctrl);
5084
5085 ret_val = e1000_copper_link_setup_82577(hw);
5086 if (ret_val)
5087 return ret_val;
5088
5089 return e1000e_setup_copper_link(hw);
5090}
5091
5092/**
5093 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
5094 * @hw: pointer to the HW structure
5095 * @speed: pointer to store current link speed
5096 * @duplex: pointer to store the current link duplex
5097 *
5098 * Calls the generic get_speed_and_duplex to retrieve the current link
5099 * information and then calls the Kumeran lock loss workaround for links at
5100 * gigabit speeds.
5101 **/
5102static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
5103 u16 *duplex)
5104{
5105 s32 ret_val;
5106
5107 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
5108 if (ret_val)
5109 return ret_val;
5110
5111 if ((hw->mac.type == e1000_ich8lan) &&
5112 (hw->phy.type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
5113 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
5114 }
5115
5116 return ret_val;
5117}
5118
5119/**
5120 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
5121 * @hw: pointer to the HW structure
5122 *
5123 * Work-around for 82566 Kumeran PCS lock loss:
5124 * On link status change (i.e. PCI reset, speed change) and link is up and
5125 * speed is gigabit-
5126 * 0) if workaround is optionally disabled do nothing
5127 * 1) wait 1ms for Kumeran link to come up
5128 * 2) check Kumeran Diagnostic register PCS lock loss bit
5129 * 3) if not set the link is locked (all is good), otherwise...
5130 * 4) reset the PHY
5131 * 5) repeat up to 10 times
5132 * Note: this is only called for IGP3 copper when speed is 1gb.
5133 **/
5134static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
5135{
5136 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5137 u32 phy_ctrl;
5138 s32 ret_val;
5139 u16 i, data;
5140 bool link;
5141
5142 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
5143 return 0;
5144
5145 /* Make sure link is up before proceeding. If not just return.
5146 * Attempting this while link is negotiating fouled up link
5147 * stability
5148 */
5149 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
5150 if (!link)
5151 return 0;
5152
5153 for (i = 0; i < 10; i++) {
5154 /* read once to clear */
5155 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5156 if (ret_val)
5157 return ret_val;
5158 /* and again to get new status */
5159 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
5160 if (ret_val)
5161 return ret_val;
5162
5163 /* check for PCS lock */
5164 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
5165 return 0;
5166
5167 /* Issue PHY reset */
5168 e1000_phy_hw_reset(hw);
5169 mdelay(5);
5170 }
5171 /* Disable GigE link negotiation */
5172 phy_ctrl = er32(PHY_CTRL);
5173 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
5174 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5175 ew32(PHY_CTRL, phy_ctrl);
5176
5177 /* Call gig speed drop workaround on Gig disable before accessing
5178 * any PHY registers
5179 */
5180 e1000e_gig_downshift_workaround_ich8lan(hw);
5181
5182 /* unable to acquire PCS lock */
5183 return -E1000_ERR_PHY;
5184}
5185
5186/**
5187 * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
5188 * @hw: pointer to the HW structure
5189 * @state: boolean value used to set the current Kumeran workaround state
5190 *
5191 * If ICH8, set the current Kumeran workaround state (enabled - true
5192 * /disabled - false).
5193 **/
5194void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
5195 bool state)
5196{
5197 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5198
5199 if (hw->mac.type != e1000_ich8lan) {
5200 e_dbg("Workaround applies to ICH8 only.\n");
5201 return;
5202 }
5203
5204 dev_spec->kmrn_lock_loss_workaround_enabled = state;
5205}
5206
5207/**
5208 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
5209 * @hw: pointer to the HW structure
5210 *
5211 * Workaround for 82566 power-down on D3 entry:
5212 * 1) disable gigabit link
5213 * 2) write VR power-down enable
5214 * 3) read it back
5215 * Continue if successful, else issue LCD reset and repeat
5216 **/
5217void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
5218{
5219 u32 reg;
5220 u16 data;
5221 u8 retry = 0;
5222
5223 if (hw->phy.type != e1000_phy_igp_3)
5224 return;
5225
5226 /* Try the workaround twice (if needed) */
5227 do {
5228 /* Disable link */
5229 reg = er32(PHY_CTRL);
5230 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
5231 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
5232 ew32(PHY_CTRL, reg);
5233
5234 /* Call gig speed drop workaround on Gig disable before
5235 * accessing any PHY registers
5236 */
5237 if (hw->mac.type == e1000_ich8lan)
5238 e1000e_gig_downshift_workaround_ich8lan(hw);
5239
5240 /* Write VR power-down enable */
5241 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5242 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5243 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
5244
5245 /* Read it back and test */
5246 e1e_rphy(hw, IGP3_VR_CTRL, &data);
5247 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
5248 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
5249 break;
5250
5251 /* Issue PHY reset and repeat at most one more time */
5252 reg = er32(CTRL);
5253 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
5254 retry++;
5255 } while (retry);
5256}
5257
5258/**
5259 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
5260 * @hw: pointer to the HW structure
5261 *
5262 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
5263 * LPLU, Gig disable, MDIC PHY reset):
5264 * 1) Set Kumeran Near-end loopback
5265 * 2) Clear Kumeran Near-end loopback
5266 * Should only be called for ICH8[m] devices with any 1G Phy.
5267 **/
5268void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
5269{
5270 s32 ret_val;
5271 u16 reg_data;
5272
5273 if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife))
5274 return;
5275
5276 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5277 ®_data);
5278 if (ret_val)
5279 return;
5280 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
5281 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
5282 reg_data);
5283 if (ret_val)
5284 return;
5285 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
5286 e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, reg_data);
5287}
5288
5289/**
5290 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
5291 * @hw: pointer to the HW structure
5292 *
5293 * During S0 to Sx transition, it is possible the link remains at gig
5294 * instead of negotiating to a lower speed. Before going to Sx, set
5295 * 'Gig Disable' to force link speed negotiation to a lower speed based on
5296 * the LPLU setting in the NVM or custom setting. For PCH and newer parts,
5297 * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also
5298 * needs to be written.
5299 * Parts that support (and are linked to a partner which support) EEE in
5300 * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power
5301 * than 10Mbps w/o EEE.
5302 **/
5303void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
5304{
5305 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
5306 u32 phy_ctrl;
5307 s32 ret_val;
5308
5309 phy_ctrl = er32(PHY_CTRL);
5310 phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE;
5311
5312 if (hw->phy.type == e1000_phy_i217) {
5313 u16 phy_reg, device_id = hw->adapter->pdev->device;
5314
5315 if ((device_id == E1000_DEV_ID_PCH_LPTLP_I218_LM) ||
5316 (device_id == E1000_DEV_ID_PCH_LPTLP_I218_V) ||
5317 (device_id == E1000_DEV_ID_PCH_I218_LM3) ||
5318 (device_id == E1000_DEV_ID_PCH_I218_V3) ||
5319 (hw->mac.type >= e1000_pch_spt)) {
5320 u32 fextnvm6 = er32(FEXTNVM6);
5321
5322 ew32(FEXTNVM6, fextnvm6 & ~E1000_FEXTNVM6_REQ_PLL_CLK);
5323 }
5324
5325 ret_val = hw->phy.ops.acquire(hw);
5326 if (ret_val)
5327 goto out;
5328
5329 if (!dev_spec->eee_disable) {
5330 u16 eee_advert;
5331
5332 ret_val =
5333 e1000_read_emi_reg_locked(hw,
5334 I217_EEE_ADVERTISEMENT,
5335 &eee_advert);
5336 if (ret_val)
5337 goto release;
5338
5339 /* Disable LPLU if both link partners support 100BaseT
5340 * EEE and 100Full is advertised on both ends of the
5341 * link, and enable Auto Enable LPI since there will
5342 * be no driver to enable LPI while in Sx.
5343 */
5344 if ((eee_advert & I82579_EEE_100_SUPPORTED) &&
5345 (dev_spec->eee_lp_ability &
5346 I82579_EEE_100_SUPPORTED) &&
5347 (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) {
5348 phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU |
5349 E1000_PHY_CTRL_NOND0A_LPLU);
5350
5351 /* Set Auto Enable LPI after link up */
5352 e1e_rphy_locked(hw,
5353 I217_LPI_GPIO_CTRL, &phy_reg);
5354 phy_reg |= I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5355 e1e_wphy_locked(hw,
5356 I217_LPI_GPIO_CTRL, phy_reg);
5357 }
5358 }
5359
5360 /* For i217 Intel Rapid Start Technology support,
5361 * when the system is going into Sx and no manageability engine
5362 * is present, the driver must configure proxy to reset only on
5363 * power good. LPI (Low Power Idle) state must also reset only
5364 * on power good, as well as the MTA (Multicast table array).
5365 * The SMBus release must also be disabled on LCD reset.
5366 */
5367 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5368 /* Enable proxy to reset only on power good. */
5369 e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg);
5370 phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE;
5371 e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg);
5372
5373 /* Set bit enable LPI (EEE) to reset only on
5374 * power good.
5375 */
5376 e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg);
5377 phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET;
5378 e1e_wphy_locked(hw, I217_SxCTRL, phy_reg);
5379
5380 /* Disable the SMB release on LCD reset. */
5381 e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5382 phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE;
5383 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5384 }
5385
5386 /* Enable MTA to reset for Intel Rapid Start Technology
5387 * Support
5388 */
5389 e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5390 phy_reg |= I217_CGFREG_ENABLE_MTA_RESET;
5391 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5392
5393release:
5394 hw->phy.ops.release(hw);
5395 }
5396out:
5397 ew32(PHY_CTRL, phy_ctrl);
5398
5399 if (hw->mac.type == e1000_ich8lan)
5400 e1000e_gig_downshift_workaround_ich8lan(hw);
5401
5402 if (hw->mac.type >= e1000_pchlan) {
5403 e1000_oem_bits_config_ich8lan(hw, false);
5404
5405 /* Reset PHY to activate OEM bits on 82577/8 */
5406 if (hw->mac.type == e1000_pchlan)
5407 e1000e_phy_hw_reset_generic(hw);
5408
5409 ret_val = hw->phy.ops.acquire(hw);
5410 if (ret_val)
5411 return;
5412 e1000_write_smbus_addr(hw);
5413 hw->phy.ops.release(hw);
5414 }
5415}
5416
5417/**
5418 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
5419 * @hw: pointer to the HW structure
5420 *
5421 * During Sx to S0 transitions on non-managed devices or managed devices
5422 * on which PHY resets are not blocked, if the PHY registers cannot be
5423 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
5424 * the PHY.
5425 * On i217, setup Intel Rapid Start Technology.
5426 **/
5427void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
5428{
5429 s32 ret_val;
5430
5431 if (hw->mac.type < e1000_pch2lan)
5432 return;
5433
5434 ret_val = e1000_init_phy_workarounds_pchlan(hw);
5435 if (ret_val) {
5436 e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val);
5437 return;
5438 }
5439
5440 /* For i217 Intel Rapid Start Technology support when the system
5441 * is transitioning from Sx and no manageability engine is present
5442 * configure SMBus to restore on reset, disable proxy, and enable
5443 * the reset on MTA (Multicast table array).
5444 */
5445 if (hw->phy.type == e1000_phy_i217) {
5446 u16 phy_reg;
5447
5448 ret_val = hw->phy.ops.acquire(hw);
5449 if (ret_val) {
5450 e_dbg("Failed to setup iRST\n");
5451 return;
5452 }
5453
5454 /* Clear Auto Enable LPI after link up */
5455 e1e_rphy_locked(hw, I217_LPI_GPIO_CTRL, &phy_reg);
5456 phy_reg &= ~I217_LPI_GPIO_CTRL_AUTO_EN_LPI;
5457 e1e_wphy_locked(hw, I217_LPI_GPIO_CTRL, phy_reg);
5458
5459 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
5460 /* Restore clear on SMB if no manageability engine
5461 * is present
5462 */
5463 ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg);
5464 if (ret_val)
5465 goto release;
5466 phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE;
5467 e1e_wphy_locked(hw, I217_MEMPWR, phy_reg);
5468
5469 /* Disable Proxy */
5470 e1e_wphy_locked(hw, I217_PROXY_CTRL, 0);
5471 }
5472 /* Enable reset on MTA */
5473 ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg);
5474 if (ret_val)
5475 goto release;
5476 phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET;
5477 e1e_wphy_locked(hw, I217_CGFREG, phy_reg);
5478release:
5479 if (ret_val)
5480 e_dbg("Error %d in resume workarounds\n", ret_val);
5481 hw->phy.ops.release(hw);
5482 }
5483}
5484
5485/**
5486 * e1000_cleanup_led_ich8lan - Restore the default LED operation
5487 * @hw: pointer to the HW structure
5488 *
5489 * Return the LED back to the default configuration.
5490 **/
5491static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
5492{
5493 if (hw->phy.type == e1000_phy_ife)
5494 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
5495
5496 ew32(LEDCTL, hw->mac.ledctl_default);
5497 return 0;
5498}
5499
5500/**
5501 * e1000_led_on_ich8lan - Turn LEDs on
5502 * @hw: pointer to the HW structure
5503 *
5504 * Turn on the LEDs.
5505 **/
5506static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
5507{
5508 if (hw->phy.type == e1000_phy_ife)
5509 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5510 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
5511
5512 ew32(LEDCTL, hw->mac.ledctl_mode2);
5513 return 0;
5514}
5515
5516/**
5517 * e1000_led_off_ich8lan - Turn LEDs off
5518 * @hw: pointer to the HW structure
5519 *
5520 * Turn off the LEDs.
5521 **/
5522static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
5523{
5524 if (hw->phy.type == e1000_phy_ife)
5525 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
5526 (IFE_PSCL_PROBE_MODE |
5527 IFE_PSCL_PROBE_LEDS_OFF));
5528
5529 ew32(LEDCTL, hw->mac.ledctl_mode1);
5530 return 0;
5531}
5532
5533/**
5534 * e1000_setup_led_pchlan - Configures SW controllable LED
5535 * @hw: pointer to the HW structure
5536 *
5537 * This prepares the SW controllable LED for use.
5538 **/
5539static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
5540{
5541 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
5542}
5543
5544/**
5545 * e1000_cleanup_led_pchlan - Restore the default LED operation
5546 * @hw: pointer to the HW structure
5547 *
5548 * Return the LED back to the default configuration.
5549 **/
5550static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
5551{
5552 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
5553}
5554
5555/**
5556 * e1000_led_on_pchlan - Turn LEDs on
5557 * @hw: pointer to the HW structure
5558 *
5559 * Turn on the LEDs.
5560 **/
5561static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
5562{
5563 u16 data = (u16)hw->mac.ledctl_mode2;
5564 u32 i, led;
5565
5566 /* If no link, then turn LED on by setting the invert bit
5567 * for each LED that's mode is "link_up" in ledctl_mode2.
5568 */
5569 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5570 for (i = 0; i < 3; i++) {
5571 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5572 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5573 E1000_LEDCTL_MODE_LINK_UP)
5574 continue;
5575 if (led & E1000_PHY_LED0_IVRT)
5576 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5577 else
5578 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5579 }
5580 }
5581
5582 return e1e_wphy(hw, HV_LED_CONFIG, data);
5583}
5584
5585/**
5586 * e1000_led_off_pchlan - Turn LEDs off
5587 * @hw: pointer to the HW structure
5588 *
5589 * Turn off the LEDs.
5590 **/
5591static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
5592{
5593 u16 data = (u16)hw->mac.ledctl_mode1;
5594 u32 i, led;
5595
5596 /* If no link, then turn LED off by clearing the invert bit
5597 * for each LED that's mode is "link_up" in ledctl_mode1.
5598 */
5599 if (!(er32(STATUS) & E1000_STATUS_LU)) {
5600 for (i = 0; i < 3; i++) {
5601 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
5602 if ((led & E1000_PHY_LED0_MODE_MASK) !=
5603 E1000_LEDCTL_MODE_LINK_UP)
5604 continue;
5605 if (led & E1000_PHY_LED0_IVRT)
5606 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
5607 else
5608 data |= (E1000_PHY_LED0_IVRT << (i * 5));
5609 }
5610 }
5611
5612 return e1e_wphy(hw, HV_LED_CONFIG, data);
5613}
5614
5615/**
5616 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
5617 * @hw: pointer to the HW structure
5618 *
5619 * Read appropriate register for the config done bit for completion status
5620 * and configure the PHY through s/w for EEPROM-less parts.
5621 *
5622 * NOTE: some silicon which is EEPROM-less will fail trying to read the
5623 * config done bit, so only an error is logged and continues. If we were
5624 * to return with error, EEPROM-less silicon would not be able to be reset
5625 * or change link.
5626 **/
5627static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
5628{
5629 s32 ret_val = 0;
5630 u32 bank = 0;
5631 u32 status;
5632
5633 e1000e_get_cfg_done_generic(hw);
5634
5635 /* Wait for indication from h/w that it has completed basic config */
5636 if (hw->mac.type >= e1000_ich10lan) {
5637 e1000_lan_init_done_ich8lan(hw);
5638 } else {
5639 ret_val = e1000e_get_auto_rd_done(hw);
5640 if (ret_val) {
5641 /* When auto config read does not complete, do not
5642 * return with an error. This can happen in situations
5643 * where there is no eeprom and prevents getting link.
5644 */
5645 e_dbg("Auto Read Done did not complete\n");
5646 ret_val = 0;
5647 }
5648 }
5649
5650 /* Clear PHY Reset Asserted bit */
5651 status = er32(STATUS);
5652 if (status & E1000_STATUS_PHYRA)
5653 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
5654 else
5655 e_dbg("PHY Reset Asserted not set - needs delay\n");
5656
5657 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
5658 if (hw->mac.type <= e1000_ich9lan) {
5659 if (!(er32(EECD) & E1000_EECD_PRES) &&
5660 (hw->phy.type == e1000_phy_igp_3)) {
5661 e1000e_phy_init_script_igp3(hw);
5662 }
5663 } else {
5664 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
5665 /* Maybe we should do a basic PHY config */
5666 e_dbg("EEPROM not present\n");
5667 ret_val = -E1000_ERR_CONFIG;
5668 }
5669 }
5670
5671 return ret_val;
5672}
5673
5674/**
5675 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
5676 * @hw: pointer to the HW structure
5677 *
5678 * In the case of a PHY power down to save power, or to turn off link during a
5679 * driver unload, or wake on lan is not enabled, remove the link.
5680 **/
5681static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
5682{
5683 /* If the management interface is not enabled, then power down */
5684 if (!(hw->mac.ops.check_mng_mode(hw) ||
5685 hw->phy.ops.check_reset_block(hw)))
5686 e1000_power_down_phy_copper(hw);
5687}
5688
5689/**
5690 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
5691 * @hw: pointer to the HW structure
5692 *
5693 * Clears hardware counters specific to the silicon family and calls
5694 * clear_hw_cntrs_generic to clear all general purpose counters.
5695 **/
5696static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
5697{
5698 u16 phy_data;
5699 s32 ret_val;
5700
5701 e1000e_clear_hw_cntrs_base(hw);
5702
5703 er32(ALGNERRC);
5704 er32(RXERRC);
5705 er32(TNCRS);
5706 er32(CEXTERR);
5707 er32(TSCTC);
5708 er32(TSCTFC);
5709
5710 er32(MGTPRC);
5711 er32(MGTPDC);
5712 er32(MGTPTC);
5713
5714 er32(IAC);
5715 er32(ICRXOC);
5716
5717 /* Clear PHY statistics registers */
5718 if ((hw->phy.type == e1000_phy_82578) ||
5719 (hw->phy.type == e1000_phy_82579) ||
5720 (hw->phy.type == e1000_phy_i217) ||
5721 (hw->phy.type == e1000_phy_82577)) {
5722 ret_val = hw->phy.ops.acquire(hw);
5723 if (ret_val)
5724 return;
5725 ret_val = hw->phy.ops.set_page(hw,
5726 HV_STATS_PAGE << IGP_PAGE_SHIFT);
5727 if (ret_val)
5728 goto release;
5729 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
5730 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
5731 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
5732 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
5733 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
5734 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
5735 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
5736 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
5737 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
5738 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
5739 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
5740 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
5741 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
5742 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
5743release:
5744 hw->phy.ops.release(hw);
5745 }
5746}
5747
5748static const struct e1000_mac_operations ich8_mac_ops = {
5749 /* check_mng_mode dependent on mac type */
5750 .check_for_link = e1000_check_for_copper_link_ich8lan,
5751 /* cleanup_led dependent on mac type */
5752 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
5753 .get_bus_info = e1000_get_bus_info_ich8lan,
5754 .set_lan_id = e1000_set_lan_id_single_port,
5755 .get_link_up_info = e1000_get_link_up_info_ich8lan,
5756 /* led_on dependent on mac type */
5757 /* led_off dependent on mac type */
5758 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
5759 .reset_hw = e1000_reset_hw_ich8lan,
5760 .init_hw = e1000_init_hw_ich8lan,
5761 .setup_link = e1000_setup_link_ich8lan,
5762 .setup_physical_interface = e1000_setup_copper_link_ich8lan,
5763 /* id_led_init dependent on mac type */
5764 .config_collision_dist = e1000e_config_collision_dist_generic,
5765 .rar_set = e1000e_rar_set_generic,
5766 .rar_get_count = e1000e_rar_get_count_generic,
5767};
5768
5769static const struct e1000_phy_operations ich8_phy_ops = {
5770 .acquire = e1000_acquire_swflag_ich8lan,
5771 .check_reset_block = e1000_check_reset_block_ich8lan,
5772 .commit = NULL,
5773 .get_cfg_done = e1000_get_cfg_done_ich8lan,
5774 .get_cable_length = e1000e_get_cable_length_igp_2,
5775 .read_reg = e1000e_read_phy_reg_igp,
5776 .release = e1000_release_swflag_ich8lan,
5777 .reset = e1000_phy_hw_reset_ich8lan,
5778 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
5779 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
5780 .write_reg = e1000e_write_phy_reg_igp,
5781};
5782
5783static const struct e1000_nvm_operations ich8_nvm_ops = {
5784 .acquire = e1000_acquire_nvm_ich8lan,
5785 .read = e1000_read_nvm_ich8lan,
5786 .release = e1000_release_nvm_ich8lan,
5787 .reload = e1000e_reload_nvm_generic,
5788 .update = e1000_update_nvm_checksum_ich8lan,
5789 .valid_led_default = e1000_valid_led_default_ich8lan,
5790 .validate = e1000_validate_nvm_checksum_ich8lan,
5791 .write = e1000_write_nvm_ich8lan,
5792};
5793
5794static const struct e1000_nvm_operations spt_nvm_ops = {
5795 .acquire = e1000_acquire_nvm_ich8lan,
5796 .release = e1000_release_nvm_ich8lan,
5797 .read = e1000_read_nvm_spt,
5798 .update = e1000_update_nvm_checksum_spt,
5799 .reload = e1000e_reload_nvm_generic,
5800 .valid_led_default = e1000_valid_led_default_ich8lan,
5801 .validate = e1000_validate_nvm_checksum_ich8lan,
5802 .write = e1000_write_nvm_ich8lan,
5803};
5804
5805const struct e1000_info e1000_ich8_info = {
5806 .mac = e1000_ich8lan,
5807 .flags = FLAG_HAS_WOL
5808 | FLAG_IS_ICH
5809 | FLAG_HAS_CTRLEXT_ON_LOAD
5810 | FLAG_HAS_AMT
5811 | FLAG_HAS_FLASH
5812 | FLAG_APME_IN_WUC,
5813 .pba = 8,
5814 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
5815 .get_variants = e1000_get_variants_ich8lan,
5816 .mac_ops = &ich8_mac_ops,
5817 .phy_ops = &ich8_phy_ops,
5818 .nvm_ops = &ich8_nvm_ops,
5819};
5820
5821const struct e1000_info e1000_ich9_info = {
5822 .mac = e1000_ich9lan,
5823 .flags = FLAG_HAS_JUMBO_FRAMES
5824 | FLAG_IS_ICH
5825 | FLAG_HAS_WOL
5826 | FLAG_HAS_CTRLEXT_ON_LOAD
5827 | FLAG_HAS_AMT
5828 | FLAG_HAS_FLASH
5829 | FLAG_APME_IN_WUC,
5830 .pba = 18,
5831 .max_hw_frame_size = DEFAULT_JUMBO,
5832 .get_variants = e1000_get_variants_ich8lan,
5833 .mac_ops = &ich8_mac_ops,
5834 .phy_ops = &ich8_phy_ops,
5835 .nvm_ops = &ich8_nvm_ops,
5836};
5837
5838const struct e1000_info e1000_ich10_info = {
5839 .mac = e1000_ich10lan,
5840 .flags = FLAG_HAS_JUMBO_FRAMES
5841 | FLAG_IS_ICH
5842 | FLAG_HAS_WOL
5843 | FLAG_HAS_CTRLEXT_ON_LOAD
5844 | FLAG_HAS_AMT
5845 | FLAG_HAS_FLASH
5846 | FLAG_APME_IN_WUC,
5847 .pba = 18,
5848 .max_hw_frame_size = DEFAULT_JUMBO,
5849 .get_variants = e1000_get_variants_ich8lan,
5850 .mac_ops = &ich8_mac_ops,
5851 .phy_ops = &ich8_phy_ops,
5852 .nvm_ops = &ich8_nvm_ops,
5853};
5854
5855const struct e1000_info e1000_pch_info = {
5856 .mac = e1000_pchlan,
5857 .flags = FLAG_IS_ICH
5858 | FLAG_HAS_WOL
5859 | FLAG_HAS_CTRLEXT_ON_LOAD
5860 | FLAG_HAS_AMT
5861 | FLAG_HAS_FLASH
5862 | FLAG_HAS_JUMBO_FRAMES
5863 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
5864 | FLAG_APME_IN_WUC,
5865 .flags2 = FLAG2_HAS_PHY_STATS,
5866 .pba = 26,
5867 .max_hw_frame_size = 4096,
5868 .get_variants = e1000_get_variants_ich8lan,
5869 .mac_ops = &ich8_mac_ops,
5870 .phy_ops = &ich8_phy_ops,
5871 .nvm_ops = &ich8_nvm_ops,
5872};
5873
5874const struct e1000_info e1000_pch2_info = {
5875 .mac = e1000_pch2lan,
5876 .flags = FLAG_IS_ICH
5877 | FLAG_HAS_WOL
5878 | FLAG_HAS_HW_TIMESTAMP
5879 | FLAG_HAS_CTRLEXT_ON_LOAD
5880 | FLAG_HAS_AMT
5881 | FLAG_HAS_FLASH
5882 | FLAG_HAS_JUMBO_FRAMES
5883 | FLAG_APME_IN_WUC,
5884 .flags2 = FLAG2_HAS_PHY_STATS
5885 | FLAG2_HAS_EEE
5886 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5887 .pba = 26,
5888 .max_hw_frame_size = 9022,
5889 .get_variants = e1000_get_variants_ich8lan,
5890 .mac_ops = &ich8_mac_ops,
5891 .phy_ops = &ich8_phy_ops,
5892 .nvm_ops = &ich8_nvm_ops,
5893};
5894
5895const struct e1000_info e1000_pch_lpt_info = {
5896 .mac = e1000_pch_lpt,
5897 .flags = FLAG_IS_ICH
5898 | FLAG_HAS_WOL
5899 | FLAG_HAS_HW_TIMESTAMP
5900 | FLAG_HAS_CTRLEXT_ON_LOAD
5901 | FLAG_HAS_AMT
5902 | FLAG_HAS_FLASH
5903 | FLAG_HAS_JUMBO_FRAMES
5904 | FLAG_APME_IN_WUC,
5905 .flags2 = FLAG2_HAS_PHY_STATS
5906 | FLAG2_HAS_EEE
5907 | FLAG2_CHECK_SYSTIM_OVERFLOW,
5908 .pba = 26,
5909 .max_hw_frame_size = 9022,
5910 .get_variants = e1000_get_variants_ich8lan,
5911 .mac_ops = &ich8_mac_ops,
5912 .phy_ops = &ich8_phy_ops,
5913 .nvm_ops = &ich8_nvm_ops,
5914};
5915
5916const struct e1000_info e1000_pch_spt_info = {
5917 .mac = e1000_pch_spt,
5918 .flags = FLAG_IS_ICH
5919 | FLAG_HAS_WOL
5920 | FLAG_HAS_HW_TIMESTAMP
5921 | FLAG_HAS_CTRLEXT_ON_LOAD
5922 | FLAG_HAS_AMT
5923 | FLAG_HAS_FLASH
5924 | FLAG_HAS_JUMBO_FRAMES
5925 | FLAG_APME_IN_WUC,
5926 .flags2 = FLAG2_HAS_PHY_STATS
5927 | FLAG2_HAS_EEE,
5928 .pba = 26,
5929 .max_hw_frame_size = 9022,
5930 .get_variants = e1000_get_variants_ich8lan,
5931 .mac_ops = &ich8_mac_ops,
5932 .phy_ops = &ich8_phy_ops,
5933 .nvm_ops = &spt_nvm_ops,
5934};
5935
5936const struct e1000_info e1000_pch_cnp_info = {
5937 .mac = e1000_pch_cnp,
5938 .flags = FLAG_IS_ICH
5939 | FLAG_HAS_WOL
5940 | FLAG_HAS_HW_TIMESTAMP
5941 | FLAG_HAS_CTRLEXT_ON_LOAD
5942 | FLAG_HAS_AMT
5943 | FLAG_HAS_FLASH
5944 | FLAG_HAS_JUMBO_FRAMES
5945 | FLAG_APME_IN_WUC,
5946 .flags2 = FLAG2_HAS_PHY_STATS
5947 | FLAG2_HAS_EEE,
5948 .pba = 26,
5949 .max_hw_frame_size = 9022,
5950 .get_variants = e1000_get_variants_ich8lan,
5951 .mac_ops = &ich8_mac_ops,
5952 .phy_ops = &ich8_phy_ops,
5953 .nvm_ops = &spt_nvm_ops,
5954};