Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9#include <linux/bitfield.h>
10#include <linux/delay.h>
11#include <linux/export.h>
12#include <linux/gpio.h>
13#include <linux/if_vlan.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_data/microchip-ksz.h>
17#include <linux/phy.h>
18#include <linux/etherdevice.h>
19#include <linux/if_bridge.h>
20#include <linux/micrel_phy.h>
21#include <net/dsa.h>
22#include <net/switchdev.h>
23#include <linux/phylink.h>
24
25#include "ksz_common.h"
26#include "ksz8795_reg.h"
27#include "ksz8.h"
28
29static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
30{
31 regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0);
32}
33
34static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
35 bool set)
36{
37 regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset),
38 bits, set ? bits : 0);
39}
40
41static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data)
42{
43 const u16 *regs;
44 u16 ctrl_addr;
45 int ret = 0;
46
47 regs = dev->info->regs;
48
49 mutex_lock(&dev->alu_mutex);
50
51 ctrl_addr = IND_ACC_TABLE(table) | addr;
52 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
53 if (!ret)
54 ret = ksz_write8(dev, regs[REG_IND_BYTE], data);
55
56 mutex_unlock(&dev->alu_mutex);
57
58 return ret;
59}
60
61int ksz8_reset_switch(struct ksz_device *dev)
62{
63 if (ksz_is_ksz88x3(dev)) {
64 /* reset switch */
65 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
66 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
67 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
68 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
69 } else {
70 /* reset switch */
71 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
72 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
73 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
74 }
75
76 return 0;
77}
78
79static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size)
80{
81 u8 ctrl2 = 0;
82
83 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE)
84 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE;
85 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
86 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE;
87
88 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE |
89 KSZ8863_HUGE_PACKET_ENABLE, ctrl2);
90}
91
92static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size)
93{
94 u8 ctrl1 = 0, ctrl2 = 0;
95 int ret;
96
97 if (frame_size > KSZ8_LEGAL_PACKET_SIZE)
98 ctrl2 |= SW_LEGAL_PACKET_DISABLE;
99 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
100 ctrl1 |= SW_HUGE_PACKET;
101
102 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1);
103 if (ret)
104 return ret;
105
106 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2);
107}
108
109int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu)
110{
111 u16 frame_size;
112
113 if (!dsa_is_cpu_port(dev->ds, port))
114 return 0;
115
116 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
117
118 switch (dev->chip_id) {
119 case KSZ8795_CHIP_ID:
120 case KSZ8794_CHIP_ID:
121 case KSZ8765_CHIP_ID:
122 return ksz8795_change_mtu(dev, frame_size);
123 case KSZ8830_CHIP_ID:
124 return ksz8863_change_mtu(dev, frame_size);
125 }
126
127 return -EOPNOTSUPP;
128}
129
130static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
131{
132 u8 hi, lo;
133
134 /* Number of queues can only be 1, 2, or 4. */
135 switch (queue) {
136 case 4:
137 case 3:
138 queue = PORT_QUEUE_SPLIT_4;
139 break;
140 case 2:
141 queue = PORT_QUEUE_SPLIT_2;
142 break;
143 default:
144 queue = PORT_QUEUE_SPLIT_1;
145 }
146 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
147 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
148 lo &= ~PORT_QUEUE_SPLIT_L;
149 if (queue & PORT_QUEUE_SPLIT_2)
150 lo |= PORT_QUEUE_SPLIT_L;
151 hi &= ~PORT_QUEUE_SPLIT_H;
152 if (queue & PORT_QUEUE_SPLIT_4)
153 hi |= PORT_QUEUE_SPLIT_H;
154 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
155 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
156
157 /* Default is port based for egress rate limit. */
158 if (queue != PORT_QUEUE_SPLIT_1)
159 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
160 true);
161}
162
163void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
164{
165 const u32 *masks;
166 const u16 *regs;
167 u16 ctrl_addr;
168 u32 data;
169 u8 check;
170 int loop;
171
172 masks = dev->info->masks;
173 regs = dev->info->regs;
174
175 ctrl_addr = addr + dev->info->reg_mib_cnt * port;
176 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
177
178 mutex_lock(&dev->alu_mutex);
179 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
180
181 /* It is almost guaranteed to always read the valid bit because of
182 * slow SPI speed.
183 */
184 for (loop = 2; loop > 0; loop--) {
185 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
186
187 if (check & masks[MIB_COUNTER_VALID]) {
188 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
189 if (check & masks[MIB_COUNTER_OVERFLOW])
190 *cnt += MIB_COUNTER_VALUE + 1;
191 *cnt += data & MIB_COUNTER_VALUE;
192 break;
193 }
194 }
195 mutex_unlock(&dev->alu_mutex);
196}
197
198static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
199 u64 *dropped, u64 *cnt)
200{
201 const u32 *masks;
202 const u16 *regs;
203 u16 ctrl_addr;
204 u32 data;
205 u8 check;
206 int loop;
207
208 masks = dev->info->masks;
209 regs = dev->info->regs;
210
211 addr -= dev->info->reg_mib_cnt;
212 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
213 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
214 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
215
216 mutex_lock(&dev->alu_mutex);
217 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
218
219 /* It is almost guaranteed to always read the valid bit because of
220 * slow SPI speed.
221 */
222 for (loop = 2; loop > 0; loop--) {
223 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
224
225 if (check & masks[MIB_COUNTER_VALID]) {
226 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
227 if (addr < 2) {
228 u64 total;
229
230 total = check & MIB_TOTAL_BYTES_H;
231 total <<= 32;
232 *cnt += total;
233 *cnt += data;
234 if (check & masks[MIB_COUNTER_OVERFLOW]) {
235 total = MIB_TOTAL_BYTES_H + 1;
236 total <<= 32;
237 *cnt += total;
238 }
239 } else {
240 if (check & masks[MIB_COUNTER_OVERFLOW])
241 *cnt += MIB_PACKET_DROPPED + 1;
242 *cnt += data & MIB_PACKET_DROPPED;
243 }
244 break;
245 }
246 }
247 mutex_unlock(&dev->alu_mutex);
248}
249
250static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
251 u64 *dropped, u64 *cnt)
252{
253 u32 *last = (u32 *)dropped;
254 const u16 *regs;
255 u16 ctrl_addr;
256 u32 data;
257 u32 cur;
258
259 regs = dev->info->regs;
260
261 addr -= dev->info->reg_mib_cnt;
262 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
263 KSZ8863_MIB_PACKET_DROPPED_RX_0;
264 ctrl_addr += port;
265 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
266
267 mutex_lock(&dev->alu_mutex);
268 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
269 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
270 mutex_unlock(&dev->alu_mutex);
271
272 data &= MIB_PACKET_DROPPED;
273 cur = last[addr];
274 if (data != cur) {
275 last[addr] = data;
276 if (data < cur)
277 data += MIB_PACKET_DROPPED + 1;
278 data -= cur;
279 *cnt += data;
280 }
281}
282
283void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
284 u64 *dropped, u64 *cnt)
285{
286 if (ksz_is_ksz88x3(dev))
287 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
288 else
289 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
290}
291
292void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
293{
294 if (ksz_is_ksz88x3(dev))
295 return;
296
297 /* enable the port for flush/freeze function */
298 if (freeze)
299 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
300 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
301
302 /* disable the port after freeze is done */
303 if (!freeze)
304 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
305}
306
307void ksz8_port_init_cnt(struct ksz_device *dev, int port)
308{
309 struct ksz_port_mib *mib = &dev->ports[port].mib;
310 u64 *dropped;
311
312 if (!ksz_is_ksz88x3(dev)) {
313 /* flush all enabled port MIB counters */
314 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
315 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
316 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
317 }
318
319 mib->cnt_ptr = 0;
320
321 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
322 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
323 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
324 &mib->counters[mib->cnt_ptr]);
325 ++mib->cnt_ptr;
326 }
327
328 /* last one in storage */
329 dropped = &mib->counters[dev->info->mib_cnt];
330
331 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
332 while (mib->cnt_ptr < dev->info->mib_cnt) {
333 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
334 dropped, &mib->counters[mib->cnt_ptr]);
335 ++mib->cnt_ptr;
336 }
337}
338
339static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
340{
341 const u16 *regs;
342 u16 ctrl_addr;
343 int ret;
344
345 regs = dev->info->regs;
346
347 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
348
349 mutex_lock(&dev->alu_mutex);
350 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
351 if (ret)
352 goto unlock_alu;
353
354 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data);
355unlock_alu:
356 mutex_unlock(&dev->alu_mutex);
357
358 return ret;
359}
360
361static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
362{
363 const u16 *regs;
364 u16 ctrl_addr;
365 int ret;
366
367 regs = dev->info->regs;
368
369 ctrl_addr = IND_ACC_TABLE(table) | addr;
370
371 mutex_lock(&dev->alu_mutex);
372 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data);
373 if (ret)
374 goto unlock_alu;
375
376 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
377unlock_alu:
378 mutex_unlock(&dev->alu_mutex);
379
380 return ret;
381}
382
383static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
384{
385 int timeout = 100;
386 const u32 *masks;
387 const u16 *regs;
388
389 masks = dev->info->masks;
390 regs = dev->info->regs;
391
392 do {
393 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
394 timeout--;
395 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
396
397 /* Entry is not ready for accessing. */
398 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) {
399 return -EAGAIN;
400 /* Entry is ready for accessing. */
401 } else {
402 ksz_read8(dev, regs[REG_IND_DATA_8], data);
403
404 /* There is no valid entry in the table. */
405 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY])
406 return -ENXIO;
407 }
408 return 0;
409}
410
411int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr,
412 u8 *fid, u8 *src_port, u8 *timestamp, u16 *entries)
413{
414 u32 data_hi, data_lo;
415 const u8 *shifts;
416 const u32 *masks;
417 const u16 *regs;
418 u16 ctrl_addr;
419 u8 data;
420 int rc;
421
422 shifts = dev->info->shifts;
423 masks = dev->info->masks;
424 regs = dev->info->regs;
425
426 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
427
428 mutex_lock(&dev->alu_mutex);
429 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
430
431 rc = ksz8_valid_dyn_entry(dev, &data);
432 if (rc == -EAGAIN) {
433 if (addr == 0)
434 *entries = 0;
435 } else if (rc == -ENXIO) {
436 *entries = 0;
437 /* At least one valid entry in the table. */
438 } else {
439 u64 buf = 0;
440 int cnt;
441
442 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
443 data_hi = (u32)(buf >> 32);
444 data_lo = (u32)buf;
445
446 /* Check out how many valid entry in the table. */
447 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
448 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
449 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
450 shifts[DYNAMIC_MAC_ENTRIES];
451 *entries = cnt + 1;
452
453 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
454 shifts[DYNAMIC_MAC_FID];
455 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
456 shifts[DYNAMIC_MAC_SRC_PORT];
457 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >>
458 shifts[DYNAMIC_MAC_TIMESTAMP];
459
460 mac_addr[5] = (u8)data_lo;
461 mac_addr[4] = (u8)(data_lo >> 8);
462 mac_addr[3] = (u8)(data_lo >> 16);
463 mac_addr[2] = (u8)(data_lo >> 24);
464
465 mac_addr[1] = (u8)data_hi;
466 mac_addr[0] = (u8)(data_hi >> 8);
467 rc = 0;
468 }
469 mutex_unlock(&dev->alu_mutex);
470
471 return rc;
472}
473
474static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
475 struct alu_struct *alu, bool *valid)
476{
477 u32 data_hi, data_lo;
478 const u8 *shifts;
479 const u32 *masks;
480 u64 data;
481 int ret;
482
483 shifts = dev->info->shifts;
484 masks = dev->info->masks;
485
486 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
487 if (ret)
488 return ret;
489
490 data_hi = data >> 32;
491 data_lo = (u32)data;
492
493 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] |
494 masks[STATIC_MAC_TABLE_OVERRIDE]))) {
495 *valid = false;
496 return 0;
497 }
498
499 alu->mac[5] = (u8)data_lo;
500 alu->mac[4] = (u8)(data_lo >> 8);
501 alu->mac[3] = (u8)(data_lo >> 16);
502 alu->mac[2] = (u8)(data_lo >> 24);
503 alu->mac[1] = (u8)data_hi;
504 alu->mac[0] = (u8)(data_hi >> 8);
505 alu->port_forward =
506 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
507 shifts[STATIC_MAC_FWD_PORTS];
508 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
509
510 /* KSZ8795 family switches have STATIC_MAC_TABLE_USE_FID and
511 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the
512 * static MAC table compared to doing write.
513 */
514 if (ksz_is_ksz87xx(dev))
515 data_hi >>= 1;
516 alu->is_static = true;
517 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
518 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
519 shifts[STATIC_MAC_FID];
520
521 *valid = true;
522
523 return 0;
524}
525
526static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
527 struct alu_struct *alu)
528{
529 u32 data_hi, data_lo;
530 const u8 *shifts;
531 const u32 *masks;
532 u64 data;
533
534 shifts = dev->info->shifts;
535 masks = dev->info->masks;
536
537 data_lo = ((u32)alu->mac[2] << 24) |
538 ((u32)alu->mac[3] << 16) |
539 ((u32)alu->mac[4] << 8) | alu->mac[5];
540 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
541 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
542
543 if (alu->is_override)
544 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
545 if (alu->is_use_fid) {
546 data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
547 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
548 }
549 if (alu->is_static)
550 data_hi |= masks[STATIC_MAC_TABLE_VALID];
551 else
552 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
553
554 data = (u64)data_hi << 32 | data_lo;
555
556 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
557}
558
559static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
560 u8 *member, u8 *valid)
561{
562 const u8 *shifts;
563 const u32 *masks;
564
565 shifts = dev->info->shifts;
566 masks = dev->info->masks;
567
568 *fid = vlan & masks[VLAN_TABLE_FID];
569 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
570 shifts[VLAN_TABLE_MEMBERSHIP_S];
571 *valid = !!(vlan & masks[VLAN_TABLE_VALID]);
572}
573
574static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
575 u16 *vlan)
576{
577 const u8 *shifts;
578 const u32 *masks;
579
580 shifts = dev->info->shifts;
581 masks = dev->info->masks;
582
583 *vlan = fid;
584 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
585 if (valid)
586 *vlan |= masks[VLAN_TABLE_VALID];
587}
588
589static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
590{
591 const u8 *shifts;
592 u64 data;
593 int i;
594
595 shifts = dev->info->shifts;
596
597 ksz8_r_table(dev, TABLE_VLAN, addr, &data);
598 addr *= 4;
599 for (i = 0; i < 4; i++) {
600 dev->vlan_cache[addr + i].table[0] = (u16)data;
601 data >>= shifts[VLAN_TABLE];
602 }
603}
604
605static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
606{
607 int index;
608 u16 *data;
609 u16 addr;
610 u64 buf;
611
612 data = (u16 *)&buf;
613 addr = vid / 4;
614 index = vid & 3;
615 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
616 *vlan = data[index];
617}
618
619static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
620{
621 int index;
622 u16 *data;
623 u16 addr;
624 u64 buf;
625
626 data = (u16 *)&buf;
627 addr = vid / 4;
628 index = vid & 3;
629 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
630 data[index] = vlan;
631 dev->vlan_cache[vid].table[0] = vlan;
632 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
633}
634
635/**
636 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY
637 * Control register (Reg. 31).
638 * @dev: The KSZ device instance.
639 * @port: The port number to be read.
640 * @val: The value read from the SMI interface.
641 *
642 * This function reads the SMI interface and translates the hardware register
643 * bit values into their corresponding control settings for a MIIM PHY Control
644 * register.
645 *
646 * Return: 0 on success, error code on failure.
647 */
648static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val)
649{
650 const u16 *regs = dev->info->regs;
651 u8 reg_val;
652 int ret;
653
654 *val = 0;
655
656 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val);
657 if (ret < 0)
658 return ret;
659
660 if (reg_val & PORT_MDIX_STATUS)
661 *val |= KSZ886X_CTRL_MDIX_STAT;
662
663 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val);
664 if (ret < 0)
665 return ret;
666
667 if (reg_val & PORT_FORCE_LINK)
668 *val |= KSZ886X_CTRL_FORCE_LINK;
669
670 if (reg_val & PORT_POWER_SAVING)
671 *val |= KSZ886X_CTRL_PWRSAVE;
672
673 if (reg_val & PORT_PHY_REMOTE_LOOPBACK)
674 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK;
675
676 return 0;
677}
678
679int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
680{
681 u8 restart, speed, ctrl, link;
682 int processed = true;
683 const u16 *regs;
684 u8 val1, val2;
685 u16 data = 0;
686 u8 p = phy;
687 int ret;
688
689 regs = dev->info->regs;
690
691 switch (reg) {
692 case MII_BMCR:
693 ret = ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
694 if (ret)
695 return ret;
696
697 ret = ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
698 if (ret)
699 return ret;
700
701 ret = ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
702 if (ret)
703 return ret;
704
705 if (restart & PORT_PHY_LOOPBACK)
706 data |= BMCR_LOOPBACK;
707 if (ctrl & PORT_FORCE_100_MBIT)
708 data |= BMCR_SPEED100;
709 if (ksz_is_ksz88x3(dev)) {
710 if ((ctrl & PORT_AUTO_NEG_ENABLE))
711 data |= BMCR_ANENABLE;
712 } else {
713 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
714 data |= BMCR_ANENABLE;
715 }
716 if (restart & PORT_POWER_DOWN)
717 data |= BMCR_PDOWN;
718 if (restart & PORT_AUTO_NEG_RESTART)
719 data |= BMCR_ANRESTART;
720 if (ctrl & PORT_FORCE_FULL_DUPLEX)
721 data |= BMCR_FULLDPLX;
722 if (speed & PORT_HP_MDIX)
723 data |= KSZ886X_BMCR_HP_MDIX;
724 if (restart & PORT_FORCE_MDIX)
725 data |= KSZ886X_BMCR_FORCE_MDI;
726 if (restart & PORT_AUTO_MDIX_DISABLE)
727 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
728 if (restart & PORT_TX_DISABLE)
729 data |= KSZ886X_BMCR_DISABLE_TRANSMIT;
730 if (restart & PORT_LED_OFF)
731 data |= KSZ886X_BMCR_DISABLE_LED;
732 break;
733 case MII_BMSR:
734 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
735 if (ret)
736 return ret;
737
738 data = BMSR_100FULL |
739 BMSR_100HALF |
740 BMSR_10FULL |
741 BMSR_10HALF |
742 BMSR_ANEGCAPABLE;
743 if (link & PORT_AUTO_NEG_COMPLETE)
744 data |= BMSR_ANEGCOMPLETE;
745 if (link & PORT_STAT_LINK_GOOD)
746 data |= BMSR_LSTATUS;
747 break;
748 case MII_PHYSID1:
749 data = KSZ8795_ID_HI;
750 break;
751 case MII_PHYSID2:
752 if (ksz_is_ksz88x3(dev))
753 data = KSZ8863_ID_LO;
754 else
755 data = KSZ8795_ID_LO;
756 break;
757 case MII_ADVERTISE:
758 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
759 if (ret)
760 return ret;
761
762 data = ADVERTISE_CSMA;
763 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
764 data |= ADVERTISE_PAUSE_CAP;
765 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
766 data |= ADVERTISE_100FULL;
767 if (ctrl & PORT_AUTO_NEG_100BTX)
768 data |= ADVERTISE_100HALF;
769 if (ctrl & PORT_AUTO_NEG_10BT_FD)
770 data |= ADVERTISE_10FULL;
771 if (ctrl & PORT_AUTO_NEG_10BT)
772 data |= ADVERTISE_10HALF;
773 break;
774 case MII_LPA:
775 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
776 if (ret)
777 return ret;
778
779 data = LPA_SLCT;
780 if (link & PORT_REMOTE_SYM_PAUSE)
781 data |= LPA_PAUSE_CAP;
782 if (link & PORT_REMOTE_100BTX_FD)
783 data |= LPA_100FULL;
784 if (link & PORT_REMOTE_100BTX)
785 data |= LPA_100HALF;
786 if (link & PORT_REMOTE_10BT_FD)
787 data |= LPA_10FULL;
788 if (link & PORT_REMOTE_10BT)
789 data |= LPA_10HALF;
790 if (data & ~LPA_SLCT)
791 data |= LPA_LPACK;
792 break;
793 case PHY_REG_LINK_MD:
794 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
795 if (ret)
796 return ret;
797
798 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
799 if (ret)
800 return ret;
801
802 if (val1 & PORT_START_CABLE_DIAG)
803 data |= PHY_START_CABLE_DIAG;
804
805 if (val1 & PORT_CABLE_10M_SHORT)
806 data |= PHY_CABLE_10M_SHORT;
807
808 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
809 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
810
811 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
812 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
813 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
814 break;
815 case PHY_REG_PHY_CTRL:
816 ret = ksz8_r_phy_ctrl(dev, p, &data);
817 if (ret)
818 return ret;
819
820 break;
821 default:
822 processed = false;
823 break;
824 }
825 if (processed)
826 *val = data;
827
828 return 0;
829}
830
831/**
832 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY
833 * Control register (Reg. 31).
834 * @dev: The KSZ device instance.
835 * @port: The port number to be configured.
836 * @val: The register value to be written.
837 *
838 * This function translates control settings from a MIIM PHY Control register
839 * into their corresponding hardware register bit values for the SMI
840 * interface.
841 *
842 * Return: 0 on success, error code on failure.
843 */
844static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val)
845{
846 u8 reg_val = 0;
847 int ret;
848
849 if (val & KSZ886X_CTRL_FORCE_LINK)
850 reg_val |= PORT_FORCE_LINK;
851
852 if (val & KSZ886X_CTRL_PWRSAVE)
853 reg_val |= PORT_POWER_SAVING;
854
855 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK)
856 reg_val |= PORT_PHY_REMOTE_LOOPBACK;
857
858 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK |
859 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val);
860 return ret;
861}
862
863int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
864{
865 u8 restart, speed, ctrl, data;
866 const u16 *regs;
867 u8 p = phy;
868 int ret;
869
870 regs = dev->info->regs;
871
872 switch (reg) {
873 case MII_BMCR:
874
875 /* Do not support PHY reset function. */
876 if (val & BMCR_RESET)
877 break;
878 ret = ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
879 if (ret)
880 return ret;
881
882 data = speed;
883 if (val & KSZ886X_BMCR_HP_MDIX)
884 data |= PORT_HP_MDIX;
885 else
886 data &= ~PORT_HP_MDIX;
887
888 if (data != speed) {
889 ret = ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data);
890 if (ret)
891 return ret;
892 }
893
894 ret = ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
895 if (ret)
896 return ret;
897
898 data = ctrl;
899 if (ksz_is_ksz88x3(dev)) {
900 if ((val & BMCR_ANENABLE))
901 data |= PORT_AUTO_NEG_ENABLE;
902 else
903 data &= ~PORT_AUTO_NEG_ENABLE;
904 } else {
905 if (!(val & BMCR_ANENABLE))
906 data |= PORT_AUTO_NEG_DISABLE;
907 else
908 data &= ~PORT_AUTO_NEG_DISABLE;
909
910 /* Fiber port does not support auto-negotiation. */
911 if (dev->ports[p].fiber)
912 data |= PORT_AUTO_NEG_DISABLE;
913 }
914
915 if (val & BMCR_SPEED100)
916 data |= PORT_FORCE_100_MBIT;
917 else
918 data &= ~PORT_FORCE_100_MBIT;
919 if (val & BMCR_FULLDPLX)
920 data |= PORT_FORCE_FULL_DUPLEX;
921 else
922 data &= ~PORT_FORCE_FULL_DUPLEX;
923
924 if (data != ctrl) {
925 ret = ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data);
926 if (ret)
927 return ret;
928 }
929
930 ret = ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
931 if (ret)
932 return ret;
933
934 data = restart;
935 if (val & KSZ886X_BMCR_DISABLE_LED)
936 data |= PORT_LED_OFF;
937 else
938 data &= ~PORT_LED_OFF;
939 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
940 data |= PORT_TX_DISABLE;
941 else
942 data &= ~PORT_TX_DISABLE;
943 if (val & BMCR_ANRESTART)
944 data |= PORT_AUTO_NEG_RESTART;
945 else
946 data &= ~(PORT_AUTO_NEG_RESTART);
947 if (val & BMCR_PDOWN)
948 data |= PORT_POWER_DOWN;
949 else
950 data &= ~PORT_POWER_DOWN;
951 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
952 data |= PORT_AUTO_MDIX_DISABLE;
953 else
954 data &= ~PORT_AUTO_MDIX_DISABLE;
955 if (val & KSZ886X_BMCR_FORCE_MDI)
956 data |= PORT_FORCE_MDIX;
957 else
958 data &= ~PORT_FORCE_MDIX;
959 if (val & BMCR_LOOPBACK)
960 data |= PORT_PHY_LOOPBACK;
961 else
962 data &= ~PORT_PHY_LOOPBACK;
963
964 if (data != restart) {
965 ret = ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL],
966 data);
967 if (ret)
968 return ret;
969 }
970 break;
971 case MII_ADVERTISE:
972 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
973 if (ret)
974 return ret;
975
976 data = ctrl;
977 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
978 PORT_AUTO_NEG_100BTX_FD |
979 PORT_AUTO_NEG_100BTX |
980 PORT_AUTO_NEG_10BT_FD |
981 PORT_AUTO_NEG_10BT);
982 if (val & ADVERTISE_PAUSE_CAP)
983 data |= PORT_AUTO_NEG_SYM_PAUSE;
984 if (val & ADVERTISE_100FULL)
985 data |= PORT_AUTO_NEG_100BTX_FD;
986 if (val & ADVERTISE_100HALF)
987 data |= PORT_AUTO_NEG_100BTX;
988 if (val & ADVERTISE_10FULL)
989 data |= PORT_AUTO_NEG_10BT_FD;
990 if (val & ADVERTISE_10HALF)
991 data |= PORT_AUTO_NEG_10BT;
992
993 if (data != ctrl) {
994 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
995 if (ret)
996 return ret;
997 }
998 break;
999 case PHY_REG_LINK_MD:
1000 if (val & PHY_START_CABLE_DIAG)
1001 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
1002 break;
1003
1004 case PHY_REG_PHY_CTRL:
1005 ret = ksz8_w_phy_ctrl(dev, p, val);
1006 if (ret)
1007 return ret;
1008 break;
1009 default:
1010 break;
1011 }
1012
1013 return 0;
1014}
1015
1016void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
1017{
1018 u8 data;
1019
1020 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1021 data &= ~PORT_VLAN_MEMBERSHIP;
1022 data |= (member & dev->port_mask);
1023 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
1024}
1025
1026void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port)
1027{
1028 u8 learn[DSA_MAX_PORTS];
1029 int first, index, cnt;
1030 const u16 *regs;
1031
1032 regs = dev->info->regs;
1033
1034 if ((uint)port < dev->info->port_cnt) {
1035 first = port;
1036 cnt = port + 1;
1037 } else {
1038 /* Flush all ports. */
1039 first = 0;
1040 cnt = dev->info->port_cnt;
1041 }
1042 for (index = first; index < cnt; index++) {
1043 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]);
1044 if (!(learn[index] & PORT_LEARN_DISABLE))
1045 ksz_pwrite8(dev, index, regs[P_STP_CTRL],
1046 learn[index] | PORT_LEARN_DISABLE);
1047 }
1048 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
1049 for (index = first; index < cnt; index++) {
1050 if (!(learn[index] & PORT_LEARN_DISABLE))
1051 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]);
1052 }
1053}
1054
1055int ksz8_fdb_dump(struct ksz_device *dev, int port,
1056 dsa_fdb_dump_cb_t *cb, void *data)
1057{
1058 int ret = 0;
1059 u16 i = 0;
1060 u16 entries = 0;
1061 u8 timestamp = 0;
1062 u8 fid;
1063 u8 src_port;
1064 u8 mac[ETH_ALEN];
1065
1066 do {
1067 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port,
1068 ×tamp, &entries);
1069 if (!ret && port == src_port) {
1070 ret = cb(mac, fid, false, data);
1071 if (ret)
1072 break;
1073 }
1074 i++;
1075 } while (i < entries);
1076 if (i >= entries)
1077 ret = 0;
1078
1079 return ret;
1080}
1081
1082static int ksz8_add_sta_mac(struct ksz_device *dev, int port,
1083 const unsigned char *addr, u16 vid)
1084{
1085 struct alu_struct alu;
1086 int index, ret;
1087 int empty = 0;
1088
1089 alu.port_forward = 0;
1090 for (index = 0; index < dev->info->num_statics; index++) {
1091 bool valid;
1092
1093 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1094 if (ret)
1095 return ret;
1096 if (!valid) {
1097 /* Remember the first empty entry. */
1098 if (!empty)
1099 empty = index + 1;
1100 continue;
1101 }
1102
1103 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1104 break;
1105 }
1106
1107 /* no available entry */
1108 if (index == dev->info->num_statics && !empty)
1109 return -ENOSPC;
1110
1111 /* add entry */
1112 if (index == dev->info->num_statics) {
1113 index = empty - 1;
1114 memset(&alu, 0, sizeof(alu));
1115 memcpy(alu.mac, addr, ETH_ALEN);
1116 alu.is_static = true;
1117 }
1118 alu.port_forward |= BIT(port);
1119 if (vid) {
1120 alu.is_use_fid = true;
1121
1122 /* Need a way to map VID to FID. */
1123 alu.fid = vid;
1124 }
1125
1126 return ksz8_w_sta_mac_table(dev, index, &alu);
1127}
1128
1129static int ksz8_del_sta_mac(struct ksz_device *dev, int port,
1130 const unsigned char *addr, u16 vid)
1131{
1132 struct alu_struct alu;
1133 int index, ret;
1134
1135 for (index = 0; index < dev->info->num_statics; index++) {
1136 bool valid;
1137
1138 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1139 if (ret)
1140 return ret;
1141 if (!valid)
1142 continue;
1143
1144 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1145 break;
1146 }
1147
1148 /* no available entry */
1149 if (index == dev->info->num_statics)
1150 return 0;
1151
1152 /* clear port */
1153 alu.port_forward &= ~BIT(port);
1154 if (!alu.port_forward)
1155 alu.is_static = false;
1156
1157 return ksz8_w_sta_mac_table(dev, index, &alu);
1158}
1159
1160int ksz8_mdb_add(struct ksz_device *dev, int port,
1161 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1162{
1163 return ksz8_add_sta_mac(dev, port, mdb->addr, mdb->vid);
1164}
1165
1166int ksz8_mdb_del(struct ksz_device *dev, int port,
1167 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1168{
1169 return ksz8_del_sta_mac(dev, port, mdb->addr, mdb->vid);
1170}
1171
1172int ksz8_fdb_add(struct ksz_device *dev, int port, const unsigned char *addr,
1173 u16 vid, struct dsa_db db)
1174{
1175 return ksz8_add_sta_mac(dev, port, addr, vid);
1176}
1177
1178int ksz8_fdb_del(struct ksz_device *dev, int port, const unsigned char *addr,
1179 u16 vid, struct dsa_db db)
1180{
1181 return ksz8_del_sta_mac(dev, port, addr, vid);
1182}
1183
1184int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag,
1185 struct netlink_ext_ack *extack)
1186{
1187 if (ksz_is_ksz88x3(dev))
1188 return -ENOTSUPP;
1189
1190 /* Discard packets with VID not enabled on the switch */
1191 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
1192
1193 /* Discard packets with VID not enabled on the ingress port */
1194 for (port = 0; port < dev->phy_port_cnt; ++port)
1195 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
1196 flag);
1197
1198 return 0;
1199}
1200
1201static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
1202{
1203 if (ksz_is_ksz88x3(dev)) {
1204 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID,
1205 0x03 << (4 - 2 * port), state);
1206 } else {
1207 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
1208 }
1209}
1210
1211int ksz8_port_vlan_add(struct ksz_device *dev, int port,
1212 const struct switchdev_obj_port_vlan *vlan,
1213 struct netlink_ext_ack *extack)
1214{
1215 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1216 struct ksz_port *p = &dev->ports[port];
1217 u16 data, new_pvid = 0;
1218 u8 fid, member, valid;
1219
1220 if (ksz_is_ksz88x3(dev))
1221 return -ENOTSUPP;
1222
1223 /* If a VLAN is added with untagged flag different from the
1224 * port's Remove Tag flag, we need to change the latter.
1225 * Ignore VID 0, which is always untagged.
1226 * Ignore CPU port, which will always be tagged.
1227 */
1228 if (untagged != p->remove_tag && vlan->vid != 0 &&
1229 port != dev->cpu_port) {
1230 unsigned int vid;
1231
1232 /* Reject attempts to add a VLAN that requires the
1233 * Remove Tag flag to be changed, unless there are no
1234 * other VLANs currently configured.
1235 */
1236 for (vid = 1; vid < dev->info->num_vlans; ++vid) {
1237 /* Skip the VID we are going to add or reconfigure */
1238 if (vid == vlan->vid)
1239 continue;
1240
1241 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
1242 &fid, &member, &valid);
1243 if (valid && (member & BIT(port)))
1244 return -EINVAL;
1245 }
1246
1247 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1248 p->remove_tag = untagged;
1249 }
1250
1251 ksz8_r_vlan_table(dev, vlan->vid, &data);
1252 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1253
1254 /* First time to setup the VLAN entry. */
1255 if (!valid) {
1256 /* Need to find a way to map VID to FID. */
1257 fid = 1;
1258 valid = 1;
1259 }
1260 member |= BIT(port);
1261
1262 ksz8_to_vlan(dev, fid, member, valid, &data);
1263 ksz8_w_vlan_table(dev, vlan->vid, data);
1264
1265 /* change PVID */
1266 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1267 new_pvid = vlan->vid;
1268
1269 if (new_pvid) {
1270 u16 vid;
1271
1272 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1273 vid &= ~VLAN_VID_MASK;
1274 vid |= new_pvid;
1275 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1276
1277 ksz8_port_enable_pvid(dev, port, true);
1278 }
1279
1280 return 0;
1281}
1282
1283int ksz8_port_vlan_del(struct ksz_device *dev, int port,
1284 const struct switchdev_obj_port_vlan *vlan)
1285{
1286 u16 data, pvid;
1287 u8 fid, member, valid;
1288
1289 if (ksz_is_ksz88x3(dev))
1290 return -ENOTSUPP;
1291
1292 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1293 pvid = pvid & 0xFFF;
1294
1295 ksz8_r_vlan_table(dev, vlan->vid, &data);
1296 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1297
1298 member &= ~BIT(port);
1299
1300 /* Invalidate the entry if no more member. */
1301 if (!member) {
1302 fid = 0;
1303 valid = 0;
1304 }
1305
1306 ksz8_to_vlan(dev, fid, member, valid, &data);
1307 ksz8_w_vlan_table(dev, vlan->vid, data);
1308
1309 if (pvid == vlan->vid)
1310 ksz8_port_enable_pvid(dev, port, false);
1311
1312 return 0;
1313}
1314
1315int ksz8_port_mirror_add(struct ksz_device *dev, int port,
1316 struct dsa_mall_mirror_tc_entry *mirror,
1317 bool ingress, struct netlink_ext_ack *extack)
1318{
1319 if (ingress) {
1320 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1321 dev->mirror_rx |= BIT(port);
1322 } else {
1323 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1324 dev->mirror_tx |= BIT(port);
1325 }
1326
1327 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1328
1329 /* configure mirror port */
1330 if (dev->mirror_rx || dev->mirror_tx)
1331 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1332 PORT_MIRROR_SNIFFER, true);
1333
1334 return 0;
1335}
1336
1337void ksz8_port_mirror_del(struct ksz_device *dev, int port,
1338 struct dsa_mall_mirror_tc_entry *mirror)
1339{
1340 u8 data;
1341
1342 if (mirror->ingress) {
1343 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1344 dev->mirror_rx &= ~BIT(port);
1345 } else {
1346 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1347 dev->mirror_tx &= ~BIT(port);
1348 }
1349
1350 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1351
1352 if (!dev->mirror_rx && !dev->mirror_tx)
1353 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1354 PORT_MIRROR_SNIFFER, false);
1355}
1356
1357static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
1358{
1359 struct ksz_port *p = &dev->ports[port];
1360
1361 if (!ksz_is_ksz87xx(dev))
1362 return;
1363
1364 if (!p->interface && dev->compat_interface) {
1365 dev_warn(dev->dev,
1366 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1367 "Please update your device tree.\n",
1368 port);
1369 p->interface = dev->compat_interface;
1370 }
1371}
1372
1373void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1374{
1375 struct dsa_switch *ds = dev->ds;
1376 const u32 *masks;
1377 u8 member;
1378
1379 masks = dev->info->masks;
1380
1381 /* enable broadcast storm limit */
1382 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1383
1384 if (!ksz_is_ksz88x3(dev))
1385 ksz8795_set_prio_queue(dev, port, 4);
1386
1387 /* disable DiffServ priority */
1388 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
1389
1390 /* replace priority */
1391 ksz_port_cfg(dev, port, P_802_1P_CTRL,
1392 masks[PORT_802_1P_REMAPPING], false);
1393
1394 /* enable 802.1p priority */
1395 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
1396
1397 if (cpu_port)
1398 member = dsa_user_ports(ds);
1399 else
1400 member = BIT(dsa_upstream_port(ds, port));
1401
1402 ksz8_cfg_port_member(dev, port, member);
1403}
1404
1405static void ksz88x3_config_rmii_clk(struct ksz_device *dev)
1406{
1407 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port);
1408 bool rmii_clk_internal;
1409
1410 if (!ksz_is_ksz88x3(dev))
1411 return;
1412
1413 rmii_clk_internal = of_property_read_bool(cpu_dp->dn,
1414 "microchip,rmii-clk-internal");
1415
1416 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE,
1417 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal);
1418}
1419
1420void ksz8_config_cpu_port(struct dsa_switch *ds)
1421{
1422 struct ksz_device *dev = ds->priv;
1423 struct ksz_port *p;
1424 const u32 *masks;
1425 const u16 *regs;
1426 u8 remote;
1427 int i;
1428
1429 masks = dev->info->masks;
1430 regs = dev->info->regs;
1431
1432 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1433
1434 ksz8_port_setup(dev, dev->cpu_port, true);
1435
1436 ksz8795_cpu_interface_select(dev, dev->cpu_port);
1437 ksz88x3_config_rmii_clk(dev);
1438
1439 for (i = 0; i < dev->phy_port_cnt; i++) {
1440 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1441 }
1442 for (i = 0; i < dev->phy_port_cnt; i++) {
1443 p = &dev->ports[i];
1444
1445 if (!ksz_is_ksz88x3(dev)) {
1446 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
1447 if (remote & KSZ8_PORT_FIBER_MODE)
1448 p->fiber = 1;
1449 }
1450 if (p->fiber)
1451 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1452 PORT_FORCE_FLOW_CTRL, true);
1453 else
1454 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1455 PORT_FORCE_FLOW_CTRL, false);
1456 }
1457}
1458
1459/**
1460 * ksz8_phy_port_link_up - Configures ports with integrated PHYs
1461 * @dev: The KSZ device instance.
1462 * @port: The port number to configure.
1463 * @duplex: The desired duplex mode.
1464 * @tx_pause: If true, enables transmit pause.
1465 * @rx_pause: If true, enables receive pause.
1466 *
1467 * Description:
1468 * The function configures flow control settings for a given port based on the
1469 * desired settings and current duplex mode.
1470 *
1471 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the
1472 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3)
1473 * determines how flow control is handled on the port:
1474 * "1 = will always enable full-duplex flow control on the port, regardless
1475 * of AN result.
1476 * 0 = full-duplex flow control is enabled based on AN result."
1477 *
1478 * This means that the flow control behavior depends on the state of this bit:
1479 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and
1480 * force flow control on the port.
1481 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable
1482 * flow control based on the AN results.
1483 *
1484 * However, there is a potential limitation in this configuration. It is
1485 * currently not possible to force disable flow control on a port if we still
1486 * advertise pause support. While such a configuration is not currently
1487 * supported by Linux, and may not make practical sense, it's important to be
1488 * aware of this limitation when working with the KSZ8873 and similar devices.
1489 */
1490static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex,
1491 bool tx_pause, bool rx_pause)
1492{
1493 const u16 *regs = dev->info->regs;
1494 u8 sctrl = 0;
1495
1496 /* The KSZ8795 switch differs from the KSZ8873 by supporting
1497 * asymmetric pause control. However, since a single bit is used to
1498 * control both RX and TX pause, we can't enforce asymmetric pause
1499 * control - both TX and RX pause will be either enabled or disabled
1500 * together.
1501 *
1502 * If auto-negotiation is enabled, we usually allow the flow control to
1503 * be determined by the auto-negotiation process based on the
1504 * capabilities of both link partners. However, for KSZ8873, the
1505 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap,
1506 * ignoring the auto-negotiation result. Thus, even in auto-negotiation
1507 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is
1508 * properly cleared.
1509 *
1510 * In the absence of pause auto-negotiation, we will enforce symmetric
1511 * pause control for both variants of switches - KSZ8873 and KSZ8795.
1512 *
1513 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL
1514 * 1 1 x 0
1515 * 0 1 x 0 (flow control probably disabled)
1516 * x 0 1 1 (flow control force enabled)
1517 * 1 0 0 0 (flow control still depends on
1518 * aneg result due to hardware)
1519 * 0 0 0 0 (flow control probably disabled)
1520 */
1521 if (dev->ports[port].manual_flow && tx_pause)
1522 sctrl |= PORT_FORCE_FLOW_CTRL;
1523
1524 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl);
1525}
1526
1527/**
1528 * ksz8_cpu_port_link_up - Configures the CPU port of the switch.
1529 * @dev: The KSZ device instance.
1530 * @speed: The desired link speed.
1531 * @duplex: The desired duplex mode.
1532 * @tx_pause: If true, enables transmit pause.
1533 * @rx_pause: If true, enables receive pause.
1534 *
1535 * Description:
1536 * The function configures flow control and speed settings for the CPU
1537 * port of the switch based on the desired settings, current duplex mode, and
1538 * speed.
1539 */
1540static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex,
1541 bool tx_pause, bool rx_pause)
1542{
1543 const u16 *regs = dev->info->regs;
1544 u8 ctrl = 0;
1545
1546 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable
1547 * at least on KSZ8873. They can have different values depending on your
1548 * board setup.
1549 */
1550 if (tx_pause || rx_pause)
1551 ctrl |= SW_FLOW_CTRL;
1552
1553 if (duplex == DUPLEX_HALF)
1554 ctrl |= SW_HALF_DUPLEX;
1555
1556 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10
1557 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.
1558 */
1559 if (speed == SPEED_10)
1560 ctrl |= SW_10_MBIT;
1561
1562 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL |
1563 SW_10_MBIT, ctrl);
1564}
1565
1566void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port,
1567 unsigned int mode, phy_interface_t interface,
1568 struct phy_device *phydev, int speed, int duplex,
1569 bool tx_pause, bool rx_pause)
1570{
1571 /* If the port is the CPU port, apply special handling. Only the CPU
1572 * port is configured via global registers.
1573 */
1574 if (dev->cpu_port == port)
1575 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
1576 else if (dev->info->internal_phy[port])
1577 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause);
1578}
1579
1580static int ksz8_handle_global_errata(struct dsa_switch *ds)
1581{
1582 struct ksz_device *dev = ds->priv;
1583 int ret = 0;
1584
1585 /* KSZ87xx Errata DS80000687C.
1586 * Module 2: Link drops with some EEE link partners.
1587 * An issue with the EEE next page exchange between the
1588 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in
1589 * the link dropping.
1590 */
1591 if (dev->info->ksz87xx_eee_link_erratum)
1592 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0);
1593
1594 return ret;
1595}
1596
1597int ksz8_enable_stp_addr(struct ksz_device *dev)
1598{
1599 struct alu_struct alu;
1600
1601 /* Setup STP address for STP operation. */
1602 memset(&alu, 0, sizeof(alu));
1603 ether_addr_copy(alu.mac, eth_stp_addr);
1604 alu.is_static = true;
1605 alu.is_override = true;
1606 alu.port_forward = dev->info->cpu_ports;
1607
1608 return ksz8_w_sta_mac_table(dev, 0, &alu);
1609}
1610
1611int ksz8_setup(struct dsa_switch *ds)
1612{
1613 struct ksz_device *dev = ds->priv;
1614 int i;
1615
1616 ds->mtu_enforcement_ingress = true;
1617
1618 /* We rely on software untagging on the CPU port, so that we
1619 * can support both tagged and untagged VLANs
1620 */
1621 ds->untag_bridge_pvid = true;
1622
1623 /* VLAN filtering is partly controlled by the global VLAN
1624 * Enable flag
1625 */
1626 ds->vlan_filtering_is_global = true;
1627
1628 /* Enable automatic fast aging when link changed detected. */
1629 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1630
1631 /* Enable aggressive back off algorithm in half duplex mode. */
1632 regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_1,
1633 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1634
1635 /*
1636 * Make sure unicast VLAN boundary is set as default and
1637 * enable no excessive collision drop.
1638 */
1639 regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_2,
1640 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1641 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1642
1643 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1644
1645 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1646
1647 if (!ksz_is_ksz88x3(dev))
1648 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1649
1650 for (i = 0; i < (dev->info->num_vlans / 4); i++)
1651 ksz8_r_vlan_entries(dev, i);
1652
1653 return ksz8_handle_global_errata(ds);
1654}
1655
1656void ksz8_get_caps(struct ksz_device *dev, int port,
1657 struct phylink_config *config)
1658{
1659 config->mac_capabilities = MAC_10 | MAC_100;
1660
1661 /* Silicon Errata Sheet (DS80000830A):
1662 * "Port 1 does not respond to received flow control PAUSE frames"
1663 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
1664 * switches.
1665 */
1666 if (!ksz_is_ksz88x3(dev) || port)
1667 config->mac_capabilities |= MAC_SYM_PAUSE;
1668
1669 /* Asym pause is not supported on KSZ8863 and KSZ8873 */
1670 if (!ksz_is_ksz88x3(dev))
1671 config->mac_capabilities |= MAC_ASYM_PAUSE;
1672}
1673
1674u32 ksz8_get_port_addr(int port, int offset)
1675{
1676 return PORT_CTRL_ADDR(port, offset);
1677}
1678
1679int ksz8_switch_init(struct ksz_device *dev)
1680{
1681 dev->cpu_port = fls(dev->info->cpu_ports) - 1;
1682 dev->phy_port_cnt = dev->info->port_cnt - 1;
1683 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports;
1684
1685 return 0;
1686}
1687
1688void ksz8_switch_exit(struct ksz_device *dev)
1689{
1690 ksz8_reset_switch(dev);
1691}
1692
1693MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1694MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1695MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9#include <linux/delay.h>
10#include <linux/export.h>
11#include <linux/gpio.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/platform_data/microchip-ksz.h>
15#include <linux/phy.h>
16#include <linux/etherdevice.h>
17#include <linux/if_bridge.h>
18#include <net/dsa.h>
19#include <net/switchdev.h>
20
21#include "ksz_common.h"
22#include "ksz8795_reg.h"
23
24static const struct {
25 char string[ETH_GSTRING_LEN];
26} mib_names[TOTAL_SWITCH_COUNTER_NUM] = {
27 { "rx_hi" },
28 { "rx_undersize" },
29 { "rx_fragments" },
30 { "rx_oversize" },
31 { "rx_jabbers" },
32 { "rx_symbol_err" },
33 { "rx_crc_err" },
34 { "rx_align_err" },
35 { "rx_mac_ctrl" },
36 { "rx_pause" },
37 { "rx_bcast" },
38 { "rx_mcast" },
39 { "rx_ucast" },
40 { "rx_64_or_less" },
41 { "rx_65_127" },
42 { "rx_128_255" },
43 { "rx_256_511" },
44 { "rx_512_1023" },
45 { "rx_1024_1522" },
46 { "rx_1523_2000" },
47 { "rx_2001" },
48 { "tx_hi" },
49 { "tx_late_col" },
50 { "tx_pause" },
51 { "tx_bcast" },
52 { "tx_mcast" },
53 { "tx_ucast" },
54 { "tx_deferred" },
55 { "tx_total_col" },
56 { "tx_exc_col" },
57 { "tx_single_col" },
58 { "tx_mult_col" },
59 { "rx_total" },
60 { "tx_total" },
61 { "rx_discards" },
62 { "tx_discards" },
63};
64
65static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
66{
67 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
68}
69
70static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
71 bool set)
72{
73 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
74 bits, set ? bits : 0);
75}
76
77static int ksz8795_reset_switch(struct ksz_device *dev)
78{
79 /* reset switch */
80 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
81 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
82 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
83
84 return 0;
85}
86
87static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
88{
89 u8 hi, lo;
90
91 /* Number of queues can only be 1, 2, or 4. */
92 switch (queue) {
93 case 4:
94 case 3:
95 queue = PORT_QUEUE_SPLIT_4;
96 break;
97 case 2:
98 queue = PORT_QUEUE_SPLIT_2;
99 break;
100 default:
101 queue = PORT_QUEUE_SPLIT_1;
102 }
103 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
104 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
105 lo &= ~PORT_QUEUE_SPLIT_L;
106 if (queue & PORT_QUEUE_SPLIT_2)
107 lo |= PORT_QUEUE_SPLIT_L;
108 hi &= ~PORT_QUEUE_SPLIT_H;
109 if (queue & PORT_QUEUE_SPLIT_4)
110 hi |= PORT_QUEUE_SPLIT_H;
111 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
112 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
113
114 /* Default is port based for egress rate limit. */
115 if (queue != PORT_QUEUE_SPLIT_1)
116 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
117 true);
118}
119
120static void ksz8795_r_mib_cnt(struct ksz_device *dev, int port, u16 addr,
121 u64 *cnt)
122{
123 u16 ctrl_addr;
124 u32 data;
125 u8 check;
126 int loop;
127
128 ctrl_addr = addr + SWITCH_COUNTER_NUM * port;
129 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
130
131 mutex_lock(&dev->alu_mutex);
132 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
133
134 /* It is almost guaranteed to always read the valid bit because of
135 * slow SPI speed.
136 */
137 for (loop = 2; loop > 0; loop--) {
138 ksz_read8(dev, REG_IND_MIB_CHECK, &check);
139
140 if (check & MIB_COUNTER_VALID) {
141 ksz_read32(dev, REG_IND_DATA_LO, &data);
142 if (check & MIB_COUNTER_OVERFLOW)
143 *cnt += MIB_COUNTER_VALUE + 1;
144 *cnt += data & MIB_COUNTER_VALUE;
145 break;
146 }
147 }
148 mutex_unlock(&dev->alu_mutex);
149}
150
151static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
152 u64 *dropped, u64 *cnt)
153{
154 u16 ctrl_addr;
155 u32 data;
156 u8 check;
157 int loop;
158
159 addr -= SWITCH_COUNTER_NUM;
160 ctrl_addr = (KS_MIB_TOTAL_RX_1 - KS_MIB_TOTAL_RX_0) * port;
161 ctrl_addr += addr + KS_MIB_TOTAL_RX_0;
162 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
163
164 mutex_lock(&dev->alu_mutex);
165 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
166
167 /* It is almost guaranteed to always read the valid bit because of
168 * slow SPI speed.
169 */
170 for (loop = 2; loop > 0; loop--) {
171 ksz_read8(dev, REG_IND_MIB_CHECK, &check);
172
173 if (check & MIB_COUNTER_VALID) {
174 ksz_read32(dev, REG_IND_DATA_LO, &data);
175 if (addr < 2) {
176 u64 total;
177
178 total = check & MIB_TOTAL_BYTES_H;
179 total <<= 32;
180 *cnt += total;
181 *cnt += data;
182 if (check & MIB_COUNTER_OVERFLOW) {
183 total = MIB_TOTAL_BYTES_H + 1;
184 total <<= 32;
185 *cnt += total;
186 }
187 } else {
188 if (check & MIB_COUNTER_OVERFLOW)
189 *cnt += MIB_PACKET_DROPPED + 1;
190 *cnt += data & MIB_PACKET_DROPPED;
191 }
192 break;
193 }
194 }
195 mutex_unlock(&dev->alu_mutex);
196}
197
198static void ksz8795_freeze_mib(struct ksz_device *dev, int port, bool freeze)
199{
200 /* enable the port for flush/freeze function */
201 if (freeze)
202 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
203 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
204
205 /* disable the port after freeze is done */
206 if (!freeze)
207 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
208}
209
210static void ksz8795_port_init_cnt(struct ksz_device *dev, int port)
211{
212 struct ksz_port_mib *mib = &dev->ports[port].mib;
213
214 /* flush all enabled port MIB counters */
215 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
216 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
217 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
218
219 mib->cnt_ptr = 0;
220
221 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
222 while (mib->cnt_ptr < dev->reg_mib_cnt) {
223 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
224 &mib->counters[mib->cnt_ptr]);
225 ++mib->cnt_ptr;
226 }
227
228 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
229 while (mib->cnt_ptr < dev->mib_cnt) {
230 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
231 NULL, &mib->counters[mib->cnt_ptr]);
232 ++mib->cnt_ptr;
233 }
234 mib->cnt_ptr = 0;
235 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
236}
237
238static void ksz8795_r_table(struct ksz_device *dev, int table, u16 addr,
239 u64 *data)
240{
241 u16 ctrl_addr;
242
243 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
244
245 mutex_lock(&dev->alu_mutex);
246 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
247 ksz_read64(dev, REG_IND_DATA_HI, data);
248 mutex_unlock(&dev->alu_mutex);
249}
250
251static void ksz8795_w_table(struct ksz_device *dev, int table, u16 addr,
252 u64 data)
253{
254 u16 ctrl_addr;
255
256 ctrl_addr = IND_ACC_TABLE(table) | addr;
257
258 mutex_lock(&dev->alu_mutex);
259 ksz_write64(dev, REG_IND_DATA_HI, data);
260 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
261 mutex_unlock(&dev->alu_mutex);
262}
263
264static int ksz8795_valid_dyn_entry(struct ksz_device *dev, u8 *data)
265{
266 int timeout = 100;
267
268 do {
269 ksz_read8(dev, REG_IND_DATA_CHECK, data);
270 timeout--;
271 } while ((*data & DYNAMIC_MAC_TABLE_NOT_READY) && timeout);
272
273 /* Entry is not ready for accessing. */
274 if (*data & DYNAMIC_MAC_TABLE_NOT_READY) {
275 return -EAGAIN;
276 /* Entry is ready for accessing. */
277 } else {
278 ksz_read8(dev, REG_IND_DATA_8, data);
279
280 /* There is no valid entry in the table. */
281 if (*data & DYNAMIC_MAC_TABLE_MAC_EMPTY)
282 return -ENXIO;
283 }
284 return 0;
285}
286
287static int ksz8795_r_dyn_mac_table(struct ksz_device *dev, u16 addr,
288 u8 *mac_addr, u8 *fid, u8 *src_port,
289 u8 *timestamp, u16 *entries)
290{
291 u32 data_hi, data_lo;
292 u16 ctrl_addr;
293 u8 data;
294 int rc;
295
296 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
297
298 mutex_lock(&dev->alu_mutex);
299 ksz_write16(dev, REG_IND_CTRL_0, ctrl_addr);
300
301 rc = ksz8795_valid_dyn_entry(dev, &data);
302 if (rc == -EAGAIN) {
303 if (addr == 0)
304 *entries = 0;
305 } else if (rc == -ENXIO) {
306 *entries = 0;
307 /* At least one valid entry in the table. */
308 } else {
309 u64 buf = 0;
310 int cnt;
311
312 ksz_read64(dev, REG_IND_DATA_HI, &buf);
313 data_hi = (u32)(buf >> 32);
314 data_lo = (u32)buf;
315
316 /* Check out how many valid entry in the table. */
317 cnt = data & DYNAMIC_MAC_TABLE_ENTRIES_H;
318 cnt <<= DYNAMIC_MAC_ENTRIES_H_S;
319 cnt |= (data_hi & DYNAMIC_MAC_TABLE_ENTRIES) >>
320 DYNAMIC_MAC_ENTRIES_S;
321 *entries = cnt + 1;
322
323 *fid = (data_hi & DYNAMIC_MAC_TABLE_FID) >>
324 DYNAMIC_MAC_FID_S;
325 *src_port = (data_hi & DYNAMIC_MAC_TABLE_SRC_PORT) >>
326 DYNAMIC_MAC_SRC_PORT_S;
327 *timestamp = (data_hi & DYNAMIC_MAC_TABLE_TIMESTAMP) >>
328 DYNAMIC_MAC_TIMESTAMP_S;
329
330 mac_addr[5] = (u8)data_lo;
331 mac_addr[4] = (u8)(data_lo >> 8);
332 mac_addr[3] = (u8)(data_lo >> 16);
333 mac_addr[2] = (u8)(data_lo >> 24);
334
335 mac_addr[1] = (u8)data_hi;
336 mac_addr[0] = (u8)(data_hi >> 8);
337 rc = 0;
338 }
339 mutex_unlock(&dev->alu_mutex);
340
341 return rc;
342}
343
344static int ksz8795_r_sta_mac_table(struct ksz_device *dev, u16 addr,
345 struct alu_struct *alu)
346{
347 u32 data_hi, data_lo;
348 u64 data;
349
350 ksz8795_r_table(dev, TABLE_STATIC_MAC, addr, &data);
351 data_hi = data >> 32;
352 data_lo = (u32)data;
353 if (data_hi & (STATIC_MAC_TABLE_VALID | STATIC_MAC_TABLE_OVERRIDE)) {
354 alu->mac[5] = (u8)data_lo;
355 alu->mac[4] = (u8)(data_lo >> 8);
356 alu->mac[3] = (u8)(data_lo >> 16);
357 alu->mac[2] = (u8)(data_lo >> 24);
358 alu->mac[1] = (u8)data_hi;
359 alu->mac[0] = (u8)(data_hi >> 8);
360 alu->port_forward = (data_hi & STATIC_MAC_TABLE_FWD_PORTS) >>
361 STATIC_MAC_FWD_PORTS_S;
362 alu->is_override =
363 (data_hi & STATIC_MAC_TABLE_OVERRIDE) ? 1 : 0;
364 data_hi >>= 1;
365 alu->is_use_fid = (data_hi & STATIC_MAC_TABLE_USE_FID) ? 1 : 0;
366 alu->fid = (data_hi & STATIC_MAC_TABLE_FID) >>
367 STATIC_MAC_FID_S;
368 return 0;
369 }
370 return -ENXIO;
371}
372
373static void ksz8795_w_sta_mac_table(struct ksz_device *dev, u16 addr,
374 struct alu_struct *alu)
375{
376 u32 data_hi, data_lo;
377 u64 data;
378
379 data_lo = ((u32)alu->mac[2] << 24) |
380 ((u32)alu->mac[3] << 16) |
381 ((u32)alu->mac[4] << 8) | alu->mac[5];
382 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
383 data_hi |= (u32)alu->port_forward << STATIC_MAC_FWD_PORTS_S;
384
385 if (alu->is_override)
386 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
387 if (alu->is_use_fid) {
388 data_hi |= STATIC_MAC_TABLE_USE_FID;
389 data_hi |= (u32)alu->fid << STATIC_MAC_FID_S;
390 }
391 if (alu->is_static)
392 data_hi |= STATIC_MAC_TABLE_VALID;
393 else
394 data_hi &= ~STATIC_MAC_TABLE_OVERRIDE;
395
396 data = (u64)data_hi << 32 | data_lo;
397 ksz8795_w_table(dev, TABLE_STATIC_MAC, addr, data);
398}
399
400static void ksz8795_from_vlan(u16 vlan, u8 *fid, u8 *member, u8 *valid)
401{
402 *fid = vlan & VLAN_TABLE_FID;
403 *member = (vlan & VLAN_TABLE_MEMBERSHIP) >> VLAN_TABLE_MEMBERSHIP_S;
404 *valid = !!(vlan & VLAN_TABLE_VALID);
405}
406
407static void ksz8795_to_vlan(u8 fid, u8 member, u8 valid, u16 *vlan)
408{
409 *vlan = fid;
410 *vlan |= (u16)member << VLAN_TABLE_MEMBERSHIP_S;
411 if (valid)
412 *vlan |= VLAN_TABLE_VALID;
413}
414
415static void ksz8795_r_vlan_entries(struct ksz_device *dev, u16 addr)
416{
417 u64 data;
418 int i;
419
420 ksz8795_r_table(dev, TABLE_VLAN, addr, &data);
421 addr *= 4;
422 for (i = 0; i < 4; i++) {
423 dev->vlan_cache[addr + i].table[0] = (u16)data;
424 data >>= VLAN_TABLE_S;
425 }
426}
427
428static void ksz8795_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
429{
430 int index;
431 u16 *data;
432 u16 addr;
433 u64 buf;
434
435 data = (u16 *)&buf;
436 addr = vid / 4;
437 index = vid & 3;
438 ksz8795_r_table(dev, TABLE_VLAN, addr, &buf);
439 *vlan = data[index];
440}
441
442static void ksz8795_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
443{
444 int index;
445 u16 *data;
446 u16 addr;
447 u64 buf;
448
449 data = (u16 *)&buf;
450 addr = vid / 4;
451 index = vid & 3;
452 ksz8795_r_table(dev, TABLE_VLAN, addr, &buf);
453 data[index] = vlan;
454 dev->vlan_cache[vid].table[0] = vlan;
455 ksz8795_w_table(dev, TABLE_VLAN, addr, buf);
456}
457
458static void ksz8795_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
459{
460 u8 restart, speed, ctrl, link;
461 int processed = true;
462 u16 data = 0;
463 u8 p = phy;
464
465 switch (reg) {
466 case PHY_REG_CTRL:
467 ksz_pread8(dev, p, P_NEG_RESTART_CTRL, &restart);
468 ksz_pread8(dev, p, P_SPEED_STATUS, &speed);
469 ksz_pread8(dev, p, P_FORCE_CTRL, &ctrl);
470 if (restart & PORT_PHY_LOOPBACK)
471 data |= PHY_LOOPBACK;
472 if (ctrl & PORT_FORCE_100_MBIT)
473 data |= PHY_SPEED_100MBIT;
474 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
475 data |= PHY_AUTO_NEG_ENABLE;
476 if (restart & PORT_POWER_DOWN)
477 data |= PHY_POWER_DOWN;
478 if (restart & PORT_AUTO_NEG_RESTART)
479 data |= PHY_AUTO_NEG_RESTART;
480 if (ctrl & PORT_FORCE_FULL_DUPLEX)
481 data |= PHY_FULL_DUPLEX;
482 if (speed & PORT_HP_MDIX)
483 data |= PHY_HP_MDIX;
484 if (restart & PORT_FORCE_MDIX)
485 data |= PHY_FORCE_MDIX;
486 if (restart & PORT_AUTO_MDIX_DISABLE)
487 data |= PHY_AUTO_MDIX_DISABLE;
488 if (restart & PORT_TX_DISABLE)
489 data |= PHY_TRANSMIT_DISABLE;
490 if (restart & PORT_LED_OFF)
491 data |= PHY_LED_DISABLE;
492 break;
493 case PHY_REG_STATUS:
494 ksz_pread8(dev, p, P_LINK_STATUS, &link);
495 data = PHY_100BTX_FD_CAPABLE |
496 PHY_100BTX_CAPABLE |
497 PHY_10BT_FD_CAPABLE |
498 PHY_10BT_CAPABLE |
499 PHY_AUTO_NEG_CAPABLE;
500 if (link & PORT_AUTO_NEG_COMPLETE)
501 data |= PHY_AUTO_NEG_ACKNOWLEDGE;
502 if (link & PORT_STAT_LINK_GOOD)
503 data |= PHY_LINK_STATUS;
504 break;
505 case PHY_REG_ID_1:
506 data = KSZ8795_ID_HI;
507 break;
508 case PHY_REG_ID_2:
509 data = KSZ8795_ID_LO;
510 break;
511 case PHY_REG_AUTO_NEGOTIATION:
512 ksz_pread8(dev, p, P_LOCAL_CTRL, &ctrl);
513 data = PHY_AUTO_NEG_802_3;
514 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
515 data |= PHY_AUTO_NEG_SYM_PAUSE;
516 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
517 data |= PHY_AUTO_NEG_100BTX_FD;
518 if (ctrl & PORT_AUTO_NEG_100BTX)
519 data |= PHY_AUTO_NEG_100BTX;
520 if (ctrl & PORT_AUTO_NEG_10BT_FD)
521 data |= PHY_AUTO_NEG_10BT_FD;
522 if (ctrl & PORT_AUTO_NEG_10BT)
523 data |= PHY_AUTO_NEG_10BT;
524 break;
525 case PHY_REG_REMOTE_CAPABILITY:
526 ksz_pread8(dev, p, P_REMOTE_STATUS, &link);
527 data = PHY_AUTO_NEG_802_3;
528 if (link & PORT_REMOTE_SYM_PAUSE)
529 data |= PHY_AUTO_NEG_SYM_PAUSE;
530 if (link & PORT_REMOTE_100BTX_FD)
531 data |= PHY_AUTO_NEG_100BTX_FD;
532 if (link & PORT_REMOTE_100BTX)
533 data |= PHY_AUTO_NEG_100BTX;
534 if (link & PORT_REMOTE_10BT_FD)
535 data |= PHY_AUTO_NEG_10BT_FD;
536 if (link & PORT_REMOTE_10BT)
537 data |= PHY_AUTO_NEG_10BT;
538 if (data & ~PHY_AUTO_NEG_802_3)
539 data |= PHY_REMOTE_ACKNOWLEDGE_NOT;
540 break;
541 default:
542 processed = false;
543 break;
544 }
545 if (processed)
546 *val = data;
547}
548
549static void ksz8795_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
550{
551 u8 p = phy;
552 u8 restart, speed, ctrl, data;
553
554 switch (reg) {
555 case PHY_REG_CTRL:
556
557 /* Do not support PHY reset function. */
558 if (val & PHY_RESET)
559 break;
560 ksz_pread8(dev, p, P_SPEED_STATUS, &speed);
561 data = speed;
562 if (val & PHY_HP_MDIX)
563 data |= PORT_HP_MDIX;
564 else
565 data &= ~PORT_HP_MDIX;
566 if (data != speed)
567 ksz_pwrite8(dev, p, P_SPEED_STATUS, data);
568 ksz_pread8(dev, p, P_FORCE_CTRL, &ctrl);
569 data = ctrl;
570 if (!(val & PHY_AUTO_NEG_ENABLE))
571 data |= PORT_AUTO_NEG_DISABLE;
572 else
573 data &= ~PORT_AUTO_NEG_DISABLE;
574
575 /* Fiber port does not support auto-negotiation. */
576 if (dev->ports[p].fiber)
577 data |= PORT_AUTO_NEG_DISABLE;
578 if (val & PHY_SPEED_100MBIT)
579 data |= PORT_FORCE_100_MBIT;
580 else
581 data &= ~PORT_FORCE_100_MBIT;
582 if (val & PHY_FULL_DUPLEX)
583 data |= PORT_FORCE_FULL_DUPLEX;
584 else
585 data &= ~PORT_FORCE_FULL_DUPLEX;
586 if (data != ctrl)
587 ksz_pwrite8(dev, p, P_FORCE_CTRL, data);
588 ksz_pread8(dev, p, P_NEG_RESTART_CTRL, &restart);
589 data = restart;
590 if (val & PHY_LED_DISABLE)
591 data |= PORT_LED_OFF;
592 else
593 data &= ~PORT_LED_OFF;
594 if (val & PHY_TRANSMIT_DISABLE)
595 data |= PORT_TX_DISABLE;
596 else
597 data &= ~PORT_TX_DISABLE;
598 if (val & PHY_AUTO_NEG_RESTART)
599 data |= PORT_AUTO_NEG_RESTART;
600 else
601 data &= ~(PORT_AUTO_NEG_RESTART);
602 if (val & PHY_POWER_DOWN)
603 data |= PORT_POWER_DOWN;
604 else
605 data &= ~PORT_POWER_DOWN;
606 if (val & PHY_AUTO_MDIX_DISABLE)
607 data |= PORT_AUTO_MDIX_DISABLE;
608 else
609 data &= ~PORT_AUTO_MDIX_DISABLE;
610 if (val & PHY_FORCE_MDIX)
611 data |= PORT_FORCE_MDIX;
612 else
613 data &= ~PORT_FORCE_MDIX;
614 if (val & PHY_LOOPBACK)
615 data |= PORT_PHY_LOOPBACK;
616 else
617 data &= ~PORT_PHY_LOOPBACK;
618 if (data != restart)
619 ksz_pwrite8(dev, p, P_NEG_RESTART_CTRL, data);
620 break;
621 case PHY_REG_AUTO_NEGOTIATION:
622 ksz_pread8(dev, p, P_LOCAL_CTRL, &ctrl);
623 data = ctrl;
624 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
625 PORT_AUTO_NEG_100BTX_FD |
626 PORT_AUTO_NEG_100BTX |
627 PORT_AUTO_NEG_10BT_FD |
628 PORT_AUTO_NEG_10BT);
629 if (val & PHY_AUTO_NEG_SYM_PAUSE)
630 data |= PORT_AUTO_NEG_SYM_PAUSE;
631 if (val & PHY_AUTO_NEG_100BTX_FD)
632 data |= PORT_AUTO_NEG_100BTX_FD;
633 if (val & PHY_AUTO_NEG_100BTX)
634 data |= PORT_AUTO_NEG_100BTX;
635 if (val & PHY_AUTO_NEG_10BT_FD)
636 data |= PORT_AUTO_NEG_10BT_FD;
637 if (val & PHY_AUTO_NEG_10BT)
638 data |= PORT_AUTO_NEG_10BT;
639 if (data != ctrl)
640 ksz_pwrite8(dev, p, P_LOCAL_CTRL, data);
641 break;
642 default:
643 break;
644 }
645}
646
647static enum dsa_tag_protocol ksz8795_get_tag_protocol(struct dsa_switch *ds,
648 int port,
649 enum dsa_tag_protocol mp)
650{
651 return DSA_TAG_PROTO_KSZ8795;
652}
653
654static void ksz8795_get_strings(struct dsa_switch *ds, int port,
655 u32 stringset, uint8_t *buf)
656{
657 int i;
658
659 for (i = 0; i < TOTAL_SWITCH_COUNTER_NUM; i++) {
660 memcpy(buf + i * ETH_GSTRING_LEN, mib_names[i].string,
661 ETH_GSTRING_LEN);
662 }
663}
664
665static void ksz8795_cfg_port_member(struct ksz_device *dev, int port,
666 u8 member)
667{
668 u8 data;
669
670 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
671 data &= ~PORT_VLAN_MEMBERSHIP;
672 data |= (member & dev->port_mask);
673 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
674 dev->ports[port].member = member;
675}
676
677static void ksz8795_port_stp_state_set(struct dsa_switch *ds, int port,
678 u8 state)
679{
680 struct ksz_device *dev = ds->priv;
681 int forward = dev->member;
682 struct ksz_port *p;
683 int member = -1;
684 u8 data;
685
686 p = &dev->ports[port];
687
688 ksz_pread8(dev, port, P_STP_CTRL, &data);
689 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
690
691 switch (state) {
692 case BR_STATE_DISABLED:
693 data |= PORT_LEARN_DISABLE;
694 if (port < SWITCH_PORT_NUM)
695 member = 0;
696 break;
697 case BR_STATE_LISTENING:
698 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
699 if (port < SWITCH_PORT_NUM &&
700 p->stp_state == BR_STATE_DISABLED)
701 member = dev->host_mask | p->vid_member;
702 break;
703 case BR_STATE_LEARNING:
704 data |= PORT_RX_ENABLE;
705 break;
706 case BR_STATE_FORWARDING:
707 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
708
709 /* This function is also used internally. */
710 if (port == dev->cpu_port)
711 break;
712
713 /* Port is a member of a bridge. */
714 if (dev->br_member & BIT(port)) {
715 dev->member |= BIT(port);
716 member = dev->member;
717 } else {
718 member = dev->host_mask | p->vid_member;
719 }
720 break;
721 case BR_STATE_BLOCKING:
722 data |= PORT_LEARN_DISABLE;
723 if (port < SWITCH_PORT_NUM &&
724 p->stp_state == BR_STATE_DISABLED)
725 member = dev->host_mask | p->vid_member;
726 break;
727 default:
728 dev_err(ds->dev, "invalid STP state: %d\n", state);
729 return;
730 }
731
732 ksz_pwrite8(dev, port, P_STP_CTRL, data);
733 p->stp_state = state;
734 /* Port membership may share register with STP state. */
735 if (member >= 0 && member != p->member)
736 ksz8795_cfg_port_member(dev, port, (u8)member);
737
738 /* Check if forwarding needs to be updated. */
739 if (state != BR_STATE_FORWARDING) {
740 if (dev->br_member & BIT(port))
741 dev->member &= ~BIT(port);
742 }
743
744 /* When topology has changed the function ksz_update_port_member
745 * should be called to modify port forwarding behavior.
746 */
747 if (forward != dev->member)
748 ksz_update_port_member(dev, port);
749}
750
751static void ksz8795_flush_dyn_mac_table(struct ksz_device *dev, int port)
752{
753 u8 learn[TOTAL_PORT_NUM];
754 int first, index, cnt;
755 struct ksz_port *p;
756
757 if ((uint)port < TOTAL_PORT_NUM) {
758 first = port;
759 cnt = port + 1;
760 } else {
761 /* Flush all ports. */
762 first = 0;
763 cnt = dev->mib_port_cnt;
764 }
765 for (index = first; index < cnt; index++) {
766 p = &dev->ports[index];
767 if (!p->on)
768 continue;
769 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]);
770 if (!(learn[index] & PORT_LEARN_DISABLE))
771 ksz_pwrite8(dev, index, P_STP_CTRL,
772 learn[index] | PORT_LEARN_DISABLE);
773 }
774 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
775 for (index = first; index < cnt; index++) {
776 p = &dev->ports[index];
777 if (!p->on)
778 continue;
779 if (!(learn[index] & PORT_LEARN_DISABLE))
780 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]);
781 }
782}
783
784static int ksz8795_port_vlan_filtering(struct dsa_switch *ds, int port,
785 bool flag)
786{
787 struct ksz_device *dev = ds->priv;
788
789 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
790
791 return 0;
792}
793
794static void ksz8795_port_vlan_add(struct dsa_switch *ds, int port,
795 const struct switchdev_obj_port_vlan *vlan)
796{
797 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
798 struct ksz_device *dev = ds->priv;
799 u16 data, vid, new_pvid = 0;
800 u8 fid, member, valid;
801
802 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
803
804 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
805 ksz8795_r_vlan_table(dev, vid, &data);
806 ksz8795_from_vlan(data, &fid, &member, &valid);
807
808 /* First time to setup the VLAN entry. */
809 if (!valid) {
810 /* Need to find a way to map VID to FID. */
811 fid = 1;
812 valid = 1;
813 }
814 member |= BIT(port);
815
816 ksz8795_to_vlan(fid, member, valid, &data);
817 ksz8795_w_vlan_table(dev, vid, data);
818
819 /* change PVID */
820 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
821 new_pvid = vid;
822 }
823
824 if (new_pvid) {
825 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
826 vid &= 0xfff;
827 vid |= new_pvid;
828 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
829 }
830}
831
832static int ksz8795_port_vlan_del(struct dsa_switch *ds, int port,
833 const struct switchdev_obj_port_vlan *vlan)
834{
835 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
836 struct ksz_device *dev = ds->priv;
837 u16 data, vid, pvid, new_pvid = 0;
838 u8 fid, member, valid;
839
840 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
841 pvid = pvid & 0xFFF;
842
843 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
844
845 for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
846 ksz8795_r_vlan_table(dev, vid, &data);
847 ksz8795_from_vlan(data, &fid, &member, &valid);
848
849 member &= ~BIT(port);
850
851 /* Invalidate the entry if no more member. */
852 if (!member) {
853 fid = 0;
854 valid = 0;
855 }
856
857 if (pvid == vid)
858 new_pvid = 1;
859
860 ksz8795_to_vlan(fid, member, valid, &data);
861 ksz8795_w_vlan_table(dev, vid, data);
862 }
863
864 if (new_pvid != pvid)
865 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, pvid);
866
867 return 0;
868}
869
870static int ksz8795_port_mirror_add(struct dsa_switch *ds, int port,
871 struct dsa_mall_mirror_tc_entry *mirror,
872 bool ingress)
873{
874 struct ksz_device *dev = ds->priv;
875
876 if (ingress) {
877 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
878 dev->mirror_rx |= BIT(port);
879 } else {
880 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
881 dev->mirror_tx |= BIT(port);
882 }
883
884 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
885
886 /* configure mirror port */
887 if (dev->mirror_rx || dev->mirror_tx)
888 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
889 PORT_MIRROR_SNIFFER, true);
890
891 return 0;
892}
893
894static void ksz8795_port_mirror_del(struct dsa_switch *ds, int port,
895 struct dsa_mall_mirror_tc_entry *mirror)
896{
897 struct ksz_device *dev = ds->priv;
898 u8 data;
899
900 if (mirror->ingress) {
901 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
902 dev->mirror_rx &= ~BIT(port);
903 } else {
904 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
905 dev->mirror_tx &= ~BIT(port);
906 }
907
908 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
909
910 if (!dev->mirror_rx && !dev->mirror_tx)
911 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
912 PORT_MIRROR_SNIFFER, false);
913}
914
915static void ksz8795_port_setup(struct ksz_device *dev, int port, bool cpu_port)
916{
917 struct ksz_port *p = &dev->ports[port];
918 u8 data8, member;
919
920 /* enable broadcast storm limit */
921 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
922
923 ksz8795_set_prio_queue(dev, port, 4);
924
925 /* disable DiffServ priority */
926 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
927
928 /* replace priority */
929 ksz_port_cfg(dev, port, P_802_1P_CTRL, PORT_802_1P_REMAPPING, false);
930
931 /* enable 802.1p priority */
932 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
933
934 if (cpu_port) {
935 if (!p->interface && dev->compat_interface) {
936 dev_warn(dev->dev,
937 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
938 "Please update your device tree.\n",
939 port);
940 p->interface = dev->compat_interface;
941 }
942
943 /* Configure MII interface for proper network communication. */
944 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
945 data8 &= ~PORT_INTERFACE_TYPE;
946 data8 &= ~PORT_GMII_1GPS_MODE;
947 switch (p->interface) {
948 case PHY_INTERFACE_MODE_MII:
949 p->phydev.speed = SPEED_100;
950 break;
951 case PHY_INTERFACE_MODE_RMII:
952 data8 |= PORT_INTERFACE_RMII;
953 p->phydev.speed = SPEED_100;
954 break;
955 case PHY_INTERFACE_MODE_GMII:
956 data8 |= PORT_GMII_1GPS_MODE;
957 data8 |= PORT_INTERFACE_GMII;
958 p->phydev.speed = SPEED_1000;
959 break;
960 default:
961 data8 &= ~PORT_RGMII_ID_IN_ENABLE;
962 data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
963 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
964 p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
965 data8 |= PORT_RGMII_ID_IN_ENABLE;
966 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
967 p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
968 data8 |= PORT_RGMII_ID_OUT_ENABLE;
969 data8 |= PORT_GMII_1GPS_MODE;
970 data8 |= PORT_INTERFACE_RGMII;
971 p->phydev.speed = SPEED_1000;
972 break;
973 }
974 ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
975 p->phydev.duplex = 1;
976
977 member = dev->port_mask;
978 } else {
979 member = dev->host_mask | p->vid_member;
980 }
981 ksz8795_cfg_port_member(dev, port, member);
982}
983
984static void ksz8795_config_cpu_port(struct dsa_switch *ds)
985{
986 struct ksz_device *dev = ds->priv;
987 struct ksz_port *p;
988 u8 remote;
989 int i;
990
991 ds->num_ports = dev->port_cnt + 1;
992
993 /* Switch marks the maximum frame with extra byte as oversize. */
994 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
995 ksz_cfg(dev, S_TAIL_TAG_CTRL, SW_TAIL_TAG_ENABLE, true);
996
997 p = &dev->ports[dev->cpu_port];
998 p->vid_member = dev->port_mask;
999 p->on = 1;
1000
1001 ksz8795_port_setup(dev, dev->cpu_port, true);
1002 dev->member = dev->host_mask;
1003
1004 for (i = 0; i < SWITCH_PORT_NUM; i++) {
1005 p = &dev->ports[i];
1006
1007 /* Initialize to non-zero so that ksz_cfg_port_member() will
1008 * be called.
1009 */
1010 p->vid_member = BIT(i);
1011 p->member = dev->port_mask;
1012 ksz8795_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1013
1014 /* Last port may be disabled. */
1015 if (i == dev->port_cnt)
1016 break;
1017 p->on = 1;
1018 p->phy = 1;
1019 }
1020 for (i = 0; i < dev->phy_port_cnt; i++) {
1021 p = &dev->ports[i];
1022 if (!p->on)
1023 continue;
1024 ksz_pread8(dev, i, P_REMOTE_STATUS, &remote);
1025 if (remote & PORT_FIBER_MODE)
1026 p->fiber = 1;
1027 if (p->fiber)
1028 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1029 true);
1030 else
1031 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1032 false);
1033 }
1034}
1035
1036static int ksz8795_setup(struct dsa_switch *ds)
1037{
1038 struct ksz_device *dev = ds->priv;
1039 struct alu_struct alu;
1040 int i, ret = 0;
1041
1042 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1043 dev->num_vlans, GFP_KERNEL);
1044 if (!dev->vlan_cache)
1045 return -ENOMEM;
1046
1047 ret = ksz8795_reset_switch(dev);
1048 if (ret) {
1049 dev_err(ds->dev, "failed to reset switch\n");
1050 return ret;
1051 }
1052
1053 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
1054
1055 /* Enable automatic fast aging when link changed detected. */
1056 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1057
1058 /* Enable aggressive back off algorithm in half duplex mode. */
1059 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1,
1060 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1061
1062 /*
1063 * Make sure unicast VLAN boundary is set as default and
1064 * enable no excessive collision drop.
1065 */
1066 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2,
1067 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1068 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1069
1070 ksz8795_config_cpu_port(ds);
1071
1072 ksz_cfg(dev, REG_SW_CTRL_2, MULTICAST_STORM_DISABLE, true);
1073
1074 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1075
1076 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1077
1078 /* set broadcast storm protection 10% rate */
1079 regmap_update_bits(dev->regmap[1], S_REPLACE_VID_CTRL,
1080 BROADCAST_STORM_RATE,
1081 (BROADCAST_STORM_VALUE *
1082 BROADCAST_STORM_PROT_RATE) / 100);
1083
1084 for (i = 0; i < VLAN_TABLE_ENTRIES; i++)
1085 ksz8795_r_vlan_entries(dev, i);
1086
1087 /* Setup STP address for STP operation. */
1088 memset(&alu, 0, sizeof(alu));
1089 ether_addr_copy(alu.mac, eth_stp_addr);
1090 alu.is_static = true;
1091 alu.is_override = true;
1092 alu.port_forward = dev->host_mask;
1093
1094 ksz8795_w_sta_mac_table(dev, 0, &alu);
1095
1096 ksz_init_mib_timer(dev);
1097
1098 return 0;
1099}
1100
1101static const struct dsa_switch_ops ksz8795_switch_ops = {
1102 .get_tag_protocol = ksz8795_get_tag_protocol,
1103 .setup = ksz8795_setup,
1104 .phy_read = ksz_phy_read16,
1105 .phy_write = ksz_phy_write16,
1106 .phylink_mac_link_down = ksz_mac_link_down,
1107 .port_enable = ksz_enable_port,
1108 .get_strings = ksz8795_get_strings,
1109 .get_ethtool_stats = ksz_get_ethtool_stats,
1110 .get_sset_count = ksz_sset_count,
1111 .port_bridge_join = ksz_port_bridge_join,
1112 .port_bridge_leave = ksz_port_bridge_leave,
1113 .port_stp_state_set = ksz8795_port_stp_state_set,
1114 .port_fast_age = ksz_port_fast_age,
1115 .port_vlan_filtering = ksz8795_port_vlan_filtering,
1116 .port_vlan_prepare = ksz_port_vlan_prepare,
1117 .port_vlan_add = ksz8795_port_vlan_add,
1118 .port_vlan_del = ksz8795_port_vlan_del,
1119 .port_fdb_dump = ksz_port_fdb_dump,
1120 .port_mdb_prepare = ksz_port_mdb_prepare,
1121 .port_mdb_add = ksz_port_mdb_add,
1122 .port_mdb_del = ksz_port_mdb_del,
1123 .port_mirror_add = ksz8795_port_mirror_add,
1124 .port_mirror_del = ksz8795_port_mirror_del,
1125};
1126
1127static u32 ksz8795_get_port_addr(int port, int offset)
1128{
1129 return PORT_CTRL_ADDR(port, offset);
1130}
1131
1132static int ksz8795_switch_detect(struct ksz_device *dev)
1133{
1134 u8 id1, id2;
1135 u16 id16;
1136 int ret;
1137
1138 /* read chip id */
1139 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
1140 if (ret)
1141 return ret;
1142
1143 id1 = id16 >> 8;
1144 id2 = id16 & SW_CHIP_ID_M;
1145 if (id1 != FAMILY_ID ||
1146 (id2 != CHIP_ID_94 && id2 != CHIP_ID_95))
1147 return -ENODEV;
1148
1149 dev->mib_port_cnt = TOTAL_PORT_NUM;
1150 dev->phy_port_cnt = SWITCH_PORT_NUM;
1151 dev->port_cnt = SWITCH_PORT_NUM;
1152
1153 if (id2 == CHIP_ID_95) {
1154 u8 val;
1155
1156 id2 = 0x95;
1157 ksz_read8(dev, REG_PORT_1_STATUS_0, &val);
1158 if (val & PORT_FIBER_MODE)
1159 id2 = 0x65;
1160 } else if (id2 == CHIP_ID_94) {
1161 dev->port_cnt--;
1162 dev->last_port = dev->port_cnt;
1163 id2 = 0x94;
1164 }
1165 id16 &= ~0xff;
1166 id16 |= id2;
1167 dev->chip_id = id16;
1168
1169 dev->cpu_port = dev->mib_port_cnt - 1;
1170 dev->host_mask = BIT(dev->cpu_port);
1171
1172 return 0;
1173}
1174
1175struct ksz_chip_data {
1176 u16 chip_id;
1177 const char *dev_name;
1178 int num_vlans;
1179 int num_alus;
1180 int num_statics;
1181 int cpu_ports;
1182 int port_cnt;
1183};
1184
1185static const struct ksz_chip_data ksz8795_switch_chips[] = {
1186 {
1187 .chip_id = 0x8795,
1188 .dev_name = "KSZ8795",
1189 .num_vlans = 4096,
1190 .num_alus = 0,
1191 .num_statics = 8,
1192 .cpu_ports = 0x10, /* can be configured as cpu port */
1193 .port_cnt = 4, /* total physical port count */
1194 },
1195 {
1196 .chip_id = 0x8794,
1197 .dev_name = "KSZ8794",
1198 .num_vlans = 4096,
1199 .num_alus = 0,
1200 .num_statics = 8,
1201 .cpu_ports = 0x10, /* can be configured as cpu port */
1202 .port_cnt = 3, /* total physical port count */
1203 },
1204 {
1205 .chip_id = 0x8765,
1206 .dev_name = "KSZ8765",
1207 .num_vlans = 4096,
1208 .num_alus = 0,
1209 .num_statics = 8,
1210 .cpu_ports = 0x10, /* can be configured as cpu port */
1211 .port_cnt = 4, /* total physical port count */
1212 },
1213};
1214
1215static int ksz8795_switch_init(struct ksz_device *dev)
1216{
1217 int i;
1218
1219 dev->ds->ops = &ksz8795_switch_ops;
1220
1221 for (i = 0; i < ARRAY_SIZE(ksz8795_switch_chips); i++) {
1222 const struct ksz_chip_data *chip = &ksz8795_switch_chips[i];
1223
1224 if (dev->chip_id == chip->chip_id) {
1225 dev->name = chip->dev_name;
1226 dev->num_vlans = chip->num_vlans;
1227 dev->num_alus = chip->num_alus;
1228 dev->num_statics = chip->num_statics;
1229 dev->port_cnt = chip->port_cnt;
1230 dev->cpu_ports = chip->cpu_ports;
1231
1232 break;
1233 }
1234 }
1235
1236 /* no switch found */
1237 if (!dev->cpu_ports)
1238 return -ENODEV;
1239
1240 dev->port_mask = BIT(dev->port_cnt) - 1;
1241 dev->port_mask |= dev->host_mask;
1242
1243 dev->reg_mib_cnt = SWITCH_COUNTER_NUM;
1244 dev->mib_cnt = TOTAL_SWITCH_COUNTER_NUM;
1245
1246 i = dev->mib_port_cnt;
1247 dev->ports = devm_kzalloc(dev->dev, sizeof(struct ksz_port) * i,
1248 GFP_KERNEL);
1249 if (!dev->ports)
1250 return -ENOMEM;
1251 for (i = 0; i < dev->mib_port_cnt; i++) {
1252 mutex_init(&dev->ports[i].mib.cnt_mutex);
1253 dev->ports[i].mib.counters =
1254 devm_kzalloc(dev->dev,
1255 sizeof(u64) *
1256 (TOTAL_SWITCH_COUNTER_NUM + 1),
1257 GFP_KERNEL);
1258 if (!dev->ports[i].mib.counters)
1259 return -ENOMEM;
1260 }
1261
1262 /* set the real number of ports */
1263 dev->ds->num_ports = dev->port_cnt + 1;
1264
1265 return 0;
1266}
1267
1268static void ksz8795_switch_exit(struct ksz_device *dev)
1269{
1270 ksz8795_reset_switch(dev);
1271}
1272
1273static const struct ksz_dev_ops ksz8795_dev_ops = {
1274 .get_port_addr = ksz8795_get_port_addr,
1275 .cfg_port_member = ksz8795_cfg_port_member,
1276 .flush_dyn_mac_table = ksz8795_flush_dyn_mac_table,
1277 .port_setup = ksz8795_port_setup,
1278 .r_phy = ksz8795_r_phy,
1279 .w_phy = ksz8795_w_phy,
1280 .r_dyn_mac_table = ksz8795_r_dyn_mac_table,
1281 .r_sta_mac_table = ksz8795_r_sta_mac_table,
1282 .w_sta_mac_table = ksz8795_w_sta_mac_table,
1283 .r_mib_cnt = ksz8795_r_mib_cnt,
1284 .r_mib_pkt = ksz8795_r_mib_pkt,
1285 .freeze_mib = ksz8795_freeze_mib,
1286 .port_init_cnt = ksz8795_port_init_cnt,
1287 .shutdown = ksz8795_reset_switch,
1288 .detect = ksz8795_switch_detect,
1289 .init = ksz8795_switch_init,
1290 .exit = ksz8795_switch_exit,
1291};
1292
1293int ksz8795_switch_register(struct ksz_device *dev)
1294{
1295 return ksz_switch_register(dev, &ksz8795_dev_ops);
1296}
1297EXPORT_SYMBOL(ksz8795_switch_register);
1298
1299MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1300MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1301MODULE_LICENSE("GPL");