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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9#include <linux/bitfield.h>
10#include <linux/delay.h>
11#include <linux/export.h>
12#include <linux/gpio.h>
13#include <linux/if_vlan.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/platform_data/microchip-ksz.h>
17#include <linux/phy.h>
18#include <linux/etherdevice.h>
19#include <linux/if_bridge.h>
20#include <linux/micrel_phy.h>
21#include <net/dsa.h>
22#include <net/switchdev.h>
23#include <linux/phylink.h>
24
25#include "ksz_common.h"
26#include "ksz8795_reg.h"
27#include "ksz8.h"
28
29static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
30{
31 regmap_update_bits(ksz_regmap_8(dev), addr, bits, set ? bits : 0);
32}
33
34static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
35 bool set)
36{
37 regmap_update_bits(ksz_regmap_8(dev), PORT_CTRL_ADDR(port, offset),
38 bits, set ? bits : 0);
39}
40
41static int ksz8_ind_write8(struct ksz_device *dev, u8 table, u16 addr, u8 data)
42{
43 const u16 *regs;
44 u16 ctrl_addr;
45 int ret = 0;
46
47 regs = dev->info->regs;
48
49 mutex_lock(&dev->alu_mutex);
50
51 ctrl_addr = IND_ACC_TABLE(table) | addr;
52 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
53 if (!ret)
54 ret = ksz_write8(dev, regs[REG_IND_BYTE], data);
55
56 mutex_unlock(&dev->alu_mutex);
57
58 return ret;
59}
60
61int ksz8_reset_switch(struct ksz_device *dev)
62{
63 if (ksz_is_ksz88x3(dev)) {
64 /* reset switch */
65 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
66 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
67 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
68 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
69 } else {
70 /* reset switch */
71 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
72 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
73 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
74 }
75
76 return 0;
77}
78
79static int ksz8863_change_mtu(struct ksz_device *dev, int frame_size)
80{
81 u8 ctrl2 = 0;
82
83 if (frame_size <= KSZ8_LEGAL_PACKET_SIZE)
84 ctrl2 |= KSZ8863_LEGAL_PACKET_ENABLE;
85 else if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
86 ctrl2 |= KSZ8863_HUGE_PACKET_ENABLE;
87
88 return ksz_rmw8(dev, REG_SW_CTRL_2, KSZ8863_LEGAL_PACKET_ENABLE |
89 KSZ8863_HUGE_PACKET_ENABLE, ctrl2);
90}
91
92static int ksz8795_change_mtu(struct ksz_device *dev, int frame_size)
93{
94 u8 ctrl1 = 0, ctrl2 = 0;
95 int ret;
96
97 if (frame_size > KSZ8_LEGAL_PACKET_SIZE)
98 ctrl2 |= SW_LEGAL_PACKET_DISABLE;
99 if (frame_size > KSZ8863_NORMAL_PACKET_SIZE)
100 ctrl1 |= SW_HUGE_PACKET;
101
102 ret = ksz_rmw8(dev, REG_SW_CTRL_1, SW_HUGE_PACKET, ctrl1);
103 if (ret)
104 return ret;
105
106 return ksz_rmw8(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, ctrl2);
107}
108
109int ksz8_change_mtu(struct ksz_device *dev, int port, int mtu)
110{
111 u16 frame_size;
112
113 if (!dsa_is_cpu_port(dev->ds, port))
114 return 0;
115
116 frame_size = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
117
118 switch (dev->chip_id) {
119 case KSZ8795_CHIP_ID:
120 case KSZ8794_CHIP_ID:
121 case KSZ8765_CHIP_ID:
122 return ksz8795_change_mtu(dev, frame_size);
123 case KSZ8830_CHIP_ID:
124 return ksz8863_change_mtu(dev, frame_size);
125 }
126
127 return -EOPNOTSUPP;
128}
129
130static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
131{
132 u8 hi, lo;
133
134 /* Number of queues can only be 1, 2, or 4. */
135 switch (queue) {
136 case 4:
137 case 3:
138 queue = PORT_QUEUE_SPLIT_4;
139 break;
140 case 2:
141 queue = PORT_QUEUE_SPLIT_2;
142 break;
143 default:
144 queue = PORT_QUEUE_SPLIT_1;
145 }
146 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
147 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
148 lo &= ~PORT_QUEUE_SPLIT_L;
149 if (queue & PORT_QUEUE_SPLIT_2)
150 lo |= PORT_QUEUE_SPLIT_L;
151 hi &= ~PORT_QUEUE_SPLIT_H;
152 if (queue & PORT_QUEUE_SPLIT_4)
153 hi |= PORT_QUEUE_SPLIT_H;
154 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
155 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
156
157 /* Default is port based for egress rate limit. */
158 if (queue != PORT_QUEUE_SPLIT_1)
159 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
160 true);
161}
162
163void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
164{
165 const u32 *masks;
166 const u16 *regs;
167 u16 ctrl_addr;
168 u32 data;
169 u8 check;
170 int loop;
171
172 masks = dev->info->masks;
173 regs = dev->info->regs;
174
175 ctrl_addr = addr + dev->info->reg_mib_cnt * port;
176 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
177
178 mutex_lock(&dev->alu_mutex);
179 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
180
181 /* It is almost guaranteed to always read the valid bit because of
182 * slow SPI speed.
183 */
184 for (loop = 2; loop > 0; loop--) {
185 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
186
187 if (check & masks[MIB_COUNTER_VALID]) {
188 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
189 if (check & masks[MIB_COUNTER_OVERFLOW])
190 *cnt += MIB_COUNTER_VALUE + 1;
191 *cnt += data & MIB_COUNTER_VALUE;
192 break;
193 }
194 }
195 mutex_unlock(&dev->alu_mutex);
196}
197
198static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
199 u64 *dropped, u64 *cnt)
200{
201 const u32 *masks;
202 const u16 *regs;
203 u16 ctrl_addr;
204 u32 data;
205 u8 check;
206 int loop;
207
208 masks = dev->info->masks;
209 regs = dev->info->regs;
210
211 addr -= dev->info->reg_mib_cnt;
212 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
213 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
214 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
215
216 mutex_lock(&dev->alu_mutex);
217 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
218
219 /* It is almost guaranteed to always read the valid bit because of
220 * slow SPI speed.
221 */
222 for (loop = 2; loop > 0; loop--) {
223 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
224
225 if (check & masks[MIB_COUNTER_VALID]) {
226 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
227 if (addr < 2) {
228 u64 total;
229
230 total = check & MIB_TOTAL_BYTES_H;
231 total <<= 32;
232 *cnt += total;
233 *cnt += data;
234 if (check & masks[MIB_COUNTER_OVERFLOW]) {
235 total = MIB_TOTAL_BYTES_H + 1;
236 total <<= 32;
237 *cnt += total;
238 }
239 } else {
240 if (check & masks[MIB_COUNTER_OVERFLOW])
241 *cnt += MIB_PACKET_DROPPED + 1;
242 *cnt += data & MIB_PACKET_DROPPED;
243 }
244 break;
245 }
246 }
247 mutex_unlock(&dev->alu_mutex);
248}
249
250static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
251 u64 *dropped, u64 *cnt)
252{
253 u32 *last = (u32 *)dropped;
254 const u16 *regs;
255 u16 ctrl_addr;
256 u32 data;
257 u32 cur;
258
259 regs = dev->info->regs;
260
261 addr -= dev->info->reg_mib_cnt;
262 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
263 KSZ8863_MIB_PACKET_DROPPED_RX_0;
264 ctrl_addr += port;
265 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
266
267 mutex_lock(&dev->alu_mutex);
268 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
269 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
270 mutex_unlock(&dev->alu_mutex);
271
272 data &= MIB_PACKET_DROPPED;
273 cur = last[addr];
274 if (data != cur) {
275 last[addr] = data;
276 if (data < cur)
277 data += MIB_PACKET_DROPPED + 1;
278 data -= cur;
279 *cnt += data;
280 }
281}
282
283void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
284 u64 *dropped, u64 *cnt)
285{
286 if (ksz_is_ksz88x3(dev))
287 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
288 else
289 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
290}
291
292void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
293{
294 if (ksz_is_ksz88x3(dev))
295 return;
296
297 /* enable the port for flush/freeze function */
298 if (freeze)
299 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
300 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
301
302 /* disable the port after freeze is done */
303 if (!freeze)
304 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
305}
306
307void ksz8_port_init_cnt(struct ksz_device *dev, int port)
308{
309 struct ksz_port_mib *mib = &dev->ports[port].mib;
310 u64 *dropped;
311
312 if (!ksz_is_ksz88x3(dev)) {
313 /* flush all enabled port MIB counters */
314 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
315 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
316 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
317 }
318
319 mib->cnt_ptr = 0;
320
321 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
322 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
323 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
324 &mib->counters[mib->cnt_ptr]);
325 ++mib->cnt_ptr;
326 }
327
328 /* last one in storage */
329 dropped = &mib->counters[dev->info->mib_cnt];
330
331 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
332 while (mib->cnt_ptr < dev->info->mib_cnt) {
333 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
334 dropped, &mib->counters[mib->cnt_ptr]);
335 ++mib->cnt_ptr;
336 }
337}
338
339static int ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
340{
341 const u16 *regs;
342 u16 ctrl_addr;
343 int ret;
344
345 regs = dev->info->regs;
346
347 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
348
349 mutex_lock(&dev->alu_mutex);
350 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
351 if (ret)
352 goto unlock_alu;
353
354 ret = ksz_read64(dev, regs[REG_IND_DATA_HI], data);
355unlock_alu:
356 mutex_unlock(&dev->alu_mutex);
357
358 return ret;
359}
360
361static int ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
362{
363 const u16 *regs;
364 u16 ctrl_addr;
365 int ret;
366
367 regs = dev->info->regs;
368
369 ctrl_addr = IND_ACC_TABLE(table) | addr;
370
371 mutex_lock(&dev->alu_mutex);
372 ret = ksz_write64(dev, regs[REG_IND_DATA_HI], data);
373 if (ret)
374 goto unlock_alu;
375
376 ret = ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
377unlock_alu:
378 mutex_unlock(&dev->alu_mutex);
379
380 return ret;
381}
382
383static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
384{
385 int timeout = 100;
386 const u32 *masks;
387 const u16 *regs;
388
389 masks = dev->info->masks;
390 regs = dev->info->regs;
391
392 do {
393 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
394 timeout--;
395 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
396
397 /* Entry is not ready for accessing. */
398 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) {
399 return -EAGAIN;
400 /* Entry is ready for accessing. */
401 } else {
402 ksz_read8(dev, regs[REG_IND_DATA_8], data);
403
404 /* There is no valid entry in the table. */
405 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY])
406 return -ENXIO;
407 }
408 return 0;
409}
410
411int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr, u8 *mac_addr,
412 u8 *fid, u8 *src_port, u8 *timestamp, u16 *entries)
413{
414 u32 data_hi, data_lo;
415 const u8 *shifts;
416 const u32 *masks;
417 const u16 *regs;
418 u16 ctrl_addr;
419 u8 data;
420 int rc;
421
422 shifts = dev->info->shifts;
423 masks = dev->info->masks;
424 regs = dev->info->regs;
425
426 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
427
428 mutex_lock(&dev->alu_mutex);
429 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
430
431 rc = ksz8_valid_dyn_entry(dev, &data);
432 if (rc == -EAGAIN) {
433 if (addr == 0)
434 *entries = 0;
435 } else if (rc == -ENXIO) {
436 *entries = 0;
437 /* At least one valid entry in the table. */
438 } else {
439 u64 buf = 0;
440 int cnt;
441
442 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
443 data_hi = (u32)(buf >> 32);
444 data_lo = (u32)buf;
445
446 /* Check out how many valid entry in the table. */
447 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
448 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
449 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
450 shifts[DYNAMIC_MAC_ENTRIES];
451 *entries = cnt + 1;
452
453 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
454 shifts[DYNAMIC_MAC_FID];
455 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
456 shifts[DYNAMIC_MAC_SRC_PORT];
457 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >>
458 shifts[DYNAMIC_MAC_TIMESTAMP];
459
460 mac_addr[5] = (u8)data_lo;
461 mac_addr[4] = (u8)(data_lo >> 8);
462 mac_addr[3] = (u8)(data_lo >> 16);
463 mac_addr[2] = (u8)(data_lo >> 24);
464
465 mac_addr[1] = (u8)data_hi;
466 mac_addr[0] = (u8)(data_hi >> 8);
467 rc = 0;
468 }
469 mutex_unlock(&dev->alu_mutex);
470
471 return rc;
472}
473
474static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
475 struct alu_struct *alu, bool *valid)
476{
477 u32 data_hi, data_lo;
478 const u8 *shifts;
479 const u32 *masks;
480 u64 data;
481 int ret;
482
483 shifts = dev->info->shifts;
484 masks = dev->info->masks;
485
486 ret = ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
487 if (ret)
488 return ret;
489
490 data_hi = data >> 32;
491 data_lo = (u32)data;
492
493 if (!(data_hi & (masks[STATIC_MAC_TABLE_VALID] |
494 masks[STATIC_MAC_TABLE_OVERRIDE]))) {
495 *valid = false;
496 return 0;
497 }
498
499 alu->mac[5] = (u8)data_lo;
500 alu->mac[4] = (u8)(data_lo >> 8);
501 alu->mac[3] = (u8)(data_lo >> 16);
502 alu->mac[2] = (u8)(data_lo >> 24);
503 alu->mac[1] = (u8)data_hi;
504 alu->mac[0] = (u8)(data_hi >> 8);
505 alu->port_forward =
506 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
507 shifts[STATIC_MAC_FWD_PORTS];
508 alu->is_override = (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
509
510 /* KSZ8795 family switches have STATIC_MAC_TABLE_USE_FID and
511 * STATIC_MAC_TABLE_FID definitions off by 1 when doing read on the
512 * static MAC table compared to doing write.
513 */
514 if (ksz_is_ksz87xx(dev))
515 data_hi >>= 1;
516 alu->is_static = true;
517 alu->is_use_fid = (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
518 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
519 shifts[STATIC_MAC_FID];
520
521 *valid = true;
522
523 return 0;
524}
525
526static int ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
527 struct alu_struct *alu)
528{
529 u32 data_hi, data_lo;
530 const u8 *shifts;
531 const u32 *masks;
532 u64 data;
533
534 shifts = dev->info->shifts;
535 masks = dev->info->masks;
536
537 data_lo = ((u32)alu->mac[2] << 24) |
538 ((u32)alu->mac[3] << 16) |
539 ((u32)alu->mac[4] << 8) | alu->mac[5];
540 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
541 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
542
543 if (alu->is_override)
544 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
545 if (alu->is_use_fid) {
546 data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
547 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
548 }
549 if (alu->is_static)
550 data_hi |= masks[STATIC_MAC_TABLE_VALID];
551 else
552 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
553
554 data = (u64)data_hi << 32 | data_lo;
555
556 return ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
557}
558
559static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
560 u8 *member, u8 *valid)
561{
562 const u8 *shifts;
563 const u32 *masks;
564
565 shifts = dev->info->shifts;
566 masks = dev->info->masks;
567
568 *fid = vlan & masks[VLAN_TABLE_FID];
569 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
570 shifts[VLAN_TABLE_MEMBERSHIP_S];
571 *valid = !!(vlan & masks[VLAN_TABLE_VALID]);
572}
573
574static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
575 u16 *vlan)
576{
577 const u8 *shifts;
578 const u32 *masks;
579
580 shifts = dev->info->shifts;
581 masks = dev->info->masks;
582
583 *vlan = fid;
584 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
585 if (valid)
586 *vlan |= masks[VLAN_TABLE_VALID];
587}
588
589static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
590{
591 const u8 *shifts;
592 u64 data;
593 int i;
594
595 shifts = dev->info->shifts;
596
597 ksz8_r_table(dev, TABLE_VLAN, addr, &data);
598 addr *= 4;
599 for (i = 0; i < 4; i++) {
600 dev->vlan_cache[addr + i].table[0] = (u16)data;
601 data >>= shifts[VLAN_TABLE];
602 }
603}
604
605static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
606{
607 int index;
608 u16 *data;
609 u16 addr;
610 u64 buf;
611
612 data = (u16 *)&buf;
613 addr = vid / 4;
614 index = vid & 3;
615 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
616 *vlan = data[index];
617}
618
619static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
620{
621 int index;
622 u16 *data;
623 u16 addr;
624 u64 buf;
625
626 data = (u16 *)&buf;
627 addr = vid / 4;
628 index = vid & 3;
629 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
630 data[index] = vlan;
631 dev->vlan_cache[vid].table[0] = vlan;
632 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
633}
634
635/**
636 * ksz8_r_phy_ctrl - Translates and reads from the SMI interface to a MIIM PHY
637 * Control register (Reg. 31).
638 * @dev: The KSZ device instance.
639 * @port: The port number to be read.
640 * @val: The value read from the SMI interface.
641 *
642 * This function reads the SMI interface and translates the hardware register
643 * bit values into their corresponding control settings for a MIIM PHY Control
644 * register.
645 *
646 * Return: 0 on success, error code on failure.
647 */
648static int ksz8_r_phy_ctrl(struct ksz_device *dev, int port, u16 *val)
649{
650 const u16 *regs = dev->info->regs;
651 u8 reg_val;
652 int ret;
653
654 *val = 0;
655
656 ret = ksz_pread8(dev, port, regs[P_LINK_STATUS], ®_val);
657 if (ret < 0)
658 return ret;
659
660 if (reg_val & PORT_MDIX_STATUS)
661 *val |= KSZ886X_CTRL_MDIX_STAT;
662
663 ret = ksz_pread8(dev, port, REG_PORT_LINK_MD_CTRL, ®_val);
664 if (ret < 0)
665 return ret;
666
667 if (reg_val & PORT_FORCE_LINK)
668 *val |= KSZ886X_CTRL_FORCE_LINK;
669
670 if (reg_val & PORT_POWER_SAVING)
671 *val |= KSZ886X_CTRL_PWRSAVE;
672
673 if (reg_val & PORT_PHY_REMOTE_LOOPBACK)
674 *val |= KSZ886X_CTRL_REMOTE_LOOPBACK;
675
676 return 0;
677}
678
679int ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
680{
681 u8 restart, speed, ctrl, link;
682 int processed = true;
683 const u16 *regs;
684 u8 val1, val2;
685 u16 data = 0;
686 u8 p = phy;
687 int ret;
688
689 regs = dev->info->regs;
690
691 switch (reg) {
692 case MII_BMCR:
693 ret = ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
694 if (ret)
695 return ret;
696
697 ret = ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
698 if (ret)
699 return ret;
700
701 ret = ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
702 if (ret)
703 return ret;
704
705 if (restart & PORT_PHY_LOOPBACK)
706 data |= BMCR_LOOPBACK;
707 if (ctrl & PORT_FORCE_100_MBIT)
708 data |= BMCR_SPEED100;
709 if (ksz_is_ksz88x3(dev)) {
710 if ((ctrl & PORT_AUTO_NEG_ENABLE))
711 data |= BMCR_ANENABLE;
712 } else {
713 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
714 data |= BMCR_ANENABLE;
715 }
716 if (restart & PORT_POWER_DOWN)
717 data |= BMCR_PDOWN;
718 if (restart & PORT_AUTO_NEG_RESTART)
719 data |= BMCR_ANRESTART;
720 if (ctrl & PORT_FORCE_FULL_DUPLEX)
721 data |= BMCR_FULLDPLX;
722 if (speed & PORT_HP_MDIX)
723 data |= KSZ886X_BMCR_HP_MDIX;
724 if (restart & PORT_FORCE_MDIX)
725 data |= KSZ886X_BMCR_FORCE_MDI;
726 if (restart & PORT_AUTO_MDIX_DISABLE)
727 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
728 if (restart & PORT_TX_DISABLE)
729 data |= KSZ886X_BMCR_DISABLE_TRANSMIT;
730 if (restart & PORT_LED_OFF)
731 data |= KSZ886X_BMCR_DISABLE_LED;
732 break;
733 case MII_BMSR:
734 ret = ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
735 if (ret)
736 return ret;
737
738 data = BMSR_100FULL |
739 BMSR_100HALF |
740 BMSR_10FULL |
741 BMSR_10HALF |
742 BMSR_ANEGCAPABLE;
743 if (link & PORT_AUTO_NEG_COMPLETE)
744 data |= BMSR_ANEGCOMPLETE;
745 if (link & PORT_STAT_LINK_GOOD)
746 data |= BMSR_LSTATUS;
747 break;
748 case MII_PHYSID1:
749 data = KSZ8795_ID_HI;
750 break;
751 case MII_PHYSID2:
752 if (ksz_is_ksz88x3(dev))
753 data = KSZ8863_ID_LO;
754 else
755 data = KSZ8795_ID_LO;
756 break;
757 case MII_ADVERTISE:
758 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
759 if (ret)
760 return ret;
761
762 data = ADVERTISE_CSMA;
763 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
764 data |= ADVERTISE_PAUSE_CAP;
765 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
766 data |= ADVERTISE_100FULL;
767 if (ctrl & PORT_AUTO_NEG_100BTX)
768 data |= ADVERTISE_100HALF;
769 if (ctrl & PORT_AUTO_NEG_10BT_FD)
770 data |= ADVERTISE_10FULL;
771 if (ctrl & PORT_AUTO_NEG_10BT)
772 data |= ADVERTISE_10HALF;
773 break;
774 case MII_LPA:
775 ret = ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
776 if (ret)
777 return ret;
778
779 data = LPA_SLCT;
780 if (link & PORT_REMOTE_SYM_PAUSE)
781 data |= LPA_PAUSE_CAP;
782 if (link & PORT_REMOTE_100BTX_FD)
783 data |= LPA_100FULL;
784 if (link & PORT_REMOTE_100BTX)
785 data |= LPA_100HALF;
786 if (link & PORT_REMOTE_10BT_FD)
787 data |= LPA_10FULL;
788 if (link & PORT_REMOTE_10BT)
789 data |= LPA_10HALF;
790 if (data & ~LPA_SLCT)
791 data |= LPA_LPACK;
792 break;
793 case PHY_REG_LINK_MD:
794 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
795 if (ret)
796 return ret;
797
798 ret = ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
799 if (ret)
800 return ret;
801
802 if (val1 & PORT_START_CABLE_DIAG)
803 data |= PHY_START_CABLE_DIAG;
804
805 if (val1 & PORT_CABLE_10M_SHORT)
806 data |= PHY_CABLE_10M_SHORT;
807
808 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
809 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
810
811 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
812 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
813 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
814 break;
815 case PHY_REG_PHY_CTRL:
816 ret = ksz8_r_phy_ctrl(dev, p, &data);
817 if (ret)
818 return ret;
819
820 break;
821 default:
822 processed = false;
823 break;
824 }
825 if (processed)
826 *val = data;
827
828 return 0;
829}
830
831/**
832 * ksz8_w_phy_ctrl - Translates and writes to the SMI interface from a MIIM PHY
833 * Control register (Reg. 31).
834 * @dev: The KSZ device instance.
835 * @port: The port number to be configured.
836 * @val: The register value to be written.
837 *
838 * This function translates control settings from a MIIM PHY Control register
839 * into their corresponding hardware register bit values for the SMI
840 * interface.
841 *
842 * Return: 0 on success, error code on failure.
843 */
844static int ksz8_w_phy_ctrl(struct ksz_device *dev, int port, u16 val)
845{
846 u8 reg_val = 0;
847 int ret;
848
849 if (val & KSZ886X_CTRL_FORCE_LINK)
850 reg_val |= PORT_FORCE_LINK;
851
852 if (val & KSZ886X_CTRL_PWRSAVE)
853 reg_val |= PORT_POWER_SAVING;
854
855 if (val & KSZ886X_CTRL_REMOTE_LOOPBACK)
856 reg_val |= PORT_PHY_REMOTE_LOOPBACK;
857
858 ret = ksz_prmw8(dev, port, REG_PORT_LINK_MD_CTRL, PORT_FORCE_LINK |
859 PORT_POWER_SAVING | PORT_PHY_REMOTE_LOOPBACK, reg_val);
860 return ret;
861}
862
863int ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
864{
865 u8 restart, speed, ctrl, data;
866 const u16 *regs;
867 u8 p = phy;
868 int ret;
869
870 regs = dev->info->regs;
871
872 switch (reg) {
873 case MII_BMCR:
874
875 /* Do not support PHY reset function. */
876 if (val & BMCR_RESET)
877 break;
878 ret = ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
879 if (ret)
880 return ret;
881
882 data = speed;
883 if (val & KSZ886X_BMCR_HP_MDIX)
884 data |= PORT_HP_MDIX;
885 else
886 data &= ~PORT_HP_MDIX;
887
888 if (data != speed) {
889 ret = ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data);
890 if (ret)
891 return ret;
892 }
893
894 ret = ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
895 if (ret)
896 return ret;
897
898 data = ctrl;
899 if (ksz_is_ksz88x3(dev)) {
900 if ((val & BMCR_ANENABLE))
901 data |= PORT_AUTO_NEG_ENABLE;
902 else
903 data &= ~PORT_AUTO_NEG_ENABLE;
904 } else {
905 if (!(val & BMCR_ANENABLE))
906 data |= PORT_AUTO_NEG_DISABLE;
907 else
908 data &= ~PORT_AUTO_NEG_DISABLE;
909
910 /* Fiber port does not support auto-negotiation. */
911 if (dev->ports[p].fiber)
912 data |= PORT_AUTO_NEG_DISABLE;
913 }
914
915 if (val & BMCR_SPEED100)
916 data |= PORT_FORCE_100_MBIT;
917 else
918 data &= ~PORT_FORCE_100_MBIT;
919 if (val & BMCR_FULLDPLX)
920 data |= PORT_FORCE_FULL_DUPLEX;
921 else
922 data &= ~PORT_FORCE_FULL_DUPLEX;
923
924 if (data != ctrl) {
925 ret = ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data);
926 if (ret)
927 return ret;
928 }
929
930 ret = ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
931 if (ret)
932 return ret;
933
934 data = restart;
935 if (val & KSZ886X_BMCR_DISABLE_LED)
936 data |= PORT_LED_OFF;
937 else
938 data &= ~PORT_LED_OFF;
939 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
940 data |= PORT_TX_DISABLE;
941 else
942 data &= ~PORT_TX_DISABLE;
943 if (val & BMCR_ANRESTART)
944 data |= PORT_AUTO_NEG_RESTART;
945 else
946 data &= ~(PORT_AUTO_NEG_RESTART);
947 if (val & BMCR_PDOWN)
948 data |= PORT_POWER_DOWN;
949 else
950 data &= ~PORT_POWER_DOWN;
951 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
952 data |= PORT_AUTO_MDIX_DISABLE;
953 else
954 data &= ~PORT_AUTO_MDIX_DISABLE;
955 if (val & KSZ886X_BMCR_FORCE_MDI)
956 data |= PORT_FORCE_MDIX;
957 else
958 data &= ~PORT_FORCE_MDIX;
959 if (val & BMCR_LOOPBACK)
960 data |= PORT_PHY_LOOPBACK;
961 else
962 data &= ~PORT_PHY_LOOPBACK;
963
964 if (data != restart) {
965 ret = ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL],
966 data);
967 if (ret)
968 return ret;
969 }
970 break;
971 case MII_ADVERTISE:
972 ret = ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
973 if (ret)
974 return ret;
975
976 data = ctrl;
977 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
978 PORT_AUTO_NEG_100BTX_FD |
979 PORT_AUTO_NEG_100BTX |
980 PORT_AUTO_NEG_10BT_FD |
981 PORT_AUTO_NEG_10BT);
982 if (val & ADVERTISE_PAUSE_CAP)
983 data |= PORT_AUTO_NEG_SYM_PAUSE;
984 if (val & ADVERTISE_100FULL)
985 data |= PORT_AUTO_NEG_100BTX_FD;
986 if (val & ADVERTISE_100HALF)
987 data |= PORT_AUTO_NEG_100BTX;
988 if (val & ADVERTISE_10FULL)
989 data |= PORT_AUTO_NEG_10BT_FD;
990 if (val & ADVERTISE_10HALF)
991 data |= PORT_AUTO_NEG_10BT;
992
993 if (data != ctrl) {
994 ret = ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
995 if (ret)
996 return ret;
997 }
998 break;
999 case PHY_REG_LINK_MD:
1000 if (val & PHY_START_CABLE_DIAG)
1001 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
1002 break;
1003
1004 case PHY_REG_PHY_CTRL:
1005 ret = ksz8_w_phy_ctrl(dev, p, val);
1006 if (ret)
1007 return ret;
1008 break;
1009 default:
1010 break;
1011 }
1012
1013 return 0;
1014}
1015
1016void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
1017{
1018 u8 data;
1019
1020 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1021 data &= ~PORT_VLAN_MEMBERSHIP;
1022 data |= (member & dev->port_mask);
1023 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
1024}
1025
1026void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port)
1027{
1028 u8 learn[DSA_MAX_PORTS];
1029 int first, index, cnt;
1030 const u16 *regs;
1031
1032 regs = dev->info->regs;
1033
1034 if ((uint)port < dev->info->port_cnt) {
1035 first = port;
1036 cnt = port + 1;
1037 } else {
1038 /* Flush all ports. */
1039 first = 0;
1040 cnt = dev->info->port_cnt;
1041 }
1042 for (index = first; index < cnt; index++) {
1043 ksz_pread8(dev, index, regs[P_STP_CTRL], &learn[index]);
1044 if (!(learn[index] & PORT_LEARN_DISABLE))
1045 ksz_pwrite8(dev, index, regs[P_STP_CTRL],
1046 learn[index] | PORT_LEARN_DISABLE);
1047 }
1048 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
1049 for (index = first; index < cnt; index++) {
1050 if (!(learn[index] & PORT_LEARN_DISABLE))
1051 ksz_pwrite8(dev, index, regs[P_STP_CTRL], learn[index]);
1052 }
1053}
1054
1055int ksz8_fdb_dump(struct ksz_device *dev, int port,
1056 dsa_fdb_dump_cb_t *cb, void *data)
1057{
1058 int ret = 0;
1059 u16 i = 0;
1060 u16 entries = 0;
1061 u8 timestamp = 0;
1062 u8 fid;
1063 u8 src_port;
1064 u8 mac[ETH_ALEN];
1065
1066 do {
1067 ret = ksz8_r_dyn_mac_table(dev, i, mac, &fid, &src_port,
1068 ×tamp, &entries);
1069 if (!ret && port == src_port) {
1070 ret = cb(mac, fid, false, data);
1071 if (ret)
1072 break;
1073 }
1074 i++;
1075 } while (i < entries);
1076 if (i >= entries)
1077 ret = 0;
1078
1079 return ret;
1080}
1081
1082static int ksz8_add_sta_mac(struct ksz_device *dev, int port,
1083 const unsigned char *addr, u16 vid)
1084{
1085 struct alu_struct alu;
1086 int index, ret;
1087 int empty = 0;
1088
1089 alu.port_forward = 0;
1090 for (index = 0; index < dev->info->num_statics; index++) {
1091 bool valid;
1092
1093 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1094 if (ret)
1095 return ret;
1096 if (!valid) {
1097 /* Remember the first empty entry. */
1098 if (!empty)
1099 empty = index + 1;
1100 continue;
1101 }
1102
1103 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1104 break;
1105 }
1106
1107 /* no available entry */
1108 if (index == dev->info->num_statics && !empty)
1109 return -ENOSPC;
1110
1111 /* add entry */
1112 if (index == dev->info->num_statics) {
1113 index = empty - 1;
1114 memset(&alu, 0, sizeof(alu));
1115 memcpy(alu.mac, addr, ETH_ALEN);
1116 alu.is_static = true;
1117 }
1118 alu.port_forward |= BIT(port);
1119 if (vid) {
1120 alu.is_use_fid = true;
1121
1122 /* Need a way to map VID to FID. */
1123 alu.fid = vid;
1124 }
1125
1126 return ksz8_w_sta_mac_table(dev, index, &alu);
1127}
1128
1129static int ksz8_del_sta_mac(struct ksz_device *dev, int port,
1130 const unsigned char *addr, u16 vid)
1131{
1132 struct alu_struct alu;
1133 int index, ret;
1134
1135 for (index = 0; index < dev->info->num_statics; index++) {
1136 bool valid;
1137
1138 ret = ksz8_r_sta_mac_table(dev, index, &alu, &valid);
1139 if (ret)
1140 return ret;
1141 if (!valid)
1142 continue;
1143
1144 if (!memcmp(alu.mac, addr, ETH_ALEN) && alu.fid == vid)
1145 break;
1146 }
1147
1148 /* no available entry */
1149 if (index == dev->info->num_statics)
1150 return 0;
1151
1152 /* clear port */
1153 alu.port_forward &= ~BIT(port);
1154 if (!alu.port_forward)
1155 alu.is_static = false;
1156
1157 return ksz8_w_sta_mac_table(dev, index, &alu);
1158}
1159
1160int ksz8_mdb_add(struct ksz_device *dev, int port,
1161 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1162{
1163 return ksz8_add_sta_mac(dev, port, mdb->addr, mdb->vid);
1164}
1165
1166int ksz8_mdb_del(struct ksz_device *dev, int port,
1167 const struct switchdev_obj_port_mdb *mdb, struct dsa_db db)
1168{
1169 return ksz8_del_sta_mac(dev, port, mdb->addr, mdb->vid);
1170}
1171
1172int ksz8_fdb_add(struct ksz_device *dev, int port, const unsigned char *addr,
1173 u16 vid, struct dsa_db db)
1174{
1175 return ksz8_add_sta_mac(dev, port, addr, vid);
1176}
1177
1178int ksz8_fdb_del(struct ksz_device *dev, int port, const unsigned char *addr,
1179 u16 vid, struct dsa_db db)
1180{
1181 return ksz8_del_sta_mac(dev, port, addr, vid);
1182}
1183
1184int ksz8_port_vlan_filtering(struct ksz_device *dev, int port, bool flag,
1185 struct netlink_ext_ack *extack)
1186{
1187 if (ksz_is_ksz88x3(dev))
1188 return -ENOTSUPP;
1189
1190 /* Discard packets with VID not enabled on the switch */
1191 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
1192
1193 /* Discard packets with VID not enabled on the ingress port */
1194 for (port = 0; port < dev->phy_port_cnt; ++port)
1195 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
1196 flag);
1197
1198 return 0;
1199}
1200
1201static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
1202{
1203 if (ksz_is_ksz88x3(dev)) {
1204 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID,
1205 0x03 << (4 - 2 * port), state);
1206 } else {
1207 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
1208 }
1209}
1210
1211int ksz8_port_vlan_add(struct ksz_device *dev, int port,
1212 const struct switchdev_obj_port_vlan *vlan,
1213 struct netlink_ext_ack *extack)
1214{
1215 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1216 struct ksz_port *p = &dev->ports[port];
1217 u16 data, new_pvid = 0;
1218 u8 fid, member, valid;
1219
1220 if (ksz_is_ksz88x3(dev))
1221 return -ENOTSUPP;
1222
1223 /* If a VLAN is added with untagged flag different from the
1224 * port's Remove Tag flag, we need to change the latter.
1225 * Ignore VID 0, which is always untagged.
1226 * Ignore CPU port, which will always be tagged.
1227 */
1228 if (untagged != p->remove_tag && vlan->vid != 0 &&
1229 port != dev->cpu_port) {
1230 unsigned int vid;
1231
1232 /* Reject attempts to add a VLAN that requires the
1233 * Remove Tag flag to be changed, unless there are no
1234 * other VLANs currently configured.
1235 */
1236 for (vid = 1; vid < dev->info->num_vlans; ++vid) {
1237 /* Skip the VID we are going to add or reconfigure */
1238 if (vid == vlan->vid)
1239 continue;
1240
1241 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
1242 &fid, &member, &valid);
1243 if (valid && (member & BIT(port)))
1244 return -EINVAL;
1245 }
1246
1247 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1248 p->remove_tag = untagged;
1249 }
1250
1251 ksz8_r_vlan_table(dev, vlan->vid, &data);
1252 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1253
1254 /* First time to setup the VLAN entry. */
1255 if (!valid) {
1256 /* Need to find a way to map VID to FID. */
1257 fid = 1;
1258 valid = 1;
1259 }
1260 member |= BIT(port);
1261
1262 ksz8_to_vlan(dev, fid, member, valid, &data);
1263 ksz8_w_vlan_table(dev, vlan->vid, data);
1264
1265 /* change PVID */
1266 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1267 new_pvid = vlan->vid;
1268
1269 if (new_pvid) {
1270 u16 vid;
1271
1272 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1273 vid &= ~VLAN_VID_MASK;
1274 vid |= new_pvid;
1275 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1276
1277 ksz8_port_enable_pvid(dev, port, true);
1278 }
1279
1280 return 0;
1281}
1282
1283int ksz8_port_vlan_del(struct ksz_device *dev, int port,
1284 const struct switchdev_obj_port_vlan *vlan)
1285{
1286 u16 data, pvid;
1287 u8 fid, member, valid;
1288
1289 if (ksz_is_ksz88x3(dev))
1290 return -ENOTSUPP;
1291
1292 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1293 pvid = pvid & 0xFFF;
1294
1295 ksz8_r_vlan_table(dev, vlan->vid, &data);
1296 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1297
1298 member &= ~BIT(port);
1299
1300 /* Invalidate the entry if no more member. */
1301 if (!member) {
1302 fid = 0;
1303 valid = 0;
1304 }
1305
1306 ksz8_to_vlan(dev, fid, member, valid, &data);
1307 ksz8_w_vlan_table(dev, vlan->vid, data);
1308
1309 if (pvid == vlan->vid)
1310 ksz8_port_enable_pvid(dev, port, false);
1311
1312 return 0;
1313}
1314
1315int ksz8_port_mirror_add(struct ksz_device *dev, int port,
1316 struct dsa_mall_mirror_tc_entry *mirror,
1317 bool ingress, struct netlink_ext_ack *extack)
1318{
1319 if (ingress) {
1320 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1321 dev->mirror_rx |= BIT(port);
1322 } else {
1323 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1324 dev->mirror_tx |= BIT(port);
1325 }
1326
1327 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1328
1329 /* configure mirror port */
1330 if (dev->mirror_rx || dev->mirror_tx)
1331 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1332 PORT_MIRROR_SNIFFER, true);
1333
1334 return 0;
1335}
1336
1337void ksz8_port_mirror_del(struct ksz_device *dev, int port,
1338 struct dsa_mall_mirror_tc_entry *mirror)
1339{
1340 u8 data;
1341
1342 if (mirror->ingress) {
1343 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1344 dev->mirror_rx &= ~BIT(port);
1345 } else {
1346 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1347 dev->mirror_tx &= ~BIT(port);
1348 }
1349
1350 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1351
1352 if (!dev->mirror_rx && !dev->mirror_tx)
1353 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1354 PORT_MIRROR_SNIFFER, false);
1355}
1356
1357static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
1358{
1359 struct ksz_port *p = &dev->ports[port];
1360
1361 if (!ksz_is_ksz87xx(dev))
1362 return;
1363
1364 if (!p->interface && dev->compat_interface) {
1365 dev_warn(dev->dev,
1366 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1367 "Please update your device tree.\n",
1368 port);
1369 p->interface = dev->compat_interface;
1370 }
1371}
1372
1373void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1374{
1375 struct dsa_switch *ds = dev->ds;
1376 const u32 *masks;
1377 u8 member;
1378
1379 masks = dev->info->masks;
1380
1381 /* enable broadcast storm limit */
1382 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1383
1384 if (!ksz_is_ksz88x3(dev))
1385 ksz8795_set_prio_queue(dev, port, 4);
1386
1387 /* disable DiffServ priority */
1388 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
1389
1390 /* replace priority */
1391 ksz_port_cfg(dev, port, P_802_1P_CTRL,
1392 masks[PORT_802_1P_REMAPPING], false);
1393
1394 /* enable 802.1p priority */
1395 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
1396
1397 if (cpu_port)
1398 member = dsa_user_ports(ds);
1399 else
1400 member = BIT(dsa_upstream_port(ds, port));
1401
1402 ksz8_cfg_port_member(dev, port, member);
1403}
1404
1405static void ksz88x3_config_rmii_clk(struct ksz_device *dev)
1406{
1407 struct dsa_port *cpu_dp = dsa_to_port(dev->ds, dev->cpu_port);
1408 bool rmii_clk_internal;
1409
1410 if (!ksz_is_ksz88x3(dev))
1411 return;
1412
1413 rmii_clk_internal = of_property_read_bool(cpu_dp->dn,
1414 "microchip,rmii-clk-internal");
1415
1416 ksz_cfg(dev, KSZ88X3_REG_FVID_AND_HOST_MODE,
1417 KSZ88X3_PORT3_RMII_CLK_INTERNAL, rmii_clk_internal);
1418}
1419
1420void ksz8_config_cpu_port(struct dsa_switch *ds)
1421{
1422 struct ksz_device *dev = ds->priv;
1423 struct ksz_port *p;
1424 const u32 *masks;
1425 const u16 *regs;
1426 u8 remote;
1427 int i;
1428
1429 masks = dev->info->masks;
1430 regs = dev->info->regs;
1431
1432 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1433
1434 ksz8_port_setup(dev, dev->cpu_port, true);
1435
1436 ksz8795_cpu_interface_select(dev, dev->cpu_port);
1437 ksz88x3_config_rmii_clk(dev);
1438
1439 for (i = 0; i < dev->phy_port_cnt; i++) {
1440 ksz_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1441 }
1442 for (i = 0; i < dev->phy_port_cnt; i++) {
1443 p = &dev->ports[i];
1444
1445 if (!ksz_is_ksz88x3(dev)) {
1446 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
1447 if (remote & KSZ8_PORT_FIBER_MODE)
1448 p->fiber = 1;
1449 }
1450 if (p->fiber)
1451 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1452 PORT_FORCE_FLOW_CTRL, true);
1453 else
1454 ksz_port_cfg(dev, i, regs[P_STP_CTRL],
1455 PORT_FORCE_FLOW_CTRL, false);
1456 }
1457}
1458
1459/**
1460 * ksz8_phy_port_link_up - Configures ports with integrated PHYs
1461 * @dev: The KSZ device instance.
1462 * @port: The port number to configure.
1463 * @duplex: The desired duplex mode.
1464 * @tx_pause: If true, enables transmit pause.
1465 * @rx_pause: If true, enables receive pause.
1466 *
1467 * Description:
1468 * The function configures flow control settings for a given port based on the
1469 * desired settings and current duplex mode.
1470 *
1471 * According to the KSZ8873 datasheet, the PORT_FORCE_FLOW_CTRL bit in the
1472 * Port Control 2 register (0x1A for Port 1, 0x22 for Port 2, 0x32 for Port 3)
1473 * determines how flow control is handled on the port:
1474 * "1 = will always enable full-duplex flow control on the port, regardless
1475 * of AN result.
1476 * 0 = full-duplex flow control is enabled based on AN result."
1477 *
1478 * This means that the flow control behavior depends on the state of this bit:
1479 * - If PORT_FORCE_FLOW_CTRL is set to 1, the switch will ignore AN results and
1480 * force flow control on the port.
1481 * - If PORT_FORCE_FLOW_CTRL is set to 0, the switch will enable or disable
1482 * flow control based on the AN results.
1483 *
1484 * However, there is a potential limitation in this configuration. It is
1485 * currently not possible to force disable flow control on a port if we still
1486 * advertise pause support. While such a configuration is not currently
1487 * supported by Linux, and may not make practical sense, it's important to be
1488 * aware of this limitation when working with the KSZ8873 and similar devices.
1489 */
1490static void ksz8_phy_port_link_up(struct ksz_device *dev, int port, int duplex,
1491 bool tx_pause, bool rx_pause)
1492{
1493 const u16 *regs = dev->info->regs;
1494 u8 sctrl = 0;
1495
1496 /* The KSZ8795 switch differs from the KSZ8873 by supporting
1497 * asymmetric pause control. However, since a single bit is used to
1498 * control both RX and TX pause, we can't enforce asymmetric pause
1499 * control - both TX and RX pause will be either enabled or disabled
1500 * together.
1501 *
1502 * If auto-negotiation is enabled, we usually allow the flow control to
1503 * be determined by the auto-negotiation process based on the
1504 * capabilities of both link partners. However, for KSZ8873, the
1505 * PORT_FORCE_FLOW_CTRL bit may be set by the hardware bootstrap,
1506 * ignoring the auto-negotiation result. Thus, even in auto-negotiation
1507 * mode, we need to ensure that the PORT_FORCE_FLOW_CTRL bit is
1508 * properly cleared.
1509 *
1510 * In the absence of pause auto-negotiation, we will enforce symmetric
1511 * pause control for both variants of switches - KSZ8873 and KSZ8795.
1512 *
1513 * Autoneg Pause Autoneg rx,tx PORT_FORCE_FLOW_CTRL
1514 * 1 1 x 0
1515 * 0 1 x 0 (flow control probably disabled)
1516 * x 0 1 1 (flow control force enabled)
1517 * 1 0 0 0 (flow control still depends on
1518 * aneg result due to hardware)
1519 * 0 0 0 0 (flow control probably disabled)
1520 */
1521 if (dev->ports[port].manual_flow && tx_pause)
1522 sctrl |= PORT_FORCE_FLOW_CTRL;
1523
1524 ksz_prmw8(dev, port, regs[P_STP_CTRL], PORT_FORCE_FLOW_CTRL, sctrl);
1525}
1526
1527/**
1528 * ksz8_cpu_port_link_up - Configures the CPU port of the switch.
1529 * @dev: The KSZ device instance.
1530 * @speed: The desired link speed.
1531 * @duplex: The desired duplex mode.
1532 * @tx_pause: If true, enables transmit pause.
1533 * @rx_pause: If true, enables receive pause.
1534 *
1535 * Description:
1536 * The function configures flow control and speed settings for the CPU
1537 * port of the switch based on the desired settings, current duplex mode, and
1538 * speed.
1539 */
1540static void ksz8_cpu_port_link_up(struct ksz_device *dev, int speed, int duplex,
1541 bool tx_pause, bool rx_pause)
1542{
1543 const u16 *regs = dev->info->regs;
1544 u8 ctrl = 0;
1545
1546 /* SW_FLOW_CTRL, SW_HALF_DUPLEX, and SW_10_MBIT bits are bootstrappable
1547 * at least on KSZ8873. They can have different values depending on your
1548 * board setup.
1549 */
1550 if (tx_pause || rx_pause)
1551 ctrl |= SW_FLOW_CTRL;
1552
1553 if (duplex == DUPLEX_HALF)
1554 ctrl |= SW_HALF_DUPLEX;
1555
1556 /* This hardware only supports SPEED_10 and SPEED_100. For SPEED_10
1557 * we need to set the SW_10_MBIT bit. Otherwise, we can leave it 0.
1558 */
1559 if (speed == SPEED_10)
1560 ctrl |= SW_10_MBIT;
1561
1562 ksz_rmw8(dev, regs[S_BROADCAST_CTRL], SW_HALF_DUPLEX | SW_FLOW_CTRL |
1563 SW_10_MBIT, ctrl);
1564}
1565
1566void ksz8_phylink_mac_link_up(struct ksz_device *dev, int port,
1567 unsigned int mode, phy_interface_t interface,
1568 struct phy_device *phydev, int speed, int duplex,
1569 bool tx_pause, bool rx_pause)
1570{
1571 /* If the port is the CPU port, apply special handling. Only the CPU
1572 * port is configured via global registers.
1573 */
1574 if (dev->cpu_port == port)
1575 ksz8_cpu_port_link_up(dev, speed, duplex, tx_pause, rx_pause);
1576 else if (dev->info->internal_phy[port])
1577 ksz8_phy_port_link_up(dev, port, duplex, tx_pause, rx_pause);
1578}
1579
1580static int ksz8_handle_global_errata(struct dsa_switch *ds)
1581{
1582 struct ksz_device *dev = ds->priv;
1583 int ret = 0;
1584
1585 /* KSZ87xx Errata DS80000687C.
1586 * Module 2: Link drops with some EEE link partners.
1587 * An issue with the EEE next page exchange between the
1588 * KSZ879x/KSZ877x/KSZ876x and some EEE link partners may result in
1589 * the link dropping.
1590 */
1591 if (dev->info->ksz87xx_eee_link_erratum)
1592 ret = ksz8_ind_write8(dev, TABLE_EEE, REG_IND_EEE_GLOB2_HI, 0);
1593
1594 return ret;
1595}
1596
1597int ksz8_enable_stp_addr(struct ksz_device *dev)
1598{
1599 struct alu_struct alu;
1600
1601 /* Setup STP address for STP operation. */
1602 memset(&alu, 0, sizeof(alu));
1603 ether_addr_copy(alu.mac, eth_stp_addr);
1604 alu.is_static = true;
1605 alu.is_override = true;
1606 alu.port_forward = dev->info->cpu_ports;
1607
1608 return ksz8_w_sta_mac_table(dev, 0, &alu);
1609}
1610
1611int ksz8_setup(struct dsa_switch *ds)
1612{
1613 struct ksz_device *dev = ds->priv;
1614 int i;
1615
1616 ds->mtu_enforcement_ingress = true;
1617
1618 /* We rely on software untagging on the CPU port, so that we
1619 * can support both tagged and untagged VLANs
1620 */
1621 ds->untag_bridge_pvid = true;
1622
1623 /* VLAN filtering is partly controlled by the global VLAN
1624 * Enable flag
1625 */
1626 ds->vlan_filtering_is_global = true;
1627
1628 /* Enable automatic fast aging when link changed detected. */
1629 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1630
1631 /* Enable aggressive back off algorithm in half duplex mode. */
1632 regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_1,
1633 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1634
1635 /*
1636 * Make sure unicast VLAN boundary is set as default and
1637 * enable no excessive collision drop.
1638 */
1639 regmap_update_bits(ksz_regmap_8(dev), REG_SW_CTRL_2,
1640 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1641 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1642
1643 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1644
1645 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1646
1647 if (!ksz_is_ksz88x3(dev))
1648 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1649
1650 for (i = 0; i < (dev->info->num_vlans / 4); i++)
1651 ksz8_r_vlan_entries(dev, i);
1652
1653 return ksz8_handle_global_errata(ds);
1654}
1655
1656void ksz8_get_caps(struct ksz_device *dev, int port,
1657 struct phylink_config *config)
1658{
1659 config->mac_capabilities = MAC_10 | MAC_100;
1660
1661 /* Silicon Errata Sheet (DS80000830A):
1662 * "Port 1 does not respond to received flow control PAUSE frames"
1663 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
1664 * switches.
1665 */
1666 if (!ksz_is_ksz88x3(dev) || port)
1667 config->mac_capabilities |= MAC_SYM_PAUSE;
1668
1669 /* Asym pause is not supported on KSZ8863 and KSZ8873 */
1670 if (!ksz_is_ksz88x3(dev))
1671 config->mac_capabilities |= MAC_ASYM_PAUSE;
1672}
1673
1674u32 ksz8_get_port_addr(int port, int offset)
1675{
1676 return PORT_CTRL_ADDR(port, offset);
1677}
1678
1679int ksz8_switch_init(struct ksz_device *dev)
1680{
1681 dev->cpu_port = fls(dev->info->cpu_ports) - 1;
1682 dev->phy_port_cnt = dev->info->port_cnt - 1;
1683 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) | dev->info->cpu_ports;
1684
1685 return 0;
1686}
1687
1688void ksz8_switch_exit(struct ksz_device *dev)
1689{
1690 ksz8_reset_switch(dev);
1691}
1692
1693MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1694MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1695MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Microchip KSZ8795 switch driver
4 *
5 * Copyright (C) 2017 Microchip Technology Inc.
6 * Tristram Ha <Tristram.Ha@microchip.com>
7 */
8
9#include <linux/bitfield.h>
10#include <linux/delay.h>
11#include <linux/export.h>
12#include <linux/gpio.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/platform_data/microchip-ksz.h>
16#include <linux/phy.h>
17#include <linux/etherdevice.h>
18#include <linux/if_bridge.h>
19#include <linux/micrel_phy.h>
20#include <net/dsa.h>
21#include <net/switchdev.h>
22#include <linux/phylink.h>
23
24#include "ksz_common.h"
25#include "ksz8795_reg.h"
26#include "ksz8.h"
27
28static const u8 ksz8795_regs[] = {
29 [REG_IND_CTRL_0] = 0x6E,
30 [REG_IND_DATA_8] = 0x70,
31 [REG_IND_DATA_CHECK] = 0x72,
32 [REG_IND_DATA_HI] = 0x71,
33 [REG_IND_DATA_LO] = 0x75,
34 [REG_IND_MIB_CHECK] = 0x74,
35 [P_FORCE_CTRL] = 0x0C,
36 [P_LINK_STATUS] = 0x0E,
37 [P_LOCAL_CTRL] = 0x07,
38 [P_NEG_RESTART_CTRL] = 0x0D,
39 [P_REMOTE_STATUS] = 0x08,
40 [P_SPEED_STATUS] = 0x09,
41 [S_TAIL_TAG_CTRL] = 0x0C,
42};
43
44static const u32 ksz8795_masks[] = {
45 [PORT_802_1P_REMAPPING] = BIT(7),
46 [SW_TAIL_TAG_ENABLE] = BIT(1),
47 [MIB_COUNTER_OVERFLOW] = BIT(6),
48 [MIB_COUNTER_VALID] = BIT(5),
49 [VLAN_TABLE_FID] = GENMASK(6, 0),
50 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
51 [VLAN_TABLE_VALID] = BIT(12),
52 [STATIC_MAC_TABLE_VALID] = BIT(21),
53 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
54 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
55 [STATIC_MAC_TABLE_OVERRIDE] = BIT(26),
56 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(24, 20),
57 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
58 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(8),
59 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
60 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
61 [DYNAMIC_MAC_TABLE_FID] = GENMASK(26, 20),
62 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
63 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
64};
65
66static const u8 ksz8795_shifts[] = {
67 [VLAN_TABLE_MEMBERSHIP_S] = 7,
68 [VLAN_TABLE] = 16,
69 [STATIC_MAC_FWD_PORTS] = 16,
70 [STATIC_MAC_FID] = 24,
71 [DYNAMIC_MAC_ENTRIES_H] = 3,
72 [DYNAMIC_MAC_ENTRIES] = 29,
73 [DYNAMIC_MAC_FID] = 16,
74 [DYNAMIC_MAC_TIMESTAMP] = 27,
75 [DYNAMIC_MAC_SRC_PORT] = 24,
76};
77
78static const u8 ksz8863_regs[] = {
79 [REG_IND_CTRL_0] = 0x79,
80 [REG_IND_DATA_8] = 0x7B,
81 [REG_IND_DATA_CHECK] = 0x7B,
82 [REG_IND_DATA_HI] = 0x7C,
83 [REG_IND_DATA_LO] = 0x80,
84 [REG_IND_MIB_CHECK] = 0x80,
85 [P_FORCE_CTRL] = 0x0C,
86 [P_LINK_STATUS] = 0x0E,
87 [P_LOCAL_CTRL] = 0x0C,
88 [P_NEG_RESTART_CTRL] = 0x0D,
89 [P_REMOTE_STATUS] = 0x0E,
90 [P_SPEED_STATUS] = 0x0F,
91 [S_TAIL_TAG_CTRL] = 0x03,
92};
93
94static const u32 ksz8863_masks[] = {
95 [PORT_802_1P_REMAPPING] = BIT(3),
96 [SW_TAIL_TAG_ENABLE] = BIT(6),
97 [MIB_COUNTER_OVERFLOW] = BIT(7),
98 [MIB_COUNTER_VALID] = BIT(6),
99 [VLAN_TABLE_FID] = GENMASK(15, 12),
100 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
101 [VLAN_TABLE_VALID] = BIT(19),
102 [STATIC_MAC_TABLE_VALID] = BIT(19),
103 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
104 [STATIC_MAC_TABLE_FID] = GENMASK(29, 26),
105 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
106 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
107 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(5, 0),
108 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
109 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
110 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 28),
111 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
112 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
113 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
114};
115
116static u8 ksz8863_shifts[] = {
117 [VLAN_TABLE_MEMBERSHIP_S] = 16,
118 [STATIC_MAC_FWD_PORTS] = 16,
119 [STATIC_MAC_FID] = 22,
120 [DYNAMIC_MAC_ENTRIES_H] = 3,
121 [DYNAMIC_MAC_ENTRIES] = 24,
122 [DYNAMIC_MAC_FID] = 16,
123 [DYNAMIC_MAC_TIMESTAMP] = 24,
124 [DYNAMIC_MAC_SRC_PORT] = 20,
125};
126
127struct mib_names {
128 char string[ETH_GSTRING_LEN];
129};
130
131static const struct mib_names ksz87xx_mib_names[] = {
132 { "rx_hi" },
133 { "rx_undersize" },
134 { "rx_fragments" },
135 { "rx_oversize" },
136 { "rx_jabbers" },
137 { "rx_symbol_err" },
138 { "rx_crc_err" },
139 { "rx_align_err" },
140 { "rx_mac_ctrl" },
141 { "rx_pause" },
142 { "rx_bcast" },
143 { "rx_mcast" },
144 { "rx_ucast" },
145 { "rx_64_or_less" },
146 { "rx_65_127" },
147 { "rx_128_255" },
148 { "rx_256_511" },
149 { "rx_512_1023" },
150 { "rx_1024_1522" },
151 { "rx_1523_2000" },
152 { "rx_2001" },
153 { "tx_hi" },
154 { "tx_late_col" },
155 { "tx_pause" },
156 { "tx_bcast" },
157 { "tx_mcast" },
158 { "tx_ucast" },
159 { "tx_deferred" },
160 { "tx_total_col" },
161 { "tx_exc_col" },
162 { "tx_single_col" },
163 { "tx_mult_col" },
164 { "rx_total" },
165 { "tx_total" },
166 { "rx_discards" },
167 { "tx_discards" },
168};
169
170static const struct mib_names ksz88xx_mib_names[] = {
171 { "rx" },
172 { "rx_hi" },
173 { "rx_undersize" },
174 { "rx_fragments" },
175 { "rx_oversize" },
176 { "rx_jabbers" },
177 { "rx_symbol_err" },
178 { "rx_crc_err" },
179 { "rx_align_err" },
180 { "rx_mac_ctrl" },
181 { "rx_pause" },
182 { "rx_bcast" },
183 { "rx_mcast" },
184 { "rx_ucast" },
185 { "rx_64_or_less" },
186 { "rx_65_127" },
187 { "rx_128_255" },
188 { "rx_256_511" },
189 { "rx_512_1023" },
190 { "rx_1024_1522" },
191 { "tx" },
192 { "tx_hi" },
193 { "tx_late_col" },
194 { "tx_pause" },
195 { "tx_bcast" },
196 { "tx_mcast" },
197 { "tx_ucast" },
198 { "tx_deferred" },
199 { "tx_total_col" },
200 { "tx_exc_col" },
201 { "tx_single_col" },
202 { "tx_mult_col" },
203 { "rx_discards" },
204 { "tx_discards" },
205};
206
207static bool ksz_is_ksz88x3(struct ksz_device *dev)
208{
209 return dev->chip_id == 0x8830;
210}
211
212static void ksz_cfg(struct ksz_device *dev, u32 addr, u8 bits, bool set)
213{
214 regmap_update_bits(dev->regmap[0], addr, bits, set ? bits : 0);
215}
216
217static void ksz_port_cfg(struct ksz_device *dev, int port, int offset, u8 bits,
218 bool set)
219{
220 regmap_update_bits(dev->regmap[0], PORT_CTRL_ADDR(port, offset),
221 bits, set ? bits : 0);
222}
223
224static int ksz8_reset_switch(struct ksz_device *dev)
225{
226 if (ksz_is_ksz88x3(dev)) {
227 /* reset switch */
228 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
229 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, true);
230 ksz_cfg(dev, KSZ8863_REG_SW_RESET,
231 KSZ8863_GLOBAL_SOFTWARE_RESET | KSZ8863_PCS_RESET, false);
232 } else {
233 /* reset switch */
234 ksz_write8(dev, REG_POWER_MANAGEMENT_1,
235 SW_SOFTWARE_POWER_DOWN << SW_POWER_MANAGEMENT_MODE_S);
236 ksz_write8(dev, REG_POWER_MANAGEMENT_1, 0);
237 }
238
239 return 0;
240}
241
242static void ksz8795_set_prio_queue(struct ksz_device *dev, int port, int queue)
243{
244 u8 hi, lo;
245
246 /* Number of queues can only be 1, 2, or 4. */
247 switch (queue) {
248 case 4:
249 case 3:
250 queue = PORT_QUEUE_SPLIT_4;
251 break;
252 case 2:
253 queue = PORT_QUEUE_SPLIT_2;
254 break;
255 default:
256 queue = PORT_QUEUE_SPLIT_1;
257 }
258 ksz_pread8(dev, port, REG_PORT_CTRL_0, &lo);
259 ksz_pread8(dev, port, P_DROP_TAG_CTRL, &hi);
260 lo &= ~PORT_QUEUE_SPLIT_L;
261 if (queue & PORT_QUEUE_SPLIT_2)
262 lo |= PORT_QUEUE_SPLIT_L;
263 hi &= ~PORT_QUEUE_SPLIT_H;
264 if (queue & PORT_QUEUE_SPLIT_4)
265 hi |= PORT_QUEUE_SPLIT_H;
266 ksz_pwrite8(dev, port, REG_PORT_CTRL_0, lo);
267 ksz_pwrite8(dev, port, P_DROP_TAG_CTRL, hi);
268
269 /* Default is port based for egress rate limit. */
270 if (queue != PORT_QUEUE_SPLIT_1)
271 ksz_cfg(dev, REG_SW_CTRL_19, SW_OUT_RATE_LIMIT_QUEUE_BASED,
272 true);
273}
274
275static void ksz8_r_mib_cnt(struct ksz_device *dev, int port, u16 addr, u64 *cnt)
276{
277 struct ksz8 *ksz8 = dev->priv;
278 const u32 *masks;
279 const u8 *regs;
280 u16 ctrl_addr;
281 u32 data;
282 u8 check;
283 int loop;
284
285 masks = ksz8->masks;
286 regs = ksz8->regs;
287
288 ctrl_addr = addr + dev->reg_mib_cnt * port;
289 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
290
291 mutex_lock(&dev->alu_mutex);
292 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
293
294 /* It is almost guaranteed to always read the valid bit because of
295 * slow SPI speed.
296 */
297 for (loop = 2; loop > 0; loop--) {
298 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
299
300 if (check & masks[MIB_COUNTER_VALID]) {
301 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
302 if (check & masks[MIB_COUNTER_OVERFLOW])
303 *cnt += MIB_COUNTER_VALUE + 1;
304 *cnt += data & MIB_COUNTER_VALUE;
305 break;
306 }
307 }
308 mutex_unlock(&dev->alu_mutex);
309}
310
311static void ksz8795_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
312 u64 *dropped, u64 *cnt)
313{
314 struct ksz8 *ksz8 = dev->priv;
315 const u32 *masks;
316 const u8 *regs;
317 u16 ctrl_addr;
318 u32 data;
319 u8 check;
320 int loop;
321
322 masks = ksz8->masks;
323 regs = ksz8->regs;
324
325 addr -= dev->reg_mib_cnt;
326 ctrl_addr = (KSZ8795_MIB_TOTAL_RX_1 - KSZ8795_MIB_TOTAL_RX_0) * port;
327 ctrl_addr += addr + KSZ8795_MIB_TOTAL_RX_0;
328 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
329
330 mutex_lock(&dev->alu_mutex);
331 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
332
333 /* It is almost guaranteed to always read the valid bit because of
334 * slow SPI speed.
335 */
336 for (loop = 2; loop > 0; loop--) {
337 ksz_read8(dev, regs[REG_IND_MIB_CHECK], &check);
338
339 if (check & masks[MIB_COUNTER_VALID]) {
340 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
341 if (addr < 2) {
342 u64 total;
343
344 total = check & MIB_TOTAL_BYTES_H;
345 total <<= 32;
346 *cnt += total;
347 *cnt += data;
348 if (check & masks[MIB_COUNTER_OVERFLOW]) {
349 total = MIB_TOTAL_BYTES_H + 1;
350 total <<= 32;
351 *cnt += total;
352 }
353 } else {
354 if (check & masks[MIB_COUNTER_OVERFLOW])
355 *cnt += MIB_PACKET_DROPPED + 1;
356 *cnt += data & MIB_PACKET_DROPPED;
357 }
358 break;
359 }
360 }
361 mutex_unlock(&dev->alu_mutex);
362}
363
364static void ksz8863_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
365 u64 *dropped, u64 *cnt)
366{
367 struct ksz8 *ksz8 = dev->priv;
368 const u8 *regs = ksz8->regs;
369 u32 *last = (u32 *)dropped;
370 u16 ctrl_addr;
371 u32 data;
372 u32 cur;
373
374 addr -= dev->reg_mib_cnt;
375 ctrl_addr = addr ? KSZ8863_MIB_PACKET_DROPPED_TX_0 :
376 KSZ8863_MIB_PACKET_DROPPED_RX_0;
377 ctrl_addr += port;
378 ctrl_addr |= IND_ACC_TABLE(TABLE_MIB | TABLE_READ);
379
380 mutex_lock(&dev->alu_mutex);
381 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
382 ksz_read32(dev, regs[REG_IND_DATA_LO], &data);
383 mutex_unlock(&dev->alu_mutex);
384
385 data &= MIB_PACKET_DROPPED;
386 cur = last[addr];
387 if (data != cur) {
388 last[addr] = data;
389 if (data < cur)
390 data += MIB_PACKET_DROPPED + 1;
391 data -= cur;
392 *cnt += data;
393 }
394}
395
396static void ksz8_r_mib_pkt(struct ksz_device *dev, int port, u16 addr,
397 u64 *dropped, u64 *cnt)
398{
399 if (ksz_is_ksz88x3(dev))
400 ksz8863_r_mib_pkt(dev, port, addr, dropped, cnt);
401 else
402 ksz8795_r_mib_pkt(dev, port, addr, dropped, cnt);
403}
404
405static void ksz8_freeze_mib(struct ksz_device *dev, int port, bool freeze)
406{
407 if (ksz_is_ksz88x3(dev))
408 return;
409
410 /* enable the port for flush/freeze function */
411 if (freeze)
412 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
413 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FREEZE, freeze);
414
415 /* disable the port after freeze is done */
416 if (!freeze)
417 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
418}
419
420static void ksz8_port_init_cnt(struct ksz_device *dev, int port)
421{
422 struct ksz_port_mib *mib = &dev->ports[port].mib;
423 u64 *dropped;
424
425 if (!ksz_is_ksz88x3(dev)) {
426 /* flush all enabled port MIB counters */
427 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), true);
428 ksz_cfg(dev, REG_SW_CTRL_6, SW_MIB_COUNTER_FLUSH, true);
429 ksz_cfg(dev, REG_SW_CTRL_6, BIT(port), false);
430 }
431
432 mib->cnt_ptr = 0;
433
434 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
435 while (mib->cnt_ptr < dev->reg_mib_cnt) {
436 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
437 &mib->counters[mib->cnt_ptr]);
438 ++mib->cnt_ptr;
439 }
440
441 /* last one in storage */
442 dropped = &mib->counters[dev->mib_cnt];
443
444 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
445 while (mib->cnt_ptr < dev->mib_cnt) {
446 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
447 dropped, &mib->counters[mib->cnt_ptr]);
448 ++mib->cnt_ptr;
449 }
450 mib->cnt_ptr = 0;
451 memset(mib->counters, 0, dev->mib_cnt * sizeof(u64));
452}
453
454static void ksz8_r_table(struct ksz_device *dev, int table, u16 addr, u64 *data)
455{
456 struct ksz8 *ksz8 = dev->priv;
457 const u8 *regs = ksz8->regs;
458 u16 ctrl_addr;
459
460 ctrl_addr = IND_ACC_TABLE(table | TABLE_READ) | addr;
461
462 mutex_lock(&dev->alu_mutex);
463 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
464 ksz_read64(dev, regs[REG_IND_DATA_HI], data);
465 mutex_unlock(&dev->alu_mutex);
466}
467
468static void ksz8_w_table(struct ksz_device *dev, int table, u16 addr, u64 data)
469{
470 struct ksz8 *ksz8 = dev->priv;
471 const u8 *regs = ksz8->regs;
472 u16 ctrl_addr;
473
474 ctrl_addr = IND_ACC_TABLE(table) | addr;
475
476 mutex_lock(&dev->alu_mutex);
477 ksz_write64(dev, regs[REG_IND_DATA_HI], data);
478 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
479 mutex_unlock(&dev->alu_mutex);
480}
481
482static int ksz8_valid_dyn_entry(struct ksz_device *dev, u8 *data)
483{
484 struct ksz8 *ksz8 = dev->priv;
485 int timeout = 100;
486 const u32 *masks;
487 const u8 *regs;
488
489 masks = ksz8->masks;
490 regs = ksz8->regs;
491
492 do {
493 ksz_read8(dev, regs[REG_IND_DATA_CHECK], data);
494 timeout--;
495 } while ((*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) && timeout);
496
497 /* Entry is not ready for accessing. */
498 if (*data & masks[DYNAMIC_MAC_TABLE_NOT_READY]) {
499 return -EAGAIN;
500 /* Entry is ready for accessing. */
501 } else {
502 ksz_read8(dev, regs[REG_IND_DATA_8], data);
503
504 /* There is no valid entry in the table. */
505 if (*data & masks[DYNAMIC_MAC_TABLE_MAC_EMPTY])
506 return -ENXIO;
507 }
508 return 0;
509}
510
511static int ksz8_r_dyn_mac_table(struct ksz_device *dev, u16 addr,
512 u8 *mac_addr, u8 *fid, u8 *src_port,
513 u8 *timestamp, u16 *entries)
514{
515 struct ksz8 *ksz8 = dev->priv;
516 u32 data_hi, data_lo;
517 const u8 *shifts;
518 const u32 *masks;
519 const u8 *regs;
520 u16 ctrl_addr;
521 u8 data;
522 int rc;
523
524 shifts = ksz8->shifts;
525 masks = ksz8->masks;
526 regs = ksz8->regs;
527
528 ctrl_addr = IND_ACC_TABLE(TABLE_DYNAMIC_MAC | TABLE_READ) | addr;
529
530 mutex_lock(&dev->alu_mutex);
531 ksz_write16(dev, regs[REG_IND_CTRL_0], ctrl_addr);
532
533 rc = ksz8_valid_dyn_entry(dev, &data);
534 if (rc == -EAGAIN) {
535 if (addr == 0)
536 *entries = 0;
537 } else if (rc == -ENXIO) {
538 *entries = 0;
539 /* At least one valid entry in the table. */
540 } else {
541 u64 buf = 0;
542 int cnt;
543
544 ksz_read64(dev, regs[REG_IND_DATA_HI], &buf);
545 data_hi = (u32)(buf >> 32);
546 data_lo = (u32)buf;
547
548 /* Check out how many valid entry in the table. */
549 cnt = data & masks[DYNAMIC_MAC_TABLE_ENTRIES_H];
550 cnt <<= shifts[DYNAMIC_MAC_ENTRIES_H];
551 cnt |= (data_hi & masks[DYNAMIC_MAC_TABLE_ENTRIES]) >>
552 shifts[DYNAMIC_MAC_ENTRIES];
553 *entries = cnt + 1;
554
555 *fid = (data_hi & masks[DYNAMIC_MAC_TABLE_FID]) >>
556 shifts[DYNAMIC_MAC_FID];
557 *src_port = (data_hi & masks[DYNAMIC_MAC_TABLE_SRC_PORT]) >>
558 shifts[DYNAMIC_MAC_SRC_PORT];
559 *timestamp = (data_hi & masks[DYNAMIC_MAC_TABLE_TIMESTAMP]) >>
560 shifts[DYNAMIC_MAC_TIMESTAMP];
561
562 mac_addr[5] = (u8)data_lo;
563 mac_addr[4] = (u8)(data_lo >> 8);
564 mac_addr[3] = (u8)(data_lo >> 16);
565 mac_addr[2] = (u8)(data_lo >> 24);
566
567 mac_addr[1] = (u8)data_hi;
568 mac_addr[0] = (u8)(data_hi >> 8);
569 rc = 0;
570 }
571 mutex_unlock(&dev->alu_mutex);
572
573 return rc;
574}
575
576static int ksz8_r_sta_mac_table(struct ksz_device *dev, u16 addr,
577 struct alu_struct *alu)
578{
579 struct ksz8 *ksz8 = dev->priv;
580 u32 data_hi, data_lo;
581 const u8 *shifts;
582 const u32 *masks;
583 u64 data;
584
585 shifts = ksz8->shifts;
586 masks = ksz8->masks;
587
588 ksz8_r_table(dev, TABLE_STATIC_MAC, addr, &data);
589 data_hi = data >> 32;
590 data_lo = (u32)data;
591 if (data_hi & (masks[STATIC_MAC_TABLE_VALID] |
592 masks[STATIC_MAC_TABLE_OVERRIDE])) {
593 alu->mac[5] = (u8)data_lo;
594 alu->mac[4] = (u8)(data_lo >> 8);
595 alu->mac[3] = (u8)(data_lo >> 16);
596 alu->mac[2] = (u8)(data_lo >> 24);
597 alu->mac[1] = (u8)data_hi;
598 alu->mac[0] = (u8)(data_hi >> 8);
599 alu->port_forward =
600 (data_hi & masks[STATIC_MAC_TABLE_FWD_PORTS]) >>
601 shifts[STATIC_MAC_FWD_PORTS];
602 alu->is_override =
603 (data_hi & masks[STATIC_MAC_TABLE_OVERRIDE]) ? 1 : 0;
604 data_hi >>= 1;
605 alu->is_static = true;
606 alu->is_use_fid =
607 (data_hi & masks[STATIC_MAC_TABLE_USE_FID]) ? 1 : 0;
608 alu->fid = (data_hi & masks[STATIC_MAC_TABLE_FID]) >>
609 shifts[STATIC_MAC_FID];
610 return 0;
611 }
612 return -ENXIO;
613}
614
615static void ksz8_w_sta_mac_table(struct ksz_device *dev, u16 addr,
616 struct alu_struct *alu)
617{
618 struct ksz8 *ksz8 = dev->priv;
619 u32 data_hi, data_lo;
620 const u8 *shifts;
621 const u32 *masks;
622 u64 data;
623
624 shifts = ksz8->shifts;
625 masks = ksz8->masks;
626
627 data_lo = ((u32)alu->mac[2] << 24) |
628 ((u32)alu->mac[3] << 16) |
629 ((u32)alu->mac[4] << 8) | alu->mac[5];
630 data_hi = ((u32)alu->mac[0] << 8) | alu->mac[1];
631 data_hi |= (u32)alu->port_forward << shifts[STATIC_MAC_FWD_PORTS];
632
633 if (alu->is_override)
634 data_hi |= masks[STATIC_MAC_TABLE_OVERRIDE];
635 if (alu->is_use_fid) {
636 data_hi |= masks[STATIC_MAC_TABLE_USE_FID];
637 data_hi |= (u32)alu->fid << shifts[STATIC_MAC_FID];
638 }
639 if (alu->is_static)
640 data_hi |= masks[STATIC_MAC_TABLE_VALID];
641 else
642 data_hi &= ~masks[STATIC_MAC_TABLE_OVERRIDE];
643
644 data = (u64)data_hi << 32 | data_lo;
645 ksz8_w_table(dev, TABLE_STATIC_MAC, addr, data);
646}
647
648static void ksz8_from_vlan(struct ksz_device *dev, u32 vlan, u8 *fid,
649 u8 *member, u8 *valid)
650{
651 struct ksz8 *ksz8 = dev->priv;
652 const u8 *shifts;
653 const u32 *masks;
654
655 shifts = ksz8->shifts;
656 masks = ksz8->masks;
657
658 *fid = vlan & masks[VLAN_TABLE_FID];
659 *member = (vlan & masks[VLAN_TABLE_MEMBERSHIP]) >>
660 shifts[VLAN_TABLE_MEMBERSHIP_S];
661 *valid = !!(vlan & masks[VLAN_TABLE_VALID]);
662}
663
664static void ksz8_to_vlan(struct ksz_device *dev, u8 fid, u8 member, u8 valid,
665 u16 *vlan)
666{
667 struct ksz8 *ksz8 = dev->priv;
668 const u8 *shifts;
669 const u32 *masks;
670
671 shifts = ksz8->shifts;
672 masks = ksz8->masks;
673
674 *vlan = fid;
675 *vlan |= (u16)member << shifts[VLAN_TABLE_MEMBERSHIP_S];
676 if (valid)
677 *vlan |= masks[VLAN_TABLE_VALID];
678}
679
680static void ksz8_r_vlan_entries(struct ksz_device *dev, u16 addr)
681{
682 struct ksz8 *ksz8 = dev->priv;
683 const u8 *shifts;
684 u64 data;
685 int i;
686
687 shifts = ksz8->shifts;
688
689 ksz8_r_table(dev, TABLE_VLAN, addr, &data);
690 addr *= 4;
691 for (i = 0; i < 4; i++) {
692 dev->vlan_cache[addr + i].table[0] = (u16)data;
693 data >>= shifts[VLAN_TABLE];
694 }
695}
696
697static void ksz8_r_vlan_table(struct ksz_device *dev, u16 vid, u16 *vlan)
698{
699 int index;
700 u16 *data;
701 u16 addr;
702 u64 buf;
703
704 data = (u16 *)&buf;
705 addr = vid / 4;
706 index = vid & 3;
707 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
708 *vlan = data[index];
709}
710
711static void ksz8_w_vlan_table(struct ksz_device *dev, u16 vid, u16 vlan)
712{
713 int index;
714 u16 *data;
715 u16 addr;
716 u64 buf;
717
718 data = (u16 *)&buf;
719 addr = vid / 4;
720 index = vid & 3;
721 ksz8_r_table(dev, TABLE_VLAN, addr, &buf);
722 data[index] = vlan;
723 dev->vlan_cache[vid].table[0] = vlan;
724 ksz8_w_table(dev, TABLE_VLAN, addr, buf);
725}
726
727static void ksz8_r_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 *val)
728{
729 struct ksz8 *ksz8 = dev->priv;
730 u8 restart, speed, ctrl, link;
731 const u8 *regs = ksz8->regs;
732 int processed = true;
733 u8 val1, val2;
734 u16 data = 0;
735 u8 p = phy;
736
737 switch (reg) {
738 case MII_BMCR:
739 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
740 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
741 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
742 if (restart & PORT_PHY_LOOPBACK)
743 data |= BMCR_LOOPBACK;
744 if (ctrl & PORT_FORCE_100_MBIT)
745 data |= BMCR_SPEED100;
746 if (ksz_is_ksz88x3(dev)) {
747 if ((ctrl & PORT_AUTO_NEG_ENABLE))
748 data |= BMCR_ANENABLE;
749 } else {
750 if (!(ctrl & PORT_AUTO_NEG_DISABLE))
751 data |= BMCR_ANENABLE;
752 }
753 if (restart & PORT_POWER_DOWN)
754 data |= BMCR_PDOWN;
755 if (restart & PORT_AUTO_NEG_RESTART)
756 data |= BMCR_ANRESTART;
757 if (ctrl & PORT_FORCE_FULL_DUPLEX)
758 data |= BMCR_FULLDPLX;
759 if (speed & PORT_HP_MDIX)
760 data |= KSZ886X_BMCR_HP_MDIX;
761 if (restart & PORT_FORCE_MDIX)
762 data |= KSZ886X_BMCR_FORCE_MDI;
763 if (restart & PORT_AUTO_MDIX_DISABLE)
764 data |= KSZ886X_BMCR_DISABLE_AUTO_MDIX;
765 if (restart & PORT_TX_DISABLE)
766 data |= KSZ886X_BMCR_DISABLE_TRANSMIT;
767 if (restart & PORT_LED_OFF)
768 data |= KSZ886X_BMCR_DISABLE_LED;
769 break;
770 case MII_BMSR:
771 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
772 data = BMSR_100FULL |
773 BMSR_100HALF |
774 BMSR_10FULL |
775 BMSR_10HALF |
776 BMSR_ANEGCAPABLE;
777 if (link & PORT_AUTO_NEG_COMPLETE)
778 data |= BMSR_ANEGCOMPLETE;
779 if (link & PORT_STAT_LINK_GOOD)
780 data |= BMSR_LSTATUS;
781 break;
782 case MII_PHYSID1:
783 data = KSZ8795_ID_HI;
784 break;
785 case MII_PHYSID2:
786 if (ksz_is_ksz88x3(dev))
787 data = KSZ8863_ID_LO;
788 else
789 data = KSZ8795_ID_LO;
790 break;
791 case MII_ADVERTISE:
792 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
793 data = ADVERTISE_CSMA;
794 if (ctrl & PORT_AUTO_NEG_SYM_PAUSE)
795 data |= ADVERTISE_PAUSE_CAP;
796 if (ctrl & PORT_AUTO_NEG_100BTX_FD)
797 data |= ADVERTISE_100FULL;
798 if (ctrl & PORT_AUTO_NEG_100BTX)
799 data |= ADVERTISE_100HALF;
800 if (ctrl & PORT_AUTO_NEG_10BT_FD)
801 data |= ADVERTISE_10FULL;
802 if (ctrl & PORT_AUTO_NEG_10BT)
803 data |= ADVERTISE_10HALF;
804 break;
805 case MII_LPA:
806 ksz_pread8(dev, p, regs[P_REMOTE_STATUS], &link);
807 data = LPA_SLCT;
808 if (link & PORT_REMOTE_SYM_PAUSE)
809 data |= LPA_PAUSE_CAP;
810 if (link & PORT_REMOTE_100BTX_FD)
811 data |= LPA_100FULL;
812 if (link & PORT_REMOTE_100BTX)
813 data |= LPA_100HALF;
814 if (link & PORT_REMOTE_10BT_FD)
815 data |= LPA_10FULL;
816 if (link & PORT_REMOTE_10BT)
817 data |= LPA_10HALF;
818 if (data & ~LPA_SLCT)
819 data |= LPA_LPACK;
820 break;
821 case PHY_REG_LINK_MD:
822 ksz_pread8(dev, p, REG_PORT_LINK_MD_CTRL, &val1);
823 ksz_pread8(dev, p, REG_PORT_LINK_MD_RESULT, &val2);
824 if (val1 & PORT_START_CABLE_DIAG)
825 data |= PHY_START_CABLE_DIAG;
826
827 if (val1 & PORT_CABLE_10M_SHORT)
828 data |= PHY_CABLE_10M_SHORT;
829
830 data |= FIELD_PREP(PHY_CABLE_DIAG_RESULT_M,
831 FIELD_GET(PORT_CABLE_DIAG_RESULT_M, val1));
832
833 data |= FIELD_PREP(PHY_CABLE_FAULT_COUNTER_M,
834 (FIELD_GET(PORT_CABLE_FAULT_COUNTER_H, val1) << 8) |
835 FIELD_GET(PORT_CABLE_FAULT_COUNTER_L, val2));
836 break;
837 case PHY_REG_PHY_CTRL:
838 ksz_pread8(dev, p, regs[P_LINK_STATUS], &link);
839 if (link & PORT_MDIX_STATUS)
840 data |= KSZ886X_CTRL_MDIX_STAT;
841 break;
842 default:
843 processed = false;
844 break;
845 }
846 if (processed)
847 *val = data;
848}
849
850static void ksz8_w_phy(struct ksz_device *dev, u16 phy, u16 reg, u16 val)
851{
852 struct ksz8 *ksz8 = dev->priv;
853 u8 restart, speed, ctrl, data;
854 const u8 *regs = ksz8->regs;
855 u8 p = phy;
856
857 switch (reg) {
858 case MII_BMCR:
859
860 /* Do not support PHY reset function. */
861 if (val & BMCR_RESET)
862 break;
863 ksz_pread8(dev, p, regs[P_SPEED_STATUS], &speed);
864 data = speed;
865 if (val & KSZ886X_BMCR_HP_MDIX)
866 data |= PORT_HP_MDIX;
867 else
868 data &= ~PORT_HP_MDIX;
869 if (data != speed)
870 ksz_pwrite8(dev, p, regs[P_SPEED_STATUS], data);
871 ksz_pread8(dev, p, regs[P_FORCE_CTRL], &ctrl);
872 data = ctrl;
873 if (ksz_is_ksz88x3(dev)) {
874 if ((val & BMCR_ANENABLE))
875 data |= PORT_AUTO_NEG_ENABLE;
876 else
877 data &= ~PORT_AUTO_NEG_ENABLE;
878 } else {
879 if (!(val & BMCR_ANENABLE))
880 data |= PORT_AUTO_NEG_DISABLE;
881 else
882 data &= ~PORT_AUTO_NEG_DISABLE;
883
884 /* Fiber port does not support auto-negotiation. */
885 if (dev->ports[p].fiber)
886 data |= PORT_AUTO_NEG_DISABLE;
887 }
888
889 if (val & BMCR_SPEED100)
890 data |= PORT_FORCE_100_MBIT;
891 else
892 data &= ~PORT_FORCE_100_MBIT;
893 if (val & BMCR_FULLDPLX)
894 data |= PORT_FORCE_FULL_DUPLEX;
895 else
896 data &= ~PORT_FORCE_FULL_DUPLEX;
897 if (data != ctrl)
898 ksz_pwrite8(dev, p, regs[P_FORCE_CTRL], data);
899 ksz_pread8(dev, p, regs[P_NEG_RESTART_CTRL], &restart);
900 data = restart;
901 if (val & KSZ886X_BMCR_DISABLE_LED)
902 data |= PORT_LED_OFF;
903 else
904 data &= ~PORT_LED_OFF;
905 if (val & KSZ886X_BMCR_DISABLE_TRANSMIT)
906 data |= PORT_TX_DISABLE;
907 else
908 data &= ~PORT_TX_DISABLE;
909 if (val & BMCR_ANRESTART)
910 data |= PORT_AUTO_NEG_RESTART;
911 else
912 data &= ~(PORT_AUTO_NEG_RESTART);
913 if (val & BMCR_PDOWN)
914 data |= PORT_POWER_DOWN;
915 else
916 data &= ~PORT_POWER_DOWN;
917 if (val & KSZ886X_BMCR_DISABLE_AUTO_MDIX)
918 data |= PORT_AUTO_MDIX_DISABLE;
919 else
920 data &= ~PORT_AUTO_MDIX_DISABLE;
921 if (val & KSZ886X_BMCR_FORCE_MDI)
922 data |= PORT_FORCE_MDIX;
923 else
924 data &= ~PORT_FORCE_MDIX;
925 if (val & BMCR_LOOPBACK)
926 data |= PORT_PHY_LOOPBACK;
927 else
928 data &= ~PORT_PHY_LOOPBACK;
929 if (data != restart)
930 ksz_pwrite8(dev, p, regs[P_NEG_RESTART_CTRL], data);
931 break;
932 case MII_ADVERTISE:
933 ksz_pread8(dev, p, regs[P_LOCAL_CTRL], &ctrl);
934 data = ctrl;
935 data &= ~(PORT_AUTO_NEG_SYM_PAUSE |
936 PORT_AUTO_NEG_100BTX_FD |
937 PORT_AUTO_NEG_100BTX |
938 PORT_AUTO_NEG_10BT_FD |
939 PORT_AUTO_NEG_10BT);
940 if (val & ADVERTISE_PAUSE_CAP)
941 data |= PORT_AUTO_NEG_SYM_PAUSE;
942 if (val & ADVERTISE_100FULL)
943 data |= PORT_AUTO_NEG_100BTX_FD;
944 if (val & ADVERTISE_100HALF)
945 data |= PORT_AUTO_NEG_100BTX;
946 if (val & ADVERTISE_10FULL)
947 data |= PORT_AUTO_NEG_10BT_FD;
948 if (val & ADVERTISE_10HALF)
949 data |= PORT_AUTO_NEG_10BT;
950 if (data != ctrl)
951 ksz_pwrite8(dev, p, regs[P_LOCAL_CTRL], data);
952 break;
953 case PHY_REG_LINK_MD:
954 if (val & PHY_START_CABLE_DIAG)
955 ksz_port_cfg(dev, p, REG_PORT_LINK_MD_CTRL, PORT_START_CABLE_DIAG, true);
956 break;
957 default:
958 break;
959 }
960}
961
962static enum dsa_tag_protocol ksz8_get_tag_protocol(struct dsa_switch *ds,
963 int port,
964 enum dsa_tag_protocol mp)
965{
966 struct ksz_device *dev = ds->priv;
967
968 /* ksz88x3 uses the same tag schema as KSZ9893 */
969 return ksz_is_ksz88x3(dev) ?
970 DSA_TAG_PROTO_KSZ9893 : DSA_TAG_PROTO_KSZ8795;
971}
972
973static u32 ksz8_sw_get_phy_flags(struct dsa_switch *ds, int port)
974{
975 /* Silicon Errata Sheet (DS80000830A):
976 * Port 1 does not work with LinkMD Cable-Testing.
977 * Port 1 does not respond to received PAUSE control frames.
978 */
979 if (!port)
980 return MICREL_KSZ8_P1_ERRATA;
981
982 return 0;
983}
984
985static void ksz8_get_strings(struct dsa_switch *ds, int port,
986 u32 stringset, uint8_t *buf)
987{
988 struct ksz_device *dev = ds->priv;
989 int i;
990
991 for (i = 0; i < dev->mib_cnt; i++) {
992 memcpy(buf + i * ETH_GSTRING_LEN,
993 dev->mib_names[i].string, ETH_GSTRING_LEN);
994 }
995}
996
997static void ksz8_cfg_port_member(struct ksz_device *dev, int port, u8 member)
998{
999 u8 data;
1000
1001 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1002 data &= ~PORT_VLAN_MEMBERSHIP;
1003 data |= (member & dev->port_mask);
1004 ksz_pwrite8(dev, port, P_MIRROR_CTRL, data);
1005 dev->ports[port].member = member;
1006}
1007
1008static void ksz8_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1009{
1010 struct ksz_device *dev = ds->priv;
1011 int forward = dev->member;
1012 struct ksz_port *p;
1013 int member = -1;
1014 u8 data;
1015
1016 p = &dev->ports[port];
1017
1018 ksz_pread8(dev, port, P_STP_CTRL, &data);
1019 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1020
1021 switch (state) {
1022 case BR_STATE_DISABLED:
1023 data |= PORT_LEARN_DISABLE;
1024 if (port < dev->phy_port_cnt)
1025 member = 0;
1026 break;
1027 case BR_STATE_LISTENING:
1028 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
1029 if (port < dev->phy_port_cnt &&
1030 p->stp_state == BR_STATE_DISABLED)
1031 member = dev->host_mask | p->vid_member;
1032 break;
1033 case BR_STATE_LEARNING:
1034 data |= PORT_RX_ENABLE;
1035 break;
1036 case BR_STATE_FORWARDING:
1037 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
1038
1039 /* This function is also used internally. */
1040 if (port == dev->cpu_port)
1041 break;
1042
1043 /* Port is a member of a bridge. */
1044 if (dev->br_member & BIT(port)) {
1045 dev->member |= BIT(port);
1046 member = dev->member;
1047 } else {
1048 member = dev->host_mask | p->vid_member;
1049 }
1050 break;
1051 case BR_STATE_BLOCKING:
1052 data |= PORT_LEARN_DISABLE;
1053 if (port < dev->phy_port_cnt &&
1054 p->stp_state == BR_STATE_DISABLED)
1055 member = dev->host_mask | p->vid_member;
1056 break;
1057 default:
1058 dev_err(ds->dev, "invalid STP state: %d\n", state);
1059 return;
1060 }
1061
1062 ksz_pwrite8(dev, port, P_STP_CTRL, data);
1063 p->stp_state = state;
1064 /* Port membership may share register with STP state. */
1065 if (member >= 0 && member != p->member)
1066 ksz8_cfg_port_member(dev, port, (u8)member);
1067
1068 /* Check if forwarding needs to be updated. */
1069 if (state != BR_STATE_FORWARDING) {
1070 if (dev->br_member & BIT(port))
1071 dev->member &= ~BIT(port);
1072 }
1073
1074 /* When topology has changed the function ksz_update_port_member
1075 * should be called to modify port forwarding behavior.
1076 */
1077 if (forward != dev->member)
1078 ksz_update_port_member(dev, port);
1079}
1080
1081static void ksz8_flush_dyn_mac_table(struct ksz_device *dev, int port)
1082{
1083 u8 learn[DSA_MAX_PORTS];
1084 int first, index, cnt;
1085 struct ksz_port *p;
1086
1087 if ((uint)port < dev->port_cnt) {
1088 first = port;
1089 cnt = port + 1;
1090 } else {
1091 /* Flush all ports. */
1092 first = 0;
1093 cnt = dev->port_cnt;
1094 }
1095 for (index = first; index < cnt; index++) {
1096 p = &dev->ports[index];
1097 if (!p->on)
1098 continue;
1099 ksz_pread8(dev, index, P_STP_CTRL, &learn[index]);
1100 if (!(learn[index] & PORT_LEARN_DISABLE))
1101 ksz_pwrite8(dev, index, P_STP_CTRL,
1102 learn[index] | PORT_LEARN_DISABLE);
1103 }
1104 ksz_cfg(dev, S_FLUSH_TABLE_CTRL, SW_FLUSH_DYN_MAC_TABLE, true);
1105 for (index = first; index < cnt; index++) {
1106 p = &dev->ports[index];
1107 if (!p->on)
1108 continue;
1109 if (!(learn[index] & PORT_LEARN_DISABLE))
1110 ksz_pwrite8(dev, index, P_STP_CTRL, learn[index]);
1111 }
1112}
1113
1114static int ksz8_port_vlan_filtering(struct dsa_switch *ds, int port, bool flag,
1115 struct netlink_ext_ack *extack)
1116{
1117 struct ksz_device *dev = ds->priv;
1118
1119 if (ksz_is_ksz88x3(dev))
1120 return -ENOTSUPP;
1121
1122 /* Discard packets with VID not enabled on the switch */
1123 ksz_cfg(dev, S_MIRROR_CTRL, SW_VLAN_ENABLE, flag);
1124
1125 /* Discard packets with VID not enabled on the ingress port */
1126 for (port = 0; port < dev->phy_port_cnt; ++port)
1127 ksz_port_cfg(dev, port, REG_PORT_CTRL_2, PORT_INGRESS_FILTER,
1128 flag);
1129
1130 return 0;
1131}
1132
1133static void ksz8_port_enable_pvid(struct ksz_device *dev, int port, bool state)
1134{
1135 if (ksz_is_ksz88x3(dev)) {
1136 ksz_cfg(dev, REG_SW_INSERT_SRC_PVID,
1137 0x03 << (4 - 2 * port), state);
1138 } else {
1139 ksz_pwrite8(dev, port, REG_PORT_CTRL_12, state ? 0x0f : 0x00);
1140 }
1141}
1142
1143static int ksz8_port_vlan_add(struct dsa_switch *ds, int port,
1144 const struct switchdev_obj_port_vlan *vlan,
1145 struct netlink_ext_ack *extack)
1146{
1147 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1148 struct ksz_device *dev = ds->priv;
1149 struct ksz_port *p = &dev->ports[port];
1150 u16 data, new_pvid = 0;
1151 u8 fid, member, valid;
1152
1153 if (ksz_is_ksz88x3(dev))
1154 return -ENOTSUPP;
1155
1156 /* If a VLAN is added with untagged flag different from the
1157 * port's Remove Tag flag, we need to change the latter.
1158 * Ignore VID 0, which is always untagged.
1159 * Ignore CPU port, which will always be tagged.
1160 */
1161 if (untagged != p->remove_tag && vlan->vid != 0 &&
1162 port != dev->cpu_port) {
1163 unsigned int vid;
1164
1165 /* Reject attempts to add a VLAN that requires the
1166 * Remove Tag flag to be changed, unless there are no
1167 * other VLANs currently configured.
1168 */
1169 for (vid = 1; vid < dev->num_vlans; ++vid) {
1170 /* Skip the VID we are going to add or reconfigure */
1171 if (vid == vlan->vid)
1172 continue;
1173
1174 ksz8_from_vlan(dev, dev->vlan_cache[vid].table[0],
1175 &fid, &member, &valid);
1176 if (valid && (member & BIT(port)))
1177 return -EINVAL;
1178 }
1179
1180 ksz_port_cfg(dev, port, P_TAG_CTRL, PORT_REMOVE_TAG, untagged);
1181 p->remove_tag = untagged;
1182 }
1183
1184 ksz8_r_vlan_table(dev, vlan->vid, &data);
1185 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1186
1187 /* First time to setup the VLAN entry. */
1188 if (!valid) {
1189 /* Need to find a way to map VID to FID. */
1190 fid = 1;
1191 valid = 1;
1192 }
1193 member |= BIT(port);
1194
1195 ksz8_to_vlan(dev, fid, member, valid, &data);
1196 ksz8_w_vlan_table(dev, vlan->vid, data);
1197
1198 /* change PVID */
1199 if (vlan->flags & BRIDGE_VLAN_INFO_PVID)
1200 new_pvid = vlan->vid;
1201
1202 if (new_pvid) {
1203 u16 vid;
1204
1205 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &vid);
1206 vid &= ~VLAN_VID_MASK;
1207 vid |= new_pvid;
1208 ksz_pwrite16(dev, port, REG_PORT_CTRL_VID, vid);
1209
1210 ksz8_port_enable_pvid(dev, port, true);
1211 }
1212
1213 return 0;
1214}
1215
1216static int ksz8_port_vlan_del(struct dsa_switch *ds, int port,
1217 const struct switchdev_obj_port_vlan *vlan)
1218{
1219 struct ksz_device *dev = ds->priv;
1220 u16 data, pvid;
1221 u8 fid, member, valid;
1222
1223 if (ksz_is_ksz88x3(dev))
1224 return -ENOTSUPP;
1225
1226 ksz_pread16(dev, port, REG_PORT_CTRL_VID, &pvid);
1227 pvid = pvid & 0xFFF;
1228
1229 ksz8_r_vlan_table(dev, vlan->vid, &data);
1230 ksz8_from_vlan(dev, data, &fid, &member, &valid);
1231
1232 member &= ~BIT(port);
1233
1234 /* Invalidate the entry if no more member. */
1235 if (!member) {
1236 fid = 0;
1237 valid = 0;
1238 }
1239
1240 ksz8_to_vlan(dev, fid, member, valid, &data);
1241 ksz8_w_vlan_table(dev, vlan->vid, data);
1242
1243 if (pvid == vlan->vid)
1244 ksz8_port_enable_pvid(dev, port, false);
1245
1246 return 0;
1247}
1248
1249static int ksz8_port_mirror_add(struct dsa_switch *ds, int port,
1250 struct dsa_mall_mirror_tc_entry *mirror,
1251 bool ingress)
1252{
1253 struct ksz_device *dev = ds->priv;
1254
1255 if (ingress) {
1256 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, true);
1257 dev->mirror_rx |= BIT(port);
1258 } else {
1259 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, true);
1260 dev->mirror_tx |= BIT(port);
1261 }
1262
1263 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_SNIFFER, false);
1264
1265 /* configure mirror port */
1266 if (dev->mirror_rx || dev->mirror_tx)
1267 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1268 PORT_MIRROR_SNIFFER, true);
1269
1270 return 0;
1271}
1272
1273static void ksz8_port_mirror_del(struct dsa_switch *ds, int port,
1274 struct dsa_mall_mirror_tc_entry *mirror)
1275{
1276 struct ksz_device *dev = ds->priv;
1277 u8 data;
1278
1279 if (mirror->ingress) {
1280 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_RX, false);
1281 dev->mirror_rx &= ~BIT(port);
1282 } else {
1283 ksz_port_cfg(dev, port, P_MIRROR_CTRL, PORT_MIRROR_TX, false);
1284 dev->mirror_tx &= ~BIT(port);
1285 }
1286
1287 ksz_pread8(dev, port, P_MIRROR_CTRL, &data);
1288
1289 if (!dev->mirror_rx && !dev->mirror_tx)
1290 ksz_port_cfg(dev, mirror->to_local_port, P_MIRROR_CTRL,
1291 PORT_MIRROR_SNIFFER, false);
1292}
1293
1294static void ksz8795_cpu_interface_select(struct ksz_device *dev, int port)
1295{
1296 struct ksz_port *p = &dev->ports[port];
1297 u8 data8;
1298
1299 if (!p->interface && dev->compat_interface) {
1300 dev_warn(dev->dev,
1301 "Using legacy switch \"phy-mode\" property, because it is missing on port %d node. "
1302 "Please update your device tree.\n",
1303 port);
1304 p->interface = dev->compat_interface;
1305 }
1306
1307 /* Configure MII interface for proper network communication. */
1308 ksz_read8(dev, REG_PORT_5_CTRL_6, &data8);
1309 data8 &= ~PORT_INTERFACE_TYPE;
1310 data8 &= ~PORT_GMII_1GPS_MODE;
1311 switch (p->interface) {
1312 case PHY_INTERFACE_MODE_MII:
1313 p->phydev.speed = SPEED_100;
1314 break;
1315 case PHY_INTERFACE_MODE_RMII:
1316 data8 |= PORT_INTERFACE_RMII;
1317 p->phydev.speed = SPEED_100;
1318 break;
1319 case PHY_INTERFACE_MODE_GMII:
1320 data8 |= PORT_GMII_1GPS_MODE;
1321 data8 |= PORT_INTERFACE_GMII;
1322 p->phydev.speed = SPEED_1000;
1323 break;
1324 default:
1325 data8 &= ~PORT_RGMII_ID_IN_ENABLE;
1326 data8 &= ~PORT_RGMII_ID_OUT_ENABLE;
1327 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1328 p->interface == PHY_INTERFACE_MODE_RGMII_RXID)
1329 data8 |= PORT_RGMII_ID_IN_ENABLE;
1330 if (p->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1331 p->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1332 data8 |= PORT_RGMII_ID_OUT_ENABLE;
1333 data8 |= PORT_GMII_1GPS_MODE;
1334 data8 |= PORT_INTERFACE_RGMII;
1335 p->phydev.speed = SPEED_1000;
1336 break;
1337 }
1338 ksz_write8(dev, REG_PORT_5_CTRL_6, data8);
1339 p->phydev.duplex = 1;
1340}
1341
1342static void ksz8_port_setup(struct ksz_device *dev, int port, bool cpu_port)
1343{
1344 struct ksz_port *p = &dev->ports[port];
1345 struct ksz8 *ksz8 = dev->priv;
1346 const u32 *masks;
1347 u8 member;
1348
1349 masks = ksz8->masks;
1350
1351 /* enable broadcast storm limit */
1352 ksz_port_cfg(dev, port, P_BCAST_STORM_CTRL, PORT_BROADCAST_STORM, true);
1353
1354 if (!ksz_is_ksz88x3(dev))
1355 ksz8795_set_prio_queue(dev, port, 4);
1356
1357 /* disable DiffServ priority */
1358 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_DIFFSERV_ENABLE, false);
1359
1360 /* replace priority */
1361 ksz_port_cfg(dev, port, P_802_1P_CTRL,
1362 masks[PORT_802_1P_REMAPPING], false);
1363
1364 /* enable 802.1p priority */
1365 ksz_port_cfg(dev, port, P_PRIO_CTRL, PORT_802_1P_ENABLE, true);
1366
1367 if (cpu_port) {
1368 if (!ksz_is_ksz88x3(dev))
1369 ksz8795_cpu_interface_select(dev, port);
1370
1371 member = dev->port_mask;
1372 } else {
1373 member = dev->host_mask | p->vid_member;
1374 }
1375 ksz8_cfg_port_member(dev, port, member);
1376}
1377
1378static void ksz8_config_cpu_port(struct dsa_switch *ds)
1379{
1380 struct ksz_device *dev = ds->priv;
1381 struct ksz8 *ksz8 = dev->priv;
1382 const u8 *regs = ksz8->regs;
1383 struct ksz_port *p;
1384 const u32 *masks;
1385 u8 remote;
1386 int i;
1387
1388 masks = ksz8->masks;
1389
1390 /* Switch marks the maximum frame with extra byte as oversize. */
1391 ksz_cfg(dev, REG_SW_CTRL_2, SW_LEGAL_PACKET_DISABLE, true);
1392 ksz_cfg(dev, regs[S_TAIL_TAG_CTRL], masks[SW_TAIL_TAG_ENABLE], true);
1393
1394 p = &dev->ports[dev->cpu_port];
1395 p->vid_member = dev->port_mask;
1396 p->on = 1;
1397
1398 ksz8_port_setup(dev, dev->cpu_port, true);
1399 dev->member = dev->host_mask;
1400
1401 for (i = 0; i < dev->phy_port_cnt; i++) {
1402 p = &dev->ports[i];
1403
1404 /* Initialize to non-zero so that ksz_cfg_port_member() will
1405 * be called.
1406 */
1407 p->vid_member = BIT(i);
1408 p->member = dev->port_mask;
1409 ksz8_port_stp_state_set(ds, i, BR_STATE_DISABLED);
1410
1411 /* Last port may be disabled. */
1412 if (i == dev->phy_port_cnt)
1413 break;
1414 p->on = 1;
1415 p->phy = 1;
1416 }
1417 for (i = 0; i < dev->phy_port_cnt; i++) {
1418 p = &dev->ports[i];
1419 if (!p->on)
1420 continue;
1421 if (!ksz_is_ksz88x3(dev)) {
1422 ksz_pread8(dev, i, regs[P_REMOTE_STATUS], &remote);
1423 if (remote & PORT_FIBER_MODE)
1424 p->fiber = 1;
1425 }
1426 if (p->fiber)
1427 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1428 true);
1429 else
1430 ksz_port_cfg(dev, i, P_STP_CTRL, PORT_FORCE_FLOW_CTRL,
1431 false);
1432 }
1433}
1434
1435static int ksz8_setup(struct dsa_switch *ds)
1436{
1437 struct ksz_device *dev = ds->priv;
1438 struct alu_struct alu;
1439 int i, ret = 0;
1440
1441 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1442 dev->num_vlans, GFP_KERNEL);
1443 if (!dev->vlan_cache)
1444 return -ENOMEM;
1445
1446 ret = ksz8_reset_switch(dev);
1447 if (ret) {
1448 dev_err(ds->dev, "failed to reset switch\n");
1449 return ret;
1450 }
1451
1452 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_FLOW_CTRL, true);
1453
1454 /* Enable automatic fast aging when link changed detected. */
1455 ksz_cfg(dev, S_LINK_AGING_CTRL, SW_LINK_AUTO_AGING, true);
1456
1457 /* Enable aggressive back off algorithm in half duplex mode. */
1458 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_1,
1459 SW_AGGR_BACKOFF, SW_AGGR_BACKOFF);
1460
1461 /*
1462 * Make sure unicast VLAN boundary is set as default and
1463 * enable no excessive collision drop.
1464 */
1465 regmap_update_bits(dev->regmap[0], REG_SW_CTRL_2,
1466 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP,
1467 UNICAST_VLAN_BOUNDARY | NO_EXC_COLLISION_DROP);
1468
1469 ksz8_config_cpu_port(ds);
1470
1471 ksz_cfg(dev, REG_SW_CTRL_2, MULTICAST_STORM_DISABLE, true);
1472
1473 ksz_cfg(dev, S_REPLACE_VID_CTRL, SW_REPLACE_VID, false);
1474
1475 ksz_cfg(dev, S_MIRROR_CTRL, SW_MIRROR_RX_TX, false);
1476
1477 if (!ksz_is_ksz88x3(dev))
1478 ksz_cfg(dev, REG_SW_CTRL_19, SW_INS_TAG_ENABLE, true);
1479
1480 /* set broadcast storm protection 10% rate */
1481 regmap_update_bits(dev->regmap[1], S_REPLACE_VID_CTRL,
1482 BROADCAST_STORM_RATE,
1483 (BROADCAST_STORM_VALUE *
1484 BROADCAST_STORM_PROT_RATE) / 100);
1485
1486 for (i = 0; i < (dev->num_vlans / 4); i++)
1487 ksz8_r_vlan_entries(dev, i);
1488
1489 /* Setup STP address for STP operation. */
1490 memset(&alu, 0, sizeof(alu));
1491 ether_addr_copy(alu.mac, eth_stp_addr);
1492 alu.is_static = true;
1493 alu.is_override = true;
1494 alu.port_forward = dev->host_mask;
1495
1496 ksz8_w_sta_mac_table(dev, 0, &alu);
1497
1498 ksz_init_mib_timer(dev);
1499
1500 ds->configure_vlan_while_not_filtering = false;
1501
1502 return 0;
1503}
1504
1505static void ksz8_validate(struct dsa_switch *ds, int port,
1506 unsigned long *supported,
1507 struct phylink_link_state *state)
1508{
1509 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1510 struct ksz_device *dev = ds->priv;
1511
1512 if (port == dev->cpu_port) {
1513 if (state->interface != PHY_INTERFACE_MODE_RMII &&
1514 state->interface != PHY_INTERFACE_MODE_MII &&
1515 state->interface != PHY_INTERFACE_MODE_NA)
1516 goto unsupported;
1517 } else {
1518 if (state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1519 state->interface != PHY_INTERFACE_MODE_NA)
1520 goto unsupported;
1521 }
1522
1523 /* Allow all the expected bits */
1524 phylink_set_port_modes(mask);
1525 phylink_set(mask, Autoneg);
1526
1527 /* Silicon Errata Sheet (DS80000830A):
1528 * "Port 1 does not respond to received flow control PAUSE frames"
1529 * So, disable Pause support on "Port 1" (port == 0) for all ksz88x3
1530 * switches.
1531 */
1532 if (!ksz_is_ksz88x3(dev) || port)
1533 phylink_set(mask, Pause);
1534
1535 /* Asym pause is not supported on KSZ8863 and KSZ8873 */
1536 if (!ksz_is_ksz88x3(dev))
1537 phylink_set(mask, Asym_Pause);
1538
1539 /* 10M and 100M are only supported */
1540 phylink_set(mask, 10baseT_Half);
1541 phylink_set(mask, 10baseT_Full);
1542 phylink_set(mask, 100baseT_Half);
1543 phylink_set(mask, 100baseT_Full);
1544
1545 bitmap_and(supported, supported, mask,
1546 __ETHTOOL_LINK_MODE_MASK_NBITS);
1547 bitmap_and(state->advertising, state->advertising, mask,
1548 __ETHTOOL_LINK_MODE_MASK_NBITS);
1549
1550 return;
1551
1552unsupported:
1553 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1554 dev_err(ds->dev, "Unsupported interface: %s, port: %d\n",
1555 phy_modes(state->interface), port);
1556}
1557
1558static const struct dsa_switch_ops ksz8_switch_ops = {
1559 .get_tag_protocol = ksz8_get_tag_protocol,
1560 .get_phy_flags = ksz8_sw_get_phy_flags,
1561 .setup = ksz8_setup,
1562 .phy_read = ksz_phy_read16,
1563 .phy_write = ksz_phy_write16,
1564 .phylink_validate = ksz8_validate,
1565 .phylink_mac_link_down = ksz_mac_link_down,
1566 .port_enable = ksz_enable_port,
1567 .get_strings = ksz8_get_strings,
1568 .get_ethtool_stats = ksz_get_ethtool_stats,
1569 .get_sset_count = ksz_sset_count,
1570 .port_bridge_join = ksz_port_bridge_join,
1571 .port_bridge_leave = ksz_port_bridge_leave,
1572 .port_stp_state_set = ksz8_port_stp_state_set,
1573 .port_fast_age = ksz_port_fast_age,
1574 .port_vlan_filtering = ksz8_port_vlan_filtering,
1575 .port_vlan_add = ksz8_port_vlan_add,
1576 .port_vlan_del = ksz8_port_vlan_del,
1577 .port_fdb_dump = ksz_port_fdb_dump,
1578 .port_mdb_add = ksz_port_mdb_add,
1579 .port_mdb_del = ksz_port_mdb_del,
1580 .port_mirror_add = ksz8_port_mirror_add,
1581 .port_mirror_del = ksz8_port_mirror_del,
1582};
1583
1584static u32 ksz8_get_port_addr(int port, int offset)
1585{
1586 return PORT_CTRL_ADDR(port, offset);
1587}
1588
1589static int ksz8_switch_detect(struct ksz_device *dev)
1590{
1591 u8 id1, id2;
1592 u16 id16;
1593 int ret;
1594
1595 /* read chip id */
1596 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
1597 if (ret)
1598 return ret;
1599
1600 id1 = id16 >> 8;
1601 id2 = id16 & SW_CHIP_ID_M;
1602
1603 switch (id1) {
1604 case KSZ87_FAMILY_ID:
1605 if ((id2 != CHIP_ID_94 && id2 != CHIP_ID_95))
1606 return -ENODEV;
1607
1608 if (id2 == CHIP_ID_95) {
1609 u8 val;
1610
1611 id2 = 0x95;
1612 ksz_read8(dev, REG_PORT_STATUS_0, &val);
1613 if (val & PORT_FIBER_MODE)
1614 id2 = 0x65;
1615 } else if (id2 == CHIP_ID_94) {
1616 id2 = 0x94;
1617 }
1618 break;
1619 case KSZ88_FAMILY_ID:
1620 if (id2 != CHIP_ID_63)
1621 return -ENODEV;
1622 break;
1623 default:
1624 dev_err(dev->dev, "invalid family id: %d\n", id1);
1625 return -ENODEV;
1626 }
1627 id16 &= ~0xff;
1628 id16 |= id2;
1629 dev->chip_id = id16;
1630
1631 return 0;
1632}
1633
1634struct ksz_chip_data {
1635 u16 chip_id;
1636 const char *dev_name;
1637 int num_vlans;
1638 int num_alus;
1639 int num_statics;
1640 int cpu_ports;
1641 int port_cnt;
1642};
1643
1644static const struct ksz_chip_data ksz8_switch_chips[] = {
1645 {
1646 .chip_id = 0x8795,
1647 .dev_name = "KSZ8795",
1648 .num_vlans = 4096,
1649 .num_alus = 0,
1650 .num_statics = 8,
1651 .cpu_ports = 0x10, /* can be configured as cpu port */
1652 .port_cnt = 5, /* total cpu and user ports */
1653 },
1654 {
1655 /*
1656 * WARNING
1657 * =======
1658 * KSZ8794 is similar to KSZ8795, except the port map
1659 * contains a gap between external and CPU ports, the
1660 * port map is NOT continuous. The per-port register
1661 * map is shifted accordingly too, i.e. registers at
1662 * offset 0x40 are NOT used on KSZ8794 and they ARE
1663 * used on KSZ8795 for external port 3.
1664 * external cpu
1665 * KSZ8794 0,1,2 4
1666 * KSZ8795 0,1,2,3 4
1667 * KSZ8765 0,1,2,3 4
1668 */
1669 .chip_id = 0x8794,
1670 .dev_name = "KSZ8794",
1671 .num_vlans = 4096,
1672 .num_alus = 0,
1673 .num_statics = 8,
1674 .cpu_ports = 0x10, /* can be configured as cpu port */
1675 .port_cnt = 4, /* total cpu and user ports */
1676 },
1677 {
1678 .chip_id = 0x8765,
1679 .dev_name = "KSZ8765",
1680 .num_vlans = 4096,
1681 .num_alus = 0,
1682 .num_statics = 8,
1683 .cpu_ports = 0x10, /* can be configured as cpu port */
1684 .port_cnt = 5, /* total cpu and user ports */
1685 },
1686 {
1687 .chip_id = 0x8830,
1688 .dev_name = "KSZ8863/KSZ8873",
1689 .num_vlans = 16,
1690 .num_alus = 0,
1691 .num_statics = 8,
1692 .cpu_ports = 0x4, /* can be configured as cpu port */
1693 .port_cnt = 3,
1694 },
1695};
1696
1697static int ksz8_switch_init(struct ksz_device *dev)
1698{
1699 struct ksz8 *ksz8 = dev->priv;
1700 int i;
1701
1702 dev->ds->ops = &ksz8_switch_ops;
1703
1704 for (i = 0; i < ARRAY_SIZE(ksz8_switch_chips); i++) {
1705 const struct ksz_chip_data *chip = &ksz8_switch_chips[i];
1706
1707 if (dev->chip_id == chip->chip_id) {
1708 dev->name = chip->dev_name;
1709 dev->num_vlans = chip->num_vlans;
1710 dev->num_alus = chip->num_alus;
1711 dev->num_statics = chip->num_statics;
1712 dev->port_cnt = fls(chip->cpu_ports);
1713 dev->cpu_port = fls(chip->cpu_ports) - 1;
1714 dev->phy_port_cnt = dev->port_cnt - 1;
1715 dev->cpu_ports = chip->cpu_ports;
1716 dev->host_mask = chip->cpu_ports;
1717 dev->port_mask = (BIT(dev->phy_port_cnt) - 1) |
1718 chip->cpu_ports;
1719 break;
1720 }
1721 }
1722
1723 /* no switch found */
1724 if (!dev->cpu_ports)
1725 return -ENODEV;
1726
1727 if (ksz_is_ksz88x3(dev)) {
1728 ksz8->regs = ksz8863_regs;
1729 ksz8->masks = ksz8863_masks;
1730 ksz8->shifts = ksz8863_shifts;
1731 dev->mib_cnt = ARRAY_SIZE(ksz88xx_mib_names);
1732 dev->mib_names = ksz88xx_mib_names;
1733 } else {
1734 ksz8->regs = ksz8795_regs;
1735 ksz8->masks = ksz8795_masks;
1736 ksz8->shifts = ksz8795_shifts;
1737 dev->mib_cnt = ARRAY_SIZE(ksz87xx_mib_names);
1738 dev->mib_names = ksz87xx_mib_names;
1739 }
1740
1741 dev->reg_mib_cnt = MIB_COUNTER_NUM;
1742
1743 dev->ports = devm_kzalloc(dev->dev,
1744 dev->port_cnt * sizeof(struct ksz_port),
1745 GFP_KERNEL);
1746 if (!dev->ports)
1747 return -ENOMEM;
1748 for (i = 0; i < dev->port_cnt; i++) {
1749 mutex_init(&dev->ports[i].mib.cnt_mutex);
1750 dev->ports[i].mib.counters =
1751 devm_kzalloc(dev->dev,
1752 sizeof(u64) *
1753 (dev->mib_cnt + 1),
1754 GFP_KERNEL);
1755 if (!dev->ports[i].mib.counters)
1756 return -ENOMEM;
1757 }
1758
1759 /* set the real number of ports */
1760 dev->ds->num_ports = dev->port_cnt;
1761
1762 /* We rely on software untagging on the CPU port, so that we
1763 * can support both tagged and untagged VLANs
1764 */
1765 dev->ds->untag_bridge_pvid = true;
1766
1767 /* VLAN filtering is partly controlled by the global VLAN
1768 * Enable flag
1769 */
1770 dev->ds->vlan_filtering_is_global = true;
1771
1772 return 0;
1773}
1774
1775static void ksz8_switch_exit(struct ksz_device *dev)
1776{
1777 ksz8_reset_switch(dev);
1778}
1779
1780static const struct ksz_dev_ops ksz8_dev_ops = {
1781 .get_port_addr = ksz8_get_port_addr,
1782 .cfg_port_member = ksz8_cfg_port_member,
1783 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
1784 .port_setup = ksz8_port_setup,
1785 .r_phy = ksz8_r_phy,
1786 .w_phy = ksz8_w_phy,
1787 .r_dyn_mac_table = ksz8_r_dyn_mac_table,
1788 .r_sta_mac_table = ksz8_r_sta_mac_table,
1789 .w_sta_mac_table = ksz8_w_sta_mac_table,
1790 .r_mib_cnt = ksz8_r_mib_cnt,
1791 .r_mib_pkt = ksz8_r_mib_pkt,
1792 .freeze_mib = ksz8_freeze_mib,
1793 .port_init_cnt = ksz8_port_init_cnt,
1794 .shutdown = ksz8_reset_switch,
1795 .detect = ksz8_switch_detect,
1796 .init = ksz8_switch_init,
1797 .exit = ksz8_switch_exit,
1798};
1799
1800int ksz8_switch_register(struct ksz_device *dev)
1801{
1802 return ksz_switch_register(dev, &ksz8_dev_ops);
1803}
1804EXPORT_SYMBOL(ksz8_switch_register);
1805
1806MODULE_AUTHOR("Tristram Ha <Tristram.Ha@microchip.com>");
1807MODULE_DESCRIPTION("Microchip KSZ8795 Series Switch DSA Driver");
1808MODULE_LICENSE("GPL");