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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Applied Micro X-Gene SoC DMA engine Driver
4 *
5 * Copyright (c) 2015, Applied Micro Circuits Corporation
6 * Authors: Rameshwar Prasad Sahu <rsahu@apm.com>
7 * Loc Ho <lho@apm.com>
8 *
9 * NOTE: PM support is currently not available.
10 */
11
12#include <linux/acpi.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h>
17#include <linux/dmapool.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/mod_devicetable.h>
22#include <linux/module.h>
23#include <linux/platform_device.h>
24
25#include "dmaengine.h"
26
27/* X-Gene DMA ring csr registers and bit definations */
28#define XGENE_DMA_RING_CONFIG 0x04
29#define XGENE_DMA_RING_ENABLE BIT(31)
30#define XGENE_DMA_RING_ID 0x08
31#define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
32#define XGENE_DMA_RING_ID_BUF 0x0C
33#define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
34#define XGENE_DMA_RING_THRESLD0_SET1 0x30
35#define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64
36#define XGENE_DMA_RING_THRESLD1_SET1 0x34
37#define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8
38#define XGENE_DMA_RING_HYSTERESIS 0x68
39#define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF
40#define XGENE_DMA_RING_STATE 0x6C
41#define XGENE_DMA_RING_STATE_WR_BASE 0x70
42#define XGENE_DMA_RING_NE_INT_MODE 0x017C
43#define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \
44 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
45#define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \
46 ((m) &= (~BIT(31 - (v))))
47#define XGENE_DMA_RING_CLKEN 0xC208
48#define XGENE_DMA_RING_SRST 0xC200
49#define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070
50#define XGENE_DMA_RING_BLK_MEM_RDY 0xD074
51#define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF
52#define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num))
53#define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v))
54#define XGENE_DMA_RING_CMD_OFFSET 0x2C
55#define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6)
56#define XGENE_DMA_RING_COHERENT_SET(m) \
57 (((u32 *)(m))[2] |= BIT(4))
58#define XGENE_DMA_RING_ADDRL_SET(m, v) \
59 (((u32 *)(m))[2] |= (((v) >> 8) << 5))
60#define XGENE_DMA_RING_ADDRH_SET(m, v) \
61 (((u32 *)(m))[3] |= ((v) >> 35))
62#define XGENE_DMA_RING_ACCEPTLERR_SET(m) \
63 (((u32 *)(m))[3] |= BIT(19))
64#define XGENE_DMA_RING_SIZE_SET(m, v) \
65 (((u32 *)(m))[3] |= ((v) << 23))
66#define XGENE_DMA_RING_RECOMBBUF_SET(m) \
67 (((u32 *)(m))[3] |= BIT(27))
68#define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \
69 (((u32 *)(m))[3] |= (0x7 << 28))
70#define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \
71 (((u32 *)(m))[4] |= 0x3)
72#define XGENE_DMA_RING_SELTHRSH_SET(m) \
73 (((u32 *)(m))[4] |= BIT(3))
74#define XGENE_DMA_RING_TYPE_SET(m, v) \
75 (((u32 *)(m))[4] |= ((v) << 19))
76
77/* X-Gene DMA device csr registers and bit definitions */
78#define XGENE_DMA_IPBRR 0x0
79#define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF)
80#define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3)
81#define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3)
82#define XGENE_DMA_GCR 0x10
83#define XGENE_DMA_CH_SETUP(v) \
84 ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
85#define XGENE_DMA_ENABLE(v) ((v) |= BIT(31))
86#define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31))
87#define XGENE_DMA_RAID6_CONT 0x14
88#define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24)
89#define XGENE_DMA_INT 0x70
90#define XGENE_DMA_INT_MASK 0x74
91#define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF
92#define XGENE_DMA_INT_ALL_UNMASK 0x0
93#define XGENE_DMA_INT_MASK_SHIFT 0x14
94#define XGENE_DMA_RING_INT0_MASK 0x90A0
95#define XGENE_DMA_RING_INT1_MASK 0x90A8
96#define XGENE_DMA_RING_INT2_MASK 0x90B0
97#define XGENE_DMA_RING_INT3_MASK 0x90B8
98#define XGENE_DMA_RING_INT4_MASK 0x90C0
99#define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0
100#define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF
101#define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
102#define XGENE_DMA_BLK_MEM_RDY 0xD074
103#define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF
104#define XGENE_DMA_RING_CMD_SM_OFFSET 0x8000
105
106/* X-Gene SoC EFUSE csr register and bit defination */
107#define XGENE_SOC_JTAG1_SHADOW 0x18
108#define XGENE_DMA_PQ_DISABLE_MASK BIT(13)
109
110/* X-Gene DMA Descriptor format */
111#define XGENE_DMA_DESC_NV_BIT BIT_ULL(50)
112#define XGENE_DMA_DESC_IN_BIT BIT_ULL(55)
113#define XGENE_DMA_DESC_C_BIT BIT_ULL(63)
114#define XGENE_DMA_DESC_DR_BIT BIT_ULL(61)
115#define XGENE_DMA_DESC_ELERR_POS 46
116#define XGENE_DMA_DESC_RTYPE_POS 56
117#define XGENE_DMA_DESC_LERR_POS 60
118#define XGENE_DMA_DESC_BUFLEN_POS 48
119#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
120#define XGENE_DMA_DESC_ELERR_RD(m) \
121 (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
122#define XGENE_DMA_DESC_LERR_RD(m) \
123 (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7)
124#define XGENE_DMA_DESC_STATUS(elerr, lerr) \
125 (((elerr) << 4) | (lerr))
126
127/* X-Gene DMA descriptor empty s/w signature */
128#define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
129
130/* X-Gene DMA configurable parameters defines */
131#define XGENE_DMA_RING_NUM 512
132#define XGENE_DMA_BUFNUM 0x0
133#define XGENE_DMA_CPU_BUFNUM 0x18
134#define XGENE_DMA_RING_OWNER_DMA 0x03
135#define XGENE_DMA_RING_OWNER_CPU 0x0F
136#define XGENE_DMA_RING_TYPE_REGULAR 0x01
137#define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */
138#define XGENE_DMA_RING_NUM_CONFIG 5
139#define XGENE_DMA_MAX_CHANNEL 4
140#define XGENE_DMA_XOR_CHANNEL 0
141#define XGENE_DMA_PQ_CHANNEL 1
142#define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */
143#define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */
144#define XGENE_DMA_MAX_XOR_SRC 5
145#define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
146#define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL
147
148/* X-Gene DMA descriptor error codes */
149#define ERR_DESC_AXI 0x01
150#define ERR_BAD_DESC 0x02
151#define ERR_READ_DATA_AXI 0x03
152#define ERR_WRITE_DATA_AXI 0x04
153#define ERR_FBP_TIMEOUT 0x05
154#define ERR_ECC 0x06
155#define ERR_DIFF_SIZE 0x08
156#define ERR_SCT_GAT_LEN 0x09
157#define ERR_CRC_ERR 0x11
158#define ERR_CHKSUM 0x12
159#define ERR_DIF 0x13
160
161/* X-Gene DMA error interrupt codes */
162#define ERR_DIF_SIZE_INT 0x0
163#define ERR_GS_ERR_INT 0x1
164#define ERR_FPB_TIMEO_INT 0x2
165#define ERR_WFIFO_OVF_INT 0x3
166#define ERR_RFIFO_OVF_INT 0x4
167#define ERR_WR_TIMEO_INT 0x5
168#define ERR_RD_TIMEO_INT 0x6
169#define ERR_WR_ERR_INT 0x7
170#define ERR_RD_ERR_INT 0x8
171#define ERR_BAD_DESC_INT 0x9
172#define ERR_DESC_DST_INT 0xA
173#define ERR_DESC_SRC_INT 0xB
174
175/* X-Gene DMA flyby operation code */
176#define FLYBY_2SRC_XOR 0x80
177#define FLYBY_3SRC_XOR 0x90
178#define FLYBY_4SRC_XOR 0xA0
179#define FLYBY_5SRC_XOR 0xB0
180
181/* X-Gene DMA SW descriptor flags */
182#define XGENE_DMA_FLAG_64B_DESC BIT(0)
183
184/* Define to dump X-Gene DMA descriptor */
185#define XGENE_DMA_DESC_DUMP(desc, m) \
186 print_hex_dump(KERN_ERR, (m), \
187 DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0)
188
189#define to_dma_desc_sw(tx) \
190 container_of(tx, struct xgene_dma_desc_sw, tx)
191#define to_dma_chan(dchan) \
192 container_of(dchan, struct xgene_dma_chan, dma_chan)
193
194#define chan_dbg(chan, fmt, arg...) \
195 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
196#define chan_err(chan, fmt, arg...) \
197 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
198
199struct xgene_dma_desc_hw {
200 __le64 m0;
201 __le64 m1;
202 __le64 m2;
203 __le64 m3;
204};
205
206enum xgene_dma_ring_cfgsize {
207 XGENE_DMA_RING_CFG_SIZE_512B,
208 XGENE_DMA_RING_CFG_SIZE_2KB,
209 XGENE_DMA_RING_CFG_SIZE_16KB,
210 XGENE_DMA_RING_CFG_SIZE_64KB,
211 XGENE_DMA_RING_CFG_SIZE_512KB,
212 XGENE_DMA_RING_CFG_SIZE_INVALID
213};
214
215struct xgene_dma_ring {
216 struct xgene_dma *pdma;
217 u8 buf_num;
218 u16 id;
219 u16 num;
220 u16 head;
221 u16 owner;
222 u16 slots;
223 u16 dst_ring_num;
224 u32 size;
225 void __iomem *cmd;
226 void __iomem *cmd_base;
227 dma_addr_t desc_paddr;
228 u32 state[XGENE_DMA_RING_NUM_CONFIG];
229 enum xgene_dma_ring_cfgsize cfgsize;
230 union {
231 void *desc_vaddr;
232 struct xgene_dma_desc_hw *desc_hw;
233 };
234};
235
236struct xgene_dma_desc_sw {
237 struct xgene_dma_desc_hw desc1;
238 struct xgene_dma_desc_hw desc2;
239 u32 flags;
240 struct list_head node;
241 struct list_head tx_list;
242 struct dma_async_tx_descriptor tx;
243};
244
245/**
246 * struct xgene_dma_chan - internal representation of an X-Gene DMA channel
247 * @dma_chan: dmaengine channel object member
248 * @pdma: X-Gene DMA device structure reference
249 * @dev: struct device reference for dma mapping api
250 * @id: raw id of this channel
251 * @rx_irq: channel IRQ
252 * @name: name of X-Gene DMA channel
253 * @lock: serializes enqueue/dequeue operations to the descriptor pool
254 * @pending: number of transaction request pushed to DMA controller for
255 * execution, but still waiting for completion,
256 * @max_outstanding: max number of outstanding request we can push to channel
257 * @ld_pending: descriptors which are queued to run, but have not yet been
258 * submitted to the hardware for execution
259 * @ld_running: descriptors which are currently being executing by the hardware
260 * @ld_completed: descriptors which have finished execution by the hardware.
261 * These descriptors have already had their cleanup actions run. They
262 * are waiting for the ACK bit to be set by the async tx API.
263 * @desc_pool: descriptor pool for DMA operations
264 * @tasklet: bottom half where all completed descriptors cleans
265 * @tx_ring: transmit ring descriptor that we use to prepare actual
266 * descriptors for further executions
267 * @rx_ring: receive ring descriptor that we use to get completed DMA
268 * descriptors during cleanup time
269 */
270struct xgene_dma_chan {
271 struct dma_chan dma_chan;
272 struct xgene_dma *pdma;
273 struct device *dev;
274 int id;
275 int rx_irq;
276 char name[10];
277 spinlock_t lock;
278 int pending;
279 int max_outstanding;
280 struct list_head ld_pending;
281 struct list_head ld_running;
282 struct list_head ld_completed;
283 struct dma_pool *desc_pool;
284 struct tasklet_struct tasklet;
285 struct xgene_dma_ring tx_ring;
286 struct xgene_dma_ring rx_ring;
287};
288
289/**
290 * struct xgene_dma - internal representation of an X-Gene DMA device
291 * @dev: reference to this device's struct device
292 * @clk: reference to this device's clock
293 * @err_irq: DMA error irq number
294 * @ring_num: start id number for DMA ring
295 * @csr_dma: base for DMA register access
296 * @csr_ring: base for DMA ring register access
297 * @csr_ring_cmd: base for DMA ring command register access
298 * @csr_efuse: base for efuse register access
299 * @dma_dev: embedded struct dma_device
300 * @chan: reference to X-Gene DMA channels
301 */
302struct xgene_dma {
303 struct device *dev;
304 struct clk *clk;
305 int err_irq;
306 int ring_num;
307 void __iomem *csr_dma;
308 void __iomem *csr_ring;
309 void __iomem *csr_ring_cmd;
310 void __iomem *csr_efuse;
311 struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL];
312 struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL];
313};
314
315static const char * const xgene_dma_desc_err[] = {
316 [ERR_DESC_AXI] = "AXI error when reading src/dst link list",
317 [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc",
318 [ERR_READ_DATA_AXI] = "AXI error when reading data",
319 [ERR_WRITE_DATA_AXI] = "AXI error when writing data",
320 [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch",
321 [ERR_ECC] = "ECC double bit error",
322 [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result",
323 [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same",
324 [ERR_CRC_ERR] = "CRC error",
325 [ERR_CHKSUM] = "Checksum error",
326 [ERR_DIF] = "DIF error",
327};
328
329static const char * const xgene_dma_err[] = {
330 [ERR_DIF_SIZE_INT] = "DIF size error",
331 [ERR_GS_ERR_INT] = "Gather scatter not same size error",
332 [ERR_FPB_TIMEO_INT] = "Free pool time out error",
333 [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error",
334 [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error",
335 [ERR_WR_TIMEO_INT] = "Write time out error",
336 [ERR_RD_TIMEO_INT] = "Read time out error",
337 [ERR_WR_ERR_INT] = "HBF bus write error",
338 [ERR_RD_ERR_INT] = "HBF bus read error",
339 [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error",
340 [ERR_DESC_DST_INT] = "HFB reading dst link address error",
341 [ERR_DESC_SRC_INT] = "HFB reading src link address error",
342};
343
344static bool is_pq_enabled(struct xgene_dma *pdma)
345{
346 u32 val;
347
348 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
349 return !(val & XGENE_DMA_PQ_DISABLE_MASK);
350}
351
352static u64 xgene_dma_encode_len(size_t len)
353{
354 return (len < XGENE_DMA_MAX_BYTE_CNT) ?
355 ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) :
356 XGENE_DMA_16K_BUFFER_LEN_CODE;
357}
358
359static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
360{
361 static u8 flyby_type[] = {
362 FLYBY_2SRC_XOR, /* Dummy */
363 FLYBY_2SRC_XOR, /* Dummy */
364 FLYBY_2SRC_XOR,
365 FLYBY_3SRC_XOR,
366 FLYBY_4SRC_XOR,
367 FLYBY_5SRC_XOR
368 };
369
370 return flyby_type[src_cnt];
371}
372
373static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
374 dma_addr_t *paddr)
375{
376 size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
377 *len : XGENE_DMA_MAX_BYTE_CNT;
378
379 *ext8 |= cpu_to_le64(*paddr);
380 *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes));
381 *len -= nbytes;
382 *paddr += nbytes;
383}
384
385static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx)
386{
387 switch (idx) {
388 case 0:
389 return &desc->m1;
390 case 1:
391 return &desc->m0;
392 case 2:
393 return &desc->m3;
394 case 3:
395 return &desc->m2;
396 default:
397 pr_err("Invalid dma descriptor index\n");
398 }
399
400 return NULL;
401}
402
403static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc,
404 u16 dst_ring_num)
405{
406 desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT);
407 desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA <<
408 XGENE_DMA_DESC_RTYPE_POS);
409 desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT);
410 desc->m3 |= cpu_to_le64((u64)dst_ring_num <<
411 XGENE_DMA_DESC_HOENQ_NUM_POS);
412}
413
414static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
415 struct xgene_dma_desc_sw *desc_sw,
416 dma_addr_t *dst, dma_addr_t *src,
417 u32 src_cnt, size_t *nbytes,
418 const u8 *scf)
419{
420 struct xgene_dma_desc_hw *desc1, *desc2;
421 size_t len = *nbytes;
422 int i;
423
424 desc1 = &desc_sw->desc1;
425 desc2 = &desc_sw->desc2;
426
427 /* Initialize DMA descriptor */
428 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
429
430 /* Set destination address */
431 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
432 desc1->m3 |= cpu_to_le64(*dst);
433
434 /* We have multiple source addresses, so need to set NV bit*/
435 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
436
437 /* Set flyby opcode */
438 desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt));
439
440 /* Set 1st to 5th source addresses */
441 for (i = 0; i < src_cnt; i++) {
442 len = *nbytes;
443 xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 :
444 xgene_dma_lookup_ext8(desc2, i - 1),
445 &len, &src[i]);
446 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8)));
447 }
448
449 /* Update meta data */
450 *nbytes = len;
451 *dst += XGENE_DMA_MAX_BYTE_CNT;
452
453 /* We need always 64B descriptor to perform xor or pq operations */
454 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
455}
456
457static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx)
458{
459 struct xgene_dma_desc_sw *desc;
460 struct xgene_dma_chan *chan;
461 dma_cookie_t cookie;
462
463 if (unlikely(!tx))
464 return -EINVAL;
465
466 chan = to_dma_chan(tx->chan);
467 desc = to_dma_desc_sw(tx);
468
469 spin_lock_bh(&chan->lock);
470
471 cookie = dma_cookie_assign(tx);
472
473 /* Add this transaction list onto the tail of the pending queue */
474 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
475
476 spin_unlock_bh(&chan->lock);
477
478 return cookie;
479}
480
481static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan,
482 struct xgene_dma_desc_sw *desc)
483{
484 list_del(&desc->node);
485 chan_dbg(chan, "LD %p free\n", desc);
486 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
487}
488
489static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
490 struct xgene_dma_chan *chan)
491{
492 struct xgene_dma_desc_sw *desc;
493 dma_addr_t phys;
494
495 desc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
496 if (!desc) {
497 chan_err(chan, "Failed to allocate LDs\n");
498 return NULL;
499 }
500
501 INIT_LIST_HEAD(&desc->tx_list);
502 desc->tx.phys = phys;
503 desc->tx.tx_submit = xgene_dma_tx_submit;
504 dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan);
505
506 chan_dbg(chan, "LD %p allocated\n", desc);
507
508 return desc;
509}
510
511/**
512 * xgene_dma_clean_completed_descriptor - free all descriptors which
513 * has been completed and acked
514 * @chan: X-Gene DMA channel
515 *
516 * This function is used on all completed and acked descriptors.
517 */
518static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan)
519{
520 struct xgene_dma_desc_sw *desc, *_desc;
521
522 /* Run the callback for each descriptor, in order */
523 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) {
524 if (async_tx_test_ack(&desc->tx))
525 xgene_dma_clean_descriptor(chan, desc);
526 }
527}
528
529/**
530 * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor
531 * @chan: X-Gene DMA channel
532 * @desc: descriptor to cleanup and free
533 *
534 * This function is used on a descriptor which has been executed by the DMA
535 * controller. It will run any callbacks, submit any dependencies.
536 */
537static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan,
538 struct xgene_dma_desc_sw *desc)
539{
540 struct dma_async_tx_descriptor *tx = &desc->tx;
541
542 /*
543 * If this is not the last transaction in the group,
544 * then no need to complete cookie and run any callback as
545 * this is not the tx_descriptor which had been sent to caller
546 * of this DMA request
547 */
548
549 if (tx->cookie == 0)
550 return;
551
552 dma_cookie_complete(tx);
553 dma_descriptor_unmap(tx);
554
555 /* Run the link descriptor callback function */
556 dmaengine_desc_get_callback_invoke(tx, NULL);
557
558 /* Run any dependencies */
559 dma_run_dependencies(tx);
560}
561
562/**
563 * xgene_dma_clean_running_descriptor - move the completed descriptor from
564 * ld_running to ld_completed
565 * @chan: X-Gene DMA channel
566 * @desc: the descriptor which is completed
567 *
568 * Free the descriptor directly if acked by async_tx api,
569 * else move it to queue ld_completed.
570 */
571static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan,
572 struct xgene_dma_desc_sw *desc)
573{
574 /* Remove from the list of running transactions */
575 list_del(&desc->node);
576
577 /*
578 * the client is allowed to attach dependent operations
579 * until 'ack' is set
580 */
581 if (!async_tx_test_ack(&desc->tx)) {
582 /*
583 * Move this descriptor to the list of descriptors which is
584 * completed, but still awaiting the 'ack' bit to be set.
585 */
586 list_add_tail(&desc->node, &chan->ld_completed);
587 return;
588 }
589
590 chan_dbg(chan, "LD %p free\n", desc);
591 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
592}
593
594static void xgene_chan_xfer_request(struct xgene_dma_chan *chan,
595 struct xgene_dma_desc_sw *desc_sw)
596{
597 struct xgene_dma_ring *ring = &chan->tx_ring;
598 struct xgene_dma_desc_hw *desc_hw;
599
600 /* Get hw descriptor from DMA tx ring */
601 desc_hw = &ring->desc_hw[ring->head];
602
603 /*
604 * Increment the head count to point next
605 * descriptor for next time
606 */
607 if (++ring->head == ring->slots)
608 ring->head = 0;
609
610 /* Copy prepared sw descriptor data to hw descriptor */
611 memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw));
612
613 /*
614 * Check if we have prepared 64B descriptor,
615 * in this case we need one more hw descriptor
616 */
617 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) {
618 desc_hw = &ring->desc_hw[ring->head];
619
620 if (++ring->head == ring->slots)
621 ring->head = 0;
622
623 memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw));
624 }
625
626 /* Increment the pending transaction count */
627 chan->pending += ((desc_sw->flags &
628 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
629
630 /* Notify the hw that we have descriptor ready for execution */
631 iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ?
632 2 : 1, ring->cmd);
633}
634
635/**
636 * xgene_chan_xfer_ld_pending - push any pending transactions to hw
637 * @chan : X-Gene DMA channel
638 *
639 * LOCKING: must hold chan->lock
640 */
641static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan)
642{
643 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
644
645 /*
646 * If the list of pending descriptors is empty, then we
647 * don't need to do any work at all
648 */
649 if (list_empty(&chan->ld_pending)) {
650 chan_dbg(chan, "No pending LDs\n");
651 return;
652 }
653
654 /*
655 * Move elements from the queue of pending transactions onto the list
656 * of running transactions and push it to hw for further executions
657 */
658 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) {
659 /*
660 * Check if have pushed max number of transactions to hw
661 * as capable, so let's stop here and will push remaining
662 * elements from pening ld queue after completing some
663 * descriptors that we have already pushed
664 */
665 if (chan->pending >= chan->max_outstanding)
666 return;
667
668 xgene_chan_xfer_request(chan, desc_sw);
669
670 /*
671 * Delete this element from ld pending queue and append it to
672 * ld running queue
673 */
674 list_move_tail(&desc_sw->node, &chan->ld_running);
675 }
676}
677
678/**
679 * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed
680 * and move them to ld_completed to free until flag 'ack' is set
681 * @chan: X-Gene DMA channel
682 *
683 * This function is used on descriptors which have been executed by the DMA
684 * controller. It will run any callbacks, submit any dependencies, then
685 * free these descriptors if flag 'ack' is set.
686 */
687static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan)
688{
689 struct xgene_dma_ring *ring = &chan->rx_ring;
690 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
691 struct xgene_dma_desc_hw *desc_hw;
692 struct list_head ld_completed;
693 u8 status;
694
695 INIT_LIST_HEAD(&ld_completed);
696
697 spin_lock(&chan->lock);
698
699 /* Clean already completed and acked descriptors */
700 xgene_dma_clean_completed_descriptor(chan);
701
702 /* Move all completed descriptors to ld completed queue, in order */
703 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
704 /* Get subsequent hw descriptor from DMA rx ring */
705 desc_hw = &ring->desc_hw[ring->head];
706
707 /* Check if this descriptor has been completed */
708 if (unlikely(le64_to_cpu(desc_hw->m0) ==
709 XGENE_DMA_DESC_EMPTY_SIGNATURE))
710 break;
711
712 if (++ring->head == ring->slots)
713 ring->head = 0;
714
715 /* Check if we have any error with DMA transactions */
716 status = XGENE_DMA_DESC_STATUS(
717 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu(
718 desc_hw->m0)),
719 XGENE_DMA_DESC_LERR_RD(le64_to_cpu(
720 desc_hw->m0)));
721 if (status) {
722 /* Print the DMA error type */
723 chan_err(chan, "%s\n", xgene_dma_desc_err[status]);
724
725 /*
726 * We have DMA transactions error here. Dump DMA Tx
727 * and Rx descriptors for this request */
728 XGENE_DMA_DESC_DUMP(&desc_sw->desc1,
729 "X-Gene DMA TX DESC1: ");
730
731 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC)
732 XGENE_DMA_DESC_DUMP(&desc_sw->desc2,
733 "X-Gene DMA TX DESC2: ");
734
735 XGENE_DMA_DESC_DUMP(desc_hw,
736 "X-Gene DMA RX ERR DESC: ");
737 }
738
739 /* Notify the hw about this completed descriptor */
740 iowrite32(-1, ring->cmd);
741
742 /* Mark this hw descriptor as processed */
743 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
744
745 /*
746 * Decrement the pending transaction count
747 * as we have processed one
748 */
749 chan->pending -= ((desc_sw->flags &
750 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
751
752 /*
753 * Delete this node from ld running queue and append it to
754 * ld completed queue for further processing
755 */
756 list_move_tail(&desc_sw->node, &ld_completed);
757 }
758
759 /*
760 * Start any pending transactions automatically
761 * In the ideal case, we keep the DMA controller busy while we go
762 * ahead and free the descriptors below.
763 */
764 xgene_chan_xfer_ld_pending(chan);
765
766 spin_unlock(&chan->lock);
767
768 /* Run the callback for each descriptor, in order */
769 list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) {
770 xgene_dma_run_tx_complete_actions(chan, desc_sw);
771 xgene_dma_clean_running_descriptor(chan, desc_sw);
772 }
773}
774
775static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
776{
777 struct xgene_dma_chan *chan = to_dma_chan(dchan);
778
779 /* Has this channel already been allocated? */
780 if (chan->desc_pool)
781 return 1;
782
783 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
784 sizeof(struct xgene_dma_desc_sw),
785 0, 0);
786 if (!chan->desc_pool) {
787 chan_err(chan, "Failed to allocate descriptor pool\n");
788 return -ENOMEM;
789 }
790
791 chan_dbg(chan, "Allocate descriptor pool\n");
792
793 return 1;
794}
795
796/**
797 * xgene_dma_free_desc_list - Free all descriptors in a queue
798 * @chan: X-Gene DMA channel
799 * @list: the list to free
800 *
801 * LOCKING: must hold chan->lock
802 */
803static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan,
804 struct list_head *list)
805{
806 struct xgene_dma_desc_sw *desc, *_desc;
807
808 list_for_each_entry_safe(desc, _desc, list, node)
809 xgene_dma_clean_descriptor(chan, desc);
810}
811
812static void xgene_dma_free_chan_resources(struct dma_chan *dchan)
813{
814 struct xgene_dma_chan *chan = to_dma_chan(dchan);
815
816 chan_dbg(chan, "Free all resources\n");
817
818 if (!chan->desc_pool)
819 return;
820
821 /* Process all running descriptor */
822 xgene_dma_cleanup_descriptors(chan);
823
824 spin_lock_bh(&chan->lock);
825
826 /* Clean all link descriptor queues */
827 xgene_dma_free_desc_list(chan, &chan->ld_pending);
828 xgene_dma_free_desc_list(chan, &chan->ld_running);
829 xgene_dma_free_desc_list(chan, &chan->ld_completed);
830
831 spin_unlock_bh(&chan->lock);
832
833 /* Delete this channel DMA pool */
834 dma_pool_destroy(chan->desc_pool);
835 chan->desc_pool = NULL;
836}
837
838static struct dma_async_tx_descriptor *xgene_dma_prep_xor(
839 struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
840 u32 src_cnt, size_t len, unsigned long flags)
841{
842 struct xgene_dma_desc_sw *first = NULL, *new;
843 struct xgene_dma_chan *chan;
844 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {
845 0x01, 0x01, 0x01, 0x01, 0x01};
846
847 if (unlikely(!dchan || !len))
848 return NULL;
849
850 chan = to_dma_chan(dchan);
851
852 do {
853 /* Allocate the link descriptor from DMA pool */
854 new = xgene_dma_alloc_descriptor(chan);
855 if (!new)
856 goto fail;
857
858 /* Prepare xor DMA descriptor */
859 xgene_dma_prep_xor_desc(chan, new, &dst, src,
860 src_cnt, &len, multi);
861
862 if (!first)
863 first = new;
864
865 new->tx.cookie = 0;
866 async_tx_ack(&new->tx);
867
868 /* Insert the link descriptor to the LD ring */
869 list_add_tail(&new->node, &first->tx_list);
870 } while (len);
871
872 new->tx.flags = flags; /* client is in control of this ack */
873 new->tx.cookie = -EBUSY;
874 list_splice(&first->tx_list, &new->tx_list);
875
876 return &new->tx;
877
878fail:
879 if (!first)
880 return NULL;
881
882 xgene_dma_free_desc_list(chan, &first->tx_list);
883 return NULL;
884}
885
886static struct dma_async_tx_descriptor *xgene_dma_prep_pq(
887 struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
888 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
889{
890 struct xgene_dma_desc_sw *first = NULL, *new;
891 struct xgene_dma_chan *chan;
892 size_t _len = len;
893 dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC];
894 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01};
895
896 if (unlikely(!dchan || !len))
897 return NULL;
898
899 chan = to_dma_chan(dchan);
900
901 /*
902 * Save source addresses on local variable, may be we have to
903 * prepare two descriptor to generate P and Q if both enabled
904 * in the flags by client
905 */
906 memcpy(_src, src, sizeof(*src) * src_cnt);
907
908 if (flags & DMA_PREP_PQ_DISABLE_P)
909 len = 0;
910
911 if (flags & DMA_PREP_PQ_DISABLE_Q)
912 _len = 0;
913
914 do {
915 /* Allocate the link descriptor from DMA pool */
916 new = xgene_dma_alloc_descriptor(chan);
917 if (!new)
918 goto fail;
919
920 if (!first)
921 first = new;
922
923 new->tx.cookie = 0;
924 async_tx_ack(&new->tx);
925
926 /* Insert the link descriptor to the LD ring */
927 list_add_tail(&new->node, &first->tx_list);
928
929 /*
930 * Prepare DMA descriptor to generate P,
931 * if DMA_PREP_PQ_DISABLE_P flag is not set
932 */
933 if (len) {
934 xgene_dma_prep_xor_desc(chan, new, &dst[0], src,
935 src_cnt, &len, multi);
936 continue;
937 }
938
939 /*
940 * Prepare DMA descriptor to generate Q,
941 * if DMA_PREP_PQ_DISABLE_Q flag is not set
942 */
943 if (_len) {
944 xgene_dma_prep_xor_desc(chan, new, &dst[1], _src,
945 src_cnt, &_len, scf);
946 }
947 } while (len || _len);
948
949 new->tx.flags = flags; /* client is in control of this ack */
950 new->tx.cookie = -EBUSY;
951 list_splice(&first->tx_list, &new->tx_list);
952
953 return &new->tx;
954
955fail:
956 if (!first)
957 return NULL;
958
959 xgene_dma_free_desc_list(chan, &first->tx_list);
960 return NULL;
961}
962
963static void xgene_dma_issue_pending(struct dma_chan *dchan)
964{
965 struct xgene_dma_chan *chan = to_dma_chan(dchan);
966
967 spin_lock_bh(&chan->lock);
968 xgene_chan_xfer_ld_pending(chan);
969 spin_unlock_bh(&chan->lock);
970}
971
972static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan,
973 dma_cookie_t cookie,
974 struct dma_tx_state *txstate)
975{
976 return dma_cookie_status(dchan, cookie, txstate);
977}
978
979static void xgene_dma_tasklet_cb(struct tasklet_struct *t)
980{
981 struct xgene_dma_chan *chan = from_tasklet(chan, t, tasklet);
982
983 /* Run all cleanup for descriptors which have been completed */
984 xgene_dma_cleanup_descriptors(chan);
985
986 /* Re-enable DMA channel IRQ */
987 enable_irq(chan->rx_irq);
988}
989
990static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
991{
992 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id;
993
994 BUG_ON(!chan);
995
996 /*
997 * Disable DMA channel IRQ until we process completed
998 * descriptors
999 */
1000 disable_irq_nosync(chan->rx_irq);
1001
1002 /*
1003 * Schedule the tasklet to handle all cleanup of the current
1004 * transaction. It will start a new transaction if there is
1005 * one pending.
1006 */
1007 tasklet_schedule(&chan->tasklet);
1008
1009 return IRQ_HANDLED;
1010}
1011
1012static irqreturn_t xgene_dma_err_isr(int irq, void *id)
1013{
1014 struct xgene_dma *pdma = (struct xgene_dma *)id;
1015 unsigned long int_mask;
1016 u32 val, i;
1017
1018 val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1019
1020 /* Clear DMA interrupts */
1021 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1022
1023 /* Print DMA error info */
1024 int_mask = val >> XGENE_DMA_INT_MASK_SHIFT;
1025 for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err))
1026 dev_err(pdma->dev,
1027 "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]);
1028
1029 return IRQ_HANDLED;
1030}
1031
1032static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring)
1033{
1034 int i;
1035
1036 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
1037
1038 for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++)
1039 iowrite32(ring->state[i], ring->pdma->csr_ring +
1040 XGENE_DMA_RING_STATE_WR_BASE + (i * 4));
1041}
1042
1043static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring)
1044{
1045 memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG);
1046 xgene_dma_wr_ring_state(ring);
1047}
1048
1049static void xgene_dma_setup_ring(struct xgene_dma_ring *ring)
1050{
1051 void *ring_cfg = ring->state;
1052 u64 addr = ring->desc_paddr;
1053 u32 i, val;
1054
1055 ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE;
1056
1057 /* Clear DMA ring state */
1058 xgene_dma_clr_ring_state(ring);
1059
1060 /* Set DMA ring type */
1061 XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR);
1062
1063 if (ring->owner == XGENE_DMA_RING_OWNER_DMA) {
1064 /* Set recombination buffer and timeout */
1065 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg);
1066 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg);
1067 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg);
1068 }
1069
1070 /* Initialize DMA ring state */
1071 XGENE_DMA_RING_SELTHRSH_SET(ring_cfg);
1072 XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg);
1073 XGENE_DMA_RING_COHERENT_SET(ring_cfg);
1074 XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr);
1075 XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr);
1076 XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize);
1077
1078 /* Write DMA ring configurations */
1079 xgene_dma_wr_ring_state(ring);
1080
1081 /* Set DMA ring id */
1082 iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id),
1083 ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1084
1085 /* Set DMA ring buffer */
1086 iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num),
1087 ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1088
1089 if (ring->owner != XGENE_DMA_RING_OWNER_CPU)
1090 return;
1091
1092 /* Set empty signature to DMA Rx ring descriptors */
1093 for (i = 0; i < ring->slots; i++) {
1094 struct xgene_dma_desc_hw *desc;
1095
1096 desc = &ring->desc_hw[i];
1097 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
1098 }
1099
1100 /* Enable DMA Rx ring interrupt */
1101 val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1102 XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num);
1103 iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1104}
1105
1106static void xgene_dma_clear_ring(struct xgene_dma_ring *ring)
1107{
1108 u32 ring_id, val;
1109
1110 if (ring->owner == XGENE_DMA_RING_OWNER_CPU) {
1111 /* Disable DMA Rx ring interrupt */
1112 val = ioread32(ring->pdma->csr_ring +
1113 XGENE_DMA_RING_NE_INT_MODE);
1114 XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num);
1115 iowrite32(val, ring->pdma->csr_ring +
1116 XGENE_DMA_RING_NE_INT_MODE);
1117 }
1118
1119 /* Clear DMA ring state */
1120 ring_id = XGENE_DMA_RING_ID_SETUP(ring->id);
1121 iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1122
1123 iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1124 xgene_dma_clr_ring_state(ring);
1125}
1126
1127static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring)
1128{
1129 ring->cmd_base = ring->pdma->csr_ring_cmd +
1130 XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num -
1131 XGENE_DMA_RING_NUM));
1132
1133 ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET;
1134}
1135
1136static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan,
1137 enum xgene_dma_ring_cfgsize cfgsize)
1138{
1139 int size;
1140
1141 switch (cfgsize) {
1142 case XGENE_DMA_RING_CFG_SIZE_512B:
1143 size = 0x200;
1144 break;
1145 case XGENE_DMA_RING_CFG_SIZE_2KB:
1146 size = 0x800;
1147 break;
1148 case XGENE_DMA_RING_CFG_SIZE_16KB:
1149 size = 0x4000;
1150 break;
1151 case XGENE_DMA_RING_CFG_SIZE_64KB:
1152 size = 0x10000;
1153 break;
1154 case XGENE_DMA_RING_CFG_SIZE_512KB:
1155 size = 0x80000;
1156 break;
1157 default:
1158 chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize);
1159 return -EINVAL;
1160 }
1161
1162 return size;
1163}
1164
1165static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring)
1166{
1167 /* Clear DMA ring configurations */
1168 xgene_dma_clear_ring(ring);
1169
1170 /* De-allocate DMA ring descriptor */
1171 if (ring->desc_vaddr) {
1172 dma_free_coherent(ring->pdma->dev, ring->size,
1173 ring->desc_vaddr, ring->desc_paddr);
1174 ring->desc_vaddr = NULL;
1175 }
1176}
1177
1178static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan)
1179{
1180 xgene_dma_delete_ring_one(&chan->rx_ring);
1181 xgene_dma_delete_ring_one(&chan->tx_ring);
1182}
1183
1184static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan,
1185 struct xgene_dma_ring *ring,
1186 enum xgene_dma_ring_cfgsize cfgsize)
1187{
1188 int ret;
1189
1190 /* Setup DMA ring descriptor variables */
1191 ring->pdma = chan->pdma;
1192 ring->cfgsize = cfgsize;
1193 ring->num = chan->pdma->ring_num++;
1194 ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num);
1195
1196 ret = xgene_dma_get_ring_size(chan, cfgsize);
1197 if (ret <= 0)
1198 return ret;
1199 ring->size = ret;
1200
1201 /* Allocate memory for DMA ring descriptor */
1202 ring->desc_vaddr = dma_alloc_coherent(chan->dev, ring->size,
1203 &ring->desc_paddr, GFP_KERNEL);
1204 if (!ring->desc_vaddr) {
1205 chan_err(chan, "Failed to allocate ring desc\n");
1206 return -ENOMEM;
1207 }
1208
1209 /* Configure and enable DMA ring */
1210 xgene_dma_set_ring_cmd(ring);
1211 xgene_dma_setup_ring(ring);
1212
1213 return 0;
1214}
1215
1216static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan)
1217{
1218 struct xgene_dma_ring *rx_ring = &chan->rx_ring;
1219 struct xgene_dma_ring *tx_ring = &chan->tx_ring;
1220 int ret;
1221
1222 /* Create DMA Rx ring descriptor */
1223 rx_ring->owner = XGENE_DMA_RING_OWNER_CPU;
1224 rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id;
1225
1226 ret = xgene_dma_create_ring_one(chan, rx_ring,
1227 XGENE_DMA_RING_CFG_SIZE_64KB);
1228 if (ret)
1229 return ret;
1230
1231 chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n",
1232 rx_ring->id, rx_ring->num, rx_ring->desc_vaddr);
1233
1234 /* Create DMA Tx ring descriptor */
1235 tx_ring->owner = XGENE_DMA_RING_OWNER_DMA;
1236 tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id;
1237
1238 ret = xgene_dma_create_ring_one(chan, tx_ring,
1239 XGENE_DMA_RING_CFG_SIZE_64KB);
1240 if (ret) {
1241 xgene_dma_delete_ring_one(rx_ring);
1242 return ret;
1243 }
1244
1245 tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num);
1246
1247 chan_dbg(chan,
1248 "Tx ring id 0x%X num %d desc 0x%p\n",
1249 tx_ring->id, tx_ring->num, tx_ring->desc_vaddr);
1250
1251 /* Set the max outstanding request possible to this channel */
1252 chan->max_outstanding = tx_ring->slots;
1253
1254 return ret;
1255}
1256
1257static int xgene_dma_init_rings(struct xgene_dma *pdma)
1258{
1259 int ret, i, j;
1260
1261 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1262 ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
1263 if (ret) {
1264 for (j = 0; j < i; j++)
1265 xgene_dma_delete_chan_rings(&pdma->chan[j]);
1266 return ret;
1267 }
1268 }
1269
1270 return ret;
1271}
1272
1273static void xgene_dma_enable(struct xgene_dma *pdma)
1274{
1275 u32 val;
1276
1277 /* Configure and enable DMA engine */
1278 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1279 XGENE_DMA_CH_SETUP(val);
1280 XGENE_DMA_ENABLE(val);
1281 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1282}
1283
1284static void xgene_dma_disable(struct xgene_dma *pdma)
1285{
1286 u32 val;
1287
1288 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1289 XGENE_DMA_DISABLE(val);
1290 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1291}
1292
1293static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
1294{
1295 /*
1296 * Mask DMA ring overflow, underflow and
1297 * AXI write/read error interrupts
1298 */
1299 iowrite32(XGENE_DMA_INT_ALL_MASK,
1300 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1301 iowrite32(XGENE_DMA_INT_ALL_MASK,
1302 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1303 iowrite32(XGENE_DMA_INT_ALL_MASK,
1304 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1305 iowrite32(XGENE_DMA_INT_ALL_MASK,
1306 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1307 iowrite32(XGENE_DMA_INT_ALL_MASK,
1308 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1309
1310 /* Mask DMA error interrupts */
1311 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1312}
1313
1314static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
1315{
1316 /*
1317 * Unmask DMA ring overflow, underflow and
1318 * AXI write/read error interrupts
1319 */
1320 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1321 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1322 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1323 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1324 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1325 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1326 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1327 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1328 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1329 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1330
1331 /* Unmask DMA error interrupts */
1332 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1333 pdma->csr_dma + XGENE_DMA_INT_MASK);
1334}
1335
1336static void xgene_dma_init_hw(struct xgene_dma *pdma)
1337{
1338 u32 val;
1339
1340 /* Associate DMA ring to corresponding ring HW */
1341 iowrite32(XGENE_DMA_ASSOC_RING_MNGR1,
1342 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1343
1344 /* Configure RAID6 polynomial control setting */
1345 if (is_pq_enabled(pdma))
1346 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D),
1347 pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1348 else
1349 dev_info(pdma->dev, "PQ is disabled in HW\n");
1350
1351 xgene_dma_enable(pdma);
1352 xgene_dma_unmask_interrupts(pdma);
1353
1354 /* Get DMA id and version info */
1355 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1356
1357 /* DMA device info */
1358 dev_info(pdma->dev,
1359 "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
1360 XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val),
1361 XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL);
1362}
1363
1364static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
1365{
1366 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
1367 (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
1368 return 0;
1369
1370 iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
1371 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
1372
1373 /* Bring up memory */
1374 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1375
1376 /* Force a barrier */
1377 ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1378
1379 /* reset may take up to 1ms */
1380 usleep_range(1000, 1100);
1381
1382 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
1383 != XGENE_DMA_RING_BLK_MEM_RDY_VAL) {
1384 dev_err(pdma->dev,
1385 "Failed to release ring mngr memory from shutdown\n");
1386 return -ENODEV;
1387 }
1388
1389 /* program threshold set 1 and all hysteresis */
1390 iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL,
1391 pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
1392 iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL,
1393 pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
1394 iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL,
1395 pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
1396
1397 /* Enable QPcore and assign error queue */
1398 iowrite32(XGENE_DMA_RING_ENABLE,
1399 pdma->csr_ring + XGENE_DMA_RING_CONFIG);
1400
1401 return 0;
1402}
1403
1404static int xgene_dma_init_mem(struct xgene_dma *pdma)
1405{
1406 int ret;
1407
1408 ret = xgene_dma_init_ring_mngr(pdma);
1409 if (ret)
1410 return ret;
1411
1412 /* Bring up memory */
1413 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1414
1415 /* Force a barrier */
1416 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1417
1418 /* reset may take up to 1ms */
1419 usleep_range(1000, 1100);
1420
1421 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1422 != XGENE_DMA_BLK_MEM_RDY_VAL) {
1423 dev_err(pdma->dev,
1424 "Failed to release DMA memory from shutdown\n");
1425 return -ENODEV;
1426 }
1427
1428 return 0;
1429}
1430
1431static int xgene_dma_request_irqs(struct xgene_dma *pdma)
1432{
1433 struct xgene_dma_chan *chan;
1434 int ret, i, j;
1435
1436 /* Register DMA error irq */
1437 ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
1438 0, "dma_error", pdma);
1439 if (ret) {
1440 dev_err(pdma->dev,
1441 "Failed to register error IRQ %d\n", pdma->err_irq);
1442 return ret;
1443 }
1444
1445 /* Register DMA channel rx irq */
1446 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1447 chan = &pdma->chan[i];
1448 irq_set_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
1449 ret = devm_request_irq(chan->dev, chan->rx_irq,
1450 xgene_dma_chan_ring_isr,
1451 0, chan->name, chan);
1452 if (ret) {
1453 chan_err(chan, "Failed to register Rx IRQ %d\n",
1454 chan->rx_irq);
1455 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1456
1457 for (j = 0; j < i; j++) {
1458 chan = &pdma->chan[i];
1459 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
1460 devm_free_irq(chan->dev, chan->rx_irq, chan);
1461 }
1462
1463 return ret;
1464 }
1465 }
1466
1467 return 0;
1468}
1469
1470static void xgene_dma_free_irqs(struct xgene_dma *pdma)
1471{
1472 struct xgene_dma_chan *chan;
1473 int i;
1474
1475 /* Free DMA device error irq */
1476 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1477
1478 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1479 chan = &pdma->chan[i];
1480 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
1481 devm_free_irq(chan->dev, chan->rx_irq, chan);
1482 }
1483}
1484
1485static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
1486 struct dma_device *dma_dev)
1487{
1488 /* Initialize DMA device capability mask */
1489 dma_cap_zero(dma_dev->cap_mask);
1490
1491 /* Set DMA device capability */
1492
1493 /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
1494 * and channel 1 supports XOR, PQ both. First thing here is we have
1495 * mechanism in hw to enable/disable PQ/XOR supports on channel 1,
1496 * we can make sure this by reading SoC Efuse register.
1497 * Second thing, we have hw errata that if we run channel 0 and
1498 * channel 1 simultaneously with executing XOR and PQ request,
1499 * suddenly DMA engine hangs, So here we enable XOR on channel 0 only
1500 * if XOR and PQ supports on channel 1 is disabled.
1501 */
1502 if ((chan->id == XGENE_DMA_PQ_CHANNEL) &&
1503 is_pq_enabled(chan->pdma)) {
1504 dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1505 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1506 } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) &&
1507 !is_pq_enabled(chan->pdma)) {
1508 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1509 }
1510
1511 /* Set base and prep routines */
1512 dma_dev->dev = chan->dev;
1513 dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources;
1514 dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
1515 dma_dev->device_issue_pending = xgene_dma_issue_pending;
1516 dma_dev->device_tx_status = xgene_dma_tx_status;
1517
1518 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1519 dma_dev->device_prep_dma_xor = xgene_dma_prep_xor;
1520 dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC;
1521 dma_dev->xor_align = DMAENGINE_ALIGN_64_BYTES;
1522 }
1523
1524 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1525 dma_dev->device_prep_dma_pq = xgene_dma_prep_pq;
1526 dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC;
1527 dma_dev->pq_align = DMAENGINE_ALIGN_64_BYTES;
1528 }
1529}
1530
1531static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
1532{
1533 struct xgene_dma_chan *chan = &pdma->chan[id];
1534 struct dma_device *dma_dev = &pdma->dma_dev[id];
1535 int ret;
1536
1537 chan->dma_chan.device = dma_dev;
1538
1539 spin_lock_init(&chan->lock);
1540 INIT_LIST_HEAD(&chan->ld_pending);
1541 INIT_LIST_HEAD(&chan->ld_running);
1542 INIT_LIST_HEAD(&chan->ld_completed);
1543 tasklet_setup(&chan->tasklet, xgene_dma_tasklet_cb);
1544
1545 chan->pending = 0;
1546 chan->desc_pool = NULL;
1547 dma_cookie_init(&chan->dma_chan);
1548
1549 /* Setup dma device capabilities and prep routines */
1550 xgene_dma_set_caps(chan, dma_dev);
1551
1552 /* Initialize DMA device list head */
1553 INIT_LIST_HEAD(&dma_dev->channels);
1554 list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);
1555
1556 /* Register with Linux async DMA framework*/
1557 ret = dma_async_device_register(dma_dev);
1558 if (ret) {
1559 chan_err(chan, "Failed to register async device %d", ret);
1560 tasklet_kill(&chan->tasklet);
1561
1562 return ret;
1563 }
1564
1565 /* DMA capability info */
1566 dev_info(pdma->dev,
1567 "%s: CAPABILITY ( %s%s)\n", dma_chan_name(&chan->dma_chan),
1568 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
1569 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");
1570
1571 return 0;
1572}
1573
1574static int xgene_dma_init_async(struct xgene_dma *pdma)
1575{
1576 int ret, i, j;
1577
1578 for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) {
1579 ret = xgene_dma_async_register(pdma, i);
1580 if (ret) {
1581 for (j = 0; j < i; j++) {
1582 dma_async_device_unregister(&pdma->dma_dev[j]);
1583 tasklet_kill(&pdma->chan[j].tasklet);
1584 }
1585
1586 return ret;
1587 }
1588 }
1589
1590 return ret;
1591}
1592
1593static void xgene_dma_async_unregister(struct xgene_dma *pdma)
1594{
1595 int i;
1596
1597 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1598 dma_async_device_unregister(&pdma->dma_dev[i]);
1599}
1600
1601static void xgene_dma_init_channels(struct xgene_dma *pdma)
1602{
1603 struct xgene_dma_chan *chan;
1604 int i;
1605
1606 pdma->ring_num = XGENE_DMA_RING_NUM;
1607
1608 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1609 chan = &pdma->chan[i];
1610 chan->dev = pdma->dev;
1611 chan->pdma = pdma;
1612 chan->id = i;
1613 snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id);
1614 }
1615}
1616
1617static int xgene_dma_get_resources(struct platform_device *pdev,
1618 struct xgene_dma *pdma)
1619{
1620 struct resource *res;
1621 int irq, i;
1622
1623 /* Get DMA csr region */
1624 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1625 if (!res) {
1626 dev_err(&pdev->dev, "Failed to get csr region\n");
1627 return -ENXIO;
1628 }
1629
1630 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1631 resource_size(res));
1632 if (!pdma->csr_dma) {
1633 dev_err(&pdev->dev, "Failed to ioremap csr region");
1634 return -ENOMEM;
1635 }
1636
1637 /* Get DMA ring csr region */
1638 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1639 if (!res) {
1640 dev_err(&pdev->dev, "Failed to get ring csr region\n");
1641 return -ENXIO;
1642 }
1643
1644 pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
1645 resource_size(res));
1646 if (!pdma->csr_ring) {
1647 dev_err(&pdev->dev, "Failed to ioremap ring csr region");
1648 return -ENOMEM;
1649 }
1650
1651 /* Get DMA ring cmd csr region */
1652 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1653 if (!res) {
1654 dev_err(&pdev->dev, "Failed to get ring cmd csr region\n");
1655 return -ENXIO;
1656 }
1657
1658 pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
1659 resource_size(res));
1660 if (!pdma->csr_ring_cmd) {
1661 dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
1662 return -ENOMEM;
1663 }
1664
1665 pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
1666
1667 /* Get efuse csr region */
1668 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1669 if (!res) {
1670 dev_err(&pdev->dev, "Failed to get efuse csr region\n");
1671 return -ENXIO;
1672 }
1673
1674 pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
1675 resource_size(res));
1676 if (!pdma->csr_efuse) {
1677 dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
1678 return -ENOMEM;
1679 }
1680
1681 /* Get DMA error interrupt */
1682 irq = platform_get_irq(pdev, 0);
1683 if (irq <= 0)
1684 return -ENXIO;
1685
1686 pdma->err_irq = irq;
1687
1688 /* Get DMA Rx ring descriptor interrupts for all DMA channels */
1689 for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) {
1690 irq = platform_get_irq(pdev, i);
1691 if (irq <= 0)
1692 return -ENXIO;
1693
1694 pdma->chan[i - 1].rx_irq = irq;
1695 }
1696
1697 return 0;
1698}
1699
1700static int xgene_dma_probe(struct platform_device *pdev)
1701{
1702 struct xgene_dma *pdma;
1703 int ret, i;
1704
1705 pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
1706 if (!pdma)
1707 return -ENOMEM;
1708
1709 pdma->dev = &pdev->dev;
1710 platform_set_drvdata(pdev, pdma);
1711
1712 ret = xgene_dma_get_resources(pdev, pdma);
1713 if (ret)
1714 return ret;
1715
1716 pdma->clk = devm_clk_get(&pdev->dev, NULL);
1717 if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) {
1718 dev_err(&pdev->dev, "Failed to get clk\n");
1719 return PTR_ERR(pdma->clk);
1720 }
1721
1722 /* Enable clk before accessing registers */
1723 if (!IS_ERR(pdma->clk)) {
1724 ret = clk_prepare_enable(pdma->clk);
1725 if (ret) {
1726 dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
1727 return ret;
1728 }
1729 }
1730
1731 /* Remove DMA RAM out of shutdown */
1732 ret = xgene_dma_init_mem(pdma);
1733 if (ret)
1734 goto err_clk_enable;
1735
1736 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42));
1737 if (ret) {
1738 dev_err(&pdev->dev, "No usable DMA configuration\n");
1739 goto err_dma_mask;
1740 }
1741
1742 /* Initialize DMA channels software state */
1743 xgene_dma_init_channels(pdma);
1744
1745 /* Configue DMA rings */
1746 ret = xgene_dma_init_rings(pdma);
1747 if (ret)
1748 goto err_clk_enable;
1749
1750 ret = xgene_dma_request_irqs(pdma);
1751 if (ret)
1752 goto err_request_irq;
1753
1754 /* Configure and enable DMA engine */
1755 xgene_dma_init_hw(pdma);
1756
1757 /* Register DMA device with linux async framework */
1758 ret = xgene_dma_init_async(pdma);
1759 if (ret)
1760 goto err_async_init;
1761
1762 return 0;
1763
1764err_async_init:
1765 xgene_dma_free_irqs(pdma);
1766
1767err_request_irq:
1768 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1769 xgene_dma_delete_chan_rings(&pdma->chan[i]);
1770
1771err_dma_mask:
1772err_clk_enable:
1773 if (!IS_ERR(pdma->clk))
1774 clk_disable_unprepare(pdma->clk);
1775
1776 return ret;
1777}
1778
1779static void xgene_dma_remove(struct platform_device *pdev)
1780{
1781 struct xgene_dma *pdma = platform_get_drvdata(pdev);
1782 struct xgene_dma_chan *chan;
1783 int i;
1784
1785 xgene_dma_async_unregister(pdma);
1786
1787 /* Mask interrupts and disable DMA engine */
1788 xgene_dma_mask_interrupts(pdma);
1789 xgene_dma_disable(pdma);
1790 xgene_dma_free_irqs(pdma);
1791
1792 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1793 chan = &pdma->chan[i];
1794 tasklet_kill(&chan->tasklet);
1795 xgene_dma_delete_chan_rings(chan);
1796 }
1797
1798 if (!IS_ERR(pdma->clk))
1799 clk_disable_unprepare(pdma->clk);
1800}
1801
1802#ifdef CONFIG_ACPI
1803static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = {
1804 {"APMC0D43", 0},
1805 {},
1806};
1807MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr);
1808#endif
1809
1810static const struct of_device_id xgene_dma_of_match_ptr[] = {
1811 {.compatible = "apm,xgene-storm-dma",},
1812 {},
1813};
1814MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr);
1815
1816static struct platform_driver xgene_dma_driver = {
1817 .probe = xgene_dma_probe,
1818 .remove_new = xgene_dma_remove,
1819 .driver = {
1820 .name = "X-Gene-DMA",
1821 .of_match_table = xgene_dma_of_match_ptr,
1822 .acpi_match_table = ACPI_PTR(xgene_dma_acpi_match_ptr),
1823 },
1824};
1825
1826module_platform_driver(xgene_dma_driver);
1827
1828MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
1829MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>");
1830MODULE_AUTHOR("Loc Ho <lho@apm.com>");
1831MODULE_LICENSE("GPL");
1832MODULE_VERSION("1.0");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Applied Micro X-Gene SoC DMA engine Driver
4 *
5 * Copyright (c) 2015, Applied Micro Circuits Corporation
6 * Authors: Rameshwar Prasad Sahu <rsahu@apm.com>
7 * Loc Ho <lho@apm.com>
8 *
9 * NOTE: PM support is currently not available.
10 */
11
12#include <linux/acpi.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dma-mapping.h>
16#include <linux/dmaengine.h>
17#include <linux/dmapool.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/module.h>
22#include <linux/of_device.h>
23
24#include "dmaengine.h"
25
26/* X-Gene DMA ring csr registers and bit definations */
27#define XGENE_DMA_RING_CONFIG 0x04
28#define XGENE_DMA_RING_ENABLE BIT(31)
29#define XGENE_DMA_RING_ID 0x08
30#define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
31#define XGENE_DMA_RING_ID_BUF 0x0C
32#define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
33#define XGENE_DMA_RING_THRESLD0_SET1 0x30
34#define XGENE_DMA_RING_THRESLD0_SET1_VAL 0X64
35#define XGENE_DMA_RING_THRESLD1_SET1 0x34
36#define XGENE_DMA_RING_THRESLD1_SET1_VAL 0xC8
37#define XGENE_DMA_RING_HYSTERESIS 0x68
38#define XGENE_DMA_RING_HYSTERESIS_VAL 0xFFFFFFFF
39#define XGENE_DMA_RING_STATE 0x6C
40#define XGENE_DMA_RING_STATE_WR_BASE 0x70
41#define XGENE_DMA_RING_NE_INT_MODE 0x017C
42#define XGENE_DMA_RING_NE_INT_MODE_SET(m, v) \
43 ((m) = ((m) & ~BIT(31 - (v))) | BIT(31 - (v)))
44#define XGENE_DMA_RING_NE_INT_MODE_RESET(m, v) \
45 ((m) &= (~BIT(31 - (v))))
46#define XGENE_DMA_RING_CLKEN 0xC208
47#define XGENE_DMA_RING_SRST 0xC200
48#define XGENE_DMA_RING_MEM_RAM_SHUTDOWN 0xD070
49#define XGENE_DMA_RING_BLK_MEM_RDY 0xD074
50#define XGENE_DMA_RING_BLK_MEM_RDY_VAL 0xFFFFFFFF
51#define XGENE_DMA_RING_ID_GET(owner, num) (((owner) << 6) | (num))
52#define XGENE_DMA_RING_DST_ID(v) ((1 << 10) | (v))
53#define XGENE_DMA_RING_CMD_OFFSET 0x2C
54#define XGENE_DMA_RING_CMD_BASE_OFFSET(v) ((v) << 6)
55#define XGENE_DMA_RING_COHERENT_SET(m) \
56 (((u32 *)(m))[2] |= BIT(4))
57#define XGENE_DMA_RING_ADDRL_SET(m, v) \
58 (((u32 *)(m))[2] |= (((v) >> 8) << 5))
59#define XGENE_DMA_RING_ADDRH_SET(m, v) \
60 (((u32 *)(m))[3] |= ((v) >> 35))
61#define XGENE_DMA_RING_ACCEPTLERR_SET(m) \
62 (((u32 *)(m))[3] |= BIT(19))
63#define XGENE_DMA_RING_SIZE_SET(m, v) \
64 (((u32 *)(m))[3] |= ((v) << 23))
65#define XGENE_DMA_RING_RECOMBBUF_SET(m) \
66 (((u32 *)(m))[3] |= BIT(27))
67#define XGENE_DMA_RING_RECOMTIMEOUTL_SET(m) \
68 (((u32 *)(m))[3] |= (0x7 << 28))
69#define XGENE_DMA_RING_RECOMTIMEOUTH_SET(m) \
70 (((u32 *)(m))[4] |= 0x3)
71#define XGENE_DMA_RING_SELTHRSH_SET(m) \
72 (((u32 *)(m))[4] |= BIT(3))
73#define XGENE_DMA_RING_TYPE_SET(m, v) \
74 (((u32 *)(m))[4] |= ((v) << 19))
75
76/* X-Gene DMA device csr registers and bit definitions */
77#define XGENE_DMA_IPBRR 0x0
78#define XGENE_DMA_DEV_ID_RD(v) ((v) & 0x00000FFF)
79#define XGENE_DMA_BUS_ID_RD(v) (((v) >> 12) & 3)
80#define XGENE_DMA_REV_NO_RD(v) (((v) >> 14) & 3)
81#define XGENE_DMA_GCR 0x10
82#define XGENE_DMA_CH_SETUP(v) \
83 ((v) = ((v) & ~0x000FFFFF) | 0x000AAFFF)
84#define XGENE_DMA_ENABLE(v) ((v) |= BIT(31))
85#define XGENE_DMA_DISABLE(v) ((v) &= ~BIT(31))
86#define XGENE_DMA_RAID6_CONT 0x14
87#define XGENE_DMA_RAID6_MULTI_CTRL(v) ((v) << 24)
88#define XGENE_DMA_INT 0x70
89#define XGENE_DMA_INT_MASK 0x74
90#define XGENE_DMA_INT_ALL_MASK 0xFFFFFFFF
91#define XGENE_DMA_INT_ALL_UNMASK 0x0
92#define XGENE_DMA_INT_MASK_SHIFT 0x14
93#define XGENE_DMA_RING_INT0_MASK 0x90A0
94#define XGENE_DMA_RING_INT1_MASK 0x90A8
95#define XGENE_DMA_RING_INT2_MASK 0x90B0
96#define XGENE_DMA_RING_INT3_MASK 0x90B8
97#define XGENE_DMA_RING_INT4_MASK 0x90C0
98#define XGENE_DMA_CFG_RING_WQ_ASSOC 0x90E0
99#define XGENE_DMA_ASSOC_RING_MNGR1 0xFFFFFFFF
100#define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
101#define XGENE_DMA_BLK_MEM_RDY 0xD074
102#define XGENE_DMA_BLK_MEM_RDY_VAL 0xFFFFFFFF
103#define XGENE_DMA_RING_CMD_SM_OFFSET 0x8000
104
105/* X-Gene SoC EFUSE csr register and bit defination */
106#define XGENE_SOC_JTAG1_SHADOW 0x18
107#define XGENE_DMA_PQ_DISABLE_MASK BIT(13)
108
109/* X-Gene DMA Descriptor format */
110#define XGENE_DMA_DESC_NV_BIT BIT_ULL(50)
111#define XGENE_DMA_DESC_IN_BIT BIT_ULL(55)
112#define XGENE_DMA_DESC_C_BIT BIT_ULL(63)
113#define XGENE_DMA_DESC_DR_BIT BIT_ULL(61)
114#define XGENE_DMA_DESC_ELERR_POS 46
115#define XGENE_DMA_DESC_RTYPE_POS 56
116#define XGENE_DMA_DESC_LERR_POS 60
117#define XGENE_DMA_DESC_BUFLEN_POS 48
118#define XGENE_DMA_DESC_HOENQ_NUM_POS 48
119#define XGENE_DMA_DESC_ELERR_RD(m) \
120 (((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
121#define XGENE_DMA_DESC_LERR_RD(m) \
122 (((m) >> XGENE_DMA_DESC_LERR_POS) & 0x7)
123#define XGENE_DMA_DESC_STATUS(elerr, lerr) \
124 (((elerr) << 4) | (lerr))
125
126/* X-Gene DMA descriptor empty s/w signature */
127#define XGENE_DMA_DESC_EMPTY_SIGNATURE ~0ULL
128
129/* X-Gene DMA configurable parameters defines */
130#define XGENE_DMA_RING_NUM 512
131#define XGENE_DMA_BUFNUM 0x0
132#define XGENE_DMA_CPU_BUFNUM 0x18
133#define XGENE_DMA_RING_OWNER_DMA 0x03
134#define XGENE_DMA_RING_OWNER_CPU 0x0F
135#define XGENE_DMA_RING_TYPE_REGULAR 0x01
136#define XGENE_DMA_RING_WQ_DESC_SIZE 32 /* 32 Bytes */
137#define XGENE_DMA_RING_NUM_CONFIG 5
138#define XGENE_DMA_MAX_CHANNEL 4
139#define XGENE_DMA_XOR_CHANNEL 0
140#define XGENE_DMA_PQ_CHANNEL 1
141#define XGENE_DMA_MAX_BYTE_CNT 0x4000 /* 16 KB */
142#define XGENE_DMA_MAX_64B_DESC_BYTE_CNT 0x14000 /* 80 KB */
143#define XGENE_DMA_MAX_XOR_SRC 5
144#define XGENE_DMA_16K_BUFFER_LEN_CODE 0x0
145#define XGENE_DMA_INVALID_LEN_CODE 0x7800000000000000ULL
146
147/* X-Gene DMA descriptor error codes */
148#define ERR_DESC_AXI 0x01
149#define ERR_BAD_DESC 0x02
150#define ERR_READ_DATA_AXI 0x03
151#define ERR_WRITE_DATA_AXI 0x04
152#define ERR_FBP_TIMEOUT 0x05
153#define ERR_ECC 0x06
154#define ERR_DIFF_SIZE 0x08
155#define ERR_SCT_GAT_LEN 0x09
156#define ERR_CRC_ERR 0x11
157#define ERR_CHKSUM 0x12
158#define ERR_DIF 0x13
159
160/* X-Gene DMA error interrupt codes */
161#define ERR_DIF_SIZE_INT 0x0
162#define ERR_GS_ERR_INT 0x1
163#define ERR_FPB_TIMEO_INT 0x2
164#define ERR_WFIFO_OVF_INT 0x3
165#define ERR_RFIFO_OVF_INT 0x4
166#define ERR_WR_TIMEO_INT 0x5
167#define ERR_RD_TIMEO_INT 0x6
168#define ERR_WR_ERR_INT 0x7
169#define ERR_RD_ERR_INT 0x8
170#define ERR_BAD_DESC_INT 0x9
171#define ERR_DESC_DST_INT 0xA
172#define ERR_DESC_SRC_INT 0xB
173
174/* X-Gene DMA flyby operation code */
175#define FLYBY_2SRC_XOR 0x80
176#define FLYBY_3SRC_XOR 0x90
177#define FLYBY_4SRC_XOR 0xA0
178#define FLYBY_5SRC_XOR 0xB0
179
180/* X-Gene DMA SW descriptor flags */
181#define XGENE_DMA_FLAG_64B_DESC BIT(0)
182
183/* Define to dump X-Gene DMA descriptor */
184#define XGENE_DMA_DESC_DUMP(desc, m) \
185 print_hex_dump(KERN_ERR, (m), \
186 DUMP_PREFIX_ADDRESS, 16, 8, (desc), 32, 0)
187
188#define to_dma_desc_sw(tx) \
189 container_of(tx, struct xgene_dma_desc_sw, tx)
190#define to_dma_chan(dchan) \
191 container_of(dchan, struct xgene_dma_chan, dma_chan)
192
193#define chan_dbg(chan, fmt, arg...) \
194 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
195#define chan_err(chan, fmt, arg...) \
196 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
197
198struct xgene_dma_desc_hw {
199 __le64 m0;
200 __le64 m1;
201 __le64 m2;
202 __le64 m3;
203};
204
205enum xgene_dma_ring_cfgsize {
206 XGENE_DMA_RING_CFG_SIZE_512B,
207 XGENE_DMA_RING_CFG_SIZE_2KB,
208 XGENE_DMA_RING_CFG_SIZE_16KB,
209 XGENE_DMA_RING_CFG_SIZE_64KB,
210 XGENE_DMA_RING_CFG_SIZE_512KB,
211 XGENE_DMA_RING_CFG_SIZE_INVALID
212};
213
214struct xgene_dma_ring {
215 struct xgene_dma *pdma;
216 u8 buf_num;
217 u16 id;
218 u16 num;
219 u16 head;
220 u16 owner;
221 u16 slots;
222 u16 dst_ring_num;
223 u32 size;
224 void __iomem *cmd;
225 void __iomem *cmd_base;
226 dma_addr_t desc_paddr;
227 u32 state[XGENE_DMA_RING_NUM_CONFIG];
228 enum xgene_dma_ring_cfgsize cfgsize;
229 union {
230 void *desc_vaddr;
231 struct xgene_dma_desc_hw *desc_hw;
232 };
233};
234
235struct xgene_dma_desc_sw {
236 struct xgene_dma_desc_hw desc1;
237 struct xgene_dma_desc_hw desc2;
238 u32 flags;
239 struct list_head node;
240 struct list_head tx_list;
241 struct dma_async_tx_descriptor tx;
242};
243
244/**
245 * struct xgene_dma_chan - internal representation of an X-Gene DMA channel
246 * @dma_chan: dmaengine channel object member
247 * @pdma: X-Gene DMA device structure reference
248 * @dev: struct device reference for dma mapping api
249 * @id: raw id of this channel
250 * @rx_irq: channel IRQ
251 * @name: name of X-Gene DMA channel
252 * @lock: serializes enqueue/dequeue operations to the descriptor pool
253 * @pending: number of transaction request pushed to DMA controller for
254 * execution, but still waiting for completion,
255 * @max_outstanding: max number of outstanding request we can push to channel
256 * @ld_pending: descriptors which are queued to run, but have not yet been
257 * submitted to the hardware for execution
258 * @ld_running: descriptors which are currently being executing by the hardware
259 * @ld_completed: descriptors which have finished execution by the hardware.
260 * These descriptors have already had their cleanup actions run. They
261 * are waiting for the ACK bit to be set by the async tx API.
262 * @desc_pool: descriptor pool for DMA operations
263 * @tasklet: bottom half where all completed descriptors cleans
264 * @tx_ring: transmit ring descriptor that we use to prepare actual
265 * descriptors for further executions
266 * @rx_ring: receive ring descriptor that we use to get completed DMA
267 * descriptors during cleanup time
268 */
269struct xgene_dma_chan {
270 struct dma_chan dma_chan;
271 struct xgene_dma *pdma;
272 struct device *dev;
273 int id;
274 int rx_irq;
275 char name[10];
276 spinlock_t lock;
277 int pending;
278 int max_outstanding;
279 struct list_head ld_pending;
280 struct list_head ld_running;
281 struct list_head ld_completed;
282 struct dma_pool *desc_pool;
283 struct tasklet_struct tasklet;
284 struct xgene_dma_ring tx_ring;
285 struct xgene_dma_ring rx_ring;
286};
287
288/**
289 * struct xgene_dma - internal representation of an X-Gene DMA device
290 * @err_irq: DMA error irq number
291 * @ring_num: start id number for DMA ring
292 * @csr_dma: base for DMA register access
293 * @csr_ring: base for DMA ring register access
294 * @csr_ring_cmd: base for DMA ring command register access
295 * @csr_efuse: base for efuse register access
296 * @dma_dev: embedded struct dma_device
297 * @chan: reference to X-Gene DMA channels
298 */
299struct xgene_dma {
300 struct device *dev;
301 struct clk *clk;
302 int err_irq;
303 int ring_num;
304 void __iomem *csr_dma;
305 void __iomem *csr_ring;
306 void __iomem *csr_ring_cmd;
307 void __iomem *csr_efuse;
308 struct dma_device dma_dev[XGENE_DMA_MAX_CHANNEL];
309 struct xgene_dma_chan chan[XGENE_DMA_MAX_CHANNEL];
310};
311
312static const char * const xgene_dma_desc_err[] = {
313 [ERR_DESC_AXI] = "AXI error when reading src/dst link list",
314 [ERR_BAD_DESC] = "ERR or El_ERR fields not set to zero in desc",
315 [ERR_READ_DATA_AXI] = "AXI error when reading data",
316 [ERR_WRITE_DATA_AXI] = "AXI error when writing data",
317 [ERR_FBP_TIMEOUT] = "Timeout on bufpool fetch",
318 [ERR_ECC] = "ECC double bit error",
319 [ERR_DIFF_SIZE] = "Bufpool too small to hold all the DIF result",
320 [ERR_SCT_GAT_LEN] = "Gather and scatter data length not same",
321 [ERR_CRC_ERR] = "CRC error",
322 [ERR_CHKSUM] = "Checksum error",
323 [ERR_DIF] = "DIF error",
324};
325
326static const char * const xgene_dma_err[] = {
327 [ERR_DIF_SIZE_INT] = "DIF size error",
328 [ERR_GS_ERR_INT] = "Gather scatter not same size error",
329 [ERR_FPB_TIMEO_INT] = "Free pool time out error",
330 [ERR_WFIFO_OVF_INT] = "Write FIFO over flow error",
331 [ERR_RFIFO_OVF_INT] = "Read FIFO over flow error",
332 [ERR_WR_TIMEO_INT] = "Write time out error",
333 [ERR_RD_TIMEO_INT] = "Read time out error",
334 [ERR_WR_ERR_INT] = "HBF bus write error",
335 [ERR_RD_ERR_INT] = "HBF bus read error",
336 [ERR_BAD_DESC_INT] = "Ring descriptor HE0 not set error",
337 [ERR_DESC_DST_INT] = "HFB reading dst link address error",
338 [ERR_DESC_SRC_INT] = "HFB reading src link address error",
339};
340
341static bool is_pq_enabled(struct xgene_dma *pdma)
342{
343 u32 val;
344
345 val = ioread32(pdma->csr_efuse + XGENE_SOC_JTAG1_SHADOW);
346 return !(val & XGENE_DMA_PQ_DISABLE_MASK);
347}
348
349static u64 xgene_dma_encode_len(size_t len)
350{
351 return (len < XGENE_DMA_MAX_BYTE_CNT) ?
352 ((u64)len << XGENE_DMA_DESC_BUFLEN_POS) :
353 XGENE_DMA_16K_BUFFER_LEN_CODE;
354}
355
356static u8 xgene_dma_encode_xor_flyby(u32 src_cnt)
357{
358 static u8 flyby_type[] = {
359 FLYBY_2SRC_XOR, /* Dummy */
360 FLYBY_2SRC_XOR, /* Dummy */
361 FLYBY_2SRC_XOR,
362 FLYBY_3SRC_XOR,
363 FLYBY_4SRC_XOR,
364 FLYBY_5SRC_XOR
365 };
366
367 return flyby_type[src_cnt];
368}
369
370static void xgene_dma_set_src_buffer(__le64 *ext8, size_t *len,
371 dma_addr_t *paddr)
372{
373 size_t nbytes = (*len < XGENE_DMA_MAX_BYTE_CNT) ?
374 *len : XGENE_DMA_MAX_BYTE_CNT;
375
376 *ext8 |= cpu_to_le64(*paddr);
377 *ext8 |= cpu_to_le64(xgene_dma_encode_len(nbytes));
378 *len -= nbytes;
379 *paddr += nbytes;
380}
381
382static __le64 *xgene_dma_lookup_ext8(struct xgene_dma_desc_hw *desc, int idx)
383{
384 switch (idx) {
385 case 0:
386 return &desc->m1;
387 case 1:
388 return &desc->m0;
389 case 2:
390 return &desc->m3;
391 case 3:
392 return &desc->m2;
393 default:
394 pr_err("Invalid dma descriptor index\n");
395 }
396
397 return NULL;
398}
399
400static void xgene_dma_init_desc(struct xgene_dma_desc_hw *desc,
401 u16 dst_ring_num)
402{
403 desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT);
404 desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA <<
405 XGENE_DMA_DESC_RTYPE_POS);
406 desc->m1 |= cpu_to_le64(XGENE_DMA_DESC_C_BIT);
407 desc->m3 |= cpu_to_le64((u64)dst_ring_num <<
408 XGENE_DMA_DESC_HOENQ_NUM_POS);
409}
410
411static void xgene_dma_prep_xor_desc(struct xgene_dma_chan *chan,
412 struct xgene_dma_desc_sw *desc_sw,
413 dma_addr_t *dst, dma_addr_t *src,
414 u32 src_cnt, size_t *nbytes,
415 const u8 *scf)
416{
417 struct xgene_dma_desc_hw *desc1, *desc2;
418 size_t len = *nbytes;
419 int i;
420
421 desc1 = &desc_sw->desc1;
422 desc2 = &desc_sw->desc2;
423
424 /* Initialize DMA descriptor */
425 xgene_dma_init_desc(desc1, chan->tx_ring.dst_ring_num);
426
427 /* Set destination address */
428 desc1->m2 |= cpu_to_le64(XGENE_DMA_DESC_DR_BIT);
429 desc1->m3 |= cpu_to_le64(*dst);
430
431 /* We have multiple source addresses, so need to set NV bit*/
432 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT);
433
434 /* Set flyby opcode */
435 desc1->m2 |= cpu_to_le64(xgene_dma_encode_xor_flyby(src_cnt));
436
437 /* Set 1st to 5th source addresses */
438 for (i = 0; i < src_cnt; i++) {
439 len = *nbytes;
440 xgene_dma_set_src_buffer((i == 0) ? &desc1->m1 :
441 xgene_dma_lookup_ext8(desc2, i - 1),
442 &len, &src[i]);
443 desc1->m2 |= cpu_to_le64((scf[i] << ((i + 1) * 8)));
444 }
445
446 /* Update meta data */
447 *nbytes = len;
448 *dst += XGENE_DMA_MAX_BYTE_CNT;
449
450 /* We need always 64B descriptor to perform xor or pq operations */
451 desc_sw->flags |= XGENE_DMA_FLAG_64B_DESC;
452}
453
454static dma_cookie_t xgene_dma_tx_submit(struct dma_async_tx_descriptor *tx)
455{
456 struct xgene_dma_desc_sw *desc;
457 struct xgene_dma_chan *chan;
458 dma_cookie_t cookie;
459
460 if (unlikely(!tx))
461 return -EINVAL;
462
463 chan = to_dma_chan(tx->chan);
464 desc = to_dma_desc_sw(tx);
465
466 spin_lock_bh(&chan->lock);
467
468 cookie = dma_cookie_assign(tx);
469
470 /* Add this transaction list onto the tail of the pending queue */
471 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
472
473 spin_unlock_bh(&chan->lock);
474
475 return cookie;
476}
477
478static void xgene_dma_clean_descriptor(struct xgene_dma_chan *chan,
479 struct xgene_dma_desc_sw *desc)
480{
481 list_del(&desc->node);
482 chan_dbg(chan, "LD %p free\n", desc);
483 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
484}
485
486static struct xgene_dma_desc_sw *xgene_dma_alloc_descriptor(
487 struct xgene_dma_chan *chan)
488{
489 struct xgene_dma_desc_sw *desc;
490 dma_addr_t phys;
491
492 desc = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
493 if (!desc) {
494 chan_err(chan, "Failed to allocate LDs\n");
495 return NULL;
496 }
497
498 INIT_LIST_HEAD(&desc->tx_list);
499 desc->tx.phys = phys;
500 desc->tx.tx_submit = xgene_dma_tx_submit;
501 dma_async_tx_descriptor_init(&desc->tx, &chan->dma_chan);
502
503 chan_dbg(chan, "LD %p allocated\n", desc);
504
505 return desc;
506}
507
508/**
509 * xgene_dma_clean_completed_descriptor - free all descriptors which
510 * has been completed and acked
511 * @chan: X-Gene DMA channel
512 *
513 * This function is used on all completed and acked descriptors.
514 */
515static void xgene_dma_clean_completed_descriptor(struct xgene_dma_chan *chan)
516{
517 struct xgene_dma_desc_sw *desc, *_desc;
518
519 /* Run the callback for each descriptor, in order */
520 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node) {
521 if (async_tx_test_ack(&desc->tx))
522 xgene_dma_clean_descriptor(chan, desc);
523 }
524}
525
526/**
527 * xgene_dma_run_tx_complete_actions - cleanup a single link descriptor
528 * @chan: X-Gene DMA channel
529 * @desc: descriptor to cleanup and free
530 *
531 * This function is used on a descriptor which has been executed by the DMA
532 * controller. It will run any callbacks, submit any dependencies.
533 */
534static void xgene_dma_run_tx_complete_actions(struct xgene_dma_chan *chan,
535 struct xgene_dma_desc_sw *desc)
536{
537 struct dma_async_tx_descriptor *tx = &desc->tx;
538
539 /*
540 * If this is not the last transaction in the group,
541 * then no need to complete cookie and run any callback as
542 * this is not the tx_descriptor which had been sent to caller
543 * of this DMA request
544 */
545
546 if (tx->cookie == 0)
547 return;
548
549 dma_cookie_complete(tx);
550 dma_descriptor_unmap(tx);
551
552 /* Run the link descriptor callback function */
553 dmaengine_desc_get_callback_invoke(tx, NULL);
554
555 /* Run any dependencies */
556 dma_run_dependencies(tx);
557}
558
559/**
560 * xgene_dma_clean_running_descriptor - move the completed descriptor from
561 * ld_running to ld_completed
562 * @chan: X-Gene DMA channel
563 * @desc: the descriptor which is completed
564 *
565 * Free the descriptor directly if acked by async_tx api,
566 * else move it to queue ld_completed.
567 */
568static void xgene_dma_clean_running_descriptor(struct xgene_dma_chan *chan,
569 struct xgene_dma_desc_sw *desc)
570{
571 /* Remove from the list of running transactions */
572 list_del(&desc->node);
573
574 /*
575 * the client is allowed to attach dependent operations
576 * until 'ack' is set
577 */
578 if (!async_tx_test_ack(&desc->tx)) {
579 /*
580 * Move this descriptor to the list of descriptors which is
581 * completed, but still awaiting the 'ack' bit to be set.
582 */
583 list_add_tail(&desc->node, &chan->ld_completed);
584 return;
585 }
586
587 chan_dbg(chan, "LD %p free\n", desc);
588 dma_pool_free(chan->desc_pool, desc, desc->tx.phys);
589}
590
591static void xgene_chan_xfer_request(struct xgene_dma_chan *chan,
592 struct xgene_dma_desc_sw *desc_sw)
593{
594 struct xgene_dma_ring *ring = &chan->tx_ring;
595 struct xgene_dma_desc_hw *desc_hw;
596
597 /* Get hw descriptor from DMA tx ring */
598 desc_hw = &ring->desc_hw[ring->head];
599
600 /*
601 * Increment the head count to point next
602 * descriptor for next time
603 */
604 if (++ring->head == ring->slots)
605 ring->head = 0;
606
607 /* Copy prepared sw descriptor data to hw descriptor */
608 memcpy(desc_hw, &desc_sw->desc1, sizeof(*desc_hw));
609
610 /*
611 * Check if we have prepared 64B descriptor,
612 * in this case we need one more hw descriptor
613 */
614 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) {
615 desc_hw = &ring->desc_hw[ring->head];
616
617 if (++ring->head == ring->slots)
618 ring->head = 0;
619
620 memcpy(desc_hw, &desc_sw->desc2, sizeof(*desc_hw));
621 }
622
623 /* Increment the pending transaction count */
624 chan->pending += ((desc_sw->flags &
625 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
626
627 /* Notify the hw that we have descriptor ready for execution */
628 iowrite32((desc_sw->flags & XGENE_DMA_FLAG_64B_DESC) ?
629 2 : 1, ring->cmd);
630}
631
632/**
633 * xgene_chan_xfer_ld_pending - push any pending transactions to hw
634 * @chan : X-Gene DMA channel
635 *
636 * LOCKING: must hold chan->lock
637 */
638static void xgene_chan_xfer_ld_pending(struct xgene_dma_chan *chan)
639{
640 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
641
642 /*
643 * If the list of pending descriptors is empty, then we
644 * don't need to do any work at all
645 */
646 if (list_empty(&chan->ld_pending)) {
647 chan_dbg(chan, "No pending LDs\n");
648 return;
649 }
650
651 /*
652 * Move elements from the queue of pending transactions onto the list
653 * of running transactions and push it to hw for further executions
654 */
655 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_pending, node) {
656 /*
657 * Check if have pushed max number of transactions to hw
658 * as capable, so let's stop here and will push remaining
659 * elements from pening ld queue after completing some
660 * descriptors that we have already pushed
661 */
662 if (chan->pending >= chan->max_outstanding)
663 return;
664
665 xgene_chan_xfer_request(chan, desc_sw);
666
667 /*
668 * Delete this element from ld pending queue and append it to
669 * ld running queue
670 */
671 list_move_tail(&desc_sw->node, &chan->ld_running);
672 }
673}
674
675/**
676 * xgene_dma_cleanup_descriptors - cleanup link descriptors which are completed
677 * and move them to ld_completed to free until flag 'ack' is set
678 * @chan: X-Gene DMA channel
679 *
680 * This function is used on descriptors which have been executed by the DMA
681 * controller. It will run any callbacks, submit any dependencies, then
682 * free these descriptors if flag 'ack' is set.
683 */
684static void xgene_dma_cleanup_descriptors(struct xgene_dma_chan *chan)
685{
686 struct xgene_dma_ring *ring = &chan->rx_ring;
687 struct xgene_dma_desc_sw *desc_sw, *_desc_sw;
688 struct xgene_dma_desc_hw *desc_hw;
689 struct list_head ld_completed;
690 u8 status;
691
692 INIT_LIST_HEAD(&ld_completed);
693
694 spin_lock(&chan->lock);
695
696 /* Clean already completed and acked descriptors */
697 xgene_dma_clean_completed_descriptor(chan);
698
699 /* Move all completed descriptors to ld completed queue, in order */
700 list_for_each_entry_safe(desc_sw, _desc_sw, &chan->ld_running, node) {
701 /* Get subsequent hw descriptor from DMA rx ring */
702 desc_hw = &ring->desc_hw[ring->head];
703
704 /* Check if this descriptor has been completed */
705 if (unlikely(le64_to_cpu(desc_hw->m0) ==
706 XGENE_DMA_DESC_EMPTY_SIGNATURE))
707 break;
708
709 if (++ring->head == ring->slots)
710 ring->head = 0;
711
712 /* Check if we have any error with DMA transactions */
713 status = XGENE_DMA_DESC_STATUS(
714 XGENE_DMA_DESC_ELERR_RD(le64_to_cpu(
715 desc_hw->m0)),
716 XGENE_DMA_DESC_LERR_RD(le64_to_cpu(
717 desc_hw->m0)));
718 if (status) {
719 /* Print the DMA error type */
720 chan_err(chan, "%s\n", xgene_dma_desc_err[status]);
721
722 /*
723 * We have DMA transactions error here. Dump DMA Tx
724 * and Rx descriptors for this request */
725 XGENE_DMA_DESC_DUMP(&desc_sw->desc1,
726 "X-Gene DMA TX DESC1: ");
727
728 if (desc_sw->flags & XGENE_DMA_FLAG_64B_DESC)
729 XGENE_DMA_DESC_DUMP(&desc_sw->desc2,
730 "X-Gene DMA TX DESC2: ");
731
732 XGENE_DMA_DESC_DUMP(desc_hw,
733 "X-Gene DMA RX ERR DESC: ");
734 }
735
736 /* Notify the hw about this completed descriptor */
737 iowrite32(-1, ring->cmd);
738
739 /* Mark this hw descriptor as processed */
740 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
741
742 /*
743 * Decrement the pending transaction count
744 * as we have processed one
745 */
746 chan->pending -= ((desc_sw->flags &
747 XGENE_DMA_FLAG_64B_DESC) ? 2 : 1);
748
749 /*
750 * Delete this node from ld running queue and append it to
751 * ld completed queue for further processing
752 */
753 list_move_tail(&desc_sw->node, &ld_completed);
754 }
755
756 /*
757 * Start any pending transactions automatically
758 * In the ideal case, we keep the DMA controller busy while we go
759 * ahead and free the descriptors below.
760 */
761 xgene_chan_xfer_ld_pending(chan);
762
763 spin_unlock(&chan->lock);
764
765 /* Run the callback for each descriptor, in order */
766 list_for_each_entry_safe(desc_sw, _desc_sw, &ld_completed, node) {
767 xgene_dma_run_tx_complete_actions(chan, desc_sw);
768 xgene_dma_clean_running_descriptor(chan, desc_sw);
769 }
770}
771
772static int xgene_dma_alloc_chan_resources(struct dma_chan *dchan)
773{
774 struct xgene_dma_chan *chan = to_dma_chan(dchan);
775
776 /* Has this channel already been allocated? */
777 if (chan->desc_pool)
778 return 1;
779
780 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
781 sizeof(struct xgene_dma_desc_sw),
782 0, 0);
783 if (!chan->desc_pool) {
784 chan_err(chan, "Failed to allocate descriptor pool\n");
785 return -ENOMEM;
786 }
787
788 chan_dbg(chan, "Allocate descriptor pool\n");
789
790 return 1;
791}
792
793/**
794 * xgene_dma_free_desc_list - Free all descriptors in a queue
795 * @chan: X-Gene DMA channel
796 * @list: the list to free
797 *
798 * LOCKING: must hold chan->lock
799 */
800static void xgene_dma_free_desc_list(struct xgene_dma_chan *chan,
801 struct list_head *list)
802{
803 struct xgene_dma_desc_sw *desc, *_desc;
804
805 list_for_each_entry_safe(desc, _desc, list, node)
806 xgene_dma_clean_descriptor(chan, desc);
807}
808
809static void xgene_dma_free_chan_resources(struct dma_chan *dchan)
810{
811 struct xgene_dma_chan *chan = to_dma_chan(dchan);
812
813 chan_dbg(chan, "Free all resources\n");
814
815 if (!chan->desc_pool)
816 return;
817
818 /* Process all running descriptor */
819 xgene_dma_cleanup_descriptors(chan);
820
821 spin_lock_bh(&chan->lock);
822
823 /* Clean all link descriptor queues */
824 xgene_dma_free_desc_list(chan, &chan->ld_pending);
825 xgene_dma_free_desc_list(chan, &chan->ld_running);
826 xgene_dma_free_desc_list(chan, &chan->ld_completed);
827
828 spin_unlock_bh(&chan->lock);
829
830 /* Delete this channel DMA pool */
831 dma_pool_destroy(chan->desc_pool);
832 chan->desc_pool = NULL;
833}
834
835static struct dma_async_tx_descriptor *xgene_dma_prep_xor(
836 struct dma_chan *dchan, dma_addr_t dst, dma_addr_t *src,
837 u32 src_cnt, size_t len, unsigned long flags)
838{
839 struct xgene_dma_desc_sw *first = NULL, *new;
840 struct xgene_dma_chan *chan;
841 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {
842 0x01, 0x01, 0x01, 0x01, 0x01};
843
844 if (unlikely(!dchan || !len))
845 return NULL;
846
847 chan = to_dma_chan(dchan);
848
849 do {
850 /* Allocate the link descriptor from DMA pool */
851 new = xgene_dma_alloc_descriptor(chan);
852 if (!new)
853 goto fail;
854
855 /* Prepare xor DMA descriptor */
856 xgene_dma_prep_xor_desc(chan, new, &dst, src,
857 src_cnt, &len, multi);
858
859 if (!first)
860 first = new;
861
862 new->tx.cookie = 0;
863 async_tx_ack(&new->tx);
864
865 /* Insert the link descriptor to the LD ring */
866 list_add_tail(&new->node, &first->tx_list);
867 } while (len);
868
869 new->tx.flags = flags; /* client is in control of this ack */
870 new->tx.cookie = -EBUSY;
871 list_splice(&first->tx_list, &new->tx_list);
872
873 return &new->tx;
874
875fail:
876 if (!first)
877 return NULL;
878
879 xgene_dma_free_desc_list(chan, &first->tx_list);
880 return NULL;
881}
882
883static struct dma_async_tx_descriptor *xgene_dma_prep_pq(
884 struct dma_chan *dchan, dma_addr_t *dst, dma_addr_t *src,
885 u32 src_cnt, const u8 *scf, size_t len, unsigned long flags)
886{
887 struct xgene_dma_desc_sw *first = NULL, *new;
888 struct xgene_dma_chan *chan;
889 size_t _len = len;
890 dma_addr_t _src[XGENE_DMA_MAX_XOR_SRC];
891 static u8 multi[XGENE_DMA_MAX_XOR_SRC] = {0x01, 0x01, 0x01, 0x01, 0x01};
892
893 if (unlikely(!dchan || !len))
894 return NULL;
895
896 chan = to_dma_chan(dchan);
897
898 /*
899 * Save source addresses on local variable, may be we have to
900 * prepare two descriptor to generate P and Q if both enabled
901 * in the flags by client
902 */
903 memcpy(_src, src, sizeof(*src) * src_cnt);
904
905 if (flags & DMA_PREP_PQ_DISABLE_P)
906 len = 0;
907
908 if (flags & DMA_PREP_PQ_DISABLE_Q)
909 _len = 0;
910
911 do {
912 /* Allocate the link descriptor from DMA pool */
913 new = xgene_dma_alloc_descriptor(chan);
914 if (!new)
915 goto fail;
916
917 if (!first)
918 first = new;
919
920 new->tx.cookie = 0;
921 async_tx_ack(&new->tx);
922
923 /* Insert the link descriptor to the LD ring */
924 list_add_tail(&new->node, &first->tx_list);
925
926 /*
927 * Prepare DMA descriptor to generate P,
928 * if DMA_PREP_PQ_DISABLE_P flag is not set
929 */
930 if (len) {
931 xgene_dma_prep_xor_desc(chan, new, &dst[0], src,
932 src_cnt, &len, multi);
933 continue;
934 }
935
936 /*
937 * Prepare DMA descriptor to generate Q,
938 * if DMA_PREP_PQ_DISABLE_Q flag is not set
939 */
940 if (_len) {
941 xgene_dma_prep_xor_desc(chan, new, &dst[1], _src,
942 src_cnt, &_len, scf);
943 }
944 } while (len || _len);
945
946 new->tx.flags = flags; /* client is in control of this ack */
947 new->tx.cookie = -EBUSY;
948 list_splice(&first->tx_list, &new->tx_list);
949
950 return &new->tx;
951
952fail:
953 if (!first)
954 return NULL;
955
956 xgene_dma_free_desc_list(chan, &first->tx_list);
957 return NULL;
958}
959
960static void xgene_dma_issue_pending(struct dma_chan *dchan)
961{
962 struct xgene_dma_chan *chan = to_dma_chan(dchan);
963
964 spin_lock_bh(&chan->lock);
965 xgene_chan_xfer_ld_pending(chan);
966 spin_unlock_bh(&chan->lock);
967}
968
969static enum dma_status xgene_dma_tx_status(struct dma_chan *dchan,
970 dma_cookie_t cookie,
971 struct dma_tx_state *txstate)
972{
973 return dma_cookie_status(dchan, cookie, txstate);
974}
975
976static void xgene_dma_tasklet_cb(unsigned long data)
977{
978 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)data;
979
980 /* Run all cleanup for descriptors which have been completed */
981 xgene_dma_cleanup_descriptors(chan);
982
983 /* Re-enable DMA channel IRQ */
984 enable_irq(chan->rx_irq);
985}
986
987static irqreturn_t xgene_dma_chan_ring_isr(int irq, void *id)
988{
989 struct xgene_dma_chan *chan = (struct xgene_dma_chan *)id;
990
991 BUG_ON(!chan);
992
993 /*
994 * Disable DMA channel IRQ until we process completed
995 * descriptors
996 */
997 disable_irq_nosync(chan->rx_irq);
998
999 /*
1000 * Schedule the tasklet to handle all cleanup of the current
1001 * transaction. It will start a new transaction if there is
1002 * one pending.
1003 */
1004 tasklet_schedule(&chan->tasklet);
1005
1006 return IRQ_HANDLED;
1007}
1008
1009static irqreturn_t xgene_dma_err_isr(int irq, void *id)
1010{
1011 struct xgene_dma *pdma = (struct xgene_dma *)id;
1012 unsigned long int_mask;
1013 u32 val, i;
1014
1015 val = ioread32(pdma->csr_dma + XGENE_DMA_INT);
1016
1017 /* Clear DMA interrupts */
1018 iowrite32(val, pdma->csr_dma + XGENE_DMA_INT);
1019
1020 /* Print DMA error info */
1021 int_mask = val >> XGENE_DMA_INT_MASK_SHIFT;
1022 for_each_set_bit(i, &int_mask, ARRAY_SIZE(xgene_dma_err))
1023 dev_err(pdma->dev,
1024 "Interrupt status 0x%08X %s\n", val, xgene_dma_err[i]);
1025
1026 return IRQ_HANDLED;
1027}
1028
1029static void xgene_dma_wr_ring_state(struct xgene_dma_ring *ring)
1030{
1031 int i;
1032
1033 iowrite32(ring->num, ring->pdma->csr_ring + XGENE_DMA_RING_STATE);
1034
1035 for (i = 0; i < XGENE_DMA_RING_NUM_CONFIG; i++)
1036 iowrite32(ring->state[i], ring->pdma->csr_ring +
1037 XGENE_DMA_RING_STATE_WR_BASE + (i * 4));
1038}
1039
1040static void xgene_dma_clr_ring_state(struct xgene_dma_ring *ring)
1041{
1042 memset(ring->state, 0, sizeof(u32) * XGENE_DMA_RING_NUM_CONFIG);
1043 xgene_dma_wr_ring_state(ring);
1044}
1045
1046static void xgene_dma_setup_ring(struct xgene_dma_ring *ring)
1047{
1048 void *ring_cfg = ring->state;
1049 u64 addr = ring->desc_paddr;
1050 u32 i, val;
1051
1052 ring->slots = ring->size / XGENE_DMA_RING_WQ_DESC_SIZE;
1053
1054 /* Clear DMA ring state */
1055 xgene_dma_clr_ring_state(ring);
1056
1057 /* Set DMA ring type */
1058 XGENE_DMA_RING_TYPE_SET(ring_cfg, XGENE_DMA_RING_TYPE_REGULAR);
1059
1060 if (ring->owner == XGENE_DMA_RING_OWNER_DMA) {
1061 /* Set recombination buffer and timeout */
1062 XGENE_DMA_RING_RECOMBBUF_SET(ring_cfg);
1063 XGENE_DMA_RING_RECOMTIMEOUTL_SET(ring_cfg);
1064 XGENE_DMA_RING_RECOMTIMEOUTH_SET(ring_cfg);
1065 }
1066
1067 /* Initialize DMA ring state */
1068 XGENE_DMA_RING_SELTHRSH_SET(ring_cfg);
1069 XGENE_DMA_RING_ACCEPTLERR_SET(ring_cfg);
1070 XGENE_DMA_RING_COHERENT_SET(ring_cfg);
1071 XGENE_DMA_RING_ADDRL_SET(ring_cfg, addr);
1072 XGENE_DMA_RING_ADDRH_SET(ring_cfg, addr);
1073 XGENE_DMA_RING_SIZE_SET(ring_cfg, ring->cfgsize);
1074
1075 /* Write DMA ring configurations */
1076 xgene_dma_wr_ring_state(ring);
1077
1078 /* Set DMA ring id */
1079 iowrite32(XGENE_DMA_RING_ID_SETUP(ring->id),
1080 ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1081
1082 /* Set DMA ring buffer */
1083 iowrite32(XGENE_DMA_RING_ID_BUF_SETUP(ring->num),
1084 ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1085
1086 if (ring->owner != XGENE_DMA_RING_OWNER_CPU)
1087 return;
1088
1089 /* Set empty signature to DMA Rx ring descriptors */
1090 for (i = 0; i < ring->slots; i++) {
1091 struct xgene_dma_desc_hw *desc;
1092
1093 desc = &ring->desc_hw[i];
1094 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE);
1095 }
1096
1097 /* Enable DMA Rx ring interrupt */
1098 val = ioread32(ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1099 XGENE_DMA_RING_NE_INT_MODE_SET(val, ring->buf_num);
1100 iowrite32(val, ring->pdma->csr_ring + XGENE_DMA_RING_NE_INT_MODE);
1101}
1102
1103static void xgene_dma_clear_ring(struct xgene_dma_ring *ring)
1104{
1105 u32 ring_id, val;
1106
1107 if (ring->owner == XGENE_DMA_RING_OWNER_CPU) {
1108 /* Disable DMA Rx ring interrupt */
1109 val = ioread32(ring->pdma->csr_ring +
1110 XGENE_DMA_RING_NE_INT_MODE);
1111 XGENE_DMA_RING_NE_INT_MODE_RESET(val, ring->buf_num);
1112 iowrite32(val, ring->pdma->csr_ring +
1113 XGENE_DMA_RING_NE_INT_MODE);
1114 }
1115
1116 /* Clear DMA ring state */
1117 ring_id = XGENE_DMA_RING_ID_SETUP(ring->id);
1118 iowrite32(ring_id, ring->pdma->csr_ring + XGENE_DMA_RING_ID);
1119
1120 iowrite32(0, ring->pdma->csr_ring + XGENE_DMA_RING_ID_BUF);
1121 xgene_dma_clr_ring_state(ring);
1122}
1123
1124static void xgene_dma_set_ring_cmd(struct xgene_dma_ring *ring)
1125{
1126 ring->cmd_base = ring->pdma->csr_ring_cmd +
1127 XGENE_DMA_RING_CMD_BASE_OFFSET((ring->num -
1128 XGENE_DMA_RING_NUM));
1129
1130 ring->cmd = ring->cmd_base + XGENE_DMA_RING_CMD_OFFSET;
1131}
1132
1133static int xgene_dma_get_ring_size(struct xgene_dma_chan *chan,
1134 enum xgene_dma_ring_cfgsize cfgsize)
1135{
1136 int size;
1137
1138 switch (cfgsize) {
1139 case XGENE_DMA_RING_CFG_SIZE_512B:
1140 size = 0x200;
1141 break;
1142 case XGENE_DMA_RING_CFG_SIZE_2KB:
1143 size = 0x800;
1144 break;
1145 case XGENE_DMA_RING_CFG_SIZE_16KB:
1146 size = 0x4000;
1147 break;
1148 case XGENE_DMA_RING_CFG_SIZE_64KB:
1149 size = 0x10000;
1150 break;
1151 case XGENE_DMA_RING_CFG_SIZE_512KB:
1152 size = 0x80000;
1153 break;
1154 default:
1155 chan_err(chan, "Unsupported cfg ring size %d\n", cfgsize);
1156 return -EINVAL;
1157 }
1158
1159 return size;
1160}
1161
1162static void xgene_dma_delete_ring_one(struct xgene_dma_ring *ring)
1163{
1164 /* Clear DMA ring configurations */
1165 xgene_dma_clear_ring(ring);
1166
1167 /* De-allocate DMA ring descriptor */
1168 if (ring->desc_vaddr) {
1169 dma_free_coherent(ring->pdma->dev, ring->size,
1170 ring->desc_vaddr, ring->desc_paddr);
1171 ring->desc_vaddr = NULL;
1172 }
1173}
1174
1175static void xgene_dma_delete_chan_rings(struct xgene_dma_chan *chan)
1176{
1177 xgene_dma_delete_ring_one(&chan->rx_ring);
1178 xgene_dma_delete_ring_one(&chan->tx_ring);
1179}
1180
1181static int xgene_dma_create_ring_one(struct xgene_dma_chan *chan,
1182 struct xgene_dma_ring *ring,
1183 enum xgene_dma_ring_cfgsize cfgsize)
1184{
1185 int ret;
1186
1187 /* Setup DMA ring descriptor variables */
1188 ring->pdma = chan->pdma;
1189 ring->cfgsize = cfgsize;
1190 ring->num = chan->pdma->ring_num++;
1191 ring->id = XGENE_DMA_RING_ID_GET(ring->owner, ring->buf_num);
1192
1193 ret = xgene_dma_get_ring_size(chan, cfgsize);
1194 if (ret <= 0)
1195 return ret;
1196 ring->size = ret;
1197
1198 /* Allocate memory for DMA ring descriptor */
1199 ring->desc_vaddr = dma_alloc_coherent(chan->dev, ring->size,
1200 &ring->desc_paddr, GFP_KERNEL);
1201 if (!ring->desc_vaddr) {
1202 chan_err(chan, "Failed to allocate ring desc\n");
1203 return -ENOMEM;
1204 }
1205
1206 /* Configure and enable DMA ring */
1207 xgene_dma_set_ring_cmd(ring);
1208 xgene_dma_setup_ring(ring);
1209
1210 return 0;
1211}
1212
1213static int xgene_dma_create_chan_rings(struct xgene_dma_chan *chan)
1214{
1215 struct xgene_dma_ring *rx_ring = &chan->rx_ring;
1216 struct xgene_dma_ring *tx_ring = &chan->tx_ring;
1217 int ret;
1218
1219 /* Create DMA Rx ring descriptor */
1220 rx_ring->owner = XGENE_DMA_RING_OWNER_CPU;
1221 rx_ring->buf_num = XGENE_DMA_CPU_BUFNUM + chan->id;
1222
1223 ret = xgene_dma_create_ring_one(chan, rx_ring,
1224 XGENE_DMA_RING_CFG_SIZE_64KB);
1225 if (ret)
1226 return ret;
1227
1228 chan_dbg(chan, "Rx ring id 0x%X num %d desc 0x%p\n",
1229 rx_ring->id, rx_ring->num, rx_ring->desc_vaddr);
1230
1231 /* Create DMA Tx ring descriptor */
1232 tx_ring->owner = XGENE_DMA_RING_OWNER_DMA;
1233 tx_ring->buf_num = XGENE_DMA_BUFNUM + chan->id;
1234
1235 ret = xgene_dma_create_ring_one(chan, tx_ring,
1236 XGENE_DMA_RING_CFG_SIZE_64KB);
1237 if (ret) {
1238 xgene_dma_delete_ring_one(rx_ring);
1239 return ret;
1240 }
1241
1242 tx_ring->dst_ring_num = XGENE_DMA_RING_DST_ID(rx_ring->num);
1243
1244 chan_dbg(chan,
1245 "Tx ring id 0x%X num %d desc 0x%p\n",
1246 tx_ring->id, tx_ring->num, tx_ring->desc_vaddr);
1247
1248 /* Set the max outstanding request possible to this channel */
1249 chan->max_outstanding = tx_ring->slots;
1250
1251 return ret;
1252}
1253
1254static int xgene_dma_init_rings(struct xgene_dma *pdma)
1255{
1256 int ret, i, j;
1257
1258 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1259 ret = xgene_dma_create_chan_rings(&pdma->chan[i]);
1260 if (ret) {
1261 for (j = 0; j < i; j++)
1262 xgene_dma_delete_chan_rings(&pdma->chan[j]);
1263 return ret;
1264 }
1265 }
1266
1267 return ret;
1268}
1269
1270static void xgene_dma_enable(struct xgene_dma *pdma)
1271{
1272 u32 val;
1273
1274 /* Configure and enable DMA engine */
1275 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1276 XGENE_DMA_CH_SETUP(val);
1277 XGENE_DMA_ENABLE(val);
1278 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1279}
1280
1281static void xgene_dma_disable(struct xgene_dma *pdma)
1282{
1283 u32 val;
1284
1285 val = ioread32(pdma->csr_dma + XGENE_DMA_GCR);
1286 XGENE_DMA_DISABLE(val);
1287 iowrite32(val, pdma->csr_dma + XGENE_DMA_GCR);
1288}
1289
1290static void xgene_dma_mask_interrupts(struct xgene_dma *pdma)
1291{
1292 /*
1293 * Mask DMA ring overflow, underflow and
1294 * AXI write/read error interrupts
1295 */
1296 iowrite32(XGENE_DMA_INT_ALL_MASK,
1297 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1298 iowrite32(XGENE_DMA_INT_ALL_MASK,
1299 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1300 iowrite32(XGENE_DMA_INT_ALL_MASK,
1301 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1302 iowrite32(XGENE_DMA_INT_ALL_MASK,
1303 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1304 iowrite32(XGENE_DMA_INT_ALL_MASK,
1305 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1306
1307 /* Mask DMA error interrupts */
1308 iowrite32(XGENE_DMA_INT_ALL_MASK, pdma->csr_dma + XGENE_DMA_INT_MASK);
1309}
1310
1311static void xgene_dma_unmask_interrupts(struct xgene_dma *pdma)
1312{
1313 /*
1314 * Unmask DMA ring overflow, underflow and
1315 * AXI write/read error interrupts
1316 */
1317 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1318 pdma->csr_dma + XGENE_DMA_RING_INT0_MASK);
1319 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1320 pdma->csr_dma + XGENE_DMA_RING_INT1_MASK);
1321 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1322 pdma->csr_dma + XGENE_DMA_RING_INT2_MASK);
1323 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1324 pdma->csr_dma + XGENE_DMA_RING_INT3_MASK);
1325 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1326 pdma->csr_dma + XGENE_DMA_RING_INT4_MASK);
1327
1328 /* Unmask DMA error interrupts */
1329 iowrite32(XGENE_DMA_INT_ALL_UNMASK,
1330 pdma->csr_dma + XGENE_DMA_INT_MASK);
1331}
1332
1333static void xgene_dma_init_hw(struct xgene_dma *pdma)
1334{
1335 u32 val;
1336
1337 /* Associate DMA ring to corresponding ring HW */
1338 iowrite32(XGENE_DMA_ASSOC_RING_MNGR1,
1339 pdma->csr_dma + XGENE_DMA_CFG_RING_WQ_ASSOC);
1340
1341 /* Configure RAID6 polynomial control setting */
1342 if (is_pq_enabled(pdma))
1343 iowrite32(XGENE_DMA_RAID6_MULTI_CTRL(0x1D),
1344 pdma->csr_dma + XGENE_DMA_RAID6_CONT);
1345 else
1346 dev_info(pdma->dev, "PQ is disabled in HW\n");
1347
1348 xgene_dma_enable(pdma);
1349 xgene_dma_unmask_interrupts(pdma);
1350
1351 /* Get DMA id and version info */
1352 val = ioread32(pdma->csr_dma + XGENE_DMA_IPBRR);
1353
1354 /* DMA device info */
1355 dev_info(pdma->dev,
1356 "X-Gene DMA v%d.%02d.%02d driver registered %d channels",
1357 XGENE_DMA_REV_NO_RD(val), XGENE_DMA_BUS_ID_RD(val),
1358 XGENE_DMA_DEV_ID_RD(val), XGENE_DMA_MAX_CHANNEL);
1359}
1360
1361static int xgene_dma_init_ring_mngr(struct xgene_dma *pdma)
1362{
1363 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_CLKEN) &&
1364 (!ioread32(pdma->csr_ring + XGENE_DMA_RING_SRST)))
1365 return 0;
1366
1367 iowrite32(0x3, pdma->csr_ring + XGENE_DMA_RING_CLKEN);
1368 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_SRST);
1369
1370 /* Bring up memory */
1371 iowrite32(0x0, pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1372
1373 /* Force a barrier */
1374 ioread32(pdma->csr_ring + XGENE_DMA_RING_MEM_RAM_SHUTDOWN);
1375
1376 /* reset may take up to 1ms */
1377 usleep_range(1000, 1100);
1378
1379 if (ioread32(pdma->csr_ring + XGENE_DMA_RING_BLK_MEM_RDY)
1380 != XGENE_DMA_RING_BLK_MEM_RDY_VAL) {
1381 dev_err(pdma->dev,
1382 "Failed to release ring mngr memory from shutdown\n");
1383 return -ENODEV;
1384 }
1385
1386 /* program threshold set 1 and all hysteresis */
1387 iowrite32(XGENE_DMA_RING_THRESLD0_SET1_VAL,
1388 pdma->csr_ring + XGENE_DMA_RING_THRESLD0_SET1);
1389 iowrite32(XGENE_DMA_RING_THRESLD1_SET1_VAL,
1390 pdma->csr_ring + XGENE_DMA_RING_THRESLD1_SET1);
1391 iowrite32(XGENE_DMA_RING_HYSTERESIS_VAL,
1392 pdma->csr_ring + XGENE_DMA_RING_HYSTERESIS);
1393
1394 /* Enable QPcore and assign error queue */
1395 iowrite32(XGENE_DMA_RING_ENABLE,
1396 pdma->csr_ring + XGENE_DMA_RING_CONFIG);
1397
1398 return 0;
1399}
1400
1401static int xgene_dma_init_mem(struct xgene_dma *pdma)
1402{
1403 int ret;
1404
1405 ret = xgene_dma_init_ring_mngr(pdma);
1406 if (ret)
1407 return ret;
1408
1409 /* Bring up memory */
1410 iowrite32(0x0, pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1411
1412 /* Force a barrier */
1413 ioread32(pdma->csr_dma + XGENE_DMA_MEM_RAM_SHUTDOWN);
1414
1415 /* reset may take up to 1ms */
1416 usleep_range(1000, 1100);
1417
1418 if (ioread32(pdma->csr_dma + XGENE_DMA_BLK_MEM_RDY)
1419 != XGENE_DMA_BLK_MEM_RDY_VAL) {
1420 dev_err(pdma->dev,
1421 "Failed to release DMA memory from shutdown\n");
1422 return -ENODEV;
1423 }
1424
1425 return 0;
1426}
1427
1428static int xgene_dma_request_irqs(struct xgene_dma *pdma)
1429{
1430 struct xgene_dma_chan *chan;
1431 int ret, i, j;
1432
1433 /* Register DMA error irq */
1434 ret = devm_request_irq(pdma->dev, pdma->err_irq, xgene_dma_err_isr,
1435 0, "dma_error", pdma);
1436 if (ret) {
1437 dev_err(pdma->dev,
1438 "Failed to register error IRQ %d\n", pdma->err_irq);
1439 return ret;
1440 }
1441
1442 /* Register DMA channel rx irq */
1443 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1444 chan = &pdma->chan[i];
1445 irq_set_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
1446 ret = devm_request_irq(chan->dev, chan->rx_irq,
1447 xgene_dma_chan_ring_isr,
1448 0, chan->name, chan);
1449 if (ret) {
1450 chan_err(chan, "Failed to register Rx IRQ %d\n",
1451 chan->rx_irq);
1452 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1453
1454 for (j = 0; j < i; j++) {
1455 chan = &pdma->chan[i];
1456 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
1457 devm_free_irq(chan->dev, chan->rx_irq, chan);
1458 }
1459
1460 return ret;
1461 }
1462 }
1463
1464 return 0;
1465}
1466
1467static void xgene_dma_free_irqs(struct xgene_dma *pdma)
1468{
1469 struct xgene_dma_chan *chan;
1470 int i;
1471
1472 /* Free DMA device error irq */
1473 devm_free_irq(pdma->dev, pdma->err_irq, pdma);
1474
1475 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1476 chan = &pdma->chan[i];
1477 irq_clear_status_flags(chan->rx_irq, IRQ_DISABLE_UNLAZY);
1478 devm_free_irq(chan->dev, chan->rx_irq, chan);
1479 }
1480}
1481
1482static void xgene_dma_set_caps(struct xgene_dma_chan *chan,
1483 struct dma_device *dma_dev)
1484{
1485 /* Initialize DMA device capability mask */
1486 dma_cap_zero(dma_dev->cap_mask);
1487
1488 /* Set DMA device capability */
1489
1490 /* Basically here, the X-Gene SoC DMA engine channel 0 supports XOR
1491 * and channel 1 supports XOR, PQ both. First thing here is we have
1492 * mechanism in hw to enable/disable PQ/XOR supports on channel 1,
1493 * we can make sure this by reading SoC Efuse register.
1494 * Second thing, we have hw errata that if we run channel 0 and
1495 * channel 1 simultaneously with executing XOR and PQ request,
1496 * suddenly DMA engine hangs, So here we enable XOR on channel 0 only
1497 * if XOR and PQ supports on channel 1 is disabled.
1498 */
1499 if ((chan->id == XGENE_DMA_PQ_CHANNEL) &&
1500 is_pq_enabled(chan->pdma)) {
1501 dma_cap_set(DMA_PQ, dma_dev->cap_mask);
1502 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1503 } else if ((chan->id == XGENE_DMA_XOR_CHANNEL) &&
1504 !is_pq_enabled(chan->pdma)) {
1505 dma_cap_set(DMA_XOR, dma_dev->cap_mask);
1506 }
1507
1508 /* Set base and prep routines */
1509 dma_dev->dev = chan->dev;
1510 dma_dev->device_alloc_chan_resources = xgene_dma_alloc_chan_resources;
1511 dma_dev->device_free_chan_resources = xgene_dma_free_chan_resources;
1512 dma_dev->device_issue_pending = xgene_dma_issue_pending;
1513 dma_dev->device_tx_status = xgene_dma_tx_status;
1514
1515 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1516 dma_dev->device_prep_dma_xor = xgene_dma_prep_xor;
1517 dma_dev->max_xor = XGENE_DMA_MAX_XOR_SRC;
1518 dma_dev->xor_align = DMAENGINE_ALIGN_64_BYTES;
1519 }
1520
1521 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1522 dma_dev->device_prep_dma_pq = xgene_dma_prep_pq;
1523 dma_dev->max_pq = XGENE_DMA_MAX_XOR_SRC;
1524 dma_dev->pq_align = DMAENGINE_ALIGN_64_BYTES;
1525 }
1526}
1527
1528static int xgene_dma_async_register(struct xgene_dma *pdma, int id)
1529{
1530 struct xgene_dma_chan *chan = &pdma->chan[id];
1531 struct dma_device *dma_dev = &pdma->dma_dev[id];
1532 int ret;
1533
1534 chan->dma_chan.device = dma_dev;
1535
1536 spin_lock_init(&chan->lock);
1537 INIT_LIST_HEAD(&chan->ld_pending);
1538 INIT_LIST_HEAD(&chan->ld_running);
1539 INIT_LIST_HEAD(&chan->ld_completed);
1540 tasklet_init(&chan->tasklet, xgene_dma_tasklet_cb,
1541 (unsigned long)chan);
1542
1543 chan->pending = 0;
1544 chan->desc_pool = NULL;
1545 dma_cookie_init(&chan->dma_chan);
1546
1547 /* Setup dma device capabilities and prep routines */
1548 xgene_dma_set_caps(chan, dma_dev);
1549
1550 /* Initialize DMA device list head */
1551 INIT_LIST_HEAD(&dma_dev->channels);
1552 list_add_tail(&chan->dma_chan.device_node, &dma_dev->channels);
1553
1554 /* Register with Linux async DMA framework*/
1555 ret = dma_async_device_register(dma_dev);
1556 if (ret) {
1557 chan_err(chan, "Failed to register async device %d", ret);
1558 tasklet_kill(&chan->tasklet);
1559
1560 return ret;
1561 }
1562
1563 /* DMA capability info */
1564 dev_info(pdma->dev,
1565 "%s: CAPABILITY ( %s%s)\n", dma_chan_name(&chan->dma_chan),
1566 dma_has_cap(DMA_XOR, dma_dev->cap_mask) ? "XOR " : "",
1567 dma_has_cap(DMA_PQ, dma_dev->cap_mask) ? "PQ " : "");
1568
1569 return 0;
1570}
1571
1572static int xgene_dma_init_async(struct xgene_dma *pdma)
1573{
1574 int ret, i, j;
1575
1576 for (i = 0; i < XGENE_DMA_MAX_CHANNEL ; i++) {
1577 ret = xgene_dma_async_register(pdma, i);
1578 if (ret) {
1579 for (j = 0; j < i; j++) {
1580 dma_async_device_unregister(&pdma->dma_dev[j]);
1581 tasklet_kill(&pdma->chan[j].tasklet);
1582 }
1583
1584 return ret;
1585 }
1586 }
1587
1588 return ret;
1589}
1590
1591static void xgene_dma_async_unregister(struct xgene_dma *pdma)
1592{
1593 int i;
1594
1595 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1596 dma_async_device_unregister(&pdma->dma_dev[i]);
1597}
1598
1599static void xgene_dma_init_channels(struct xgene_dma *pdma)
1600{
1601 struct xgene_dma_chan *chan;
1602 int i;
1603
1604 pdma->ring_num = XGENE_DMA_RING_NUM;
1605
1606 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1607 chan = &pdma->chan[i];
1608 chan->dev = pdma->dev;
1609 chan->pdma = pdma;
1610 chan->id = i;
1611 snprintf(chan->name, sizeof(chan->name), "dmachan%d", chan->id);
1612 }
1613}
1614
1615static int xgene_dma_get_resources(struct platform_device *pdev,
1616 struct xgene_dma *pdma)
1617{
1618 struct resource *res;
1619 int irq, i;
1620
1621 /* Get DMA csr region */
1622 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1623 if (!res) {
1624 dev_err(&pdev->dev, "Failed to get csr region\n");
1625 return -ENXIO;
1626 }
1627
1628 pdma->csr_dma = devm_ioremap(&pdev->dev, res->start,
1629 resource_size(res));
1630 if (!pdma->csr_dma) {
1631 dev_err(&pdev->dev, "Failed to ioremap csr region");
1632 return -ENOMEM;
1633 }
1634
1635 /* Get DMA ring csr region */
1636 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1637 if (!res) {
1638 dev_err(&pdev->dev, "Failed to get ring csr region\n");
1639 return -ENXIO;
1640 }
1641
1642 pdma->csr_ring = devm_ioremap(&pdev->dev, res->start,
1643 resource_size(res));
1644 if (!pdma->csr_ring) {
1645 dev_err(&pdev->dev, "Failed to ioremap ring csr region");
1646 return -ENOMEM;
1647 }
1648
1649 /* Get DMA ring cmd csr region */
1650 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1651 if (!res) {
1652 dev_err(&pdev->dev, "Failed to get ring cmd csr region\n");
1653 return -ENXIO;
1654 }
1655
1656 pdma->csr_ring_cmd = devm_ioremap(&pdev->dev, res->start,
1657 resource_size(res));
1658 if (!pdma->csr_ring_cmd) {
1659 dev_err(&pdev->dev, "Failed to ioremap ring cmd csr region");
1660 return -ENOMEM;
1661 }
1662
1663 pdma->csr_ring_cmd += XGENE_DMA_RING_CMD_SM_OFFSET;
1664
1665 /* Get efuse csr region */
1666 res = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1667 if (!res) {
1668 dev_err(&pdev->dev, "Failed to get efuse csr region\n");
1669 return -ENXIO;
1670 }
1671
1672 pdma->csr_efuse = devm_ioremap(&pdev->dev, res->start,
1673 resource_size(res));
1674 if (!pdma->csr_efuse) {
1675 dev_err(&pdev->dev, "Failed to ioremap efuse csr region");
1676 return -ENOMEM;
1677 }
1678
1679 /* Get DMA error interrupt */
1680 irq = platform_get_irq(pdev, 0);
1681 if (irq <= 0)
1682 return -ENXIO;
1683
1684 pdma->err_irq = irq;
1685
1686 /* Get DMA Rx ring descriptor interrupts for all DMA channels */
1687 for (i = 1; i <= XGENE_DMA_MAX_CHANNEL; i++) {
1688 irq = platform_get_irq(pdev, i);
1689 if (irq <= 0)
1690 return -ENXIO;
1691
1692 pdma->chan[i - 1].rx_irq = irq;
1693 }
1694
1695 return 0;
1696}
1697
1698static int xgene_dma_probe(struct platform_device *pdev)
1699{
1700 struct xgene_dma *pdma;
1701 int ret, i;
1702
1703 pdma = devm_kzalloc(&pdev->dev, sizeof(*pdma), GFP_KERNEL);
1704 if (!pdma)
1705 return -ENOMEM;
1706
1707 pdma->dev = &pdev->dev;
1708 platform_set_drvdata(pdev, pdma);
1709
1710 ret = xgene_dma_get_resources(pdev, pdma);
1711 if (ret)
1712 return ret;
1713
1714 pdma->clk = devm_clk_get(&pdev->dev, NULL);
1715 if (IS_ERR(pdma->clk) && !ACPI_COMPANION(&pdev->dev)) {
1716 dev_err(&pdev->dev, "Failed to get clk\n");
1717 return PTR_ERR(pdma->clk);
1718 }
1719
1720 /* Enable clk before accessing registers */
1721 if (!IS_ERR(pdma->clk)) {
1722 ret = clk_prepare_enable(pdma->clk);
1723 if (ret) {
1724 dev_err(&pdev->dev, "Failed to enable clk %d\n", ret);
1725 return ret;
1726 }
1727 }
1728
1729 /* Remove DMA RAM out of shutdown */
1730 ret = xgene_dma_init_mem(pdma);
1731 if (ret)
1732 goto err_clk_enable;
1733
1734 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(42));
1735 if (ret) {
1736 dev_err(&pdev->dev, "No usable DMA configuration\n");
1737 goto err_dma_mask;
1738 }
1739
1740 /* Initialize DMA channels software state */
1741 xgene_dma_init_channels(pdma);
1742
1743 /* Configue DMA rings */
1744 ret = xgene_dma_init_rings(pdma);
1745 if (ret)
1746 goto err_clk_enable;
1747
1748 ret = xgene_dma_request_irqs(pdma);
1749 if (ret)
1750 goto err_request_irq;
1751
1752 /* Configure and enable DMA engine */
1753 xgene_dma_init_hw(pdma);
1754
1755 /* Register DMA device with linux async framework */
1756 ret = xgene_dma_init_async(pdma);
1757 if (ret)
1758 goto err_async_init;
1759
1760 return 0;
1761
1762err_async_init:
1763 xgene_dma_free_irqs(pdma);
1764
1765err_request_irq:
1766 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++)
1767 xgene_dma_delete_chan_rings(&pdma->chan[i]);
1768
1769err_dma_mask:
1770err_clk_enable:
1771 if (!IS_ERR(pdma->clk))
1772 clk_disable_unprepare(pdma->clk);
1773
1774 return ret;
1775}
1776
1777static int xgene_dma_remove(struct platform_device *pdev)
1778{
1779 struct xgene_dma *pdma = platform_get_drvdata(pdev);
1780 struct xgene_dma_chan *chan;
1781 int i;
1782
1783 xgene_dma_async_unregister(pdma);
1784
1785 /* Mask interrupts and disable DMA engine */
1786 xgene_dma_mask_interrupts(pdma);
1787 xgene_dma_disable(pdma);
1788 xgene_dma_free_irqs(pdma);
1789
1790 for (i = 0; i < XGENE_DMA_MAX_CHANNEL; i++) {
1791 chan = &pdma->chan[i];
1792 tasklet_kill(&chan->tasklet);
1793 xgene_dma_delete_chan_rings(chan);
1794 }
1795
1796 if (!IS_ERR(pdma->clk))
1797 clk_disable_unprepare(pdma->clk);
1798
1799 return 0;
1800}
1801
1802#ifdef CONFIG_ACPI
1803static const struct acpi_device_id xgene_dma_acpi_match_ptr[] = {
1804 {"APMC0D43", 0},
1805 {},
1806};
1807MODULE_DEVICE_TABLE(acpi, xgene_dma_acpi_match_ptr);
1808#endif
1809
1810static const struct of_device_id xgene_dma_of_match_ptr[] = {
1811 {.compatible = "apm,xgene-storm-dma",},
1812 {},
1813};
1814MODULE_DEVICE_TABLE(of, xgene_dma_of_match_ptr);
1815
1816static struct platform_driver xgene_dma_driver = {
1817 .probe = xgene_dma_probe,
1818 .remove = xgene_dma_remove,
1819 .driver = {
1820 .name = "X-Gene-DMA",
1821 .of_match_table = xgene_dma_of_match_ptr,
1822 .acpi_match_table = ACPI_PTR(xgene_dma_acpi_match_ptr),
1823 },
1824};
1825
1826module_platform_driver(xgene_dma_driver);
1827
1828MODULE_DESCRIPTION("APM X-Gene SoC DMA driver");
1829MODULE_AUTHOR("Rameshwar Prasad Sahu <rsahu@apm.com>");
1830MODULE_AUTHOR("Loc Ho <lho@apm.com>");
1831MODULE_LICENSE("GPL");
1832MODULE_VERSION("1.0");