Loading...
Note: File does not exist in v6.8.
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * RocketPort device driver for Linux
4 *
5 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 *
7 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 */
9
10/*
11 * Kernel Synchronization:
12 *
13 * This driver has 2 kernel control paths - exception handlers (calls into the driver
14 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
15 * are not used.
16 *
17 * Critical data:
18 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
19 * serial port state information and the xmit_buf circular buffer. Protected by
20 * a per port spinlock.
21 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
22 * is data to be transmitted. Protected by atomic bit operations.
23 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
24 *
25 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
26 * simultaneous access to the same port by more than one process.
27 */
28
29/****** Defines ******/
30#define ROCKET_PARANOIA_CHECK
31#define ROCKET_DISABLE_SIMUSAGE
32
33#undef ROCKET_SOFT_FLOW
34#undef ROCKET_DEBUG_OPEN
35#undef ROCKET_DEBUG_INTR
36#undef ROCKET_DEBUG_WRITE
37#undef ROCKET_DEBUG_FLOW
38#undef ROCKET_DEBUG_THROTTLE
39#undef ROCKET_DEBUG_WAIT_UNTIL_SENT
40#undef ROCKET_DEBUG_RECEIVE
41#undef ROCKET_DEBUG_HANGUP
42#undef REV_PCI_ORDER
43#undef ROCKET_DEBUG_IO
44
45#define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
46
47/****** Kernel includes ******/
48
49#include <linux/module.h>
50#include <linux/errno.h>
51#include <linux/major.h>
52#include <linux/kernel.h>
53#include <linux/signal.h>
54#include <linux/slab.h>
55#include <linux/mm.h>
56#include <linux/sched.h>
57#include <linux/timer.h>
58#include <linux/interrupt.h>
59#include <linux/tty.h>
60#include <linux/tty_driver.h>
61#include <linux/tty_flip.h>
62#include <linux/serial.h>
63#include <linux/string.h>
64#include <linux/fcntl.h>
65#include <linux/ptrace.h>
66#include <linux/mutex.h>
67#include <linux/ioport.h>
68#include <linux/delay.h>
69#include <linux/completion.h>
70#include <linux/wait.h>
71#include <linux/pci.h>
72#include <linux/uaccess.h>
73#include <linux/atomic.h>
74#include <asm/unaligned.h>
75#include <linux/bitops.h>
76#include <linux/spinlock.h>
77#include <linux/init.h>
78
79/****** RocketPort includes ******/
80
81#include "rocket_int.h"
82#include "rocket.h"
83
84#define ROCKET_VERSION "2.09"
85#define ROCKET_DATE "12-June-2003"
86
87/****** RocketPort Local Variables ******/
88
89static void rp_do_poll(struct timer_list *unused);
90
91static struct tty_driver *rocket_driver;
92
93static struct rocket_version driver_version = {
94 ROCKET_VERSION, ROCKET_DATE
95};
96
97static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
98static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
99 /* eg. Bit 0 indicates port 0 has xmit data, ... */
100static atomic_t rp_num_ports_open; /* Number of serial ports open */
101static DEFINE_TIMER(rocket_timer, rp_do_poll);
102
103static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
104static unsigned long board2;
105static unsigned long board3;
106static unsigned long board4;
107static unsigned long controller;
108static bool support_low_speed;
109static unsigned long modem1;
110static unsigned long modem2;
111static unsigned long modem3;
112static unsigned long modem4;
113static unsigned long pc104_1[8];
114static unsigned long pc104_2[8];
115static unsigned long pc104_3[8];
116static unsigned long pc104_4[8];
117static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
118
119static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
120static unsigned long rcktpt_io_addr[NUM_BOARDS];
121static int rcktpt_type[NUM_BOARDS];
122static int is_PCI[NUM_BOARDS];
123static rocketModel_t rocketModel[NUM_BOARDS];
124static int max_board;
125static const struct tty_port_operations rocket_port_ops;
126
127/*
128 * The following arrays define the interrupt bits corresponding to each AIOP.
129 * These bits are different between the ISA and regular PCI boards and the
130 * Universal PCI boards.
131 */
132
133static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
134 AIOP_INTR_BIT_0,
135 AIOP_INTR_BIT_1,
136 AIOP_INTR_BIT_2,
137 AIOP_INTR_BIT_3
138};
139
140#ifdef CONFIG_PCI
141static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
142 UPCI_AIOP_INTR_BIT_0,
143 UPCI_AIOP_INTR_BIT_1,
144 UPCI_AIOP_INTR_BIT_2,
145 UPCI_AIOP_INTR_BIT_3
146};
147#endif
148
149static Byte_t RData[RDATASIZE] = {
150 0x00, 0x09, 0xf6, 0x82,
151 0x02, 0x09, 0x86, 0xfb,
152 0x04, 0x09, 0x00, 0x0a,
153 0x06, 0x09, 0x01, 0x0a,
154 0x08, 0x09, 0x8a, 0x13,
155 0x0a, 0x09, 0xc5, 0x11,
156 0x0c, 0x09, 0x86, 0x85,
157 0x0e, 0x09, 0x20, 0x0a,
158 0x10, 0x09, 0x21, 0x0a,
159 0x12, 0x09, 0x41, 0xff,
160 0x14, 0x09, 0x82, 0x00,
161 0x16, 0x09, 0x82, 0x7b,
162 0x18, 0x09, 0x8a, 0x7d,
163 0x1a, 0x09, 0x88, 0x81,
164 0x1c, 0x09, 0x86, 0x7a,
165 0x1e, 0x09, 0x84, 0x81,
166 0x20, 0x09, 0x82, 0x7c,
167 0x22, 0x09, 0x0a, 0x0a
168};
169
170static Byte_t RRegData[RREGDATASIZE] = {
171 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
172 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
173 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
174 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
175 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
176 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
177 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
178 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
179 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
180 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
181 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
182 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
183 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
184};
185
186static CONTROLLER_T sController[CTL_SIZE] = {
187 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
188 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
189 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
190 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
191 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
192 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
193 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
194 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
195};
196
197static Byte_t sBitMapClrTbl[8] = {
198 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
199};
200
201static Byte_t sBitMapSetTbl[8] = {
202 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
203};
204
205static int sClockPrescale = 0x14;
206
207/*
208 * Line number is the ttySIx number (x), the Minor number. We
209 * assign them sequentially, starting at zero. The following
210 * array keeps track of the line number assigned to a given board/aiop/channel.
211 */
212static unsigned char lineNumbers[MAX_RP_PORTS];
213static unsigned long nextLineNumber;
214
215/***** RocketPort Static Prototypes *********/
216static int __init init_ISA(int i);
217static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
218static void rp_flush_buffer(struct tty_struct *tty);
219static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
220static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
221static void rp_start(struct tty_struct *tty);
222static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
223 int ChanNum);
224static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
225static void sFlushRxFIFO(CHANNEL_T * ChP);
226static void sFlushTxFIFO(CHANNEL_T * ChP);
227static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
228static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
229static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
230static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
231static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
232static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
233 ByteIO_t * AiopIOList, int AiopIOListSize,
234 int IRQNum, Byte_t Frequency, int PeriodicOnly);
235static int sReadAiopID(ByteIO_t io);
236static int sReadAiopNumChan(WordIO_t io);
237
238MODULE_AUTHOR("Theodore Ts'o");
239MODULE_DESCRIPTION("Comtrol RocketPort driver");
240module_param_hw(board1, ulong, ioport, 0);
241MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
242module_param_hw(board2, ulong, ioport, 0);
243MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
244module_param_hw(board3, ulong, ioport, 0);
245MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
246module_param_hw(board4, ulong, ioport, 0);
247MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
248module_param_hw(controller, ulong, ioport, 0);
249MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
250module_param(support_low_speed, bool, 0);
251MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
252module_param(modem1, ulong, 0);
253MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
254module_param(modem2, ulong, 0);
255MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
256module_param(modem3, ulong, 0);
257MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
258module_param(modem4, ulong, 0);
259MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
260module_param_array(pc104_1, ulong, NULL, 0);
261MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
262module_param_array(pc104_2, ulong, NULL, 0);
263MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
264module_param_array(pc104_3, ulong, NULL, 0);
265MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
266module_param_array(pc104_4, ulong, NULL, 0);
267MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
268
269static int __init rp_init(void);
270static void rp_cleanup_module(void);
271
272module_init(rp_init);
273module_exit(rp_cleanup_module);
274
275
276MODULE_LICENSE("Dual BSD/GPL");
277
278/*************************************************************************/
279/* Module code starts here */
280
281static inline int rocket_paranoia_check(struct r_port *info,
282 const char *routine)
283{
284#ifdef ROCKET_PARANOIA_CHECK
285 if (!info)
286 return 1;
287 if (info->magic != RPORT_MAGIC) {
288 printk(KERN_WARNING "Warning: bad magic number for rocketport "
289 "struct in %s\n", routine);
290 return 1;
291 }
292#endif
293 return 0;
294}
295
296
297/* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
298 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
299 * tty layer.
300 */
301static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
302 unsigned int ChanStatus)
303{
304 unsigned int CharNStat;
305 int ToRecv, wRecv, space;
306 unsigned char *cbuf;
307
308 ToRecv = sGetRxCnt(cp);
309#ifdef ROCKET_DEBUG_INTR
310 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
311#endif
312 if (ToRecv == 0)
313 return;
314
315 /*
316 * if status indicates there are errored characters in the
317 * FIFO, then enter status mode (a word in FIFO holds
318 * character and status).
319 */
320 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
321 if (!(ChanStatus & STATMODE)) {
322#ifdef ROCKET_DEBUG_RECEIVE
323 printk(KERN_INFO "Entering STATMODE...\n");
324#endif
325 ChanStatus |= STATMODE;
326 sEnRxStatusMode(cp);
327 }
328 }
329
330 /*
331 * if we previously entered status mode, then read down the
332 * FIFO one word at a time, pulling apart the character and
333 * the status. Update error counters depending on status
334 */
335 if (ChanStatus & STATMODE) {
336#ifdef ROCKET_DEBUG_RECEIVE
337 printk(KERN_INFO "Ignore %x, read %x...\n",
338 info->ignore_status_mask, info->read_status_mask);
339#endif
340 while (ToRecv) {
341 char flag;
342
343 CharNStat = sInW(sGetTxRxDataIO(cp));
344#ifdef ROCKET_DEBUG_RECEIVE
345 printk(KERN_INFO "%x...\n", CharNStat);
346#endif
347 if (CharNStat & STMBREAKH)
348 CharNStat &= ~(STMFRAMEH | STMPARITYH);
349 if (CharNStat & info->ignore_status_mask) {
350 ToRecv--;
351 continue;
352 }
353 CharNStat &= info->read_status_mask;
354 if (CharNStat & STMBREAKH)
355 flag = TTY_BREAK;
356 else if (CharNStat & STMPARITYH)
357 flag = TTY_PARITY;
358 else if (CharNStat & STMFRAMEH)
359 flag = TTY_FRAME;
360 else if (CharNStat & STMRCVROVRH)
361 flag = TTY_OVERRUN;
362 else
363 flag = TTY_NORMAL;
364 tty_insert_flip_char(&info->port, CharNStat & 0xff,
365 flag);
366 ToRecv--;
367 }
368
369 /*
370 * after we've emptied the FIFO in status mode, turn
371 * status mode back off
372 */
373 if (sGetRxCnt(cp) == 0) {
374#ifdef ROCKET_DEBUG_RECEIVE
375 printk(KERN_INFO "Status mode off.\n");
376#endif
377 sDisRxStatusMode(cp);
378 }
379 } else {
380 /*
381 * we aren't in status mode, so read down the FIFO two
382 * characters at time by doing repeated word IO
383 * transfer.
384 */
385 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
386 if (space < ToRecv) {
387#ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
389#endif
390 if (space <= 0)
391 return;
392 ToRecv = space;
393 }
394 wRecv = ToRecv >> 1;
395 if (wRecv)
396 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
397 if (ToRecv & 1)
398 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
399 }
400 /* Push the data up to the tty layer */
401 tty_flip_buffer_push(&info->port);
402}
403
404/*
405 * Serial port transmit data function. Called from the timer polling loop as a
406 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
407 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
408 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
409 */
410static void rp_do_transmit(struct r_port *info)
411{
412 int c;
413 CHANNEL_t *cp = &info->channel;
414 struct tty_struct *tty;
415 unsigned long flags;
416
417#ifdef ROCKET_DEBUG_INTR
418 printk(KERN_DEBUG "%s\n", __func__);
419#endif
420 if (!info)
421 return;
422 tty = tty_port_tty_get(&info->port);
423
424 if (tty == NULL) {
425 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
426 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
427 return;
428 }
429
430 spin_lock_irqsave(&info->slock, flags);
431 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
432
433 /* Loop sending data to FIFO until done or FIFO full */
434 while (1) {
435 if (tty->stopped)
436 break;
437 c = min(info->xmit_fifo_room, info->xmit_cnt);
438 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
439 if (c <= 0 || info->xmit_fifo_room <= 0)
440 break;
441 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
442 if (c & 1)
443 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
444 info->xmit_tail += c;
445 info->xmit_tail &= XMIT_BUF_SIZE - 1;
446 info->xmit_cnt -= c;
447 info->xmit_fifo_room -= c;
448#ifdef ROCKET_DEBUG_INTR
449 printk(KERN_INFO "tx %d chars...\n", c);
450#endif
451 }
452
453 if (info->xmit_cnt == 0)
454 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
455
456 if (info->xmit_cnt < WAKEUP_CHARS) {
457 tty_wakeup(tty);
458#ifdef ROCKETPORT_HAVE_POLL_WAIT
459 wake_up_interruptible(&tty->poll_wait);
460#endif
461 }
462
463 spin_unlock_irqrestore(&info->slock, flags);
464 tty_kref_put(tty);
465
466#ifdef ROCKET_DEBUG_INTR
467 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
468 info->xmit_tail, info->xmit_fifo_room);
469#endif
470}
471
472/*
473 * Called when a serial port signals it has read data in it's RX FIFO.
474 * It checks what interrupts are pending and services them, including
475 * receiving serial data.
476 */
477static void rp_handle_port(struct r_port *info)
478{
479 CHANNEL_t *cp;
480 unsigned int IntMask, ChanStatus;
481
482 if (!info)
483 return;
484
485 if (!tty_port_initialized(&info->port)) {
486 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
487 "info->flags & NOT_INIT\n");
488 return;
489 }
490
491 cp = &info->channel;
492
493 IntMask = sGetChanIntID(cp) & info->intmask;
494#ifdef ROCKET_DEBUG_INTR
495 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
496#endif
497 ChanStatus = sGetChanStatus(cp);
498 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
499 rp_do_receive(info, cp, ChanStatus);
500 }
501 if (IntMask & DELTA_CD) { /* CD change */
502#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
503 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
504 (ChanStatus & CD_ACT) ? "on" : "off");
505#endif
506 if (!(ChanStatus & CD_ACT) && info->cd_status) {
507#ifdef ROCKET_DEBUG_HANGUP
508 printk(KERN_INFO "CD drop, calling hangup.\n");
509#endif
510 tty_port_tty_hangup(&info->port, false);
511 }
512 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
513 wake_up_interruptible(&info->port.open_wait);
514 }
515#ifdef ROCKET_DEBUG_INTR
516 if (IntMask & DELTA_CTS) { /* CTS change */
517 printk(KERN_INFO "CTS change...\n");
518 }
519 if (IntMask & DELTA_DSR) { /* DSR change */
520 printk(KERN_INFO "DSR change...\n");
521 }
522#endif
523}
524
525/*
526 * The top level polling routine. Repeats every 1/100 HZ (10ms).
527 */
528static void rp_do_poll(struct timer_list *unused)
529{
530 CONTROLLER_t *ctlp;
531 int ctrl, aiop, ch, line;
532 unsigned int xmitmask, i;
533 unsigned int CtlMask;
534 unsigned char AiopMask;
535 Word_t bit;
536
537 /* Walk through all the boards (ctrl's) */
538 for (ctrl = 0; ctrl < max_board; ctrl++) {
539 if (rcktpt_io_addr[ctrl] <= 0)
540 continue;
541
542 /* Get a ptr to the board's control struct */
543 ctlp = sCtlNumToCtlPtr(ctrl);
544
545 /* Get the interrupt status from the board */
546#ifdef CONFIG_PCI
547 if (ctlp->BusType == isPCI)
548 CtlMask = sPCIGetControllerIntStatus(ctlp);
549 else
550#endif
551 CtlMask = sGetControllerIntStatus(ctlp);
552
553 /* Check if any AIOP read bits are set */
554 for (aiop = 0; CtlMask; aiop++) {
555 bit = ctlp->AiopIntrBits[aiop];
556 if (CtlMask & bit) {
557 CtlMask &= ~bit;
558 AiopMask = sGetAiopIntStatus(ctlp, aiop);
559
560 /* Check if any port read bits are set */
561 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
562 if (AiopMask & 1) {
563
564 /* Get the line number (/dev/ttyRx number). */
565 /* Read the data from the port. */
566 line = GetLineNumber(ctrl, aiop, ch);
567 rp_handle_port(rp_table[line]);
568 }
569 }
570 }
571 }
572
573 xmitmask = xmit_flags[ctrl];
574
575 /*
576 * xmit_flags contains bit-significant flags, indicating there is data
577 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
578 * 1, ... (32 total possible). The variable i has the aiop and ch
579 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
580 */
581 if (xmitmask) {
582 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
583 if (xmitmask & (1 << i)) {
584 aiop = (i & 0x18) >> 3;
585 ch = i & 0x07;
586 line = GetLineNumber(ctrl, aiop, ch);
587 rp_do_transmit(rp_table[line]);
588 }
589 }
590 }
591 }
592
593 /*
594 * Reset the timer so we get called at the next clock tick (10ms).
595 */
596 if (atomic_read(&rp_num_ports_open))
597 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
598}
599
600/*
601 * Initializes the r_port structure for a port, as well as enabling the port on
602 * the board.
603 * Inputs: board, aiop, chan numbers
604 */
605static void __init
606init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
607{
608 unsigned rocketMode;
609 struct r_port *info;
610 int line;
611 CONTROLLER_T *ctlp;
612
613 /* Get the next available line number */
614 line = SetLineNumber(board, aiop, chan);
615
616 ctlp = sCtlNumToCtlPtr(board);
617
618 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
619 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
620 if (!info) {
621 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
622 line);
623 return;
624 }
625
626 info->magic = RPORT_MAGIC;
627 info->line = line;
628 info->ctlp = ctlp;
629 info->board = board;
630 info->aiop = aiop;
631 info->chan = chan;
632 tty_port_init(&info->port);
633 info->port.ops = &rocket_port_ops;
634 info->flags &= ~ROCKET_MODE_MASK;
635 switch (pc104[board][line]) {
636 case 422:
637 info->flags |= ROCKET_MODE_RS422;
638 break;
639 case 485:
640 info->flags |= ROCKET_MODE_RS485;
641 break;
642 case 232:
643 default:
644 info->flags |= ROCKET_MODE_RS232;
645 break;
646 }
647
648 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
649 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
650 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
651 board, aiop, chan);
652 tty_port_destroy(&info->port);
653 kfree(info);
654 return;
655 }
656
657 rocketMode = info->flags & ROCKET_MODE_MASK;
658
659 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
660 sEnRTSToggle(&info->channel);
661 else
662 sDisRTSToggle(&info->channel);
663
664 if (ctlp->boardType == ROCKET_TYPE_PC104) {
665 switch (rocketMode) {
666 case ROCKET_MODE_RS485:
667 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
668 break;
669 case ROCKET_MODE_RS422:
670 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
671 break;
672 case ROCKET_MODE_RS232:
673 default:
674 if (info->flags & ROCKET_RTS_TOGGLE)
675 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
676 else
677 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
678 break;
679 }
680 }
681 spin_lock_init(&info->slock);
682 mutex_init(&info->write_mtx);
683 rp_table[line] = info;
684 tty_port_register_device(&info->port, rocket_driver, line,
685 pci_dev ? &pci_dev->dev : NULL);
686}
687
688/*
689 * Configures a rocketport port according to its termio settings. Called from
690 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
691 */
692static void configure_r_port(struct tty_struct *tty, struct r_port *info,
693 struct ktermios *old_termios)
694{
695 unsigned cflag;
696 unsigned long flags;
697 unsigned rocketMode;
698 int bits, baud, divisor;
699 CHANNEL_t *cp;
700 struct ktermios *t = &tty->termios;
701
702 cp = &info->channel;
703 cflag = t->c_cflag;
704
705 /* Byte size and parity */
706 if ((cflag & CSIZE) == CS8) {
707 sSetData8(cp);
708 bits = 10;
709 } else {
710 sSetData7(cp);
711 bits = 9;
712 }
713 if (cflag & CSTOPB) {
714 sSetStop2(cp);
715 bits++;
716 } else {
717 sSetStop1(cp);
718 }
719
720 if (cflag & PARENB) {
721 sEnParity(cp);
722 bits++;
723 if (cflag & PARODD) {
724 sSetOddParity(cp);
725 } else {
726 sSetEvenParity(cp);
727 }
728 } else {
729 sDisParity(cp);
730 }
731
732 /* baud rate */
733 baud = tty_get_baud_rate(tty);
734 if (!baud)
735 baud = 9600;
736 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
737 if ((divisor >= 8192 || divisor < 0) && old_termios) {
738 baud = tty_termios_baud_rate(old_termios);
739 if (!baud)
740 baud = 9600;
741 divisor = (rp_baud_base[info->board] / baud) - 1;
742 }
743 if (divisor >= 8192 || divisor < 0) {
744 baud = 9600;
745 divisor = (rp_baud_base[info->board] / baud) - 1;
746 }
747 info->cps = baud / bits;
748 sSetBaud(cp, divisor);
749
750 /* FIXME: Should really back compute a baud rate from the divisor */
751 tty_encode_baud_rate(tty, baud, baud);
752
753 if (cflag & CRTSCTS) {
754 info->intmask |= DELTA_CTS;
755 sEnCTSFlowCtl(cp);
756 } else {
757 info->intmask &= ~DELTA_CTS;
758 sDisCTSFlowCtl(cp);
759 }
760 if (cflag & CLOCAL) {
761 info->intmask &= ~DELTA_CD;
762 } else {
763 spin_lock_irqsave(&info->slock, flags);
764 if (sGetChanStatus(cp) & CD_ACT)
765 info->cd_status = 1;
766 else
767 info->cd_status = 0;
768 info->intmask |= DELTA_CD;
769 spin_unlock_irqrestore(&info->slock, flags);
770 }
771
772 /*
773 * Handle software flow control in the board
774 */
775#ifdef ROCKET_SOFT_FLOW
776 if (I_IXON(tty)) {
777 sEnTxSoftFlowCtl(cp);
778 if (I_IXANY(tty)) {
779 sEnIXANY(cp);
780 } else {
781 sDisIXANY(cp);
782 }
783 sSetTxXONChar(cp, START_CHAR(tty));
784 sSetTxXOFFChar(cp, STOP_CHAR(tty));
785 } else {
786 sDisTxSoftFlowCtl(cp);
787 sDisIXANY(cp);
788 sClrTxXOFF(cp);
789 }
790#endif
791
792 /*
793 * Set up ignore/read mask words
794 */
795 info->read_status_mask = STMRCVROVRH | 0xFF;
796 if (I_INPCK(tty))
797 info->read_status_mask |= STMFRAMEH | STMPARITYH;
798 if (I_BRKINT(tty) || I_PARMRK(tty))
799 info->read_status_mask |= STMBREAKH;
800
801 /*
802 * Characters to ignore
803 */
804 info->ignore_status_mask = 0;
805 if (I_IGNPAR(tty))
806 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
807 if (I_IGNBRK(tty)) {
808 info->ignore_status_mask |= STMBREAKH;
809 /*
810 * If we're ignoring parity and break indicators,
811 * ignore overruns too. (For real raw support).
812 */
813 if (I_IGNPAR(tty))
814 info->ignore_status_mask |= STMRCVROVRH;
815 }
816
817 rocketMode = info->flags & ROCKET_MODE_MASK;
818
819 if ((info->flags & ROCKET_RTS_TOGGLE)
820 || (rocketMode == ROCKET_MODE_RS485))
821 sEnRTSToggle(cp);
822 else
823 sDisRTSToggle(cp);
824
825 sSetRTS(&info->channel);
826
827 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
828 switch (rocketMode) {
829 case ROCKET_MODE_RS485:
830 sSetInterfaceMode(cp, InterfaceModeRS485);
831 break;
832 case ROCKET_MODE_RS422:
833 sSetInterfaceMode(cp, InterfaceModeRS422);
834 break;
835 case ROCKET_MODE_RS232:
836 default:
837 if (info->flags & ROCKET_RTS_TOGGLE)
838 sSetInterfaceMode(cp, InterfaceModeRS232T);
839 else
840 sSetInterfaceMode(cp, InterfaceModeRS232);
841 break;
842 }
843 }
844}
845
846static int carrier_raised(struct tty_port *port)
847{
848 struct r_port *info = container_of(port, struct r_port, port);
849 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
850}
851
852static void dtr_rts(struct tty_port *port, int on)
853{
854 struct r_port *info = container_of(port, struct r_port, port);
855 if (on) {
856 sSetDTR(&info->channel);
857 sSetRTS(&info->channel);
858 } else {
859 sClrDTR(&info->channel);
860 sClrRTS(&info->channel);
861 }
862}
863
864/*
865 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
866 * port's r_port struct. Initializes the port hardware.
867 */
868static int rp_open(struct tty_struct *tty, struct file *filp)
869{
870 struct r_port *info;
871 struct tty_port *port;
872 int retval;
873 CHANNEL_t *cp;
874 unsigned long page;
875
876 info = rp_table[tty->index];
877 if (info == NULL)
878 return -ENXIO;
879 port = &info->port;
880
881 page = __get_free_page(GFP_KERNEL);
882 if (!page)
883 return -ENOMEM;
884
885 /*
886 * We must not sleep from here until the port is marked fully in use.
887 */
888 if (info->xmit_buf)
889 free_page(page);
890 else
891 info->xmit_buf = (unsigned char *) page;
892
893 tty->driver_data = info;
894 tty_port_tty_set(port, tty);
895
896 if (port->count++ == 0) {
897 atomic_inc(&rp_num_ports_open);
898
899#ifdef ROCKET_DEBUG_OPEN
900 printk(KERN_INFO "rocket mod++ = %d...\n",
901 atomic_read(&rp_num_ports_open));
902#endif
903 }
904#ifdef ROCKET_DEBUG_OPEN
905 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
906#endif
907
908 /*
909 * Info->count is now 1; so it's safe to sleep now.
910 */
911 if (!tty_port_initialized(port)) {
912 cp = &info->channel;
913 sSetRxTrigger(cp, TRIG_1);
914 if (sGetChanStatus(cp) & CD_ACT)
915 info->cd_status = 1;
916 else
917 info->cd_status = 0;
918 sDisRxStatusMode(cp);
919 sFlushRxFIFO(cp);
920 sFlushTxFIFO(cp);
921
922 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
923 sSetRxTrigger(cp, TRIG_1);
924
925 sGetChanStatus(cp);
926 sDisRxStatusMode(cp);
927 sClrTxXOFF(cp);
928
929 sDisCTSFlowCtl(cp);
930 sDisTxSoftFlowCtl(cp);
931
932 sEnRxFIFO(cp);
933 sEnTransmit(cp);
934
935 tty_port_set_initialized(&info->port, 1);
936
937 configure_r_port(tty, info, NULL);
938 if (C_BAUD(tty)) {
939 sSetDTR(cp);
940 sSetRTS(cp);
941 }
942 }
943 /* Starts (or resets) the maint polling loop */
944 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
945
946 retval = tty_port_block_til_ready(port, tty, filp);
947 if (retval) {
948#ifdef ROCKET_DEBUG_OPEN
949 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
950#endif
951 return retval;
952 }
953 return 0;
954}
955
956/*
957 * Exception handler that closes a serial port. info->port.count is considered critical.
958 */
959static void rp_close(struct tty_struct *tty, struct file *filp)
960{
961 struct r_port *info = tty->driver_data;
962 struct tty_port *port = &info->port;
963 int timeout;
964 CHANNEL_t *cp;
965
966 if (rocket_paranoia_check(info, "rp_close"))
967 return;
968
969#ifdef ROCKET_DEBUG_OPEN
970 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
971#endif
972
973 if (tty_port_close_start(port, tty, filp) == 0)
974 return;
975
976 mutex_lock(&port->mutex);
977 cp = &info->channel;
978 /*
979 * Before we drop DTR, make sure the UART transmitter
980 * has completely drained; this is especially
981 * important if there is a transmit FIFO!
982 */
983 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
984 if (timeout == 0)
985 timeout = 1;
986 rp_wait_until_sent(tty, timeout);
987 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
988
989 sDisTransmit(cp);
990 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
991 sDisCTSFlowCtl(cp);
992 sDisTxSoftFlowCtl(cp);
993 sClrTxXOFF(cp);
994 sFlushRxFIFO(cp);
995 sFlushTxFIFO(cp);
996 sClrRTS(cp);
997 if (C_HUPCL(tty))
998 sClrDTR(cp);
999
1000 rp_flush_buffer(tty);
1001
1002 tty_ldisc_flush(tty);
1003
1004 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1005
1006 /* We can't yet use tty_port_close_end as the buffer handling in this
1007 driver is a bit different to the usual */
1008
1009 if (port->blocked_open) {
1010 if (port->close_delay) {
1011 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1012 }
1013 wake_up_interruptible(&port->open_wait);
1014 } else {
1015 if (info->xmit_buf) {
1016 free_page((unsigned long) info->xmit_buf);
1017 info->xmit_buf = NULL;
1018 }
1019 }
1020 spin_lock_irq(&port->lock);
1021 tty->closing = 0;
1022 spin_unlock_irq(&port->lock);
1023 tty_port_set_initialized(port, 0);
1024 tty_port_set_active(port, 0);
1025 mutex_unlock(&port->mutex);
1026 tty_port_tty_set(port, NULL);
1027
1028 atomic_dec(&rp_num_ports_open);
1029
1030#ifdef ROCKET_DEBUG_OPEN
1031 printk(KERN_INFO "rocket mod-- = %d...\n",
1032 atomic_read(&rp_num_ports_open));
1033 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1034#endif
1035
1036}
1037
1038static void rp_set_termios(struct tty_struct *tty,
1039 struct ktermios *old_termios)
1040{
1041 struct r_port *info = tty->driver_data;
1042 CHANNEL_t *cp;
1043 unsigned cflag;
1044
1045 if (rocket_paranoia_check(info, "rp_set_termios"))
1046 return;
1047
1048 cflag = tty->termios.c_cflag;
1049
1050 /*
1051 * This driver doesn't support CS5 or CS6
1052 */
1053 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1054 tty->termios.c_cflag =
1055 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1056 /* Or CMSPAR */
1057 tty->termios.c_cflag &= ~CMSPAR;
1058
1059 configure_r_port(tty, info, old_termios);
1060
1061 cp = &info->channel;
1062
1063 /* Handle transition to B0 status */
1064 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
1065 sClrDTR(cp);
1066 sClrRTS(cp);
1067 }
1068
1069 /* Handle transition away from B0 status */
1070 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
1071 sSetRTS(cp);
1072 sSetDTR(cp);
1073 }
1074
1075 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty))
1076 rp_start(tty);
1077}
1078
1079static int rp_break(struct tty_struct *tty, int break_state)
1080{
1081 struct r_port *info = tty->driver_data;
1082 unsigned long flags;
1083
1084 if (rocket_paranoia_check(info, "rp_break"))
1085 return -EINVAL;
1086
1087 spin_lock_irqsave(&info->slock, flags);
1088 if (break_state == -1)
1089 sSendBreak(&info->channel);
1090 else
1091 sClrBreak(&info->channel);
1092 spin_unlock_irqrestore(&info->slock, flags);
1093 return 0;
1094}
1095
1096/*
1097 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1098 * the UPCI boards was added, it was decided to make this a function because
1099 * the macro was getting too complicated. All cases except the first one
1100 * (UPCIRingInd) are taken directly from the original macro.
1101 */
1102static int sGetChanRI(CHANNEL_T * ChP)
1103{
1104 CONTROLLER_t *CtlP = ChP->CtlP;
1105 int ChanNum = ChP->ChanNum;
1106 int RingInd = 0;
1107
1108 if (CtlP->UPCIRingInd)
1109 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1110 else if (CtlP->AltChanRingIndicator)
1111 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1112 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1113 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1114
1115 return RingInd;
1116}
1117
1118/********************************************************************************************/
1119/* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1120
1121/*
1122 * Returns the state of the serial modem control lines. These next 2 functions
1123 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1124 */
1125static int rp_tiocmget(struct tty_struct *tty)
1126{
1127 struct r_port *info = tty->driver_data;
1128 unsigned int control, result, ChanStatus;
1129
1130 ChanStatus = sGetChanStatusLo(&info->channel);
1131 control = info->channel.TxControl[3];
1132 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1133 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1134 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1135 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1136 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1137 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1138
1139 return result;
1140}
1141
1142/*
1143 * Sets the modem control lines
1144 */
1145static int rp_tiocmset(struct tty_struct *tty,
1146 unsigned int set, unsigned int clear)
1147{
1148 struct r_port *info = tty->driver_data;
1149
1150 if (set & TIOCM_RTS)
1151 info->channel.TxControl[3] |= SET_RTS;
1152 if (set & TIOCM_DTR)
1153 info->channel.TxControl[3] |= SET_DTR;
1154 if (clear & TIOCM_RTS)
1155 info->channel.TxControl[3] &= ~SET_RTS;
1156 if (clear & TIOCM_DTR)
1157 info->channel.TxControl[3] &= ~SET_DTR;
1158
1159 out32(info->channel.IndexAddr, info->channel.TxControl);
1160 return 0;
1161}
1162
1163static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1164{
1165 struct rocket_config tmp;
1166
1167 memset(&tmp, 0, sizeof (tmp));
1168 mutex_lock(&info->port.mutex);
1169 tmp.line = info->line;
1170 tmp.flags = info->flags;
1171 tmp.close_delay = info->port.close_delay;
1172 tmp.closing_wait = info->port.closing_wait;
1173 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1174 mutex_unlock(&info->port.mutex);
1175
1176 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1177 return -EFAULT;
1178 return 0;
1179}
1180
1181static int set_config(struct tty_struct *tty, struct r_port *info,
1182 struct rocket_config __user *new_info)
1183{
1184 struct rocket_config new_serial;
1185
1186 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1187 return -EFAULT;
1188
1189 mutex_lock(&info->port.mutex);
1190 if (!capable(CAP_SYS_ADMIN))
1191 {
1192 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1193 mutex_unlock(&info->port.mutex);
1194 return -EPERM;
1195 }
1196 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1197 mutex_unlock(&info->port.mutex);
1198 return 0;
1199 }
1200
1201 if ((new_serial.flags ^ info->flags) & ROCKET_SPD_MASK) {
1202 /* warn about deprecation, unless clearing */
1203 if (new_serial.flags & ROCKET_SPD_MASK)
1204 dev_warn_ratelimited(tty->dev, "use of SPD flags is deprecated\n");
1205 }
1206
1207 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1208 info->port.close_delay = new_serial.close_delay;
1209 info->port.closing_wait = new_serial.closing_wait;
1210
1211 mutex_unlock(&info->port.mutex);
1212
1213 configure_r_port(tty, info, NULL);
1214 return 0;
1215}
1216
1217/*
1218 * This function fills in a rocket_ports struct with information
1219 * about what boards/ports are in the system. This info is passed
1220 * to user space. See setrocket.c where the info is used to create
1221 * the /dev/ttyRx ports.
1222 */
1223static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1224{
1225 struct rocket_ports tmp;
1226 int board;
1227
1228 memset(&tmp, 0, sizeof (tmp));
1229 tmp.tty_major = rocket_driver->major;
1230
1231 for (board = 0; board < 4; board++) {
1232 tmp.rocketModel[board].model = rocketModel[board].model;
1233 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1234 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1235 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1236 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1237 }
1238 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1239 return -EFAULT;
1240 return 0;
1241}
1242
1243static int reset_rm2(struct r_port *info, void __user *arg)
1244{
1245 int reset;
1246
1247 if (!capable(CAP_SYS_ADMIN))
1248 return -EPERM;
1249
1250 if (copy_from_user(&reset, arg, sizeof (int)))
1251 return -EFAULT;
1252 if (reset)
1253 reset = 1;
1254
1255 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1256 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1257 return -EINVAL;
1258
1259 if (info->ctlp->BusType == isISA)
1260 sModemReset(info->ctlp, info->chan, reset);
1261 else
1262 sPCIModemReset(info->ctlp, info->chan, reset);
1263
1264 return 0;
1265}
1266
1267static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1268{
1269 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1270 return -EFAULT;
1271 return 0;
1272}
1273
1274/* IOCTL call handler into the driver */
1275static int rp_ioctl(struct tty_struct *tty,
1276 unsigned int cmd, unsigned long arg)
1277{
1278 struct r_port *info = tty->driver_data;
1279 void __user *argp = (void __user *)arg;
1280 int ret = 0;
1281
1282 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1283 return -ENXIO;
1284
1285 switch (cmd) {
1286 case RCKP_GET_CONFIG:
1287 dev_warn_ratelimited(tty->dev,
1288 "RCKP_GET_CONFIG option is deprecated\n");
1289 ret = get_config(info, argp);
1290 break;
1291 case RCKP_SET_CONFIG:
1292 dev_warn_ratelimited(tty->dev,
1293 "RCKP_SET_CONFIG option is deprecated\n");
1294 ret = set_config(tty, info, argp);
1295 break;
1296 case RCKP_GET_PORTS:
1297 dev_warn_ratelimited(tty->dev,
1298 "RCKP_GET_PORTS option is deprecated\n");
1299 ret = get_ports(info, argp);
1300 break;
1301 case RCKP_RESET_RM2:
1302 dev_warn_ratelimited(tty->dev,
1303 "RCKP_RESET_RM2 option is deprecated\n");
1304 ret = reset_rm2(info, argp);
1305 break;
1306 case RCKP_GET_VERSION:
1307 dev_warn_ratelimited(tty->dev,
1308 "RCKP_GET_VERSION option is deprecated\n");
1309 ret = get_version(info, argp);
1310 break;
1311 default:
1312 ret = -ENOIOCTLCMD;
1313 }
1314 return ret;
1315}
1316
1317static void rp_send_xchar(struct tty_struct *tty, char ch)
1318{
1319 struct r_port *info = tty->driver_data;
1320 CHANNEL_t *cp;
1321
1322 if (rocket_paranoia_check(info, "rp_send_xchar"))
1323 return;
1324
1325 cp = &info->channel;
1326 if (sGetTxCnt(cp))
1327 sWriteTxPrioByte(cp, ch);
1328 else
1329 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1330}
1331
1332static void rp_throttle(struct tty_struct *tty)
1333{
1334 struct r_port *info = tty->driver_data;
1335
1336#ifdef ROCKET_DEBUG_THROTTLE
1337 printk(KERN_INFO "throttle %s ....\n", tty->name);
1338#endif
1339
1340 if (rocket_paranoia_check(info, "rp_throttle"))
1341 return;
1342
1343 if (I_IXOFF(tty))
1344 rp_send_xchar(tty, STOP_CHAR(tty));
1345
1346 sClrRTS(&info->channel);
1347}
1348
1349static void rp_unthrottle(struct tty_struct *tty)
1350{
1351 struct r_port *info = tty->driver_data;
1352#ifdef ROCKET_DEBUG_THROTTLE
1353 printk(KERN_INFO "unthrottle %s ....\n", tty->name);
1354#endif
1355
1356 if (rocket_paranoia_check(info, "rp_unthrottle"))
1357 return;
1358
1359 if (I_IXOFF(tty))
1360 rp_send_xchar(tty, START_CHAR(tty));
1361
1362 sSetRTS(&info->channel);
1363}
1364
1365/*
1366 * ------------------------------------------------------------
1367 * rp_stop() and rp_start()
1368 *
1369 * This routines are called before setting or resetting tty->stopped.
1370 * They enable or disable transmitter interrupts, as necessary.
1371 * ------------------------------------------------------------
1372 */
1373static void rp_stop(struct tty_struct *tty)
1374{
1375 struct r_port *info = tty->driver_data;
1376
1377#ifdef ROCKET_DEBUG_FLOW
1378 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1379 info->xmit_cnt, info->xmit_fifo_room);
1380#endif
1381
1382 if (rocket_paranoia_check(info, "rp_stop"))
1383 return;
1384
1385 if (sGetTxCnt(&info->channel))
1386 sDisTransmit(&info->channel);
1387}
1388
1389static void rp_start(struct tty_struct *tty)
1390{
1391 struct r_port *info = tty->driver_data;
1392
1393#ifdef ROCKET_DEBUG_FLOW
1394 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1395 info->xmit_cnt, info->xmit_fifo_room);
1396#endif
1397
1398 if (rocket_paranoia_check(info, "rp_stop"))
1399 return;
1400
1401 sEnTransmit(&info->channel);
1402 set_bit((info->aiop * 8) + info->chan,
1403 (void *) &xmit_flags[info->board]);
1404}
1405
1406/*
1407 * rp_wait_until_sent() --- wait until the transmitter is empty
1408 */
1409static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1410{
1411 struct r_port *info = tty->driver_data;
1412 CHANNEL_t *cp;
1413 unsigned long orig_jiffies;
1414 int check_time, exit_time;
1415 int txcnt;
1416
1417 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1418 return;
1419
1420 cp = &info->channel;
1421
1422 orig_jiffies = jiffies;
1423#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1424 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1425 jiffies);
1426 printk(KERN_INFO "cps=%d...\n", info->cps);
1427#endif
1428 while (1) {
1429 txcnt = sGetTxCnt(cp);
1430 if (!txcnt) {
1431 if (sGetChanStatusLo(cp) & TXSHRMT)
1432 break;
1433 check_time = (HZ / info->cps) / 5;
1434 } else {
1435 check_time = HZ * txcnt / info->cps;
1436 }
1437 if (timeout) {
1438 exit_time = orig_jiffies + timeout - jiffies;
1439 if (exit_time <= 0)
1440 break;
1441 if (exit_time < check_time)
1442 check_time = exit_time;
1443 }
1444 if (check_time == 0)
1445 check_time = 1;
1446#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1447 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1448 jiffies, check_time);
1449#endif
1450 msleep_interruptible(jiffies_to_msecs(check_time));
1451 if (signal_pending(current))
1452 break;
1453 }
1454 __set_current_state(TASK_RUNNING);
1455#ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1456 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1457#endif
1458}
1459
1460/*
1461 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1462 */
1463static void rp_hangup(struct tty_struct *tty)
1464{
1465 CHANNEL_t *cp;
1466 struct r_port *info = tty->driver_data;
1467 unsigned long flags;
1468
1469 if (rocket_paranoia_check(info, "rp_hangup"))
1470 return;
1471
1472#if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1473 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1474#endif
1475 rp_flush_buffer(tty);
1476 spin_lock_irqsave(&info->port.lock, flags);
1477 if (info->port.count)
1478 atomic_dec(&rp_num_ports_open);
1479 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1480 spin_unlock_irqrestore(&info->port.lock, flags);
1481
1482 tty_port_hangup(&info->port);
1483
1484 cp = &info->channel;
1485 sDisRxFIFO(cp);
1486 sDisTransmit(cp);
1487 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1488 sDisCTSFlowCtl(cp);
1489 sDisTxSoftFlowCtl(cp);
1490 sClrTxXOFF(cp);
1491 tty_port_set_initialized(&info->port, 0);
1492
1493 wake_up_interruptible(&info->port.open_wait);
1494}
1495
1496/*
1497 * Exception handler - write char routine. The RocketPort driver uses a
1498 * double-buffering strategy, with the twist that if the in-memory CPU
1499 * buffer is empty, and there's space in the transmit FIFO, the
1500 * writing routines will write directly to transmit FIFO.
1501 * Write buffer and counters protected by spinlocks
1502 */
1503static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1504{
1505 struct r_port *info = tty->driver_data;
1506 CHANNEL_t *cp;
1507 unsigned long flags;
1508
1509 if (rocket_paranoia_check(info, "rp_put_char"))
1510 return 0;
1511
1512 /*
1513 * Grab the port write mutex, locking out other processes that try to
1514 * write to this port
1515 */
1516 mutex_lock(&info->write_mtx);
1517
1518#ifdef ROCKET_DEBUG_WRITE
1519 printk(KERN_INFO "rp_put_char %c...\n", ch);
1520#endif
1521
1522 spin_lock_irqsave(&info->slock, flags);
1523 cp = &info->channel;
1524
1525 if (!tty->stopped && info->xmit_fifo_room == 0)
1526 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1527
1528 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1529 info->xmit_buf[info->xmit_head++] = ch;
1530 info->xmit_head &= XMIT_BUF_SIZE - 1;
1531 info->xmit_cnt++;
1532 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1533 } else {
1534 sOutB(sGetTxRxDataIO(cp), ch);
1535 info->xmit_fifo_room--;
1536 }
1537 spin_unlock_irqrestore(&info->slock, flags);
1538 mutex_unlock(&info->write_mtx);
1539 return 1;
1540}
1541
1542/*
1543 * Exception handler - write routine, called when user app writes to the device.
1544 * A per port write mutex is used to protect from another process writing to
1545 * this port at the same time. This other process could be running on the other CPU
1546 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1547 * Spinlocks protect the info xmit members.
1548 */
1549static int rp_write(struct tty_struct *tty,
1550 const unsigned char *buf, int count)
1551{
1552 struct r_port *info = tty->driver_data;
1553 CHANNEL_t *cp;
1554 const unsigned char *b;
1555 int c, retval = 0;
1556 unsigned long flags;
1557
1558 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1559 return 0;
1560
1561 if (mutex_lock_interruptible(&info->write_mtx))
1562 return -ERESTARTSYS;
1563
1564#ifdef ROCKET_DEBUG_WRITE
1565 printk(KERN_INFO "rp_write %d chars...\n", count);
1566#endif
1567 cp = &info->channel;
1568
1569 if (!tty->stopped && info->xmit_fifo_room < count)
1570 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1571
1572 /*
1573 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1574 * into FIFO. Use the write queue for temp storage.
1575 */
1576 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1577 c = min(count, info->xmit_fifo_room);
1578 b = buf;
1579
1580 /* Push data into FIFO, 2 bytes at a time */
1581 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1582
1583 /* If there is a byte remaining, write it */
1584 if (c & 1)
1585 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1586
1587 retval += c;
1588 buf += c;
1589 count -= c;
1590
1591 spin_lock_irqsave(&info->slock, flags);
1592 info->xmit_fifo_room -= c;
1593 spin_unlock_irqrestore(&info->slock, flags);
1594 }
1595
1596 /* If count is zero, we wrote it all and are done */
1597 if (!count)
1598 goto end;
1599
1600 /* Write remaining data into the port's xmit_buf */
1601 while (1) {
1602 /* Hung up ? */
1603 if (!tty_port_active(&info->port))
1604 goto end;
1605 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1606 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1607 if (c <= 0)
1608 break;
1609
1610 b = buf;
1611 memcpy(info->xmit_buf + info->xmit_head, b, c);
1612
1613 spin_lock_irqsave(&info->slock, flags);
1614 info->xmit_head =
1615 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1616 info->xmit_cnt += c;
1617 spin_unlock_irqrestore(&info->slock, flags);
1618
1619 buf += c;
1620 count -= c;
1621 retval += c;
1622 }
1623
1624 if ((retval > 0) && !tty->stopped)
1625 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1626
1627end:
1628 if (info->xmit_cnt < WAKEUP_CHARS) {
1629 tty_wakeup(tty);
1630#ifdef ROCKETPORT_HAVE_POLL_WAIT
1631 wake_up_interruptible(&tty->poll_wait);
1632#endif
1633 }
1634 mutex_unlock(&info->write_mtx);
1635 return retval;
1636}
1637
1638/*
1639 * Return the number of characters that can be sent. We estimate
1640 * only using the in-memory transmit buffer only, and ignore the
1641 * potential space in the transmit FIFO.
1642 */
1643static int rp_write_room(struct tty_struct *tty)
1644{
1645 struct r_port *info = tty->driver_data;
1646 int ret;
1647
1648 if (rocket_paranoia_check(info, "rp_write_room"))
1649 return 0;
1650
1651 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1652 if (ret < 0)
1653 ret = 0;
1654#ifdef ROCKET_DEBUG_WRITE
1655 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1656#endif
1657 return ret;
1658}
1659
1660/*
1661 * Return the number of characters in the buffer. Again, this only
1662 * counts those characters in the in-memory transmit buffer.
1663 */
1664static int rp_chars_in_buffer(struct tty_struct *tty)
1665{
1666 struct r_port *info = tty->driver_data;
1667
1668 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1669 return 0;
1670
1671#ifdef ROCKET_DEBUG_WRITE
1672 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1673#endif
1674 return info->xmit_cnt;
1675}
1676
1677/*
1678 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1679 * r_port struct for the port. Note that spinlock are used to protect info members,
1680 * do not call this function if the spinlock is already held.
1681 */
1682static void rp_flush_buffer(struct tty_struct *tty)
1683{
1684 struct r_port *info = tty->driver_data;
1685 CHANNEL_t *cp;
1686 unsigned long flags;
1687
1688 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1689 return;
1690
1691 spin_lock_irqsave(&info->slock, flags);
1692 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1693 spin_unlock_irqrestore(&info->slock, flags);
1694
1695#ifdef ROCKETPORT_HAVE_POLL_WAIT
1696 wake_up_interruptible(&tty->poll_wait);
1697#endif
1698 tty_wakeup(tty);
1699
1700 cp = &info->channel;
1701 sFlushTxFIFO(cp);
1702}
1703
1704#ifdef CONFIG_PCI
1705
1706static const struct pci_device_id rocket_pci_ids[] = {
1707 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1708 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1709 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1710 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1711 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1712 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1713 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1714 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1715 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1716 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1717 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1718 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1719 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1720 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1721 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1722 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1723 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1724 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1725 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1726 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1727 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1728 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1729 { }
1730};
1731MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1732
1733/* Resets the speaker controller on RocketModem II and III devices */
1734static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1735{
1736 ByteIO_t addr;
1737
1738 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1739 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1740 addr = CtlP->AiopIO[0] + 0x4F;
1741 sOutB(addr, 0);
1742 }
1743
1744 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1745 if ((model == MODEL_UPCI_RM3_8PORT)
1746 || (model == MODEL_UPCI_RM3_4PORT)) {
1747 addr = CtlP->AiopIO[0] + 0x88;
1748 sOutB(addr, 0);
1749 }
1750}
1751
1752/***************************************************************************
1753Function: sPCIInitController
1754Purpose: Initialization of controller global registers and controller
1755 structure.
1756Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1757 IRQNum,Frequency,PeriodicOnly)
1758 CONTROLLER_T *CtlP; Ptr to controller structure
1759 int CtlNum; Controller number
1760 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1761 This list must be in the order the AIOPs will be found on the
1762 controller. Once an AIOP in the list is not found, it is
1763 assumed that there are no more AIOPs on the controller.
1764 int AiopIOListSize; Number of addresses in AiopIOList
1765 int IRQNum; Interrupt Request number. Can be any of the following:
1766 0: Disable global interrupts
1767 3: IRQ 3
1768 4: IRQ 4
1769 5: IRQ 5
1770 9: IRQ 9
1771 10: IRQ 10
1772 11: IRQ 11
1773 12: IRQ 12
1774 15: IRQ 15
1775 Byte_t Frequency: A flag identifying the frequency
1776 of the periodic interrupt, can be any one of the following:
1777 FREQ_DIS - periodic interrupt disabled
1778 FREQ_137HZ - 137 Hertz
1779 FREQ_69HZ - 69 Hertz
1780 FREQ_34HZ - 34 Hertz
1781 FREQ_17HZ - 17 Hertz
1782 FREQ_9HZ - 9 Hertz
1783 FREQ_4HZ - 4 Hertz
1784 If IRQNum is set to 0 the Frequency parameter is
1785 overidden, it is forced to a value of FREQ_DIS.
1786 int PeriodicOnly: 1 if all interrupts except the periodic
1787 interrupt are to be blocked.
1788 0 is both the periodic interrupt and
1789 other channel interrupts are allowed.
1790 If IRQNum is set to 0 the PeriodicOnly parameter is
1791 overidden, it is forced to a value of 0.
1792Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1793 initialization failed.
1794
1795Comments:
1796 If periodic interrupts are to be disabled but AIOP interrupts
1797 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1798
1799 If interrupts are to be completely disabled set IRQNum to 0.
1800
1801 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1802 invalid combination.
1803
1804 This function performs initialization of global interrupt modes,
1805 but it does not actually enable global interrupts. To enable
1806 and disable global interrupts use functions sEnGlobalInt() and
1807 sDisGlobalInt(). Enabling of global interrupts is normally not
1808 done until all other initializations are complete.
1809
1810 Even if interrupts are globally enabled, they must also be
1811 individually enabled for each channel that is to generate
1812 interrupts.
1813
1814Warnings: No range checking on any of the parameters is done.
1815
1816 No context switches are allowed while executing this function.
1817
1818 After this function all AIOPs on the controller are disabled,
1819 they can be enabled with sEnAiop().
1820*/
1821static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1822 ByteIO_t * AiopIOList, int AiopIOListSize,
1823 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1824 int PeriodicOnly, int altChanRingIndicator,
1825 int UPCIRingInd)
1826{
1827 int i;
1828 ByteIO_t io;
1829
1830 CtlP->AltChanRingIndicator = altChanRingIndicator;
1831 CtlP->UPCIRingInd = UPCIRingInd;
1832 CtlP->CtlNum = CtlNum;
1833 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1834 CtlP->BusType = isPCI; /* controller release 1 */
1835
1836 if (ConfigIO) {
1837 CtlP->isUPCI = 1;
1838 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1839 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1840 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1841 } else {
1842 CtlP->isUPCI = 0;
1843 CtlP->PCIIO =
1844 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1845 CtlP->AiopIntrBits = aiop_intr_bits;
1846 }
1847
1848 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1849 /* Init AIOPs */
1850 CtlP->NumAiop = 0;
1851 for (i = 0; i < AiopIOListSize; i++) {
1852 io = AiopIOList[i];
1853 CtlP->AiopIO[i] = (WordIO_t) io;
1854 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1855
1856 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1857 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1858 break; /* done looking for AIOPs */
1859
1860 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1861 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1862 sOutB(io + _INDX_DATA, sClockPrescale);
1863 CtlP->NumAiop++; /* bump count of AIOPs */
1864 }
1865
1866 if (CtlP->NumAiop == 0)
1867 return (-1);
1868 else
1869 return (CtlP->NumAiop);
1870}
1871
1872/*
1873 * Called when a PCI card is found. Retrieves and stores model information,
1874 * init's aiopic and serial port hardware.
1875 * Inputs: i is the board number (0-n)
1876 */
1877static __init int register_PCI(int i, struct pci_dev *dev)
1878{
1879 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1880 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1881 CONTROLLER_t *ctlp;
1882
1883 int fast_clock = 0;
1884 int altChanRingIndicator = 0;
1885 int ports_per_aiop = 8;
1886 WordIO_t ConfigIO = 0;
1887 ByteIO_t UPCIRingInd = 0;
1888
1889 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1890 pci_enable_device(dev) || i >= NUM_BOARDS)
1891 return 0;
1892
1893 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1894
1895 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1896 rocketModel[i].loadrm2 = 0;
1897 rocketModel[i].startingPortNumber = nextLineNumber;
1898
1899 /* Depending on the model, set up some config variables */
1900 switch (dev->device) {
1901 case PCI_DEVICE_ID_RP4QUAD:
1902 max_num_aiops = 1;
1903 ports_per_aiop = 4;
1904 rocketModel[i].model = MODEL_RP4QUAD;
1905 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1906 rocketModel[i].numPorts = 4;
1907 break;
1908 case PCI_DEVICE_ID_RP8OCTA:
1909 max_num_aiops = 1;
1910 rocketModel[i].model = MODEL_RP8OCTA;
1911 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1912 rocketModel[i].numPorts = 8;
1913 break;
1914 case PCI_DEVICE_ID_URP8OCTA:
1915 max_num_aiops = 1;
1916 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1917 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1918 rocketModel[i].numPorts = 8;
1919 break;
1920 case PCI_DEVICE_ID_RP8INTF:
1921 max_num_aiops = 1;
1922 rocketModel[i].model = MODEL_RP8INTF;
1923 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1924 rocketModel[i].numPorts = 8;
1925 break;
1926 case PCI_DEVICE_ID_URP8INTF:
1927 max_num_aiops = 1;
1928 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1929 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1930 rocketModel[i].numPorts = 8;
1931 break;
1932 case PCI_DEVICE_ID_RP8J:
1933 max_num_aiops = 1;
1934 rocketModel[i].model = MODEL_RP8J;
1935 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1936 rocketModel[i].numPorts = 8;
1937 break;
1938 case PCI_DEVICE_ID_RP4J:
1939 max_num_aiops = 1;
1940 ports_per_aiop = 4;
1941 rocketModel[i].model = MODEL_RP4J;
1942 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1943 rocketModel[i].numPorts = 4;
1944 break;
1945 case PCI_DEVICE_ID_RP8SNI:
1946 max_num_aiops = 1;
1947 rocketModel[i].model = MODEL_RP8SNI;
1948 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1949 rocketModel[i].numPorts = 8;
1950 break;
1951 case PCI_DEVICE_ID_RP16SNI:
1952 max_num_aiops = 2;
1953 rocketModel[i].model = MODEL_RP16SNI;
1954 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1955 rocketModel[i].numPorts = 16;
1956 break;
1957 case PCI_DEVICE_ID_RP16INTF:
1958 max_num_aiops = 2;
1959 rocketModel[i].model = MODEL_RP16INTF;
1960 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1961 rocketModel[i].numPorts = 16;
1962 break;
1963 case PCI_DEVICE_ID_URP16INTF:
1964 max_num_aiops = 2;
1965 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1966 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1967 rocketModel[i].numPorts = 16;
1968 break;
1969 case PCI_DEVICE_ID_CRP16INTF:
1970 max_num_aiops = 2;
1971 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1972 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1973 rocketModel[i].numPorts = 16;
1974 break;
1975 case PCI_DEVICE_ID_RP32INTF:
1976 max_num_aiops = 4;
1977 rocketModel[i].model = MODEL_RP32INTF;
1978 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1979 rocketModel[i].numPorts = 32;
1980 break;
1981 case PCI_DEVICE_ID_URP32INTF:
1982 max_num_aiops = 4;
1983 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1984 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1985 rocketModel[i].numPorts = 32;
1986 break;
1987 case PCI_DEVICE_ID_RPP4:
1988 max_num_aiops = 1;
1989 ports_per_aiop = 4;
1990 altChanRingIndicator++;
1991 fast_clock++;
1992 rocketModel[i].model = MODEL_RPP4;
1993 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1994 rocketModel[i].numPorts = 4;
1995 break;
1996 case PCI_DEVICE_ID_RPP8:
1997 max_num_aiops = 2;
1998 ports_per_aiop = 4;
1999 altChanRingIndicator++;
2000 fast_clock++;
2001 rocketModel[i].model = MODEL_RPP8;
2002 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2003 rocketModel[i].numPorts = 8;
2004 break;
2005 case PCI_DEVICE_ID_RP2_232:
2006 max_num_aiops = 1;
2007 ports_per_aiop = 2;
2008 altChanRingIndicator++;
2009 fast_clock++;
2010 rocketModel[i].model = MODEL_RP2_232;
2011 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2012 rocketModel[i].numPorts = 2;
2013 break;
2014 case PCI_DEVICE_ID_RP2_422:
2015 max_num_aiops = 1;
2016 ports_per_aiop = 2;
2017 altChanRingIndicator++;
2018 fast_clock++;
2019 rocketModel[i].model = MODEL_RP2_422;
2020 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2021 rocketModel[i].numPorts = 2;
2022 break;
2023 case PCI_DEVICE_ID_RP6M:
2024
2025 max_num_aiops = 1;
2026 ports_per_aiop = 6;
2027
2028 /* If revision is 1, the rocketmodem flash must be loaded.
2029 * If it is 2 it is a "socketed" version. */
2030 if (dev->revision == 1) {
2031 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2032 rocketModel[i].loadrm2 = 1;
2033 } else {
2034 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2035 }
2036
2037 rocketModel[i].model = MODEL_RP6M;
2038 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2039 rocketModel[i].numPorts = 6;
2040 break;
2041 case PCI_DEVICE_ID_RP4M:
2042 max_num_aiops = 1;
2043 ports_per_aiop = 4;
2044 if (dev->revision == 1) {
2045 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2046 rocketModel[i].loadrm2 = 1;
2047 } else {
2048 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2049 }
2050
2051 rocketModel[i].model = MODEL_RP4M;
2052 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2053 rocketModel[i].numPorts = 4;
2054 break;
2055 default:
2056 max_num_aiops = 0;
2057 break;
2058 }
2059
2060 /*
2061 * Check for UPCI boards.
2062 */
2063
2064 switch (dev->device) {
2065 case PCI_DEVICE_ID_URP32INTF:
2066 case PCI_DEVICE_ID_URP8INTF:
2067 case PCI_DEVICE_ID_URP16INTF:
2068 case PCI_DEVICE_ID_CRP16INTF:
2069 case PCI_DEVICE_ID_URP8OCTA:
2070 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2071 ConfigIO = pci_resource_start(dev, 1);
2072 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2073 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2074
2075 /*
2076 * Check for octa or quad cable.
2077 */
2078 if (!
2079 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2080 PCI_GPIO_CTRL_8PORT)) {
2081 ports_per_aiop = 4;
2082 rocketModel[i].numPorts = 4;
2083 }
2084 }
2085 break;
2086 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2087 max_num_aiops = 1;
2088 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2089 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2090 rocketModel[i].numPorts = 8;
2091 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2092 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2093 ConfigIO = pci_resource_start(dev, 1);
2094 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2095 break;
2096 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2097 max_num_aiops = 1;
2098 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2099 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2100 rocketModel[i].numPorts = 4;
2101 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2102 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2103 ConfigIO = pci_resource_start(dev, 1);
2104 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2105 break;
2106 default:
2107 break;
2108 }
2109
2110 if (fast_clock) {
2111 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2112 rp_baud_base[i] = 921600;
2113 } else {
2114 /*
2115 * If support_low_speed is set, use the slow clock
2116 * prescale, which supports 50 bps
2117 */
2118 if (support_low_speed) {
2119 /* mod 9 (divide by 10) prescale */
2120 sClockPrescale = 0x19;
2121 rp_baud_base[i] = 230400;
2122 } else {
2123 /* mod 4 (divide by 5) prescale */
2124 sClockPrescale = 0x14;
2125 rp_baud_base[i] = 460800;
2126 }
2127 }
2128
2129 for (aiop = 0; aiop < max_num_aiops; aiop++)
2130 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2131 ctlp = sCtlNumToCtlPtr(i);
2132 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2133 for (aiop = 0; aiop < max_num_aiops; aiop++)
2134 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2135
2136 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2137 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2138 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2139 rocketModel[i].startingPortNumber,
2140 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2141
2142 if (num_aiops <= 0) {
2143 rcktpt_io_addr[i] = 0;
2144 return (0);
2145 }
2146 is_PCI[i] = 1;
2147
2148 /* Reset the AIOPIC, init the serial ports */
2149 for (aiop = 0; aiop < num_aiops; aiop++) {
2150 sResetAiopByNum(ctlp, aiop);
2151 num_chan = ports_per_aiop;
2152 for (chan = 0; chan < num_chan; chan++)
2153 init_r_port(i, aiop, chan, dev);
2154 }
2155
2156 /* Rocket modems must be reset */
2157 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2158 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2159 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2160 num_chan = ports_per_aiop;
2161 for (chan = 0; chan < num_chan; chan++)
2162 sPCIModemReset(ctlp, chan, 1);
2163 msleep(500);
2164 for (chan = 0; chan < num_chan; chan++)
2165 sPCIModemReset(ctlp, chan, 0);
2166 msleep(500);
2167 rmSpeakerReset(ctlp, rocketModel[i].model);
2168 }
2169 return (1);
2170}
2171
2172/*
2173 * Probes for PCI cards, inits them if found
2174 * Input: board_found = number of ISA boards already found, or the
2175 * starting board number
2176 * Returns: Number of PCI boards found
2177 */
2178static int __init init_PCI(int boards_found)
2179{
2180 struct pci_dev *dev = NULL;
2181 int count = 0;
2182
2183 /* Work through the PCI device list, pulling out ours */
2184 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2185 if (register_PCI(count + boards_found, dev))
2186 count++;
2187 }
2188 return (count);
2189}
2190
2191#endif /* CONFIG_PCI */
2192
2193/*
2194 * Probes for ISA cards
2195 * Input: i = the board number to look for
2196 * Returns: 1 if board found, 0 else
2197 */
2198static int __init init_ISA(int i)
2199{
2200 int num_aiops, num_chan = 0, total_num_chan = 0;
2201 int aiop, chan;
2202 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2203 CONTROLLER_t *ctlp;
2204 char *type_string;
2205
2206 /* If io_addr is zero, no board configured */
2207 if (rcktpt_io_addr[i] == 0)
2208 return (0);
2209
2210 /* Reserve the IO region */
2211 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2212 printk(KERN_ERR "Unable to reserve IO region for configured "
2213 "ISA RocketPort at address 0x%lx, board not "
2214 "installed...\n", rcktpt_io_addr[i]);
2215 rcktpt_io_addr[i] = 0;
2216 return (0);
2217 }
2218
2219 ctlp = sCtlNumToCtlPtr(i);
2220
2221 ctlp->boardType = rcktpt_type[i];
2222
2223 switch (rcktpt_type[i]) {
2224 case ROCKET_TYPE_PC104:
2225 type_string = "(PC104)";
2226 break;
2227 case ROCKET_TYPE_MODEM:
2228 type_string = "(RocketModem)";
2229 break;
2230 case ROCKET_TYPE_MODEMII:
2231 type_string = "(RocketModem II)";
2232 break;
2233 default:
2234 type_string = "";
2235 break;
2236 }
2237
2238 /*
2239 * If support_low_speed is set, use the slow clock prescale,
2240 * which supports 50 bps
2241 */
2242 if (support_low_speed) {
2243 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2244 rp_baud_base[i] = 230400;
2245 } else {
2246 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2247 rp_baud_base[i] = 460800;
2248 }
2249
2250 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2251 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2252
2253 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2254
2255 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2256 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2257 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2258 }
2259
2260 /* If something went wrong initing the AIOP's release the ISA IO memory */
2261 if (num_aiops <= 0) {
2262 release_region(rcktpt_io_addr[i], 64);
2263 rcktpt_io_addr[i] = 0;
2264 return (0);
2265 }
2266
2267 rocketModel[i].startingPortNumber = nextLineNumber;
2268
2269 for (aiop = 0; aiop < num_aiops; aiop++) {
2270 sResetAiopByNum(ctlp, aiop);
2271 sEnAiop(ctlp, aiop);
2272 num_chan = sGetAiopNumChan(ctlp, aiop);
2273 total_num_chan += num_chan;
2274 for (chan = 0; chan < num_chan; chan++)
2275 init_r_port(i, aiop, chan, NULL);
2276 }
2277 is_PCI[i] = 0;
2278 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2279 num_chan = sGetAiopNumChan(ctlp, 0);
2280 total_num_chan = num_chan;
2281 for (chan = 0; chan < num_chan; chan++)
2282 sModemReset(ctlp, chan, 1);
2283 msleep(500);
2284 for (chan = 0; chan < num_chan; chan++)
2285 sModemReset(ctlp, chan, 0);
2286 msleep(500);
2287 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2288 } else {
2289 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2290 }
2291 rocketModel[i].numPorts = total_num_chan;
2292 rocketModel[i].model = MODEL_ISA;
2293
2294 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2295 i, rcktpt_io_addr[i], num_aiops, type_string);
2296
2297 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2298 rocketModel[i].modelString,
2299 rocketModel[i].startingPortNumber,
2300 rocketModel[i].startingPortNumber +
2301 rocketModel[i].numPorts - 1);
2302
2303 return (1);
2304}
2305
2306static const struct tty_operations rocket_ops = {
2307 .open = rp_open,
2308 .close = rp_close,
2309 .write = rp_write,
2310 .put_char = rp_put_char,
2311 .write_room = rp_write_room,
2312 .chars_in_buffer = rp_chars_in_buffer,
2313 .flush_buffer = rp_flush_buffer,
2314 .ioctl = rp_ioctl,
2315 .throttle = rp_throttle,
2316 .unthrottle = rp_unthrottle,
2317 .set_termios = rp_set_termios,
2318 .stop = rp_stop,
2319 .start = rp_start,
2320 .hangup = rp_hangup,
2321 .break_ctl = rp_break,
2322 .send_xchar = rp_send_xchar,
2323 .wait_until_sent = rp_wait_until_sent,
2324 .tiocmget = rp_tiocmget,
2325 .tiocmset = rp_tiocmset,
2326};
2327
2328static const struct tty_port_operations rocket_port_ops = {
2329 .carrier_raised = carrier_raised,
2330 .dtr_rts = dtr_rts,
2331};
2332
2333/*
2334 * The module "startup" routine; it's run when the module is loaded.
2335 */
2336static int __init rp_init(void)
2337{
2338 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2339
2340 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2341 ROCKET_VERSION, ROCKET_DATE);
2342
2343 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2344 if (!rocket_driver)
2345 goto err;
2346
2347 /*
2348 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2349 * zero, use the default controller IO address of board1 + 0x40.
2350 */
2351 if (board1) {
2352 if (controller == 0)
2353 controller = board1 + 0x40;
2354 } else {
2355 controller = 0; /* Used as a flag, meaning no ISA boards */
2356 }
2357
2358 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2359 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2360 printk(KERN_ERR "Unable to reserve IO region for first "
2361 "configured ISA RocketPort controller 0x%lx. "
2362 "Driver exiting\n", controller);
2363 ret = -EBUSY;
2364 goto err_tty;
2365 }
2366
2367 /* Store ISA variable retrieved from command line or .conf file. */
2368 rcktpt_io_addr[0] = board1;
2369 rcktpt_io_addr[1] = board2;
2370 rcktpt_io_addr[2] = board3;
2371 rcktpt_io_addr[3] = board4;
2372
2373 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2374 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2375 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2376 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2377 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2378 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2379 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2380 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2381
2382 /*
2383 * Set up the tty driver structure and then register this
2384 * driver with the tty layer.
2385 */
2386
2387 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2388 rocket_driver->name = "ttyR";
2389 rocket_driver->driver_name = "Comtrol RocketPort";
2390 rocket_driver->major = TTY_ROCKET_MAJOR;
2391 rocket_driver->minor_start = 0;
2392 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2393 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2394 rocket_driver->init_termios = tty_std_termios;
2395 rocket_driver->init_termios.c_cflag =
2396 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2397 rocket_driver->init_termios.c_ispeed = 9600;
2398 rocket_driver->init_termios.c_ospeed = 9600;
2399#ifdef ROCKET_SOFT_FLOW
2400 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2401#endif
2402 tty_set_operations(rocket_driver, &rocket_ops);
2403
2404 ret = tty_register_driver(rocket_driver);
2405 if (ret < 0) {
2406 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2407 goto err_controller;
2408 }
2409
2410#ifdef ROCKET_DEBUG_OPEN
2411 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2412#endif
2413
2414 /*
2415 * OK, let's probe each of the controllers looking for boards. Any boards found
2416 * will be initialized here.
2417 */
2418 isa_boards_found = 0;
2419 pci_boards_found = 0;
2420
2421 for (i = 0; i < NUM_BOARDS; i++) {
2422 if (init_ISA(i))
2423 isa_boards_found++;
2424 }
2425
2426#ifdef CONFIG_PCI
2427 if (isa_boards_found < NUM_BOARDS)
2428 pci_boards_found = init_PCI(isa_boards_found);
2429#endif
2430
2431 max_board = pci_boards_found + isa_boards_found;
2432
2433 if (max_board == 0) {
2434 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2435 ret = -ENXIO;
2436 goto err_ttyu;
2437 }
2438
2439 return 0;
2440err_ttyu:
2441 tty_unregister_driver(rocket_driver);
2442err_controller:
2443 if (controller)
2444 release_region(controller, 4);
2445err_tty:
2446 put_tty_driver(rocket_driver);
2447err:
2448 return ret;
2449}
2450
2451
2452static void rp_cleanup_module(void)
2453{
2454 int retval;
2455 int i;
2456
2457 del_timer_sync(&rocket_timer);
2458
2459 retval = tty_unregister_driver(rocket_driver);
2460 if (retval)
2461 printk(KERN_ERR "Error %d while trying to unregister "
2462 "rocketport driver\n", -retval);
2463
2464 for (i = 0; i < MAX_RP_PORTS; i++)
2465 if (rp_table[i]) {
2466 tty_unregister_device(rocket_driver, i);
2467 tty_port_destroy(&rp_table[i]->port);
2468 kfree(rp_table[i]);
2469 }
2470
2471 put_tty_driver(rocket_driver);
2472
2473 for (i = 0; i < NUM_BOARDS; i++) {
2474 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2475 continue;
2476 release_region(rcktpt_io_addr[i], 64);
2477 }
2478 if (controller)
2479 release_region(controller, 4);
2480}
2481
2482/***************************************************************************
2483Function: sInitController
2484Purpose: Initialization of controller global registers and controller
2485 structure.
2486Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2487 IRQNum,Frequency,PeriodicOnly)
2488 CONTROLLER_T *CtlP; Ptr to controller structure
2489 int CtlNum; Controller number
2490 ByteIO_t MudbacIO; Mudbac base I/O address.
2491 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2492 This list must be in the order the AIOPs will be found on the
2493 controller. Once an AIOP in the list is not found, it is
2494 assumed that there are no more AIOPs on the controller.
2495 int AiopIOListSize; Number of addresses in AiopIOList
2496 int IRQNum; Interrupt Request number. Can be any of the following:
2497 0: Disable global interrupts
2498 3: IRQ 3
2499 4: IRQ 4
2500 5: IRQ 5
2501 9: IRQ 9
2502 10: IRQ 10
2503 11: IRQ 11
2504 12: IRQ 12
2505 15: IRQ 15
2506 Byte_t Frequency: A flag identifying the frequency
2507 of the periodic interrupt, can be any one of the following:
2508 FREQ_DIS - periodic interrupt disabled
2509 FREQ_137HZ - 137 Hertz
2510 FREQ_69HZ - 69 Hertz
2511 FREQ_34HZ - 34 Hertz
2512 FREQ_17HZ - 17 Hertz
2513 FREQ_9HZ - 9 Hertz
2514 FREQ_4HZ - 4 Hertz
2515 If IRQNum is set to 0 the Frequency parameter is
2516 overidden, it is forced to a value of FREQ_DIS.
2517 int PeriodicOnly: 1 if all interrupts except the periodic
2518 interrupt are to be blocked.
2519 0 is both the periodic interrupt and
2520 other channel interrupts are allowed.
2521 If IRQNum is set to 0 the PeriodicOnly parameter is
2522 overidden, it is forced to a value of 0.
2523Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2524 initialization failed.
2525
2526Comments:
2527 If periodic interrupts are to be disabled but AIOP interrupts
2528 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2529
2530 If interrupts are to be completely disabled set IRQNum to 0.
2531
2532 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2533 invalid combination.
2534
2535 This function performs initialization of global interrupt modes,
2536 but it does not actually enable global interrupts. To enable
2537 and disable global interrupts use functions sEnGlobalInt() and
2538 sDisGlobalInt(). Enabling of global interrupts is normally not
2539 done until all other initializations are complete.
2540
2541 Even if interrupts are globally enabled, they must also be
2542 individually enabled for each channel that is to generate
2543 interrupts.
2544
2545Warnings: No range checking on any of the parameters is done.
2546
2547 No context switches are allowed while executing this function.
2548
2549 After this function all AIOPs on the controller are disabled,
2550 they can be enabled with sEnAiop().
2551*/
2552static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2553 ByteIO_t * AiopIOList, int AiopIOListSize,
2554 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2555{
2556 int i;
2557 ByteIO_t io;
2558 int done;
2559
2560 CtlP->AiopIntrBits = aiop_intr_bits;
2561 CtlP->AltChanRingIndicator = 0;
2562 CtlP->CtlNum = CtlNum;
2563 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2564 CtlP->BusType = isISA;
2565 CtlP->MBaseIO = MudbacIO;
2566 CtlP->MReg1IO = MudbacIO + 1;
2567 CtlP->MReg2IO = MudbacIO + 2;
2568 CtlP->MReg3IO = MudbacIO + 3;
2569#if 1
2570 CtlP->MReg2 = 0; /* interrupt disable */
2571 CtlP->MReg3 = 0; /* no periodic interrupts */
2572#else
2573 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2574 CtlP->MReg2 = 0; /* interrupt disable */
2575 CtlP->MReg3 = 0; /* no periodic interrupts */
2576 } else {
2577 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2578 CtlP->MReg3 = Frequency; /* set frequency */
2579 if (PeriodicOnly) { /* periodic interrupt only */
2580 CtlP->MReg3 |= PERIODIC_ONLY;
2581 }
2582 }
2583#endif
2584 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2585 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2586 sControllerEOI(CtlP); /* clear EOI if warm init */
2587 /* Init AIOPs */
2588 CtlP->NumAiop = 0;
2589 for (i = done = 0; i < AiopIOListSize; i++) {
2590 io = AiopIOList[i];
2591 CtlP->AiopIO[i] = (WordIO_t) io;
2592 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2593 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2594 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2595 if (done)
2596 continue;
2597 sEnAiop(CtlP, i); /* enable the AIOP */
2598 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2599 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2600 done = 1; /* done looking for AIOPs */
2601 else {
2602 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2603 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2604 sOutB(io + _INDX_DATA, sClockPrescale);
2605 CtlP->NumAiop++; /* bump count of AIOPs */
2606 }
2607 sDisAiop(CtlP, i); /* disable AIOP */
2608 }
2609
2610 if (CtlP->NumAiop == 0)
2611 return (-1);
2612 else
2613 return (CtlP->NumAiop);
2614}
2615
2616/***************************************************************************
2617Function: sReadAiopID
2618Purpose: Read the AIOP idenfication number directly from an AIOP.
2619Call: sReadAiopID(io)
2620 ByteIO_t io: AIOP base I/O address
2621Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2622 is replace by an identifying number.
2623 Flag AIOPID_NULL if no valid AIOP is found
2624Warnings: No context switches are allowed while executing this function.
2625
2626*/
2627static int sReadAiopID(ByteIO_t io)
2628{
2629 Byte_t AiopID; /* ID byte from AIOP */
2630
2631 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2632 sOutB(io + _CMD_REG, 0x0);
2633 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2634 if (AiopID == 0x06)
2635 return (1);
2636 else /* AIOP does not exist */
2637 return (-1);
2638}
2639
2640/***************************************************************************
2641Function: sReadAiopNumChan
2642Purpose: Read the number of channels available in an AIOP directly from
2643 an AIOP.
2644Call: sReadAiopNumChan(io)
2645 WordIO_t io: AIOP base I/O address
2646Return: int: The number of channels available
2647Comments: The number of channels is determined by write/reads from identical
2648 offsets within the SRAM address spaces for channels 0 and 4.
2649 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2650 AIOP, otherwise it is an 8 channel.
2651Warnings: No context switches are allowed while executing this function.
2652*/
2653static int sReadAiopNumChan(WordIO_t io)
2654{
2655 Word_t x;
2656 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2657
2658 /* write to chan 0 SRAM */
2659 out32((DWordIO_t) io + _INDX_ADDR, R);
2660 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2661 x = sInW(io + _INDX_DATA);
2662 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2663 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2664 return (8);
2665 else
2666 return (4);
2667}
2668
2669/***************************************************************************
2670Function: sInitChan
2671Purpose: Initialization of a channel and channel structure
2672Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2673 CONTROLLER_T *CtlP; Ptr to controller structure
2674 CHANNEL_T *ChP; Ptr to channel structure
2675 int AiopNum; AIOP number within controller
2676 int ChanNum; Channel number within AIOP
2677Return: int: 1 if initialization succeeded, 0 if it fails because channel
2678 number exceeds number of channels available in AIOP.
2679Comments: This function must be called before a channel can be used.
2680Warnings: No range checking on any of the parameters is done.
2681
2682 No context switches are allowed while executing this function.
2683*/
2684static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2685 int ChanNum)
2686{
2687 int i;
2688 WordIO_t AiopIO;
2689 WordIO_t ChIOOff;
2690 Byte_t *ChR;
2691 Word_t ChOff;
2692 static Byte_t R[4];
2693 int brd9600;
2694
2695 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2696 return 0; /* exceeds num chans in AIOP */
2697
2698 /* Channel, AIOP, and controller identifiers */
2699 ChP->CtlP = CtlP;
2700 ChP->ChanID = CtlP->AiopID[AiopNum];
2701 ChP->AiopNum = AiopNum;
2702 ChP->ChanNum = ChanNum;
2703
2704 /* Global direct addresses */
2705 AiopIO = CtlP->AiopIO[AiopNum];
2706 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2707 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2708 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2709 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2710 ChP->IndexData = AiopIO + _INDX_DATA;
2711
2712 /* Channel direct addresses */
2713 ChIOOff = AiopIO + ChP->ChanNum * 2;
2714 ChP->TxRxData = ChIOOff + _TD0;
2715 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2716 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2717 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2718
2719 /* Initialize the channel from the RData array */
2720 for (i = 0; i < RDATASIZE; i += 4) {
2721 R[0] = RData[i];
2722 R[1] = RData[i + 1] + 0x10 * ChanNum;
2723 R[2] = RData[i + 2];
2724 R[3] = RData[i + 3];
2725 out32(ChP->IndexAddr, R);
2726 }
2727
2728 ChR = ChP->R;
2729 for (i = 0; i < RREGDATASIZE; i += 4) {
2730 ChR[i] = RRegData[i];
2731 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2732 ChR[i + 2] = RRegData[i + 2];
2733 ChR[i + 3] = RRegData[i + 3];
2734 }
2735
2736 /* Indexed registers */
2737 ChOff = (Word_t) ChanNum *0x1000;
2738
2739 if (sClockPrescale == 0x14)
2740 brd9600 = 47;
2741 else
2742 brd9600 = 23;
2743
2744 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2745 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2746 ChP->BaudDiv[2] = (Byte_t) brd9600;
2747 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2748 out32(ChP->IndexAddr, ChP->BaudDiv);
2749
2750 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2751 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2752 ChP->TxControl[2] = 0;
2753 ChP->TxControl[3] = 0;
2754 out32(ChP->IndexAddr, ChP->TxControl);
2755
2756 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2757 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2758 ChP->RxControl[2] = 0;
2759 ChP->RxControl[3] = 0;
2760 out32(ChP->IndexAddr, ChP->RxControl);
2761
2762 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2763 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2764 ChP->TxEnables[2] = 0;
2765 ChP->TxEnables[3] = 0;
2766 out32(ChP->IndexAddr, ChP->TxEnables);
2767
2768 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2769 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2770 ChP->TxCompare[2] = 0;
2771 ChP->TxCompare[3] = 0;
2772 out32(ChP->IndexAddr, ChP->TxCompare);
2773
2774 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2775 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2776 ChP->TxReplace1[2] = 0;
2777 ChP->TxReplace1[3] = 0;
2778 out32(ChP->IndexAddr, ChP->TxReplace1);
2779
2780 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2781 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2782 ChP->TxReplace2[2] = 0;
2783 ChP->TxReplace2[3] = 0;
2784 out32(ChP->IndexAddr, ChP->TxReplace2);
2785
2786 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2787 ChP->TxFIFO = ChOff + _TX_FIFO;
2788
2789 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2790 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2791 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2792 sOutW(ChP->IndexData, 0);
2793 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2794 ChP->RxFIFO = ChOff + _RX_FIFO;
2795
2796 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2797 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2798 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2799 sOutW(ChP->IndexData, 0);
2800 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2801 sOutW(ChP->IndexData, 0);
2802 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2803 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2804 sOutB(ChP->IndexData, 0);
2805 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2806 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2807 sOutB(ChP->IndexData, 0);
2808 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2809 sEnRxProcessor(ChP); /* start the Rx processor */
2810
2811 return 1;
2812}
2813
2814/***************************************************************************
2815Function: sStopRxProcessor
2816Purpose: Stop the receive processor from processing a channel.
2817Call: sStopRxProcessor(ChP)
2818 CHANNEL_T *ChP; Ptr to channel structure
2819
2820Comments: The receive processor can be started again with sStartRxProcessor().
2821 This function causes the receive processor to skip over the
2822 stopped channel. It does not stop it from processing other channels.
2823
2824Warnings: No context switches are allowed while executing this function.
2825
2826 Do not leave the receive processor stopped for more than one
2827 character time.
2828
2829 After calling this function a delay of 4 uS is required to ensure
2830 that the receive processor is no longer processing this channel.
2831*/
2832static void sStopRxProcessor(CHANNEL_T * ChP)
2833{
2834 Byte_t R[4];
2835
2836 R[0] = ChP->R[0];
2837 R[1] = ChP->R[1];
2838 R[2] = 0x0a;
2839 R[3] = ChP->R[3];
2840 out32(ChP->IndexAddr, R);
2841}
2842
2843/***************************************************************************
2844Function: sFlushRxFIFO
2845Purpose: Flush the Rx FIFO
2846Call: sFlushRxFIFO(ChP)
2847 CHANNEL_T *ChP; Ptr to channel structure
2848Return: void
2849Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2850 while it is being flushed the receive processor is stopped
2851 and the transmitter is disabled. After these operations a
2852 4 uS delay is done before clearing the pointers to allow
2853 the receive processor to stop. These items are handled inside
2854 this function.
2855Warnings: No context switches are allowed while executing this function.
2856*/
2857static void sFlushRxFIFO(CHANNEL_T * ChP)
2858{
2859 int i;
2860 Byte_t Ch; /* channel number within AIOP */
2861 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2862
2863 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2864 return; /* don't need to flush */
2865
2866 RxFIFOEnabled = 0;
2867 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2868 RxFIFOEnabled = 1;
2869 sDisRxFIFO(ChP); /* disable it */
2870 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2871 sInB(ChP->IntChan); /* depends on bus i/o timing */
2872 }
2873 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2874 Ch = (Byte_t) sGetChanNum(ChP);
2875 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2876 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2877 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2878 sOutW(ChP->IndexData, 0);
2879 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2880 sOutW(ChP->IndexData, 0);
2881 if (RxFIFOEnabled)
2882 sEnRxFIFO(ChP); /* enable Rx FIFO */
2883}
2884
2885/***************************************************************************
2886Function: sFlushTxFIFO
2887Purpose: Flush the Tx FIFO
2888Call: sFlushTxFIFO(ChP)
2889 CHANNEL_T *ChP; Ptr to channel structure
2890Return: void
2891Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2892 while it is being flushed the receive processor is stopped
2893 and the transmitter is disabled. After these operations a
2894 4 uS delay is done before clearing the pointers to allow
2895 the receive processor to stop. These items are handled inside
2896 this function.
2897Warnings: No context switches are allowed while executing this function.
2898*/
2899static void sFlushTxFIFO(CHANNEL_T * ChP)
2900{
2901 int i;
2902 Byte_t Ch; /* channel number within AIOP */
2903 int TxEnabled; /* 1 if transmitter enabled */
2904
2905 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2906 return; /* don't need to flush */
2907
2908 TxEnabled = 0;
2909 if (ChP->TxControl[3] & TX_ENABLE) {
2910 TxEnabled = 1;
2911 sDisTransmit(ChP); /* disable transmitter */
2912 }
2913 sStopRxProcessor(ChP); /* stop Rx processor */
2914 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2915 sInB(ChP->IntChan); /* depends on bus i/o timing */
2916 Ch = (Byte_t) sGetChanNum(ChP);
2917 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2918 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2919 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2920 sOutW(ChP->IndexData, 0);
2921 if (TxEnabled)
2922 sEnTransmit(ChP); /* enable transmitter */
2923 sStartRxProcessor(ChP); /* restart Rx processor */
2924}
2925
2926/***************************************************************************
2927Function: sWriteTxPrioByte
2928Purpose: Write a byte of priority transmit data to a channel
2929Call: sWriteTxPrioByte(ChP,Data)
2930 CHANNEL_T *ChP; Ptr to channel structure
2931 Byte_t Data; The transmit data byte
2932
2933Return: int: 1 if the bytes is successfully written, otherwise 0.
2934
2935Comments: The priority byte is transmitted before any data in the Tx FIFO.
2936
2937Warnings: No context switches are allowed while executing this function.
2938*/
2939static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2940{
2941 Byte_t DWBuf[4]; /* buffer for double word writes */
2942 Word_t *WordPtr; /* must be far because Win SS != DS */
2943 register DWordIO_t IndexAddr;
2944
2945 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2946 IndexAddr = ChP->IndexAddr;
2947 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2948 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2949 return (0); /* nothing sent */
2950
2951 WordPtr = (Word_t *) (&DWBuf[0]);
2952 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2953
2954 DWBuf[2] = Data; /* data byte value */
2955 out32(IndexAddr, DWBuf); /* write it out */
2956
2957 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2958
2959 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2960 DWBuf[3] = 0; /* priority buffer pointer */
2961 out32(IndexAddr, DWBuf); /* write it out */
2962 } else { /* write it to Tx FIFO */
2963
2964 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2965 }
2966 return (1); /* 1 byte sent */
2967}
2968
2969/***************************************************************************
2970Function: sEnInterrupts
2971Purpose: Enable one or more interrupts for a channel
2972Call: sEnInterrupts(ChP,Flags)
2973 CHANNEL_T *ChP; Ptr to channel structure
2974 Word_t Flags: Interrupt enable flags, can be any combination
2975 of the following flags:
2976 TXINT_EN: Interrupt on Tx FIFO empty
2977 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
2978 sSetRxTrigger())
2979 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
2980 MCINT_EN: Interrupt on modem input change
2981 CHANINT_EN: Allow channel interrupt signal to the AIOP's
2982 Interrupt Channel Register.
2983Return: void
2984Comments: If an interrupt enable flag is set in Flags, that interrupt will be
2985 enabled. If an interrupt enable flag is not set in Flags, that
2986 interrupt will not be changed. Interrupts can be disabled with
2987 function sDisInterrupts().
2988
2989 This function sets the appropriate bit for the channel in the AIOP's
2990 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
2991 this channel's bit to be set in the AIOP's Interrupt Channel Register.
2992
2993 Interrupts must also be globally enabled before channel interrupts
2994 will be passed on to the host. This is done with function
2995 sEnGlobalInt().
2996
2997 In some cases it may be desirable to disable interrupts globally but
2998 enable channel interrupts. This would allow the global interrupt
2999 status register to be used to determine which AIOPs need service.
3000*/
3001static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3002{
3003 Byte_t Mask; /* Interrupt Mask Register */
3004
3005 ChP->RxControl[2] |=
3006 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3007
3008 out32(ChP->IndexAddr, ChP->RxControl);
3009
3010 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3011
3012 out32(ChP->IndexAddr, ChP->TxControl);
3013
3014 if (Flags & CHANINT_EN) {
3015 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3016 sOutB(ChP->IntMask, Mask);
3017 }
3018}
3019
3020/***************************************************************************
3021Function: sDisInterrupts
3022Purpose: Disable one or more interrupts for a channel
3023Call: sDisInterrupts(ChP,Flags)
3024 CHANNEL_T *ChP; Ptr to channel structure
3025 Word_t Flags: Interrupt flags, can be any combination
3026 of the following flags:
3027 TXINT_EN: Interrupt on Tx FIFO empty
3028 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3029 sSetRxTrigger())
3030 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3031 MCINT_EN: Interrupt on modem input change
3032 CHANINT_EN: Disable channel interrupt signal to the
3033 AIOP's Interrupt Channel Register.
3034Return: void
3035Comments: If an interrupt flag is set in Flags, that interrupt will be
3036 disabled. If an interrupt flag is not set in Flags, that
3037 interrupt will not be changed. Interrupts can be enabled with
3038 function sEnInterrupts().
3039
3040 This function clears the appropriate bit for the channel in the AIOP's
3041 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3042 this channel's bit from being set in the AIOP's Interrupt Channel
3043 Register.
3044*/
3045static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3046{
3047 Byte_t Mask; /* Interrupt Mask Register */
3048
3049 ChP->RxControl[2] &=
3050 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3051 out32(ChP->IndexAddr, ChP->RxControl);
3052 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3053 out32(ChP->IndexAddr, ChP->TxControl);
3054
3055 if (Flags & CHANINT_EN) {
3056 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3057 sOutB(ChP->IntMask, Mask);
3058 }
3059}
3060
3061static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3062{
3063 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3064}
3065
3066/*
3067 * Not an official SSCI function, but how to reset RocketModems.
3068 * ISA bus version
3069 */
3070static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3071{
3072 ByteIO_t addr;
3073 Byte_t val;
3074
3075 addr = CtlP->AiopIO[0] + 0x400;
3076 val = sInB(CtlP->MReg3IO);
3077 /* if AIOP[1] is not enabled, enable it */
3078 if ((val & 2) == 0) {
3079 val = sInB(CtlP->MReg2IO);
3080 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3081 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3082 }
3083
3084 sEnAiop(CtlP, 1);
3085 if (!on)
3086 addr += 8;
3087 sOutB(addr + chan, 0); /* apply or remove reset */
3088 sDisAiop(CtlP, 1);
3089}
3090
3091/*
3092 * Not an official SSCI function, but how to reset RocketModems.
3093 * PCI bus version
3094 */
3095static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3096{
3097 ByteIO_t addr;
3098
3099 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3100 if (!on)
3101 addr += 8;
3102 sOutB(addr + chan, 0); /* apply or remove reset */
3103}
3104
3105/* Returns the line number given the controller (board), aiop and channel number */
3106static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3107{
3108 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3109}
3110
3111/*
3112 * Stores the line number associated with a given controller (board), aiop
3113 * and channel number.
3114 * Returns: The line number assigned
3115 */
3116static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3117{
3118 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3119 return (nextLineNumber - 1);
3120}