Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
4 *
5 * Copyright (c) 2009-2010 Micrel, Inc.
6 * Tristram Ha <Tristram.Ha@micrel.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18#include <linux/mii.h>
19#include <linux/platform_device.h>
20#include <linux/ethtool.h>
21#include <linux/etherdevice.h>
22#include <linux/in.h>
23#include <linux/ip.h>
24#include <linux/if_vlan.h>
25#include <linux/crc32.h>
26#include <linux/sched.h>
27#include <linux/slab.h>
28#include <linux/micrel_phy.h>
29
30
31/* DMA Registers */
32
33#define KS_DMA_TX_CTRL 0x0000
34#define DMA_TX_ENABLE 0x00000001
35#define DMA_TX_CRC_ENABLE 0x00000002
36#define DMA_TX_PAD_ENABLE 0x00000004
37#define DMA_TX_LOOPBACK 0x00000100
38#define DMA_TX_FLOW_ENABLE 0x00000200
39#define DMA_TX_CSUM_IP 0x00010000
40#define DMA_TX_CSUM_TCP 0x00020000
41#define DMA_TX_CSUM_UDP 0x00040000
42#define DMA_TX_BURST_SIZE 0x3F000000
43
44#define KS_DMA_RX_CTRL 0x0004
45#define DMA_RX_ENABLE 0x00000001
46#define KS884X_DMA_RX_MULTICAST 0x00000002
47#define DMA_RX_PROMISCUOUS 0x00000004
48#define DMA_RX_ERROR 0x00000008
49#define DMA_RX_UNICAST 0x00000010
50#define DMA_RX_ALL_MULTICAST 0x00000020
51#define DMA_RX_BROADCAST 0x00000040
52#define DMA_RX_FLOW_ENABLE 0x00000200
53#define DMA_RX_CSUM_IP 0x00010000
54#define DMA_RX_CSUM_TCP 0x00020000
55#define DMA_RX_CSUM_UDP 0x00040000
56#define DMA_RX_BURST_SIZE 0x3F000000
57
58#define DMA_BURST_SHIFT 24
59#define DMA_BURST_DEFAULT 8
60
61#define KS_DMA_TX_START 0x0008
62#define KS_DMA_RX_START 0x000C
63#define DMA_START 0x00000001
64
65#define KS_DMA_TX_ADDR 0x0010
66#define KS_DMA_RX_ADDR 0x0014
67
68#define DMA_ADDR_LIST_MASK 0xFFFFFFFC
69#define DMA_ADDR_LIST_SHIFT 2
70
71/* MTR0 */
72#define KS884X_MULTICAST_0_OFFSET 0x0020
73#define KS884X_MULTICAST_1_OFFSET 0x0021
74#define KS884X_MULTICAST_2_OFFSET 0x0022
75#define KS884x_MULTICAST_3_OFFSET 0x0023
76/* MTR1 */
77#define KS884X_MULTICAST_4_OFFSET 0x0024
78#define KS884X_MULTICAST_5_OFFSET 0x0025
79#define KS884X_MULTICAST_6_OFFSET 0x0026
80#define KS884X_MULTICAST_7_OFFSET 0x0027
81
82/* Interrupt Registers */
83
84/* INTEN */
85#define KS884X_INTERRUPTS_ENABLE 0x0028
86/* INTST */
87#define KS884X_INTERRUPTS_STATUS 0x002C
88
89#define KS884X_INT_RX_STOPPED 0x02000000
90#define KS884X_INT_TX_STOPPED 0x04000000
91#define KS884X_INT_RX_OVERRUN 0x08000000
92#define KS884X_INT_TX_EMPTY 0x10000000
93#define KS884X_INT_RX 0x20000000
94#define KS884X_INT_TX 0x40000000
95#define KS884X_INT_PHY 0x80000000
96
97#define KS884X_INT_RX_MASK \
98 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
99#define KS884X_INT_TX_MASK \
100 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
101#define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
102
103/* MAC Additional Station Address */
104
105/* MAAL0 */
106#define KS_ADD_ADDR_0_LO 0x0080
107/* MAAH0 */
108#define KS_ADD_ADDR_0_HI 0x0084
109/* MAAL1 */
110#define KS_ADD_ADDR_1_LO 0x0088
111/* MAAH1 */
112#define KS_ADD_ADDR_1_HI 0x008C
113/* MAAL2 */
114#define KS_ADD_ADDR_2_LO 0x0090
115/* MAAH2 */
116#define KS_ADD_ADDR_2_HI 0x0094
117/* MAAL3 */
118#define KS_ADD_ADDR_3_LO 0x0098
119/* MAAH3 */
120#define KS_ADD_ADDR_3_HI 0x009C
121/* MAAL4 */
122#define KS_ADD_ADDR_4_LO 0x00A0
123/* MAAH4 */
124#define KS_ADD_ADDR_4_HI 0x00A4
125/* MAAL5 */
126#define KS_ADD_ADDR_5_LO 0x00A8
127/* MAAH5 */
128#define KS_ADD_ADDR_5_HI 0x00AC
129/* MAAL6 */
130#define KS_ADD_ADDR_6_LO 0x00B0
131/* MAAH6 */
132#define KS_ADD_ADDR_6_HI 0x00B4
133/* MAAL7 */
134#define KS_ADD_ADDR_7_LO 0x00B8
135/* MAAH7 */
136#define KS_ADD_ADDR_7_HI 0x00BC
137/* MAAL8 */
138#define KS_ADD_ADDR_8_LO 0x00C0
139/* MAAH8 */
140#define KS_ADD_ADDR_8_HI 0x00C4
141/* MAAL9 */
142#define KS_ADD_ADDR_9_LO 0x00C8
143/* MAAH9 */
144#define KS_ADD_ADDR_9_HI 0x00CC
145/* MAAL10 */
146#define KS_ADD_ADDR_A_LO 0x00D0
147/* MAAH10 */
148#define KS_ADD_ADDR_A_HI 0x00D4
149/* MAAL11 */
150#define KS_ADD_ADDR_B_LO 0x00D8
151/* MAAH11 */
152#define KS_ADD_ADDR_B_HI 0x00DC
153/* MAAL12 */
154#define KS_ADD_ADDR_C_LO 0x00E0
155/* MAAH12 */
156#define KS_ADD_ADDR_C_HI 0x00E4
157/* MAAL13 */
158#define KS_ADD_ADDR_D_LO 0x00E8
159/* MAAH13 */
160#define KS_ADD_ADDR_D_HI 0x00EC
161/* MAAL14 */
162#define KS_ADD_ADDR_E_LO 0x00F0
163/* MAAH14 */
164#define KS_ADD_ADDR_E_HI 0x00F4
165/* MAAL15 */
166#define KS_ADD_ADDR_F_LO 0x00F8
167/* MAAH15 */
168#define KS_ADD_ADDR_F_HI 0x00FC
169
170#define ADD_ADDR_HI_MASK 0x0000FFFF
171#define ADD_ADDR_ENABLE 0x80000000
172#define ADD_ADDR_INCR 8
173
174/* Miscellaneous Registers */
175
176/* MARL */
177#define KS884X_ADDR_0_OFFSET 0x0200
178#define KS884X_ADDR_1_OFFSET 0x0201
179/* MARM */
180#define KS884X_ADDR_2_OFFSET 0x0202
181#define KS884X_ADDR_3_OFFSET 0x0203
182/* MARH */
183#define KS884X_ADDR_4_OFFSET 0x0204
184#define KS884X_ADDR_5_OFFSET 0x0205
185
186/* OBCR */
187#define KS884X_BUS_CTRL_OFFSET 0x0210
188
189#define BUS_SPEED_125_MHZ 0x0000
190#define BUS_SPEED_62_5_MHZ 0x0001
191#define BUS_SPEED_41_66_MHZ 0x0002
192#define BUS_SPEED_25_MHZ 0x0003
193
194/* EEPCR */
195#define KS884X_EEPROM_CTRL_OFFSET 0x0212
196
197#define EEPROM_CHIP_SELECT 0x0001
198#define EEPROM_SERIAL_CLOCK 0x0002
199#define EEPROM_DATA_OUT 0x0004
200#define EEPROM_DATA_IN 0x0008
201#define EEPROM_ACCESS_ENABLE 0x0010
202
203/* MBIR */
204#define KS884X_MEM_INFO_OFFSET 0x0214
205
206#define RX_MEM_TEST_FAILED 0x0008
207#define RX_MEM_TEST_FINISHED 0x0010
208#define TX_MEM_TEST_FAILED 0x0800
209#define TX_MEM_TEST_FINISHED 0x1000
210
211/* GCR */
212#define KS884X_GLOBAL_CTRL_OFFSET 0x0216
213#define GLOBAL_SOFTWARE_RESET 0x0001
214
215#define KS8841_POWER_MANAGE_OFFSET 0x0218
216
217/* WFCR */
218#define KS8841_WOL_CTRL_OFFSET 0x021A
219#define KS8841_WOL_MAGIC_ENABLE 0x0080
220#define KS8841_WOL_FRAME3_ENABLE 0x0008
221#define KS8841_WOL_FRAME2_ENABLE 0x0004
222#define KS8841_WOL_FRAME1_ENABLE 0x0002
223#define KS8841_WOL_FRAME0_ENABLE 0x0001
224
225/* WF0 */
226#define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
227#define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
228#define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
229
230/* IACR */
231#define KS884X_IACR_P 0x04A0
232#define KS884X_IACR_OFFSET KS884X_IACR_P
233
234/* IADR1 */
235#define KS884X_IADR1_P 0x04A2
236#define KS884X_IADR2_P 0x04A4
237#define KS884X_IADR3_P 0x04A6
238#define KS884X_IADR4_P 0x04A8
239#define KS884X_IADR5_P 0x04AA
240
241#define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
242#define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
243
244#define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
245#define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
246#define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
247#define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
248#define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
249#define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
250#define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
251#define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
252#define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
253
254/* P1MBCR */
255#define KS884X_P1MBCR_P 0x04D0
256#define KS884X_P1MBSR_P 0x04D2
257#define KS884X_PHY1ILR_P 0x04D4
258#define KS884X_PHY1IHR_P 0x04D6
259#define KS884X_P1ANAR_P 0x04D8
260#define KS884X_P1ANLPR_P 0x04DA
261
262/* P2MBCR */
263#define KS884X_P2MBCR_P 0x04E0
264#define KS884X_P2MBSR_P 0x04E2
265#define KS884X_PHY2ILR_P 0x04E4
266#define KS884X_PHY2IHR_P 0x04E6
267#define KS884X_P2ANAR_P 0x04E8
268#define KS884X_P2ANLPR_P 0x04EA
269
270#define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
271#define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
272
273#define KS884X_PHY_CTRL_OFFSET 0x00
274
275#define KS884X_PHY_STATUS_OFFSET 0x02
276
277#define KS884X_PHY_ID_1_OFFSET 0x04
278#define KS884X_PHY_ID_2_OFFSET 0x06
279
280#define KS884X_PHY_AUTO_NEG_OFFSET 0x08
281
282#define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
283
284/* P1VCT */
285#define KS884X_P1VCT_P 0x04F0
286#define KS884X_P1PHYCTRL_P 0x04F2
287
288/* P2VCT */
289#define KS884X_P2VCT_P 0x04F4
290#define KS884X_P2PHYCTRL_P 0x04F6
291
292#define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
293#define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
294
295#define KS884X_PHY_LINK_MD_OFFSET 0x00
296
297#define PHY_START_CABLE_DIAG 0x8000
298#define PHY_CABLE_DIAG_RESULT 0x6000
299#define PHY_CABLE_STAT_NORMAL 0x0000
300#define PHY_CABLE_STAT_OPEN 0x2000
301#define PHY_CABLE_STAT_SHORT 0x4000
302#define PHY_CABLE_STAT_FAILED 0x6000
303#define PHY_CABLE_10M_SHORT 0x1000
304#define PHY_CABLE_FAULT_COUNTER 0x01FF
305
306#define KS884X_PHY_PHY_CTRL_OFFSET 0x02
307
308#define PHY_STAT_REVERSED_POLARITY 0x0020
309#define PHY_STAT_MDIX 0x0010
310#define PHY_FORCE_LINK 0x0008
311#define PHY_POWER_SAVING_DISABLE 0x0004
312#define PHY_REMOTE_LOOPBACK 0x0002
313
314/* SIDER */
315#define KS884X_SIDER_P 0x0400
316#define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
317#define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
318
319#define REG_FAMILY_ID 0x88
320
321#define REG_CHIP_ID_41 0x8810
322#define REG_CHIP_ID_42 0x8800
323
324#define KS884X_CHIP_ID_MASK_41 0xFF10
325#define KS884X_CHIP_ID_MASK 0xFFF0
326#define KS884X_CHIP_ID_SHIFT 4
327#define KS884X_REVISION_MASK 0x000E
328#define KS884X_REVISION_SHIFT 1
329#define KS8842_START 0x0001
330
331#define CHIP_IP_41_M 0x8810
332#define CHIP_IP_42_M 0x8800
333#define CHIP_IP_61_M 0x8890
334#define CHIP_IP_62_M 0x8880
335
336#define CHIP_IP_41_P 0x8850
337#define CHIP_IP_42_P 0x8840
338#define CHIP_IP_61_P 0x88D0
339#define CHIP_IP_62_P 0x88C0
340
341/* SGCR1 */
342#define KS8842_SGCR1_P 0x0402
343#define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
344
345#define SWITCH_PASS_ALL 0x8000
346#define SWITCH_TX_FLOW_CTRL 0x2000
347#define SWITCH_RX_FLOW_CTRL 0x1000
348#define SWITCH_CHECK_LENGTH 0x0800
349#define SWITCH_AGING_ENABLE 0x0400
350#define SWITCH_FAST_AGING 0x0200
351#define SWITCH_AGGR_BACKOFF 0x0100
352#define SWITCH_PASS_PAUSE 0x0008
353#define SWITCH_LINK_AUTO_AGING 0x0001
354
355/* SGCR2 */
356#define KS8842_SGCR2_P 0x0404
357#define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
358
359#define SWITCH_VLAN_ENABLE 0x8000
360#define SWITCH_IGMP_SNOOP 0x4000
361#define IPV6_MLD_SNOOP_ENABLE 0x2000
362#define IPV6_MLD_SNOOP_OPTION 0x1000
363#define PRIORITY_SCHEME_SELECT 0x0800
364#define SWITCH_MIRROR_RX_TX 0x0100
365#define UNICAST_VLAN_BOUNDARY 0x0080
366#define MULTICAST_STORM_DISABLE 0x0040
367#define SWITCH_BACK_PRESSURE 0x0020
368#define FAIR_FLOW_CTRL 0x0010
369#define NO_EXC_COLLISION_DROP 0x0008
370#define SWITCH_HUGE_PACKET 0x0004
371#define SWITCH_LEGAL_PACKET 0x0002
372#define SWITCH_BUF_RESERVE 0x0001
373
374/* SGCR3 */
375#define KS8842_SGCR3_P 0x0406
376#define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
377
378#define BROADCAST_STORM_RATE_LO 0xFF00
379#define SWITCH_REPEATER 0x0080
380#define SWITCH_HALF_DUPLEX 0x0040
381#define SWITCH_FLOW_CTRL 0x0020
382#define SWITCH_10_MBIT 0x0010
383#define SWITCH_REPLACE_NULL_VID 0x0008
384#define BROADCAST_STORM_RATE_HI 0x0007
385
386#define BROADCAST_STORM_RATE 0x07FF
387
388/* SGCR4 */
389#define KS8842_SGCR4_P 0x0408
390
391/* SGCR5 */
392#define KS8842_SGCR5_P 0x040A
393#define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
394
395#define LED_MODE 0x8200
396#define LED_SPEED_DUPLEX_ACT 0x0000
397#define LED_SPEED_DUPLEX_LINK_ACT 0x8000
398#define LED_DUPLEX_10_100 0x0200
399
400/* SGCR6 */
401#define KS8842_SGCR6_P 0x0410
402#define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
403
404#define KS8842_PRIORITY_MASK 3
405#define KS8842_PRIORITY_SHIFT 2
406
407/* SGCR7 */
408#define KS8842_SGCR7_P 0x0412
409#define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
410
411#define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
412#define SWITCH_UNK_DEF_PORT_3 0x0004
413#define SWITCH_UNK_DEF_PORT_2 0x0002
414#define SWITCH_UNK_DEF_PORT_1 0x0001
415
416/* MACAR1 */
417#define KS8842_MACAR1_P 0x0470
418#define KS8842_MACAR2_P 0x0472
419#define KS8842_MACAR3_P 0x0474
420#define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
421#define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
422#define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
423#define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
424#define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
425#define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
426
427/* TOSR1 */
428#define KS8842_TOSR1_P 0x0480
429#define KS8842_TOSR2_P 0x0482
430#define KS8842_TOSR3_P 0x0484
431#define KS8842_TOSR4_P 0x0486
432#define KS8842_TOSR5_P 0x0488
433#define KS8842_TOSR6_P 0x048A
434#define KS8842_TOSR7_P 0x0490
435#define KS8842_TOSR8_P 0x0492
436#define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
437#define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
438#define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
439#define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
440#define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
441#define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
442
443#define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
444#define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
445
446/* P1CR1 */
447#define KS8842_P1CR1_P 0x0500
448#define KS8842_P1CR2_P 0x0502
449#define KS8842_P1VIDR_P 0x0504
450#define KS8842_P1CR3_P 0x0506
451#define KS8842_P1IRCR_P 0x0508
452#define KS8842_P1ERCR_P 0x050A
453#define KS884X_P1SCSLMD_P 0x0510
454#define KS884X_P1CR4_P 0x0512
455#define KS884X_P1SR_P 0x0514
456
457/* P2CR1 */
458#define KS8842_P2CR1_P 0x0520
459#define KS8842_P2CR2_P 0x0522
460#define KS8842_P2VIDR_P 0x0524
461#define KS8842_P2CR3_P 0x0526
462#define KS8842_P2IRCR_P 0x0528
463#define KS8842_P2ERCR_P 0x052A
464#define KS884X_P2SCSLMD_P 0x0530
465#define KS884X_P2CR4_P 0x0532
466#define KS884X_P2SR_P 0x0534
467
468/* P3CR1 */
469#define KS8842_P3CR1_P 0x0540
470#define KS8842_P3CR2_P 0x0542
471#define KS8842_P3VIDR_P 0x0544
472#define KS8842_P3CR3_P 0x0546
473#define KS8842_P3IRCR_P 0x0548
474#define KS8842_P3ERCR_P 0x054A
475
476#define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
477#define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
478#define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
479
480#define PORT_CTRL_ADDR(port, addr) \
481 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
482 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
483
484#define KS8842_PORT_CTRL_1_OFFSET 0x00
485
486#define PORT_BROADCAST_STORM 0x0080
487#define PORT_DIFFSERV_ENABLE 0x0040
488#define PORT_802_1P_ENABLE 0x0020
489#define PORT_BASED_PRIORITY_MASK 0x0018
490#define PORT_BASED_PRIORITY_BASE 0x0003
491#define PORT_BASED_PRIORITY_SHIFT 3
492#define PORT_BASED_PRIORITY_0 0x0000
493#define PORT_BASED_PRIORITY_1 0x0008
494#define PORT_BASED_PRIORITY_2 0x0010
495#define PORT_BASED_PRIORITY_3 0x0018
496#define PORT_INSERT_TAG 0x0004
497#define PORT_REMOVE_TAG 0x0002
498#define PORT_PRIO_QUEUE_ENABLE 0x0001
499
500#define KS8842_PORT_CTRL_2_OFFSET 0x02
501
502#define PORT_INGRESS_VLAN_FILTER 0x4000
503#define PORT_DISCARD_NON_VID 0x2000
504#define PORT_FORCE_FLOW_CTRL 0x1000
505#define PORT_BACK_PRESSURE 0x0800
506#define PORT_TX_ENABLE 0x0400
507#define PORT_RX_ENABLE 0x0200
508#define PORT_LEARN_DISABLE 0x0100
509#define PORT_MIRROR_SNIFFER 0x0080
510#define PORT_MIRROR_RX 0x0040
511#define PORT_MIRROR_TX 0x0020
512#define PORT_USER_PRIORITY_CEILING 0x0008
513#define PORT_VLAN_MEMBERSHIP 0x0007
514
515#define KS8842_PORT_CTRL_VID_OFFSET 0x04
516
517#define PORT_DEFAULT_VID 0x0001
518
519#define KS8842_PORT_CTRL_3_OFFSET 0x06
520
521#define PORT_INGRESS_LIMIT_MODE 0x000C
522#define PORT_INGRESS_ALL 0x0000
523#define PORT_INGRESS_UNICAST 0x0004
524#define PORT_INGRESS_MULTICAST 0x0008
525#define PORT_INGRESS_BROADCAST 0x000C
526#define PORT_COUNT_IFG 0x0002
527#define PORT_COUNT_PREAMBLE 0x0001
528
529#define KS8842_PORT_IN_RATE_OFFSET 0x08
530#define KS8842_PORT_OUT_RATE_OFFSET 0x0A
531
532#define PORT_PRIORITY_RATE 0x0F
533#define PORT_PRIORITY_RATE_SHIFT 4
534
535#define KS884X_PORT_LINK_MD 0x10
536
537#define PORT_CABLE_10M_SHORT 0x8000
538#define PORT_CABLE_DIAG_RESULT 0x6000
539#define PORT_CABLE_STAT_NORMAL 0x0000
540#define PORT_CABLE_STAT_OPEN 0x2000
541#define PORT_CABLE_STAT_SHORT 0x4000
542#define PORT_CABLE_STAT_FAILED 0x6000
543#define PORT_START_CABLE_DIAG 0x1000
544#define PORT_FORCE_LINK 0x0800
545#define PORT_POWER_SAVING_DISABLE 0x0400
546#define PORT_PHY_REMOTE_LOOPBACK 0x0200
547#define PORT_CABLE_FAULT_COUNTER 0x01FF
548
549#define KS884X_PORT_CTRL_4_OFFSET 0x12
550
551#define PORT_LED_OFF 0x8000
552#define PORT_TX_DISABLE 0x4000
553#define PORT_AUTO_NEG_RESTART 0x2000
554#define PORT_REMOTE_FAULT_DISABLE 0x1000
555#define PORT_POWER_DOWN 0x0800
556#define PORT_AUTO_MDIX_DISABLE 0x0400
557#define PORT_FORCE_MDIX 0x0200
558#define PORT_LOOPBACK 0x0100
559#define PORT_AUTO_NEG_ENABLE 0x0080
560#define PORT_FORCE_100_MBIT 0x0040
561#define PORT_FORCE_FULL_DUPLEX 0x0020
562#define PORT_AUTO_NEG_SYM_PAUSE 0x0010
563#define PORT_AUTO_NEG_100BTX_FD 0x0008
564#define PORT_AUTO_NEG_100BTX 0x0004
565#define PORT_AUTO_NEG_10BT_FD 0x0002
566#define PORT_AUTO_NEG_10BT 0x0001
567
568#define KS884X_PORT_STATUS_OFFSET 0x14
569
570#define PORT_HP_MDIX 0x8000
571#define PORT_REVERSED_POLARITY 0x2000
572#define PORT_RX_FLOW_CTRL 0x0800
573#define PORT_TX_FLOW_CTRL 0x1000
574#define PORT_STATUS_SPEED_100MBIT 0x0400
575#define PORT_STATUS_FULL_DUPLEX 0x0200
576#define PORT_REMOTE_FAULT 0x0100
577#define PORT_MDIX_STATUS 0x0080
578#define PORT_AUTO_NEG_COMPLETE 0x0040
579#define PORT_STATUS_LINK_GOOD 0x0020
580#define PORT_REMOTE_SYM_PAUSE 0x0010
581#define PORT_REMOTE_100BTX_FD 0x0008
582#define PORT_REMOTE_100BTX 0x0004
583#define PORT_REMOTE_10BT_FD 0x0002
584#define PORT_REMOTE_10BT 0x0001
585
586/*
587#define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
588#define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
589#define STATIC_MAC_TABLE_VALID 00-00080000-00000000
590#define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
591#define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
592#define STATIC_MAC_TABLE_FID 00-03C00000-00000000
593*/
594
595#define STATIC_MAC_TABLE_ADDR 0x0000FFFF
596#define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
597#define STATIC_MAC_TABLE_VALID 0x00080000
598#define STATIC_MAC_TABLE_OVERRIDE 0x00100000
599#define STATIC_MAC_TABLE_USE_FID 0x00200000
600#define STATIC_MAC_TABLE_FID 0x03C00000
601
602#define STATIC_MAC_FWD_PORTS_SHIFT 16
603#define STATIC_MAC_FID_SHIFT 22
604
605/*
606#define VLAN_TABLE_VID 00-00000000-00000FFF
607#define VLAN_TABLE_FID 00-00000000-0000F000
608#define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
609#define VLAN_TABLE_VALID 00-00000000-00080000
610*/
611
612#define VLAN_TABLE_VID 0x00000FFF
613#define VLAN_TABLE_FID 0x0000F000
614#define VLAN_TABLE_MEMBERSHIP 0x00070000
615#define VLAN_TABLE_VALID 0x00080000
616
617#define VLAN_TABLE_FID_SHIFT 12
618#define VLAN_TABLE_MEMBERSHIP_SHIFT 16
619
620/*
621#define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
622#define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
623#define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
624#define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
625#define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
626#define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
627#define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
628#define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
629*/
630
631#define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
632#define DYNAMIC_MAC_TABLE_FID 0x000F0000
633#define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
634#define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
635#define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
636
637#define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
638#define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
639#define DYNAMIC_MAC_TABLE_RESERVED 0x78
640#define DYNAMIC_MAC_TABLE_NOT_READY 0x80
641
642#define DYNAMIC_MAC_FID_SHIFT 16
643#define DYNAMIC_MAC_SRC_PORT_SHIFT 20
644#define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
645#define DYNAMIC_MAC_ENTRIES_SHIFT 24
646#define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
647
648/*
649#define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
650#define MIB_COUNTER_VALID 00-00000000-40000000
651#define MIB_COUNTER_OVERFLOW 00-00000000-80000000
652*/
653
654#define MIB_COUNTER_VALUE 0x3FFFFFFF
655#define MIB_COUNTER_VALID 0x40000000
656#define MIB_COUNTER_OVERFLOW 0x80000000
657
658#define MIB_PACKET_DROPPED 0x0000FFFF
659
660#define KS_MIB_PACKET_DROPPED_TX_0 0x100
661#define KS_MIB_PACKET_DROPPED_TX_1 0x101
662#define KS_MIB_PACKET_DROPPED_TX 0x102
663#define KS_MIB_PACKET_DROPPED_RX_0 0x103
664#define KS_MIB_PACKET_DROPPED_RX_1 0x104
665#define KS_MIB_PACKET_DROPPED_RX 0x105
666
667/* Change default LED mode. */
668#define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
669
670#define MAC_ADDR_ORDER(i) (ETH_ALEN - 1 - (i))
671
672#define MAX_ETHERNET_BODY_SIZE 1500
673#define ETHERNET_HEADER_SIZE (14 + VLAN_HLEN)
674
675#define MAX_ETHERNET_PACKET_SIZE \
676 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
677
678#define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
679#define MAX_RX_BUF_SIZE (1912 + 4)
680
681#define ADDITIONAL_ENTRIES 16
682#define MAX_MULTICAST_LIST 32
683
684#define HW_MULTICAST_SIZE 8
685
686#define HW_TO_DEV_PORT(port) (port - 1)
687
688enum {
689 media_connected,
690 media_disconnected
691};
692
693enum {
694 OID_COUNTER_UNKOWN,
695
696 OID_COUNTER_FIRST,
697
698 /* total transmit errors */
699 OID_COUNTER_XMIT_ERROR,
700
701 /* total receive errors */
702 OID_COUNTER_RCV_ERROR,
703
704 OID_COUNTER_LAST
705};
706
707/*
708 * Hardware descriptor definitions
709 */
710
711#define DESC_ALIGNMENT 16
712#define BUFFER_ALIGNMENT 8
713
714#define NUM_OF_RX_DESC 64
715#define NUM_OF_TX_DESC 64
716
717#define KS_DESC_RX_FRAME_LEN 0x000007FF
718#define KS_DESC_RX_FRAME_TYPE 0x00008000
719#define KS_DESC_RX_ERROR_CRC 0x00010000
720#define KS_DESC_RX_ERROR_RUNT 0x00020000
721#define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
722#define KS_DESC_RX_ERROR_PHY 0x00080000
723#define KS884X_DESC_RX_PORT_MASK 0x00300000
724#define KS_DESC_RX_MULTICAST 0x01000000
725#define KS_DESC_RX_ERROR 0x02000000
726#define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
727#define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
728#define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
729#define KS_DESC_RX_LAST 0x20000000
730#define KS_DESC_RX_FIRST 0x40000000
731#define KS_DESC_RX_ERROR_COND \
732 (KS_DESC_RX_ERROR_CRC | \
733 KS_DESC_RX_ERROR_RUNT | \
734 KS_DESC_RX_ERROR_PHY | \
735 KS_DESC_RX_ERROR_TOO_LONG)
736
737#define KS_DESC_HW_OWNED 0x80000000
738
739#define KS_DESC_BUF_SIZE 0x000007FF
740#define KS884X_DESC_TX_PORT_MASK 0x00300000
741#define KS_DESC_END_OF_RING 0x02000000
742#define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
743#define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
744#define KS_DESC_TX_CSUM_GEN_IP 0x10000000
745#define KS_DESC_TX_LAST 0x20000000
746#define KS_DESC_TX_FIRST 0x40000000
747#define KS_DESC_TX_INTERRUPT 0x80000000
748
749#define KS_DESC_PORT_SHIFT 20
750
751#define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
752
753#define KS_DESC_TX_MASK \
754 (KS_DESC_TX_INTERRUPT | \
755 KS_DESC_TX_FIRST | \
756 KS_DESC_TX_LAST | \
757 KS_DESC_TX_CSUM_GEN_IP | \
758 KS_DESC_TX_CSUM_GEN_TCP | \
759 KS_DESC_TX_CSUM_GEN_UDP | \
760 KS_DESC_BUF_SIZE)
761
762struct ksz_desc_rx_stat {
763#ifdef __BIG_ENDIAN_BITFIELD
764 u32 hw_owned:1;
765 u32 first_desc:1;
766 u32 last_desc:1;
767 u32 csum_err_ip:1;
768 u32 csum_err_tcp:1;
769 u32 csum_err_udp:1;
770 u32 error:1;
771 u32 multicast:1;
772 u32 src_port:4;
773 u32 err_phy:1;
774 u32 err_too_long:1;
775 u32 err_runt:1;
776 u32 err_crc:1;
777 u32 frame_type:1;
778 u32 reserved1:4;
779 u32 frame_len:11;
780#else
781 u32 frame_len:11;
782 u32 reserved1:4;
783 u32 frame_type:1;
784 u32 err_crc:1;
785 u32 err_runt:1;
786 u32 err_too_long:1;
787 u32 err_phy:1;
788 u32 src_port:4;
789 u32 multicast:1;
790 u32 error:1;
791 u32 csum_err_udp:1;
792 u32 csum_err_tcp:1;
793 u32 csum_err_ip:1;
794 u32 last_desc:1;
795 u32 first_desc:1;
796 u32 hw_owned:1;
797#endif
798};
799
800struct ksz_desc_tx_stat {
801#ifdef __BIG_ENDIAN_BITFIELD
802 u32 hw_owned:1;
803 u32 reserved1:31;
804#else
805 u32 reserved1:31;
806 u32 hw_owned:1;
807#endif
808};
809
810struct ksz_desc_rx_buf {
811#ifdef __BIG_ENDIAN_BITFIELD
812 u32 reserved4:6;
813 u32 end_of_ring:1;
814 u32 reserved3:14;
815 u32 buf_size:11;
816#else
817 u32 buf_size:11;
818 u32 reserved3:14;
819 u32 end_of_ring:1;
820 u32 reserved4:6;
821#endif
822};
823
824struct ksz_desc_tx_buf {
825#ifdef __BIG_ENDIAN_BITFIELD
826 u32 intr:1;
827 u32 first_seg:1;
828 u32 last_seg:1;
829 u32 csum_gen_ip:1;
830 u32 csum_gen_tcp:1;
831 u32 csum_gen_udp:1;
832 u32 end_of_ring:1;
833 u32 reserved4:1;
834 u32 dest_port:4;
835 u32 reserved3:9;
836 u32 buf_size:11;
837#else
838 u32 buf_size:11;
839 u32 reserved3:9;
840 u32 dest_port:4;
841 u32 reserved4:1;
842 u32 end_of_ring:1;
843 u32 csum_gen_udp:1;
844 u32 csum_gen_tcp:1;
845 u32 csum_gen_ip:1;
846 u32 last_seg:1;
847 u32 first_seg:1;
848 u32 intr:1;
849#endif
850};
851
852union desc_stat {
853 struct ksz_desc_rx_stat rx;
854 struct ksz_desc_tx_stat tx;
855 u32 data;
856};
857
858union desc_buf {
859 struct ksz_desc_rx_buf rx;
860 struct ksz_desc_tx_buf tx;
861 u32 data;
862};
863
864/**
865 * struct ksz_hw_desc - Hardware descriptor data structure
866 * @ctrl: Descriptor control value.
867 * @buf: Descriptor buffer value.
868 * @addr: Physical address of memory buffer.
869 * @next: Pointer to next hardware descriptor.
870 */
871struct ksz_hw_desc {
872 union desc_stat ctrl;
873 union desc_buf buf;
874 u32 addr;
875 u32 next;
876};
877
878/**
879 * struct ksz_sw_desc - Software descriptor data structure
880 * @ctrl: Descriptor control value.
881 * @buf: Descriptor buffer value.
882 * @buf_size: Current buffers size value in hardware descriptor.
883 */
884struct ksz_sw_desc {
885 union desc_stat ctrl;
886 union desc_buf buf;
887 u32 buf_size;
888};
889
890/**
891 * struct ksz_dma_buf - OS dependent DMA buffer data structure
892 * @skb: Associated socket buffer.
893 * @dma: Associated physical DMA address.
894 * @len: Actual len used.
895 */
896struct ksz_dma_buf {
897 struct sk_buff *skb;
898 dma_addr_t dma;
899 int len;
900};
901
902/**
903 * struct ksz_desc - Descriptor structure
904 * @phw: Hardware descriptor pointer to uncached physical memory.
905 * @sw: Cached memory to hold hardware descriptor values for
906 * manipulation.
907 * @dma_buf: Operating system dependent data structure to hold physical
908 * memory buffer allocation information.
909 */
910struct ksz_desc {
911 struct ksz_hw_desc *phw;
912 struct ksz_sw_desc sw;
913 struct ksz_dma_buf dma_buf;
914};
915
916#define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
917
918/**
919 * struct ksz_desc_info - Descriptor information data structure
920 * @ring: First descriptor in the ring.
921 * @cur: Current descriptor being manipulated.
922 * @ring_virt: First hardware descriptor in the ring.
923 * @ring_phys: The physical address of the first descriptor of the ring.
924 * @size: Size of hardware descriptor.
925 * @alloc: Number of descriptors allocated.
926 * @avail: Number of descriptors available for use.
927 * @last: Index for last descriptor released to hardware.
928 * @next: Index for next descriptor available for use.
929 * @mask: Mask for index wrapping.
930 */
931struct ksz_desc_info {
932 struct ksz_desc *ring;
933 struct ksz_desc *cur;
934 struct ksz_hw_desc *ring_virt;
935 u32 ring_phys;
936 int size;
937 int alloc;
938 int avail;
939 int last;
940 int next;
941 int mask;
942};
943
944/*
945 * KSZ8842 switch definitions
946 */
947
948enum {
949 TABLE_STATIC_MAC = 0,
950 TABLE_VLAN,
951 TABLE_DYNAMIC_MAC,
952 TABLE_MIB
953};
954
955#define LEARNED_MAC_TABLE_ENTRIES 1024
956#define STATIC_MAC_TABLE_ENTRIES 8
957
958/**
959 * struct ksz_mac_table - Static MAC table data structure
960 * @mac_addr: MAC address to filter.
961 * @vid: VID value.
962 * @fid: FID value.
963 * @ports: Port membership.
964 * @override: Override setting.
965 * @use_fid: FID use setting.
966 * @valid: Valid setting indicating the entry is being used.
967 */
968struct ksz_mac_table {
969 u8 mac_addr[ETH_ALEN];
970 u16 vid;
971 u8 fid;
972 u8 ports;
973 u8 override:1;
974 u8 use_fid:1;
975 u8 valid:1;
976};
977
978#define VLAN_TABLE_ENTRIES 16
979
980/**
981 * struct ksz_vlan_table - VLAN table data structure
982 * @vid: VID value.
983 * @fid: FID value.
984 * @member: Port membership.
985 */
986struct ksz_vlan_table {
987 u16 vid;
988 u8 fid;
989 u8 member;
990};
991
992#define DIFFSERV_ENTRIES 64
993#define PRIO_802_1P_ENTRIES 8
994#define PRIO_QUEUES 4
995
996#define SWITCH_PORT_NUM 2
997#define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
998#define HOST_MASK (1 << SWITCH_PORT_NUM)
999#define PORT_MASK 7
1000
1001#define MAIN_PORT 0
1002#define OTHER_PORT 1
1003#define HOST_PORT SWITCH_PORT_NUM
1004
1005#define PORT_COUNTER_NUM 0x20
1006#define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1007
1008#define MIB_COUNTER_RX_LO_PRIORITY 0x00
1009#define MIB_COUNTER_RX_HI_PRIORITY 0x01
1010#define MIB_COUNTER_RX_UNDERSIZE 0x02
1011#define MIB_COUNTER_RX_FRAGMENT 0x03
1012#define MIB_COUNTER_RX_OVERSIZE 0x04
1013#define MIB_COUNTER_RX_JABBER 0x05
1014#define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1015#define MIB_COUNTER_RX_CRC_ERR 0x07
1016#define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1017#define MIB_COUNTER_RX_CTRL_8808 0x09
1018#define MIB_COUNTER_RX_PAUSE 0x0A
1019#define MIB_COUNTER_RX_BROADCAST 0x0B
1020#define MIB_COUNTER_RX_MULTICAST 0x0C
1021#define MIB_COUNTER_RX_UNICAST 0x0D
1022#define MIB_COUNTER_RX_OCTET_64 0x0E
1023#define MIB_COUNTER_RX_OCTET_65_127 0x0F
1024#define MIB_COUNTER_RX_OCTET_128_255 0x10
1025#define MIB_COUNTER_RX_OCTET_256_511 0x11
1026#define MIB_COUNTER_RX_OCTET_512_1023 0x12
1027#define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1028#define MIB_COUNTER_TX_LO_PRIORITY 0x14
1029#define MIB_COUNTER_TX_HI_PRIORITY 0x15
1030#define MIB_COUNTER_TX_LATE_COLLISION 0x16
1031#define MIB_COUNTER_TX_PAUSE 0x17
1032#define MIB_COUNTER_TX_BROADCAST 0x18
1033#define MIB_COUNTER_TX_MULTICAST 0x19
1034#define MIB_COUNTER_TX_UNICAST 0x1A
1035#define MIB_COUNTER_TX_DEFERRED 0x1B
1036#define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1037#define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1038#define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1039#define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1040
1041#define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1042#define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1043
1044/**
1045 * struct ksz_port_mib - Port MIB data structure
1046 * @cnt_ptr: Current pointer to MIB counter index.
1047 * @link_down: Indication the link has just gone down.
1048 * @state: Connection status of the port.
1049 * @mib_start: The starting counter index. Some ports do not start at 0.
1050 * @counter: 64-bit MIB counter value.
1051 * @dropped: Temporary buffer to remember last read packet dropped values.
1052 *
1053 * MIB counters needs to be read periodically so that counters do not get
1054 * overflowed and give incorrect values. A right balance is needed to
1055 * satisfy this condition and not waste too much CPU time.
1056 *
1057 * It is pointless to read MIB counters when the port is disconnected. The
1058 * @state provides the connection status so that MIB counters are read only
1059 * when the port is connected. The @link_down indicates the port is just
1060 * disconnected so that all MIB counters are read one last time to update the
1061 * information.
1062 */
1063struct ksz_port_mib {
1064 u8 cnt_ptr;
1065 u8 link_down;
1066 u8 state;
1067 u8 mib_start;
1068
1069 u64 counter[TOTAL_PORT_COUNTER_NUM];
1070 u32 dropped[2];
1071};
1072
1073/**
1074 * struct ksz_port_cfg - Port configuration data structure
1075 * @vid: VID value.
1076 * @member: Port membership.
1077 * @port_prio: Port priority.
1078 * @rx_rate: Receive priority rate.
1079 * @tx_rate: Transmit priority rate.
1080 * @stp_state: Current Spanning Tree Protocol state.
1081 */
1082struct ksz_port_cfg {
1083 u16 vid;
1084 u8 member;
1085 u8 port_prio;
1086 u32 rx_rate[PRIO_QUEUES];
1087 u32 tx_rate[PRIO_QUEUES];
1088 int stp_state;
1089};
1090
1091/**
1092 * struct ksz_switch - KSZ8842 switch data structure
1093 * @mac_table: MAC table entries information.
1094 * @vlan_table: VLAN table entries information.
1095 * @port_cfg: Port configuration information.
1096 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1097 * (bit7 ~ bit2) field.
1098 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1099 * Tag priority field.
1100 * @br_addr: Bridge address. Used for STP.
1101 * @other_addr: Other MAC address. Used for multiple network device mode.
1102 * @broad_per: Broadcast storm percentage.
1103 * @member: Current port membership. Used for STP.
1104 */
1105struct ksz_switch {
1106 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1107 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1108 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1109
1110 u8 diffserv[DIFFSERV_ENTRIES];
1111 u8 p_802_1p[PRIO_802_1P_ENTRIES];
1112
1113 u8 br_addr[ETH_ALEN];
1114 u8 other_addr[ETH_ALEN];
1115
1116 u8 broad_per;
1117 u8 member;
1118};
1119
1120#define TX_RATE_UNIT 10000
1121
1122/**
1123 * struct ksz_port_info - Port information data structure
1124 * @state: Connection status of the port.
1125 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1126 * @duplex: Duplex mode.
1127 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1128 * @partner: Auto-negotiation partner setting. Used to determine link.
1129 * @port_id: Port index to access actual hardware register.
1130 * @pdev: Pointer to OS dependent network device.
1131 */
1132struct ksz_port_info {
1133 uint state;
1134 uint tx_rate;
1135 u8 duplex;
1136 u8 advertised;
1137 u8 partner;
1138 u8 port_id;
1139 void *pdev;
1140};
1141
1142#define MAX_TX_HELD_SIZE 52000
1143
1144/* Hardware features and bug fixes. */
1145#define LINK_INT_WORKING (1 << 0)
1146#define SMALL_PACKET_TX_BUG (1 << 1)
1147#define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1148#define RX_HUGE_FRAME (1 << 4)
1149#define STP_SUPPORT (1 << 8)
1150
1151/* Software overrides. */
1152#define PAUSE_FLOW_CTRL (1 << 0)
1153#define FAST_AGING (1 << 1)
1154
1155/**
1156 * struct ksz_hw - KSZ884X hardware data structure
1157 * @io: Virtual address assigned.
1158 * @ksz_switch: Pointer to KSZ8842 switch.
1159 * @port_info: Port information.
1160 * @port_mib: Port MIB information.
1161 * @dev_count: Number of network devices this hardware supports.
1162 * @dst_ports: Destination ports in switch for transmission.
1163 * @id: Hardware ID. Used for display only.
1164 * @mib_cnt: Number of MIB counters this hardware has.
1165 * @mib_port_cnt: Number of ports with MIB counters.
1166 * @tx_cfg: Cached transmit control settings.
1167 * @rx_cfg: Cached receive control settings.
1168 * @intr_mask: Current interrupt mask.
1169 * @intr_set: Current interrup set.
1170 * @intr_blocked: Interrupt blocked.
1171 * @rx_desc_info: Receive descriptor information.
1172 * @tx_desc_info: Transmit descriptor information.
1173 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1174 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1175 * @tx_size: Transmit data size. Used for TX optimization.
1176 * The maximum is defined by MAX_TX_HELD_SIZE.
1177 * @perm_addr: Permanent MAC address.
1178 * @override_addr: Overridden MAC address.
1179 * @address: Additional MAC address entries.
1180 * @addr_list_size: Additional MAC address list size.
1181 * @mac_override: Indication of MAC address overridden.
1182 * @promiscuous: Counter to keep track of promiscuous mode set.
1183 * @all_multi: Counter to keep track of all multicast mode set.
1184 * @multi_list: Multicast address entries.
1185 * @multi_bits: Cached multicast hash table settings.
1186 * @multi_list_size: Multicast address list size.
1187 * @enabled: Indication of hardware enabled.
1188 * @rx_stop: Indication of receive process stop.
1189 * @reserved2: none
1190 * @features: Hardware features to enable.
1191 * @overrides: Hardware features to override.
1192 * @parent: Pointer to parent, network device private structure.
1193 */
1194struct ksz_hw {
1195 void __iomem *io;
1196
1197 struct ksz_switch *ksz_switch;
1198 struct ksz_port_info port_info[SWITCH_PORT_NUM];
1199 struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1200 int dev_count;
1201 int dst_ports;
1202 int id;
1203 int mib_cnt;
1204 int mib_port_cnt;
1205
1206 u32 tx_cfg;
1207 u32 rx_cfg;
1208 u32 intr_mask;
1209 u32 intr_set;
1210 uint intr_blocked;
1211
1212 struct ksz_desc_info rx_desc_info;
1213 struct ksz_desc_info tx_desc_info;
1214
1215 int tx_int_cnt;
1216 int tx_int_mask;
1217 int tx_size;
1218
1219 u8 perm_addr[ETH_ALEN];
1220 u8 override_addr[ETH_ALEN];
1221 u8 address[ADDITIONAL_ENTRIES][ETH_ALEN];
1222 u8 addr_list_size;
1223 u8 mac_override;
1224 u8 promiscuous;
1225 u8 all_multi;
1226 u8 multi_list[MAX_MULTICAST_LIST][ETH_ALEN];
1227 u8 multi_bits[HW_MULTICAST_SIZE];
1228 u8 multi_list_size;
1229
1230 u8 enabled;
1231 u8 rx_stop;
1232 u8 reserved2[1];
1233
1234 uint features;
1235 uint overrides;
1236
1237 void *parent;
1238};
1239
1240enum {
1241 PHY_NO_FLOW_CTRL,
1242 PHY_FLOW_CTRL,
1243 PHY_TX_ONLY,
1244 PHY_RX_ONLY
1245};
1246
1247/**
1248 * struct ksz_port - Virtual port data structure
1249 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1250 * duplex, and 0 for auto, which normally results in full
1251 * duplex.
1252 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1253 * 0 for auto, which normally results in 100 Mbit.
1254 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1255 * force.
1256 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1257 * control, and PHY_FLOW_CTRL for flow control.
1258 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1259 * Mbit PHY.
1260 * @first_port: Index of first port this port supports.
1261 * @mib_port_cnt: Number of ports with MIB counters.
1262 * @port_cnt: Number of ports this port supports.
1263 * @counter: Port statistics counter.
1264 * @hw: Pointer to hardware structure.
1265 * @linked: Pointer to port information linked to this port.
1266 */
1267struct ksz_port {
1268 u8 duplex;
1269 u8 speed;
1270 u8 force_link;
1271 u8 flow_ctrl;
1272
1273 int first_port;
1274 int mib_port_cnt;
1275 int port_cnt;
1276 u64 counter[OID_COUNTER_LAST];
1277
1278 struct ksz_hw *hw;
1279 struct ksz_port_info *linked;
1280};
1281
1282/**
1283 * struct ksz_timer_info - Timer information data structure
1284 * @timer: Kernel timer.
1285 * @cnt: Running timer counter.
1286 * @max: Number of times to run timer; -1 for infinity.
1287 * @period: Timer period in jiffies.
1288 */
1289struct ksz_timer_info {
1290 struct timer_list timer;
1291 int cnt;
1292 int max;
1293 int period;
1294};
1295
1296/**
1297 * struct ksz_shared_mem - OS dependent shared memory data structure
1298 * @dma_addr: Physical DMA address allocated.
1299 * @alloc_size: Allocation size.
1300 * @phys: Actual physical address used.
1301 * @alloc_virt: Virtual address allocated.
1302 * @virt: Actual virtual address used.
1303 */
1304struct ksz_shared_mem {
1305 dma_addr_t dma_addr;
1306 uint alloc_size;
1307 uint phys;
1308 u8 *alloc_virt;
1309 u8 *virt;
1310};
1311
1312/**
1313 * struct ksz_counter_info - OS dependent counter information data structure
1314 * @counter: Wait queue to wakeup after counters are read.
1315 * @time: Next time in jiffies to read counter.
1316 * @read: Indication of counters read in full or not.
1317 */
1318struct ksz_counter_info {
1319 wait_queue_head_t counter;
1320 unsigned long time;
1321 int read;
1322};
1323
1324/**
1325 * struct dev_info - Network device information data structure
1326 * @dev: Pointer to network device.
1327 * @pdev: Pointer to PCI device.
1328 * @hw: Hardware structure.
1329 * @desc_pool: Physical memory used for descriptor pool.
1330 * @hwlock: Spinlock to prevent hardware from accessing.
1331 * @lock: Mutex lock to prevent device from accessing.
1332 * @dev_rcv: Receive process function used.
1333 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1334 * @skb_index: Buffer index for receiving fragments.
1335 * @skb_len: Buffer length for receiving fragments.
1336 * @mib_read: Workqueue to read MIB counters.
1337 * @mib_timer_info: Timer to read MIB counters.
1338 * @counter: Used for MIB reading.
1339 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1340 * the maximum is MAX_RX_BUF_SIZE.
1341 * @opened: Counter to keep track of device open.
1342 * @rx_tasklet: Receive processing tasklet.
1343 * @tx_tasklet: Transmit processing tasklet.
1344 * @wol_enable: Wake-on-LAN enable set by ethtool.
1345 * @wol_support: Wake-on-LAN support used by ethtool.
1346 * @pme_wait: Used for KSZ8841 power management.
1347 */
1348struct dev_info {
1349 struct net_device *dev;
1350 struct pci_dev *pdev;
1351
1352 struct ksz_hw hw;
1353 struct ksz_shared_mem desc_pool;
1354
1355 spinlock_t hwlock;
1356 struct mutex lock;
1357
1358 int (*dev_rcv)(struct dev_info *);
1359
1360 struct sk_buff *last_skb;
1361 int skb_index;
1362 int skb_len;
1363
1364 struct work_struct mib_read;
1365 struct ksz_timer_info mib_timer_info;
1366 struct ksz_counter_info counter[TOTAL_PORT_NUM];
1367
1368 int mtu;
1369 int opened;
1370
1371 struct tasklet_struct rx_tasklet;
1372 struct tasklet_struct tx_tasklet;
1373
1374 int wol_enable;
1375 int wol_support;
1376 unsigned long pme_wait;
1377};
1378
1379/**
1380 * struct dev_priv - Network device private data structure
1381 * @adapter: Adapter device information.
1382 * @port: Port information.
1383 * @monitor_timer_info: Timer to monitor ports.
1384 * @proc_sem: Semaphore for proc accessing.
1385 * @id: Device ID.
1386 * @mii_if: MII interface information.
1387 * @advertising: Temporary variable to store advertised settings.
1388 * @msg_enable: The message flags controlling driver output.
1389 * @media_state: The connection status of the device.
1390 * @multicast: The all multicast state of the device.
1391 * @promiscuous: The promiscuous state of the device.
1392 */
1393struct dev_priv {
1394 struct dev_info *adapter;
1395 struct ksz_port port;
1396 struct ksz_timer_info monitor_timer_info;
1397
1398 struct semaphore proc_sem;
1399 int id;
1400
1401 struct mii_if_info mii_if;
1402 u32 advertising;
1403
1404 u32 msg_enable;
1405 int media_state;
1406 int multicast;
1407 int promiscuous;
1408};
1409
1410#define DRV_NAME "KSZ884X PCI"
1411#define DEVICE_NAME "KSZ884x PCI"
1412#define DRV_VERSION "1.0.0"
1413#define DRV_RELDATE "Feb 8, 2010"
1414
1415static char version[] =
1416 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1417
1418static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1419
1420/*
1421 * Interrupt processing primary routines
1422 */
1423
1424static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1425{
1426 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1427}
1428
1429static inline void hw_dis_intr(struct ksz_hw *hw)
1430{
1431 hw->intr_blocked = hw->intr_mask;
1432 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1433 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1434}
1435
1436static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1437{
1438 hw->intr_set = interrupt;
1439 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1440}
1441
1442static inline void hw_ena_intr(struct ksz_hw *hw)
1443{
1444 hw->intr_blocked = 0;
1445 hw_set_intr(hw, hw->intr_mask);
1446}
1447
1448static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1449{
1450 hw->intr_mask &= ~(bit);
1451}
1452
1453static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1454{
1455 u32 read_intr;
1456
1457 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1458 hw->intr_set = read_intr & ~interrupt;
1459 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1460 hw_dis_intr_bit(hw, interrupt);
1461}
1462
1463/**
1464 * hw_turn_on_intr - turn on specified interrupts
1465 * @hw: The hardware instance.
1466 * @bit: The interrupt bits to be on.
1467 *
1468 * This routine turns on the specified interrupts in the interrupt mask so that
1469 * those interrupts will be enabled.
1470 */
1471static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1472{
1473 hw->intr_mask |= bit;
1474
1475 if (!hw->intr_blocked)
1476 hw_set_intr(hw, hw->intr_mask);
1477}
1478
1479static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1480{
1481 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1482 *status = *status & hw->intr_set;
1483}
1484
1485static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1486{
1487 if (interrupt)
1488 hw_ena_intr(hw);
1489}
1490
1491/**
1492 * hw_block_intr - block hardware interrupts
1493 * @hw: The hardware instance.
1494 *
1495 * This function blocks all interrupts of the hardware and returns the current
1496 * interrupt enable mask so that interrupts can be restored later.
1497 *
1498 * Return the current interrupt enable mask.
1499 */
1500static uint hw_block_intr(struct ksz_hw *hw)
1501{
1502 uint interrupt = 0;
1503
1504 if (!hw->intr_blocked) {
1505 hw_dis_intr(hw);
1506 interrupt = hw->intr_blocked;
1507 }
1508 return interrupt;
1509}
1510
1511/*
1512 * Hardware descriptor routines
1513 */
1514
1515static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1516{
1517 status.rx.hw_owned = 0;
1518 desc->phw->ctrl.data = cpu_to_le32(status.data);
1519}
1520
1521static inline void release_desc(struct ksz_desc *desc)
1522{
1523 desc->sw.ctrl.tx.hw_owned = 1;
1524 if (desc->sw.buf_size != desc->sw.buf.data) {
1525 desc->sw.buf_size = desc->sw.buf.data;
1526 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1527 }
1528 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1529}
1530
1531static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1532{
1533 *desc = &info->ring[info->last];
1534 info->last++;
1535 info->last &= info->mask;
1536 info->avail--;
1537 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1538}
1539
1540static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1541{
1542 desc->phw->addr = cpu_to_le32(addr);
1543}
1544
1545static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1546{
1547 desc->sw.buf.rx.buf_size = len;
1548}
1549
1550static inline void get_tx_pkt(struct ksz_desc_info *info,
1551 struct ksz_desc **desc)
1552{
1553 *desc = &info->ring[info->next];
1554 info->next++;
1555 info->next &= info->mask;
1556 info->avail--;
1557 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1558}
1559
1560static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1561{
1562 desc->phw->addr = cpu_to_le32(addr);
1563}
1564
1565static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1566{
1567 desc->sw.buf.tx.buf_size = len;
1568}
1569
1570/* Switch functions */
1571
1572#define TABLE_READ 0x10
1573#define TABLE_SEL_SHIFT 2
1574
1575#define HW_DELAY(hw, reg) \
1576 do { \
1577 readw(hw->io + reg); \
1578 } while (0)
1579
1580/**
1581 * sw_r_table - read 4 bytes of data from switch table
1582 * @hw: The hardware instance.
1583 * @table: The table selector.
1584 * @addr: The address of the table entry.
1585 * @data: Buffer to store the read data.
1586 *
1587 * This routine reads 4 bytes of data from the table of the switch.
1588 * Hardware interrupts are disabled to minimize corruption of read data.
1589 */
1590static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1591{
1592 u16 ctrl_addr;
1593 uint interrupt;
1594
1595 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1596
1597 interrupt = hw_block_intr(hw);
1598
1599 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1600 HW_DELAY(hw, KS884X_IACR_OFFSET);
1601 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1602
1603 hw_restore_intr(hw, interrupt);
1604}
1605
1606/**
1607 * sw_w_table_64 - write 8 bytes of data to the switch table
1608 * @hw: The hardware instance.
1609 * @table: The table selector.
1610 * @addr: The address of the table entry.
1611 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1612 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1613 *
1614 * This routine writes 8 bytes of data to the table of the switch.
1615 * Hardware interrupts are disabled to minimize corruption of written data.
1616 */
1617static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1618 u32 data_lo)
1619{
1620 u16 ctrl_addr;
1621 uint interrupt;
1622
1623 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1624
1625 interrupt = hw_block_intr(hw);
1626
1627 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1628 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1629
1630 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1631 HW_DELAY(hw, KS884X_IACR_OFFSET);
1632
1633 hw_restore_intr(hw, interrupt);
1634}
1635
1636/**
1637 * sw_w_sta_mac_table - write to the static MAC table
1638 * @hw: The hardware instance.
1639 * @addr: The address of the table entry.
1640 * @mac_addr: The MAC address.
1641 * @ports: The port members.
1642 * @override: The flag to override the port receive/transmit settings.
1643 * @valid: The flag to indicate entry is valid.
1644 * @use_fid: The flag to indicate the FID is valid.
1645 * @fid: The FID value.
1646 *
1647 * This routine writes an entry of the static MAC table of the switch. It
1648 * calls sw_w_table_64() to write the data.
1649 */
1650static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1651 u8 ports, int override, int valid, int use_fid, u8 fid)
1652{
1653 u32 data_hi;
1654 u32 data_lo;
1655
1656 data_lo = ((u32) mac_addr[2] << 24) |
1657 ((u32) mac_addr[3] << 16) |
1658 ((u32) mac_addr[4] << 8) | mac_addr[5];
1659 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1660 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1661
1662 if (override)
1663 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1664 if (use_fid) {
1665 data_hi |= STATIC_MAC_TABLE_USE_FID;
1666 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1667 }
1668 if (valid)
1669 data_hi |= STATIC_MAC_TABLE_VALID;
1670
1671 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1672}
1673
1674/**
1675 * sw_r_vlan_table - read from the VLAN table
1676 * @hw: The hardware instance.
1677 * @addr: The address of the table entry.
1678 * @vid: Buffer to store the VID.
1679 * @fid: Buffer to store the VID.
1680 * @member: Buffer to store the port membership.
1681 *
1682 * This function reads an entry of the VLAN table of the switch. It calls
1683 * sw_r_table() to get the data.
1684 *
1685 * Return 0 if the entry is valid; otherwise -1.
1686 */
1687static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1688 u8 *member)
1689{
1690 u32 data;
1691
1692 sw_r_table(hw, TABLE_VLAN, addr, &data);
1693 if (data & VLAN_TABLE_VALID) {
1694 *vid = (u16)(data & VLAN_TABLE_VID);
1695 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1696 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1697 VLAN_TABLE_MEMBERSHIP_SHIFT);
1698 return 0;
1699 }
1700 return -1;
1701}
1702
1703/**
1704 * port_r_mib_cnt - read MIB counter
1705 * @hw: The hardware instance.
1706 * @port: The port index.
1707 * @addr: The address of the counter.
1708 * @cnt: Buffer to store the counter.
1709 *
1710 * This routine reads a MIB counter of the port.
1711 * Hardware interrupts are disabled to minimize corruption of read data.
1712 */
1713static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1714{
1715 u32 data;
1716 u16 ctrl_addr;
1717 uint interrupt;
1718 int timeout;
1719
1720 ctrl_addr = addr + PORT_COUNTER_NUM * port;
1721
1722 interrupt = hw_block_intr(hw);
1723
1724 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1725 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1726 HW_DELAY(hw, KS884X_IACR_OFFSET);
1727
1728 for (timeout = 100; timeout > 0; timeout--) {
1729 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1730
1731 if (data & MIB_COUNTER_VALID) {
1732 if (data & MIB_COUNTER_OVERFLOW)
1733 *cnt += MIB_COUNTER_VALUE + 1;
1734 *cnt += data & MIB_COUNTER_VALUE;
1735 break;
1736 }
1737 }
1738
1739 hw_restore_intr(hw, interrupt);
1740}
1741
1742/**
1743 * port_r_mib_pkt - read dropped packet counts
1744 * @hw: The hardware instance.
1745 * @port: The port index.
1746 * @last: last one
1747 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1748 *
1749 * This routine reads the dropped packet counts of the port.
1750 * Hardware interrupts are disabled to minimize corruption of read data.
1751 */
1752static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1753{
1754 u32 cur;
1755 u32 data;
1756 u16 ctrl_addr;
1757 uint interrupt;
1758 int index;
1759
1760 index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1761 do {
1762 interrupt = hw_block_intr(hw);
1763
1764 ctrl_addr = (u16) index;
1765 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1766 << 8);
1767 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1768 HW_DELAY(hw, KS884X_IACR_OFFSET);
1769 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1770
1771 hw_restore_intr(hw, interrupt);
1772
1773 data &= MIB_PACKET_DROPPED;
1774 cur = *last;
1775 if (data != cur) {
1776 *last = data;
1777 if (data < cur)
1778 data += MIB_PACKET_DROPPED + 1;
1779 data -= cur;
1780 *cnt += data;
1781 }
1782 ++last;
1783 ++cnt;
1784 index -= KS_MIB_PACKET_DROPPED_TX -
1785 KS_MIB_PACKET_DROPPED_TX_0 + 1;
1786 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1787}
1788
1789/**
1790 * port_r_cnt - read MIB counters periodically
1791 * @hw: The hardware instance.
1792 * @port: The port index.
1793 *
1794 * This routine is used to read the counters of the port periodically to avoid
1795 * counter overflow. The hardware should be acquired first before calling this
1796 * routine.
1797 *
1798 * Return non-zero when not all counters not read.
1799 */
1800static int port_r_cnt(struct ksz_hw *hw, int port)
1801{
1802 struct ksz_port_mib *mib = &hw->port_mib[port];
1803
1804 if (mib->mib_start < PORT_COUNTER_NUM)
1805 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1806 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1807 &mib->counter[mib->cnt_ptr]);
1808 ++mib->cnt_ptr;
1809 }
1810 if (hw->mib_cnt > PORT_COUNTER_NUM)
1811 port_r_mib_pkt(hw, port, mib->dropped,
1812 &mib->counter[PORT_COUNTER_NUM]);
1813 mib->cnt_ptr = 0;
1814 return 0;
1815}
1816
1817/**
1818 * port_init_cnt - initialize MIB counter values
1819 * @hw: The hardware instance.
1820 * @port: The port index.
1821 *
1822 * This routine is used to initialize all counters to zero if the hardware
1823 * cannot do it after reset.
1824 */
1825static void port_init_cnt(struct ksz_hw *hw, int port)
1826{
1827 struct ksz_port_mib *mib = &hw->port_mib[port];
1828
1829 mib->cnt_ptr = 0;
1830 if (mib->mib_start < PORT_COUNTER_NUM)
1831 do {
1832 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1833 &mib->counter[mib->cnt_ptr]);
1834 ++mib->cnt_ptr;
1835 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1836 if (hw->mib_cnt > PORT_COUNTER_NUM)
1837 port_r_mib_pkt(hw, port, mib->dropped,
1838 &mib->counter[PORT_COUNTER_NUM]);
1839 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1840 mib->cnt_ptr = 0;
1841}
1842
1843/*
1844 * Port functions
1845 */
1846
1847/**
1848 * port_cfg - set port register bits
1849 * @hw: The hardware instance.
1850 * @port: The port index.
1851 * @offset: The offset of the port register.
1852 * @bits: The data bits to set.
1853 * @set: The flag indicating whether the bits are to be set or not.
1854 *
1855 * This routine sets or resets the specified bits of the port register.
1856 */
1857static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1858 int set)
1859{
1860 u32 addr;
1861 u16 data;
1862
1863 PORT_CTRL_ADDR(port, addr);
1864 addr += offset;
1865 data = readw(hw->io + addr);
1866 if (set)
1867 data |= bits;
1868 else
1869 data &= ~bits;
1870 writew(data, hw->io + addr);
1871}
1872
1873/**
1874 * port_r8 - read byte from port register
1875 * @hw: The hardware instance.
1876 * @port: The port index.
1877 * @offset: The offset of the port register.
1878 * @data: Buffer to store the data.
1879 *
1880 * This routine reads a byte from the port register.
1881 */
1882static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
1883{
1884 u32 addr;
1885
1886 PORT_CTRL_ADDR(port, addr);
1887 addr += offset;
1888 *data = readb(hw->io + addr);
1889}
1890
1891/**
1892 * port_r16 - read word from port register.
1893 * @hw: The hardware instance.
1894 * @port: The port index.
1895 * @offset: The offset of the port register.
1896 * @data: Buffer to store the data.
1897 *
1898 * This routine reads a word from the port register.
1899 */
1900static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
1901{
1902 u32 addr;
1903
1904 PORT_CTRL_ADDR(port, addr);
1905 addr += offset;
1906 *data = readw(hw->io + addr);
1907}
1908
1909/**
1910 * port_w16 - write word to port register.
1911 * @hw: The hardware instance.
1912 * @port: The port index.
1913 * @offset: The offset of the port register.
1914 * @data: Data to write.
1915 *
1916 * This routine writes a word to the port register.
1917 */
1918static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
1919{
1920 u32 addr;
1921
1922 PORT_CTRL_ADDR(port, addr);
1923 addr += offset;
1924 writew(data, hw->io + addr);
1925}
1926
1927/**
1928 * sw_chk - check switch register bits
1929 * @hw: The hardware instance.
1930 * @addr: The address of the switch register.
1931 * @bits: The data bits to check.
1932 *
1933 * This function checks whether the specified bits of the switch register are
1934 * set or not.
1935 *
1936 * Return 0 if the bits are not set.
1937 */
1938static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
1939{
1940 u16 data;
1941
1942 data = readw(hw->io + addr);
1943 return (data & bits) == bits;
1944}
1945
1946/**
1947 * sw_cfg - set switch register bits
1948 * @hw: The hardware instance.
1949 * @addr: The address of the switch register.
1950 * @bits: The data bits to set.
1951 * @set: The flag indicating whether the bits are to be set or not.
1952 *
1953 * This function sets or resets the specified bits of the switch register.
1954 */
1955static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
1956{
1957 u16 data;
1958
1959 data = readw(hw->io + addr);
1960 if (set)
1961 data |= bits;
1962 else
1963 data &= ~bits;
1964 writew(data, hw->io + addr);
1965}
1966
1967/* Bandwidth */
1968
1969static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
1970{
1971 port_cfg(hw, p,
1972 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
1973}
1974
1975/* Driver set switch broadcast storm protection at 10% rate. */
1976#define BROADCAST_STORM_PROTECTION_RATE 10
1977
1978/* 148,800 frames * 67 ms / 100 */
1979#define BROADCAST_STORM_VALUE 9969
1980
1981/**
1982 * sw_cfg_broad_storm - configure broadcast storm threshold
1983 * @hw: The hardware instance.
1984 * @percent: Broadcast storm threshold in percent of transmit rate.
1985 *
1986 * This routine configures the broadcast storm threshold of the switch.
1987 */
1988static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
1989{
1990 u16 data;
1991 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
1992
1993 if (value > BROADCAST_STORM_RATE)
1994 value = BROADCAST_STORM_RATE;
1995
1996 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
1997 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
1998 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
1999 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2000}
2001
2002/**
2003 * sw_get_broad_storm - get broadcast storm threshold
2004 * @hw: The hardware instance.
2005 * @percent: Buffer to store the broadcast storm threshold percentage.
2006 *
2007 * This routine retrieves the broadcast storm threshold of the switch.
2008 */
2009static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2010{
2011 int num;
2012 u16 data;
2013
2014 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2015 num = (data & BROADCAST_STORM_RATE_HI);
2016 num <<= 8;
2017 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2018 num = DIV_ROUND_CLOSEST(num * 100, BROADCAST_STORM_VALUE);
2019 *percent = (u8) num;
2020}
2021
2022/**
2023 * sw_dis_broad_storm - disable broadstorm
2024 * @hw: The hardware instance.
2025 * @port: The port index.
2026 *
2027 * This routine disables the broadcast storm limit function of the switch.
2028 */
2029static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2030{
2031 port_cfg_broad_storm(hw, port, 0);
2032}
2033
2034/**
2035 * sw_ena_broad_storm - enable broadcast storm
2036 * @hw: The hardware instance.
2037 * @port: The port index.
2038 *
2039 * This routine enables the broadcast storm limit function of the switch.
2040 */
2041static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2042{
2043 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2044 port_cfg_broad_storm(hw, port, 1);
2045}
2046
2047/**
2048 * sw_init_broad_storm - initialize broadcast storm
2049 * @hw: The hardware instance.
2050 *
2051 * This routine initializes the broadcast storm limit function of the switch.
2052 */
2053static void sw_init_broad_storm(struct ksz_hw *hw)
2054{
2055 int port;
2056
2057 hw->ksz_switch->broad_per = 1;
2058 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2059 for (port = 0; port < TOTAL_PORT_NUM; port++)
2060 sw_dis_broad_storm(hw, port);
2061 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2062}
2063
2064/**
2065 * hw_cfg_broad_storm - configure broadcast storm
2066 * @hw: The hardware instance.
2067 * @percent: Broadcast storm threshold in percent of transmit rate.
2068 *
2069 * This routine configures the broadcast storm threshold of the switch.
2070 * It is called by user functions. The hardware should be acquired first.
2071 */
2072static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2073{
2074 if (percent > 100)
2075 percent = 100;
2076
2077 sw_cfg_broad_storm(hw, percent);
2078 sw_get_broad_storm(hw, &percent);
2079 hw->ksz_switch->broad_per = percent;
2080}
2081
2082/**
2083 * sw_dis_prio_rate - disable switch priority rate
2084 * @hw: The hardware instance.
2085 * @port: The port index.
2086 *
2087 * This routine disables the priority rate function of the switch.
2088 */
2089static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2090{
2091 u32 addr;
2092
2093 PORT_CTRL_ADDR(port, addr);
2094 addr += KS8842_PORT_IN_RATE_OFFSET;
2095 writel(0, hw->io + addr);
2096}
2097
2098/**
2099 * sw_init_prio_rate - initialize switch prioirty rate
2100 * @hw: The hardware instance.
2101 *
2102 * This routine initializes the priority rate function of the switch.
2103 */
2104static void sw_init_prio_rate(struct ksz_hw *hw)
2105{
2106 int port;
2107 int prio;
2108 struct ksz_switch *sw = hw->ksz_switch;
2109
2110 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2111 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2112 sw->port_cfg[port].rx_rate[prio] =
2113 sw->port_cfg[port].tx_rate[prio] = 0;
2114 }
2115 sw_dis_prio_rate(hw, port);
2116 }
2117}
2118
2119/* Communication */
2120
2121static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2122{
2123 port_cfg(hw, p,
2124 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2125}
2126
2127/* Mirroring */
2128
2129static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2130{
2131 port_cfg(hw, p,
2132 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2133}
2134
2135static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2136{
2137 port_cfg(hw, p,
2138 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2139}
2140
2141static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2142{
2143 port_cfg(hw, p,
2144 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2145}
2146
2147static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2148{
2149 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2150}
2151
2152static void sw_init_mirror(struct ksz_hw *hw)
2153{
2154 int port;
2155
2156 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2157 port_cfg_mirror_sniffer(hw, port, 0);
2158 port_cfg_mirror_rx(hw, port, 0);
2159 port_cfg_mirror_tx(hw, port, 0);
2160 }
2161 sw_cfg_mirror_rx_tx(hw, 0);
2162}
2163
2164/* Priority */
2165
2166static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2167{
2168 port_cfg(hw, p,
2169 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2170}
2171
2172static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2173{
2174 port_cfg(hw, p,
2175 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2176}
2177
2178static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2179{
2180 port_cfg(hw, p,
2181 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2182}
2183
2184static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2185{
2186 port_cfg(hw, p,
2187 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2188}
2189
2190/**
2191 * sw_dis_diffserv - disable switch DiffServ priority
2192 * @hw: The hardware instance.
2193 * @port: The port index.
2194 *
2195 * This routine disables the DiffServ priority function of the switch.
2196 */
2197static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2198{
2199 port_cfg_diffserv(hw, port, 0);
2200}
2201
2202/**
2203 * sw_dis_802_1p - disable switch 802.1p priority
2204 * @hw: The hardware instance.
2205 * @port: The port index.
2206 *
2207 * This routine disables the 802.1p priority function of the switch.
2208 */
2209static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2210{
2211 port_cfg_802_1p(hw, port, 0);
2212}
2213
2214/**
2215 * sw_cfg_replace_null_vid -
2216 * @hw: The hardware instance.
2217 * @set: The flag to disable or enable.
2218 *
2219 */
2220static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2221{
2222 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2223}
2224
2225/**
2226 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2227 * @hw: The hardware instance.
2228 * @port: The port index.
2229 * @set: The flag to disable or enable.
2230 *
2231 * This routine enables the 802.1p priority re-mapping function of the switch.
2232 * That allows 802.1p priority field to be replaced with the port's default
2233 * tag's priority value if the ingress packet's 802.1p priority has a higher
2234 * priority than port's default tag's priority.
2235 */
2236static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2237{
2238 port_cfg_replace_vid(hw, port, set);
2239}
2240
2241/**
2242 * sw_cfg_port_based - configure switch port based priority
2243 * @hw: The hardware instance.
2244 * @port: The port index.
2245 * @prio: The priority to set.
2246 *
2247 * This routine configures the port based priority of the switch.
2248 */
2249static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2250{
2251 u16 data;
2252
2253 if (prio > PORT_BASED_PRIORITY_BASE)
2254 prio = PORT_BASED_PRIORITY_BASE;
2255
2256 hw->ksz_switch->port_cfg[port].port_prio = prio;
2257
2258 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2259 data &= ~PORT_BASED_PRIORITY_MASK;
2260 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2261 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2262}
2263
2264/**
2265 * sw_dis_multi_queue - disable transmit multiple queues
2266 * @hw: The hardware instance.
2267 * @port: The port index.
2268 *
2269 * This routine disables the transmit multiple queues selection of the switch
2270 * port. Only single transmit queue on the port.
2271 */
2272static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2273{
2274 port_cfg_prio(hw, port, 0);
2275}
2276
2277/**
2278 * sw_init_prio - initialize switch priority
2279 * @hw: The hardware instance.
2280 *
2281 * This routine initializes the switch QoS priority functions.
2282 */
2283static void sw_init_prio(struct ksz_hw *hw)
2284{
2285 int port;
2286 int tos;
2287 struct ksz_switch *sw = hw->ksz_switch;
2288
2289 /*
2290 * Init all the 802.1p tag priority value to be assigned to different
2291 * priority queue.
2292 */
2293 sw->p_802_1p[0] = 0;
2294 sw->p_802_1p[1] = 0;
2295 sw->p_802_1p[2] = 1;
2296 sw->p_802_1p[3] = 1;
2297 sw->p_802_1p[4] = 2;
2298 sw->p_802_1p[5] = 2;
2299 sw->p_802_1p[6] = 3;
2300 sw->p_802_1p[7] = 3;
2301
2302 /*
2303 * Init all the DiffServ priority value to be assigned to priority
2304 * queue 0.
2305 */
2306 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2307 sw->diffserv[tos] = 0;
2308
2309 /* All QoS functions disabled. */
2310 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2311 sw_dis_multi_queue(hw, port);
2312 sw_dis_diffserv(hw, port);
2313 sw_dis_802_1p(hw, port);
2314 sw_cfg_replace_vid(hw, port, 0);
2315
2316 sw->port_cfg[port].port_prio = 0;
2317 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2318 }
2319 sw_cfg_replace_null_vid(hw, 0);
2320}
2321
2322/**
2323 * port_get_def_vid - get port default VID.
2324 * @hw: The hardware instance.
2325 * @port: The port index.
2326 * @vid: Buffer to store the VID.
2327 *
2328 * This routine retrieves the default VID of the port.
2329 */
2330static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2331{
2332 u32 addr;
2333
2334 PORT_CTRL_ADDR(port, addr);
2335 addr += KS8842_PORT_CTRL_VID_OFFSET;
2336 *vid = readw(hw->io + addr);
2337}
2338
2339/**
2340 * sw_init_vlan - initialize switch VLAN
2341 * @hw: The hardware instance.
2342 *
2343 * This routine initializes the VLAN function of the switch.
2344 */
2345static void sw_init_vlan(struct ksz_hw *hw)
2346{
2347 int port;
2348 int entry;
2349 struct ksz_switch *sw = hw->ksz_switch;
2350
2351 /* Read 16 VLAN entries from device's VLAN table. */
2352 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2353 sw_r_vlan_table(hw, entry,
2354 &sw->vlan_table[entry].vid,
2355 &sw->vlan_table[entry].fid,
2356 &sw->vlan_table[entry].member);
2357 }
2358
2359 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2360 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2361 sw->port_cfg[port].member = PORT_MASK;
2362 }
2363}
2364
2365/**
2366 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2367 * @hw: The hardware instance.
2368 * @port: The port index.
2369 * @member: The port-based VLAN membership.
2370 *
2371 * This routine configures the port-based VLAN membership of the port.
2372 */
2373static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2374{
2375 u32 addr;
2376 u8 data;
2377
2378 PORT_CTRL_ADDR(port, addr);
2379 addr += KS8842_PORT_CTRL_2_OFFSET;
2380
2381 data = readb(hw->io + addr);
2382 data &= ~PORT_VLAN_MEMBERSHIP;
2383 data |= (member & PORT_MASK);
2384 writeb(data, hw->io + addr);
2385
2386 hw->ksz_switch->port_cfg[port].member = member;
2387}
2388
2389/**
2390 * sw_set_addr - configure switch MAC address
2391 * @hw: The hardware instance.
2392 * @mac_addr: The MAC address.
2393 *
2394 * This function configures the MAC address of the switch.
2395 */
2396static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2397{
2398 int i;
2399
2400 for (i = 0; i < 6; i += 2) {
2401 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2402 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2403 }
2404}
2405
2406/**
2407 * sw_set_global_ctrl - set switch global control
2408 * @hw: The hardware instance.
2409 *
2410 * This routine sets the global control of the switch function.
2411 */
2412static void sw_set_global_ctrl(struct ksz_hw *hw)
2413{
2414 u16 data;
2415
2416 /* Enable switch MII flow control. */
2417 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2418 data |= SWITCH_FLOW_CTRL;
2419 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2420
2421 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2422
2423 /* Enable aggressive back off algorithm in half duplex mode. */
2424 data |= SWITCH_AGGR_BACKOFF;
2425
2426 /* Enable automatic fast aging when link changed detected. */
2427 data |= SWITCH_AGING_ENABLE;
2428 data |= SWITCH_LINK_AUTO_AGING;
2429
2430 if (hw->overrides & FAST_AGING)
2431 data |= SWITCH_FAST_AGING;
2432 else
2433 data &= ~SWITCH_FAST_AGING;
2434 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2435
2436 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2437
2438 /* Enable no excessive collision drop. */
2439 data |= NO_EXC_COLLISION_DROP;
2440 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2441}
2442
2443enum {
2444 STP_STATE_DISABLED = 0,
2445 STP_STATE_LISTENING,
2446 STP_STATE_LEARNING,
2447 STP_STATE_FORWARDING,
2448 STP_STATE_BLOCKED,
2449 STP_STATE_SIMPLE
2450};
2451
2452/**
2453 * port_set_stp_state - configure port spanning tree state
2454 * @hw: The hardware instance.
2455 * @port: The port index.
2456 * @state: The spanning tree state.
2457 *
2458 * This routine configures the spanning tree state of the port.
2459 */
2460static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2461{
2462 u16 data;
2463
2464 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2465 switch (state) {
2466 case STP_STATE_DISABLED:
2467 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2468 data |= PORT_LEARN_DISABLE;
2469 break;
2470 case STP_STATE_LISTENING:
2471/*
2472 * No need to turn on transmit because of port direct mode.
2473 * Turning on receive is required if static MAC table is not setup.
2474 */
2475 data &= ~PORT_TX_ENABLE;
2476 data |= PORT_RX_ENABLE;
2477 data |= PORT_LEARN_DISABLE;
2478 break;
2479 case STP_STATE_LEARNING:
2480 data &= ~PORT_TX_ENABLE;
2481 data |= PORT_RX_ENABLE;
2482 data &= ~PORT_LEARN_DISABLE;
2483 break;
2484 case STP_STATE_FORWARDING:
2485 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2486 data &= ~PORT_LEARN_DISABLE;
2487 break;
2488 case STP_STATE_BLOCKED:
2489/*
2490 * Need to setup static MAC table with override to keep receiving BPDU
2491 * messages. See sw_init_stp routine.
2492 */
2493 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2494 data |= PORT_LEARN_DISABLE;
2495 break;
2496 case STP_STATE_SIMPLE:
2497 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2498 data |= PORT_LEARN_DISABLE;
2499 break;
2500 }
2501 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2502 hw->ksz_switch->port_cfg[port].stp_state = state;
2503}
2504
2505#define STP_ENTRY 0
2506#define BROADCAST_ENTRY 1
2507#define BRIDGE_ADDR_ENTRY 2
2508#define IPV6_ADDR_ENTRY 3
2509
2510/**
2511 * sw_clr_sta_mac_table - clear static MAC table
2512 * @hw: The hardware instance.
2513 *
2514 * This routine clears the static MAC table.
2515 */
2516static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2517{
2518 struct ksz_mac_table *entry;
2519 int i;
2520
2521 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2522 entry = &hw->ksz_switch->mac_table[i];
2523 sw_w_sta_mac_table(hw, i,
2524 entry->mac_addr, entry->ports,
2525 entry->override, 0,
2526 entry->use_fid, entry->fid);
2527 }
2528}
2529
2530/**
2531 * sw_init_stp - initialize switch spanning tree support
2532 * @hw: The hardware instance.
2533 *
2534 * This routine initializes the spanning tree support of the switch.
2535 */
2536static void sw_init_stp(struct ksz_hw *hw)
2537{
2538 struct ksz_mac_table *entry;
2539
2540 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2541 entry->mac_addr[0] = 0x01;
2542 entry->mac_addr[1] = 0x80;
2543 entry->mac_addr[2] = 0xC2;
2544 entry->mac_addr[3] = 0x00;
2545 entry->mac_addr[4] = 0x00;
2546 entry->mac_addr[5] = 0x00;
2547 entry->ports = HOST_MASK;
2548 entry->override = 1;
2549 entry->valid = 1;
2550 sw_w_sta_mac_table(hw, STP_ENTRY,
2551 entry->mac_addr, entry->ports,
2552 entry->override, entry->valid,
2553 entry->use_fid, entry->fid);
2554}
2555
2556/**
2557 * sw_block_addr - block certain packets from the host port
2558 * @hw: The hardware instance.
2559 *
2560 * This routine blocks certain packets from reaching to the host port.
2561 */
2562static void sw_block_addr(struct ksz_hw *hw)
2563{
2564 struct ksz_mac_table *entry;
2565 int i;
2566
2567 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2568 entry = &hw->ksz_switch->mac_table[i];
2569 entry->valid = 0;
2570 sw_w_sta_mac_table(hw, i,
2571 entry->mac_addr, entry->ports,
2572 entry->override, entry->valid,
2573 entry->use_fid, entry->fid);
2574 }
2575}
2576
2577static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2578{
2579 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2580}
2581
2582static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2583{
2584 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2585}
2586
2587/**
2588 * hw_r_phy - read data from PHY register
2589 * @hw: The hardware instance.
2590 * @port: Port to read.
2591 * @reg: PHY register to read.
2592 * @val: Buffer to store the read data.
2593 *
2594 * This routine reads data from the PHY register.
2595 */
2596static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2597{
2598 int phy;
2599
2600 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2601 *val = readw(hw->io + phy);
2602}
2603
2604/**
2605 * hw_w_phy - write data to PHY register
2606 * @hw: The hardware instance.
2607 * @port: Port to write.
2608 * @reg: PHY register to write.
2609 * @val: Word data to write.
2610 *
2611 * This routine writes data to the PHY register.
2612 */
2613static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
2614{
2615 int phy;
2616
2617 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2618 writew(val, hw->io + phy);
2619}
2620
2621/*
2622 * EEPROM access functions
2623 */
2624
2625#define AT93C_CODE 0
2626#define AT93C_WR_OFF 0x00
2627#define AT93C_WR_ALL 0x10
2628#define AT93C_ER_ALL 0x20
2629#define AT93C_WR_ON 0x30
2630
2631#define AT93C_WRITE 1
2632#define AT93C_READ 2
2633#define AT93C_ERASE 3
2634
2635#define EEPROM_DELAY 4
2636
2637static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
2638{
2639 u16 data;
2640
2641 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
2642 data &= ~gpio;
2643 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
2644}
2645
2646static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
2647{
2648 u16 data;
2649
2650 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
2651 data |= gpio;
2652 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
2653}
2654
2655static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
2656{
2657 u16 data;
2658
2659 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
2660 return (u8)(data & gpio);
2661}
2662
2663static void eeprom_clk(struct ksz_hw *hw)
2664{
2665 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
2666 udelay(EEPROM_DELAY);
2667 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
2668 udelay(EEPROM_DELAY);
2669}
2670
2671static u16 spi_r(struct ksz_hw *hw)
2672{
2673 int i;
2674 u16 temp = 0;
2675
2676 for (i = 15; i >= 0; i--) {
2677 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
2678 udelay(EEPROM_DELAY);
2679
2680 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
2681
2682 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
2683 udelay(EEPROM_DELAY);
2684 }
2685 return temp;
2686}
2687
2688static void spi_w(struct ksz_hw *hw, u16 data)
2689{
2690 int i;
2691
2692 for (i = 15; i >= 0; i--) {
2693 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
2694 drop_gpio(hw, EEPROM_DATA_OUT);
2695 eeprom_clk(hw);
2696 }
2697}
2698
2699static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
2700{
2701 int i;
2702
2703 /* Initial start bit */
2704 raise_gpio(hw, EEPROM_DATA_OUT);
2705 eeprom_clk(hw);
2706
2707 /* AT93C operation */
2708 for (i = 1; i >= 0; i--) {
2709 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
2710 drop_gpio(hw, EEPROM_DATA_OUT);
2711 eeprom_clk(hw);
2712 }
2713
2714 /* Address location */
2715 for (i = 5; i >= 0; i--) {
2716 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
2717 drop_gpio(hw, EEPROM_DATA_OUT);
2718 eeprom_clk(hw);
2719 }
2720}
2721
2722#define EEPROM_DATA_RESERVED 0
2723#define EEPROM_DATA_MAC_ADDR_0 1
2724#define EEPROM_DATA_MAC_ADDR_1 2
2725#define EEPROM_DATA_MAC_ADDR_2 3
2726#define EEPROM_DATA_SUBSYS_ID 4
2727#define EEPROM_DATA_SUBSYS_VEN_ID 5
2728#define EEPROM_DATA_PM_CAP 6
2729
2730/* User defined EEPROM data */
2731#define EEPROM_DATA_OTHER_MAC_ADDR 9
2732
2733/**
2734 * eeprom_read - read from AT93C46 EEPROM
2735 * @hw: The hardware instance.
2736 * @reg: The register offset.
2737 *
2738 * This function reads a word from the AT93C46 EEPROM.
2739 *
2740 * Return the data value.
2741 */
2742static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
2743{
2744 u16 data;
2745
2746 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
2747
2748 spi_reg(hw, AT93C_READ, reg);
2749 data = spi_r(hw);
2750
2751 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
2752
2753 return data;
2754}
2755
2756/**
2757 * eeprom_write - write to AT93C46 EEPROM
2758 * @hw: The hardware instance.
2759 * @reg: The register offset.
2760 * @data: The data value.
2761 *
2762 * This procedure writes a word to the AT93C46 EEPROM.
2763 */
2764static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
2765{
2766 int timeout;
2767
2768 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
2769
2770 /* Enable write. */
2771 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
2772 drop_gpio(hw, EEPROM_CHIP_SELECT);
2773 udelay(1);
2774
2775 /* Erase the register. */
2776 raise_gpio(hw, EEPROM_CHIP_SELECT);
2777 spi_reg(hw, AT93C_ERASE, reg);
2778 drop_gpio(hw, EEPROM_CHIP_SELECT);
2779 udelay(1);
2780
2781 /* Check operation complete. */
2782 raise_gpio(hw, EEPROM_CHIP_SELECT);
2783 timeout = 8;
2784 mdelay(2);
2785 do {
2786 mdelay(1);
2787 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
2788 drop_gpio(hw, EEPROM_CHIP_SELECT);
2789 udelay(1);
2790
2791 /* Write the register. */
2792 raise_gpio(hw, EEPROM_CHIP_SELECT);
2793 spi_reg(hw, AT93C_WRITE, reg);
2794 spi_w(hw, data);
2795 drop_gpio(hw, EEPROM_CHIP_SELECT);
2796 udelay(1);
2797
2798 /* Check operation complete. */
2799 raise_gpio(hw, EEPROM_CHIP_SELECT);
2800 timeout = 8;
2801 mdelay(2);
2802 do {
2803 mdelay(1);
2804 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
2805 drop_gpio(hw, EEPROM_CHIP_SELECT);
2806 udelay(1);
2807
2808 /* Disable write. */
2809 raise_gpio(hw, EEPROM_CHIP_SELECT);
2810 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
2811
2812 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
2813}
2814
2815/*
2816 * Link detection routines
2817 */
2818
2819static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
2820{
2821 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
2822 switch (port->flow_ctrl) {
2823 case PHY_FLOW_CTRL:
2824 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
2825 break;
2826 /* Not supported. */
2827 case PHY_TX_ONLY:
2828 case PHY_RX_ONLY:
2829 default:
2830 break;
2831 }
2832 return ctrl;
2833}
2834
2835static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
2836{
2837 u32 rx_cfg;
2838 u32 tx_cfg;
2839
2840 rx_cfg = hw->rx_cfg;
2841 tx_cfg = hw->tx_cfg;
2842 if (rx)
2843 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
2844 else
2845 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
2846 if (tx)
2847 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
2848 else
2849 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
2850 if (hw->enabled) {
2851 if (rx_cfg != hw->rx_cfg)
2852 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
2853 if (tx_cfg != hw->tx_cfg)
2854 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
2855 }
2856}
2857
2858static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
2859 u16 local, u16 remote)
2860{
2861 int rx;
2862 int tx;
2863
2864 if (hw->overrides & PAUSE_FLOW_CTRL)
2865 return;
2866
2867 rx = tx = 0;
2868 if (port->force_link)
2869 rx = tx = 1;
2870 if (remote & LPA_PAUSE_CAP) {
2871 if (local & ADVERTISE_PAUSE_CAP) {
2872 rx = tx = 1;
2873 } else if ((remote & LPA_PAUSE_ASYM) &&
2874 (local &
2875 (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) ==
2876 ADVERTISE_PAUSE_ASYM) {
2877 tx = 1;
2878 }
2879 } else if (remote & LPA_PAUSE_ASYM) {
2880 if ((local & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM))
2881 == (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM))
2882 rx = 1;
2883 }
2884 if (!hw->ksz_switch)
2885 set_flow_ctrl(hw, rx, tx);
2886}
2887
2888static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
2889 struct ksz_port_info *info, u16 link_status)
2890{
2891 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
2892 !(hw->overrides & PAUSE_FLOW_CTRL)) {
2893 u32 cfg = hw->tx_cfg;
2894
2895 /* Disable flow control in the half duplex mode. */
2896 if (1 == info->duplex)
2897 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
2898 if (hw->enabled && cfg != hw->tx_cfg)
2899 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
2900 }
2901}
2902
2903/**
2904 * port_get_link_speed - get current link status
2905 * @port: The port instance.
2906 *
2907 * This routine reads PHY registers to determine the current link status of the
2908 * switch ports.
2909 */
2910static void port_get_link_speed(struct ksz_port *port)
2911{
2912 uint interrupt;
2913 struct ksz_port_info *info;
2914 struct ksz_port_info *linked = NULL;
2915 struct ksz_hw *hw = port->hw;
2916 u16 data;
2917 u16 status;
2918 u8 local;
2919 u8 remote;
2920 int i;
2921 int p;
2922
2923 interrupt = hw_block_intr(hw);
2924
2925 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
2926 info = &hw->port_info[p];
2927 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
2928 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
2929
2930 /*
2931 * Link status is changing all the time even when there is no
2932 * cable connection!
2933 */
2934 remote = status & (PORT_AUTO_NEG_COMPLETE |
2935 PORT_STATUS_LINK_GOOD);
2936 local = (u8) data;
2937
2938 /* No change to status. */
2939 if (local == info->advertised && remote == info->partner)
2940 continue;
2941
2942 info->advertised = local;
2943 info->partner = remote;
2944 if (status & PORT_STATUS_LINK_GOOD) {
2945
2946 /* Remember the first linked port. */
2947 if (!linked)
2948 linked = info;
2949
2950 info->tx_rate = 10 * TX_RATE_UNIT;
2951 if (status & PORT_STATUS_SPEED_100MBIT)
2952 info->tx_rate = 100 * TX_RATE_UNIT;
2953
2954 info->duplex = 1;
2955 if (status & PORT_STATUS_FULL_DUPLEX)
2956 info->duplex = 2;
2957
2958 if (media_connected != info->state) {
2959 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
2960 &data);
2961 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
2962 &status);
2963 determine_flow_ctrl(hw, port, data, status);
2964 if (hw->ksz_switch) {
2965 port_cfg_back_pressure(hw, p,
2966 (1 == info->duplex));
2967 }
2968 port_cfg_change(hw, port, info, status);
2969 }
2970 info->state = media_connected;
2971 } else {
2972 /* Indicate the link just goes down. */
2973 if (media_disconnected != info->state)
2974 hw->port_mib[p].link_down = 1;
2975
2976 info->state = media_disconnected;
2977 }
2978 hw->port_mib[p].state = (u8) info->state;
2979 }
2980
2981 if (linked && media_disconnected == port->linked->state)
2982 port->linked = linked;
2983
2984 hw_restore_intr(hw, interrupt);
2985}
2986
2987#define PHY_RESET_TIMEOUT 10
2988
2989/**
2990 * port_set_link_speed - set port speed
2991 * @port: The port instance.
2992 *
2993 * This routine sets the link speed of the switch ports.
2994 */
2995static void port_set_link_speed(struct ksz_port *port)
2996{
2997 struct ksz_hw *hw = port->hw;
2998 u16 data;
2999 u16 cfg;
3000 u8 status;
3001 int i;
3002 int p;
3003
3004 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3005 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3006 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3007
3008 cfg = 0;
3009 if (status & PORT_STATUS_LINK_GOOD)
3010 cfg = data;
3011
3012 data |= PORT_AUTO_NEG_ENABLE;
3013 data = advertised_flow_ctrl(port, data);
3014
3015 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3016 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3017
3018 /* Check if manual configuration is specified by the user. */
3019 if (port->speed || port->duplex) {
3020 if (10 == port->speed)
3021 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3022 PORT_AUTO_NEG_100BTX);
3023 else if (100 == port->speed)
3024 data &= ~(PORT_AUTO_NEG_10BT_FD |
3025 PORT_AUTO_NEG_10BT);
3026 if (1 == port->duplex)
3027 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3028 PORT_AUTO_NEG_10BT_FD);
3029 else if (2 == port->duplex)
3030 data &= ~(PORT_AUTO_NEG_100BTX |
3031 PORT_AUTO_NEG_10BT);
3032 }
3033 if (data != cfg) {
3034 data |= PORT_AUTO_NEG_RESTART;
3035 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3036 }
3037 }
3038}
3039
3040/**
3041 * port_force_link_speed - force port speed
3042 * @port: The port instance.
3043 *
3044 * This routine forces the link speed of the switch ports.
3045 */
3046static void port_force_link_speed(struct ksz_port *port)
3047{
3048 struct ksz_hw *hw = port->hw;
3049 u16 data;
3050 int i;
3051 int phy;
3052 int p;
3053
3054 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3055 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3056 hw_r_phy_ctrl(hw, phy, &data);
3057
3058 data &= ~BMCR_ANENABLE;
3059
3060 if (10 == port->speed)
3061 data &= ~BMCR_SPEED100;
3062 else if (100 == port->speed)
3063 data |= BMCR_SPEED100;
3064 if (1 == port->duplex)
3065 data &= ~BMCR_FULLDPLX;
3066 else if (2 == port->duplex)
3067 data |= BMCR_FULLDPLX;
3068 hw_w_phy_ctrl(hw, phy, data);
3069 }
3070}
3071
3072static void port_set_power_saving(struct ksz_port *port, int enable)
3073{
3074 struct ksz_hw *hw = port->hw;
3075 int i;
3076 int p;
3077
3078 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3079 port_cfg(hw, p,
3080 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3081}
3082
3083/*
3084 * KSZ8841 power management functions
3085 */
3086
3087/**
3088 * hw_chk_wol_pme_status - check PMEN pin
3089 * @hw: The hardware instance.
3090 *
3091 * This function is used to check PMEN pin is asserted.
3092 *
3093 * Return 1 if PMEN pin is asserted; otherwise, 0.
3094 */
3095static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3096{
3097 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3098 struct pci_dev *pdev = hw_priv->pdev;
3099 u16 data;
3100
3101 if (!pdev->pm_cap)
3102 return 0;
3103 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3104 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3105}
3106
3107/**
3108 * hw_clr_wol_pme_status - clear PMEN pin
3109 * @hw: The hardware instance.
3110 *
3111 * This routine is used to clear PME_Status to deassert PMEN pin.
3112 */
3113static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3114{
3115 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3116 struct pci_dev *pdev = hw_priv->pdev;
3117 u16 data;
3118
3119 if (!pdev->pm_cap)
3120 return;
3121
3122 /* Clear PME_Status to deassert PMEN pin. */
3123 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3124 data |= PCI_PM_CTRL_PME_STATUS;
3125 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3126}
3127
3128/**
3129 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3130 * @hw: The hardware instance.
3131 * @set: The flag indicating whether to enable or disable.
3132 *
3133 * This routine is used to enable or disable Wake-on-LAN.
3134 */
3135static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3136{
3137 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3138 struct pci_dev *pdev = hw_priv->pdev;
3139 u16 data;
3140
3141 if (!pdev->pm_cap)
3142 return;
3143 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3144 data &= ~PCI_PM_CTRL_STATE_MASK;
3145 if (set)
3146 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3147 else
3148 data &= ~PCI_PM_CTRL_PME_ENABLE;
3149 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3150}
3151
3152/**
3153 * hw_cfg_wol - configure Wake-on-LAN features
3154 * @hw: The hardware instance.
3155 * @frame: The pattern frame bit.
3156 * @set: The flag indicating whether to enable or disable.
3157 *
3158 * This routine is used to enable or disable certain Wake-on-LAN features.
3159 */
3160static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3161{
3162 u16 data;
3163
3164 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3165 if (set)
3166 data |= frame;
3167 else
3168 data &= ~frame;
3169 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3170}
3171
3172/**
3173 * hw_set_wol_frame - program Wake-on-LAN pattern
3174 * @hw: The hardware instance.
3175 * @i: The frame index.
3176 * @mask_size: The size of the mask.
3177 * @mask: Mask to ignore certain bytes in the pattern.
3178 * @frame_size: The size of the frame.
3179 * @pattern: The frame data.
3180 *
3181 * This routine is used to program Wake-on-LAN pattern.
3182 */
3183static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3184 const u8 *mask, uint frame_size, const u8 *pattern)
3185{
3186 int bits;
3187 int from;
3188 int len;
3189 int to;
3190 u32 crc;
3191 u8 data[64];
3192 u8 val = 0;
3193
3194 if (frame_size > mask_size * 8)
3195 frame_size = mask_size * 8;
3196 if (frame_size > 64)
3197 frame_size = 64;
3198
3199 i *= 0x10;
3200 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3201 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3202
3203 bits = len = from = to = 0;
3204 do {
3205 if (bits) {
3206 if ((val & 1))
3207 data[to++] = pattern[from];
3208 val >>= 1;
3209 ++from;
3210 --bits;
3211 } else {
3212 val = mask[len];
3213 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3214 + len);
3215 ++len;
3216 if (val)
3217 bits = 8;
3218 else
3219 from += 8;
3220 }
3221 } while (from < (int) frame_size);
3222 if (val) {
3223 bits = mask[len - 1];
3224 val <<= (from % 8);
3225 bits &= ~val;
3226 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3227 1);
3228 }
3229 crc = ether_crc(to, data);
3230 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3231}
3232
3233/**
3234 * hw_add_wol_arp - add ARP pattern
3235 * @hw: The hardware instance.
3236 * @ip_addr: The IPv4 address assigned to the device.
3237 *
3238 * This routine is used to add ARP pattern for waking up the host.
3239 */
3240static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
3241{
3242 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3243 u8 pattern[42] = {
3244 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3246 0x08, 0x06,
3247 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3248 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3249 0x00, 0x00, 0x00, 0x00,
3250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3251 0x00, 0x00, 0x00, 0x00 };
3252
3253 memcpy(&pattern[38], ip_addr, 4);
3254 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3255}
3256
3257/**
3258 * hw_add_wol_bcast - add broadcast pattern
3259 * @hw: The hardware instance.
3260 *
3261 * This routine is used to add broadcast pattern for waking up the host.
3262 */
3263static void hw_add_wol_bcast(struct ksz_hw *hw)
3264{
3265 static const u8 mask[] = { 0x3F };
3266 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3267
3268 hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern);
3269}
3270
3271/**
3272 * hw_add_wol_mcast - add multicast pattern
3273 * @hw: The hardware instance.
3274 *
3275 * This routine is used to add multicast pattern for waking up the host.
3276 *
3277 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3278 * by IPv6 ping command. Note that multicast packets are filtred through the
3279 * multicast hash table, so not all multicast packets can wake up the host.
3280 */
3281static void hw_add_wol_mcast(struct ksz_hw *hw)
3282{
3283 static const u8 mask[] = { 0x3F };
3284 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3285
3286 memcpy(&pattern[3], &hw->override_addr[3], 3);
3287 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3288}
3289
3290/**
3291 * hw_add_wol_ucast - add unicast pattern
3292 * @hw: The hardware instance.
3293 *
3294 * This routine is used to add unicast pattern to wakeup the host.
3295 *
3296 * It is assumed the unicast packet is directed to the device, as the hardware
3297 * can only receive them in normal case.
3298 */
3299static void hw_add_wol_ucast(struct ksz_hw *hw)
3300{
3301 static const u8 mask[] = { 0x3F };
3302
3303 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr);
3304}
3305
3306/**
3307 * hw_enable_wol - enable Wake-on-LAN
3308 * @hw: The hardware instance.
3309 * @wol_enable: The Wake-on-LAN settings.
3310 * @net_addr: The IPv4 address assigned to the device.
3311 *
3312 * This routine is used to enable Wake-on-LAN depending on driver settings.
3313 */
3314static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
3315{
3316 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3317 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3318 hw_add_wol_ucast(hw);
3319 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3320 hw_add_wol_mcast(hw);
3321 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3322 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3323 hw_add_wol_arp(hw, net_addr);
3324}
3325
3326/**
3327 * hw_init - check driver is correct for the hardware
3328 * @hw: The hardware instance.
3329 *
3330 * This function checks the hardware is correct for this driver and sets the
3331 * hardware up for proper initialization.
3332 *
3333 * Return number of ports or 0 if not right.
3334 */
3335static int hw_init(struct ksz_hw *hw)
3336{
3337 int rc = 0;
3338 u16 data;
3339 u16 revision;
3340
3341 /* Set bus speed to 125MHz. */
3342 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3343
3344 /* Check KSZ884x chip ID. */
3345 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3346
3347 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3348 data &= KS884X_CHIP_ID_MASK_41;
3349 if (REG_CHIP_ID_41 == data)
3350 rc = 1;
3351 else if (REG_CHIP_ID_42 == data)
3352 rc = 2;
3353 else
3354 return 0;
3355
3356 /* Setup hardware features or bug workarounds. */
3357 if (revision <= 1) {
3358 hw->features |= SMALL_PACKET_TX_BUG;
3359 if (1 == rc)
3360 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3361 }
3362 return rc;
3363}
3364
3365/**
3366 * hw_reset - reset the hardware
3367 * @hw: The hardware instance.
3368 *
3369 * This routine resets the hardware.
3370 */
3371static void hw_reset(struct ksz_hw *hw)
3372{
3373 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3374
3375 /* Wait for device to reset. */
3376 mdelay(10);
3377
3378 /* Write 0 to clear device reset. */
3379 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3380}
3381
3382/**
3383 * hw_setup - setup the hardware
3384 * @hw: The hardware instance.
3385 *
3386 * This routine setup the hardware for proper operation.
3387 */
3388static void hw_setup(struct ksz_hw *hw)
3389{
3390#if SET_DEFAULT_LED
3391 u16 data;
3392
3393 /* Change default LED mode. */
3394 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3395 data &= ~LED_MODE;
3396 data |= SET_DEFAULT_LED;
3397 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3398#endif
3399
3400 /* Setup transmit control. */
3401 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3402 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3403
3404 /* Setup receive control. */
3405 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3406 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3407 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3408
3409 /* Hardware cannot handle UDP packet in IP fragments. */
3410 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3411
3412 if (hw->all_multi)
3413 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3414 if (hw->promiscuous)
3415 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3416}
3417
3418/**
3419 * hw_setup_intr - setup interrupt mask
3420 * @hw: The hardware instance.
3421 *
3422 * This routine setup the interrupt mask for proper operation.
3423 */
3424static void hw_setup_intr(struct ksz_hw *hw)
3425{
3426 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3427}
3428
3429static void ksz_check_desc_num(struct ksz_desc_info *info)
3430{
3431#define MIN_DESC_SHIFT 2
3432
3433 int alloc = info->alloc;
3434 int shift;
3435
3436 shift = 0;
3437 while (!(alloc & 1)) {
3438 shift++;
3439 alloc >>= 1;
3440 }
3441 if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3442 pr_alert("Hardware descriptor numbers not right!\n");
3443 while (alloc) {
3444 shift++;
3445 alloc >>= 1;
3446 }
3447 if (shift < MIN_DESC_SHIFT)
3448 shift = MIN_DESC_SHIFT;
3449 alloc = 1 << shift;
3450 info->alloc = alloc;
3451 }
3452 info->mask = info->alloc - 1;
3453}
3454
3455static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3456{
3457 int i;
3458 u32 phys = desc_info->ring_phys;
3459 struct ksz_hw_desc *desc = desc_info->ring_virt;
3460 struct ksz_desc *cur = desc_info->ring;
3461 struct ksz_desc *previous = NULL;
3462
3463 for (i = 0; i < desc_info->alloc; i++) {
3464 cur->phw = desc++;
3465 phys += desc_info->size;
3466 previous = cur++;
3467 previous->phw->next = cpu_to_le32(phys);
3468 }
3469 previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3470 previous->sw.buf.rx.end_of_ring = 1;
3471 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3472
3473 desc_info->avail = desc_info->alloc;
3474 desc_info->last = desc_info->next = 0;
3475
3476 desc_info->cur = desc_info->ring;
3477}
3478
3479/**
3480 * hw_set_desc_base - set descriptor base addresses
3481 * @hw: The hardware instance.
3482 * @tx_addr: The transmit descriptor base.
3483 * @rx_addr: The receive descriptor base.
3484 *
3485 * This routine programs the descriptor base addresses after reset.
3486 */
3487static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3488{
3489 /* Set base address of Tx/Rx descriptors. */
3490 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3491 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3492}
3493
3494static void hw_reset_pkts(struct ksz_desc_info *info)
3495{
3496 info->cur = info->ring;
3497 info->avail = info->alloc;
3498 info->last = info->next = 0;
3499}
3500
3501static inline void hw_resume_rx(struct ksz_hw *hw)
3502{
3503 writel(DMA_START, hw->io + KS_DMA_RX_START);
3504}
3505
3506/**
3507 * hw_start_rx - start receiving
3508 * @hw: The hardware instance.
3509 *
3510 * This routine starts the receive function of the hardware.
3511 */
3512static void hw_start_rx(struct ksz_hw *hw)
3513{
3514 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3515
3516 /* Notify when the receive stops. */
3517 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3518
3519 writel(DMA_START, hw->io + KS_DMA_RX_START);
3520 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3521 hw->rx_stop++;
3522
3523 /* Variable overflows. */
3524 if (0 == hw->rx_stop)
3525 hw->rx_stop = 2;
3526}
3527
3528/**
3529 * hw_stop_rx - stop receiving
3530 * @hw: The hardware instance.
3531 *
3532 * This routine stops the receive function of the hardware.
3533 */
3534static void hw_stop_rx(struct ksz_hw *hw)
3535{
3536 hw->rx_stop = 0;
3537 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3538 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3539}
3540
3541/**
3542 * hw_start_tx - start transmitting
3543 * @hw: The hardware instance.
3544 *
3545 * This routine starts the transmit function of the hardware.
3546 */
3547static void hw_start_tx(struct ksz_hw *hw)
3548{
3549 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3550}
3551
3552/**
3553 * hw_stop_tx - stop transmitting
3554 * @hw: The hardware instance.
3555 *
3556 * This routine stops the transmit function of the hardware.
3557 */
3558static void hw_stop_tx(struct ksz_hw *hw)
3559{
3560 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3561}
3562
3563/**
3564 * hw_disable - disable hardware
3565 * @hw: The hardware instance.
3566 *
3567 * This routine disables the hardware.
3568 */
3569static void hw_disable(struct ksz_hw *hw)
3570{
3571 hw_stop_rx(hw);
3572 hw_stop_tx(hw);
3573 hw->enabled = 0;
3574}
3575
3576/**
3577 * hw_enable - enable hardware
3578 * @hw: The hardware instance.
3579 *
3580 * This routine enables the hardware.
3581 */
3582static void hw_enable(struct ksz_hw *hw)
3583{
3584 hw_start_tx(hw);
3585 hw_start_rx(hw);
3586 hw->enabled = 1;
3587}
3588
3589/**
3590 * hw_alloc_pkt - allocate enough descriptors for transmission
3591 * @hw: The hardware instance.
3592 * @length: The length of the packet.
3593 * @physical: Number of descriptors required.
3594 *
3595 * This function allocates descriptors for transmission.
3596 *
3597 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3598 */
3599static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3600{
3601 /* Always leave one descriptor free. */
3602 if (hw->tx_desc_info.avail <= 1)
3603 return 0;
3604
3605 /* Allocate a descriptor for transmission and mark it current. */
3606 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3607 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
3608
3609 /* Keep track of number of transmit descriptors used so far. */
3610 ++hw->tx_int_cnt;
3611 hw->tx_size += length;
3612
3613 /* Cannot hold on too much data. */
3614 if (hw->tx_size >= MAX_TX_HELD_SIZE)
3615 hw->tx_int_cnt = hw->tx_int_mask + 1;
3616
3617 if (physical > hw->tx_desc_info.avail)
3618 return 1;
3619
3620 return hw->tx_desc_info.avail;
3621}
3622
3623/**
3624 * hw_send_pkt - mark packet for transmission
3625 * @hw: The hardware instance.
3626 *
3627 * This routine marks the packet for transmission in PCI version.
3628 */
3629static void hw_send_pkt(struct ksz_hw *hw)
3630{
3631 struct ksz_desc *cur = hw->tx_desc_info.cur;
3632
3633 cur->sw.buf.tx.last_seg = 1;
3634
3635 /* Interrupt only after specified number of descriptors used. */
3636 if (hw->tx_int_cnt > hw->tx_int_mask) {
3637 cur->sw.buf.tx.intr = 1;
3638 hw->tx_int_cnt = 0;
3639 hw->tx_size = 0;
3640 }
3641
3642 /* KSZ8842 supports port directed transmission. */
3643 cur->sw.buf.tx.dest_port = hw->dst_ports;
3644
3645 release_desc(cur);
3646
3647 writel(0, hw->io + KS_DMA_TX_START);
3648}
3649
3650static int empty_addr(u8 *addr)
3651{
3652 u32 *addr1 = (u32 *) addr;
3653 u16 *addr2 = (u16 *) &addr[4];
3654
3655 return 0 == *addr1 && 0 == *addr2;
3656}
3657
3658/**
3659 * hw_set_addr - set MAC address
3660 * @hw: The hardware instance.
3661 *
3662 * This routine programs the MAC address of the hardware when the address is
3663 * overridden.
3664 */
3665static void hw_set_addr(struct ksz_hw *hw)
3666{
3667 int i;
3668
3669 for (i = 0; i < ETH_ALEN; i++)
3670 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
3671 hw->io + KS884X_ADDR_0_OFFSET + i);
3672
3673 sw_set_addr(hw, hw->override_addr);
3674}
3675
3676/**
3677 * hw_read_addr - read MAC address
3678 * @hw: The hardware instance.
3679 *
3680 * This routine retrieves the MAC address of the hardware.
3681 */
3682static void hw_read_addr(struct ksz_hw *hw)
3683{
3684 int i;
3685
3686 for (i = 0; i < ETH_ALEN; i++)
3687 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
3688 KS884X_ADDR_0_OFFSET + i);
3689
3690 if (!hw->mac_override) {
3691 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN);
3692 if (empty_addr(hw->override_addr)) {
3693 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN);
3694 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
3695 ETH_ALEN);
3696 hw->override_addr[5] += hw->id;
3697 hw_set_addr(hw);
3698 }
3699 }
3700}
3701
3702static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
3703{
3704 int i;
3705 u32 mac_addr_lo;
3706 u32 mac_addr_hi;
3707
3708 mac_addr_hi = 0;
3709 for (i = 0; i < 2; i++) {
3710 mac_addr_hi <<= 8;
3711 mac_addr_hi |= mac_addr[i];
3712 }
3713 mac_addr_hi |= ADD_ADDR_ENABLE;
3714 mac_addr_lo = 0;
3715 for (i = 2; i < 6; i++) {
3716 mac_addr_lo <<= 8;
3717 mac_addr_lo |= mac_addr[i];
3718 }
3719 index *= ADD_ADDR_INCR;
3720
3721 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
3722 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
3723}
3724
3725static void hw_set_add_addr(struct ksz_hw *hw)
3726{
3727 int i;
3728
3729 for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
3730 if (empty_addr(hw->address[i]))
3731 writel(0, hw->io + ADD_ADDR_INCR * i +
3732 KS_ADD_ADDR_0_HI);
3733 else
3734 hw_ena_add_addr(hw, i, hw->address[i]);
3735 }
3736}
3737
3738static int hw_add_addr(struct ksz_hw *hw, const u8 *mac_addr)
3739{
3740 int i;
3741 int j = ADDITIONAL_ENTRIES;
3742
3743 if (ether_addr_equal(hw->override_addr, mac_addr))
3744 return 0;
3745 for (i = 0; i < hw->addr_list_size; i++) {
3746 if (ether_addr_equal(hw->address[i], mac_addr))
3747 return 0;
3748 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
3749 j = i;
3750 }
3751 if (j < ADDITIONAL_ENTRIES) {
3752 memcpy(hw->address[j], mac_addr, ETH_ALEN);
3753 hw_ena_add_addr(hw, j, hw->address[j]);
3754 return 0;
3755 }
3756 return -1;
3757}
3758
3759static int hw_del_addr(struct ksz_hw *hw, const u8 *mac_addr)
3760{
3761 int i;
3762
3763 for (i = 0; i < hw->addr_list_size; i++) {
3764 if (ether_addr_equal(hw->address[i], mac_addr)) {
3765 eth_zero_addr(hw->address[i]);
3766 writel(0, hw->io + ADD_ADDR_INCR * i +
3767 KS_ADD_ADDR_0_HI);
3768 return 0;
3769 }
3770 }
3771 return -1;
3772}
3773
3774/**
3775 * hw_clr_multicast - clear multicast addresses
3776 * @hw: The hardware instance.
3777 *
3778 * This routine removes all multicast addresses set in the hardware.
3779 */
3780static void hw_clr_multicast(struct ksz_hw *hw)
3781{
3782 int i;
3783
3784 for (i = 0; i < HW_MULTICAST_SIZE; i++) {
3785 hw->multi_bits[i] = 0;
3786
3787 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
3788 }
3789}
3790
3791/**
3792 * hw_set_grp_addr - set multicast addresses
3793 * @hw: The hardware instance.
3794 *
3795 * This routine programs multicast addresses for the hardware to accept those
3796 * addresses.
3797 */
3798static void hw_set_grp_addr(struct ksz_hw *hw)
3799{
3800 int i;
3801 int index;
3802 int position;
3803 int value;
3804
3805 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
3806
3807 for (i = 0; i < hw->multi_list_size; i++) {
3808 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
3809 index = position >> 3;
3810 value = 1 << (position & 7);
3811 hw->multi_bits[index] |= (u8) value;
3812 }
3813
3814 for (i = 0; i < HW_MULTICAST_SIZE; i++)
3815 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
3816 i);
3817}
3818
3819/**
3820 * hw_set_multicast - enable or disable all multicast receiving
3821 * @hw: The hardware instance.
3822 * @multicast: To turn on or off the all multicast feature.
3823 *
3824 * This routine enables/disables the hardware to accept all multicast packets.
3825 */
3826static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
3827{
3828 /* Stop receiving for reconfiguration. */
3829 hw_stop_rx(hw);
3830
3831 if (multicast)
3832 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3833 else
3834 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
3835
3836 if (hw->enabled)
3837 hw_start_rx(hw);
3838}
3839
3840/**
3841 * hw_set_promiscuous - enable or disable promiscuous receiving
3842 * @hw: The hardware instance.
3843 * @prom: To turn on or off the promiscuous feature.
3844 *
3845 * This routine enables/disables the hardware to accept all packets.
3846 */
3847static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
3848{
3849 /* Stop receiving for reconfiguration. */
3850 hw_stop_rx(hw);
3851
3852 if (prom)
3853 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3854 else
3855 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
3856
3857 if (hw->enabled)
3858 hw_start_rx(hw);
3859}
3860
3861/**
3862 * sw_enable - enable the switch
3863 * @hw: The hardware instance.
3864 * @enable: The flag to enable or disable the switch
3865 *
3866 * This routine is used to enable/disable the switch in KSZ8842.
3867 */
3868static void sw_enable(struct ksz_hw *hw, int enable)
3869{
3870 int port;
3871
3872 for (port = 0; port < SWITCH_PORT_NUM; port++) {
3873 if (hw->dev_count > 1) {
3874 /* Set port-base vlan membership with host port. */
3875 sw_cfg_port_base_vlan(hw, port,
3876 HOST_MASK | (1 << port));
3877 port_set_stp_state(hw, port, STP_STATE_DISABLED);
3878 } else {
3879 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
3880 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
3881 }
3882 }
3883 if (hw->dev_count > 1)
3884 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
3885 else
3886 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
3887
3888 if (enable)
3889 enable = KS8842_START;
3890 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
3891}
3892
3893/**
3894 * sw_setup - setup the switch
3895 * @hw: The hardware instance.
3896 *
3897 * This routine setup the hardware switch engine for default operation.
3898 */
3899static void sw_setup(struct ksz_hw *hw)
3900{
3901 int port;
3902
3903 sw_set_global_ctrl(hw);
3904
3905 /* Enable switch broadcast storm protection at 10% percent rate. */
3906 sw_init_broad_storm(hw);
3907 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
3908 for (port = 0; port < SWITCH_PORT_NUM; port++)
3909 sw_ena_broad_storm(hw, port);
3910
3911 sw_init_prio(hw);
3912
3913 sw_init_mirror(hw);
3914
3915 sw_init_prio_rate(hw);
3916
3917 sw_init_vlan(hw);
3918
3919 if (hw->features & STP_SUPPORT)
3920 sw_init_stp(hw);
3921 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
3922 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
3923 hw->overrides |= PAUSE_FLOW_CTRL;
3924 sw_enable(hw, 1);
3925}
3926
3927/**
3928 * ksz_start_timer - start kernel timer
3929 * @info: Kernel timer information.
3930 * @time: The time tick.
3931 *
3932 * This routine starts the kernel timer after the specified time tick.
3933 */
3934static void ksz_start_timer(struct ksz_timer_info *info, int time)
3935{
3936 info->cnt = 0;
3937 info->timer.expires = jiffies + time;
3938 add_timer(&info->timer);
3939
3940 /* infinity */
3941 info->max = -1;
3942}
3943
3944/**
3945 * ksz_stop_timer - stop kernel timer
3946 * @info: Kernel timer information.
3947 *
3948 * This routine stops the kernel timer.
3949 */
3950static void ksz_stop_timer(struct ksz_timer_info *info)
3951{
3952 if (info->max) {
3953 info->max = 0;
3954 del_timer_sync(&info->timer);
3955 }
3956}
3957
3958static void ksz_init_timer(struct ksz_timer_info *info, int period,
3959 void (*function)(struct timer_list *))
3960{
3961 info->max = 0;
3962 info->period = period;
3963 timer_setup(&info->timer, function, 0);
3964}
3965
3966static void ksz_update_timer(struct ksz_timer_info *info)
3967{
3968 ++info->cnt;
3969 if (info->max > 0) {
3970 if (info->cnt < info->max) {
3971 info->timer.expires = jiffies + info->period;
3972 add_timer(&info->timer);
3973 } else
3974 info->max = 0;
3975 } else if (info->max < 0) {
3976 info->timer.expires = jiffies + info->period;
3977 add_timer(&info->timer);
3978 }
3979}
3980
3981/**
3982 * ksz_alloc_soft_desc - allocate software descriptors
3983 * @desc_info: Descriptor information structure.
3984 * @transmit: Indication that descriptors are for transmit.
3985 *
3986 * This local function allocates software descriptors for manipulation in
3987 * memory.
3988 *
3989 * Return 0 if successful.
3990 */
3991static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
3992{
3993 desc_info->ring = kcalloc(desc_info->alloc, sizeof(struct ksz_desc),
3994 GFP_KERNEL);
3995 if (!desc_info->ring)
3996 return 1;
3997 hw_init_desc(desc_info, transmit);
3998 return 0;
3999}
4000
4001/**
4002 * ksz_alloc_desc - allocate hardware descriptors
4003 * @adapter: Adapter information structure.
4004 *
4005 * This local function allocates hardware descriptors for receiving and
4006 * transmitting.
4007 *
4008 * Return 0 if successful.
4009 */
4010static int ksz_alloc_desc(struct dev_info *adapter)
4011{
4012 struct ksz_hw *hw = &adapter->hw;
4013 int offset;
4014
4015 /* Allocate memory for RX & TX descriptors. */
4016 adapter->desc_pool.alloc_size =
4017 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4018 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4019 DESC_ALIGNMENT;
4020
4021 adapter->desc_pool.alloc_virt =
4022 dma_alloc_coherent(&adapter->pdev->dev,
4023 adapter->desc_pool.alloc_size,
4024 &adapter->desc_pool.dma_addr, GFP_KERNEL);
4025 if (adapter->desc_pool.alloc_virt == NULL) {
4026 adapter->desc_pool.alloc_size = 0;
4027 return 1;
4028 }
4029
4030 /* Align to the next cache line boundary. */
4031 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4032 (DESC_ALIGNMENT -
4033 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4034 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4035 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4036
4037 /* Allocate receive/transmit descriptors. */
4038 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4039 adapter->desc_pool.virt;
4040 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4041 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4042 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4043 (adapter->desc_pool.virt + offset);
4044 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4045
4046 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4047 return 1;
4048 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4049 return 1;
4050
4051 return 0;
4052}
4053
4054/**
4055 * free_dma_buf - release DMA buffer resources
4056 * @adapter: Adapter information structure.
4057 * @dma_buf: pointer to buf
4058 * @direction: to or from device
4059 *
4060 * This routine is just a helper function to release the DMA buffer resources.
4061 */
4062static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4063 int direction)
4064{
4065 dma_unmap_single(&adapter->pdev->dev, dma_buf->dma, dma_buf->len,
4066 direction);
4067 dev_kfree_skb(dma_buf->skb);
4068 dma_buf->skb = NULL;
4069 dma_buf->dma = 0;
4070}
4071
4072/**
4073 * ksz_init_rx_buffers - initialize receive descriptors
4074 * @adapter: Adapter information structure.
4075 *
4076 * This routine initializes DMA buffers for receiving.
4077 */
4078static void ksz_init_rx_buffers(struct dev_info *adapter)
4079{
4080 int i;
4081 struct ksz_desc *desc;
4082 struct ksz_dma_buf *dma_buf;
4083 struct ksz_hw *hw = &adapter->hw;
4084 struct ksz_desc_info *info = &hw->rx_desc_info;
4085
4086 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4087 get_rx_pkt(info, &desc);
4088
4089 dma_buf = DMA_BUFFER(desc);
4090 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4091 free_dma_buf(adapter, dma_buf, DMA_FROM_DEVICE);
4092 dma_buf->len = adapter->mtu;
4093 if (!dma_buf->skb)
4094 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4095 if (dma_buf->skb && !dma_buf->dma)
4096 dma_buf->dma = dma_map_single(&adapter->pdev->dev,
4097 skb_tail_pointer(dma_buf->skb),
4098 dma_buf->len,
4099 DMA_FROM_DEVICE);
4100
4101 /* Set descriptor. */
4102 set_rx_buf(desc, dma_buf->dma);
4103 set_rx_len(desc, dma_buf->len);
4104 release_desc(desc);
4105 }
4106}
4107
4108/**
4109 * ksz_alloc_mem - allocate memory for hardware descriptors
4110 * @adapter: Adapter information structure.
4111 *
4112 * This function allocates memory for use by hardware descriptors for receiving
4113 * and transmitting.
4114 *
4115 * Return 0 if successful.
4116 */
4117static int ksz_alloc_mem(struct dev_info *adapter)
4118{
4119 struct ksz_hw *hw = &adapter->hw;
4120
4121 /* Determine the number of receive and transmit descriptors. */
4122 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4123 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4124
4125 /* Determine how many descriptors to skip transmit interrupt. */
4126 hw->tx_int_cnt = 0;
4127 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4128 if (hw->tx_int_mask > 8)
4129 hw->tx_int_mask = 8;
4130 while (hw->tx_int_mask) {
4131 hw->tx_int_cnt++;
4132 hw->tx_int_mask >>= 1;
4133 }
4134 if (hw->tx_int_cnt) {
4135 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4136 hw->tx_int_cnt = 0;
4137 }
4138
4139 /* Determine the descriptor size. */
4140 hw->rx_desc_info.size =
4141 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4142 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4143 hw->tx_desc_info.size =
4144 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4145 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4146 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4147 pr_alert("Hardware descriptor size not right!\n");
4148 ksz_check_desc_num(&hw->rx_desc_info);
4149 ksz_check_desc_num(&hw->tx_desc_info);
4150
4151 /* Allocate descriptors. */
4152 if (ksz_alloc_desc(adapter))
4153 return 1;
4154
4155 return 0;
4156}
4157
4158/**
4159 * ksz_free_desc - free software and hardware descriptors
4160 * @adapter: Adapter information structure.
4161 *
4162 * This local routine frees the software and hardware descriptors allocated by
4163 * ksz_alloc_desc().
4164 */
4165static void ksz_free_desc(struct dev_info *adapter)
4166{
4167 struct ksz_hw *hw = &adapter->hw;
4168
4169 /* Reset descriptor. */
4170 hw->rx_desc_info.ring_virt = NULL;
4171 hw->tx_desc_info.ring_virt = NULL;
4172 hw->rx_desc_info.ring_phys = 0;
4173 hw->tx_desc_info.ring_phys = 0;
4174
4175 /* Free memory. */
4176 if (adapter->desc_pool.alloc_virt)
4177 dma_free_coherent(&adapter->pdev->dev,
4178 adapter->desc_pool.alloc_size,
4179 adapter->desc_pool.alloc_virt,
4180 adapter->desc_pool.dma_addr);
4181
4182 /* Reset resource pool. */
4183 adapter->desc_pool.alloc_size = 0;
4184 adapter->desc_pool.alloc_virt = NULL;
4185
4186 kfree(hw->rx_desc_info.ring);
4187 hw->rx_desc_info.ring = NULL;
4188 kfree(hw->tx_desc_info.ring);
4189 hw->tx_desc_info.ring = NULL;
4190}
4191
4192/**
4193 * ksz_free_buffers - free buffers used in the descriptors
4194 * @adapter: Adapter information structure.
4195 * @desc_info: Descriptor information structure.
4196 * @direction: to or from device
4197 *
4198 * This local routine frees buffers used in the DMA buffers.
4199 */
4200static void ksz_free_buffers(struct dev_info *adapter,
4201 struct ksz_desc_info *desc_info, int direction)
4202{
4203 int i;
4204 struct ksz_dma_buf *dma_buf;
4205 struct ksz_desc *desc = desc_info->ring;
4206
4207 for (i = 0; i < desc_info->alloc; i++) {
4208 dma_buf = DMA_BUFFER(desc);
4209 if (dma_buf->skb)
4210 free_dma_buf(adapter, dma_buf, direction);
4211 desc++;
4212 }
4213}
4214
4215/**
4216 * ksz_free_mem - free all resources used by descriptors
4217 * @adapter: Adapter information structure.
4218 *
4219 * This local routine frees all the resources allocated by ksz_alloc_mem().
4220 */
4221static void ksz_free_mem(struct dev_info *adapter)
4222{
4223 /* Free transmit buffers. */
4224 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info, DMA_TO_DEVICE);
4225
4226 /* Free receive buffers. */
4227 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info, DMA_FROM_DEVICE);
4228
4229 /* Free descriptors. */
4230 ksz_free_desc(adapter);
4231}
4232
4233static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4234 u64 *counter)
4235{
4236 int i;
4237 int mib;
4238 int port;
4239 struct ksz_port_mib *port_mib;
4240
4241 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4242 for (i = 0, port = first; i < cnt; i++, port++) {
4243 port_mib = &hw->port_mib[port];
4244 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4245 counter[mib] += port_mib->counter[mib];
4246 }
4247}
4248
4249/**
4250 * send_packet - send packet
4251 * @skb: Socket buffer.
4252 * @dev: Network device.
4253 *
4254 * This routine is used to send a packet out to the network.
4255 */
4256static void send_packet(struct sk_buff *skb, struct net_device *dev)
4257{
4258 struct ksz_desc *desc;
4259 struct ksz_desc *first;
4260 struct dev_priv *priv = netdev_priv(dev);
4261 struct dev_info *hw_priv = priv->adapter;
4262 struct ksz_hw *hw = &hw_priv->hw;
4263 struct ksz_desc_info *info = &hw->tx_desc_info;
4264 struct ksz_dma_buf *dma_buf;
4265 int len;
4266 int last_frag = skb_shinfo(skb)->nr_frags;
4267
4268 /*
4269 * KSZ8842 with multiple device interfaces needs to be told which port
4270 * to send.
4271 */
4272 if (hw->dev_count > 1)
4273 hw->dst_ports = 1 << priv->port.first_port;
4274
4275 /* Hardware will pad the length to 60. */
4276 len = skb->len;
4277
4278 /* Remember the very first descriptor. */
4279 first = info->cur;
4280 desc = first;
4281
4282 dma_buf = DMA_BUFFER(desc);
4283 if (last_frag) {
4284 int frag;
4285 skb_frag_t *this_frag;
4286
4287 dma_buf->len = skb_headlen(skb);
4288
4289 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev, skb->data,
4290 dma_buf->len, DMA_TO_DEVICE);
4291 set_tx_buf(desc, dma_buf->dma);
4292 set_tx_len(desc, dma_buf->len);
4293
4294 frag = 0;
4295 do {
4296 this_frag = &skb_shinfo(skb)->frags[frag];
4297
4298 /* Get a new descriptor. */
4299 get_tx_pkt(info, &desc);
4300
4301 /* Keep track of descriptors used so far. */
4302 ++hw->tx_int_cnt;
4303
4304 dma_buf = DMA_BUFFER(desc);
4305 dma_buf->len = skb_frag_size(this_frag);
4306
4307 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev,
4308 skb_frag_address(this_frag),
4309 dma_buf->len,
4310 DMA_TO_DEVICE);
4311 set_tx_buf(desc, dma_buf->dma);
4312 set_tx_len(desc, dma_buf->len);
4313
4314 frag++;
4315 if (frag == last_frag)
4316 break;
4317
4318 /* Do not release the last descriptor here. */
4319 release_desc(desc);
4320 } while (1);
4321
4322 /* current points to the last descriptor. */
4323 info->cur = desc;
4324
4325 /* Release the first descriptor. */
4326 release_desc(first);
4327 } else {
4328 dma_buf->len = len;
4329
4330 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev, skb->data,
4331 dma_buf->len, DMA_TO_DEVICE);
4332 set_tx_buf(desc, dma_buf->dma);
4333 set_tx_len(desc, dma_buf->len);
4334 }
4335
4336 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4337 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4338 (desc)->sw.buf.tx.csum_gen_udp = 1;
4339 }
4340
4341 /*
4342 * The last descriptor holds the packet so that it can be returned to
4343 * network subsystem after all descriptors are transmitted.
4344 */
4345 dma_buf->skb = skb;
4346
4347 hw_send_pkt(hw);
4348
4349 /* Update transmit statistics. */
4350 dev->stats.tx_packets++;
4351 dev->stats.tx_bytes += len;
4352}
4353
4354/**
4355 * transmit_cleanup - clean up transmit descriptors
4356 * @hw_priv: Network device.
4357 * @normal: break if owned
4358 *
4359 * This routine is called to clean up the transmitted buffers.
4360 */
4361static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4362{
4363 int last;
4364 union desc_stat status;
4365 struct ksz_hw *hw = &hw_priv->hw;
4366 struct ksz_desc_info *info = &hw->tx_desc_info;
4367 struct ksz_desc *desc;
4368 struct ksz_dma_buf *dma_buf;
4369 struct net_device *dev = NULL;
4370
4371 spin_lock_irq(&hw_priv->hwlock);
4372 last = info->last;
4373
4374 while (info->avail < info->alloc) {
4375 /* Get next descriptor which is not hardware owned. */
4376 desc = &info->ring[last];
4377 status.data = le32_to_cpu(desc->phw->ctrl.data);
4378 if (status.tx.hw_owned) {
4379 if (normal)
4380 break;
4381 else
4382 reset_desc(desc, status);
4383 }
4384
4385 dma_buf = DMA_BUFFER(desc);
4386 dma_unmap_single(&hw_priv->pdev->dev, dma_buf->dma,
4387 dma_buf->len, DMA_TO_DEVICE);
4388
4389 /* This descriptor contains the last buffer in the packet. */
4390 if (dma_buf->skb) {
4391 dev = dma_buf->skb->dev;
4392
4393 /* Release the packet back to network subsystem. */
4394 dev_kfree_skb_irq(dma_buf->skb);
4395 dma_buf->skb = NULL;
4396 }
4397
4398 /* Free the transmitted descriptor. */
4399 last++;
4400 last &= info->mask;
4401 info->avail++;
4402 }
4403 info->last = last;
4404 spin_unlock_irq(&hw_priv->hwlock);
4405
4406 /* Notify the network subsystem that the packet has been sent. */
4407 if (dev)
4408 netif_trans_update(dev);
4409}
4410
4411/**
4412 * tx_done - transmit done processing
4413 * @hw_priv: Network device.
4414 *
4415 * This routine is called when the transmit interrupt is triggered, indicating
4416 * either a packet is sent successfully or there are transmit errors.
4417 */
4418static void tx_done(struct dev_info *hw_priv)
4419{
4420 struct ksz_hw *hw = &hw_priv->hw;
4421 int port;
4422
4423 transmit_cleanup(hw_priv, 1);
4424
4425 for (port = 0; port < hw->dev_count; port++) {
4426 struct net_device *dev = hw->port_info[port].pdev;
4427
4428 if (netif_running(dev) && netif_queue_stopped(dev))
4429 netif_wake_queue(dev);
4430 }
4431}
4432
4433static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4434{
4435 skb->dev = old->dev;
4436 skb->protocol = old->protocol;
4437 skb->ip_summed = old->ip_summed;
4438 skb->csum = old->csum;
4439 skb_set_network_header(skb, ETH_HLEN);
4440
4441 dev_consume_skb_any(old);
4442}
4443
4444/**
4445 * netdev_tx - send out packet
4446 * @skb: Socket buffer.
4447 * @dev: Network device.
4448 *
4449 * This function is used by the upper network layer to send out a packet.
4450 *
4451 * Return 0 if successful; otherwise an error code indicating failure.
4452 */
4453static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev)
4454{
4455 struct dev_priv *priv = netdev_priv(dev);
4456 struct dev_info *hw_priv = priv->adapter;
4457 struct ksz_hw *hw = &hw_priv->hw;
4458 int left;
4459 int num = 1;
4460 int rc = 0;
4461
4462 if (hw->features & SMALL_PACKET_TX_BUG) {
4463 struct sk_buff *org_skb = skb;
4464
4465 if (skb->len <= 48) {
4466 if (skb_end_pointer(skb) - skb->data >= 50) {
4467 memset(&skb->data[skb->len], 0, 50 - skb->len);
4468 skb->len = 50;
4469 } else {
4470 skb = netdev_alloc_skb(dev, 50);
4471 if (!skb)
4472 return NETDEV_TX_BUSY;
4473 memcpy(skb->data, org_skb->data, org_skb->len);
4474 memset(&skb->data[org_skb->len], 0,
4475 50 - org_skb->len);
4476 skb->len = 50;
4477 copy_old_skb(org_skb, skb);
4478 }
4479 }
4480 }
4481
4482 spin_lock_irq(&hw_priv->hwlock);
4483
4484 num = skb_shinfo(skb)->nr_frags + 1;
4485 left = hw_alloc_pkt(hw, skb->len, num);
4486 if (left) {
4487 if (left < num ||
4488 (CHECKSUM_PARTIAL == skb->ip_summed &&
4489 skb->protocol == htons(ETH_P_IPV6))) {
4490 struct sk_buff *org_skb = skb;
4491
4492 skb = netdev_alloc_skb(dev, org_skb->len);
4493 if (!skb) {
4494 rc = NETDEV_TX_BUSY;
4495 goto unlock;
4496 }
4497 skb_copy_and_csum_dev(org_skb, skb->data);
4498 org_skb->ip_summed = CHECKSUM_NONE;
4499 skb->len = org_skb->len;
4500 copy_old_skb(org_skb, skb);
4501 }
4502 send_packet(skb, dev);
4503 if (left <= num)
4504 netif_stop_queue(dev);
4505 } else {
4506 /* Stop the transmit queue until packet is allocated. */
4507 netif_stop_queue(dev);
4508 rc = NETDEV_TX_BUSY;
4509 }
4510unlock:
4511 spin_unlock_irq(&hw_priv->hwlock);
4512
4513 return rc;
4514}
4515
4516/**
4517 * netdev_tx_timeout - transmit timeout processing
4518 * @dev: Network device.
4519 * @txqueue: index of hanging queue
4520 *
4521 * This routine is called when the transmit timer expires. That indicates the
4522 * hardware is not running correctly because transmit interrupts are not
4523 * triggered to free up resources so that the transmit routine can continue
4524 * sending out packets. The hardware is reset to correct the problem.
4525 */
4526static void netdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
4527{
4528 static unsigned long last_reset;
4529
4530 struct dev_priv *priv = netdev_priv(dev);
4531 struct dev_info *hw_priv = priv->adapter;
4532 struct ksz_hw *hw = &hw_priv->hw;
4533 int port;
4534
4535 if (hw->dev_count > 1) {
4536 /*
4537 * Only reset the hardware if time between calls is long
4538 * enough.
4539 */
4540 if (time_before_eq(jiffies, last_reset + dev->watchdog_timeo))
4541 hw_priv = NULL;
4542 }
4543
4544 last_reset = jiffies;
4545 if (hw_priv) {
4546 hw_dis_intr(hw);
4547 hw_disable(hw);
4548
4549 transmit_cleanup(hw_priv, 0);
4550 hw_reset_pkts(&hw->rx_desc_info);
4551 hw_reset_pkts(&hw->tx_desc_info);
4552 ksz_init_rx_buffers(hw_priv);
4553
4554 hw_reset(hw);
4555
4556 hw_set_desc_base(hw,
4557 hw->tx_desc_info.ring_phys,
4558 hw->rx_desc_info.ring_phys);
4559 hw_set_addr(hw);
4560 if (hw->all_multi)
4561 hw_set_multicast(hw, hw->all_multi);
4562 else if (hw->multi_list_size)
4563 hw_set_grp_addr(hw);
4564
4565 if (hw->dev_count > 1) {
4566 hw_set_add_addr(hw);
4567 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4568 struct net_device *port_dev;
4569
4570 port_set_stp_state(hw, port,
4571 STP_STATE_DISABLED);
4572
4573 port_dev = hw->port_info[port].pdev;
4574 if (netif_running(port_dev))
4575 port_set_stp_state(hw, port,
4576 STP_STATE_SIMPLE);
4577 }
4578 }
4579
4580 hw_enable(hw);
4581 hw_ena_intr(hw);
4582 }
4583
4584 netif_trans_update(dev);
4585 netif_wake_queue(dev);
4586}
4587
4588static inline void csum_verified(struct sk_buff *skb)
4589{
4590 unsigned short protocol;
4591 struct iphdr *iph;
4592
4593 protocol = skb->protocol;
4594 skb_reset_network_header(skb);
4595 iph = (struct iphdr *) skb_network_header(skb);
4596 if (protocol == htons(ETH_P_8021Q)) {
4597 protocol = iph->tot_len;
4598 skb_set_network_header(skb, VLAN_HLEN);
4599 iph = (struct iphdr *) skb_network_header(skb);
4600 }
4601 if (protocol == htons(ETH_P_IP)) {
4602 if (iph->protocol == IPPROTO_TCP)
4603 skb->ip_summed = CHECKSUM_UNNECESSARY;
4604 }
4605}
4606
4607static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
4608 struct ksz_desc *desc, union desc_stat status)
4609{
4610 int packet_len;
4611 struct dev_priv *priv = netdev_priv(dev);
4612 struct dev_info *hw_priv = priv->adapter;
4613 struct ksz_dma_buf *dma_buf;
4614 struct sk_buff *skb;
4615
4616 /* Received length includes 4-byte CRC. */
4617 packet_len = status.rx.frame_len - 4;
4618
4619 dma_buf = DMA_BUFFER(desc);
4620 dma_sync_single_for_cpu(&hw_priv->pdev->dev, dma_buf->dma,
4621 packet_len + 4, DMA_FROM_DEVICE);
4622
4623 do {
4624 /* skb->data != skb->head */
4625 skb = netdev_alloc_skb(dev, packet_len + 2);
4626 if (!skb) {
4627 dev->stats.rx_dropped++;
4628 return -ENOMEM;
4629 }
4630
4631 /*
4632 * Align socket buffer in 4-byte boundary for better
4633 * performance.
4634 */
4635 skb_reserve(skb, 2);
4636
4637 skb_put_data(skb, dma_buf->skb->data, packet_len);
4638 } while (0);
4639
4640 skb->protocol = eth_type_trans(skb, dev);
4641
4642 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
4643 csum_verified(skb);
4644
4645 /* Update receive statistics. */
4646 dev->stats.rx_packets++;
4647 dev->stats.rx_bytes += packet_len;
4648
4649 /* Notify upper layer for received packet. */
4650 netif_rx(skb);
4651
4652 return 0;
4653}
4654
4655static int dev_rcv_packets(struct dev_info *hw_priv)
4656{
4657 int next;
4658 union desc_stat status;
4659 struct ksz_hw *hw = &hw_priv->hw;
4660 struct net_device *dev = hw->port_info[0].pdev;
4661 struct ksz_desc_info *info = &hw->rx_desc_info;
4662 int left = info->alloc;
4663 struct ksz_desc *desc;
4664 int received = 0;
4665
4666 next = info->next;
4667 while (left--) {
4668 /* Get next descriptor which is not hardware owned. */
4669 desc = &info->ring[next];
4670 status.data = le32_to_cpu(desc->phw->ctrl.data);
4671 if (status.rx.hw_owned)
4672 break;
4673
4674 /* Status valid only when last descriptor bit is set. */
4675 if (status.rx.last_desc && status.rx.first_desc) {
4676 if (rx_proc(dev, hw, desc, status))
4677 goto release_packet;
4678 received++;
4679 }
4680
4681release_packet:
4682 release_desc(desc);
4683 next++;
4684 next &= info->mask;
4685 }
4686 info->next = next;
4687
4688 return received;
4689}
4690
4691static int port_rcv_packets(struct dev_info *hw_priv)
4692{
4693 int next;
4694 union desc_stat status;
4695 struct ksz_hw *hw = &hw_priv->hw;
4696 struct net_device *dev = hw->port_info[0].pdev;
4697 struct ksz_desc_info *info = &hw->rx_desc_info;
4698 int left = info->alloc;
4699 struct ksz_desc *desc;
4700 int received = 0;
4701
4702 next = info->next;
4703 while (left--) {
4704 /* Get next descriptor which is not hardware owned. */
4705 desc = &info->ring[next];
4706 status.data = le32_to_cpu(desc->phw->ctrl.data);
4707 if (status.rx.hw_owned)
4708 break;
4709
4710 if (hw->dev_count > 1) {
4711 /* Get received port number. */
4712 int p = HW_TO_DEV_PORT(status.rx.src_port);
4713
4714 dev = hw->port_info[p].pdev;
4715 if (!netif_running(dev))
4716 goto release_packet;
4717 }
4718
4719 /* Status valid only when last descriptor bit is set. */
4720 if (status.rx.last_desc && status.rx.first_desc) {
4721 if (rx_proc(dev, hw, desc, status))
4722 goto release_packet;
4723 received++;
4724 }
4725
4726release_packet:
4727 release_desc(desc);
4728 next++;
4729 next &= info->mask;
4730 }
4731 info->next = next;
4732
4733 return received;
4734}
4735
4736static int dev_rcv_special(struct dev_info *hw_priv)
4737{
4738 int next;
4739 union desc_stat status;
4740 struct ksz_hw *hw = &hw_priv->hw;
4741 struct net_device *dev = hw->port_info[0].pdev;
4742 struct ksz_desc_info *info = &hw->rx_desc_info;
4743 int left = info->alloc;
4744 struct ksz_desc *desc;
4745 int received = 0;
4746
4747 next = info->next;
4748 while (left--) {
4749 /* Get next descriptor which is not hardware owned. */
4750 desc = &info->ring[next];
4751 status.data = le32_to_cpu(desc->phw->ctrl.data);
4752 if (status.rx.hw_owned)
4753 break;
4754
4755 if (hw->dev_count > 1) {
4756 /* Get received port number. */
4757 int p = HW_TO_DEV_PORT(status.rx.src_port);
4758
4759 dev = hw->port_info[p].pdev;
4760 if (!netif_running(dev))
4761 goto release_packet;
4762 }
4763
4764 /* Status valid only when last descriptor bit is set. */
4765 if (status.rx.last_desc && status.rx.first_desc) {
4766 /*
4767 * Receive without error. With receive errors
4768 * disabled, packets with receive errors will be
4769 * dropped, so no need to check the error bit.
4770 */
4771 if (!status.rx.error || (status.data &
4772 KS_DESC_RX_ERROR_COND) ==
4773 KS_DESC_RX_ERROR_TOO_LONG) {
4774 if (rx_proc(dev, hw, desc, status))
4775 goto release_packet;
4776 received++;
4777 } else {
4778 struct dev_priv *priv = netdev_priv(dev);
4779
4780 /* Update receive error statistics. */
4781 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
4782 }
4783 }
4784
4785release_packet:
4786 release_desc(desc);
4787 next++;
4788 next &= info->mask;
4789 }
4790 info->next = next;
4791
4792 return received;
4793}
4794
4795static void rx_proc_task(struct tasklet_struct *t)
4796{
4797 struct dev_info *hw_priv = from_tasklet(hw_priv, t, rx_tasklet);
4798 struct ksz_hw *hw = &hw_priv->hw;
4799
4800 if (!hw->enabled)
4801 return;
4802 if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
4803
4804 /* In case receive process is suspended because of overrun. */
4805 hw_resume_rx(hw);
4806
4807 /* tasklets are interruptible. */
4808 spin_lock_irq(&hw_priv->hwlock);
4809 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
4810 spin_unlock_irq(&hw_priv->hwlock);
4811 } else {
4812 hw_ack_intr(hw, KS884X_INT_RX);
4813 tasklet_schedule(&hw_priv->rx_tasklet);
4814 }
4815}
4816
4817static void tx_proc_task(struct tasklet_struct *t)
4818{
4819 struct dev_info *hw_priv = from_tasklet(hw_priv, t, tx_tasklet);
4820 struct ksz_hw *hw = &hw_priv->hw;
4821
4822 hw_ack_intr(hw, KS884X_INT_TX_MASK);
4823
4824 tx_done(hw_priv);
4825
4826 /* tasklets are interruptible. */
4827 spin_lock_irq(&hw_priv->hwlock);
4828 hw_turn_on_intr(hw, KS884X_INT_TX);
4829 spin_unlock_irq(&hw_priv->hwlock);
4830}
4831
4832static inline void handle_rx_stop(struct ksz_hw *hw)
4833{
4834 /* Receive just has been stopped. */
4835 if (0 == hw->rx_stop)
4836 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
4837 else if (hw->rx_stop > 1) {
4838 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
4839 hw_start_rx(hw);
4840 } else {
4841 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
4842 hw->rx_stop = 0;
4843 }
4844 } else
4845 /* Receive just has been started. */
4846 hw->rx_stop++;
4847}
4848
4849/**
4850 * netdev_intr - interrupt handling
4851 * @irq: Interrupt number.
4852 * @dev_id: Network device.
4853 *
4854 * This function is called by upper network layer to signal interrupt.
4855 *
4856 * Return IRQ_HANDLED if interrupt is handled.
4857 */
4858static irqreturn_t netdev_intr(int irq, void *dev_id)
4859{
4860 uint int_enable = 0;
4861 struct net_device *dev = (struct net_device *) dev_id;
4862 struct dev_priv *priv = netdev_priv(dev);
4863 struct dev_info *hw_priv = priv->adapter;
4864 struct ksz_hw *hw = &hw_priv->hw;
4865
4866 spin_lock(&hw_priv->hwlock);
4867
4868 hw_read_intr(hw, &int_enable);
4869
4870 /* Not our interrupt! */
4871 if (!int_enable) {
4872 spin_unlock(&hw_priv->hwlock);
4873 return IRQ_NONE;
4874 }
4875
4876 do {
4877 hw_ack_intr(hw, int_enable);
4878 int_enable &= hw->intr_mask;
4879
4880 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
4881 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
4882 tasklet_schedule(&hw_priv->tx_tasklet);
4883 }
4884
4885 if (likely(int_enable & KS884X_INT_RX)) {
4886 hw_dis_intr_bit(hw, KS884X_INT_RX);
4887 tasklet_schedule(&hw_priv->rx_tasklet);
4888 }
4889
4890 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
4891 dev->stats.rx_fifo_errors++;
4892 hw_resume_rx(hw);
4893 }
4894
4895 if (unlikely(int_enable & KS884X_INT_PHY)) {
4896 struct ksz_port *port = &priv->port;
4897
4898 hw->features |= LINK_INT_WORKING;
4899 port_get_link_speed(port);
4900 }
4901
4902 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
4903 handle_rx_stop(hw);
4904 break;
4905 }
4906
4907 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
4908 u32 data;
4909
4910 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
4911 pr_info("Tx stopped\n");
4912 data = readl(hw->io + KS_DMA_TX_CTRL);
4913 if (!(data & DMA_TX_ENABLE))
4914 pr_info("Tx disabled\n");
4915 break;
4916 }
4917 } while (0);
4918
4919 hw_ena_intr(hw);
4920
4921 spin_unlock(&hw_priv->hwlock);
4922
4923 return IRQ_HANDLED;
4924}
4925
4926/*
4927 * Linux network device functions
4928 */
4929
4930
4931#ifdef CONFIG_NET_POLL_CONTROLLER
4932static void netdev_netpoll(struct net_device *dev)
4933{
4934 struct dev_priv *priv = netdev_priv(dev);
4935 struct dev_info *hw_priv = priv->adapter;
4936
4937 hw_dis_intr(&hw_priv->hw);
4938 netdev_intr(dev->irq, dev);
4939}
4940#endif
4941
4942static void bridge_change(struct ksz_hw *hw)
4943{
4944 int port;
4945 u8 member;
4946 struct ksz_switch *sw = hw->ksz_switch;
4947
4948 /* No ports in forwarding state. */
4949 if (!sw->member) {
4950 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4951 sw_block_addr(hw);
4952 }
4953 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4954 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
4955 member = HOST_MASK | sw->member;
4956 else
4957 member = HOST_MASK | (1 << port);
4958 if (member != sw->port_cfg[port].member)
4959 sw_cfg_port_base_vlan(hw, port, member);
4960 }
4961}
4962
4963/**
4964 * netdev_close - close network device
4965 * @dev: Network device.
4966 *
4967 * This function process the close operation of network device. This is caused
4968 * by the user command "ifconfig ethX down."
4969 *
4970 * Return 0 if successful; otherwise an error code indicating failure.
4971 */
4972static int netdev_close(struct net_device *dev)
4973{
4974 struct dev_priv *priv = netdev_priv(dev);
4975 struct dev_info *hw_priv = priv->adapter;
4976 struct ksz_port *port = &priv->port;
4977 struct ksz_hw *hw = &hw_priv->hw;
4978 int pi;
4979
4980 netif_stop_queue(dev);
4981
4982 ksz_stop_timer(&priv->monitor_timer_info);
4983
4984 /* Need to shut the port manually in multiple device interfaces mode. */
4985 if (hw->dev_count > 1) {
4986 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
4987
4988 /* Port is closed. Need to change bridge setting. */
4989 if (hw->features & STP_SUPPORT) {
4990 pi = 1 << port->first_port;
4991 if (hw->ksz_switch->member & pi) {
4992 hw->ksz_switch->member &= ~pi;
4993 bridge_change(hw);
4994 }
4995 }
4996 }
4997 if (port->first_port > 0)
4998 hw_del_addr(hw, dev->dev_addr);
4999 if (!hw_priv->wol_enable)
5000 port_set_power_saving(port, true);
5001
5002 if (priv->multicast)
5003 --hw->all_multi;
5004 if (priv->promiscuous)
5005 --hw->promiscuous;
5006
5007 hw_priv->opened--;
5008 if (!(hw_priv->opened)) {
5009 ksz_stop_timer(&hw_priv->mib_timer_info);
5010 flush_work(&hw_priv->mib_read);
5011
5012 hw_dis_intr(hw);
5013 hw_disable(hw);
5014 hw_clr_multicast(hw);
5015
5016 /* Delay for receive task to stop scheduling itself. */
5017 msleep(2000 / HZ);
5018
5019 tasklet_kill(&hw_priv->rx_tasklet);
5020 tasklet_kill(&hw_priv->tx_tasklet);
5021 free_irq(dev->irq, hw_priv->dev);
5022
5023 transmit_cleanup(hw_priv, 0);
5024 hw_reset_pkts(&hw->rx_desc_info);
5025 hw_reset_pkts(&hw->tx_desc_info);
5026
5027 /* Clean out static MAC table when the switch is shutdown. */
5028 if (hw->features & STP_SUPPORT)
5029 sw_clr_sta_mac_table(hw);
5030 }
5031
5032 return 0;
5033}
5034
5035static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5036{
5037 if (hw->ksz_switch) {
5038 u32 data;
5039
5040 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5041 if (hw->features & RX_HUGE_FRAME)
5042 data |= SWITCH_HUGE_PACKET;
5043 else
5044 data &= ~SWITCH_HUGE_PACKET;
5045 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5046 }
5047 if (hw->features & RX_HUGE_FRAME) {
5048 hw->rx_cfg |= DMA_RX_ERROR;
5049 hw_priv->dev_rcv = dev_rcv_special;
5050 } else {
5051 hw->rx_cfg &= ~DMA_RX_ERROR;
5052 if (hw->dev_count > 1)
5053 hw_priv->dev_rcv = port_rcv_packets;
5054 else
5055 hw_priv->dev_rcv = dev_rcv_packets;
5056 }
5057}
5058
5059static int prepare_hardware(struct net_device *dev)
5060{
5061 struct dev_priv *priv = netdev_priv(dev);
5062 struct dev_info *hw_priv = priv->adapter;
5063 struct ksz_hw *hw = &hw_priv->hw;
5064 int rc = 0;
5065
5066 /* Remember the network device that requests interrupts. */
5067 hw_priv->dev = dev;
5068 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5069 if (rc)
5070 return rc;
5071 tasklet_setup(&hw_priv->rx_tasklet, rx_proc_task);
5072 tasklet_setup(&hw_priv->tx_tasklet, tx_proc_task);
5073
5074 hw->promiscuous = 0;
5075 hw->all_multi = 0;
5076 hw->multi_list_size = 0;
5077
5078 hw_reset(hw);
5079
5080 hw_set_desc_base(hw,
5081 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5082 hw_set_addr(hw);
5083 hw_cfg_huge_frame(hw_priv, hw);
5084 ksz_init_rx_buffers(hw_priv);
5085 return 0;
5086}
5087
5088static void set_media_state(struct net_device *dev, int media_state)
5089{
5090 struct dev_priv *priv = netdev_priv(dev);
5091
5092 if (media_state == priv->media_state)
5093 netif_carrier_on(dev);
5094 else
5095 netif_carrier_off(dev);
5096 netif_info(priv, link, dev, "link %s\n",
5097 media_state == priv->media_state ? "on" : "off");
5098}
5099
5100/**
5101 * netdev_open - open network device
5102 * @dev: Network device.
5103 *
5104 * This function process the open operation of network device. This is caused
5105 * by the user command "ifconfig ethX up."
5106 *
5107 * Return 0 if successful; otherwise an error code indicating failure.
5108 */
5109static int netdev_open(struct net_device *dev)
5110{
5111 struct dev_priv *priv = netdev_priv(dev);
5112 struct dev_info *hw_priv = priv->adapter;
5113 struct ksz_hw *hw = &hw_priv->hw;
5114 struct ksz_port *port = &priv->port;
5115 unsigned long next_jiffies;
5116 int i;
5117 int p;
5118 int rc = 0;
5119
5120 next_jiffies = jiffies + HZ * 2;
5121 priv->multicast = 0;
5122 priv->promiscuous = 0;
5123
5124 /* Reset device statistics. */
5125 memset(&dev->stats, 0, sizeof(struct net_device_stats));
5126 memset((void *) port->counter, 0,
5127 (sizeof(u64) * OID_COUNTER_LAST));
5128
5129 if (!(hw_priv->opened)) {
5130 rc = prepare_hardware(dev);
5131 if (rc)
5132 return rc;
5133 for (i = 0; i < hw->mib_port_cnt; i++) {
5134 next_jiffies += HZ * 1;
5135 hw_priv->counter[i].time = next_jiffies;
5136 hw->port_mib[i].state = media_disconnected;
5137 port_init_cnt(hw, i);
5138 }
5139 if (hw->ksz_switch)
5140 hw->port_mib[HOST_PORT].state = media_connected;
5141 else {
5142 hw_add_wol_bcast(hw);
5143 hw_cfg_wol_pme(hw, 0);
5144 hw_clr_wol_pme_status(&hw_priv->hw);
5145 }
5146 }
5147 port_set_power_saving(port, false);
5148
5149 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5150 /*
5151 * Initialize to invalid value so that link detection
5152 * is done.
5153 */
5154 hw->port_info[p].partner = 0xFF;
5155 hw->port_info[p].state = media_disconnected;
5156 }
5157
5158 /* Need to open the port in multiple device interfaces mode. */
5159 if (hw->dev_count > 1) {
5160 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5161 if (port->first_port > 0)
5162 hw_add_addr(hw, dev->dev_addr);
5163 }
5164
5165 port_get_link_speed(port);
5166 if (port->force_link)
5167 port_force_link_speed(port);
5168 else
5169 port_set_link_speed(port);
5170
5171 if (!(hw_priv->opened)) {
5172 hw_setup_intr(hw);
5173 hw_enable(hw);
5174 hw_ena_intr(hw);
5175
5176 if (hw->mib_port_cnt)
5177 ksz_start_timer(&hw_priv->mib_timer_info,
5178 hw_priv->mib_timer_info.period);
5179 }
5180
5181 hw_priv->opened++;
5182
5183 ksz_start_timer(&priv->monitor_timer_info,
5184 priv->monitor_timer_info.period);
5185
5186 priv->media_state = port->linked->state;
5187
5188 set_media_state(dev, media_connected);
5189 netif_start_queue(dev);
5190
5191 return 0;
5192}
5193
5194/* RX errors = rx_errors */
5195/* RX dropped = rx_dropped */
5196/* RX overruns = rx_fifo_errors */
5197/* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5198/* TX errors = tx_errors */
5199/* TX dropped = tx_dropped */
5200/* TX overruns = tx_fifo_errors */
5201/* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5202/* collisions = collisions */
5203
5204/**
5205 * netdev_query_statistics - query network device statistics
5206 * @dev: Network device.
5207 *
5208 * This function returns the statistics of the network device. The device
5209 * needs not be opened.
5210 *
5211 * Return network device statistics.
5212 */
5213static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5214{
5215 struct dev_priv *priv = netdev_priv(dev);
5216 struct ksz_port *port = &priv->port;
5217 struct ksz_hw *hw = &priv->adapter->hw;
5218 struct ksz_port_mib *mib;
5219 int i;
5220 int p;
5221
5222 dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5223 dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5224
5225 /* Reset to zero to add count later. */
5226 dev->stats.multicast = 0;
5227 dev->stats.collisions = 0;
5228 dev->stats.rx_length_errors = 0;
5229 dev->stats.rx_crc_errors = 0;
5230 dev->stats.rx_frame_errors = 0;
5231 dev->stats.tx_window_errors = 0;
5232
5233 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5234 mib = &hw->port_mib[p];
5235
5236 dev->stats.multicast += (unsigned long)
5237 mib->counter[MIB_COUNTER_RX_MULTICAST];
5238
5239 dev->stats.collisions += (unsigned long)
5240 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5241
5242 dev->stats.rx_length_errors += (unsigned long)(
5243 mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5244 mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5245 mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5246 mib->counter[MIB_COUNTER_RX_JABBER]);
5247 dev->stats.rx_crc_errors += (unsigned long)
5248 mib->counter[MIB_COUNTER_RX_CRC_ERR];
5249 dev->stats.rx_frame_errors += (unsigned long)(
5250 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5251 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5252
5253 dev->stats.tx_window_errors += (unsigned long)
5254 mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5255 }
5256
5257 return &dev->stats;
5258}
5259
5260/**
5261 * netdev_set_mac_address - set network device MAC address
5262 * @dev: Network device.
5263 * @addr: Buffer of MAC address.
5264 *
5265 * This function is used to set the MAC address of the network device.
5266 *
5267 * Return 0 to indicate success.
5268 */
5269static int netdev_set_mac_address(struct net_device *dev, void *addr)
5270{
5271 struct dev_priv *priv = netdev_priv(dev);
5272 struct dev_info *hw_priv = priv->adapter;
5273 struct ksz_hw *hw = &hw_priv->hw;
5274 struct sockaddr *mac = addr;
5275 uint interrupt;
5276
5277 if (priv->port.first_port > 0)
5278 hw_del_addr(hw, dev->dev_addr);
5279 else {
5280 hw->mac_override = 1;
5281 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN);
5282 }
5283
5284 eth_hw_addr_set(dev, mac->sa_data);
5285
5286 interrupt = hw_block_intr(hw);
5287
5288 if (priv->port.first_port > 0)
5289 hw_add_addr(hw, dev->dev_addr);
5290 else
5291 hw_set_addr(hw);
5292 hw_restore_intr(hw, interrupt);
5293
5294 return 0;
5295}
5296
5297static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5298 struct ksz_hw *hw, int promiscuous)
5299{
5300 if (promiscuous != priv->promiscuous) {
5301 u8 prev_state = hw->promiscuous;
5302
5303 if (promiscuous)
5304 ++hw->promiscuous;
5305 else
5306 --hw->promiscuous;
5307 priv->promiscuous = promiscuous;
5308
5309 /* Turn on/off promiscuous mode. */
5310 if (hw->promiscuous <= 1 && prev_state <= 1)
5311 hw_set_promiscuous(hw, hw->promiscuous);
5312
5313 /*
5314 * Port is not in promiscuous mode, meaning it is released
5315 * from the bridge.
5316 */
5317 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5318 netif_is_bridge_port(dev)) {
5319 struct ksz_switch *sw = hw->ksz_switch;
5320 int port = priv->port.first_port;
5321
5322 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5323 port = 1 << port;
5324 if (sw->member & port) {
5325 sw->member &= ~port;
5326 bridge_change(hw);
5327 }
5328 }
5329 }
5330}
5331
5332static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5333 int multicast)
5334{
5335 if (multicast != priv->multicast) {
5336 u8 all_multi = hw->all_multi;
5337
5338 if (multicast)
5339 ++hw->all_multi;
5340 else
5341 --hw->all_multi;
5342 priv->multicast = multicast;
5343
5344 /* Turn on/off all multicast mode. */
5345 if (hw->all_multi <= 1 && all_multi <= 1)
5346 hw_set_multicast(hw, hw->all_multi);
5347 }
5348}
5349
5350/**
5351 * netdev_set_rx_mode
5352 * @dev: Network device.
5353 *
5354 * This routine is used to set multicast addresses or put the network device
5355 * into promiscuous mode.
5356 */
5357static void netdev_set_rx_mode(struct net_device *dev)
5358{
5359 struct dev_priv *priv = netdev_priv(dev);
5360 struct dev_info *hw_priv = priv->adapter;
5361 struct ksz_hw *hw = &hw_priv->hw;
5362 struct netdev_hw_addr *ha;
5363 int multicast = (dev->flags & IFF_ALLMULTI);
5364
5365 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5366
5367 if (hw_priv->hw.dev_count > 1)
5368 multicast |= (dev->flags & IFF_MULTICAST);
5369 dev_set_multicast(priv, hw, multicast);
5370
5371 /* Cannot use different hashes in multiple device interfaces mode. */
5372 if (hw_priv->hw.dev_count > 1)
5373 return;
5374
5375 if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
5376 int i = 0;
5377
5378 /* List too big to support so turn on all multicast mode. */
5379 if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) {
5380 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5381 hw->multi_list_size = MAX_MULTICAST_LIST;
5382 ++hw->all_multi;
5383 hw_set_multicast(hw, hw->all_multi);
5384 }
5385 return;
5386 }
5387
5388 netdev_for_each_mc_addr(ha, dev) {
5389 if (i >= MAX_MULTICAST_LIST)
5390 break;
5391 memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN);
5392 }
5393 hw->multi_list_size = (u8) i;
5394 hw_set_grp_addr(hw);
5395 } else {
5396 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5397 --hw->all_multi;
5398 hw_set_multicast(hw, hw->all_multi);
5399 }
5400 hw->multi_list_size = 0;
5401 hw_clr_multicast(hw);
5402 }
5403}
5404
5405static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5406{
5407 struct dev_priv *priv = netdev_priv(dev);
5408 struct dev_info *hw_priv = priv->adapter;
5409 struct ksz_hw *hw = &hw_priv->hw;
5410 int hw_mtu;
5411
5412 if (netif_running(dev))
5413 return -EBUSY;
5414
5415 /* Cannot use different MTU in multiple device interfaces mode. */
5416 if (hw->dev_count > 1)
5417 if (dev != hw_priv->dev)
5418 return 0;
5419
5420 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5421 if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5422 hw->features |= RX_HUGE_FRAME;
5423 hw_mtu = MAX_RX_BUF_SIZE;
5424 } else {
5425 hw->features &= ~RX_HUGE_FRAME;
5426 hw_mtu = REGULAR_RX_BUF_SIZE;
5427 }
5428 hw_mtu = (hw_mtu + 3) & ~3;
5429 hw_priv->mtu = hw_mtu;
5430 dev->mtu = new_mtu;
5431
5432 return 0;
5433}
5434
5435/**
5436 * netdev_ioctl - I/O control processing
5437 * @dev: Network device.
5438 * @ifr: Interface request structure.
5439 * @cmd: I/O control code.
5440 *
5441 * This function is used to process I/O control calls.
5442 *
5443 * Return 0 to indicate success.
5444 */
5445static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5446{
5447 struct dev_priv *priv = netdev_priv(dev);
5448 struct dev_info *hw_priv = priv->adapter;
5449 struct ksz_hw *hw = &hw_priv->hw;
5450 struct ksz_port *port = &priv->port;
5451 int result = 0;
5452 struct mii_ioctl_data *data = if_mii(ifr);
5453
5454 if (down_interruptible(&priv->proc_sem))
5455 return -ERESTARTSYS;
5456
5457 switch (cmd) {
5458 /* Get address of MII PHY in use. */
5459 case SIOCGMIIPHY:
5460 data->phy_id = priv->id;
5461 fallthrough;
5462
5463 /* Read MII PHY register. */
5464 case SIOCGMIIREG:
5465 if (data->phy_id != priv->id || data->reg_num >= 6)
5466 result = -EIO;
5467 else
5468 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5469 &data->val_out);
5470 break;
5471
5472 /* Write MII PHY register. */
5473 case SIOCSMIIREG:
5474 if (!capable(CAP_NET_ADMIN))
5475 result = -EPERM;
5476 else if (data->phy_id != priv->id || data->reg_num >= 6)
5477 result = -EIO;
5478 else
5479 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5480 data->val_in);
5481 break;
5482
5483 default:
5484 result = -EOPNOTSUPP;
5485 }
5486
5487 up(&priv->proc_sem);
5488
5489 return result;
5490}
5491
5492/*
5493 * MII support
5494 */
5495
5496/**
5497 * mdio_read - read PHY register
5498 * @dev: Network device.
5499 * @phy_id: The PHY id.
5500 * @reg_num: The register number.
5501 *
5502 * This function returns the PHY register value.
5503 *
5504 * Return the register value.
5505 */
5506static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5507{
5508 struct dev_priv *priv = netdev_priv(dev);
5509 struct ksz_port *port = &priv->port;
5510 struct ksz_hw *hw = port->hw;
5511 u16 val_out;
5512
5513 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5514 return val_out;
5515}
5516
5517/**
5518 * mdio_write - set PHY register
5519 * @dev: Network device.
5520 * @phy_id: The PHY id.
5521 * @reg_num: The register number.
5522 * @val: The register value.
5523 *
5524 * This procedure sets the PHY register value.
5525 */
5526static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5527{
5528 struct dev_priv *priv = netdev_priv(dev);
5529 struct ksz_port *port = &priv->port;
5530 struct ksz_hw *hw = port->hw;
5531 int i;
5532 int pi;
5533
5534 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5535 hw_w_phy(hw, pi, reg_num << 1, val);
5536}
5537
5538/*
5539 * ethtool support
5540 */
5541
5542#define EEPROM_SIZE 0x40
5543
5544static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5545
5546#define ADVERTISED_ALL \
5547 (ADVERTISED_10baseT_Half | \
5548 ADVERTISED_10baseT_Full | \
5549 ADVERTISED_100baseT_Half | \
5550 ADVERTISED_100baseT_Full)
5551
5552/* These functions use the MII functions in mii.c. */
5553
5554/**
5555 * netdev_get_link_ksettings - get network device settings
5556 * @dev: Network device.
5557 * @cmd: Ethtool command.
5558 *
5559 * This function queries the PHY and returns its state in the ethtool command.
5560 *
5561 * Return 0 if successful; otherwise an error code.
5562 */
5563static int netdev_get_link_ksettings(struct net_device *dev,
5564 struct ethtool_link_ksettings *cmd)
5565{
5566 struct dev_priv *priv = netdev_priv(dev);
5567 struct dev_info *hw_priv = priv->adapter;
5568
5569 mutex_lock(&hw_priv->lock);
5570 mii_ethtool_get_link_ksettings(&priv->mii_if, cmd);
5571 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
5572 mutex_unlock(&hw_priv->lock);
5573
5574 /* Save advertised settings for workaround in next function. */
5575 ethtool_convert_link_mode_to_legacy_u32(&priv->advertising,
5576 cmd->link_modes.advertising);
5577
5578 return 0;
5579}
5580
5581/**
5582 * netdev_set_link_ksettings - set network device settings
5583 * @dev: Network device.
5584 * @cmd: Ethtool command.
5585 *
5586 * This function sets the PHY according to the ethtool command.
5587 *
5588 * Return 0 if successful; otherwise an error code.
5589 */
5590static int netdev_set_link_ksettings(struct net_device *dev,
5591 const struct ethtool_link_ksettings *cmd)
5592{
5593 struct dev_priv *priv = netdev_priv(dev);
5594 struct dev_info *hw_priv = priv->adapter;
5595 struct ksz_port *port = &priv->port;
5596 struct ethtool_link_ksettings copy_cmd;
5597 u32 speed = cmd->base.speed;
5598 u32 advertising;
5599 int rc;
5600
5601 ethtool_convert_link_mode_to_legacy_u32(&advertising,
5602 cmd->link_modes.advertising);
5603
5604 /*
5605 * ethtool utility does not change advertised setting if auto
5606 * negotiation is not specified explicitly.
5607 */
5608 if (cmd->base.autoneg && priv->advertising == advertising) {
5609 advertising |= ADVERTISED_ALL;
5610 if (10 == speed)
5611 advertising &=
5612 ~(ADVERTISED_100baseT_Full |
5613 ADVERTISED_100baseT_Half);
5614 else if (100 == speed)
5615 advertising &=
5616 ~(ADVERTISED_10baseT_Full |
5617 ADVERTISED_10baseT_Half);
5618 if (0 == cmd->base.duplex)
5619 advertising &=
5620 ~(ADVERTISED_100baseT_Full |
5621 ADVERTISED_10baseT_Full);
5622 else if (1 == cmd->base.duplex)
5623 advertising &=
5624 ~(ADVERTISED_100baseT_Half |
5625 ADVERTISED_10baseT_Half);
5626 }
5627 mutex_lock(&hw_priv->lock);
5628 if (cmd->base.autoneg &&
5629 (advertising & ADVERTISED_ALL) == ADVERTISED_ALL) {
5630 port->duplex = 0;
5631 port->speed = 0;
5632 port->force_link = 0;
5633 } else {
5634 port->duplex = cmd->base.duplex + 1;
5635 if (1000 != speed)
5636 port->speed = speed;
5637 if (cmd->base.autoneg)
5638 port->force_link = 0;
5639 else
5640 port->force_link = 1;
5641 }
5642
5643 memcpy(©_cmd, cmd, sizeof(copy_cmd));
5644 ethtool_convert_legacy_u32_to_link_mode(copy_cmd.link_modes.advertising,
5645 advertising);
5646 rc = mii_ethtool_set_link_ksettings(
5647 &priv->mii_if,
5648 (const struct ethtool_link_ksettings *)©_cmd);
5649 mutex_unlock(&hw_priv->lock);
5650 return rc;
5651}
5652
5653/**
5654 * netdev_nway_reset - restart auto-negotiation
5655 * @dev: Network device.
5656 *
5657 * This function restarts the PHY for auto-negotiation.
5658 *
5659 * Return 0 if successful; otherwise an error code.
5660 */
5661static int netdev_nway_reset(struct net_device *dev)
5662{
5663 struct dev_priv *priv = netdev_priv(dev);
5664 struct dev_info *hw_priv = priv->adapter;
5665 int rc;
5666
5667 mutex_lock(&hw_priv->lock);
5668 rc = mii_nway_restart(&priv->mii_if);
5669 mutex_unlock(&hw_priv->lock);
5670 return rc;
5671}
5672
5673/**
5674 * netdev_get_link - get network device link status
5675 * @dev: Network device.
5676 *
5677 * This function gets the link status from the PHY.
5678 *
5679 * Return true if PHY is linked and false otherwise.
5680 */
5681static u32 netdev_get_link(struct net_device *dev)
5682{
5683 struct dev_priv *priv = netdev_priv(dev);
5684 int rc;
5685
5686 rc = mii_link_ok(&priv->mii_if);
5687 return rc;
5688}
5689
5690/**
5691 * netdev_get_drvinfo - get network driver information
5692 * @dev: Network device.
5693 * @info: Ethtool driver info data structure.
5694 *
5695 * This procedure returns the driver information.
5696 */
5697static void netdev_get_drvinfo(struct net_device *dev,
5698 struct ethtool_drvinfo *info)
5699{
5700 struct dev_priv *priv = netdev_priv(dev);
5701 struct dev_info *hw_priv = priv->adapter;
5702
5703 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
5704 strscpy(info->version, DRV_VERSION, sizeof(info->version));
5705 strscpy(info->bus_info, pci_name(hw_priv->pdev),
5706 sizeof(info->bus_info));
5707}
5708
5709static struct hw_regs {
5710 int start;
5711 int end;
5712} hw_regs_range[] = {
5713 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS },
5714 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI },
5715 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
5716 { KS884X_SIDER_P, KS8842_SGCR7_P },
5717 { KS8842_MACAR1_P, KS8842_TOSR8_P },
5718 { KS884X_P1MBCR_P, KS8842_P3ERCR_P },
5719 { 0, 0 }
5720};
5721
5722/**
5723 * netdev_get_regs_len - get length of register dump
5724 * @dev: Network device.
5725 *
5726 * This function returns the length of the register dump.
5727 *
5728 * Return length of the register dump.
5729 */
5730static int netdev_get_regs_len(struct net_device *dev)
5731{
5732 struct hw_regs *range = hw_regs_range;
5733 int regs_len = 0x10 * sizeof(u32);
5734
5735 while (range->end > range->start) {
5736 regs_len += (range->end - range->start + 3) / 4 * 4;
5737 range++;
5738 }
5739 return regs_len;
5740}
5741
5742/**
5743 * netdev_get_regs - get register dump
5744 * @dev: Network device.
5745 * @regs: Ethtool registers data structure.
5746 * @ptr: Buffer to store the register values.
5747 *
5748 * This procedure dumps the register values in the provided buffer.
5749 */
5750static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
5751 void *ptr)
5752{
5753 struct dev_priv *priv = netdev_priv(dev);
5754 struct dev_info *hw_priv = priv->adapter;
5755 struct ksz_hw *hw = &hw_priv->hw;
5756 int *buf = (int *) ptr;
5757 struct hw_regs *range = hw_regs_range;
5758 int len;
5759
5760 mutex_lock(&hw_priv->lock);
5761 regs->version = 0;
5762 for (len = 0; len < 0x40; len += 4) {
5763 pci_read_config_dword(hw_priv->pdev, len, buf);
5764 buf++;
5765 }
5766 while (range->end > range->start) {
5767 for (len = range->start; len < range->end; len += 4) {
5768 *buf = readl(hw->io + len);
5769 buf++;
5770 }
5771 range++;
5772 }
5773 mutex_unlock(&hw_priv->lock);
5774}
5775
5776#define WOL_SUPPORT \
5777 (WAKE_PHY | WAKE_MAGIC | \
5778 WAKE_UCAST | WAKE_MCAST | \
5779 WAKE_BCAST | WAKE_ARP)
5780
5781/**
5782 * netdev_get_wol - get Wake-on-LAN support
5783 * @dev: Network device.
5784 * @wol: Ethtool Wake-on-LAN data structure.
5785 *
5786 * This procedure returns Wake-on-LAN support.
5787 */
5788static void netdev_get_wol(struct net_device *dev,
5789 struct ethtool_wolinfo *wol)
5790{
5791 struct dev_priv *priv = netdev_priv(dev);
5792 struct dev_info *hw_priv = priv->adapter;
5793
5794 wol->supported = hw_priv->wol_support;
5795 wol->wolopts = hw_priv->wol_enable;
5796 memset(&wol->sopass, 0, sizeof(wol->sopass));
5797}
5798
5799/**
5800 * netdev_set_wol - set Wake-on-LAN support
5801 * @dev: Network device.
5802 * @wol: Ethtool Wake-on-LAN data structure.
5803 *
5804 * This function sets Wake-on-LAN support.
5805 *
5806 * Return 0 if successful; otherwise an error code.
5807 */
5808static int netdev_set_wol(struct net_device *dev,
5809 struct ethtool_wolinfo *wol)
5810{
5811 struct dev_priv *priv = netdev_priv(dev);
5812 struct dev_info *hw_priv = priv->adapter;
5813
5814 /* Need to find a way to retrieve the device IP address. */
5815 static const u8 net_addr[] = { 192, 168, 1, 1 };
5816
5817 if (wol->wolopts & ~hw_priv->wol_support)
5818 return -EINVAL;
5819
5820 hw_priv->wol_enable = wol->wolopts;
5821
5822 /* Link wakeup cannot really be disabled. */
5823 if (wol->wolopts)
5824 hw_priv->wol_enable |= WAKE_PHY;
5825 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
5826 return 0;
5827}
5828
5829/**
5830 * netdev_get_msglevel - get debug message level
5831 * @dev: Network device.
5832 *
5833 * This function returns current debug message level.
5834 *
5835 * Return current debug message flags.
5836 */
5837static u32 netdev_get_msglevel(struct net_device *dev)
5838{
5839 struct dev_priv *priv = netdev_priv(dev);
5840
5841 return priv->msg_enable;
5842}
5843
5844/**
5845 * netdev_set_msglevel - set debug message level
5846 * @dev: Network device.
5847 * @value: Debug message flags.
5848 *
5849 * This procedure sets debug message level.
5850 */
5851static void netdev_set_msglevel(struct net_device *dev, u32 value)
5852{
5853 struct dev_priv *priv = netdev_priv(dev);
5854
5855 priv->msg_enable = value;
5856}
5857
5858/**
5859 * netdev_get_eeprom_len - get EEPROM length
5860 * @dev: Network device.
5861 *
5862 * This function returns the length of the EEPROM.
5863 *
5864 * Return length of the EEPROM.
5865 */
5866static int netdev_get_eeprom_len(struct net_device *dev)
5867{
5868 return EEPROM_SIZE * 2;
5869}
5870
5871#define EEPROM_MAGIC 0x10A18842
5872
5873/**
5874 * netdev_get_eeprom - get EEPROM data
5875 * @dev: Network device.
5876 * @eeprom: Ethtool EEPROM data structure.
5877 * @data: Buffer to store the EEPROM data.
5878 *
5879 * This function dumps the EEPROM data in the provided buffer.
5880 *
5881 * Return 0 if successful; otherwise an error code.
5882 */
5883static int netdev_get_eeprom(struct net_device *dev,
5884 struct ethtool_eeprom *eeprom, u8 *data)
5885{
5886 struct dev_priv *priv = netdev_priv(dev);
5887 struct dev_info *hw_priv = priv->adapter;
5888 u8 *eeprom_byte = (u8 *) eeprom_data;
5889 int i;
5890 int len;
5891
5892 len = (eeprom->offset + eeprom->len + 1) / 2;
5893 for (i = eeprom->offset / 2; i < len; i++)
5894 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
5895 eeprom->magic = EEPROM_MAGIC;
5896 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
5897
5898 return 0;
5899}
5900
5901/**
5902 * netdev_set_eeprom - write EEPROM data
5903 * @dev: Network device.
5904 * @eeprom: Ethtool EEPROM data structure.
5905 * @data: Data buffer.
5906 *
5907 * This function modifies the EEPROM data one byte at a time.
5908 *
5909 * Return 0 if successful; otherwise an error code.
5910 */
5911static int netdev_set_eeprom(struct net_device *dev,
5912 struct ethtool_eeprom *eeprom, u8 *data)
5913{
5914 struct dev_priv *priv = netdev_priv(dev);
5915 struct dev_info *hw_priv = priv->adapter;
5916 u16 eeprom_word[EEPROM_SIZE];
5917 u8 *eeprom_byte = (u8 *) eeprom_word;
5918 int i;
5919 int len;
5920
5921 if (eeprom->magic != EEPROM_MAGIC)
5922 return -EINVAL;
5923
5924 len = (eeprom->offset + eeprom->len + 1) / 2;
5925 for (i = eeprom->offset / 2; i < len; i++)
5926 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
5927 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
5928 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
5929 for (i = 0; i < EEPROM_SIZE; i++)
5930 if (eeprom_word[i] != eeprom_data[i]) {
5931 eeprom_data[i] = eeprom_word[i];
5932 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
5933 }
5934
5935 return 0;
5936}
5937
5938/**
5939 * netdev_get_pauseparam - get flow control parameters
5940 * @dev: Network device.
5941 * @pause: Ethtool PAUSE settings data structure.
5942 *
5943 * This procedure returns the PAUSE control flow settings.
5944 */
5945static void netdev_get_pauseparam(struct net_device *dev,
5946 struct ethtool_pauseparam *pause)
5947{
5948 struct dev_priv *priv = netdev_priv(dev);
5949 struct dev_info *hw_priv = priv->adapter;
5950 struct ksz_hw *hw = &hw_priv->hw;
5951
5952 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
5953 if (!hw->ksz_switch) {
5954 pause->rx_pause =
5955 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
5956 pause->tx_pause =
5957 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
5958 } else {
5959 pause->rx_pause =
5960 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
5961 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
5962 pause->tx_pause =
5963 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
5964 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
5965 }
5966}
5967
5968/**
5969 * netdev_set_pauseparam - set flow control parameters
5970 * @dev: Network device.
5971 * @pause: Ethtool PAUSE settings data structure.
5972 *
5973 * This function sets the PAUSE control flow settings.
5974 * Not implemented yet.
5975 *
5976 * Return 0 if successful; otherwise an error code.
5977 */
5978static int netdev_set_pauseparam(struct net_device *dev,
5979 struct ethtool_pauseparam *pause)
5980{
5981 struct dev_priv *priv = netdev_priv(dev);
5982 struct dev_info *hw_priv = priv->adapter;
5983 struct ksz_hw *hw = &hw_priv->hw;
5984 struct ksz_port *port = &priv->port;
5985
5986 mutex_lock(&hw_priv->lock);
5987 if (pause->autoneg) {
5988 if (!pause->rx_pause && !pause->tx_pause)
5989 port->flow_ctrl = PHY_NO_FLOW_CTRL;
5990 else
5991 port->flow_ctrl = PHY_FLOW_CTRL;
5992 hw->overrides &= ~PAUSE_FLOW_CTRL;
5993 port->force_link = 0;
5994 if (hw->ksz_switch) {
5995 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
5996 SWITCH_RX_FLOW_CTRL, 1);
5997 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
5998 SWITCH_TX_FLOW_CTRL, 1);
5999 }
6000 port_set_link_speed(port);
6001 } else {
6002 hw->overrides |= PAUSE_FLOW_CTRL;
6003 if (hw->ksz_switch) {
6004 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6005 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6006 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6007 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6008 } else
6009 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6010 }
6011 mutex_unlock(&hw_priv->lock);
6012
6013 return 0;
6014}
6015
6016/**
6017 * netdev_get_ringparam - get tx/rx ring parameters
6018 * @dev: Network device.
6019 * @ring: Ethtool RING settings data structure.
6020 * @kernel_ring: Ethtool external RING settings data structure.
6021 * @extack: Netlink handle.
6022 *
6023 * This procedure returns the TX/RX ring settings.
6024 */
6025static void netdev_get_ringparam(struct net_device *dev,
6026 struct ethtool_ringparam *ring,
6027 struct kernel_ethtool_ringparam *kernel_ring,
6028 struct netlink_ext_ack *extack)
6029{
6030 struct dev_priv *priv = netdev_priv(dev);
6031 struct dev_info *hw_priv = priv->adapter;
6032 struct ksz_hw *hw = &hw_priv->hw;
6033
6034 ring->tx_max_pending = (1 << 9);
6035 ring->tx_pending = hw->tx_desc_info.alloc;
6036 ring->rx_max_pending = (1 << 9);
6037 ring->rx_pending = hw->rx_desc_info.alloc;
6038}
6039
6040#define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6041
6042static struct {
6043 char string[ETH_GSTRING_LEN];
6044} ethtool_stats_keys[STATS_LEN] = {
6045 { "rx_lo_priority_octets" },
6046 { "rx_hi_priority_octets" },
6047 { "rx_undersize_packets" },
6048 { "rx_fragments" },
6049 { "rx_oversize_packets" },
6050 { "rx_jabbers" },
6051 { "rx_symbol_errors" },
6052 { "rx_crc_errors" },
6053 { "rx_align_errors" },
6054 { "rx_mac_ctrl_packets" },
6055 { "rx_pause_packets" },
6056 { "rx_bcast_packets" },
6057 { "rx_mcast_packets" },
6058 { "rx_ucast_packets" },
6059 { "rx_64_or_less_octet_packets" },
6060 { "rx_65_to_127_octet_packets" },
6061 { "rx_128_to_255_octet_packets" },
6062 { "rx_256_to_511_octet_packets" },
6063 { "rx_512_to_1023_octet_packets" },
6064 { "rx_1024_to_1522_octet_packets" },
6065
6066 { "tx_lo_priority_octets" },
6067 { "tx_hi_priority_octets" },
6068 { "tx_late_collisions" },
6069 { "tx_pause_packets" },
6070 { "tx_bcast_packets" },
6071 { "tx_mcast_packets" },
6072 { "tx_ucast_packets" },
6073 { "tx_deferred" },
6074 { "tx_total_collisions" },
6075 { "tx_excessive_collisions" },
6076 { "tx_single_collisions" },
6077 { "tx_mult_collisions" },
6078
6079 { "rx_discards" },
6080 { "tx_discards" },
6081};
6082
6083/**
6084 * netdev_get_strings - get statistics identity strings
6085 * @dev: Network device.
6086 * @stringset: String set identifier.
6087 * @buf: Buffer to store the strings.
6088 *
6089 * This procedure returns the strings used to identify the statistics.
6090 */
6091static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6092{
6093 struct dev_priv *priv = netdev_priv(dev);
6094 struct dev_info *hw_priv = priv->adapter;
6095 struct ksz_hw *hw = &hw_priv->hw;
6096
6097 if (ETH_SS_STATS == stringset)
6098 memcpy(buf, ðtool_stats_keys,
6099 ETH_GSTRING_LEN * hw->mib_cnt);
6100}
6101
6102/**
6103 * netdev_get_sset_count - get statistics size
6104 * @dev: Network device.
6105 * @sset: The statistics set number.
6106 *
6107 * This function returns the size of the statistics to be reported.
6108 *
6109 * Return size of the statistics to be reported.
6110 */
6111static int netdev_get_sset_count(struct net_device *dev, int sset)
6112{
6113 struct dev_priv *priv = netdev_priv(dev);
6114 struct dev_info *hw_priv = priv->adapter;
6115 struct ksz_hw *hw = &hw_priv->hw;
6116
6117 switch (sset) {
6118 case ETH_SS_STATS:
6119 return hw->mib_cnt;
6120 default:
6121 return -EOPNOTSUPP;
6122 }
6123}
6124
6125/**
6126 * netdev_get_ethtool_stats - get network device statistics
6127 * @dev: Network device.
6128 * @stats: Ethtool statistics data structure.
6129 * @data: Buffer to store the statistics.
6130 *
6131 * This procedure returns the statistics.
6132 */
6133static void netdev_get_ethtool_stats(struct net_device *dev,
6134 struct ethtool_stats *stats, u64 *data)
6135{
6136 struct dev_priv *priv = netdev_priv(dev);
6137 struct dev_info *hw_priv = priv->adapter;
6138 struct ksz_hw *hw = &hw_priv->hw;
6139 struct ksz_port *port = &priv->port;
6140 int n_stats = stats->n_stats;
6141 int i;
6142 int n;
6143 int p;
6144 u64 counter[TOTAL_PORT_COUNTER_NUM];
6145
6146 mutex_lock(&hw_priv->lock);
6147 n = SWITCH_PORT_NUM;
6148 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6149 if (media_connected == hw->port_mib[p].state) {
6150 hw_priv->counter[p].read = 1;
6151
6152 /* Remember first port that requests read. */
6153 if (n == SWITCH_PORT_NUM)
6154 n = p;
6155 }
6156 }
6157 mutex_unlock(&hw_priv->lock);
6158
6159 if (n < SWITCH_PORT_NUM)
6160 schedule_work(&hw_priv->mib_read);
6161
6162 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6163 p = n;
6164 wait_event_interruptible_timeout(
6165 hw_priv->counter[p].counter,
6166 2 == hw_priv->counter[p].read,
6167 HZ * 1);
6168 } else
6169 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6170 if (0 == i) {
6171 wait_event_interruptible_timeout(
6172 hw_priv->counter[p].counter,
6173 2 == hw_priv->counter[p].read,
6174 HZ * 2);
6175 } else if (hw->port_mib[p].cnt_ptr) {
6176 wait_event_interruptible_timeout(
6177 hw_priv->counter[p].counter,
6178 2 == hw_priv->counter[p].read,
6179 HZ * 1);
6180 }
6181 }
6182
6183 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6184 n = hw->mib_cnt;
6185 if (n > n_stats)
6186 n = n_stats;
6187 n_stats -= n;
6188 for (i = 0; i < n; i++)
6189 *data++ = counter[i];
6190}
6191
6192/**
6193 * netdev_set_features - set receive checksum support
6194 * @dev: Network device.
6195 * @features: New device features (offloads).
6196 *
6197 * This function sets receive checksum support setting.
6198 *
6199 * Return 0 if successful; otherwise an error code.
6200 */
6201static int netdev_set_features(struct net_device *dev,
6202 netdev_features_t features)
6203{
6204 struct dev_priv *priv = netdev_priv(dev);
6205 struct dev_info *hw_priv = priv->adapter;
6206 struct ksz_hw *hw = &hw_priv->hw;
6207
6208 mutex_lock(&hw_priv->lock);
6209
6210 /* see note in hw_setup() */
6211 if (features & NETIF_F_RXCSUM)
6212 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6213 else
6214 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6215
6216 if (hw->enabled)
6217 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6218
6219 mutex_unlock(&hw_priv->lock);
6220
6221 return 0;
6222}
6223
6224static const struct ethtool_ops netdev_ethtool_ops = {
6225 .nway_reset = netdev_nway_reset,
6226 .get_link = netdev_get_link,
6227 .get_drvinfo = netdev_get_drvinfo,
6228 .get_regs_len = netdev_get_regs_len,
6229 .get_regs = netdev_get_regs,
6230 .get_wol = netdev_get_wol,
6231 .set_wol = netdev_set_wol,
6232 .get_msglevel = netdev_get_msglevel,
6233 .set_msglevel = netdev_set_msglevel,
6234 .get_eeprom_len = netdev_get_eeprom_len,
6235 .get_eeprom = netdev_get_eeprom,
6236 .set_eeprom = netdev_set_eeprom,
6237 .get_pauseparam = netdev_get_pauseparam,
6238 .set_pauseparam = netdev_set_pauseparam,
6239 .get_ringparam = netdev_get_ringparam,
6240 .get_strings = netdev_get_strings,
6241 .get_sset_count = netdev_get_sset_count,
6242 .get_ethtool_stats = netdev_get_ethtool_stats,
6243 .get_link_ksettings = netdev_get_link_ksettings,
6244 .set_link_ksettings = netdev_set_link_ksettings,
6245};
6246
6247/*
6248 * Hardware monitoring
6249 */
6250
6251static void update_link(struct net_device *dev, struct dev_priv *priv,
6252 struct ksz_port *port)
6253{
6254 if (priv->media_state != port->linked->state) {
6255 priv->media_state = port->linked->state;
6256 if (netif_running(dev))
6257 set_media_state(dev, media_connected);
6258 }
6259}
6260
6261static void mib_read_work(struct work_struct *work)
6262{
6263 struct dev_info *hw_priv =
6264 container_of(work, struct dev_info, mib_read);
6265 struct ksz_hw *hw = &hw_priv->hw;
6266 unsigned long next_jiffies;
6267 struct ksz_port_mib *mib;
6268 int i;
6269
6270 next_jiffies = jiffies;
6271 for (i = 0; i < hw->mib_port_cnt; i++) {
6272 mib = &hw->port_mib[i];
6273
6274 /* Reading MIB counters or requested to read. */
6275 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6276
6277 /* Need to process receive interrupt. */
6278 if (port_r_cnt(hw, i))
6279 break;
6280 hw_priv->counter[i].read = 0;
6281
6282 /* Finish reading counters. */
6283 if (0 == mib->cnt_ptr) {
6284 hw_priv->counter[i].read = 2;
6285 wake_up_interruptible(
6286 &hw_priv->counter[i].counter);
6287 }
6288 } else if (time_after_eq(jiffies, hw_priv->counter[i].time)) {
6289 /* Only read MIB counters when the port is connected. */
6290 if (media_connected == mib->state)
6291 hw_priv->counter[i].read = 1;
6292 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6293 hw_priv->counter[i].time = next_jiffies;
6294
6295 /* Port is just disconnected. */
6296 } else if (mib->link_down) {
6297 mib->link_down = 0;
6298
6299 /* Read counters one last time after link is lost. */
6300 hw_priv->counter[i].read = 1;
6301 }
6302 }
6303}
6304
6305static void mib_monitor(struct timer_list *t)
6306{
6307 struct dev_info *hw_priv = from_timer(hw_priv, t, mib_timer_info.timer);
6308
6309 mib_read_work(&hw_priv->mib_read);
6310
6311 /* This is used to verify Wake-on-LAN is working. */
6312 if (hw_priv->pme_wait) {
6313 if (time_is_before_eq_jiffies(hw_priv->pme_wait)) {
6314 hw_clr_wol_pme_status(&hw_priv->hw);
6315 hw_priv->pme_wait = 0;
6316 }
6317 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6318
6319 /* PME is asserted. Wait 2 seconds to clear it. */
6320 hw_priv->pme_wait = jiffies + HZ * 2;
6321 }
6322
6323 ksz_update_timer(&hw_priv->mib_timer_info);
6324}
6325
6326/**
6327 * dev_monitor - periodic monitoring
6328 * @t: timer list containing a network device pointer.
6329 *
6330 * This routine is run in a kernel timer to monitor the network device.
6331 */
6332static void dev_monitor(struct timer_list *t)
6333{
6334 struct dev_priv *priv = from_timer(priv, t, monitor_timer_info.timer);
6335 struct net_device *dev = priv->mii_if.dev;
6336 struct dev_info *hw_priv = priv->adapter;
6337 struct ksz_hw *hw = &hw_priv->hw;
6338 struct ksz_port *port = &priv->port;
6339
6340 if (!(hw->features & LINK_INT_WORKING))
6341 port_get_link_speed(port);
6342 update_link(dev, priv, port);
6343
6344 ksz_update_timer(&priv->monitor_timer_info);
6345}
6346
6347/*
6348 * Linux network device interface functions
6349 */
6350
6351/* Driver exported variables */
6352
6353static int msg_enable;
6354
6355static char *macaddr = ":";
6356static char *mac1addr = ":";
6357
6358/*
6359 * This enables multiple network device mode for KSZ8842, which contains a
6360 * switch with two physical ports. Some users like to take control of the
6361 * ports for running Spanning Tree Protocol. The driver will create an
6362 * additional eth? device for the other port.
6363 *
6364 * Some limitations are the network devices cannot have different MTU and
6365 * multicast hash tables.
6366 */
6367static int multi_dev;
6368
6369/*
6370 * As most users select multiple network device mode to use Spanning Tree
6371 * Protocol, this enables a feature in which most unicast and multicast packets
6372 * are forwarded inside the switch and not passed to the host. Only packets
6373 * that need the host's attention are passed to it. This prevents the host
6374 * wasting CPU time to examine each and every incoming packets and do the
6375 * forwarding itself.
6376 *
6377 * As the hack requires the private bridge header, the driver cannot compile
6378 * with just the kernel headers.
6379 *
6380 * Enabling STP support also turns on multiple network device mode.
6381 */
6382static int stp;
6383
6384/*
6385 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6386 * needs that. However, fast aging is used to flush the dynamic MAC table when
6387 * STP support is enabled.
6388 */
6389static int fast_aging;
6390
6391/**
6392 * netdev_init - initialize network device.
6393 * @dev: Network device.
6394 *
6395 * This function initializes the network device.
6396 *
6397 * Return 0 if successful; otherwise an error code indicating failure.
6398 */
6399static int __init netdev_init(struct net_device *dev)
6400{
6401 struct dev_priv *priv = netdev_priv(dev);
6402
6403 /* 500 ms timeout */
6404 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6405 dev_monitor);
6406
6407 /* 500 ms timeout */
6408 dev->watchdog_timeo = HZ / 2;
6409
6410 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_RXCSUM;
6411
6412 /*
6413 * Hardware does not really support IPv6 checksum generation, but
6414 * driver actually runs faster with this on.
6415 */
6416 dev->hw_features |= NETIF_F_IPV6_CSUM;
6417
6418 dev->features |= dev->hw_features;
6419
6420 sema_init(&priv->proc_sem, 1);
6421
6422 priv->mii_if.phy_id_mask = 0x1;
6423 priv->mii_if.reg_num_mask = 0x7;
6424 priv->mii_if.dev = dev;
6425 priv->mii_if.mdio_read = mdio_read;
6426 priv->mii_if.mdio_write = mdio_write;
6427 priv->mii_if.phy_id = priv->port.first_port + 1;
6428
6429 priv->msg_enable = netif_msg_init(msg_enable,
6430 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6431
6432 return 0;
6433}
6434
6435static const struct net_device_ops netdev_ops = {
6436 .ndo_init = netdev_init,
6437 .ndo_open = netdev_open,
6438 .ndo_stop = netdev_close,
6439 .ndo_get_stats = netdev_query_statistics,
6440 .ndo_start_xmit = netdev_tx,
6441 .ndo_tx_timeout = netdev_tx_timeout,
6442 .ndo_change_mtu = netdev_change_mtu,
6443 .ndo_set_features = netdev_set_features,
6444 .ndo_set_mac_address = netdev_set_mac_address,
6445 .ndo_validate_addr = eth_validate_addr,
6446 .ndo_eth_ioctl = netdev_ioctl,
6447 .ndo_set_rx_mode = netdev_set_rx_mode,
6448#ifdef CONFIG_NET_POLL_CONTROLLER
6449 .ndo_poll_controller = netdev_netpoll,
6450#endif
6451};
6452
6453static void netdev_free(struct net_device *dev)
6454{
6455 if (dev->watchdog_timeo)
6456 unregister_netdev(dev);
6457
6458 free_netdev(dev);
6459}
6460
6461struct platform_info {
6462 struct dev_info dev_info;
6463 struct net_device *netdev[SWITCH_PORT_NUM];
6464};
6465
6466static int net_device_present;
6467
6468static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6469{
6470 int i;
6471 int j;
6472 int got_num;
6473 int num;
6474
6475 i = j = num = got_num = 0;
6476 while (j < ETH_ALEN) {
6477 if (macaddr[i]) {
6478 int digit;
6479
6480 got_num = 1;
6481 digit = hex_to_bin(macaddr[i]);
6482 if (digit >= 0)
6483 num = num * 16 + digit;
6484 else if (':' == macaddr[i])
6485 got_num = 2;
6486 else
6487 break;
6488 } else if (got_num)
6489 got_num = 2;
6490 else
6491 break;
6492 if (2 == got_num) {
6493 if (MAIN_PORT == port) {
6494 hw_priv->hw.override_addr[j++] = (u8) num;
6495 hw_priv->hw.override_addr[5] +=
6496 hw_priv->hw.id;
6497 } else {
6498 hw_priv->hw.ksz_switch->other_addr[j++] =
6499 (u8) num;
6500 hw_priv->hw.ksz_switch->other_addr[5] +=
6501 hw_priv->hw.id;
6502 }
6503 num = got_num = 0;
6504 }
6505 i++;
6506 }
6507 if (ETH_ALEN == j) {
6508 if (MAIN_PORT == port)
6509 hw_priv->hw.mac_override = 1;
6510 }
6511}
6512
6513#define KS884X_DMA_MASK (~0x0UL)
6514
6515static void read_other_addr(struct ksz_hw *hw)
6516{
6517 int i;
6518 u16 data[3];
6519 struct ksz_switch *sw = hw->ksz_switch;
6520
6521 for (i = 0; i < 3; i++)
6522 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6523 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6524 sw->other_addr[5] = (u8) data[0];
6525 sw->other_addr[4] = (u8)(data[0] >> 8);
6526 sw->other_addr[3] = (u8) data[1];
6527 sw->other_addr[2] = (u8)(data[1] >> 8);
6528 sw->other_addr[1] = (u8) data[2];
6529 sw->other_addr[0] = (u8)(data[2] >> 8);
6530 }
6531}
6532
6533#ifndef PCI_VENDOR_ID_MICREL_KS
6534#define PCI_VENDOR_ID_MICREL_KS 0x16c6
6535#endif
6536
6537static int pcidev_init(struct pci_dev *pdev, const struct pci_device_id *id)
6538{
6539 struct net_device *dev;
6540 struct dev_priv *priv;
6541 struct dev_info *hw_priv;
6542 struct ksz_hw *hw;
6543 struct platform_info *info;
6544 struct ksz_port *port;
6545 unsigned long reg_base;
6546 unsigned long reg_len;
6547 int cnt;
6548 int i;
6549 int mib_port_count;
6550 int pi;
6551 int port_count;
6552 int result;
6553 char banner[sizeof(version)];
6554 struct ksz_switch *sw = NULL;
6555
6556 result = pcim_enable_device(pdev);
6557 if (result)
6558 return result;
6559
6560 result = -ENODEV;
6561
6562 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) ||
6563 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)))
6564 return result;
6565
6566 reg_base = pci_resource_start(pdev, 0);
6567 reg_len = pci_resource_len(pdev, 0);
6568 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
6569 return result;
6570
6571 if (!request_mem_region(reg_base, reg_len, DRV_NAME))
6572 return result;
6573 pci_set_master(pdev);
6574
6575 result = -ENOMEM;
6576
6577 info = kzalloc(sizeof(struct platform_info), GFP_KERNEL);
6578 if (!info)
6579 goto pcidev_init_dev_err;
6580
6581 hw_priv = &info->dev_info;
6582 hw_priv->pdev = pdev;
6583
6584 hw = &hw_priv->hw;
6585
6586 hw->io = ioremap(reg_base, reg_len);
6587 if (!hw->io)
6588 goto pcidev_init_io_err;
6589
6590 cnt = hw_init(hw);
6591 if (!cnt) {
6592 if (msg_enable & NETIF_MSG_PROBE)
6593 pr_alert("chip not detected\n");
6594 result = -ENODEV;
6595 goto pcidev_init_alloc_err;
6596 }
6597
6598 snprintf(banner, sizeof(banner), "%s", version);
6599 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */
6600 dev_info(&hw_priv->pdev->dev, "%s\n", banner);
6601 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
6602
6603 /* Assume device is KSZ8841. */
6604 hw->dev_count = 1;
6605 port_count = 1;
6606 mib_port_count = 1;
6607 hw->addr_list_size = 0;
6608 hw->mib_cnt = PORT_COUNTER_NUM;
6609 hw->mib_port_cnt = 1;
6610
6611 /* KSZ8842 has a switch with multiple ports. */
6612 if (2 == cnt) {
6613 if (fast_aging)
6614 hw->overrides |= FAST_AGING;
6615
6616 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
6617
6618 /* Multiple network device interfaces are required. */
6619 if (multi_dev) {
6620 hw->dev_count = SWITCH_PORT_NUM;
6621 hw->addr_list_size = SWITCH_PORT_NUM - 1;
6622 }
6623
6624 /* Single network device has multiple ports. */
6625 if (1 == hw->dev_count) {
6626 port_count = SWITCH_PORT_NUM;
6627 mib_port_count = SWITCH_PORT_NUM;
6628 }
6629 hw->mib_port_cnt = TOTAL_PORT_NUM;
6630 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL);
6631 if (!hw->ksz_switch)
6632 goto pcidev_init_alloc_err;
6633
6634 sw = hw->ksz_switch;
6635 }
6636 for (i = 0; i < hw->mib_port_cnt; i++)
6637 hw->port_mib[i].mib_start = 0;
6638
6639 hw->parent = hw_priv;
6640
6641 /* Default MTU is 1500. */
6642 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
6643
6644 if (ksz_alloc_mem(hw_priv))
6645 goto pcidev_init_mem_err;
6646
6647 hw_priv->hw.id = net_device_present;
6648
6649 spin_lock_init(&hw_priv->hwlock);
6650 mutex_init(&hw_priv->lock);
6651
6652 for (i = 0; i < TOTAL_PORT_NUM; i++)
6653 init_waitqueue_head(&hw_priv->counter[i].counter);
6654
6655 if (macaddr[0] != ':')
6656 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
6657
6658 /* Read MAC address and initialize override address if not overridden. */
6659 hw_read_addr(hw);
6660
6661 /* Multiple device interfaces mode requires a second MAC address. */
6662 if (hw->dev_count > 1) {
6663 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN);
6664 read_other_addr(hw);
6665 if (mac1addr[0] != ':')
6666 get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
6667 }
6668
6669 hw_setup(hw);
6670 if (hw->ksz_switch)
6671 sw_setup(hw);
6672 else {
6673 hw_priv->wol_support = WOL_SUPPORT;
6674 hw_priv->wol_enable = 0;
6675 }
6676
6677 INIT_WORK(&hw_priv->mib_read, mib_read_work);
6678
6679 /* 500 ms timeout */
6680 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
6681 mib_monitor);
6682
6683 for (i = 0; i < hw->dev_count; i++) {
6684 dev = alloc_etherdev(sizeof(struct dev_priv));
6685 if (!dev)
6686 goto pcidev_init_reg_err;
6687 SET_NETDEV_DEV(dev, &pdev->dev);
6688 info->netdev[i] = dev;
6689
6690 priv = netdev_priv(dev);
6691 priv->adapter = hw_priv;
6692 priv->id = net_device_present++;
6693
6694 port = &priv->port;
6695 port->port_cnt = port_count;
6696 port->mib_port_cnt = mib_port_count;
6697 port->first_port = i;
6698 port->flow_ctrl = PHY_FLOW_CTRL;
6699
6700 port->hw = hw;
6701 port->linked = &hw->port_info[port->first_port];
6702
6703 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
6704 hw->port_info[pi].port_id = pi;
6705 hw->port_info[pi].pdev = dev;
6706 hw->port_info[pi].state = media_disconnected;
6707 }
6708
6709 dev->mem_start = (unsigned long) hw->io;
6710 dev->mem_end = dev->mem_start + reg_len - 1;
6711 dev->irq = pdev->irq;
6712 if (MAIN_PORT == i)
6713 eth_hw_addr_set(dev, hw_priv->hw.override_addr);
6714 else {
6715 u8 addr[ETH_ALEN];
6716
6717 ether_addr_copy(addr, sw->other_addr);
6718 if (ether_addr_equal(sw->other_addr, hw->override_addr))
6719 addr[5] += port->first_port;
6720 eth_hw_addr_set(dev, addr);
6721 }
6722
6723 dev->netdev_ops = &netdev_ops;
6724 dev->ethtool_ops = &netdev_ethtool_ops;
6725
6726 /* MTU range: 60 - 1894 */
6727 dev->min_mtu = ETH_ZLEN;
6728 dev->max_mtu = MAX_RX_BUF_SIZE -
6729 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
6730
6731 if (register_netdev(dev))
6732 goto pcidev_init_reg_err;
6733 port_set_power_saving(port, true);
6734 }
6735
6736 pci_dev_get(hw_priv->pdev);
6737 pci_set_drvdata(pdev, info);
6738 return 0;
6739
6740pcidev_init_reg_err:
6741 for (i = 0; i < hw->dev_count; i++) {
6742 if (info->netdev[i]) {
6743 netdev_free(info->netdev[i]);
6744 info->netdev[i] = NULL;
6745 }
6746 }
6747
6748pcidev_init_mem_err:
6749 ksz_free_mem(hw_priv);
6750 kfree(hw->ksz_switch);
6751
6752pcidev_init_alloc_err:
6753 iounmap(hw->io);
6754
6755pcidev_init_io_err:
6756 kfree(info);
6757
6758pcidev_init_dev_err:
6759 release_mem_region(reg_base, reg_len);
6760
6761 return result;
6762}
6763
6764static void pcidev_exit(struct pci_dev *pdev)
6765{
6766 int i;
6767 struct platform_info *info = pci_get_drvdata(pdev);
6768 struct dev_info *hw_priv = &info->dev_info;
6769
6770 release_mem_region(pci_resource_start(pdev, 0),
6771 pci_resource_len(pdev, 0));
6772 for (i = 0; i < hw_priv->hw.dev_count; i++) {
6773 if (info->netdev[i])
6774 netdev_free(info->netdev[i]);
6775 }
6776 if (hw_priv->hw.io)
6777 iounmap(hw_priv->hw.io);
6778 ksz_free_mem(hw_priv);
6779 kfree(hw_priv->hw.ksz_switch);
6780 pci_dev_put(hw_priv->pdev);
6781 kfree(info);
6782}
6783
6784static int __maybe_unused pcidev_resume(struct device *dev_d)
6785{
6786 int i;
6787 struct platform_info *info = dev_get_drvdata(dev_d);
6788 struct dev_info *hw_priv = &info->dev_info;
6789 struct ksz_hw *hw = &hw_priv->hw;
6790
6791 device_wakeup_disable(dev_d);
6792
6793 if (hw_priv->wol_enable)
6794 hw_cfg_wol_pme(hw, 0);
6795 for (i = 0; i < hw->dev_count; i++) {
6796 if (info->netdev[i]) {
6797 struct net_device *dev = info->netdev[i];
6798
6799 if (netif_running(dev)) {
6800 netdev_open(dev);
6801 netif_device_attach(dev);
6802 }
6803 }
6804 }
6805 return 0;
6806}
6807
6808static int __maybe_unused pcidev_suspend(struct device *dev_d)
6809{
6810 int i;
6811 struct platform_info *info = dev_get_drvdata(dev_d);
6812 struct dev_info *hw_priv = &info->dev_info;
6813 struct ksz_hw *hw = &hw_priv->hw;
6814
6815 /* Need to find a way to retrieve the device IP address. */
6816 static const u8 net_addr[] = { 192, 168, 1, 1 };
6817
6818 for (i = 0; i < hw->dev_count; i++) {
6819 if (info->netdev[i]) {
6820 struct net_device *dev = info->netdev[i];
6821
6822 if (netif_running(dev)) {
6823 netif_device_detach(dev);
6824 netdev_close(dev);
6825 }
6826 }
6827 }
6828 if (hw_priv->wol_enable) {
6829 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
6830 hw_cfg_wol_pme(hw, 1);
6831 }
6832
6833 device_wakeup_enable(dev_d);
6834 return 0;
6835}
6836
6837static char pcidev_name[] = "ksz884xp";
6838
6839static const struct pci_device_id pcidev_table[] = {
6840 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
6841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
6842 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
6843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
6844 { 0 }
6845};
6846
6847MODULE_DEVICE_TABLE(pci, pcidev_table);
6848
6849static SIMPLE_DEV_PM_OPS(pcidev_pm_ops, pcidev_suspend, pcidev_resume);
6850
6851static struct pci_driver pci_device_driver = {
6852 .driver.pm = &pcidev_pm_ops,
6853 .name = pcidev_name,
6854 .id_table = pcidev_table,
6855 .probe = pcidev_init,
6856 .remove = pcidev_exit
6857};
6858
6859module_pci_driver(pci_device_driver);
6860
6861MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
6862MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
6863MODULE_LICENSE("GPL");
6864
6865module_param_named(message, msg_enable, int, 0);
6866MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
6867
6868module_param(macaddr, charp, 0);
6869module_param(mac1addr, charp, 0);
6870module_param(fast_aging, int, 0);
6871module_param(multi_dev, int, 0);
6872module_param(stp, int, 0);
6873MODULE_PARM_DESC(macaddr, "MAC address");
6874MODULE_PARM_DESC(mac1addr, "Second MAC address");
6875MODULE_PARM_DESC(fast_aging, "Fast aging");
6876MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
6877MODULE_PARM_DESC(stp, "STP support");
1// SPDX-License-Identifier: GPL-2.0-only
2/**
3 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
4 *
5 * Copyright (c) 2009-2010 Micrel, Inc.
6 * Tristram Ha <Tristram.Ha@micrel.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18#include <linux/mii.h>
19#include <linux/platform_device.h>
20#include <linux/ethtool.h>
21#include <linux/etherdevice.h>
22#include <linux/in.h>
23#include <linux/ip.h>
24#include <linux/if_vlan.h>
25#include <linux/crc32.h>
26#include <linux/sched.h>
27#include <linux/slab.h>
28
29
30/* DMA Registers */
31
32#define KS_DMA_TX_CTRL 0x0000
33#define DMA_TX_ENABLE 0x00000001
34#define DMA_TX_CRC_ENABLE 0x00000002
35#define DMA_TX_PAD_ENABLE 0x00000004
36#define DMA_TX_LOOPBACK 0x00000100
37#define DMA_TX_FLOW_ENABLE 0x00000200
38#define DMA_TX_CSUM_IP 0x00010000
39#define DMA_TX_CSUM_TCP 0x00020000
40#define DMA_TX_CSUM_UDP 0x00040000
41#define DMA_TX_BURST_SIZE 0x3F000000
42
43#define KS_DMA_RX_CTRL 0x0004
44#define DMA_RX_ENABLE 0x00000001
45#define KS884X_DMA_RX_MULTICAST 0x00000002
46#define DMA_RX_PROMISCUOUS 0x00000004
47#define DMA_RX_ERROR 0x00000008
48#define DMA_RX_UNICAST 0x00000010
49#define DMA_RX_ALL_MULTICAST 0x00000020
50#define DMA_RX_BROADCAST 0x00000040
51#define DMA_RX_FLOW_ENABLE 0x00000200
52#define DMA_RX_CSUM_IP 0x00010000
53#define DMA_RX_CSUM_TCP 0x00020000
54#define DMA_RX_CSUM_UDP 0x00040000
55#define DMA_RX_BURST_SIZE 0x3F000000
56
57#define DMA_BURST_SHIFT 24
58#define DMA_BURST_DEFAULT 8
59
60#define KS_DMA_TX_START 0x0008
61#define KS_DMA_RX_START 0x000C
62#define DMA_START 0x00000001
63
64#define KS_DMA_TX_ADDR 0x0010
65#define KS_DMA_RX_ADDR 0x0014
66
67#define DMA_ADDR_LIST_MASK 0xFFFFFFFC
68#define DMA_ADDR_LIST_SHIFT 2
69
70/* MTR0 */
71#define KS884X_MULTICAST_0_OFFSET 0x0020
72#define KS884X_MULTICAST_1_OFFSET 0x0021
73#define KS884X_MULTICAST_2_OFFSET 0x0022
74#define KS884x_MULTICAST_3_OFFSET 0x0023
75/* MTR1 */
76#define KS884X_MULTICAST_4_OFFSET 0x0024
77#define KS884X_MULTICAST_5_OFFSET 0x0025
78#define KS884X_MULTICAST_6_OFFSET 0x0026
79#define KS884X_MULTICAST_7_OFFSET 0x0027
80
81/* Interrupt Registers */
82
83/* INTEN */
84#define KS884X_INTERRUPTS_ENABLE 0x0028
85/* INTST */
86#define KS884X_INTERRUPTS_STATUS 0x002C
87
88#define KS884X_INT_RX_STOPPED 0x02000000
89#define KS884X_INT_TX_STOPPED 0x04000000
90#define KS884X_INT_RX_OVERRUN 0x08000000
91#define KS884X_INT_TX_EMPTY 0x10000000
92#define KS884X_INT_RX 0x20000000
93#define KS884X_INT_TX 0x40000000
94#define KS884X_INT_PHY 0x80000000
95
96#define KS884X_INT_RX_MASK \
97 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
98#define KS884X_INT_TX_MASK \
99 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
100#define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
101
102/* MAC Additional Station Address */
103
104/* MAAL0 */
105#define KS_ADD_ADDR_0_LO 0x0080
106/* MAAH0 */
107#define KS_ADD_ADDR_0_HI 0x0084
108/* MAAL1 */
109#define KS_ADD_ADDR_1_LO 0x0088
110/* MAAH1 */
111#define KS_ADD_ADDR_1_HI 0x008C
112/* MAAL2 */
113#define KS_ADD_ADDR_2_LO 0x0090
114/* MAAH2 */
115#define KS_ADD_ADDR_2_HI 0x0094
116/* MAAL3 */
117#define KS_ADD_ADDR_3_LO 0x0098
118/* MAAH3 */
119#define KS_ADD_ADDR_3_HI 0x009C
120/* MAAL4 */
121#define KS_ADD_ADDR_4_LO 0x00A0
122/* MAAH4 */
123#define KS_ADD_ADDR_4_HI 0x00A4
124/* MAAL5 */
125#define KS_ADD_ADDR_5_LO 0x00A8
126/* MAAH5 */
127#define KS_ADD_ADDR_5_HI 0x00AC
128/* MAAL6 */
129#define KS_ADD_ADDR_6_LO 0x00B0
130/* MAAH6 */
131#define KS_ADD_ADDR_6_HI 0x00B4
132/* MAAL7 */
133#define KS_ADD_ADDR_7_LO 0x00B8
134/* MAAH7 */
135#define KS_ADD_ADDR_7_HI 0x00BC
136/* MAAL8 */
137#define KS_ADD_ADDR_8_LO 0x00C0
138/* MAAH8 */
139#define KS_ADD_ADDR_8_HI 0x00C4
140/* MAAL9 */
141#define KS_ADD_ADDR_9_LO 0x00C8
142/* MAAH9 */
143#define KS_ADD_ADDR_9_HI 0x00CC
144/* MAAL10 */
145#define KS_ADD_ADDR_A_LO 0x00D0
146/* MAAH10 */
147#define KS_ADD_ADDR_A_HI 0x00D4
148/* MAAL11 */
149#define KS_ADD_ADDR_B_LO 0x00D8
150/* MAAH11 */
151#define KS_ADD_ADDR_B_HI 0x00DC
152/* MAAL12 */
153#define KS_ADD_ADDR_C_LO 0x00E0
154/* MAAH12 */
155#define KS_ADD_ADDR_C_HI 0x00E4
156/* MAAL13 */
157#define KS_ADD_ADDR_D_LO 0x00E8
158/* MAAH13 */
159#define KS_ADD_ADDR_D_HI 0x00EC
160/* MAAL14 */
161#define KS_ADD_ADDR_E_LO 0x00F0
162/* MAAH14 */
163#define KS_ADD_ADDR_E_HI 0x00F4
164/* MAAL15 */
165#define KS_ADD_ADDR_F_LO 0x00F8
166/* MAAH15 */
167#define KS_ADD_ADDR_F_HI 0x00FC
168
169#define ADD_ADDR_HI_MASK 0x0000FFFF
170#define ADD_ADDR_ENABLE 0x80000000
171#define ADD_ADDR_INCR 8
172
173/* Miscellaneous Registers */
174
175/* MARL */
176#define KS884X_ADDR_0_OFFSET 0x0200
177#define KS884X_ADDR_1_OFFSET 0x0201
178/* MARM */
179#define KS884X_ADDR_2_OFFSET 0x0202
180#define KS884X_ADDR_3_OFFSET 0x0203
181/* MARH */
182#define KS884X_ADDR_4_OFFSET 0x0204
183#define KS884X_ADDR_5_OFFSET 0x0205
184
185/* OBCR */
186#define KS884X_BUS_CTRL_OFFSET 0x0210
187
188#define BUS_SPEED_125_MHZ 0x0000
189#define BUS_SPEED_62_5_MHZ 0x0001
190#define BUS_SPEED_41_66_MHZ 0x0002
191#define BUS_SPEED_25_MHZ 0x0003
192
193/* EEPCR */
194#define KS884X_EEPROM_CTRL_OFFSET 0x0212
195
196#define EEPROM_CHIP_SELECT 0x0001
197#define EEPROM_SERIAL_CLOCK 0x0002
198#define EEPROM_DATA_OUT 0x0004
199#define EEPROM_DATA_IN 0x0008
200#define EEPROM_ACCESS_ENABLE 0x0010
201
202/* MBIR */
203#define KS884X_MEM_INFO_OFFSET 0x0214
204
205#define RX_MEM_TEST_FAILED 0x0008
206#define RX_MEM_TEST_FINISHED 0x0010
207#define TX_MEM_TEST_FAILED 0x0800
208#define TX_MEM_TEST_FINISHED 0x1000
209
210/* GCR */
211#define KS884X_GLOBAL_CTRL_OFFSET 0x0216
212#define GLOBAL_SOFTWARE_RESET 0x0001
213
214#define KS8841_POWER_MANAGE_OFFSET 0x0218
215
216/* WFCR */
217#define KS8841_WOL_CTRL_OFFSET 0x021A
218#define KS8841_WOL_MAGIC_ENABLE 0x0080
219#define KS8841_WOL_FRAME3_ENABLE 0x0008
220#define KS8841_WOL_FRAME2_ENABLE 0x0004
221#define KS8841_WOL_FRAME1_ENABLE 0x0002
222#define KS8841_WOL_FRAME0_ENABLE 0x0001
223
224/* WF0 */
225#define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
226#define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
227#define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
228
229/* IACR */
230#define KS884X_IACR_P 0x04A0
231#define KS884X_IACR_OFFSET KS884X_IACR_P
232
233/* IADR1 */
234#define KS884X_IADR1_P 0x04A2
235#define KS884X_IADR2_P 0x04A4
236#define KS884X_IADR3_P 0x04A6
237#define KS884X_IADR4_P 0x04A8
238#define KS884X_IADR5_P 0x04AA
239
240#define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
241#define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
242
243#define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
244#define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
245#define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
246#define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
247#define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
248#define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
249#define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
250#define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
251#define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
252
253/* P1MBCR */
254#define KS884X_P1MBCR_P 0x04D0
255#define KS884X_P1MBSR_P 0x04D2
256#define KS884X_PHY1ILR_P 0x04D4
257#define KS884X_PHY1IHR_P 0x04D6
258#define KS884X_P1ANAR_P 0x04D8
259#define KS884X_P1ANLPR_P 0x04DA
260
261/* P2MBCR */
262#define KS884X_P2MBCR_P 0x04E0
263#define KS884X_P2MBSR_P 0x04E2
264#define KS884X_PHY2ILR_P 0x04E4
265#define KS884X_PHY2IHR_P 0x04E6
266#define KS884X_P2ANAR_P 0x04E8
267#define KS884X_P2ANLPR_P 0x04EA
268
269#define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
270#define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
271
272#define KS884X_PHY_CTRL_OFFSET 0x00
273
274/* Mode Control Register */
275#define PHY_REG_CTRL 0
276
277#define PHY_RESET 0x8000
278#define PHY_LOOPBACK 0x4000
279#define PHY_SPEED_100MBIT 0x2000
280#define PHY_AUTO_NEG_ENABLE 0x1000
281#define PHY_POWER_DOWN 0x0800
282#define PHY_MII_DISABLE 0x0400
283#define PHY_AUTO_NEG_RESTART 0x0200
284#define PHY_FULL_DUPLEX 0x0100
285#define PHY_COLLISION_TEST 0x0080
286#define PHY_HP_MDIX 0x0020
287#define PHY_FORCE_MDIX 0x0010
288#define PHY_AUTO_MDIX_DISABLE 0x0008
289#define PHY_REMOTE_FAULT_DISABLE 0x0004
290#define PHY_TRANSMIT_DISABLE 0x0002
291#define PHY_LED_DISABLE 0x0001
292
293#define KS884X_PHY_STATUS_OFFSET 0x02
294
295/* Mode Status Register */
296#define PHY_REG_STATUS 1
297
298#define PHY_100BT4_CAPABLE 0x8000
299#define PHY_100BTX_FD_CAPABLE 0x4000
300#define PHY_100BTX_CAPABLE 0x2000
301#define PHY_10BT_FD_CAPABLE 0x1000
302#define PHY_10BT_CAPABLE 0x0800
303#define PHY_MII_SUPPRESS_CAPABLE 0x0040
304#define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020
305#define PHY_REMOTE_FAULT 0x0010
306#define PHY_AUTO_NEG_CAPABLE 0x0008
307#define PHY_LINK_STATUS 0x0004
308#define PHY_JABBER_DETECT 0x0002
309#define PHY_EXTENDED_CAPABILITY 0x0001
310
311#define KS884X_PHY_ID_1_OFFSET 0x04
312#define KS884X_PHY_ID_2_OFFSET 0x06
313
314/* PHY Identifier Registers */
315#define PHY_REG_ID_1 2
316#define PHY_REG_ID_2 3
317
318#define KS884X_PHY_AUTO_NEG_OFFSET 0x08
319
320/* Auto-Negotiation Advertisement Register */
321#define PHY_REG_AUTO_NEGOTIATION 4
322
323#define PHY_AUTO_NEG_NEXT_PAGE 0x8000
324#define PHY_AUTO_NEG_REMOTE_FAULT 0x2000
325/* Not supported. */
326#define PHY_AUTO_NEG_ASYM_PAUSE 0x0800
327#define PHY_AUTO_NEG_SYM_PAUSE 0x0400
328#define PHY_AUTO_NEG_100BT4 0x0200
329#define PHY_AUTO_NEG_100BTX_FD 0x0100
330#define PHY_AUTO_NEG_100BTX 0x0080
331#define PHY_AUTO_NEG_10BT_FD 0x0040
332#define PHY_AUTO_NEG_10BT 0x0020
333#define PHY_AUTO_NEG_SELECTOR 0x001F
334#define PHY_AUTO_NEG_802_3 0x0001
335
336#define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
337
338#define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
339
340/* Auto-Negotiation Link Partner Ability Register */
341#define PHY_REG_REMOTE_CAPABILITY 5
342
343#define PHY_REMOTE_NEXT_PAGE 0x8000
344#define PHY_REMOTE_ACKNOWLEDGE 0x4000
345#define PHY_REMOTE_REMOTE_FAULT 0x2000
346#define PHY_REMOTE_SYM_PAUSE 0x0400
347#define PHY_REMOTE_100BTX_FD 0x0100
348#define PHY_REMOTE_100BTX 0x0080
349#define PHY_REMOTE_10BT_FD 0x0040
350#define PHY_REMOTE_10BT 0x0020
351
352/* P1VCT */
353#define KS884X_P1VCT_P 0x04F0
354#define KS884X_P1PHYCTRL_P 0x04F2
355
356/* P2VCT */
357#define KS884X_P2VCT_P 0x04F4
358#define KS884X_P2PHYCTRL_P 0x04F6
359
360#define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
361#define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
362
363#define KS884X_PHY_LINK_MD_OFFSET 0x00
364
365#define PHY_START_CABLE_DIAG 0x8000
366#define PHY_CABLE_DIAG_RESULT 0x6000
367#define PHY_CABLE_STAT_NORMAL 0x0000
368#define PHY_CABLE_STAT_OPEN 0x2000
369#define PHY_CABLE_STAT_SHORT 0x4000
370#define PHY_CABLE_STAT_FAILED 0x6000
371#define PHY_CABLE_10M_SHORT 0x1000
372#define PHY_CABLE_FAULT_COUNTER 0x01FF
373
374#define KS884X_PHY_PHY_CTRL_OFFSET 0x02
375
376#define PHY_STAT_REVERSED_POLARITY 0x0020
377#define PHY_STAT_MDIX 0x0010
378#define PHY_FORCE_LINK 0x0008
379#define PHY_POWER_SAVING_DISABLE 0x0004
380#define PHY_REMOTE_LOOPBACK 0x0002
381
382/* SIDER */
383#define KS884X_SIDER_P 0x0400
384#define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
385#define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
386
387#define REG_FAMILY_ID 0x88
388
389#define REG_CHIP_ID_41 0x8810
390#define REG_CHIP_ID_42 0x8800
391
392#define KS884X_CHIP_ID_MASK_41 0xFF10
393#define KS884X_CHIP_ID_MASK 0xFFF0
394#define KS884X_CHIP_ID_SHIFT 4
395#define KS884X_REVISION_MASK 0x000E
396#define KS884X_REVISION_SHIFT 1
397#define KS8842_START 0x0001
398
399#define CHIP_IP_41_M 0x8810
400#define CHIP_IP_42_M 0x8800
401#define CHIP_IP_61_M 0x8890
402#define CHIP_IP_62_M 0x8880
403
404#define CHIP_IP_41_P 0x8850
405#define CHIP_IP_42_P 0x8840
406#define CHIP_IP_61_P 0x88D0
407#define CHIP_IP_62_P 0x88C0
408
409/* SGCR1 */
410#define KS8842_SGCR1_P 0x0402
411#define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
412
413#define SWITCH_PASS_ALL 0x8000
414#define SWITCH_TX_FLOW_CTRL 0x2000
415#define SWITCH_RX_FLOW_CTRL 0x1000
416#define SWITCH_CHECK_LENGTH 0x0800
417#define SWITCH_AGING_ENABLE 0x0400
418#define SWITCH_FAST_AGING 0x0200
419#define SWITCH_AGGR_BACKOFF 0x0100
420#define SWITCH_PASS_PAUSE 0x0008
421#define SWITCH_LINK_AUTO_AGING 0x0001
422
423/* SGCR2 */
424#define KS8842_SGCR2_P 0x0404
425#define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
426
427#define SWITCH_VLAN_ENABLE 0x8000
428#define SWITCH_IGMP_SNOOP 0x4000
429#define IPV6_MLD_SNOOP_ENABLE 0x2000
430#define IPV6_MLD_SNOOP_OPTION 0x1000
431#define PRIORITY_SCHEME_SELECT 0x0800
432#define SWITCH_MIRROR_RX_TX 0x0100
433#define UNICAST_VLAN_BOUNDARY 0x0080
434#define MULTICAST_STORM_DISABLE 0x0040
435#define SWITCH_BACK_PRESSURE 0x0020
436#define FAIR_FLOW_CTRL 0x0010
437#define NO_EXC_COLLISION_DROP 0x0008
438#define SWITCH_HUGE_PACKET 0x0004
439#define SWITCH_LEGAL_PACKET 0x0002
440#define SWITCH_BUF_RESERVE 0x0001
441
442/* SGCR3 */
443#define KS8842_SGCR3_P 0x0406
444#define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
445
446#define BROADCAST_STORM_RATE_LO 0xFF00
447#define SWITCH_REPEATER 0x0080
448#define SWITCH_HALF_DUPLEX 0x0040
449#define SWITCH_FLOW_CTRL 0x0020
450#define SWITCH_10_MBIT 0x0010
451#define SWITCH_REPLACE_NULL_VID 0x0008
452#define BROADCAST_STORM_RATE_HI 0x0007
453
454#define BROADCAST_STORM_RATE 0x07FF
455
456/* SGCR4 */
457#define KS8842_SGCR4_P 0x0408
458
459/* SGCR5 */
460#define KS8842_SGCR5_P 0x040A
461#define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
462
463#define LED_MODE 0x8200
464#define LED_SPEED_DUPLEX_ACT 0x0000
465#define LED_SPEED_DUPLEX_LINK_ACT 0x8000
466#define LED_DUPLEX_10_100 0x0200
467
468/* SGCR6 */
469#define KS8842_SGCR6_P 0x0410
470#define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
471
472#define KS8842_PRIORITY_MASK 3
473#define KS8842_PRIORITY_SHIFT 2
474
475/* SGCR7 */
476#define KS8842_SGCR7_P 0x0412
477#define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
478
479#define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
480#define SWITCH_UNK_DEF_PORT_3 0x0004
481#define SWITCH_UNK_DEF_PORT_2 0x0002
482#define SWITCH_UNK_DEF_PORT_1 0x0001
483
484/* MACAR1 */
485#define KS8842_MACAR1_P 0x0470
486#define KS8842_MACAR2_P 0x0472
487#define KS8842_MACAR3_P 0x0474
488#define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
489#define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
490#define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
491#define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
492#define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
493#define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
494
495/* TOSR1 */
496#define KS8842_TOSR1_P 0x0480
497#define KS8842_TOSR2_P 0x0482
498#define KS8842_TOSR3_P 0x0484
499#define KS8842_TOSR4_P 0x0486
500#define KS8842_TOSR5_P 0x0488
501#define KS8842_TOSR6_P 0x048A
502#define KS8842_TOSR7_P 0x0490
503#define KS8842_TOSR8_P 0x0492
504#define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
505#define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
506#define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
507#define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
508#define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
509#define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
510
511#define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
512#define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
513
514/* P1CR1 */
515#define KS8842_P1CR1_P 0x0500
516#define KS8842_P1CR2_P 0x0502
517#define KS8842_P1VIDR_P 0x0504
518#define KS8842_P1CR3_P 0x0506
519#define KS8842_P1IRCR_P 0x0508
520#define KS8842_P1ERCR_P 0x050A
521#define KS884X_P1SCSLMD_P 0x0510
522#define KS884X_P1CR4_P 0x0512
523#define KS884X_P1SR_P 0x0514
524
525/* P2CR1 */
526#define KS8842_P2CR1_P 0x0520
527#define KS8842_P2CR2_P 0x0522
528#define KS8842_P2VIDR_P 0x0524
529#define KS8842_P2CR3_P 0x0526
530#define KS8842_P2IRCR_P 0x0528
531#define KS8842_P2ERCR_P 0x052A
532#define KS884X_P2SCSLMD_P 0x0530
533#define KS884X_P2CR4_P 0x0532
534#define KS884X_P2SR_P 0x0534
535
536/* P3CR1 */
537#define KS8842_P3CR1_P 0x0540
538#define KS8842_P3CR2_P 0x0542
539#define KS8842_P3VIDR_P 0x0544
540#define KS8842_P3CR3_P 0x0546
541#define KS8842_P3IRCR_P 0x0548
542#define KS8842_P3ERCR_P 0x054A
543
544#define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
545#define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
546#define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
547
548#define PORT_CTRL_ADDR(port, addr) \
549 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
550 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
551
552#define KS8842_PORT_CTRL_1_OFFSET 0x00
553
554#define PORT_BROADCAST_STORM 0x0080
555#define PORT_DIFFSERV_ENABLE 0x0040
556#define PORT_802_1P_ENABLE 0x0020
557#define PORT_BASED_PRIORITY_MASK 0x0018
558#define PORT_BASED_PRIORITY_BASE 0x0003
559#define PORT_BASED_PRIORITY_SHIFT 3
560#define PORT_BASED_PRIORITY_0 0x0000
561#define PORT_BASED_PRIORITY_1 0x0008
562#define PORT_BASED_PRIORITY_2 0x0010
563#define PORT_BASED_PRIORITY_3 0x0018
564#define PORT_INSERT_TAG 0x0004
565#define PORT_REMOVE_TAG 0x0002
566#define PORT_PRIO_QUEUE_ENABLE 0x0001
567
568#define KS8842_PORT_CTRL_2_OFFSET 0x02
569
570#define PORT_INGRESS_VLAN_FILTER 0x4000
571#define PORT_DISCARD_NON_VID 0x2000
572#define PORT_FORCE_FLOW_CTRL 0x1000
573#define PORT_BACK_PRESSURE 0x0800
574#define PORT_TX_ENABLE 0x0400
575#define PORT_RX_ENABLE 0x0200
576#define PORT_LEARN_DISABLE 0x0100
577#define PORT_MIRROR_SNIFFER 0x0080
578#define PORT_MIRROR_RX 0x0040
579#define PORT_MIRROR_TX 0x0020
580#define PORT_USER_PRIORITY_CEILING 0x0008
581#define PORT_VLAN_MEMBERSHIP 0x0007
582
583#define KS8842_PORT_CTRL_VID_OFFSET 0x04
584
585#define PORT_DEFAULT_VID 0x0001
586
587#define KS8842_PORT_CTRL_3_OFFSET 0x06
588
589#define PORT_INGRESS_LIMIT_MODE 0x000C
590#define PORT_INGRESS_ALL 0x0000
591#define PORT_INGRESS_UNICAST 0x0004
592#define PORT_INGRESS_MULTICAST 0x0008
593#define PORT_INGRESS_BROADCAST 0x000C
594#define PORT_COUNT_IFG 0x0002
595#define PORT_COUNT_PREAMBLE 0x0001
596
597#define KS8842_PORT_IN_RATE_OFFSET 0x08
598#define KS8842_PORT_OUT_RATE_OFFSET 0x0A
599
600#define PORT_PRIORITY_RATE 0x0F
601#define PORT_PRIORITY_RATE_SHIFT 4
602
603#define KS884X_PORT_LINK_MD 0x10
604
605#define PORT_CABLE_10M_SHORT 0x8000
606#define PORT_CABLE_DIAG_RESULT 0x6000
607#define PORT_CABLE_STAT_NORMAL 0x0000
608#define PORT_CABLE_STAT_OPEN 0x2000
609#define PORT_CABLE_STAT_SHORT 0x4000
610#define PORT_CABLE_STAT_FAILED 0x6000
611#define PORT_START_CABLE_DIAG 0x1000
612#define PORT_FORCE_LINK 0x0800
613#define PORT_POWER_SAVING_DISABLE 0x0400
614#define PORT_PHY_REMOTE_LOOPBACK 0x0200
615#define PORT_CABLE_FAULT_COUNTER 0x01FF
616
617#define KS884X_PORT_CTRL_4_OFFSET 0x12
618
619#define PORT_LED_OFF 0x8000
620#define PORT_TX_DISABLE 0x4000
621#define PORT_AUTO_NEG_RESTART 0x2000
622#define PORT_REMOTE_FAULT_DISABLE 0x1000
623#define PORT_POWER_DOWN 0x0800
624#define PORT_AUTO_MDIX_DISABLE 0x0400
625#define PORT_FORCE_MDIX 0x0200
626#define PORT_LOOPBACK 0x0100
627#define PORT_AUTO_NEG_ENABLE 0x0080
628#define PORT_FORCE_100_MBIT 0x0040
629#define PORT_FORCE_FULL_DUPLEX 0x0020
630#define PORT_AUTO_NEG_SYM_PAUSE 0x0010
631#define PORT_AUTO_NEG_100BTX_FD 0x0008
632#define PORT_AUTO_NEG_100BTX 0x0004
633#define PORT_AUTO_NEG_10BT_FD 0x0002
634#define PORT_AUTO_NEG_10BT 0x0001
635
636#define KS884X_PORT_STATUS_OFFSET 0x14
637
638#define PORT_HP_MDIX 0x8000
639#define PORT_REVERSED_POLARITY 0x2000
640#define PORT_RX_FLOW_CTRL 0x0800
641#define PORT_TX_FLOW_CTRL 0x1000
642#define PORT_STATUS_SPEED_100MBIT 0x0400
643#define PORT_STATUS_FULL_DUPLEX 0x0200
644#define PORT_REMOTE_FAULT 0x0100
645#define PORT_MDIX_STATUS 0x0080
646#define PORT_AUTO_NEG_COMPLETE 0x0040
647#define PORT_STATUS_LINK_GOOD 0x0020
648#define PORT_REMOTE_SYM_PAUSE 0x0010
649#define PORT_REMOTE_100BTX_FD 0x0008
650#define PORT_REMOTE_100BTX 0x0004
651#define PORT_REMOTE_10BT_FD 0x0002
652#define PORT_REMOTE_10BT 0x0001
653
654/*
655#define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
656#define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
657#define STATIC_MAC_TABLE_VALID 00-00080000-00000000
658#define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
659#define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
660#define STATIC_MAC_TABLE_FID 00-03C00000-00000000
661*/
662
663#define STATIC_MAC_TABLE_ADDR 0x0000FFFF
664#define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
665#define STATIC_MAC_TABLE_VALID 0x00080000
666#define STATIC_MAC_TABLE_OVERRIDE 0x00100000
667#define STATIC_MAC_TABLE_USE_FID 0x00200000
668#define STATIC_MAC_TABLE_FID 0x03C00000
669
670#define STATIC_MAC_FWD_PORTS_SHIFT 16
671#define STATIC_MAC_FID_SHIFT 22
672
673/*
674#define VLAN_TABLE_VID 00-00000000-00000FFF
675#define VLAN_TABLE_FID 00-00000000-0000F000
676#define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
677#define VLAN_TABLE_VALID 00-00000000-00080000
678*/
679
680#define VLAN_TABLE_VID 0x00000FFF
681#define VLAN_TABLE_FID 0x0000F000
682#define VLAN_TABLE_MEMBERSHIP 0x00070000
683#define VLAN_TABLE_VALID 0x00080000
684
685#define VLAN_TABLE_FID_SHIFT 12
686#define VLAN_TABLE_MEMBERSHIP_SHIFT 16
687
688/*
689#define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
690#define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
691#define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
692#define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
693#define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
694#define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
695#define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
696#define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
697*/
698
699#define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
700#define DYNAMIC_MAC_TABLE_FID 0x000F0000
701#define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
702#define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
703#define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
704
705#define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
706#define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
707#define DYNAMIC_MAC_TABLE_RESERVED 0x78
708#define DYNAMIC_MAC_TABLE_NOT_READY 0x80
709
710#define DYNAMIC_MAC_FID_SHIFT 16
711#define DYNAMIC_MAC_SRC_PORT_SHIFT 20
712#define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
713#define DYNAMIC_MAC_ENTRIES_SHIFT 24
714#define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
715
716/*
717#define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
718#define MIB_COUNTER_VALID 00-00000000-40000000
719#define MIB_COUNTER_OVERFLOW 00-00000000-80000000
720*/
721
722#define MIB_COUNTER_VALUE 0x3FFFFFFF
723#define MIB_COUNTER_VALID 0x40000000
724#define MIB_COUNTER_OVERFLOW 0x80000000
725
726#define MIB_PACKET_DROPPED 0x0000FFFF
727
728#define KS_MIB_PACKET_DROPPED_TX_0 0x100
729#define KS_MIB_PACKET_DROPPED_TX_1 0x101
730#define KS_MIB_PACKET_DROPPED_TX 0x102
731#define KS_MIB_PACKET_DROPPED_RX_0 0x103
732#define KS_MIB_PACKET_DROPPED_RX_1 0x104
733#define KS_MIB_PACKET_DROPPED_RX 0x105
734
735/* Change default LED mode. */
736#define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
737
738#define MAC_ADDR_ORDER(i) (ETH_ALEN - 1 - (i))
739
740#define MAX_ETHERNET_BODY_SIZE 1500
741#define ETHERNET_HEADER_SIZE (14 + VLAN_HLEN)
742
743#define MAX_ETHERNET_PACKET_SIZE \
744 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
745
746#define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
747#define MAX_RX_BUF_SIZE (1912 + 4)
748
749#define ADDITIONAL_ENTRIES 16
750#define MAX_MULTICAST_LIST 32
751
752#define HW_MULTICAST_SIZE 8
753
754#define HW_TO_DEV_PORT(port) (port - 1)
755
756enum {
757 media_connected,
758 media_disconnected
759};
760
761enum {
762 OID_COUNTER_UNKOWN,
763
764 OID_COUNTER_FIRST,
765
766 /* total transmit errors */
767 OID_COUNTER_XMIT_ERROR,
768
769 /* total receive errors */
770 OID_COUNTER_RCV_ERROR,
771
772 OID_COUNTER_LAST
773};
774
775/*
776 * Hardware descriptor definitions
777 */
778
779#define DESC_ALIGNMENT 16
780#define BUFFER_ALIGNMENT 8
781
782#define NUM_OF_RX_DESC 64
783#define NUM_OF_TX_DESC 64
784
785#define KS_DESC_RX_FRAME_LEN 0x000007FF
786#define KS_DESC_RX_FRAME_TYPE 0x00008000
787#define KS_DESC_RX_ERROR_CRC 0x00010000
788#define KS_DESC_RX_ERROR_RUNT 0x00020000
789#define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
790#define KS_DESC_RX_ERROR_PHY 0x00080000
791#define KS884X_DESC_RX_PORT_MASK 0x00300000
792#define KS_DESC_RX_MULTICAST 0x01000000
793#define KS_DESC_RX_ERROR 0x02000000
794#define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
795#define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
796#define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
797#define KS_DESC_RX_LAST 0x20000000
798#define KS_DESC_RX_FIRST 0x40000000
799#define KS_DESC_RX_ERROR_COND \
800 (KS_DESC_RX_ERROR_CRC | \
801 KS_DESC_RX_ERROR_RUNT | \
802 KS_DESC_RX_ERROR_PHY | \
803 KS_DESC_RX_ERROR_TOO_LONG)
804
805#define KS_DESC_HW_OWNED 0x80000000
806
807#define KS_DESC_BUF_SIZE 0x000007FF
808#define KS884X_DESC_TX_PORT_MASK 0x00300000
809#define KS_DESC_END_OF_RING 0x02000000
810#define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
811#define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
812#define KS_DESC_TX_CSUM_GEN_IP 0x10000000
813#define KS_DESC_TX_LAST 0x20000000
814#define KS_DESC_TX_FIRST 0x40000000
815#define KS_DESC_TX_INTERRUPT 0x80000000
816
817#define KS_DESC_PORT_SHIFT 20
818
819#define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
820
821#define KS_DESC_TX_MASK \
822 (KS_DESC_TX_INTERRUPT | \
823 KS_DESC_TX_FIRST | \
824 KS_DESC_TX_LAST | \
825 KS_DESC_TX_CSUM_GEN_IP | \
826 KS_DESC_TX_CSUM_GEN_TCP | \
827 KS_DESC_TX_CSUM_GEN_UDP | \
828 KS_DESC_BUF_SIZE)
829
830struct ksz_desc_rx_stat {
831#ifdef __BIG_ENDIAN_BITFIELD
832 u32 hw_owned:1;
833 u32 first_desc:1;
834 u32 last_desc:1;
835 u32 csum_err_ip:1;
836 u32 csum_err_tcp:1;
837 u32 csum_err_udp:1;
838 u32 error:1;
839 u32 multicast:1;
840 u32 src_port:4;
841 u32 err_phy:1;
842 u32 err_too_long:1;
843 u32 err_runt:1;
844 u32 err_crc:1;
845 u32 frame_type:1;
846 u32 reserved1:4;
847 u32 frame_len:11;
848#else
849 u32 frame_len:11;
850 u32 reserved1:4;
851 u32 frame_type:1;
852 u32 err_crc:1;
853 u32 err_runt:1;
854 u32 err_too_long:1;
855 u32 err_phy:1;
856 u32 src_port:4;
857 u32 multicast:1;
858 u32 error:1;
859 u32 csum_err_udp:1;
860 u32 csum_err_tcp:1;
861 u32 csum_err_ip:1;
862 u32 last_desc:1;
863 u32 first_desc:1;
864 u32 hw_owned:1;
865#endif
866};
867
868struct ksz_desc_tx_stat {
869#ifdef __BIG_ENDIAN_BITFIELD
870 u32 hw_owned:1;
871 u32 reserved1:31;
872#else
873 u32 reserved1:31;
874 u32 hw_owned:1;
875#endif
876};
877
878struct ksz_desc_rx_buf {
879#ifdef __BIG_ENDIAN_BITFIELD
880 u32 reserved4:6;
881 u32 end_of_ring:1;
882 u32 reserved3:14;
883 u32 buf_size:11;
884#else
885 u32 buf_size:11;
886 u32 reserved3:14;
887 u32 end_of_ring:1;
888 u32 reserved4:6;
889#endif
890};
891
892struct ksz_desc_tx_buf {
893#ifdef __BIG_ENDIAN_BITFIELD
894 u32 intr:1;
895 u32 first_seg:1;
896 u32 last_seg:1;
897 u32 csum_gen_ip:1;
898 u32 csum_gen_tcp:1;
899 u32 csum_gen_udp:1;
900 u32 end_of_ring:1;
901 u32 reserved4:1;
902 u32 dest_port:4;
903 u32 reserved3:9;
904 u32 buf_size:11;
905#else
906 u32 buf_size:11;
907 u32 reserved3:9;
908 u32 dest_port:4;
909 u32 reserved4:1;
910 u32 end_of_ring:1;
911 u32 csum_gen_udp:1;
912 u32 csum_gen_tcp:1;
913 u32 csum_gen_ip:1;
914 u32 last_seg:1;
915 u32 first_seg:1;
916 u32 intr:1;
917#endif
918};
919
920union desc_stat {
921 struct ksz_desc_rx_stat rx;
922 struct ksz_desc_tx_stat tx;
923 u32 data;
924};
925
926union desc_buf {
927 struct ksz_desc_rx_buf rx;
928 struct ksz_desc_tx_buf tx;
929 u32 data;
930};
931
932/**
933 * struct ksz_hw_desc - Hardware descriptor data structure
934 * @ctrl: Descriptor control value.
935 * @buf: Descriptor buffer value.
936 * @addr: Physical address of memory buffer.
937 * @next: Pointer to next hardware descriptor.
938 */
939struct ksz_hw_desc {
940 union desc_stat ctrl;
941 union desc_buf buf;
942 u32 addr;
943 u32 next;
944};
945
946/**
947 * struct ksz_sw_desc - Software descriptor data structure
948 * @ctrl: Descriptor control value.
949 * @buf: Descriptor buffer value.
950 * @buf_size: Current buffers size value in hardware descriptor.
951 */
952struct ksz_sw_desc {
953 union desc_stat ctrl;
954 union desc_buf buf;
955 u32 buf_size;
956};
957
958/**
959 * struct ksz_dma_buf - OS dependent DMA buffer data structure
960 * @skb: Associated socket buffer.
961 * @dma: Associated physical DMA address.
962 * len: Actual len used.
963 */
964struct ksz_dma_buf {
965 struct sk_buff *skb;
966 dma_addr_t dma;
967 int len;
968};
969
970/**
971 * struct ksz_desc - Descriptor structure
972 * @phw: Hardware descriptor pointer to uncached physical memory.
973 * @sw: Cached memory to hold hardware descriptor values for
974 * manipulation.
975 * @dma_buf: Operating system dependent data structure to hold physical
976 * memory buffer allocation information.
977 */
978struct ksz_desc {
979 struct ksz_hw_desc *phw;
980 struct ksz_sw_desc sw;
981 struct ksz_dma_buf dma_buf;
982};
983
984#define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
985
986/**
987 * struct ksz_desc_info - Descriptor information data structure
988 * @ring: First descriptor in the ring.
989 * @cur: Current descriptor being manipulated.
990 * @ring_virt: First hardware descriptor in the ring.
991 * @ring_phys: The physical address of the first descriptor of the ring.
992 * @size: Size of hardware descriptor.
993 * @alloc: Number of descriptors allocated.
994 * @avail: Number of descriptors available for use.
995 * @last: Index for last descriptor released to hardware.
996 * @next: Index for next descriptor available for use.
997 * @mask: Mask for index wrapping.
998 */
999struct ksz_desc_info {
1000 struct ksz_desc *ring;
1001 struct ksz_desc *cur;
1002 struct ksz_hw_desc *ring_virt;
1003 u32 ring_phys;
1004 int size;
1005 int alloc;
1006 int avail;
1007 int last;
1008 int next;
1009 int mask;
1010};
1011
1012/*
1013 * KSZ8842 switch definitions
1014 */
1015
1016enum {
1017 TABLE_STATIC_MAC = 0,
1018 TABLE_VLAN,
1019 TABLE_DYNAMIC_MAC,
1020 TABLE_MIB
1021};
1022
1023#define LEARNED_MAC_TABLE_ENTRIES 1024
1024#define STATIC_MAC_TABLE_ENTRIES 8
1025
1026/**
1027 * struct ksz_mac_table - Static MAC table data structure
1028 * @mac_addr: MAC address to filter.
1029 * @vid: VID value.
1030 * @fid: FID value.
1031 * @ports: Port membership.
1032 * @override: Override setting.
1033 * @use_fid: FID use setting.
1034 * @valid: Valid setting indicating the entry is being used.
1035 */
1036struct ksz_mac_table {
1037 u8 mac_addr[ETH_ALEN];
1038 u16 vid;
1039 u8 fid;
1040 u8 ports;
1041 u8 override:1;
1042 u8 use_fid:1;
1043 u8 valid:1;
1044};
1045
1046#define VLAN_TABLE_ENTRIES 16
1047
1048/**
1049 * struct ksz_vlan_table - VLAN table data structure
1050 * @vid: VID value.
1051 * @fid: FID value.
1052 * @member: Port membership.
1053 */
1054struct ksz_vlan_table {
1055 u16 vid;
1056 u8 fid;
1057 u8 member;
1058};
1059
1060#define DIFFSERV_ENTRIES 64
1061#define PRIO_802_1P_ENTRIES 8
1062#define PRIO_QUEUES 4
1063
1064#define SWITCH_PORT_NUM 2
1065#define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
1066#define HOST_MASK (1 << SWITCH_PORT_NUM)
1067#define PORT_MASK 7
1068
1069#define MAIN_PORT 0
1070#define OTHER_PORT 1
1071#define HOST_PORT SWITCH_PORT_NUM
1072
1073#define PORT_COUNTER_NUM 0x20
1074#define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1075
1076#define MIB_COUNTER_RX_LO_PRIORITY 0x00
1077#define MIB_COUNTER_RX_HI_PRIORITY 0x01
1078#define MIB_COUNTER_RX_UNDERSIZE 0x02
1079#define MIB_COUNTER_RX_FRAGMENT 0x03
1080#define MIB_COUNTER_RX_OVERSIZE 0x04
1081#define MIB_COUNTER_RX_JABBER 0x05
1082#define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1083#define MIB_COUNTER_RX_CRC_ERR 0x07
1084#define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1085#define MIB_COUNTER_RX_CTRL_8808 0x09
1086#define MIB_COUNTER_RX_PAUSE 0x0A
1087#define MIB_COUNTER_RX_BROADCAST 0x0B
1088#define MIB_COUNTER_RX_MULTICAST 0x0C
1089#define MIB_COUNTER_RX_UNICAST 0x0D
1090#define MIB_COUNTER_RX_OCTET_64 0x0E
1091#define MIB_COUNTER_RX_OCTET_65_127 0x0F
1092#define MIB_COUNTER_RX_OCTET_128_255 0x10
1093#define MIB_COUNTER_RX_OCTET_256_511 0x11
1094#define MIB_COUNTER_RX_OCTET_512_1023 0x12
1095#define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1096#define MIB_COUNTER_TX_LO_PRIORITY 0x14
1097#define MIB_COUNTER_TX_HI_PRIORITY 0x15
1098#define MIB_COUNTER_TX_LATE_COLLISION 0x16
1099#define MIB_COUNTER_TX_PAUSE 0x17
1100#define MIB_COUNTER_TX_BROADCAST 0x18
1101#define MIB_COUNTER_TX_MULTICAST 0x19
1102#define MIB_COUNTER_TX_UNICAST 0x1A
1103#define MIB_COUNTER_TX_DEFERRED 0x1B
1104#define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1105#define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1106#define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1107#define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1108
1109#define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1110#define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1111
1112/**
1113 * struct ksz_port_mib - Port MIB data structure
1114 * @cnt_ptr: Current pointer to MIB counter index.
1115 * @link_down: Indication the link has just gone down.
1116 * @state: Connection status of the port.
1117 * @mib_start: The starting counter index. Some ports do not start at 0.
1118 * @counter: 64-bit MIB counter value.
1119 * @dropped: Temporary buffer to remember last read packet dropped values.
1120 *
1121 * MIB counters needs to be read periodically so that counters do not get
1122 * overflowed and give incorrect values. A right balance is needed to
1123 * satisfy this condition and not waste too much CPU time.
1124 *
1125 * It is pointless to read MIB counters when the port is disconnected. The
1126 * @state provides the connection status so that MIB counters are read only
1127 * when the port is connected. The @link_down indicates the port is just
1128 * disconnected so that all MIB counters are read one last time to update the
1129 * information.
1130 */
1131struct ksz_port_mib {
1132 u8 cnt_ptr;
1133 u8 link_down;
1134 u8 state;
1135 u8 mib_start;
1136
1137 u64 counter[TOTAL_PORT_COUNTER_NUM];
1138 u32 dropped[2];
1139};
1140
1141/**
1142 * struct ksz_port_cfg - Port configuration data structure
1143 * @vid: VID value.
1144 * @member: Port membership.
1145 * @port_prio: Port priority.
1146 * @rx_rate: Receive priority rate.
1147 * @tx_rate: Transmit priority rate.
1148 * @stp_state: Current Spanning Tree Protocol state.
1149 */
1150struct ksz_port_cfg {
1151 u16 vid;
1152 u8 member;
1153 u8 port_prio;
1154 u32 rx_rate[PRIO_QUEUES];
1155 u32 tx_rate[PRIO_QUEUES];
1156 int stp_state;
1157};
1158
1159/**
1160 * struct ksz_switch - KSZ8842 switch data structure
1161 * @mac_table: MAC table entries information.
1162 * @vlan_table: VLAN table entries information.
1163 * @port_cfg: Port configuration information.
1164 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1165 * (bit7 ~ bit2) field.
1166 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1167 * Tag priority field.
1168 * @br_addr: Bridge address. Used for STP.
1169 * @other_addr: Other MAC address. Used for multiple network device mode.
1170 * @broad_per: Broadcast storm percentage.
1171 * @member: Current port membership. Used for STP.
1172 */
1173struct ksz_switch {
1174 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1175 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1176 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1177
1178 u8 diffserv[DIFFSERV_ENTRIES];
1179 u8 p_802_1p[PRIO_802_1P_ENTRIES];
1180
1181 u8 br_addr[ETH_ALEN];
1182 u8 other_addr[ETH_ALEN];
1183
1184 u8 broad_per;
1185 u8 member;
1186};
1187
1188#define TX_RATE_UNIT 10000
1189
1190/**
1191 * struct ksz_port_info - Port information data structure
1192 * @state: Connection status of the port.
1193 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1194 * @duplex: Duplex mode.
1195 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1196 * @partner: Auto-negotiation partner setting. Used to determine link.
1197 * @port_id: Port index to access actual hardware register.
1198 * @pdev: Pointer to OS dependent network device.
1199 */
1200struct ksz_port_info {
1201 uint state;
1202 uint tx_rate;
1203 u8 duplex;
1204 u8 advertised;
1205 u8 partner;
1206 u8 port_id;
1207 void *pdev;
1208};
1209
1210#define MAX_TX_HELD_SIZE 52000
1211
1212/* Hardware features and bug fixes. */
1213#define LINK_INT_WORKING (1 << 0)
1214#define SMALL_PACKET_TX_BUG (1 << 1)
1215#define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1216#define RX_HUGE_FRAME (1 << 4)
1217#define STP_SUPPORT (1 << 8)
1218
1219/* Software overrides. */
1220#define PAUSE_FLOW_CTRL (1 << 0)
1221#define FAST_AGING (1 << 1)
1222
1223/**
1224 * struct ksz_hw - KSZ884X hardware data structure
1225 * @io: Virtual address assigned.
1226 * @ksz_switch: Pointer to KSZ8842 switch.
1227 * @port_info: Port information.
1228 * @port_mib: Port MIB information.
1229 * @dev_count: Number of network devices this hardware supports.
1230 * @dst_ports: Destination ports in switch for transmission.
1231 * @id: Hardware ID. Used for display only.
1232 * @mib_cnt: Number of MIB counters this hardware has.
1233 * @mib_port_cnt: Number of ports with MIB counters.
1234 * @tx_cfg: Cached transmit control settings.
1235 * @rx_cfg: Cached receive control settings.
1236 * @intr_mask: Current interrupt mask.
1237 * @intr_set: Current interrup set.
1238 * @intr_blocked: Interrupt blocked.
1239 * @rx_desc_info: Receive descriptor information.
1240 * @tx_desc_info: Transmit descriptor information.
1241 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1242 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1243 * @tx_size: Transmit data size. Used for TX optimization.
1244 * The maximum is defined by MAX_TX_HELD_SIZE.
1245 * @perm_addr: Permanent MAC address.
1246 * @override_addr: Overridden MAC address.
1247 * @address: Additional MAC address entries.
1248 * @addr_list_size: Additional MAC address list size.
1249 * @mac_override: Indication of MAC address overridden.
1250 * @promiscuous: Counter to keep track of promiscuous mode set.
1251 * @all_multi: Counter to keep track of all multicast mode set.
1252 * @multi_list: Multicast address entries.
1253 * @multi_bits: Cached multicast hash table settings.
1254 * @multi_list_size: Multicast address list size.
1255 * @enabled: Indication of hardware enabled.
1256 * @rx_stop: Indication of receive process stop.
1257 * @features: Hardware features to enable.
1258 * @overrides: Hardware features to override.
1259 * @parent: Pointer to parent, network device private structure.
1260 */
1261struct ksz_hw {
1262 void __iomem *io;
1263
1264 struct ksz_switch *ksz_switch;
1265 struct ksz_port_info port_info[SWITCH_PORT_NUM];
1266 struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1267 int dev_count;
1268 int dst_ports;
1269 int id;
1270 int mib_cnt;
1271 int mib_port_cnt;
1272
1273 u32 tx_cfg;
1274 u32 rx_cfg;
1275 u32 intr_mask;
1276 u32 intr_set;
1277 uint intr_blocked;
1278
1279 struct ksz_desc_info rx_desc_info;
1280 struct ksz_desc_info tx_desc_info;
1281
1282 int tx_int_cnt;
1283 int tx_int_mask;
1284 int tx_size;
1285
1286 u8 perm_addr[ETH_ALEN];
1287 u8 override_addr[ETH_ALEN];
1288 u8 address[ADDITIONAL_ENTRIES][ETH_ALEN];
1289 u8 addr_list_size;
1290 u8 mac_override;
1291 u8 promiscuous;
1292 u8 all_multi;
1293 u8 multi_list[MAX_MULTICAST_LIST][ETH_ALEN];
1294 u8 multi_bits[HW_MULTICAST_SIZE];
1295 u8 multi_list_size;
1296
1297 u8 enabled;
1298 u8 rx_stop;
1299 u8 reserved2[1];
1300
1301 uint features;
1302 uint overrides;
1303
1304 void *parent;
1305};
1306
1307enum {
1308 PHY_NO_FLOW_CTRL,
1309 PHY_FLOW_CTRL,
1310 PHY_TX_ONLY,
1311 PHY_RX_ONLY
1312};
1313
1314/**
1315 * struct ksz_port - Virtual port data structure
1316 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1317 * duplex, and 0 for auto, which normally results in full
1318 * duplex.
1319 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1320 * 0 for auto, which normally results in 100 Mbit.
1321 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1322 * force.
1323 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1324 * control, and PHY_FLOW_CTRL for flow control.
1325 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1326 * Mbit PHY.
1327 * @first_port: Index of first port this port supports.
1328 * @mib_port_cnt: Number of ports with MIB counters.
1329 * @port_cnt: Number of ports this port supports.
1330 * @counter: Port statistics counter.
1331 * @hw: Pointer to hardware structure.
1332 * @linked: Pointer to port information linked to this port.
1333 */
1334struct ksz_port {
1335 u8 duplex;
1336 u8 speed;
1337 u8 force_link;
1338 u8 flow_ctrl;
1339
1340 int first_port;
1341 int mib_port_cnt;
1342 int port_cnt;
1343 u64 counter[OID_COUNTER_LAST];
1344
1345 struct ksz_hw *hw;
1346 struct ksz_port_info *linked;
1347};
1348
1349/**
1350 * struct ksz_timer_info - Timer information data structure
1351 * @timer: Kernel timer.
1352 * @cnt: Running timer counter.
1353 * @max: Number of times to run timer; -1 for infinity.
1354 * @period: Timer period in jiffies.
1355 */
1356struct ksz_timer_info {
1357 struct timer_list timer;
1358 int cnt;
1359 int max;
1360 int period;
1361};
1362
1363/**
1364 * struct ksz_shared_mem - OS dependent shared memory data structure
1365 * @dma_addr: Physical DMA address allocated.
1366 * @alloc_size: Allocation size.
1367 * @phys: Actual physical address used.
1368 * @alloc_virt: Virtual address allocated.
1369 * @virt: Actual virtual address used.
1370 */
1371struct ksz_shared_mem {
1372 dma_addr_t dma_addr;
1373 uint alloc_size;
1374 uint phys;
1375 u8 *alloc_virt;
1376 u8 *virt;
1377};
1378
1379/**
1380 * struct ksz_counter_info - OS dependent counter information data structure
1381 * @counter: Wait queue to wakeup after counters are read.
1382 * @time: Next time in jiffies to read counter.
1383 * @read: Indication of counters read in full or not.
1384 */
1385struct ksz_counter_info {
1386 wait_queue_head_t counter;
1387 unsigned long time;
1388 int read;
1389};
1390
1391/**
1392 * struct dev_info - Network device information data structure
1393 * @dev: Pointer to network device.
1394 * @pdev: Pointer to PCI device.
1395 * @hw: Hardware structure.
1396 * @desc_pool: Physical memory used for descriptor pool.
1397 * @hwlock: Spinlock to prevent hardware from accessing.
1398 * @lock: Mutex lock to prevent device from accessing.
1399 * @dev_rcv: Receive process function used.
1400 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1401 * @skb_index: Buffer index for receiving fragments.
1402 * @skb_len: Buffer length for receiving fragments.
1403 * @mib_read: Workqueue to read MIB counters.
1404 * @mib_timer_info: Timer to read MIB counters.
1405 * @counter: Used for MIB reading.
1406 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1407 * the maximum is MAX_RX_BUF_SIZE.
1408 * @opened: Counter to keep track of device open.
1409 * @rx_tasklet: Receive processing tasklet.
1410 * @tx_tasklet: Transmit processing tasklet.
1411 * @wol_enable: Wake-on-LAN enable set by ethtool.
1412 * @wol_support: Wake-on-LAN support used by ethtool.
1413 * @pme_wait: Used for KSZ8841 power management.
1414 */
1415struct dev_info {
1416 struct net_device *dev;
1417 struct pci_dev *pdev;
1418
1419 struct ksz_hw hw;
1420 struct ksz_shared_mem desc_pool;
1421
1422 spinlock_t hwlock;
1423 struct mutex lock;
1424
1425 int (*dev_rcv)(struct dev_info *);
1426
1427 struct sk_buff *last_skb;
1428 int skb_index;
1429 int skb_len;
1430
1431 struct work_struct mib_read;
1432 struct ksz_timer_info mib_timer_info;
1433 struct ksz_counter_info counter[TOTAL_PORT_NUM];
1434
1435 int mtu;
1436 int opened;
1437
1438 struct tasklet_struct rx_tasklet;
1439 struct tasklet_struct tx_tasklet;
1440
1441 int wol_enable;
1442 int wol_support;
1443 unsigned long pme_wait;
1444};
1445
1446/**
1447 * struct dev_priv - Network device private data structure
1448 * @adapter: Adapter device information.
1449 * @port: Port information.
1450 * @monitor_time_info: Timer to monitor ports.
1451 * @proc_sem: Semaphore for proc accessing.
1452 * @id: Device ID.
1453 * @mii_if: MII interface information.
1454 * @advertising: Temporary variable to store advertised settings.
1455 * @msg_enable: The message flags controlling driver output.
1456 * @media_state: The connection status of the device.
1457 * @multicast: The all multicast state of the device.
1458 * @promiscuous: The promiscuous state of the device.
1459 */
1460struct dev_priv {
1461 struct dev_info *adapter;
1462 struct ksz_port port;
1463 struct ksz_timer_info monitor_timer_info;
1464
1465 struct semaphore proc_sem;
1466 int id;
1467
1468 struct mii_if_info mii_if;
1469 u32 advertising;
1470
1471 u32 msg_enable;
1472 int media_state;
1473 int multicast;
1474 int promiscuous;
1475};
1476
1477#define DRV_NAME "KSZ884X PCI"
1478#define DEVICE_NAME "KSZ884x PCI"
1479#define DRV_VERSION "1.0.0"
1480#define DRV_RELDATE "Feb 8, 2010"
1481
1482static char version[] =
1483 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1484
1485static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1486
1487/*
1488 * Interrupt processing primary routines
1489 */
1490
1491static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1492{
1493 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1494}
1495
1496static inline void hw_dis_intr(struct ksz_hw *hw)
1497{
1498 hw->intr_blocked = hw->intr_mask;
1499 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1500 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1501}
1502
1503static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1504{
1505 hw->intr_set = interrupt;
1506 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1507}
1508
1509static inline void hw_ena_intr(struct ksz_hw *hw)
1510{
1511 hw->intr_blocked = 0;
1512 hw_set_intr(hw, hw->intr_mask);
1513}
1514
1515static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1516{
1517 hw->intr_mask &= ~(bit);
1518}
1519
1520static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1521{
1522 u32 read_intr;
1523
1524 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1525 hw->intr_set = read_intr & ~interrupt;
1526 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1527 hw_dis_intr_bit(hw, interrupt);
1528}
1529
1530/**
1531 * hw_turn_on_intr - turn on specified interrupts
1532 * @hw: The hardware instance.
1533 * @bit: The interrupt bits to be on.
1534 *
1535 * This routine turns on the specified interrupts in the interrupt mask so that
1536 * those interrupts will be enabled.
1537 */
1538static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1539{
1540 hw->intr_mask |= bit;
1541
1542 if (!hw->intr_blocked)
1543 hw_set_intr(hw, hw->intr_mask);
1544}
1545
1546static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1547{
1548 u32 read_intr;
1549
1550 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1551 hw->intr_set = read_intr | interrupt;
1552 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1553}
1554
1555static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1556{
1557 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1558 *status = *status & hw->intr_set;
1559}
1560
1561static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1562{
1563 if (interrupt)
1564 hw_ena_intr(hw);
1565}
1566
1567/**
1568 * hw_block_intr - block hardware interrupts
1569 *
1570 * This function blocks all interrupts of the hardware and returns the current
1571 * interrupt enable mask so that interrupts can be restored later.
1572 *
1573 * Return the current interrupt enable mask.
1574 */
1575static uint hw_block_intr(struct ksz_hw *hw)
1576{
1577 uint interrupt = 0;
1578
1579 if (!hw->intr_blocked) {
1580 hw_dis_intr(hw);
1581 interrupt = hw->intr_blocked;
1582 }
1583 return interrupt;
1584}
1585
1586/*
1587 * Hardware descriptor routines
1588 */
1589
1590static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1591{
1592 status.rx.hw_owned = 0;
1593 desc->phw->ctrl.data = cpu_to_le32(status.data);
1594}
1595
1596static inline void release_desc(struct ksz_desc *desc)
1597{
1598 desc->sw.ctrl.tx.hw_owned = 1;
1599 if (desc->sw.buf_size != desc->sw.buf.data) {
1600 desc->sw.buf_size = desc->sw.buf.data;
1601 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1602 }
1603 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1604}
1605
1606static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1607{
1608 *desc = &info->ring[info->last];
1609 info->last++;
1610 info->last &= info->mask;
1611 info->avail--;
1612 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1613}
1614
1615static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1616{
1617 desc->phw->addr = cpu_to_le32(addr);
1618}
1619
1620static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1621{
1622 desc->sw.buf.rx.buf_size = len;
1623}
1624
1625static inline void get_tx_pkt(struct ksz_desc_info *info,
1626 struct ksz_desc **desc)
1627{
1628 *desc = &info->ring[info->next];
1629 info->next++;
1630 info->next &= info->mask;
1631 info->avail--;
1632 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1633}
1634
1635static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1636{
1637 desc->phw->addr = cpu_to_le32(addr);
1638}
1639
1640static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1641{
1642 desc->sw.buf.tx.buf_size = len;
1643}
1644
1645/* Switch functions */
1646
1647#define TABLE_READ 0x10
1648#define TABLE_SEL_SHIFT 2
1649
1650#define HW_DELAY(hw, reg) \
1651 do { \
1652 u16 dummy; \
1653 dummy = readw(hw->io + reg); \
1654 } while (0)
1655
1656/**
1657 * sw_r_table - read 4 bytes of data from switch table
1658 * @hw: The hardware instance.
1659 * @table: The table selector.
1660 * @addr: The address of the table entry.
1661 * @data: Buffer to store the read data.
1662 *
1663 * This routine reads 4 bytes of data from the table of the switch.
1664 * Hardware interrupts are disabled to minimize corruption of read data.
1665 */
1666static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1667{
1668 u16 ctrl_addr;
1669 uint interrupt;
1670
1671 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1672
1673 interrupt = hw_block_intr(hw);
1674
1675 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1676 HW_DELAY(hw, KS884X_IACR_OFFSET);
1677 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1678
1679 hw_restore_intr(hw, interrupt);
1680}
1681
1682/**
1683 * sw_w_table_64 - write 8 bytes of data to the switch table
1684 * @hw: The hardware instance.
1685 * @table: The table selector.
1686 * @addr: The address of the table entry.
1687 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1688 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1689 *
1690 * This routine writes 8 bytes of data to the table of the switch.
1691 * Hardware interrupts are disabled to minimize corruption of written data.
1692 */
1693static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1694 u32 data_lo)
1695{
1696 u16 ctrl_addr;
1697 uint interrupt;
1698
1699 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1700
1701 interrupt = hw_block_intr(hw);
1702
1703 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1704 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1705
1706 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1707 HW_DELAY(hw, KS884X_IACR_OFFSET);
1708
1709 hw_restore_intr(hw, interrupt);
1710}
1711
1712/**
1713 * sw_w_sta_mac_table - write to the static MAC table
1714 * @hw: The hardware instance.
1715 * @addr: The address of the table entry.
1716 * @mac_addr: The MAC address.
1717 * @ports: The port members.
1718 * @override: The flag to override the port receive/transmit settings.
1719 * @valid: The flag to indicate entry is valid.
1720 * @use_fid: The flag to indicate the FID is valid.
1721 * @fid: The FID value.
1722 *
1723 * This routine writes an entry of the static MAC table of the switch. It
1724 * calls sw_w_table_64() to write the data.
1725 */
1726static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1727 u8 ports, int override, int valid, int use_fid, u8 fid)
1728{
1729 u32 data_hi;
1730 u32 data_lo;
1731
1732 data_lo = ((u32) mac_addr[2] << 24) |
1733 ((u32) mac_addr[3] << 16) |
1734 ((u32) mac_addr[4] << 8) | mac_addr[5];
1735 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1736 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1737
1738 if (override)
1739 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1740 if (use_fid) {
1741 data_hi |= STATIC_MAC_TABLE_USE_FID;
1742 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1743 }
1744 if (valid)
1745 data_hi |= STATIC_MAC_TABLE_VALID;
1746
1747 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1748}
1749
1750/**
1751 * sw_r_vlan_table - read from the VLAN table
1752 * @hw: The hardware instance.
1753 * @addr: The address of the table entry.
1754 * @vid: Buffer to store the VID.
1755 * @fid: Buffer to store the VID.
1756 * @member: Buffer to store the port membership.
1757 *
1758 * This function reads an entry of the VLAN table of the switch. It calls
1759 * sw_r_table() to get the data.
1760 *
1761 * Return 0 if the entry is valid; otherwise -1.
1762 */
1763static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1764 u8 *member)
1765{
1766 u32 data;
1767
1768 sw_r_table(hw, TABLE_VLAN, addr, &data);
1769 if (data & VLAN_TABLE_VALID) {
1770 *vid = (u16)(data & VLAN_TABLE_VID);
1771 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1772 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1773 VLAN_TABLE_MEMBERSHIP_SHIFT);
1774 return 0;
1775 }
1776 return -1;
1777}
1778
1779/**
1780 * port_r_mib_cnt - read MIB counter
1781 * @hw: The hardware instance.
1782 * @port: The port index.
1783 * @addr: The address of the counter.
1784 * @cnt: Buffer to store the counter.
1785 *
1786 * This routine reads a MIB counter of the port.
1787 * Hardware interrupts are disabled to minimize corruption of read data.
1788 */
1789static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1790{
1791 u32 data;
1792 u16 ctrl_addr;
1793 uint interrupt;
1794 int timeout;
1795
1796 ctrl_addr = addr + PORT_COUNTER_NUM * port;
1797
1798 interrupt = hw_block_intr(hw);
1799
1800 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1801 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1802 HW_DELAY(hw, KS884X_IACR_OFFSET);
1803
1804 for (timeout = 100; timeout > 0; timeout--) {
1805 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1806
1807 if (data & MIB_COUNTER_VALID) {
1808 if (data & MIB_COUNTER_OVERFLOW)
1809 *cnt += MIB_COUNTER_VALUE + 1;
1810 *cnt += data & MIB_COUNTER_VALUE;
1811 break;
1812 }
1813 }
1814
1815 hw_restore_intr(hw, interrupt);
1816}
1817
1818/**
1819 * port_r_mib_pkt - read dropped packet counts
1820 * @hw: The hardware instance.
1821 * @port: The port index.
1822 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1823 *
1824 * This routine reads the dropped packet counts of the port.
1825 * Hardware interrupts are disabled to minimize corruption of read data.
1826 */
1827static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1828{
1829 u32 cur;
1830 u32 data;
1831 u16 ctrl_addr;
1832 uint interrupt;
1833 int index;
1834
1835 index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1836 do {
1837 interrupt = hw_block_intr(hw);
1838
1839 ctrl_addr = (u16) index;
1840 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1841 << 8);
1842 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1843 HW_DELAY(hw, KS884X_IACR_OFFSET);
1844 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1845
1846 hw_restore_intr(hw, interrupt);
1847
1848 data &= MIB_PACKET_DROPPED;
1849 cur = *last;
1850 if (data != cur) {
1851 *last = data;
1852 if (data < cur)
1853 data += MIB_PACKET_DROPPED + 1;
1854 data -= cur;
1855 *cnt += data;
1856 }
1857 ++last;
1858 ++cnt;
1859 index -= KS_MIB_PACKET_DROPPED_TX -
1860 KS_MIB_PACKET_DROPPED_TX_0 + 1;
1861 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1862}
1863
1864/**
1865 * port_r_cnt - read MIB counters periodically
1866 * @hw: The hardware instance.
1867 * @port: The port index.
1868 *
1869 * This routine is used to read the counters of the port periodically to avoid
1870 * counter overflow. The hardware should be acquired first before calling this
1871 * routine.
1872 *
1873 * Return non-zero when not all counters not read.
1874 */
1875static int port_r_cnt(struct ksz_hw *hw, int port)
1876{
1877 struct ksz_port_mib *mib = &hw->port_mib[port];
1878
1879 if (mib->mib_start < PORT_COUNTER_NUM)
1880 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1881 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1882 &mib->counter[mib->cnt_ptr]);
1883 ++mib->cnt_ptr;
1884 }
1885 if (hw->mib_cnt > PORT_COUNTER_NUM)
1886 port_r_mib_pkt(hw, port, mib->dropped,
1887 &mib->counter[PORT_COUNTER_NUM]);
1888 mib->cnt_ptr = 0;
1889 return 0;
1890}
1891
1892/**
1893 * port_init_cnt - initialize MIB counter values
1894 * @hw: The hardware instance.
1895 * @port: The port index.
1896 *
1897 * This routine is used to initialize all counters to zero if the hardware
1898 * cannot do it after reset.
1899 */
1900static void port_init_cnt(struct ksz_hw *hw, int port)
1901{
1902 struct ksz_port_mib *mib = &hw->port_mib[port];
1903
1904 mib->cnt_ptr = 0;
1905 if (mib->mib_start < PORT_COUNTER_NUM)
1906 do {
1907 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1908 &mib->counter[mib->cnt_ptr]);
1909 ++mib->cnt_ptr;
1910 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1911 if (hw->mib_cnt > PORT_COUNTER_NUM)
1912 port_r_mib_pkt(hw, port, mib->dropped,
1913 &mib->counter[PORT_COUNTER_NUM]);
1914 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1915 mib->cnt_ptr = 0;
1916}
1917
1918/*
1919 * Port functions
1920 */
1921
1922/**
1923 * port_chk - check port register bits
1924 * @hw: The hardware instance.
1925 * @port: The port index.
1926 * @offset: The offset of the port register.
1927 * @bits: The data bits to check.
1928 *
1929 * This function checks whether the specified bits of the port register are set
1930 * or not.
1931 *
1932 * Return 0 if the bits are not set.
1933 */
1934static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits)
1935{
1936 u32 addr;
1937 u16 data;
1938
1939 PORT_CTRL_ADDR(port, addr);
1940 addr += offset;
1941 data = readw(hw->io + addr);
1942 return (data & bits) == bits;
1943}
1944
1945/**
1946 * port_cfg - set port register bits
1947 * @hw: The hardware instance.
1948 * @port: The port index.
1949 * @offset: The offset of the port register.
1950 * @bits: The data bits to set.
1951 * @set: The flag indicating whether the bits are to be set or not.
1952 *
1953 * This routine sets or resets the specified bits of the port register.
1954 */
1955static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1956 int set)
1957{
1958 u32 addr;
1959 u16 data;
1960
1961 PORT_CTRL_ADDR(port, addr);
1962 addr += offset;
1963 data = readw(hw->io + addr);
1964 if (set)
1965 data |= bits;
1966 else
1967 data &= ~bits;
1968 writew(data, hw->io + addr);
1969}
1970
1971/**
1972 * port_chk_shift - check port bit
1973 * @hw: The hardware instance.
1974 * @port: The port index.
1975 * @offset: The offset of the register.
1976 * @shift: Number of bits to shift.
1977 *
1978 * This function checks whether the specified port is set in the register or
1979 * not.
1980 *
1981 * Return 0 if the port is not set.
1982 */
1983static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift)
1984{
1985 u16 data;
1986 u16 bit = 1 << port;
1987
1988 data = readw(hw->io + addr);
1989 data >>= shift;
1990 return (data & bit) == bit;
1991}
1992
1993/**
1994 * port_cfg_shift - set port bit
1995 * @hw: The hardware instance.
1996 * @port: The port index.
1997 * @offset: The offset of the register.
1998 * @shift: Number of bits to shift.
1999 * @set: The flag indicating whether the port is to be set or not.
2000 *
2001 * This routine sets or resets the specified port in the register.
2002 */
2003static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift,
2004 int set)
2005{
2006 u16 data;
2007 u16 bits = 1 << port;
2008
2009 data = readw(hw->io + addr);
2010 bits <<= shift;
2011 if (set)
2012 data |= bits;
2013 else
2014 data &= ~bits;
2015 writew(data, hw->io + addr);
2016}
2017
2018/**
2019 * port_r8 - read byte from port register
2020 * @hw: The hardware instance.
2021 * @port: The port index.
2022 * @offset: The offset of the port register.
2023 * @data: Buffer to store the data.
2024 *
2025 * This routine reads a byte from the port register.
2026 */
2027static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
2028{
2029 u32 addr;
2030
2031 PORT_CTRL_ADDR(port, addr);
2032 addr += offset;
2033 *data = readb(hw->io + addr);
2034}
2035
2036/**
2037 * port_r16 - read word from port register.
2038 * @hw: The hardware instance.
2039 * @port: The port index.
2040 * @offset: The offset of the port register.
2041 * @data: Buffer to store the data.
2042 *
2043 * This routine reads a word from the port register.
2044 */
2045static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
2046{
2047 u32 addr;
2048
2049 PORT_CTRL_ADDR(port, addr);
2050 addr += offset;
2051 *data = readw(hw->io + addr);
2052}
2053
2054/**
2055 * port_w16 - write word to port register.
2056 * @hw: The hardware instance.
2057 * @port: The port index.
2058 * @offset: The offset of the port register.
2059 * @data: Data to write.
2060 *
2061 * This routine writes a word to the port register.
2062 */
2063static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2064{
2065 u32 addr;
2066
2067 PORT_CTRL_ADDR(port, addr);
2068 addr += offset;
2069 writew(data, hw->io + addr);
2070}
2071
2072/**
2073 * sw_chk - check switch register bits
2074 * @hw: The hardware instance.
2075 * @addr: The address of the switch register.
2076 * @bits: The data bits to check.
2077 *
2078 * This function checks whether the specified bits of the switch register are
2079 * set or not.
2080 *
2081 * Return 0 if the bits are not set.
2082 */
2083static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
2084{
2085 u16 data;
2086
2087 data = readw(hw->io + addr);
2088 return (data & bits) == bits;
2089}
2090
2091/**
2092 * sw_cfg - set switch register bits
2093 * @hw: The hardware instance.
2094 * @addr: The address of the switch register.
2095 * @bits: The data bits to set.
2096 * @set: The flag indicating whether the bits are to be set or not.
2097 *
2098 * This function sets or resets the specified bits of the switch register.
2099 */
2100static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
2101{
2102 u16 data;
2103
2104 data = readw(hw->io + addr);
2105 if (set)
2106 data |= bits;
2107 else
2108 data &= ~bits;
2109 writew(data, hw->io + addr);
2110}
2111
2112/* Bandwidth */
2113
2114static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
2115{
2116 port_cfg(hw, p,
2117 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
2118}
2119
2120static inline int port_chk_broad_storm(struct ksz_hw *hw, int p)
2121{
2122 return port_chk(hw, p,
2123 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM);
2124}
2125
2126/* Driver set switch broadcast storm protection at 10% rate. */
2127#define BROADCAST_STORM_PROTECTION_RATE 10
2128
2129/* 148,800 frames * 67 ms / 100 */
2130#define BROADCAST_STORM_VALUE 9969
2131
2132/**
2133 * sw_cfg_broad_storm - configure broadcast storm threshold
2134 * @hw: The hardware instance.
2135 * @percent: Broadcast storm threshold in percent of transmit rate.
2136 *
2137 * This routine configures the broadcast storm threshold of the switch.
2138 */
2139static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2140{
2141 u16 data;
2142 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
2143
2144 if (value > BROADCAST_STORM_RATE)
2145 value = BROADCAST_STORM_RATE;
2146
2147 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2148 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
2149 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
2150 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2151}
2152
2153/**
2154 * sw_get_board_storm - get broadcast storm threshold
2155 * @hw: The hardware instance.
2156 * @percent: Buffer to store the broadcast storm threshold percentage.
2157 *
2158 * This routine retrieves the broadcast storm threshold of the switch.
2159 */
2160static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2161{
2162 int num;
2163 u16 data;
2164
2165 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2166 num = (data & BROADCAST_STORM_RATE_HI);
2167 num <<= 8;
2168 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2169 num = DIV_ROUND_CLOSEST(num * 100, BROADCAST_STORM_VALUE);
2170 *percent = (u8) num;
2171}
2172
2173/**
2174 * sw_dis_broad_storm - disable broadstorm
2175 * @hw: The hardware instance.
2176 * @port: The port index.
2177 *
2178 * This routine disables the broadcast storm limit function of the switch.
2179 */
2180static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2181{
2182 port_cfg_broad_storm(hw, port, 0);
2183}
2184
2185/**
2186 * sw_ena_broad_storm - enable broadcast storm
2187 * @hw: The hardware instance.
2188 * @port: The port index.
2189 *
2190 * This routine enables the broadcast storm limit function of the switch.
2191 */
2192static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2193{
2194 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2195 port_cfg_broad_storm(hw, port, 1);
2196}
2197
2198/**
2199 * sw_init_broad_storm - initialize broadcast storm
2200 * @hw: The hardware instance.
2201 *
2202 * This routine initializes the broadcast storm limit function of the switch.
2203 */
2204static void sw_init_broad_storm(struct ksz_hw *hw)
2205{
2206 int port;
2207
2208 hw->ksz_switch->broad_per = 1;
2209 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2210 for (port = 0; port < TOTAL_PORT_NUM; port++)
2211 sw_dis_broad_storm(hw, port);
2212 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2213}
2214
2215/**
2216 * hw_cfg_broad_storm - configure broadcast storm
2217 * @hw: The hardware instance.
2218 * @percent: Broadcast storm threshold in percent of transmit rate.
2219 *
2220 * This routine configures the broadcast storm threshold of the switch.
2221 * It is called by user functions. The hardware should be acquired first.
2222 */
2223static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2224{
2225 if (percent > 100)
2226 percent = 100;
2227
2228 sw_cfg_broad_storm(hw, percent);
2229 sw_get_broad_storm(hw, &percent);
2230 hw->ksz_switch->broad_per = percent;
2231}
2232
2233/**
2234 * sw_dis_prio_rate - disable switch priority rate
2235 * @hw: The hardware instance.
2236 * @port: The port index.
2237 *
2238 * This routine disables the priority rate function of the switch.
2239 */
2240static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2241{
2242 u32 addr;
2243
2244 PORT_CTRL_ADDR(port, addr);
2245 addr += KS8842_PORT_IN_RATE_OFFSET;
2246 writel(0, hw->io + addr);
2247}
2248
2249/**
2250 * sw_init_prio_rate - initialize switch prioirty rate
2251 * @hw: The hardware instance.
2252 *
2253 * This routine initializes the priority rate function of the switch.
2254 */
2255static void sw_init_prio_rate(struct ksz_hw *hw)
2256{
2257 int port;
2258 int prio;
2259 struct ksz_switch *sw = hw->ksz_switch;
2260
2261 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2262 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2263 sw->port_cfg[port].rx_rate[prio] =
2264 sw->port_cfg[port].tx_rate[prio] = 0;
2265 }
2266 sw_dis_prio_rate(hw, port);
2267 }
2268}
2269
2270/* Communication */
2271
2272static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2273{
2274 port_cfg(hw, p,
2275 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2276}
2277
2278static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set)
2279{
2280 port_cfg(hw, p,
2281 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set);
2282}
2283
2284static inline int port_chk_back_pressure(struct ksz_hw *hw, int p)
2285{
2286 return port_chk(hw, p,
2287 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE);
2288}
2289
2290static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p)
2291{
2292 return port_chk(hw, p,
2293 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL);
2294}
2295
2296/* Spanning Tree */
2297
2298static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set)
2299{
2300 port_cfg(hw, p,
2301 KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set);
2302}
2303
2304static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set)
2305{
2306 port_cfg(hw, p,
2307 KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set);
2308}
2309
2310static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set)
2311{
2312 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set);
2313}
2314
2315static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw)
2316{
2317 if (!(hw->overrides & FAST_AGING)) {
2318 sw_cfg_fast_aging(hw, 1);
2319 mdelay(1);
2320 sw_cfg_fast_aging(hw, 0);
2321 }
2322}
2323
2324/* VLAN */
2325
2326static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert)
2327{
2328 port_cfg(hw, p,
2329 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert);
2330}
2331
2332static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove)
2333{
2334 port_cfg(hw, p,
2335 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove);
2336}
2337
2338static inline int port_chk_ins_tag(struct ksz_hw *hw, int p)
2339{
2340 return port_chk(hw, p,
2341 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG);
2342}
2343
2344static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p)
2345{
2346 return port_chk(hw, p,
2347 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG);
2348}
2349
2350static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set)
2351{
2352 port_cfg(hw, p,
2353 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set);
2354}
2355
2356static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set)
2357{
2358 port_cfg(hw, p,
2359 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set);
2360}
2361
2362static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p)
2363{
2364 return port_chk(hw, p,
2365 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID);
2366}
2367
2368static inline int port_chk_in_filter(struct ksz_hw *hw, int p)
2369{
2370 return port_chk(hw, p,
2371 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER);
2372}
2373
2374/* Mirroring */
2375
2376static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2377{
2378 port_cfg(hw, p,
2379 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2380}
2381
2382static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2383{
2384 port_cfg(hw, p,
2385 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2386}
2387
2388static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2389{
2390 port_cfg(hw, p,
2391 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2392}
2393
2394static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2395{
2396 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2397}
2398
2399static void sw_init_mirror(struct ksz_hw *hw)
2400{
2401 int port;
2402
2403 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2404 port_cfg_mirror_sniffer(hw, port, 0);
2405 port_cfg_mirror_rx(hw, port, 0);
2406 port_cfg_mirror_tx(hw, port, 0);
2407 }
2408 sw_cfg_mirror_rx_tx(hw, 0);
2409}
2410
2411static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set)
2412{
2413 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2414 SWITCH_UNK_DEF_PORT_ENABLE, set);
2415}
2416
2417static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw)
2418{
2419 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2420 SWITCH_UNK_DEF_PORT_ENABLE);
2421}
2422
2423static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set)
2424{
2425 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set);
2426}
2427
2428static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port)
2429{
2430 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0);
2431}
2432
2433/* Priority */
2434
2435static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2436{
2437 port_cfg(hw, p,
2438 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2439}
2440
2441static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2442{
2443 port_cfg(hw, p,
2444 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2445}
2446
2447static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2448{
2449 port_cfg(hw, p,
2450 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2451}
2452
2453static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2454{
2455 port_cfg(hw, p,
2456 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2457}
2458
2459static inline int port_chk_diffserv(struct ksz_hw *hw, int p)
2460{
2461 return port_chk(hw, p,
2462 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE);
2463}
2464
2465static inline int port_chk_802_1p(struct ksz_hw *hw, int p)
2466{
2467 return port_chk(hw, p,
2468 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE);
2469}
2470
2471static inline int port_chk_replace_vid(struct ksz_hw *hw, int p)
2472{
2473 return port_chk(hw, p,
2474 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING);
2475}
2476
2477static inline int port_chk_prio(struct ksz_hw *hw, int p)
2478{
2479 return port_chk(hw, p,
2480 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE);
2481}
2482
2483/**
2484 * sw_dis_diffserv - disable switch DiffServ priority
2485 * @hw: The hardware instance.
2486 * @port: The port index.
2487 *
2488 * This routine disables the DiffServ priority function of the switch.
2489 */
2490static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2491{
2492 port_cfg_diffserv(hw, port, 0);
2493}
2494
2495/**
2496 * sw_dis_802_1p - disable switch 802.1p priority
2497 * @hw: The hardware instance.
2498 * @port: The port index.
2499 *
2500 * This routine disables the 802.1p priority function of the switch.
2501 */
2502static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2503{
2504 port_cfg_802_1p(hw, port, 0);
2505}
2506
2507/**
2508 * sw_cfg_replace_null_vid -
2509 * @hw: The hardware instance.
2510 * @set: The flag to disable or enable.
2511 *
2512 */
2513static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2514{
2515 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2516}
2517
2518/**
2519 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2520 * @hw: The hardware instance.
2521 * @port: The port index.
2522 * @set: The flag to disable or enable.
2523 *
2524 * This routine enables the 802.1p priority re-mapping function of the switch.
2525 * That allows 802.1p priority field to be replaced with the port's default
2526 * tag's priority value if the ingress packet's 802.1p priority has a higher
2527 * priority than port's default tag's priority.
2528 */
2529static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2530{
2531 port_cfg_replace_vid(hw, port, set);
2532}
2533
2534/**
2535 * sw_cfg_port_based - configure switch port based priority
2536 * @hw: The hardware instance.
2537 * @port: The port index.
2538 * @prio: The priority to set.
2539 *
2540 * This routine configures the port based priority of the switch.
2541 */
2542static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2543{
2544 u16 data;
2545
2546 if (prio > PORT_BASED_PRIORITY_BASE)
2547 prio = PORT_BASED_PRIORITY_BASE;
2548
2549 hw->ksz_switch->port_cfg[port].port_prio = prio;
2550
2551 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2552 data &= ~PORT_BASED_PRIORITY_MASK;
2553 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2554 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2555}
2556
2557/**
2558 * sw_dis_multi_queue - disable transmit multiple queues
2559 * @hw: The hardware instance.
2560 * @port: The port index.
2561 *
2562 * This routine disables the transmit multiple queues selection of the switch
2563 * port. Only single transmit queue on the port.
2564 */
2565static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2566{
2567 port_cfg_prio(hw, port, 0);
2568}
2569
2570/**
2571 * sw_init_prio - initialize switch priority
2572 * @hw: The hardware instance.
2573 *
2574 * This routine initializes the switch QoS priority functions.
2575 */
2576static void sw_init_prio(struct ksz_hw *hw)
2577{
2578 int port;
2579 int tos;
2580 struct ksz_switch *sw = hw->ksz_switch;
2581
2582 /*
2583 * Init all the 802.1p tag priority value to be assigned to different
2584 * priority queue.
2585 */
2586 sw->p_802_1p[0] = 0;
2587 sw->p_802_1p[1] = 0;
2588 sw->p_802_1p[2] = 1;
2589 sw->p_802_1p[3] = 1;
2590 sw->p_802_1p[4] = 2;
2591 sw->p_802_1p[5] = 2;
2592 sw->p_802_1p[6] = 3;
2593 sw->p_802_1p[7] = 3;
2594
2595 /*
2596 * Init all the DiffServ priority value to be assigned to priority
2597 * queue 0.
2598 */
2599 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2600 sw->diffserv[tos] = 0;
2601
2602 /* All QoS functions disabled. */
2603 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2604 sw_dis_multi_queue(hw, port);
2605 sw_dis_diffserv(hw, port);
2606 sw_dis_802_1p(hw, port);
2607 sw_cfg_replace_vid(hw, port, 0);
2608
2609 sw->port_cfg[port].port_prio = 0;
2610 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2611 }
2612 sw_cfg_replace_null_vid(hw, 0);
2613}
2614
2615/**
2616 * port_get_def_vid - get port default VID.
2617 * @hw: The hardware instance.
2618 * @port: The port index.
2619 * @vid: Buffer to store the VID.
2620 *
2621 * This routine retrieves the default VID of the port.
2622 */
2623static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2624{
2625 u32 addr;
2626
2627 PORT_CTRL_ADDR(port, addr);
2628 addr += KS8842_PORT_CTRL_VID_OFFSET;
2629 *vid = readw(hw->io + addr);
2630}
2631
2632/**
2633 * sw_init_vlan - initialize switch VLAN
2634 * @hw: The hardware instance.
2635 *
2636 * This routine initializes the VLAN function of the switch.
2637 */
2638static void sw_init_vlan(struct ksz_hw *hw)
2639{
2640 int port;
2641 int entry;
2642 struct ksz_switch *sw = hw->ksz_switch;
2643
2644 /* Read 16 VLAN entries from device's VLAN table. */
2645 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2646 sw_r_vlan_table(hw, entry,
2647 &sw->vlan_table[entry].vid,
2648 &sw->vlan_table[entry].fid,
2649 &sw->vlan_table[entry].member);
2650 }
2651
2652 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2653 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2654 sw->port_cfg[port].member = PORT_MASK;
2655 }
2656}
2657
2658/**
2659 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2660 * @hw: The hardware instance.
2661 * @port: The port index.
2662 * @member: The port-based VLAN membership.
2663 *
2664 * This routine configures the port-based VLAN membership of the port.
2665 */
2666static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2667{
2668 u32 addr;
2669 u8 data;
2670
2671 PORT_CTRL_ADDR(port, addr);
2672 addr += KS8842_PORT_CTRL_2_OFFSET;
2673
2674 data = readb(hw->io + addr);
2675 data &= ~PORT_VLAN_MEMBERSHIP;
2676 data |= (member & PORT_MASK);
2677 writeb(data, hw->io + addr);
2678
2679 hw->ksz_switch->port_cfg[port].member = member;
2680}
2681
2682/**
2683 * sw_get_addr - get the switch MAC address.
2684 * @hw: The hardware instance.
2685 * @mac_addr: Buffer to store the MAC address.
2686 *
2687 * This function retrieves the MAC address of the switch.
2688 */
2689static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr)
2690{
2691 int i;
2692
2693 for (i = 0; i < 6; i += 2) {
2694 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2695 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2696 }
2697}
2698
2699/**
2700 * sw_set_addr - configure switch MAC address
2701 * @hw: The hardware instance.
2702 * @mac_addr: The MAC address.
2703 *
2704 * This function configures the MAC address of the switch.
2705 */
2706static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2707{
2708 int i;
2709
2710 for (i = 0; i < 6; i += 2) {
2711 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2712 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2713 }
2714}
2715
2716/**
2717 * sw_set_global_ctrl - set switch global control
2718 * @hw: The hardware instance.
2719 *
2720 * This routine sets the global control of the switch function.
2721 */
2722static void sw_set_global_ctrl(struct ksz_hw *hw)
2723{
2724 u16 data;
2725
2726 /* Enable switch MII flow control. */
2727 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2728 data |= SWITCH_FLOW_CTRL;
2729 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2730
2731 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2732
2733 /* Enable aggressive back off algorithm in half duplex mode. */
2734 data |= SWITCH_AGGR_BACKOFF;
2735
2736 /* Enable automatic fast aging when link changed detected. */
2737 data |= SWITCH_AGING_ENABLE;
2738 data |= SWITCH_LINK_AUTO_AGING;
2739
2740 if (hw->overrides & FAST_AGING)
2741 data |= SWITCH_FAST_AGING;
2742 else
2743 data &= ~SWITCH_FAST_AGING;
2744 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2745
2746 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2747
2748 /* Enable no excessive collision drop. */
2749 data |= NO_EXC_COLLISION_DROP;
2750 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2751}
2752
2753enum {
2754 STP_STATE_DISABLED = 0,
2755 STP_STATE_LISTENING,
2756 STP_STATE_LEARNING,
2757 STP_STATE_FORWARDING,
2758 STP_STATE_BLOCKED,
2759 STP_STATE_SIMPLE
2760};
2761
2762/**
2763 * port_set_stp_state - configure port spanning tree state
2764 * @hw: The hardware instance.
2765 * @port: The port index.
2766 * @state: The spanning tree state.
2767 *
2768 * This routine configures the spanning tree state of the port.
2769 */
2770static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2771{
2772 u16 data;
2773
2774 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2775 switch (state) {
2776 case STP_STATE_DISABLED:
2777 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2778 data |= PORT_LEARN_DISABLE;
2779 break;
2780 case STP_STATE_LISTENING:
2781/*
2782 * No need to turn on transmit because of port direct mode.
2783 * Turning on receive is required if static MAC table is not setup.
2784 */
2785 data &= ~PORT_TX_ENABLE;
2786 data |= PORT_RX_ENABLE;
2787 data |= PORT_LEARN_DISABLE;
2788 break;
2789 case STP_STATE_LEARNING:
2790 data &= ~PORT_TX_ENABLE;
2791 data |= PORT_RX_ENABLE;
2792 data &= ~PORT_LEARN_DISABLE;
2793 break;
2794 case STP_STATE_FORWARDING:
2795 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2796 data &= ~PORT_LEARN_DISABLE;
2797 break;
2798 case STP_STATE_BLOCKED:
2799/*
2800 * Need to setup static MAC table with override to keep receiving BPDU
2801 * messages. See sw_init_stp routine.
2802 */
2803 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2804 data |= PORT_LEARN_DISABLE;
2805 break;
2806 case STP_STATE_SIMPLE:
2807 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2808 data |= PORT_LEARN_DISABLE;
2809 break;
2810 }
2811 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2812 hw->ksz_switch->port_cfg[port].stp_state = state;
2813}
2814
2815#define STP_ENTRY 0
2816#define BROADCAST_ENTRY 1
2817#define BRIDGE_ADDR_ENTRY 2
2818#define IPV6_ADDR_ENTRY 3
2819
2820/**
2821 * sw_clr_sta_mac_table - clear static MAC table
2822 * @hw: The hardware instance.
2823 *
2824 * This routine clears the static MAC table.
2825 */
2826static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2827{
2828 struct ksz_mac_table *entry;
2829 int i;
2830
2831 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2832 entry = &hw->ksz_switch->mac_table[i];
2833 sw_w_sta_mac_table(hw, i,
2834 entry->mac_addr, entry->ports,
2835 entry->override, 0,
2836 entry->use_fid, entry->fid);
2837 }
2838}
2839
2840/**
2841 * sw_init_stp - initialize switch spanning tree support
2842 * @hw: The hardware instance.
2843 *
2844 * This routine initializes the spanning tree support of the switch.
2845 */
2846static void sw_init_stp(struct ksz_hw *hw)
2847{
2848 struct ksz_mac_table *entry;
2849
2850 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2851 entry->mac_addr[0] = 0x01;
2852 entry->mac_addr[1] = 0x80;
2853 entry->mac_addr[2] = 0xC2;
2854 entry->mac_addr[3] = 0x00;
2855 entry->mac_addr[4] = 0x00;
2856 entry->mac_addr[5] = 0x00;
2857 entry->ports = HOST_MASK;
2858 entry->override = 1;
2859 entry->valid = 1;
2860 sw_w_sta_mac_table(hw, STP_ENTRY,
2861 entry->mac_addr, entry->ports,
2862 entry->override, entry->valid,
2863 entry->use_fid, entry->fid);
2864}
2865
2866/**
2867 * sw_block_addr - block certain packets from the host port
2868 * @hw: The hardware instance.
2869 *
2870 * This routine blocks certain packets from reaching to the host port.
2871 */
2872static void sw_block_addr(struct ksz_hw *hw)
2873{
2874 struct ksz_mac_table *entry;
2875 int i;
2876
2877 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2878 entry = &hw->ksz_switch->mac_table[i];
2879 entry->valid = 0;
2880 sw_w_sta_mac_table(hw, i,
2881 entry->mac_addr, entry->ports,
2882 entry->override, entry->valid,
2883 entry->use_fid, entry->fid);
2884 }
2885}
2886
2887#define PHY_LINK_SUPPORT \
2888 (PHY_AUTO_NEG_ASYM_PAUSE | \
2889 PHY_AUTO_NEG_SYM_PAUSE | \
2890 PHY_AUTO_NEG_100BT4 | \
2891 PHY_AUTO_NEG_100BTX_FD | \
2892 PHY_AUTO_NEG_100BTX | \
2893 PHY_AUTO_NEG_10BT_FD | \
2894 PHY_AUTO_NEG_10BT)
2895
2896static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2897{
2898 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2899}
2900
2901static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2902{
2903 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2904}
2905
2906static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2907{
2908 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2909}
2910
2911static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2912{
2913 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2914}
2915
2916static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2917{
2918 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2919}
2920
2921static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2922{
2923 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2924}
2925
2926static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2927{
2928 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2929}
2930
2931static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2932{
2933 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2934}
2935
2936static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2937{
2938 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2939}
2940
2941static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2942{
2943 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2944}
2945
2946static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2947{
2948 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2949}
2950
2951static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2952{
2953 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2954}
2955
2956/**
2957 * hw_r_phy - read data from PHY register
2958 * @hw: The hardware instance.
2959 * @port: Port to read.
2960 * @reg: PHY register to read.
2961 * @val: Buffer to store the read data.
2962 *
2963 * This routine reads data from the PHY register.
2964 */
2965static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2966{
2967 int phy;
2968
2969 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2970 *val = readw(hw->io + phy);
2971}
2972
2973/**
2974 * port_w_phy - write data to PHY register
2975 * @hw: The hardware instance.
2976 * @port: Port to write.
2977 * @reg: PHY register to write.
2978 * @val: Word data to write.
2979 *
2980 * This routine writes data to the PHY register.
2981 */
2982static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
2983{
2984 int phy;
2985
2986 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2987 writew(val, hw->io + phy);
2988}
2989
2990/*
2991 * EEPROM access functions
2992 */
2993
2994#define AT93C_CODE 0
2995#define AT93C_WR_OFF 0x00
2996#define AT93C_WR_ALL 0x10
2997#define AT93C_ER_ALL 0x20
2998#define AT93C_WR_ON 0x30
2999
3000#define AT93C_WRITE 1
3001#define AT93C_READ 2
3002#define AT93C_ERASE 3
3003
3004#define EEPROM_DELAY 4
3005
3006static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
3007{
3008 u16 data;
3009
3010 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3011 data &= ~gpio;
3012 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3013}
3014
3015static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
3016{
3017 u16 data;
3018
3019 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3020 data |= gpio;
3021 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3022}
3023
3024static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
3025{
3026 u16 data;
3027
3028 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3029 return (u8)(data & gpio);
3030}
3031
3032static void eeprom_clk(struct ksz_hw *hw)
3033{
3034 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3035 udelay(EEPROM_DELAY);
3036 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3037 udelay(EEPROM_DELAY);
3038}
3039
3040static u16 spi_r(struct ksz_hw *hw)
3041{
3042 int i;
3043 u16 temp = 0;
3044
3045 for (i = 15; i >= 0; i--) {
3046 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3047 udelay(EEPROM_DELAY);
3048
3049 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
3050
3051 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3052 udelay(EEPROM_DELAY);
3053 }
3054 return temp;
3055}
3056
3057static void spi_w(struct ksz_hw *hw, u16 data)
3058{
3059 int i;
3060
3061 for (i = 15; i >= 0; i--) {
3062 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3063 drop_gpio(hw, EEPROM_DATA_OUT);
3064 eeprom_clk(hw);
3065 }
3066}
3067
3068static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
3069{
3070 int i;
3071
3072 /* Initial start bit */
3073 raise_gpio(hw, EEPROM_DATA_OUT);
3074 eeprom_clk(hw);
3075
3076 /* AT93C operation */
3077 for (i = 1; i >= 0; i--) {
3078 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3079 drop_gpio(hw, EEPROM_DATA_OUT);
3080 eeprom_clk(hw);
3081 }
3082
3083 /* Address location */
3084 for (i = 5; i >= 0; i--) {
3085 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3086 drop_gpio(hw, EEPROM_DATA_OUT);
3087 eeprom_clk(hw);
3088 }
3089}
3090
3091#define EEPROM_DATA_RESERVED 0
3092#define EEPROM_DATA_MAC_ADDR_0 1
3093#define EEPROM_DATA_MAC_ADDR_1 2
3094#define EEPROM_DATA_MAC_ADDR_2 3
3095#define EEPROM_DATA_SUBSYS_ID 4
3096#define EEPROM_DATA_SUBSYS_VEN_ID 5
3097#define EEPROM_DATA_PM_CAP 6
3098
3099/* User defined EEPROM data */
3100#define EEPROM_DATA_OTHER_MAC_ADDR 9
3101
3102/**
3103 * eeprom_read - read from AT93C46 EEPROM
3104 * @hw: The hardware instance.
3105 * @reg: The register offset.
3106 *
3107 * This function reads a word from the AT93C46 EEPROM.
3108 *
3109 * Return the data value.
3110 */
3111static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
3112{
3113 u16 data;
3114
3115 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3116
3117 spi_reg(hw, AT93C_READ, reg);
3118 data = spi_r(hw);
3119
3120 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3121
3122 return data;
3123}
3124
3125/**
3126 * eeprom_write - write to AT93C46 EEPROM
3127 * @hw: The hardware instance.
3128 * @reg: The register offset.
3129 * @data: The data value.
3130 *
3131 * This procedure writes a word to the AT93C46 EEPROM.
3132 */
3133static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3134{
3135 int timeout;
3136
3137 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3138
3139 /* Enable write. */
3140 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
3141 drop_gpio(hw, EEPROM_CHIP_SELECT);
3142 udelay(1);
3143
3144 /* Erase the register. */
3145 raise_gpio(hw, EEPROM_CHIP_SELECT);
3146 spi_reg(hw, AT93C_ERASE, reg);
3147 drop_gpio(hw, EEPROM_CHIP_SELECT);
3148 udelay(1);
3149
3150 /* Check operation complete. */
3151 raise_gpio(hw, EEPROM_CHIP_SELECT);
3152 timeout = 8;
3153 mdelay(2);
3154 do {
3155 mdelay(1);
3156 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3157 drop_gpio(hw, EEPROM_CHIP_SELECT);
3158 udelay(1);
3159
3160 /* Write the register. */
3161 raise_gpio(hw, EEPROM_CHIP_SELECT);
3162 spi_reg(hw, AT93C_WRITE, reg);
3163 spi_w(hw, data);
3164 drop_gpio(hw, EEPROM_CHIP_SELECT);
3165 udelay(1);
3166
3167 /* Check operation complete. */
3168 raise_gpio(hw, EEPROM_CHIP_SELECT);
3169 timeout = 8;
3170 mdelay(2);
3171 do {
3172 mdelay(1);
3173 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3174 drop_gpio(hw, EEPROM_CHIP_SELECT);
3175 udelay(1);
3176
3177 /* Disable write. */
3178 raise_gpio(hw, EEPROM_CHIP_SELECT);
3179 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
3180
3181 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3182}
3183
3184/*
3185 * Link detection routines
3186 */
3187
3188static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
3189{
3190 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
3191 switch (port->flow_ctrl) {
3192 case PHY_FLOW_CTRL:
3193 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
3194 break;
3195 /* Not supported. */
3196 case PHY_TX_ONLY:
3197 case PHY_RX_ONLY:
3198 default:
3199 break;
3200 }
3201 return ctrl;
3202}
3203
3204static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
3205{
3206 u32 rx_cfg;
3207 u32 tx_cfg;
3208
3209 rx_cfg = hw->rx_cfg;
3210 tx_cfg = hw->tx_cfg;
3211 if (rx)
3212 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3213 else
3214 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3215 if (tx)
3216 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
3217 else
3218 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3219 if (hw->enabled) {
3220 if (rx_cfg != hw->rx_cfg)
3221 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3222 if (tx_cfg != hw->tx_cfg)
3223 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3224 }
3225}
3226
3227static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
3228 u16 local, u16 remote)
3229{
3230 int rx;
3231 int tx;
3232
3233 if (hw->overrides & PAUSE_FLOW_CTRL)
3234 return;
3235
3236 rx = tx = 0;
3237 if (port->force_link)
3238 rx = tx = 1;
3239 if (remote & PHY_AUTO_NEG_SYM_PAUSE) {
3240 if (local & PHY_AUTO_NEG_SYM_PAUSE) {
3241 rx = tx = 1;
3242 } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) &&
3243 (local & PHY_AUTO_NEG_PAUSE) ==
3244 PHY_AUTO_NEG_ASYM_PAUSE) {
3245 tx = 1;
3246 }
3247 } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) {
3248 if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE)
3249 rx = 1;
3250 }
3251 if (!hw->ksz_switch)
3252 set_flow_ctrl(hw, rx, tx);
3253}
3254
3255static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
3256 struct ksz_port_info *info, u16 link_status)
3257{
3258 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
3259 !(hw->overrides & PAUSE_FLOW_CTRL)) {
3260 u32 cfg = hw->tx_cfg;
3261
3262 /* Disable flow control in the half duplex mode. */
3263 if (1 == info->duplex)
3264 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3265 if (hw->enabled && cfg != hw->tx_cfg)
3266 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3267 }
3268}
3269
3270/**
3271 * port_get_link_speed - get current link status
3272 * @port: The port instance.
3273 *
3274 * This routine reads PHY registers to determine the current link status of the
3275 * switch ports.
3276 */
3277static void port_get_link_speed(struct ksz_port *port)
3278{
3279 uint interrupt;
3280 struct ksz_port_info *info;
3281 struct ksz_port_info *linked = NULL;
3282 struct ksz_hw *hw = port->hw;
3283 u16 data;
3284 u16 status;
3285 u8 local;
3286 u8 remote;
3287 int i;
3288 int p;
3289 int change = 0;
3290
3291 interrupt = hw_block_intr(hw);
3292
3293 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3294 info = &hw->port_info[p];
3295 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3296 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3297
3298 /*
3299 * Link status is changing all the time even when there is no
3300 * cable connection!
3301 */
3302 remote = status & (PORT_AUTO_NEG_COMPLETE |
3303 PORT_STATUS_LINK_GOOD);
3304 local = (u8) data;
3305
3306 /* No change to status. */
3307 if (local == info->advertised && remote == info->partner)
3308 continue;
3309
3310 info->advertised = local;
3311 info->partner = remote;
3312 if (status & PORT_STATUS_LINK_GOOD) {
3313
3314 /* Remember the first linked port. */
3315 if (!linked)
3316 linked = info;
3317
3318 info->tx_rate = 10 * TX_RATE_UNIT;
3319 if (status & PORT_STATUS_SPEED_100MBIT)
3320 info->tx_rate = 100 * TX_RATE_UNIT;
3321
3322 info->duplex = 1;
3323 if (status & PORT_STATUS_FULL_DUPLEX)
3324 info->duplex = 2;
3325
3326 if (media_connected != info->state) {
3327 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
3328 &data);
3329 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
3330 &status);
3331 determine_flow_ctrl(hw, port, data, status);
3332 if (hw->ksz_switch) {
3333 port_cfg_back_pressure(hw, p,
3334 (1 == info->duplex));
3335 }
3336 change |= 1 << i;
3337 port_cfg_change(hw, port, info, status);
3338 }
3339 info->state = media_connected;
3340 } else {
3341 if (media_disconnected != info->state) {
3342 change |= 1 << i;
3343
3344 /* Indicate the link just goes down. */
3345 hw->port_mib[p].link_down = 1;
3346 }
3347 info->state = media_disconnected;
3348 }
3349 hw->port_mib[p].state = (u8) info->state;
3350 }
3351
3352 if (linked && media_disconnected == port->linked->state)
3353 port->linked = linked;
3354
3355 hw_restore_intr(hw, interrupt);
3356}
3357
3358#define PHY_RESET_TIMEOUT 10
3359
3360/**
3361 * port_set_link_speed - set port speed
3362 * @port: The port instance.
3363 *
3364 * This routine sets the link speed of the switch ports.
3365 */
3366static void port_set_link_speed(struct ksz_port *port)
3367{
3368 struct ksz_hw *hw = port->hw;
3369 u16 data;
3370 u16 cfg;
3371 u8 status;
3372 int i;
3373 int p;
3374
3375 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3376 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3377 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3378
3379 cfg = 0;
3380 if (status & PORT_STATUS_LINK_GOOD)
3381 cfg = data;
3382
3383 data |= PORT_AUTO_NEG_ENABLE;
3384 data = advertised_flow_ctrl(port, data);
3385
3386 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3387 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3388
3389 /* Check if manual configuration is specified by the user. */
3390 if (port->speed || port->duplex) {
3391 if (10 == port->speed)
3392 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3393 PORT_AUTO_NEG_100BTX);
3394 else if (100 == port->speed)
3395 data &= ~(PORT_AUTO_NEG_10BT_FD |
3396 PORT_AUTO_NEG_10BT);
3397 if (1 == port->duplex)
3398 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3399 PORT_AUTO_NEG_10BT_FD);
3400 else if (2 == port->duplex)
3401 data &= ~(PORT_AUTO_NEG_100BTX |
3402 PORT_AUTO_NEG_10BT);
3403 }
3404 if (data != cfg) {
3405 data |= PORT_AUTO_NEG_RESTART;
3406 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3407 }
3408 }
3409}
3410
3411/**
3412 * port_force_link_speed - force port speed
3413 * @port: The port instance.
3414 *
3415 * This routine forces the link speed of the switch ports.
3416 */
3417static void port_force_link_speed(struct ksz_port *port)
3418{
3419 struct ksz_hw *hw = port->hw;
3420 u16 data;
3421 int i;
3422 int phy;
3423 int p;
3424
3425 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3426 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3427 hw_r_phy_ctrl(hw, phy, &data);
3428
3429 data &= ~PHY_AUTO_NEG_ENABLE;
3430
3431 if (10 == port->speed)
3432 data &= ~PHY_SPEED_100MBIT;
3433 else if (100 == port->speed)
3434 data |= PHY_SPEED_100MBIT;
3435 if (1 == port->duplex)
3436 data &= ~PHY_FULL_DUPLEX;
3437 else if (2 == port->duplex)
3438 data |= PHY_FULL_DUPLEX;
3439 hw_w_phy_ctrl(hw, phy, data);
3440 }
3441}
3442
3443static void port_set_power_saving(struct ksz_port *port, int enable)
3444{
3445 struct ksz_hw *hw = port->hw;
3446 int i;
3447 int p;
3448
3449 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3450 port_cfg(hw, p,
3451 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3452}
3453
3454/*
3455 * KSZ8841 power management functions
3456 */
3457
3458/**
3459 * hw_chk_wol_pme_status - check PMEN pin
3460 * @hw: The hardware instance.
3461 *
3462 * This function is used to check PMEN pin is asserted.
3463 *
3464 * Return 1 if PMEN pin is asserted; otherwise, 0.
3465 */
3466static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3467{
3468 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3469 struct pci_dev *pdev = hw_priv->pdev;
3470 u16 data;
3471
3472 if (!pdev->pm_cap)
3473 return 0;
3474 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3475 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3476}
3477
3478/**
3479 * hw_clr_wol_pme_status - clear PMEN pin
3480 * @hw: The hardware instance.
3481 *
3482 * This routine is used to clear PME_Status to deassert PMEN pin.
3483 */
3484static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3485{
3486 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3487 struct pci_dev *pdev = hw_priv->pdev;
3488 u16 data;
3489
3490 if (!pdev->pm_cap)
3491 return;
3492
3493 /* Clear PME_Status to deassert PMEN pin. */
3494 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3495 data |= PCI_PM_CTRL_PME_STATUS;
3496 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3497}
3498
3499/**
3500 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3501 * @hw: The hardware instance.
3502 * @set: The flag indicating whether to enable or disable.
3503 *
3504 * This routine is used to enable or disable Wake-on-LAN.
3505 */
3506static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3507{
3508 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3509 struct pci_dev *pdev = hw_priv->pdev;
3510 u16 data;
3511
3512 if (!pdev->pm_cap)
3513 return;
3514 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3515 data &= ~PCI_PM_CTRL_STATE_MASK;
3516 if (set)
3517 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3518 else
3519 data &= ~PCI_PM_CTRL_PME_ENABLE;
3520 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3521}
3522
3523/**
3524 * hw_cfg_wol - configure Wake-on-LAN features
3525 * @hw: The hardware instance.
3526 * @frame: The pattern frame bit.
3527 * @set: The flag indicating whether to enable or disable.
3528 *
3529 * This routine is used to enable or disable certain Wake-on-LAN features.
3530 */
3531static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3532{
3533 u16 data;
3534
3535 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3536 if (set)
3537 data |= frame;
3538 else
3539 data &= ~frame;
3540 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3541}
3542
3543/**
3544 * hw_set_wol_frame - program Wake-on-LAN pattern
3545 * @hw: The hardware instance.
3546 * @i: The frame index.
3547 * @mask_size: The size of the mask.
3548 * @mask: Mask to ignore certain bytes in the pattern.
3549 * @frame_size: The size of the frame.
3550 * @pattern: The frame data.
3551 *
3552 * This routine is used to program Wake-on-LAN pattern.
3553 */
3554static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3555 const u8 *mask, uint frame_size, const u8 *pattern)
3556{
3557 int bits;
3558 int from;
3559 int len;
3560 int to;
3561 u32 crc;
3562 u8 data[64];
3563 u8 val = 0;
3564
3565 if (frame_size > mask_size * 8)
3566 frame_size = mask_size * 8;
3567 if (frame_size > 64)
3568 frame_size = 64;
3569
3570 i *= 0x10;
3571 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3572 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3573
3574 bits = len = from = to = 0;
3575 do {
3576 if (bits) {
3577 if ((val & 1))
3578 data[to++] = pattern[from];
3579 val >>= 1;
3580 ++from;
3581 --bits;
3582 } else {
3583 val = mask[len];
3584 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3585 + len);
3586 ++len;
3587 if (val)
3588 bits = 8;
3589 else
3590 from += 8;
3591 }
3592 } while (from < (int) frame_size);
3593 if (val) {
3594 bits = mask[len - 1];
3595 val <<= (from % 8);
3596 bits &= ~val;
3597 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3598 1);
3599 }
3600 crc = ether_crc(to, data);
3601 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3602}
3603
3604/**
3605 * hw_add_wol_arp - add ARP pattern
3606 * @hw: The hardware instance.
3607 * @ip_addr: The IPv4 address assigned to the device.
3608 *
3609 * This routine is used to add ARP pattern for waking up the host.
3610 */
3611static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
3612{
3613 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3614 u8 pattern[42] = {
3615 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3616 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3617 0x08, 0x06,
3618 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3619 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3620 0x00, 0x00, 0x00, 0x00,
3621 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3622 0x00, 0x00, 0x00, 0x00 };
3623
3624 memcpy(&pattern[38], ip_addr, 4);
3625 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3626}
3627
3628/**
3629 * hw_add_wol_bcast - add broadcast pattern
3630 * @hw: The hardware instance.
3631 *
3632 * This routine is used to add broadcast pattern for waking up the host.
3633 */
3634static void hw_add_wol_bcast(struct ksz_hw *hw)
3635{
3636 static const u8 mask[] = { 0x3F };
3637 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3638
3639 hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern);
3640}
3641
3642/**
3643 * hw_add_wol_mcast - add multicast pattern
3644 * @hw: The hardware instance.
3645 *
3646 * This routine is used to add multicast pattern for waking up the host.
3647 *
3648 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3649 * by IPv6 ping command. Note that multicast packets are filtred through the
3650 * multicast hash table, so not all multicast packets can wake up the host.
3651 */
3652static void hw_add_wol_mcast(struct ksz_hw *hw)
3653{
3654 static const u8 mask[] = { 0x3F };
3655 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3656
3657 memcpy(&pattern[3], &hw->override_addr[3], 3);
3658 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3659}
3660
3661/**
3662 * hw_add_wol_ucast - add unicast pattern
3663 * @hw: The hardware instance.
3664 *
3665 * This routine is used to add unicast pattern to wakeup the host.
3666 *
3667 * It is assumed the unicast packet is directed to the device, as the hardware
3668 * can only receive them in normal case.
3669 */
3670static void hw_add_wol_ucast(struct ksz_hw *hw)
3671{
3672 static const u8 mask[] = { 0x3F };
3673
3674 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr);
3675}
3676
3677/**
3678 * hw_enable_wol - enable Wake-on-LAN
3679 * @hw: The hardware instance.
3680 * @wol_enable: The Wake-on-LAN settings.
3681 * @net_addr: The IPv4 address assigned to the device.
3682 *
3683 * This routine is used to enable Wake-on-LAN depending on driver settings.
3684 */
3685static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
3686{
3687 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3688 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3689 hw_add_wol_ucast(hw);
3690 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3691 hw_add_wol_mcast(hw);
3692 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3693 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3694 hw_add_wol_arp(hw, net_addr);
3695}
3696
3697/**
3698 * hw_init - check driver is correct for the hardware
3699 * @hw: The hardware instance.
3700 *
3701 * This function checks the hardware is correct for this driver and sets the
3702 * hardware up for proper initialization.
3703 *
3704 * Return number of ports or 0 if not right.
3705 */
3706static int hw_init(struct ksz_hw *hw)
3707{
3708 int rc = 0;
3709 u16 data;
3710 u16 revision;
3711
3712 /* Set bus speed to 125MHz. */
3713 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3714
3715 /* Check KSZ884x chip ID. */
3716 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3717
3718 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3719 data &= KS884X_CHIP_ID_MASK_41;
3720 if (REG_CHIP_ID_41 == data)
3721 rc = 1;
3722 else if (REG_CHIP_ID_42 == data)
3723 rc = 2;
3724 else
3725 return 0;
3726
3727 /* Setup hardware features or bug workarounds. */
3728 if (revision <= 1) {
3729 hw->features |= SMALL_PACKET_TX_BUG;
3730 if (1 == rc)
3731 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3732 }
3733 return rc;
3734}
3735
3736/**
3737 * hw_reset - reset the hardware
3738 * @hw: The hardware instance.
3739 *
3740 * This routine resets the hardware.
3741 */
3742static void hw_reset(struct ksz_hw *hw)
3743{
3744 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3745
3746 /* Wait for device to reset. */
3747 mdelay(10);
3748
3749 /* Write 0 to clear device reset. */
3750 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3751}
3752
3753/**
3754 * hw_setup - setup the hardware
3755 * @hw: The hardware instance.
3756 *
3757 * This routine setup the hardware for proper operation.
3758 */
3759static void hw_setup(struct ksz_hw *hw)
3760{
3761#if SET_DEFAULT_LED
3762 u16 data;
3763
3764 /* Change default LED mode. */
3765 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3766 data &= ~LED_MODE;
3767 data |= SET_DEFAULT_LED;
3768 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3769#endif
3770
3771 /* Setup transmit control. */
3772 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3773 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3774
3775 /* Setup receive control. */
3776 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3777 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3778 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3779
3780 /* Hardware cannot handle UDP packet in IP fragments. */
3781 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3782
3783 if (hw->all_multi)
3784 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3785 if (hw->promiscuous)
3786 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3787}
3788
3789/**
3790 * hw_setup_intr - setup interrupt mask
3791 * @hw: The hardware instance.
3792 *
3793 * This routine setup the interrupt mask for proper operation.
3794 */
3795static void hw_setup_intr(struct ksz_hw *hw)
3796{
3797 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3798}
3799
3800static void ksz_check_desc_num(struct ksz_desc_info *info)
3801{
3802#define MIN_DESC_SHIFT 2
3803
3804 int alloc = info->alloc;
3805 int shift;
3806
3807 shift = 0;
3808 while (!(alloc & 1)) {
3809 shift++;
3810 alloc >>= 1;
3811 }
3812 if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3813 pr_alert("Hardware descriptor numbers not right!\n");
3814 while (alloc) {
3815 shift++;
3816 alloc >>= 1;
3817 }
3818 if (shift < MIN_DESC_SHIFT)
3819 shift = MIN_DESC_SHIFT;
3820 alloc = 1 << shift;
3821 info->alloc = alloc;
3822 }
3823 info->mask = info->alloc - 1;
3824}
3825
3826static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3827{
3828 int i;
3829 u32 phys = desc_info->ring_phys;
3830 struct ksz_hw_desc *desc = desc_info->ring_virt;
3831 struct ksz_desc *cur = desc_info->ring;
3832 struct ksz_desc *previous = NULL;
3833
3834 for (i = 0; i < desc_info->alloc; i++) {
3835 cur->phw = desc++;
3836 phys += desc_info->size;
3837 previous = cur++;
3838 previous->phw->next = cpu_to_le32(phys);
3839 }
3840 previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3841 previous->sw.buf.rx.end_of_ring = 1;
3842 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3843
3844 desc_info->avail = desc_info->alloc;
3845 desc_info->last = desc_info->next = 0;
3846
3847 desc_info->cur = desc_info->ring;
3848}
3849
3850/**
3851 * hw_set_desc_base - set descriptor base addresses
3852 * @hw: The hardware instance.
3853 * @tx_addr: The transmit descriptor base.
3854 * @rx_addr: The receive descriptor base.
3855 *
3856 * This routine programs the descriptor base addresses after reset.
3857 */
3858static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3859{
3860 /* Set base address of Tx/Rx descriptors. */
3861 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3862 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3863}
3864
3865static void hw_reset_pkts(struct ksz_desc_info *info)
3866{
3867 info->cur = info->ring;
3868 info->avail = info->alloc;
3869 info->last = info->next = 0;
3870}
3871
3872static inline void hw_resume_rx(struct ksz_hw *hw)
3873{
3874 writel(DMA_START, hw->io + KS_DMA_RX_START);
3875}
3876
3877/**
3878 * hw_start_rx - start receiving
3879 * @hw: The hardware instance.
3880 *
3881 * This routine starts the receive function of the hardware.
3882 */
3883static void hw_start_rx(struct ksz_hw *hw)
3884{
3885 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3886
3887 /* Notify when the receive stops. */
3888 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3889
3890 writel(DMA_START, hw->io + KS_DMA_RX_START);
3891 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3892 hw->rx_stop++;
3893
3894 /* Variable overflows. */
3895 if (0 == hw->rx_stop)
3896 hw->rx_stop = 2;
3897}
3898
3899/**
3900 * hw_stop_rx - stop receiving
3901 * @hw: The hardware instance.
3902 *
3903 * This routine stops the receive function of the hardware.
3904 */
3905static void hw_stop_rx(struct ksz_hw *hw)
3906{
3907 hw->rx_stop = 0;
3908 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3909 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3910}
3911
3912/**
3913 * hw_start_tx - start transmitting
3914 * @hw: The hardware instance.
3915 *
3916 * This routine starts the transmit function of the hardware.
3917 */
3918static void hw_start_tx(struct ksz_hw *hw)
3919{
3920 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3921}
3922
3923/**
3924 * hw_stop_tx - stop transmitting
3925 * @hw: The hardware instance.
3926 *
3927 * This routine stops the transmit function of the hardware.
3928 */
3929static void hw_stop_tx(struct ksz_hw *hw)
3930{
3931 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3932}
3933
3934/**
3935 * hw_disable - disable hardware
3936 * @hw: The hardware instance.
3937 *
3938 * This routine disables the hardware.
3939 */
3940static void hw_disable(struct ksz_hw *hw)
3941{
3942 hw_stop_rx(hw);
3943 hw_stop_tx(hw);
3944 hw->enabled = 0;
3945}
3946
3947/**
3948 * hw_enable - enable hardware
3949 * @hw: The hardware instance.
3950 *
3951 * This routine enables the hardware.
3952 */
3953static void hw_enable(struct ksz_hw *hw)
3954{
3955 hw_start_tx(hw);
3956 hw_start_rx(hw);
3957 hw->enabled = 1;
3958}
3959
3960/**
3961 * hw_alloc_pkt - allocate enough descriptors for transmission
3962 * @hw: The hardware instance.
3963 * @length: The length of the packet.
3964 * @physical: Number of descriptors required.
3965 *
3966 * This function allocates descriptors for transmission.
3967 *
3968 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3969 */
3970static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3971{
3972 /* Always leave one descriptor free. */
3973 if (hw->tx_desc_info.avail <= 1)
3974 return 0;
3975
3976 /* Allocate a descriptor for transmission and mark it current. */
3977 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3978 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
3979
3980 /* Keep track of number of transmit descriptors used so far. */
3981 ++hw->tx_int_cnt;
3982 hw->tx_size += length;
3983
3984 /* Cannot hold on too much data. */
3985 if (hw->tx_size >= MAX_TX_HELD_SIZE)
3986 hw->tx_int_cnt = hw->tx_int_mask + 1;
3987
3988 if (physical > hw->tx_desc_info.avail)
3989 return 1;
3990
3991 return hw->tx_desc_info.avail;
3992}
3993
3994/**
3995 * hw_send_pkt - mark packet for transmission
3996 * @hw: The hardware instance.
3997 *
3998 * This routine marks the packet for transmission in PCI version.
3999 */
4000static void hw_send_pkt(struct ksz_hw *hw)
4001{
4002 struct ksz_desc *cur = hw->tx_desc_info.cur;
4003
4004 cur->sw.buf.tx.last_seg = 1;
4005
4006 /* Interrupt only after specified number of descriptors used. */
4007 if (hw->tx_int_cnt > hw->tx_int_mask) {
4008 cur->sw.buf.tx.intr = 1;
4009 hw->tx_int_cnt = 0;
4010 hw->tx_size = 0;
4011 }
4012
4013 /* KSZ8842 supports port directed transmission. */
4014 cur->sw.buf.tx.dest_port = hw->dst_ports;
4015
4016 release_desc(cur);
4017
4018 writel(0, hw->io + KS_DMA_TX_START);
4019}
4020
4021static int empty_addr(u8 *addr)
4022{
4023 u32 *addr1 = (u32 *) addr;
4024 u16 *addr2 = (u16 *) &addr[4];
4025
4026 return 0 == *addr1 && 0 == *addr2;
4027}
4028
4029/**
4030 * hw_set_addr - set MAC address
4031 * @hw: The hardware instance.
4032 *
4033 * This routine programs the MAC address of the hardware when the address is
4034 * overridden.
4035 */
4036static void hw_set_addr(struct ksz_hw *hw)
4037{
4038 int i;
4039
4040 for (i = 0; i < ETH_ALEN; i++)
4041 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
4042 hw->io + KS884X_ADDR_0_OFFSET + i);
4043
4044 sw_set_addr(hw, hw->override_addr);
4045}
4046
4047/**
4048 * hw_read_addr - read MAC address
4049 * @hw: The hardware instance.
4050 *
4051 * This routine retrieves the MAC address of the hardware.
4052 */
4053static void hw_read_addr(struct ksz_hw *hw)
4054{
4055 int i;
4056
4057 for (i = 0; i < ETH_ALEN; i++)
4058 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
4059 KS884X_ADDR_0_OFFSET + i);
4060
4061 if (!hw->mac_override) {
4062 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN);
4063 if (empty_addr(hw->override_addr)) {
4064 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN);
4065 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
4066 ETH_ALEN);
4067 hw->override_addr[5] += hw->id;
4068 hw_set_addr(hw);
4069 }
4070 }
4071}
4072
4073static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
4074{
4075 int i;
4076 u32 mac_addr_lo;
4077 u32 mac_addr_hi;
4078
4079 mac_addr_hi = 0;
4080 for (i = 0; i < 2; i++) {
4081 mac_addr_hi <<= 8;
4082 mac_addr_hi |= mac_addr[i];
4083 }
4084 mac_addr_hi |= ADD_ADDR_ENABLE;
4085 mac_addr_lo = 0;
4086 for (i = 2; i < 6; i++) {
4087 mac_addr_lo <<= 8;
4088 mac_addr_lo |= mac_addr[i];
4089 }
4090 index *= ADD_ADDR_INCR;
4091
4092 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
4093 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
4094}
4095
4096static void hw_set_add_addr(struct ksz_hw *hw)
4097{
4098 int i;
4099
4100 for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
4101 if (empty_addr(hw->address[i]))
4102 writel(0, hw->io + ADD_ADDR_INCR * i +
4103 KS_ADD_ADDR_0_HI);
4104 else
4105 hw_ena_add_addr(hw, i, hw->address[i]);
4106 }
4107}
4108
4109static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr)
4110{
4111 int i;
4112 int j = ADDITIONAL_ENTRIES;
4113
4114 if (ether_addr_equal(hw->override_addr, mac_addr))
4115 return 0;
4116 for (i = 0; i < hw->addr_list_size; i++) {
4117 if (ether_addr_equal(hw->address[i], mac_addr))
4118 return 0;
4119 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
4120 j = i;
4121 }
4122 if (j < ADDITIONAL_ENTRIES) {
4123 memcpy(hw->address[j], mac_addr, ETH_ALEN);
4124 hw_ena_add_addr(hw, j, hw->address[j]);
4125 return 0;
4126 }
4127 return -1;
4128}
4129
4130static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr)
4131{
4132 int i;
4133
4134 for (i = 0; i < hw->addr_list_size; i++) {
4135 if (ether_addr_equal(hw->address[i], mac_addr)) {
4136 eth_zero_addr(hw->address[i]);
4137 writel(0, hw->io + ADD_ADDR_INCR * i +
4138 KS_ADD_ADDR_0_HI);
4139 return 0;
4140 }
4141 }
4142 return -1;
4143}
4144
4145/**
4146 * hw_clr_multicast - clear multicast addresses
4147 * @hw: The hardware instance.
4148 *
4149 * This routine removes all multicast addresses set in the hardware.
4150 */
4151static void hw_clr_multicast(struct ksz_hw *hw)
4152{
4153 int i;
4154
4155 for (i = 0; i < HW_MULTICAST_SIZE; i++) {
4156 hw->multi_bits[i] = 0;
4157
4158 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
4159 }
4160}
4161
4162/**
4163 * hw_set_grp_addr - set multicast addresses
4164 * @hw: The hardware instance.
4165 *
4166 * This routine programs multicast addresses for the hardware to accept those
4167 * addresses.
4168 */
4169static void hw_set_grp_addr(struct ksz_hw *hw)
4170{
4171 int i;
4172 int index;
4173 int position;
4174 int value;
4175
4176 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
4177
4178 for (i = 0; i < hw->multi_list_size; i++) {
4179 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
4180 index = position >> 3;
4181 value = 1 << (position & 7);
4182 hw->multi_bits[index] |= (u8) value;
4183 }
4184
4185 for (i = 0; i < HW_MULTICAST_SIZE; i++)
4186 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
4187 i);
4188}
4189
4190/**
4191 * hw_set_multicast - enable or disable all multicast receiving
4192 * @hw: The hardware instance.
4193 * @multicast: To turn on or off the all multicast feature.
4194 *
4195 * This routine enables/disables the hardware to accept all multicast packets.
4196 */
4197static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
4198{
4199 /* Stop receiving for reconfiguration. */
4200 hw_stop_rx(hw);
4201
4202 if (multicast)
4203 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4204 else
4205 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4206
4207 if (hw->enabled)
4208 hw_start_rx(hw);
4209}
4210
4211/**
4212 * hw_set_promiscuous - enable or disable promiscuous receiving
4213 * @hw: The hardware instance.
4214 * @prom: To turn on or off the promiscuous feature.
4215 *
4216 * This routine enables/disables the hardware to accept all packets.
4217 */
4218static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
4219{
4220 /* Stop receiving for reconfiguration. */
4221 hw_stop_rx(hw);
4222
4223 if (prom)
4224 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4225 else
4226 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4227
4228 if (hw->enabled)
4229 hw_start_rx(hw);
4230}
4231
4232/**
4233 * sw_enable - enable the switch
4234 * @hw: The hardware instance.
4235 * @enable: The flag to enable or disable the switch
4236 *
4237 * This routine is used to enable/disable the switch in KSZ8842.
4238 */
4239static void sw_enable(struct ksz_hw *hw, int enable)
4240{
4241 int port;
4242
4243 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4244 if (hw->dev_count > 1) {
4245 /* Set port-base vlan membership with host port. */
4246 sw_cfg_port_base_vlan(hw, port,
4247 HOST_MASK | (1 << port));
4248 port_set_stp_state(hw, port, STP_STATE_DISABLED);
4249 } else {
4250 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
4251 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
4252 }
4253 }
4254 if (hw->dev_count > 1)
4255 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4256 else
4257 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
4258
4259 if (enable)
4260 enable = KS8842_START;
4261 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
4262}
4263
4264/**
4265 * sw_setup - setup the switch
4266 * @hw: The hardware instance.
4267 *
4268 * This routine setup the hardware switch engine for default operation.
4269 */
4270static void sw_setup(struct ksz_hw *hw)
4271{
4272 int port;
4273
4274 sw_set_global_ctrl(hw);
4275
4276 /* Enable switch broadcast storm protection at 10% percent rate. */
4277 sw_init_broad_storm(hw);
4278 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
4279 for (port = 0; port < SWITCH_PORT_NUM; port++)
4280 sw_ena_broad_storm(hw, port);
4281
4282 sw_init_prio(hw);
4283
4284 sw_init_mirror(hw);
4285
4286 sw_init_prio_rate(hw);
4287
4288 sw_init_vlan(hw);
4289
4290 if (hw->features & STP_SUPPORT)
4291 sw_init_stp(hw);
4292 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
4293 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
4294 hw->overrides |= PAUSE_FLOW_CTRL;
4295 sw_enable(hw, 1);
4296}
4297
4298/**
4299 * ksz_start_timer - start kernel timer
4300 * @info: Kernel timer information.
4301 * @time: The time tick.
4302 *
4303 * This routine starts the kernel timer after the specified time tick.
4304 */
4305static void ksz_start_timer(struct ksz_timer_info *info, int time)
4306{
4307 info->cnt = 0;
4308 info->timer.expires = jiffies + time;
4309 add_timer(&info->timer);
4310
4311 /* infinity */
4312 info->max = -1;
4313}
4314
4315/**
4316 * ksz_stop_timer - stop kernel timer
4317 * @info: Kernel timer information.
4318 *
4319 * This routine stops the kernel timer.
4320 */
4321static void ksz_stop_timer(struct ksz_timer_info *info)
4322{
4323 if (info->max) {
4324 info->max = 0;
4325 del_timer_sync(&info->timer);
4326 }
4327}
4328
4329static void ksz_init_timer(struct ksz_timer_info *info, int period,
4330 void (*function)(struct timer_list *))
4331{
4332 info->max = 0;
4333 info->period = period;
4334 timer_setup(&info->timer, function, 0);
4335}
4336
4337static void ksz_update_timer(struct ksz_timer_info *info)
4338{
4339 ++info->cnt;
4340 if (info->max > 0) {
4341 if (info->cnt < info->max) {
4342 info->timer.expires = jiffies + info->period;
4343 add_timer(&info->timer);
4344 } else
4345 info->max = 0;
4346 } else if (info->max < 0) {
4347 info->timer.expires = jiffies + info->period;
4348 add_timer(&info->timer);
4349 }
4350}
4351
4352/**
4353 * ksz_alloc_soft_desc - allocate software descriptors
4354 * @desc_info: Descriptor information structure.
4355 * @transmit: Indication that descriptors are for transmit.
4356 *
4357 * This local function allocates software descriptors for manipulation in
4358 * memory.
4359 *
4360 * Return 0 if successful.
4361 */
4362static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
4363{
4364 desc_info->ring = kcalloc(desc_info->alloc, sizeof(struct ksz_desc),
4365 GFP_KERNEL);
4366 if (!desc_info->ring)
4367 return 1;
4368 hw_init_desc(desc_info, transmit);
4369 return 0;
4370}
4371
4372/**
4373 * ksz_alloc_desc - allocate hardware descriptors
4374 * @adapter: Adapter information structure.
4375 *
4376 * This local function allocates hardware descriptors for receiving and
4377 * transmitting.
4378 *
4379 * Return 0 if successful.
4380 */
4381static int ksz_alloc_desc(struct dev_info *adapter)
4382{
4383 struct ksz_hw *hw = &adapter->hw;
4384 int offset;
4385
4386 /* Allocate memory for RX & TX descriptors. */
4387 adapter->desc_pool.alloc_size =
4388 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4389 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4390 DESC_ALIGNMENT;
4391
4392 adapter->desc_pool.alloc_virt =
4393 pci_zalloc_consistent(adapter->pdev,
4394 adapter->desc_pool.alloc_size,
4395 &adapter->desc_pool.dma_addr);
4396 if (adapter->desc_pool.alloc_virt == NULL) {
4397 adapter->desc_pool.alloc_size = 0;
4398 return 1;
4399 }
4400
4401 /* Align to the next cache line boundary. */
4402 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4403 (DESC_ALIGNMENT -
4404 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4405 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4406 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4407
4408 /* Allocate receive/transmit descriptors. */
4409 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4410 adapter->desc_pool.virt;
4411 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4412 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4413 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4414 (adapter->desc_pool.virt + offset);
4415 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4416
4417 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4418 return 1;
4419 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4420 return 1;
4421
4422 return 0;
4423}
4424
4425/**
4426 * free_dma_buf - release DMA buffer resources
4427 * @adapter: Adapter information structure.
4428 *
4429 * This routine is just a helper function to release the DMA buffer resources.
4430 */
4431static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4432 int direction)
4433{
4434 pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction);
4435 dev_kfree_skb(dma_buf->skb);
4436 dma_buf->skb = NULL;
4437 dma_buf->dma = 0;
4438}
4439
4440/**
4441 * ksz_init_rx_buffers - initialize receive descriptors
4442 * @adapter: Adapter information structure.
4443 *
4444 * This routine initializes DMA buffers for receiving.
4445 */
4446static void ksz_init_rx_buffers(struct dev_info *adapter)
4447{
4448 int i;
4449 struct ksz_desc *desc;
4450 struct ksz_dma_buf *dma_buf;
4451 struct ksz_hw *hw = &adapter->hw;
4452 struct ksz_desc_info *info = &hw->rx_desc_info;
4453
4454 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4455 get_rx_pkt(info, &desc);
4456
4457 dma_buf = DMA_BUFFER(desc);
4458 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4459 free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE);
4460 dma_buf->len = adapter->mtu;
4461 if (!dma_buf->skb)
4462 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4463 if (dma_buf->skb && !dma_buf->dma)
4464 dma_buf->dma = pci_map_single(
4465 adapter->pdev,
4466 skb_tail_pointer(dma_buf->skb),
4467 dma_buf->len,
4468 PCI_DMA_FROMDEVICE);
4469
4470 /* Set descriptor. */
4471 set_rx_buf(desc, dma_buf->dma);
4472 set_rx_len(desc, dma_buf->len);
4473 release_desc(desc);
4474 }
4475}
4476
4477/**
4478 * ksz_alloc_mem - allocate memory for hardware descriptors
4479 * @adapter: Adapter information structure.
4480 *
4481 * This function allocates memory for use by hardware descriptors for receiving
4482 * and transmitting.
4483 *
4484 * Return 0 if successful.
4485 */
4486static int ksz_alloc_mem(struct dev_info *adapter)
4487{
4488 struct ksz_hw *hw = &adapter->hw;
4489
4490 /* Determine the number of receive and transmit descriptors. */
4491 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4492 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4493
4494 /* Determine how many descriptors to skip transmit interrupt. */
4495 hw->tx_int_cnt = 0;
4496 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4497 if (hw->tx_int_mask > 8)
4498 hw->tx_int_mask = 8;
4499 while (hw->tx_int_mask) {
4500 hw->tx_int_cnt++;
4501 hw->tx_int_mask >>= 1;
4502 }
4503 if (hw->tx_int_cnt) {
4504 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4505 hw->tx_int_cnt = 0;
4506 }
4507
4508 /* Determine the descriptor size. */
4509 hw->rx_desc_info.size =
4510 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4511 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4512 hw->tx_desc_info.size =
4513 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4514 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4515 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4516 pr_alert("Hardware descriptor size not right!\n");
4517 ksz_check_desc_num(&hw->rx_desc_info);
4518 ksz_check_desc_num(&hw->tx_desc_info);
4519
4520 /* Allocate descriptors. */
4521 if (ksz_alloc_desc(adapter))
4522 return 1;
4523
4524 return 0;
4525}
4526
4527/**
4528 * ksz_free_desc - free software and hardware descriptors
4529 * @adapter: Adapter information structure.
4530 *
4531 * This local routine frees the software and hardware descriptors allocated by
4532 * ksz_alloc_desc().
4533 */
4534static void ksz_free_desc(struct dev_info *adapter)
4535{
4536 struct ksz_hw *hw = &adapter->hw;
4537
4538 /* Reset descriptor. */
4539 hw->rx_desc_info.ring_virt = NULL;
4540 hw->tx_desc_info.ring_virt = NULL;
4541 hw->rx_desc_info.ring_phys = 0;
4542 hw->tx_desc_info.ring_phys = 0;
4543
4544 /* Free memory. */
4545 if (adapter->desc_pool.alloc_virt)
4546 pci_free_consistent(
4547 adapter->pdev,
4548 adapter->desc_pool.alloc_size,
4549 adapter->desc_pool.alloc_virt,
4550 adapter->desc_pool.dma_addr);
4551
4552 /* Reset resource pool. */
4553 adapter->desc_pool.alloc_size = 0;
4554 adapter->desc_pool.alloc_virt = NULL;
4555
4556 kfree(hw->rx_desc_info.ring);
4557 hw->rx_desc_info.ring = NULL;
4558 kfree(hw->tx_desc_info.ring);
4559 hw->tx_desc_info.ring = NULL;
4560}
4561
4562/**
4563 * ksz_free_buffers - free buffers used in the descriptors
4564 * @adapter: Adapter information structure.
4565 * @desc_info: Descriptor information structure.
4566 *
4567 * This local routine frees buffers used in the DMA buffers.
4568 */
4569static void ksz_free_buffers(struct dev_info *adapter,
4570 struct ksz_desc_info *desc_info, int direction)
4571{
4572 int i;
4573 struct ksz_dma_buf *dma_buf;
4574 struct ksz_desc *desc = desc_info->ring;
4575
4576 for (i = 0; i < desc_info->alloc; i++) {
4577 dma_buf = DMA_BUFFER(desc);
4578 if (dma_buf->skb)
4579 free_dma_buf(adapter, dma_buf, direction);
4580 desc++;
4581 }
4582}
4583
4584/**
4585 * ksz_free_mem - free all resources used by descriptors
4586 * @adapter: Adapter information structure.
4587 *
4588 * This local routine frees all the resources allocated by ksz_alloc_mem().
4589 */
4590static void ksz_free_mem(struct dev_info *adapter)
4591{
4592 /* Free transmit buffers. */
4593 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info,
4594 PCI_DMA_TODEVICE);
4595
4596 /* Free receive buffers. */
4597 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info,
4598 PCI_DMA_FROMDEVICE);
4599
4600 /* Free descriptors. */
4601 ksz_free_desc(adapter);
4602}
4603
4604static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4605 u64 *counter)
4606{
4607 int i;
4608 int mib;
4609 int port;
4610 struct ksz_port_mib *port_mib;
4611
4612 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4613 for (i = 0, port = first; i < cnt; i++, port++) {
4614 port_mib = &hw->port_mib[port];
4615 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4616 counter[mib] += port_mib->counter[mib];
4617 }
4618}
4619
4620/**
4621 * send_packet - send packet
4622 * @skb: Socket buffer.
4623 * @dev: Network device.
4624 *
4625 * This routine is used to send a packet out to the network.
4626 */
4627static void send_packet(struct sk_buff *skb, struct net_device *dev)
4628{
4629 struct ksz_desc *desc;
4630 struct ksz_desc *first;
4631 struct dev_priv *priv = netdev_priv(dev);
4632 struct dev_info *hw_priv = priv->adapter;
4633 struct ksz_hw *hw = &hw_priv->hw;
4634 struct ksz_desc_info *info = &hw->tx_desc_info;
4635 struct ksz_dma_buf *dma_buf;
4636 int len;
4637 int last_frag = skb_shinfo(skb)->nr_frags;
4638
4639 /*
4640 * KSZ8842 with multiple device interfaces needs to be told which port
4641 * to send.
4642 */
4643 if (hw->dev_count > 1)
4644 hw->dst_ports = 1 << priv->port.first_port;
4645
4646 /* Hardware will pad the length to 60. */
4647 len = skb->len;
4648
4649 /* Remember the very first descriptor. */
4650 first = info->cur;
4651 desc = first;
4652
4653 dma_buf = DMA_BUFFER(desc);
4654 if (last_frag) {
4655 int frag;
4656 skb_frag_t *this_frag;
4657
4658 dma_buf->len = skb_headlen(skb);
4659
4660 dma_buf->dma = pci_map_single(
4661 hw_priv->pdev, skb->data, dma_buf->len,
4662 PCI_DMA_TODEVICE);
4663 set_tx_buf(desc, dma_buf->dma);
4664 set_tx_len(desc, dma_buf->len);
4665
4666 frag = 0;
4667 do {
4668 this_frag = &skb_shinfo(skb)->frags[frag];
4669
4670 /* Get a new descriptor. */
4671 get_tx_pkt(info, &desc);
4672
4673 /* Keep track of descriptors used so far. */
4674 ++hw->tx_int_cnt;
4675
4676 dma_buf = DMA_BUFFER(desc);
4677 dma_buf->len = skb_frag_size(this_frag);
4678
4679 dma_buf->dma = pci_map_single(
4680 hw_priv->pdev,
4681 skb_frag_address(this_frag),
4682 dma_buf->len,
4683 PCI_DMA_TODEVICE);
4684 set_tx_buf(desc, dma_buf->dma);
4685 set_tx_len(desc, dma_buf->len);
4686
4687 frag++;
4688 if (frag == last_frag)
4689 break;
4690
4691 /* Do not release the last descriptor here. */
4692 release_desc(desc);
4693 } while (1);
4694
4695 /* current points to the last descriptor. */
4696 info->cur = desc;
4697
4698 /* Release the first descriptor. */
4699 release_desc(first);
4700 } else {
4701 dma_buf->len = len;
4702
4703 dma_buf->dma = pci_map_single(
4704 hw_priv->pdev, skb->data, dma_buf->len,
4705 PCI_DMA_TODEVICE);
4706 set_tx_buf(desc, dma_buf->dma);
4707 set_tx_len(desc, dma_buf->len);
4708 }
4709
4710 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4711 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4712 (desc)->sw.buf.tx.csum_gen_udp = 1;
4713 }
4714
4715 /*
4716 * The last descriptor holds the packet so that it can be returned to
4717 * network subsystem after all descriptors are transmitted.
4718 */
4719 dma_buf->skb = skb;
4720
4721 hw_send_pkt(hw);
4722
4723 /* Update transmit statistics. */
4724 dev->stats.tx_packets++;
4725 dev->stats.tx_bytes += len;
4726}
4727
4728/**
4729 * transmit_cleanup - clean up transmit descriptors
4730 * @dev: Network device.
4731 *
4732 * This routine is called to clean up the transmitted buffers.
4733 */
4734static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4735{
4736 int last;
4737 union desc_stat status;
4738 struct ksz_hw *hw = &hw_priv->hw;
4739 struct ksz_desc_info *info = &hw->tx_desc_info;
4740 struct ksz_desc *desc;
4741 struct ksz_dma_buf *dma_buf;
4742 struct net_device *dev = NULL;
4743
4744 spin_lock_irq(&hw_priv->hwlock);
4745 last = info->last;
4746
4747 while (info->avail < info->alloc) {
4748 /* Get next descriptor which is not hardware owned. */
4749 desc = &info->ring[last];
4750 status.data = le32_to_cpu(desc->phw->ctrl.data);
4751 if (status.tx.hw_owned) {
4752 if (normal)
4753 break;
4754 else
4755 reset_desc(desc, status);
4756 }
4757
4758 dma_buf = DMA_BUFFER(desc);
4759 pci_unmap_single(
4760 hw_priv->pdev, dma_buf->dma, dma_buf->len,
4761 PCI_DMA_TODEVICE);
4762
4763 /* This descriptor contains the last buffer in the packet. */
4764 if (dma_buf->skb) {
4765 dev = dma_buf->skb->dev;
4766
4767 /* Release the packet back to network subsystem. */
4768 dev_kfree_skb_irq(dma_buf->skb);
4769 dma_buf->skb = NULL;
4770 }
4771
4772 /* Free the transmitted descriptor. */
4773 last++;
4774 last &= info->mask;
4775 info->avail++;
4776 }
4777 info->last = last;
4778 spin_unlock_irq(&hw_priv->hwlock);
4779
4780 /* Notify the network subsystem that the packet has been sent. */
4781 if (dev)
4782 netif_trans_update(dev);
4783}
4784
4785/**
4786 * transmit_done - transmit done processing
4787 * @dev: Network device.
4788 *
4789 * This routine is called when the transmit interrupt is triggered, indicating
4790 * either a packet is sent successfully or there are transmit errors.
4791 */
4792static void tx_done(struct dev_info *hw_priv)
4793{
4794 struct ksz_hw *hw = &hw_priv->hw;
4795 int port;
4796
4797 transmit_cleanup(hw_priv, 1);
4798
4799 for (port = 0; port < hw->dev_count; port++) {
4800 struct net_device *dev = hw->port_info[port].pdev;
4801
4802 if (netif_running(dev) && netif_queue_stopped(dev))
4803 netif_wake_queue(dev);
4804 }
4805}
4806
4807static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4808{
4809 skb->dev = old->dev;
4810 skb->protocol = old->protocol;
4811 skb->ip_summed = old->ip_summed;
4812 skb->csum = old->csum;
4813 skb_set_network_header(skb, ETH_HLEN);
4814
4815 dev_consume_skb_any(old);
4816}
4817
4818/**
4819 * netdev_tx - send out packet
4820 * @skb: Socket buffer.
4821 * @dev: Network device.
4822 *
4823 * This function is used by the upper network layer to send out a packet.
4824 *
4825 * Return 0 if successful; otherwise an error code indicating failure.
4826 */
4827static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev)
4828{
4829 struct dev_priv *priv = netdev_priv(dev);
4830 struct dev_info *hw_priv = priv->adapter;
4831 struct ksz_hw *hw = &hw_priv->hw;
4832 int left;
4833 int num = 1;
4834 int rc = 0;
4835
4836 if (hw->features & SMALL_PACKET_TX_BUG) {
4837 struct sk_buff *org_skb = skb;
4838
4839 if (skb->len <= 48) {
4840 if (skb_end_pointer(skb) - skb->data >= 50) {
4841 memset(&skb->data[skb->len], 0, 50 - skb->len);
4842 skb->len = 50;
4843 } else {
4844 skb = netdev_alloc_skb(dev, 50);
4845 if (!skb)
4846 return NETDEV_TX_BUSY;
4847 memcpy(skb->data, org_skb->data, org_skb->len);
4848 memset(&skb->data[org_skb->len], 0,
4849 50 - org_skb->len);
4850 skb->len = 50;
4851 copy_old_skb(org_skb, skb);
4852 }
4853 }
4854 }
4855
4856 spin_lock_irq(&hw_priv->hwlock);
4857
4858 num = skb_shinfo(skb)->nr_frags + 1;
4859 left = hw_alloc_pkt(hw, skb->len, num);
4860 if (left) {
4861 if (left < num ||
4862 (CHECKSUM_PARTIAL == skb->ip_summed &&
4863 skb->protocol == htons(ETH_P_IPV6))) {
4864 struct sk_buff *org_skb = skb;
4865
4866 skb = netdev_alloc_skb(dev, org_skb->len);
4867 if (!skb) {
4868 rc = NETDEV_TX_BUSY;
4869 goto unlock;
4870 }
4871 skb_copy_and_csum_dev(org_skb, skb->data);
4872 org_skb->ip_summed = CHECKSUM_NONE;
4873 skb->len = org_skb->len;
4874 copy_old_skb(org_skb, skb);
4875 }
4876 send_packet(skb, dev);
4877 if (left <= num)
4878 netif_stop_queue(dev);
4879 } else {
4880 /* Stop the transmit queue until packet is allocated. */
4881 netif_stop_queue(dev);
4882 rc = NETDEV_TX_BUSY;
4883 }
4884unlock:
4885 spin_unlock_irq(&hw_priv->hwlock);
4886
4887 return rc;
4888}
4889
4890/**
4891 * netdev_tx_timeout - transmit timeout processing
4892 * @dev: Network device.
4893 *
4894 * This routine is called when the transmit timer expires. That indicates the
4895 * hardware is not running correctly because transmit interrupts are not
4896 * triggered to free up resources so that the transmit routine can continue
4897 * sending out packets. The hardware is reset to correct the problem.
4898 */
4899static void netdev_tx_timeout(struct net_device *dev)
4900{
4901 static unsigned long last_reset;
4902
4903 struct dev_priv *priv = netdev_priv(dev);
4904 struct dev_info *hw_priv = priv->adapter;
4905 struct ksz_hw *hw = &hw_priv->hw;
4906 int port;
4907
4908 if (hw->dev_count > 1) {
4909 /*
4910 * Only reset the hardware if time between calls is long
4911 * enough.
4912 */
4913 if (time_before_eq(jiffies, last_reset + dev->watchdog_timeo))
4914 hw_priv = NULL;
4915 }
4916
4917 last_reset = jiffies;
4918 if (hw_priv) {
4919 hw_dis_intr(hw);
4920 hw_disable(hw);
4921
4922 transmit_cleanup(hw_priv, 0);
4923 hw_reset_pkts(&hw->rx_desc_info);
4924 hw_reset_pkts(&hw->tx_desc_info);
4925 ksz_init_rx_buffers(hw_priv);
4926
4927 hw_reset(hw);
4928
4929 hw_set_desc_base(hw,
4930 hw->tx_desc_info.ring_phys,
4931 hw->rx_desc_info.ring_phys);
4932 hw_set_addr(hw);
4933 if (hw->all_multi)
4934 hw_set_multicast(hw, hw->all_multi);
4935 else if (hw->multi_list_size)
4936 hw_set_grp_addr(hw);
4937
4938 if (hw->dev_count > 1) {
4939 hw_set_add_addr(hw);
4940 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4941 struct net_device *port_dev;
4942
4943 port_set_stp_state(hw, port,
4944 STP_STATE_DISABLED);
4945
4946 port_dev = hw->port_info[port].pdev;
4947 if (netif_running(port_dev))
4948 port_set_stp_state(hw, port,
4949 STP_STATE_SIMPLE);
4950 }
4951 }
4952
4953 hw_enable(hw);
4954 hw_ena_intr(hw);
4955 }
4956
4957 netif_trans_update(dev);
4958 netif_wake_queue(dev);
4959}
4960
4961static inline void csum_verified(struct sk_buff *skb)
4962{
4963 unsigned short protocol;
4964 struct iphdr *iph;
4965
4966 protocol = skb->protocol;
4967 skb_reset_network_header(skb);
4968 iph = (struct iphdr *) skb_network_header(skb);
4969 if (protocol == htons(ETH_P_8021Q)) {
4970 protocol = iph->tot_len;
4971 skb_set_network_header(skb, VLAN_HLEN);
4972 iph = (struct iphdr *) skb_network_header(skb);
4973 }
4974 if (protocol == htons(ETH_P_IP)) {
4975 if (iph->protocol == IPPROTO_TCP)
4976 skb->ip_summed = CHECKSUM_UNNECESSARY;
4977 }
4978}
4979
4980static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
4981 struct ksz_desc *desc, union desc_stat status)
4982{
4983 int packet_len;
4984 struct dev_priv *priv = netdev_priv(dev);
4985 struct dev_info *hw_priv = priv->adapter;
4986 struct ksz_dma_buf *dma_buf;
4987 struct sk_buff *skb;
4988 int rx_status;
4989
4990 /* Received length includes 4-byte CRC. */
4991 packet_len = status.rx.frame_len - 4;
4992
4993 dma_buf = DMA_BUFFER(desc);
4994 pci_dma_sync_single_for_cpu(
4995 hw_priv->pdev, dma_buf->dma, packet_len + 4,
4996 PCI_DMA_FROMDEVICE);
4997
4998 do {
4999 /* skb->data != skb->head */
5000 skb = netdev_alloc_skb(dev, packet_len + 2);
5001 if (!skb) {
5002 dev->stats.rx_dropped++;
5003 return -ENOMEM;
5004 }
5005
5006 /*
5007 * Align socket buffer in 4-byte boundary for better
5008 * performance.
5009 */
5010 skb_reserve(skb, 2);
5011
5012 skb_put_data(skb, dma_buf->skb->data, packet_len);
5013 } while (0);
5014
5015 skb->protocol = eth_type_trans(skb, dev);
5016
5017 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5018 csum_verified(skb);
5019
5020 /* Update receive statistics. */
5021 dev->stats.rx_packets++;
5022 dev->stats.rx_bytes += packet_len;
5023
5024 /* Notify upper layer for received packet. */
5025 rx_status = netif_rx(skb);
5026
5027 return 0;
5028}
5029
5030static int dev_rcv_packets(struct dev_info *hw_priv)
5031{
5032 int next;
5033 union desc_stat status;
5034 struct ksz_hw *hw = &hw_priv->hw;
5035 struct net_device *dev = hw->port_info[0].pdev;
5036 struct ksz_desc_info *info = &hw->rx_desc_info;
5037 int left = info->alloc;
5038 struct ksz_desc *desc;
5039 int received = 0;
5040
5041 next = info->next;
5042 while (left--) {
5043 /* Get next descriptor which is not hardware owned. */
5044 desc = &info->ring[next];
5045 status.data = le32_to_cpu(desc->phw->ctrl.data);
5046 if (status.rx.hw_owned)
5047 break;
5048
5049 /* Status valid only when last descriptor bit is set. */
5050 if (status.rx.last_desc && status.rx.first_desc) {
5051 if (rx_proc(dev, hw, desc, status))
5052 goto release_packet;
5053 received++;
5054 }
5055
5056release_packet:
5057 release_desc(desc);
5058 next++;
5059 next &= info->mask;
5060 }
5061 info->next = next;
5062
5063 return received;
5064}
5065
5066static int port_rcv_packets(struct dev_info *hw_priv)
5067{
5068 int next;
5069 union desc_stat status;
5070 struct ksz_hw *hw = &hw_priv->hw;
5071 struct net_device *dev = hw->port_info[0].pdev;
5072 struct ksz_desc_info *info = &hw->rx_desc_info;
5073 int left = info->alloc;
5074 struct ksz_desc *desc;
5075 int received = 0;
5076
5077 next = info->next;
5078 while (left--) {
5079 /* Get next descriptor which is not hardware owned. */
5080 desc = &info->ring[next];
5081 status.data = le32_to_cpu(desc->phw->ctrl.data);
5082 if (status.rx.hw_owned)
5083 break;
5084
5085 if (hw->dev_count > 1) {
5086 /* Get received port number. */
5087 int p = HW_TO_DEV_PORT(status.rx.src_port);
5088
5089 dev = hw->port_info[p].pdev;
5090 if (!netif_running(dev))
5091 goto release_packet;
5092 }
5093
5094 /* Status valid only when last descriptor bit is set. */
5095 if (status.rx.last_desc && status.rx.first_desc) {
5096 if (rx_proc(dev, hw, desc, status))
5097 goto release_packet;
5098 received++;
5099 }
5100
5101release_packet:
5102 release_desc(desc);
5103 next++;
5104 next &= info->mask;
5105 }
5106 info->next = next;
5107
5108 return received;
5109}
5110
5111static int dev_rcv_special(struct dev_info *hw_priv)
5112{
5113 int next;
5114 union desc_stat status;
5115 struct ksz_hw *hw = &hw_priv->hw;
5116 struct net_device *dev = hw->port_info[0].pdev;
5117 struct ksz_desc_info *info = &hw->rx_desc_info;
5118 int left = info->alloc;
5119 struct ksz_desc *desc;
5120 int received = 0;
5121
5122 next = info->next;
5123 while (left--) {
5124 /* Get next descriptor which is not hardware owned. */
5125 desc = &info->ring[next];
5126 status.data = le32_to_cpu(desc->phw->ctrl.data);
5127 if (status.rx.hw_owned)
5128 break;
5129
5130 if (hw->dev_count > 1) {
5131 /* Get received port number. */
5132 int p = HW_TO_DEV_PORT(status.rx.src_port);
5133
5134 dev = hw->port_info[p].pdev;
5135 if (!netif_running(dev))
5136 goto release_packet;
5137 }
5138
5139 /* Status valid only when last descriptor bit is set. */
5140 if (status.rx.last_desc && status.rx.first_desc) {
5141 /*
5142 * Receive without error. With receive errors
5143 * disabled, packets with receive errors will be
5144 * dropped, so no need to check the error bit.
5145 */
5146 if (!status.rx.error || (status.data &
5147 KS_DESC_RX_ERROR_COND) ==
5148 KS_DESC_RX_ERROR_TOO_LONG) {
5149 if (rx_proc(dev, hw, desc, status))
5150 goto release_packet;
5151 received++;
5152 } else {
5153 struct dev_priv *priv = netdev_priv(dev);
5154
5155 /* Update receive error statistics. */
5156 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
5157 }
5158 }
5159
5160release_packet:
5161 release_desc(desc);
5162 next++;
5163 next &= info->mask;
5164 }
5165 info->next = next;
5166
5167 return received;
5168}
5169
5170static void rx_proc_task(unsigned long data)
5171{
5172 struct dev_info *hw_priv = (struct dev_info *) data;
5173 struct ksz_hw *hw = &hw_priv->hw;
5174
5175 if (!hw->enabled)
5176 return;
5177 if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
5178
5179 /* In case receive process is suspended because of overrun. */
5180 hw_resume_rx(hw);
5181
5182 /* tasklets are interruptible. */
5183 spin_lock_irq(&hw_priv->hwlock);
5184 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
5185 spin_unlock_irq(&hw_priv->hwlock);
5186 } else {
5187 hw_ack_intr(hw, KS884X_INT_RX);
5188 tasklet_schedule(&hw_priv->rx_tasklet);
5189 }
5190}
5191
5192static void tx_proc_task(unsigned long data)
5193{
5194 struct dev_info *hw_priv = (struct dev_info *) data;
5195 struct ksz_hw *hw = &hw_priv->hw;
5196
5197 hw_ack_intr(hw, KS884X_INT_TX_MASK);
5198
5199 tx_done(hw_priv);
5200
5201 /* tasklets are interruptible. */
5202 spin_lock_irq(&hw_priv->hwlock);
5203 hw_turn_on_intr(hw, KS884X_INT_TX);
5204 spin_unlock_irq(&hw_priv->hwlock);
5205}
5206
5207static inline void handle_rx_stop(struct ksz_hw *hw)
5208{
5209 /* Receive just has been stopped. */
5210 if (0 == hw->rx_stop)
5211 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5212 else if (hw->rx_stop > 1) {
5213 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5214 hw_start_rx(hw);
5215 } else {
5216 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5217 hw->rx_stop = 0;
5218 }
5219 } else
5220 /* Receive just has been started. */
5221 hw->rx_stop++;
5222}
5223
5224/**
5225 * netdev_intr - interrupt handling
5226 * @irq: Interrupt number.
5227 * @dev_id: Network device.
5228 *
5229 * This function is called by upper network layer to signal interrupt.
5230 *
5231 * Return IRQ_HANDLED if interrupt is handled.
5232 */
5233static irqreturn_t netdev_intr(int irq, void *dev_id)
5234{
5235 uint int_enable = 0;
5236 struct net_device *dev = (struct net_device *) dev_id;
5237 struct dev_priv *priv = netdev_priv(dev);
5238 struct dev_info *hw_priv = priv->adapter;
5239 struct ksz_hw *hw = &hw_priv->hw;
5240
5241 spin_lock(&hw_priv->hwlock);
5242
5243 hw_read_intr(hw, &int_enable);
5244
5245 /* Not our interrupt! */
5246 if (!int_enable) {
5247 spin_unlock(&hw_priv->hwlock);
5248 return IRQ_NONE;
5249 }
5250
5251 do {
5252 hw_ack_intr(hw, int_enable);
5253 int_enable &= hw->intr_mask;
5254
5255 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
5256 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
5257 tasklet_schedule(&hw_priv->tx_tasklet);
5258 }
5259
5260 if (likely(int_enable & KS884X_INT_RX)) {
5261 hw_dis_intr_bit(hw, KS884X_INT_RX);
5262 tasklet_schedule(&hw_priv->rx_tasklet);
5263 }
5264
5265 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
5266 dev->stats.rx_fifo_errors++;
5267 hw_resume_rx(hw);
5268 }
5269
5270 if (unlikely(int_enable & KS884X_INT_PHY)) {
5271 struct ksz_port *port = &priv->port;
5272
5273 hw->features |= LINK_INT_WORKING;
5274 port_get_link_speed(port);
5275 }
5276
5277 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
5278 handle_rx_stop(hw);
5279 break;
5280 }
5281
5282 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
5283 u32 data;
5284
5285 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
5286 pr_info("Tx stopped\n");
5287 data = readl(hw->io + KS_DMA_TX_CTRL);
5288 if (!(data & DMA_TX_ENABLE))
5289 pr_info("Tx disabled\n");
5290 break;
5291 }
5292 } while (0);
5293
5294 hw_ena_intr(hw);
5295
5296 spin_unlock(&hw_priv->hwlock);
5297
5298 return IRQ_HANDLED;
5299}
5300
5301/*
5302 * Linux network device functions
5303 */
5304
5305static unsigned long next_jiffies;
5306
5307#ifdef CONFIG_NET_POLL_CONTROLLER
5308static void netdev_netpoll(struct net_device *dev)
5309{
5310 struct dev_priv *priv = netdev_priv(dev);
5311 struct dev_info *hw_priv = priv->adapter;
5312
5313 hw_dis_intr(&hw_priv->hw);
5314 netdev_intr(dev->irq, dev);
5315}
5316#endif
5317
5318static void bridge_change(struct ksz_hw *hw)
5319{
5320 int port;
5321 u8 member;
5322 struct ksz_switch *sw = hw->ksz_switch;
5323
5324 /* No ports in forwarding state. */
5325 if (!sw->member) {
5326 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
5327 sw_block_addr(hw);
5328 }
5329 for (port = 0; port < SWITCH_PORT_NUM; port++) {
5330 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
5331 member = HOST_MASK | sw->member;
5332 else
5333 member = HOST_MASK | (1 << port);
5334 if (member != sw->port_cfg[port].member)
5335 sw_cfg_port_base_vlan(hw, port, member);
5336 }
5337}
5338
5339/**
5340 * netdev_close - close network device
5341 * @dev: Network device.
5342 *
5343 * This function process the close operation of network device. This is caused
5344 * by the user command "ifconfig ethX down."
5345 *
5346 * Return 0 if successful; otherwise an error code indicating failure.
5347 */
5348static int netdev_close(struct net_device *dev)
5349{
5350 struct dev_priv *priv = netdev_priv(dev);
5351 struct dev_info *hw_priv = priv->adapter;
5352 struct ksz_port *port = &priv->port;
5353 struct ksz_hw *hw = &hw_priv->hw;
5354 int pi;
5355
5356 netif_stop_queue(dev);
5357
5358 ksz_stop_timer(&priv->monitor_timer_info);
5359
5360 /* Need to shut the port manually in multiple device interfaces mode. */
5361 if (hw->dev_count > 1) {
5362 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
5363
5364 /* Port is closed. Need to change bridge setting. */
5365 if (hw->features & STP_SUPPORT) {
5366 pi = 1 << port->first_port;
5367 if (hw->ksz_switch->member & pi) {
5368 hw->ksz_switch->member &= ~pi;
5369 bridge_change(hw);
5370 }
5371 }
5372 }
5373 if (port->first_port > 0)
5374 hw_del_addr(hw, dev->dev_addr);
5375 if (!hw_priv->wol_enable)
5376 port_set_power_saving(port, true);
5377
5378 if (priv->multicast)
5379 --hw->all_multi;
5380 if (priv->promiscuous)
5381 --hw->promiscuous;
5382
5383 hw_priv->opened--;
5384 if (!(hw_priv->opened)) {
5385 ksz_stop_timer(&hw_priv->mib_timer_info);
5386 flush_work(&hw_priv->mib_read);
5387
5388 hw_dis_intr(hw);
5389 hw_disable(hw);
5390 hw_clr_multicast(hw);
5391
5392 /* Delay for receive task to stop scheduling itself. */
5393 msleep(2000 / HZ);
5394
5395 tasklet_kill(&hw_priv->rx_tasklet);
5396 tasklet_kill(&hw_priv->tx_tasklet);
5397 free_irq(dev->irq, hw_priv->dev);
5398
5399 transmit_cleanup(hw_priv, 0);
5400 hw_reset_pkts(&hw->rx_desc_info);
5401 hw_reset_pkts(&hw->tx_desc_info);
5402
5403 /* Clean out static MAC table when the switch is shutdown. */
5404 if (hw->features & STP_SUPPORT)
5405 sw_clr_sta_mac_table(hw);
5406 }
5407
5408 return 0;
5409}
5410
5411static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5412{
5413 if (hw->ksz_switch) {
5414 u32 data;
5415
5416 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5417 if (hw->features & RX_HUGE_FRAME)
5418 data |= SWITCH_HUGE_PACKET;
5419 else
5420 data &= ~SWITCH_HUGE_PACKET;
5421 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5422 }
5423 if (hw->features & RX_HUGE_FRAME) {
5424 hw->rx_cfg |= DMA_RX_ERROR;
5425 hw_priv->dev_rcv = dev_rcv_special;
5426 } else {
5427 hw->rx_cfg &= ~DMA_RX_ERROR;
5428 if (hw->dev_count > 1)
5429 hw_priv->dev_rcv = port_rcv_packets;
5430 else
5431 hw_priv->dev_rcv = dev_rcv_packets;
5432 }
5433}
5434
5435static int prepare_hardware(struct net_device *dev)
5436{
5437 struct dev_priv *priv = netdev_priv(dev);
5438 struct dev_info *hw_priv = priv->adapter;
5439 struct ksz_hw *hw = &hw_priv->hw;
5440 int rc = 0;
5441
5442 /* Remember the network device that requests interrupts. */
5443 hw_priv->dev = dev;
5444 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5445 if (rc)
5446 return rc;
5447 tasklet_init(&hw_priv->rx_tasklet, rx_proc_task,
5448 (unsigned long) hw_priv);
5449 tasklet_init(&hw_priv->tx_tasklet, tx_proc_task,
5450 (unsigned long) hw_priv);
5451
5452 hw->promiscuous = 0;
5453 hw->all_multi = 0;
5454 hw->multi_list_size = 0;
5455
5456 hw_reset(hw);
5457
5458 hw_set_desc_base(hw,
5459 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5460 hw_set_addr(hw);
5461 hw_cfg_huge_frame(hw_priv, hw);
5462 ksz_init_rx_buffers(hw_priv);
5463 return 0;
5464}
5465
5466static void set_media_state(struct net_device *dev, int media_state)
5467{
5468 struct dev_priv *priv = netdev_priv(dev);
5469
5470 if (media_state == priv->media_state)
5471 netif_carrier_on(dev);
5472 else
5473 netif_carrier_off(dev);
5474 netif_info(priv, link, dev, "link %s\n",
5475 media_state == priv->media_state ? "on" : "off");
5476}
5477
5478/**
5479 * netdev_open - open network device
5480 * @dev: Network device.
5481 *
5482 * This function process the open operation of network device. This is caused
5483 * by the user command "ifconfig ethX up."
5484 *
5485 * Return 0 if successful; otherwise an error code indicating failure.
5486 */
5487static int netdev_open(struct net_device *dev)
5488{
5489 struct dev_priv *priv = netdev_priv(dev);
5490 struct dev_info *hw_priv = priv->adapter;
5491 struct ksz_hw *hw = &hw_priv->hw;
5492 struct ksz_port *port = &priv->port;
5493 int i;
5494 int p;
5495 int rc = 0;
5496
5497 priv->multicast = 0;
5498 priv->promiscuous = 0;
5499
5500 /* Reset device statistics. */
5501 memset(&dev->stats, 0, sizeof(struct net_device_stats));
5502 memset((void *) port->counter, 0,
5503 (sizeof(u64) * OID_COUNTER_LAST));
5504
5505 if (!(hw_priv->opened)) {
5506 rc = prepare_hardware(dev);
5507 if (rc)
5508 return rc;
5509 for (i = 0; i < hw->mib_port_cnt; i++) {
5510 if (next_jiffies < jiffies)
5511 next_jiffies = jiffies + HZ * 2;
5512 else
5513 next_jiffies += HZ * 1;
5514 hw_priv->counter[i].time = next_jiffies;
5515 hw->port_mib[i].state = media_disconnected;
5516 port_init_cnt(hw, i);
5517 }
5518 if (hw->ksz_switch)
5519 hw->port_mib[HOST_PORT].state = media_connected;
5520 else {
5521 hw_add_wol_bcast(hw);
5522 hw_cfg_wol_pme(hw, 0);
5523 hw_clr_wol_pme_status(&hw_priv->hw);
5524 }
5525 }
5526 port_set_power_saving(port, false);
5527
5528 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5529 /*
5530 * Initialize to invalid value so that link detection
5531 * is done.
5532 */
5533 hw->port_info[p].partner = 0xFF;
5534 hw->port_info[p].state = media_disconnected;
5535 }
5536
5537 /* Need to open the port in multiple device interfaces mode. */
5538 if (hw->dev_count > 1) {
5539 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5540 if (port->first_port > 0)
5541 hw_add_addr(hw, dev->dev_addr);
5542 }
5543
5544 port_get_link_speed(port);
5545 if (port->force_link)
5546 port_force_link_speed(port);
5547 else
5548 port_set_link_speed(port);
5549
5550 if (!(hw_priv->opened)) {
5551 hw_setup_intr(hw);
5552 hw_enable(hw);
5553 hw_ena_intr(hw);
5554
5555 if (hw->mib_port_cnt)
5556 ksz_start_timer(&hw_priv->mib_timer_info,
5557 hw_priv->mib_timer_info.period);
5558 }
5559
5560 hw_priv->opened++;
5561
5562 ksz_start_timer(&priv->monitor_timer_info,
5563 priv->monitor_timer_info.period);
5564
5565 priv->media_state = port->linked->state;
5566
5567 set_media_state(dev, media_connected);
5568 netif_start_queue(dev);
5569
5570 return 0;
5571}
5572
5573/* RX errors = rx_errors */
5574/* RX dropped = rx_dropped */
5575/* RX overruns = rx_fifo_errors */
5576/* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5577/* TX errors = tx_errors */
5578/* TX dropped = tx_dropped */
5579/* TX overruns = tx_fifo_errors */
5580/* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5581/* collisions = collisions */
5582
5583/**
5584 * netdev_query_statistics - query network device statistics
5585 * @dev: Network device.
5586 *
5587 * This function returns the statistics of the network device. The device
5588 * needs not be opened.
5589 *
5590 * Return network device statistics.
5591 */
5592static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5593{
5594 struct dev_priv *priv = netdev_priv(dev);
5595 struct ksz_port *port = &priv->port;
5596 struct ksz_hw *hw = &priv->adapter->hw;
5597 struct ksz_port_mib *mib;
5598 int i;
5599 int p;
5600
5601 dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5602 dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5603
5604 /* Reset to zero to add count later. */
5605 dev->stats.multicast = 0;
5606 dev->stats.collisions = 0;
5607 dev->stats.rx_length_errors = 0;
5608 dev->stats.rx_crc_errors = 0;
5609 dev->stats.rx_frame_errors = 0;
5610 dev->stats.tx_window_errors = 0;
5611
5612 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5613 mib = &hw->port_mib[p];
5614
5615 dev->stats.multicast += (unsigned long)
5616 mib->counter[MIB_COUNTER_RX_MULTICAST];
5617
5618 dev->stats.collisions += (unsigned long)
5619 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5620
5621 dev->stats.rx_length_errors += (unsigned long)(
5622 mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5623 mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5624 mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5625 mib->counter[MIB_COUNTER_RX_JABBER]);
5626 dev->stats.rx_crc_errors += (unsigned long)
5627 mib->counter[MIB_COUNTER_RX_CRC_ERR];
5628 dev->stats.rx_frame_errors += (unsigned long)(
5629 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5630 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5631
5632 dev->stats.tx_window_errors += (unsigned long)
5633 mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5634 }
5635
5636 return &dev->stats;
5637}
5638
5639/**
5640 * netdev_set_mac_address - set network device MAC address
5641 * @dev: Network device.
5642 * @addr: Buffer of MAC address.
5643 *
5644 * This function is used to set the MAC address of the network device.
5645 *
5646 * Return 0 to indicate success.
5647 */
5648static int netdev_set_mac_address(struct net_device *dev, void *addr)
5649{
5650 struct dev_priv *priv = netdev_priv(dev);
5651 struct dev_info *hw_priv = priv->adapter;
5652 struct ksz_hw *hw = &hw_priv->hw;
5653 struct sockaddr *mac = addr;
5654 uint interrupt;
5655
5656 if (priv->port.first_port > 0)
5657 hw_del_addr(hw, dev->dev_addr);
5658 else {
5659 hw->mac_override = 1;
5660 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN);
5661 }
5662
5663 memcpy(dev->dev_addr, mac->sa_data, ETH_ALEN);
5664
5665 interrupt = hw_block_intr(hw);
5666
5667 if (priv->port.first_port > 0)
5668 hw_add_addr(hw, dev->dev_addr);
5669 else
5670 hw_set_addr(hw);
5671 hw_restore_intr(hw, interrupt);
5672
5673 return 0;
5674}
5675
5676static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5677 struct ksz_hw *hw, int promiscuous)
5678{
5679 if (promiscuous != priv->promiscuous) {
5680 u8 prev_state = hw->promiscuous;
5681
5682 if (promiscuous)
5683 ++hw->promiscuous;
5684 else
5685 --hw->promiscuous;
5686 priv->promiscuous = promiscuous;
5687
5688 /* Turn on/off promiscuous mode. */
5689 if (hw->promiscuous <= 1 && prev_state <= 1)
5690 hw_set_promiscuous(hw, hw->promiscuous);
5691
5692 /*
5693 * Port is not in promiscuous mode, meaning it is released
5694 * from the bridge.
5695 */
5696 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5697 (dev->priv_flags & IFF_BRIDGE_PORT)) {
5698 struct ksz_switch *sw = hw->ksz_switch;
5699 int port = priv->port.first_port;
5700
5701 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5702 port = 1 << port;
5703 if (sw->member & port) {
5704 sw->member &= ~port;
5705 bridge_change(hw);
5706 }
5707 }
5708 }
5709}
5710
5711static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5712 int multicast)
5713{
5714 if (multicast != priv->multicast) {
5715 u8 all_multi = hw->all_multi;
5716
5717 if (multicast)
5718 ++hw->all_multi;
5719 else
5720 --hw->all_multi;
5721 priv->multicast = multicast;
5722
5723 /* Turn on/off all multicast mode. */
5724 if (hw->all_multi <= 1 && all_multi <= 1)
5725 hw_set_multicast(hw, hw->all_multi);
5726 }
5727}
5728
5729/**
5730 * netdev_set_rx_mode
5731 * @dev: Network device.
5732 *
5733 * This routine is used to set multicast addresses or put the network device
5734 * into promiscuous mode.
5735 */
5736static void netdev_set_rx_mode(struct net_device *dev)
5737{
5738 struct dev_priv *priv = netdev_priv(dev);
5739 struct dev_info *hw_priv = priv->adapter;
5740 struct ksz_hw *hw = &hw_priv->hw;
5741 struct netdev_hw_addr *ha;
5742 int multicast = (dev->flags & IFF_ALLMULTI);
5743
5744 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5745
5746 if (hw_priv->hw.dev_count > 1)
5747 multicast |= (dev->flags & IFF_MULTICAST);
5748 dev_set_multicast(priv, hw, multicast);
5749
5750 /* Cannot use different hashes in multiple device interfaces mode. */
5751 if (hw_priv->hw.dev_count > 1)
5752 return;
5753
5754 if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
5755 int i = 0;
5756
5757 /* List too big to support so turn on all multicast mode. */
5758 if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) {
5759 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5760 hw->multi_list_size = MAX_MULTICAST_LIST;
5761 ++hw->all_multi;
5762 hw_set_multicast(hw, hw->all_multi);
5763 }
5764 return;
5765 }
5766
5767 netdev_for_each_mc_addr(ha, dev) {
5768 if (i >= MAX_MULTICAST_LIST)
5769 break;
5770 memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN);
5771 }
5772 hw->multi_list_size = (u8) i;
5773 hw_set_grp_addr(hw);
5774 } else {
5775 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5776 --hw->all_multi;
5777 hw_set_multicast(hw, hw->all_multi);
5778 }
5779 hw->multi_list_size = 0;
5780 hw_clr_multicast(hw);
5781 }
5782}
5783
5784static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5785{
5786 struct dev_priv *priv = netdev_priv(dev);
5787 struct dev_info *hw_priv = priv->adapter;
5788 struct ksz_hw *hw = &hw_priv->hw;
5789 int hw_mtu;
5790
5791 if (netif_running(dev))
5792 return -EBUSY;
5793
5794 /* Cannot use different MTU in multiple device interfaces mode. */
5795 if (hw->dev_count > 1)
5796 if (dev != hw_priv->dev)
5797 return 0;
5798
5799 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5800 if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5801 hw->features |= RX_HUGE_FRAME;
5802 hw_mtu = MAX_RX_BUF_SIZE;
5803 } else {
5804 hw->features &= ~RX_HUGE_FRAME;
5805 hw_mtu = REGULAR_RX_BUF_SIZE;
5806 }
5807 hw_mtu = (hw_mtu + 3) & ~3;
5808 hw_priv->mtu = hw_mtu;
5809 dev->mtu = new_mtu;
5810
5811 return 0;
5812}
5813
5814/**
5815 * netdev_ioctl - I/O control processing
5816 * @dev: Network device.
5817 * @ifr: Interface request structure.
5818 * @cmd: I/O control code.
5819 *
5820 * This function is used to process I/O control calls.
5821 *
5822 * Return 0 to indicate success.
5823 */
5824static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5825{
5826 struct dev_priv *priv = netdev_priv(dev);
5827 struct dev_info *hw_priv = priv->adapter;
5828 struct ksz_hw *hw = &hw_priv->hw;
5829 struct ksz_port *port = &priv->port;
5830 int result = 0;
5831 struct mii_ioctl_data *data = if_mii(ifr);
5832
5833 if (down_interruptible(&priv->proc_sem))
5834 return -ERESTARTSYS;
5835
5836 switch (cmd) {
5837 /* Get address of MII PHY in use. */
5838 case SIOCGMIIPHY:
5839 data->phy_id = priv->id;
5840
5841 /* Fallthrough... */
5842
5843 /* Read MII PHY register. */
5844 case SIOCGMIIREG:
5845 if (data->phy_id != priv->id || data->reg_num >= 6)
5846 result = -EIO;
5847 else
5848 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5849 &data->val_out);
5850 break;
5851
5852 /* Write MII PHY register. */
5853 case SIOCSMIIREG:
5854 if (!capable(CAP_NET_ADMIN))
5855 result = -EPERM;
5856 else if (data->phy_id != priv->id || data->reg_num >= 6)
5857 result = -EIO;
5858 else
5859 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5860 data->val_in);
5861 break;
5862
5863 default:
5864 result = -EOPNOTSUPP;
5865 }
5866
5867 up(&priv->proc_sem);
5868
5869 return result;
5870}
5871
5872/*
5873 * MII support
5874 */
5875
5876/**
5877 * mdio_read - read PHY register
5878 * @dev: Network device.
5879 * @phy_id: The PHY id.
5880 * @reg_num: The register number.
5881 *
5882 * This function returns the PHY register value.
5883 *
5884 * Return the register value.
5885 */
5886static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5887{
5888 struct dev_priv *priv = netdev_priv(dev);
5889 struct ksz_port *port = &priv->port;
5890 struct ksz_hw *hw = port->hw;
5891 u16 val_out;
5892
5893 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5894 return val_out;
5895}
5896
5897/**
5898 * mdio_write - set PHY register
5899 * @dev: Network device.
5900 * @phy_id: The PHY id.
5901 * @reg_num: The register number.
5902 * @val: The register value.
5903 *
5904 * This procedure sets the PHY register value.
5905 */
5906static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5907{
5908 struct dev_priv *priv = netdev_priv(dev);
5909 struct ksz_port *port = &priv->port;
5910 struct ksz_hw *hw = port->hw;
5911 int i;
5912 int pi;
5913
5914 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5915 hw_w_phy(hw, pi, reg_num << 1, val);
5916}
5917
5918/*
5919 * ethtool support
5920 */
5921
5922#define EEPROM_SIZE 0x40
5923
5924static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5925
5926#define ADVERTISED_ALL \
5927 (ADVERTISED_10baseT_Half | \
5928 ADVERTISED_10baseT_Full | \
5929 ADVERTISED_100baseT_Half | \
5930 ADVERTISED_100baseT_Full)
5931
5932/* These functions use the MII functions in mii.c. */
5933
5934/**
5935 * netdev_get_link_ksettings - get network device settings
5936 * @dev: Network device.
5937 * @cmd: Ethtool command.
5938 *
5939 * This function queries the PHY and returns its state in the ethtool command.
5940 *
5941 * Return 0 if successful; otherwise an error code.
5942 */
5943static int netdev_get_link_ksettings(struct net_device *dev,
5944 struct ethtool_link_ksettings *cmd)
5945{
5946 struct dev_priv *priv = netdev_priv(dev);
5947 struct dev_info *hw_priv = priv->adapter;
5948
5949 mutex_lock(&hw_priv->lock);
5950 mii_ethtool_get_link_ksettings(&priv->mii_if, cmd);
5951 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
5952 mutex_unlock(&hw_priv->lock);
5953
5954 /* Save advertised settings for workaround in next function. */
5955 ethtool_convert_link_mode_to_legacy_u32(&priv->advertising,
5956 cmd->link_modes.advertising);
5957
5958 return 0;
5959}
5960
5961/**
5962 * netdev_set_link_ksettings - set network device settings
5963 * @dev: Network device.
5964 * @cmd: Ethtool command.
5965 *
5966 * This function sets the PHY according to the ethtool command.
5967 *
5968 * Return 0 if successful; otherwise an error code.
5969 */
5970static int netdev_set_link_ksettings(struct net_device *dev,
5971 const struct ethtool_link_ksettings *cmd)
5972{
5973 struct dev_priv *priv = netdev_priv(dev);
5974 struct dev_info *hw_priv = priv->adapter;
5975 struct ksz_port *port = &priv->port;
5976 struct ethtool_link_ksettings copy_cmd;
5977 u32 speed = cmd->base.speed;
5978 u32 advertising;
5979 int rc;
5980
5981 ethtool_convert_link_mode_to_legacy_u32(&advertising,
5982 cmd->link_modes.advertising);
5983
5984 /*
5985 * ethtool utility does not change advertised setting if auto
5986 * negotiation is not specified explicitly.
5987 */
5988 if (cmd->base.autoneg && priv->advertising == advertising) {
5989 advertising |= ADVERTISED_ALL;
5990 if (10 == speed)
5991 advertising &=
5992 ~(ADVERTISED_100baseT_Full |
5993 ADVERTISED_100baseT_Half);
5994 else if (100 == speed)
5995 advertising &=
5996 ~(ADVERTISED_10baseT_Full |
5997 ADVERTISED_10baseT_Half);
5998 if (0 == cmd->base.duplex)
5999 advertising &=
6000 ~(ADVERTISED_100baseT_Full |
6001 ADVERTISED_10baseT_Full);
6002 else if (1 == cmd->base.duplex)
6003 advertising &=
6004 ~(ADVERTISED_100baseT_Half |
6005 ADVERTISED_10baseT_Half);
6006 }
6007 mutex_lock(&hw_priv->lock);
6008 if (cmd->base.autoneg &&
6009 (advertising & ADVERTISED_ALL) == ADVERTISED_ALL) {
6010 port->duplex = 0;
6011 port->speed = 0;
6012 port->force_link = 0;
6013 } else {
6014 port->duplex = cmd->base.duplex + 1;
6015 if (1000 != speed)
6016 port->speed = speed;
6017 if (cmd->base.autoneg)
6018 port->force_link = 0;
6019 else
6020 port->force_link = 1;
6021 }
6022
6023 memcpy(©_cmd, cmd, sizeof(copy_cmd));
6024 ethtool_convert_legacy_u32_to_link_mode(copy_cmd.link_modes.advertising,
6025 advertising);
6026 rc = mii_ethtool_set_link_ksettings(
6027 &priv->mii_if,
6028 (const struct ethtool_link_ksettings *)©_cmd);
6029 mutex_unlock(&hw_priv->lock);
6030 return rc;
6031}
6032
6033/**
6034 * netdev_nway_reset - restart auto-negotiation
6035 * @dev: Network device.
6036 *
6037 * This function restarts the PHY for auto-negotiation.
6038 *
6039 * Return 0 if successful; otherwise an error code.
6040 */
6041static int netdev_nway_reset(struct net_device *dev)
6042{
6043 struct dev_priv *priv = netdev_priv(dev);
6044 struct dev_info *hw_priv = priv->adapter;
6045 int rc;
6046
6047 mutex_lock(&hw_priv->lock);
6048 rc = mii_nway_restart(&priv->mii_if);
6049 mutex_unlock(&hw_priv->lock);
6050 return rc;
6051}
6052
6053/**
6054 * netdev_get_link - get network device link status
6055 * @dev: Network device.
6056 *
6057 * This function gets the link status from the PHY.
6058 *
6059 * Return true if PHY is linked and false otherwise.
6060 */
6061static u32 netdev_get_link(struct net_device *dev)
6062{
6063 struct dev_priv *priv = netdev_priv(dev);
6064 int rc;
6065
6066 rc = mii_link_ok(&priv->mii_if);
6067 return rc;
6068}
6069
6070/**
6071 * netdev_get_drvinfo - get network driver information
6072 * @dev: Network device.
6073 * @info: Ethtool driver info data structure.
6074 *
6075 * This procedure returns the driver information.
6076 */
6077static void netdev_get_drvinfo(struct net_device *dev,
6078 struct ethtool_drvinfo *info)
6079{
6080 struct dev_priv *priv = netdev_priv(dev);
6081 struct dev_info *hw_priv = priv->adapter;
6082
6083 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
6084 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
6085 strlcpy(info->bus_info, pci_name(hw_priv->pdev),
6086 sizeof(info->bus_info));
6087}
6088
6089/**
6090 * netdev_get_regs_len - get length of register dump
6091 * @dev: Network device.
6092 *
6093 * This function returns the length of the register dump.
6094 *
6095 * Return length of the register dump.
6096 */
6097static struct hw_regs {
6098 int start;
6099 int end;
6100} hw_regs_range[] = {
6101 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS },
6102 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI },
6103 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
6104 { KS884X_SIDER_P, KS8842_SGCR7_P },
6105 { KS8842_MACAR1_P, KS8842_TOSR8_P },
6106 { KS884X_P1MBCR_P, KS8842_P3ERCR_P },
6107 { 0, 0 }
6108};
6109
6110static int netdev_get_regs_len(struct net_device *dev)
6111{
6112 struct hw_regs *range = hw_regs_range;
6113 int regs_len = 0x10 * sizeof(u32);
6114
6115 while (range->end > range->start) {
6116 regs_len += (range->end - range->start + 3) / 4 * 4;
6117 range++;
6118 }
6119 return regs_len;
6120}
6121
6122/**
6123 * netdev_get_regs - get register dump
6124 * @dev: Network device.
6125 * @regs: Ethtool registers data structure.
6126 * @ptr: Buffer to store the register values.
6127 *
6128 * This procedure dumps the register values in the provided buffer.
6129 */
6130static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
6131 void *ptr)
6132{
6133 struct dev_priv *priv = netdev_priv(dev);
6134 struct dev_info *hw_priv = priv->adapter;
6135 struct ksz_hw *hw = &hw_priv->hw;
6136 int *buf = (int *) ptr;
6137 struct hw_regs *range = hw_regs_range;
6138 int len;
6139
6140 mutex_lock(&hw_priv->lock);
6141 regs->version = 0;
6142 for (len = 0; len < 0x40; len += 4) {
6143 pci_read_config_dword(hw_priv->pdev, len, buf);
6144 buf++;
6145 }
6146 while (range->end > range->start) {
6147 for (len = range->start; len < range->end; len += 4) {
6148 *buf = readl(hw->io + len);
6149 buf++;
6150 }
6151 range++;
6152 }
6153 mutex_unlock(&hw_priv->lock);
6154}
6155
6156#define WOL_SUPPORT \
6157 (WAKE_PHY | WAKE_MAGIC | \
6158 WAKE_UCAST | WAKE_MCAST | \
6159 WAKE_BCAST | WAKE_ARP)
6160
6161/**
6162 * netdev_get_wol - get Wake-on-LAN support
6163 * @dev: Network device.
6164 * @wol: Ethtool Wake-on-LAN data structure.
6165 *
6166 * This procedure returns Wake-on-LAN support.
6167 */
6168static void netdev_get_wol(struct net_device *dev,
6169 struct ethtool_wolinfo *wol)
6170{
6171 struct dev_priv *priv = netdev_priv(dev);
6172 struct dev_info *hw_priv = priv->adapter;
6173
6174 wol->supported = hw_priv->wol_support;
6175 wol->wolopts = hw_priv->wol_enable;
6176 memset(&wol->sopass, 0, sizeof(wol->sopass));
6177}
6178
6179/**
6180 * netdev_set_wol - set Wake-on-LAN support
6181 * @dev: Network device.
6182 * @wol: Ethtool Wake-on-LAN data structure.
6183 *
6184 * This function sets Wake-on-LAN support.
6185 *
6186 * Return 0 if successful; otherwise an error code.
6187 */
6188static int netdev_set_wol(struct net_device *dev,
6189 struct ethtool_wolinfo *wol)
6190{
6191 struct dev_priv *priv = netdev_priv(dev);
6192 struct dev_info *hw_priv = priv->adapter;
6193
6194 /* Need to find a way to retrieve the device IP address. */
6195 static const u8 net_addr[] = { 192, 168, 1, 1 };
6196
6197 if (wol->wolopts & ~hw_priv->wol_support)
6198 return -EINVAL;
6199
6200 hw_priv->wol_enable = wol->wolopts;
6201
6202 /* Link wakeup cannot really be disabled. */
6203 if (wol->wolopts)
6204 hw_priv->wol_enable |= WAKE_PHY;
6205 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
6206 return 0;
6207}
6208
6209/**
6210 * netdev_get_msglevel - get debug message level
6211 * @dev: Network device.
6212 *
6213 * This function returns current debug message level.
6214 *
6215 * Return current debug message flags.
6216 */
6217static u32 netdev_get_msglevel(struct net_device *dev)
6218{
6219 struct dev_priv *priv = netdev_priv(dev);
6220
6221 return priv->msg_enable;
6222}
6223
6224/**
6225 * netdev_set_msglevel - set debug message level
6226 * @dev: Network device.
6227 * @value: Debug message flags.
6228 *
6229 * This procedure sets debug message level.
6230 */
6231static void netdev_set_msglevel(struct net_device *dev, u32 value)
6232{
6233 struct dev_priv *priv = netdev_priv(dev);
6234
6235 priv->msg_enable = value;
6236}
6237
6238/**
6239 * netdev_get_eeprom_len - get EEPROM length
6240 * @dev: Network device.
6241 *
6242 * This function returns the length of the EEPROM.
6243 *
6244 * Return length of the EEPROM.
6245 */
6246static int netdev_get_eeprom_len(struct net_device *dev)
6247{
6248 return EEPROM_SIZE * 2;
6249}
6250
6251/**
6252 * netdev_get_eeprom - get EEPROM data
6253 * @dev: Network device.
6254 * @eeprom: Ethtool EEPROM data structure.
6255 * @data: Buffer to store the EEPROM data.
6256 *
6257 * This function dumps the EEPROM data in the provided buffer.
6258 *
6259 * Return 0 if successful; otherwise an error code.
6260 */
6261#define EEPROM_MAGIC 0x10A18842
6262
6263static int netdev_get_eeprom(struct net_device *dev,
6264 struct ethtool_eeprom *eeprom, u8 *data)
6265{
6266 struct dev_priv *priv = netdev_priv(dev);
6267 struct dev_info *hw_priv = priv->adapter;
6268 u8 *eeprom_byte = (u8 *) eeprom_data;
6269 int i;
6270 int len;
6271
6272 len = (eeprom->offset + eeprom->len + 1) / 2;
6273 for (i = eeprom->offset / 2; i < len; i++)
6274 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6275 eeprom->magic = EEPROM_MAGIC;
6276 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
6277
6278 return 0;
6279}
6280
6281/**
6282 * netdev_set_eeprom - write EEPROM data
6283 * @dev: Network device.
6284 * @eeprom: Ethtool EEPROM data structure.
6285 * @data: Data buffer.
6286 *
6287 * This function modifies the EEPROM data one byte at a time.
6288 *
6289 * Return 0 if successful; otherwise an error code.
6290 */
6291static int netdev_set_eeprom(struct net_device *dev,
6292 struct ethtool_eeprom *eeprom, u8 *data)
6293{
6294 struct dev_priv *priv = netdev_priv(dev);
6295 struct dev_info *hw_priv = priv->adapter;
6296 u16 eeprom_word[EEPROM_SIZE];
6297 u8 *eeprom_byte = (u8 *) eeprom_word;
6298 int i;
6299 int len;
6300
6301 if (eeprom->magic != EEPROM_MAGIC)
6302 return -EINVAL;
6303
6304 len = (eeprom->offset + eeprom->len + 1) / 2;
6305 for (i = eeprom->offset / 2; i < len; i++)
6306 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6307 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
6308 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
6309 for (i = 0; i < EEPROM_SIZE; i++)
6310 if (eeprom_word[i] != eeprom_data[i]) {
6311 eeprom_data[i] = eeprom_word[i];
6312 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
6313 }
6314
6315 return 0;
6316}
6317
6318/**
6319 * netdev_get_pauseparam - get flow control parameters
6320 * @dev: Network device.
6321 * @pause: Ethtool PAUSE settings data structure.
6322 *
6323 * This procedure returns the PAUSE control flow settings.
6324 */
6325static void netdev_get_pauseparam(struct net_device *dev,
6326 struct ethtool_pauseparam *pause)
6327{
6328 struct dev_priv *priv = netdev_priv(dev);
6329 struct dev_info *hw_priv = priv->adapter;
6330 struct ksz_hw *hw = &hw_priv->hw;
6331
6332 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
6333 if (!hw->ksz_switch) {
6334 pause->rx_pause =
6335 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6336 pause->tx_pause =
6337 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
6338 } else {
6339 pause->rx_pause =
6340 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6341 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
6342 pause->tx_pause =
6343 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6344 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
6345 }
6346}
6347
6348/**
6349 * netdev_set_pauseparam - set flow control parameters
6350 * @dev: Network device.
6351 * @pause: Ethtool PAUSE settings data structure.
6352 *
6353 * This function sets the PAUSE control flow settings.
6354 * Not implemented yet.
6355 *
6356 * Return 0 if successful; otherwise an error code.
6357 */
6358static int netdev_set_pauseparam(struct net_device *dev,
6359 struct ethtool_pauseparam *pause)
6360{
6361 struct dev_priv *priv = netdev_priv(dev);
6362 struct dev_info *hw_priv = priv->adapter;
6363 struct ksz_hw *hw = &hw_priv->hw;
6364 struct ksz_port *port = &priv->port;
6365
6366 mutex_lock(&hw_priv->lock);
6367 if (pause->autoneg) {
6368 if (!pause->rx_pause && !pause->tx_pause)
6369 port->flow_ctrl = PHY_NO_FLOW_CTRL;
6370 else
6371 port->flow_ctrl = PHY_FLOW_CTRL;
6372 hw->overrides &= ~PAUSE_FLOW_CTRL;
6373 port->force_link = 0;
6374 if (hw->ksz_switch) {
6375 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6376 SWITCH_RX_FLOW_CTRL, 1);
6377 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6378 SWITCH_TX_FLOW_CTRL, 1);
6379 }
6380 port_set_link_speed(port);
6381 } else {
6382 hw->overrides |= PAUSE_FLOW_CTRL;
6383 if (hw->ksz_switch) {
6384 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6385 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6386 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6387 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6388 } else
6389 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6390 }
6391 mutex_unlock(&hw_priv->lock);
6392
6393 return 0;
6394}
6395
6396/**
6397 * netdev_get_ringparam - get tx/rx ring parameters
6398 * @dev: Network device.
6399 * @pause: Ethtool RING settings data structure.
6400 *
6401 * This procedure returns the TX/RX ring settings.
6402 */
6403static void netdev_get_ringparam(struct net_device *dev,
6404 struct ethtool_ringparam *ring)
6405{
6406 struct dev_priv *priv = netdev_priv(dev);
6407 struct dev_info *hw_priv = priv->adapter;
6408 struct ksz_hw *hw = &hw_priv->hw;
6409
6410 ring->tx_max_pending = (1 << 9);
6411 ring->tx_pending = hw->tx_desc_info.alloc;
6412 ring->rx_max_pending = (1 << 9);
6413 ring->rx_pending = hw->rx_desc_info.alloc;
6414}
6415
6416#define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6417
6418static struct {
6419 char string[ETH_GSTRING_LEN];
6420} ethtool_stats_keys[STATS_LEN] = {
6421 { "rx_lo_priority_octets" },
6422 { "rx_hi_priority_octets" },
6423 { "rx_undersize_packets" },
6424 { "rx_fragments" },
6425 { "rx_oversize_packets" },
6426 { "rx_jabbers" },
6427 { "rx_symbol_errors" },
6428 { "rx_crc_errors" },
6429 { "rx_align_errors" },
6430 { "rx_mac_ctrl_packets" },
6431 { "rx_pause_packets" },
6432 { "rx_bcast_packets" },
6433 { "rx_mcast_packets" },
6434 { "rx_ucast_packets" },
6435 { "rx_64_or_less_octet_packets" },
6436 { "rx_65_to_127_octet_packets" },
6437 { "rx_128_to_255_octet_packets" },
6438 { "rx_256_to_511_octet_packets" },
6439 { "rx_512_to_1023_octet_packets" },
6440 { "rx_1024_to_1522_octet_packets" },
6441
6442 { "tx_lo_priority_octets" },
6443 { "tx_hi_priority_octets" },
6444 { "tx_late_collisions" },
6445 { "tx_pause_packets" },
6446 { "tx_bcast_packets" },
6447 { "tx_mcast_packets" },
6448 { "tx_ucast_packets" },
6449 { "tx_deferred" },
6450 { "tx_total_collisions" },
6451 { "tx_excessive_collisions" },
6452 { "tx_single_collisions" },
6453 { "tx_mult_collisions" },
6454
6455 { "rx_discards" },
6456 { "tx_discards" },
6457};
6458
6459/**
6460 * netdev_get_strings - get statistics identity strings
6461 * @dev: Network device.
6462 * @stringset: String set identifier.
6463 * @buf: Buffer to store the strings.
6464 *
6465 * This procedure returns the strings used to identify the statistics.
6466 */
6467static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6468{
6469 struct dev_priv *priv = netdev_priv(dev);
6470 struct dev_info *hw_priv = priv->adapter;
6471 struct ksz_hw *hw = &hw_priv->hw;
6472
6473 if (ETH_SS_STATS == stringset)
6474 memcpy(buf, ðtool_stats_keys,
6475 ETH_GSTRING_LEN * hw->mib_cnt);
6476}
6477
6478/**
6479 * netdev_get_sset_count - get statistics size
6480 * @dev: Network device.
6481 * @sset: The statistics set number.
6482 *
6483 * This function returns the size of the statistics to be reported.
6484 *
6485 * Return size of the statistics to be reported.
6486 */
6487static int netdev_get_sset_count(struct net_device *dev, int sset)
6488{
6489 struct dev_priv *priv = netdev_priv(dev);
6490 struct dev_info *hw_priv = priv->adapter;
6491 struct ksz_hw *hw = &hw_priv->hw;
6492
6493 switch (sset) {
6494 case ETH_SS_STATS:
6495 return hw->mib_cnt;
6496 default:
6497 return -EOPNOTSUPP;
6498 }
6499}
6500
6501/**
6502 * netdev_get_ethtool_stats - get network device statistics
6503 * @dev: Network device.
6504 * @stats: Ethtool statistics data structure.
6505 * @data: Buffer to store the statistics.
6506 *
6507 * This procedure returns the statistics.
6508 */
6509static void netdev_get_ethtool_stats(struct net_device *dev,
6510 struct ethtool_stats *stats, u64 *data)
6511{
6512 struct dev_priv *priv = netdev_priv(dev);
6513 struct dev_info *hw_priv = priv->adapter;
6514 struct ksz_hw *hw = &hw_priv->hw;
6515 struct ksz_port *port = &priv->port;
6516 int n_stats = stats->n_stats;
6517 int i;
6518 int n;
6519 int p;
6520 int rc;
6521 u64 counter[TOTAL_PORT_COUNTER_NUM];
6522
6523 mutex_lock(&hw_priv->lock);
6524 n = SWITCH_PORT_NUM;
6525 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6526 if (media_connected == hw->port_mib[p].state) {
6527 hw_priv->counter[p].read = 1;
6528
6529 /* Remember first port that requests read. */
6530 if (n == SWITCH_PORT_NUM)
6531 n = p;
6532 }
6533 }
6534 mutex_unlock(&hw_priv->lock);
6535
6536 if (n < SWITCH_PORT_NUM)
6537 schedule_work(&hw_priv->mib_read);
6538
6539 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6540 p = n;
6541 rc = wait_event_interruptible_timeout(
6542 hw_priv->counter[p].counter,
6543 2 == hw_priv->counter[p].read,
6544 HZ * 1);
6545 } else
6546 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6547 if (0 == i) {
6548 rc = wait_event_interruptible_timeout(
6549 hw_priv->counter[p].counter,
6550 2 == hw_priv->counter[p].read,
6551 HZ * 2);
6552 } else if (hw->port_mib[p].cnt_ptr) {
6553 rc = wait_event_interruptible_timeout(
6554 hw_priv->counter[p].counter,
6555 2 == hw_priv->counter[p].read,
6556 HZ * 1);
6557 }
6558 }
6559
6560 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6561 n = hw->mib_cnt;
6562 if (n > n_stats)
6563 n = n_stats;
6564 n_stats -= n;
6565 for (i = 0; i < n; i++)
6566 *data++ = counter[i];
6567}
6568
6569/**
6570 * netdev_set_features - set receive checksum support
6571 * @dev: Network device.
6572 * @features: New device features (offloads).
6573 *
6574 * This function sets receive checksum support setting.
6575 *
6576 * Return 0 if successful; otherwise an error code.
6577 */
6578static int netdev_set_features(struct net_device *dev,
6579 netdev_features_t features)
6580{
6581 struct dev_priv *priv = netdev_priv(dev);
6582 struct dev_info *hw_priv = priv->adapter;
6583 struct ksz_hw *hw = &hw_priv->hw;
6584
6585 mutex_lock(&hw_priv->lock);
6586
6587 /* see note in hw_setup() */
6588 if (features & NETIF_F_RXCSUM)
6589 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6590 else
6591 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6592
6593 if (hw->enabled)
6594 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6595
6596 mutex_unlock(&hw_priv->lock);
6597
6598 return 0;
6599}
6600
6601static const struct ethtool_ops netdev_ethtool_ops = {
6602 .nway_reset = netdev_nway_reset,
6603 .get_link = netdev_get_link,
6604 .get_drvinfo = netdev_get_drvinfo,
6605 .get_regs_len = netdev_get_regs_len,
6606 .get_regs = netdev_get_regs,
6607 .get_wol = netdev_get_wol,
6608 .set_wol = netdev_set_wol,
6609 .get_msglevel = netdev_get_msglevel,
6610 .set_msglevel = netdev_set_msglevel,
6611 .get_eeprom_len = netdev_get_eeprom_len,
6612 .get_eeprom = netdev_get_eeprom,
6613 .set_eeprom = netdev_set_eeprom,
6614 .get_pauseparam = netdev_get_pauseparam,
6615 .set_pauseparam = netdev_set_pauseparam,
6616 .get_ringparam = netdev_get_ringparam,
6617 .get_strings = netdev_get_strings,
6618 .get_sset_count = netdev_get_sset_count,
6619 .get_ethtool_stats = netdev_get_ethtool_stats,
6620 .get_link_ksettings = netdev_get_link_ksettings,
6621 .set_link_ksettings = netdev_set_link_ksettings,
6622};
6623
6624/*
6625 * Hardware monitoring
6626 */
6627
6628static void update_link(struct net_device *dev, struct dev_priv *priv,
6629 struct ksz_port *port)
6630{
6631 if (priv->media_state != port->linked->state) {
6632 priv->media_state = port->linked->state;
6633 if (netif_running(dev))
6634 set_media_state(dev, media_connected);
6635 }
6636}
6637
6638static void mib_read_work(struct work_struct *work)
6639{
6640 struct dev_info *hw_priv =
6641 container_of(work, struct dev_info, mib_read);
6642 struct ksz_hw *hw = &hw_priv->hw;
6643 struct ksz_port_mib *mib;
6644 int i;
6645
6646 next_jiffies = jiffies;
6647 for (i = 0; i < hw->mib_port_cnt; i++) {
6648 mib = &hw->port_mib[i];
6649
6650 /* Reading MIB counters or requested to read. */
6651 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6652
6653 /* Need to process receive interrupt. */
6654 if (port_r_cnt(hw, i))
6655 break;
6656 hw_priv->counter[i].read = 0;
6657
6658 /* Finish reading counters. */
6659 if (0 == mib->cnt_ptr) {
6660 hw_priv->counter[i].read = 2;
6661 wake_up_interruptible(
6662 &hw_priv->counter[i].counter);
6663 }
6664 } else if (time_after_eq(jiffies, hw_priv->counter[i].time)) {
6665 /* Only read MIB counters when the port is connected. */
6666 if (media_connected == mib->state)
6667 hw_priv->counter[i].read = 1;
6668 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6669 hw_priv->counter[i].time = next_jiffies;
6670
6671 /* Port is just disconnected. */
6672 } else if (mib->link_down) {
6673 mib->link_down = 0;
6674
6675 /* Read counters one last time after link is lost. */
6676 hw_priv->counter[i].read = 1;
6677 }
6678 }
6679}
6680
6681static void mib_monitor(struct timer_list *t)
6682{
6683 struct dev_info *hw_priv = from_timer(hw_priv, t, mib_timer_info.timer);
6684
6685 mib_read_work(&hw_priv->mib_read);
6686
6687 /* This is used to verify Wake-on-LAN is working. */
6688 if (hw_priv->pme_wait) {
6689 if (time_is_before_eq_jiffies(hw_priv->pme_wait)) {
6690 hw_clr_wol_pme_status(&hw_priv->hw);
6691 hw_priv->pme_wait = 0;
6692 }
6693 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6694
6695 /* PME is asserted. Wait 2 seconds to clear it. */
6696 hw_priv->pme_wait = jiffies + HZ * 2;
6697 }
6698
6699 ksz_update_timer(&hw_priv->mib_timer_info);
6700}
6701
6702/**
6703 * dev_monitor - periodic monitoring
6704 * @ptr: Network device pointer.
6705 *
6706 * This routine is run in a kernel timer to monitor the network device.
6707 */
6708static void dev_monitor(struct timer_list *t)
6709{
6710 struct dev_priv *priv = from_timer(priv, t, monitor_timer_info.timer);
6711 struct net_device *dev = priv->mii_if.dev;
6712 struct dev_info *hw_priv = priv->adapter;
6713 struct ksz_hw *hw = &hw_priv->hw;
6714 struct ksz_port *port = &priv->port;
6715
6716 if (!(hw->features & LINK_INT_WORKING))
6717 port_get_link_speed(port);
6718 update_link(dev, priv, port);
6719
6720 ksz_update_timer(&priv->monitor_timer_info);
6721}
6722
6723/*
6724 * Linux network device interface functions
6725 */
6726
6727/* Driver exported variables */
6728
6729static int msg_enable;
6730
6731static char *macaddr = ":";
6732static char *mac1addr = ":";
6733
6734/*
6735 * This enables multiple network device mode for KSZ8842, which contains a
6736 * switch with two physical ports. Some users like to take control of the
6737 * ports for running Spanning Tree Protocol. The driver will create an
6738 * additional eth? device for the other port.
6739 *
6740 * Some limitations are the network devices cannot have different MTU and
6741 * multicast hash tables.
6742 */
6743static int multi_dev;
6744
6745/*
6746 * As most users select multiple network device mode to use Spanning Tree
6747 * Protocol, this enables a feature in which most unicast and multicast packets
6748 * are forwarded inside the switch and not passed to the host. Only packets
6749 * that need the host's attention are passed to it. This prevents the host
6750 * wasting CPU time to examine each and every incoming packets and do the
6751 * forwarding itself.
6752 *
6753 * As the hack requires the private bridge header, the driver cannot compile
6754 * with just the kernel headers.
6755 *
6756 * Enabling STP support also turns on multiple network device mode.
6757 */
6758static int stp;
6759
6760/*
6761 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6762 * needs that. However, fast aging is used to flush the dynamic MAC table when
6763 * STP support is enabled.
6764 */
6765static int fast_aging;
6766
6767/**
6768 * netdev_init - initialize network device.
6769 * @dev: Network device.
6770 *
6771 * This function initializes the network device.
6772 *
6773 * Return 0 if successful; otherwise an error code indicating failure.
6774 */
6775static int __init netdev_init(struct net_device *dev)
6776{
6777 struct dev_priv *priv = netdev_priv(dev);
6778
6779 /* 500 ms timeout */
6780 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6781 dev_monitor);
6782
6783 /* 500 ms timeout */
6784 dev->watchdog_timeo = HZ / 2;
6785
6786 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_RXCSUM;
6787
6788 /*
6789 * Hardware does not really support IPv6 checksum generation, but
6790 * driver actually runs faster with this on.
6791 */
6792 dev->hw_features |= NETIF_F_IPV6_CSUM;
6793
6794 dev->features |= dev->hw_features;
6795
6796 sema_init(&priv->proc_sem, 1);
6797
6798 priv->mii_if.phy_id_mask = 0x1;
6799 priv->mii_if.reg_num_mask = 0x7;
6800 priv->mii_if.dev = dev;
6801 priv->mii_if.mdio_read = mdio_read;
6802 priv->mii_if.mdio_write = mdio_write;
6803 priv->mii_if.phy_id = priv->port.first_port + 1;
6804
6805 priv->msg_enable = netif_msg_init(msg_enable,
6806 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6807
6808 return 0;
6809}
6810
6811static const struct net_device_ops netdev_ops = {
6812 .ndo_init = netdev_init,
6813 .ndo_open = netdev_open,
6814 .ndo_stop = netdev_close,
6815 .ndo_get_stats = netdev_query_statistics,
6816 .ndo_start_xmit = netdev_tx,
6817 .ndo_tx_timeout = netdev_tx_timeout,
6818 .ndo_change_mtu = netdev_change_mtu,
6819 .ndo_set_features = netdev_set_features,
6820 .ndo_set_mac_address = netdev_set_mac_address,
6821 .ndo_validate_addr = eth_validate_addr,
6822 .ndo_do_ioctl = netdev_ioctl,
6823 .ndo_set_rx_mode = netdev_set_rx_mode,
6824#ifdef CONFIG_NET_POLL_CONTROLLER
6825 .ndo_poll_controller = netdev_netpoll,
6826#endif
6827};
6828
6829static void netdev_free(struct net_device *dev)
6830{
6831 if (dev->watchdog_timeo)
6832 unregister_netdev(dev);
6833
6834 free_netdev(dev);
6835}
6836
6837struct platform_info {
6838 struct dev_info dev_info;
6839 struct net_device *netdev[SWITCH_PORT_NUM];
6840};
6841
6842static int net_device_present;
6843
6844static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6845{
6846 int i;
6847 int j;
6848 int got_num;
6849 int num;
6850
6851 i = j = num = got_num = 0;
6852 while (j < ETH_ALEN) {
6853 if (macaddr[i]) {
6854 int digit;
6855
6856 got_num = 1;
6857 digit = hex_to_bin(macaddr[i]);
6858 if (digit >= 0)
6859 num = num * 16 + digit;
6860 else if (':' == macaddr[i])
6861 got_num = 2;
6862 else
6863 break;
6864 } else if (got_num)
6865 got_num = 2;
6866 else
6867 break;
6868 if (2 == got_num) {
6869 if (MAIN_PORT == port) {
6870 hw_priv->hw.override_addr[j++] = (u8) num;
6871 hw_priv->hw.override_addr[5] +=
6872 hw_priv->hw.id;
6873 } else {
6874 hw_priv->hw.ksz_switch->other_addr[j++] =
6875 (u8) num;
6876 hw_priv->hw.ksz_switch->other_addr[5] +=
6877 hw_priv->hw.id;
6878 }
6879 num = got_num = 0;
6880 }
6881 i++;
6882 }
6883 if (ETH_ALEN == j) {
6884 if (MAIN_PORT == port)
6885 hw_priv->hw.mac_override = 1;
6886 }
6887}
6888
6889#define KS884X_DMA_MASK (~0x0UL)
6890
6891static void read_other_addr(struct ksz_hw *hw)
6892{
6893 int i;
6894 u16 data[3];
6895 struct ksz_switch *sw = hw->ksz_switch;
6896
6897 for (i = 0; i < 3; i++)
6898 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6899 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6900 sw->other_addr[5] = (u8) data[0];
6901 sw->other_addr[4] = (u8)(data[0] >> 8);
6902 sw->other_addr[3] = (u8) data[1];
6903 sw->other_addr[2] = (u8)(data[1] >> 8);
6904 sw->other_addr[1] = (u8) data[2];
6905 sw->other_addr[0] = (u8)(data[2] >> 8);
6906 }
6907}
6908
6909#ifndef PCI_VENDOR_ID_MICREL_KS
6910#define PCI_VENDOR_ID_MICREL_KS 0x16c6
6911#endif
6912
6913static int pcidev_init(struct pci_dev *pdev, const struct pci_device_id *id)
6914{
6915 struct net_device *dev;
6916 struct dev_priv *priv;
6917 struct dev_info *hw_priv;
6918 struct ksz_hw *hw;
6919 struct platform_info *info;
6920 struct ksz_port *port;
6921 unsigned long reg_base;
6922 unsigned long reg_len;
6923 int cnt;
6924 int i;
6925 int mib_port_count;
6926 int pi;
6927 int port_count;
6928 int result;
6929 char banner[sizeof(version)];
6930 struct ksz_switch *sw = NULL;
6931
6932 result = pci_enable_device(pdev);
6933 if (result)
6934 return result;
6935
6936 result = -ENODEV;
6937
6938 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
6939 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
6940 return result;
6941
6942 reg_base = pci_resource_start(pdev, 0);
6943 reg_len = pci_resource_len(pdev, 0);
6944 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
6945 return result;
6946
6947 if (!request_mem_region(reg_base, reg_len, DRV_NAME))
6948 return result;
6949 pci_set_master(pdev);
6950
6951 result = -ENOMEM;
6952
6953 info = kzalloc(sizeof(struct platform_info), GFP_KERNEL);
6954 if (!info)
6955 goto pcidev_init_dev_err;
6956
6957 hw_priv = &info->dev_info;
6958 hw_priv->pdev = pdev;
6959
6960 hw = &hw_priv->hw;
6961
6962 hw->io = ioremap(reg_base, reg_len);
6963 if (!hw->io)
6964 goto pcidev_init_io_err;
6965
6966 cnt = hw_init(hw);
6967 if (!cnt) {
6968 if (msg_enable & NETIF_MSG_PROBE)
6969 pr_alert("chip not detected\n");
6970 result = -ENODEV;
6971 goto pcidev_init_alloc_err;
6972 }
6973
6974 snprintf(banner, sizeof(banner), "%s", version);
6975 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */
6976 dev_info(&hw_priv->pdev->dev, "%s\n", banner);
6977 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
6978
6979 /* Assume device is KSZ8841. */
6980 hw->dev_count = 1;
6981 port_count = 1;
6982 mib_port_count = 1;
6983 hw->addr_list_size = 0;
6984 hw->mib_cnt = PORT_COUNTER_NUM;
6985 hw->mib_port_cnt = 1;
6986
6987 /* KSZ8842 has a switch with multiple ports. */
6988 if (2 == cnt) {
6989 if (fast_aging)
6990 hw->overrides |= FAST_AGING;
6991
6992 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
6993
6994 /* Multiple network device interfaces are required. */
6995 if (multi_dev) {
6996 hw->dev_count = SWITCH_PORT_NUM;
6997 hw->addr_list_size = SWITCH_PORT_NUM - 1;
6998 }
6999
7000 /* Single network device has multiple ports. */
7001 if (1 == hw->dev_count) {
7002 port_count = SWITCH_PORT_NUM;
7003 mib_port_count = SWITCH_PORT_NUM;
7004 }
7005 hw->mib_port_cnt = TOTAL_PORT_NUM;
7006 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL);
7007 if (!hw->ksz_switch)
7008 goto pcidev_init_alloc_err;
7009
7010 sw = hw->ksz_switch;
7011 }
7012 for (i = 0; i < hw->mib_port_cnt; i++)
7013 hw->port_mib[i].mib_start = 0;
7014
7015 hw->parent = hw_priv;
7016
7017 /* Default MTU is 1500. */
7018 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
7019
7020 if (ksz_alloc_mem(hw_priv))
7021 goto pcidev_init_mem_err;
7022
7023 hw_priv->hw.id = net_device_present;
7024
7025 spin_lock_init(&hw_priv->hwlock);
7026 mutex_init(&hw_priv->lock);
7027
7028 for (i = 0; i < TOTAL_PORT_NUM; i++)
7029 init_waitqueue_head(&hw_priv->counter[i].counter);
7030
7031 if (macaddr[0] != ':')
7032 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
7033
7034 /* Read MAC address and initialize override address if not overridden. */
7035 hw_read_addr(hw);
7036
7037 /* Multiple device interfaces mode requires a second MAC address. */
7038 if (hw->dev_count > 1) {
7039 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN);
7040 read_other_addr(hw);
7041 if (mac1addr[0] != ':')
7042 get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
7043 }
7044
7045 hw_setup(hw);
7046 if (hw->ksz_switch)
7047 sw_setup(hw);
7048 else {
7049 hw_priv->wol_support = WOL_SUPPORT;
7050 hw_priv->wol_enable = 0;
7051 }
7052
7053 INIT_WORK(&hw_priv->mib_read, mib_read_work);
7054
7055 /* 500 ms timeout */
7056 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
7057 mib_monitor);
7058
7059 for (i = 0; i < hw->dev_count; i++) {
7060 dev = alloc_etherdev(sizeof(struct dev_priv));
7061 if (!dev)
7062 goto pcidev_init_reg_err;
7063 SET_NETDEV_DEV(dev, &pdev->dev);
7064 info->netdev[i] = dev;
7065
7066 priv = netdev_priv(dev);
7067 priv->adapter = hw_priv;
7068 priv->id = net_device_present++;
7069
7070 port = &priv->port;
7071 port->port_cnt = port_count;
7072 port->mib_port_cnt = mib_port_count;
7073 port->first_port = i;
7074 port->flow_ctrl = PHY_FLOW_CTRL;
7075
7076 port->hw = hw;
7077 port->linked = &hw->port_info[port->first_port];
7078
7079 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
7080 hw->port_info[pi].port_id = pi;
7081 hw->port_info[pi].pdev = dev;
7082 hw->port_info[pi].state = media_disconnected;
7083 }
7084
7085 dev->mem_start = (unsigned long) hw->io;
7086 dev->mem_end = dev->mem_start + reg_len - 1;
7087 dev->irq = pdev->irq;
7088 if (MAIN_PORT == i)
7089 memcpy(dev->dev_addr, hw_priv->hw.override_addr,
7090 ETH_ALEN);
7091 else {
7092 memcpy(dev->dev_addr, sw->other_addr, ETH_ALEN);
7093 if (ether_addr_equal(sw->other_addr, hw->override_addr))
7094 dev->dev_addr[5] += port->first_port;
7095 }
7096
7097 dev->netdev_ops = &netdev_ops;
7098 dev->ethtool_ops = &netdev_ethtool_ops;
7099
7100 /* MTU range: 60 - 1894 */
7101 dev->min_mtu = ETH_ZLEN;
7102 dev->max_mtu = MAX_RX_BUF_SIZE -
7103 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7104
7105 if (register_netdev(dev))
7106 goto pcidev_init_reg_err;
7107 port_set_power_saving(port, true);
7108 }
7109
7110 pci_dev_get(hw_priv->pdev);
7111 pci_set_drvdata(pdev, info);
7112 return 0;
7113
7114pcidev_init_reg_err:
7115 for (i = 0; i < hw->dev_count; i++) {
7116 if (info->netdev[i]) {
7117 netdev_free(info->netdev[i]);
7118 info->netdev[i] = NULL;
7119 }
7120 }
7121
7122pcidev_init_mem_err:
7123 ksz_free_mem(hw_priv);
7124 kfree(hw->ksz_switch);
7125
7126pcidev_init_alloc_err:
7127 iounmap(hw->io);
7128
7129pcidev_init_io_err:
7130 kfree(info);
7131
7132pcidev_init_dev_err:
7133 release_mem_region(reg_base, reg_len);
7134
7135 return result;
7136}
7137
7138static void pcidev_exit(struct pci_dev *pdev)
7139{
7140 int i;
7141 struct platform_info *info = pci_get_drvdata(pdev);
7142 struct dev_info *hw_priv = &info->dev_info;
7143
7144 release_mem_region(pci_resource_start(pdev, 0),
7145 pci_resource_len(pdev, 0));
7146 for (i = 0; i < hw_priv->hw.dev_count; i++) {
7147 if (info->netdev[i])
7148 netdev_free(info->netdev[i]);
7149 }
7150 if (hw_priv->hw.io)
7151 iounmap(hw_priv->hw.io);
7152 ksz_free_mem(hw_priv);
7153 kfree(hw_priv->hw.ksz_switch);
7154 pci_dev_put(hw_priv->pdev);
7155 kfree(info);
7156}
7157
7158#ifdef CONFIG_PM
7159static int pcidev_resume(struct pci_dev *pdev)
7160{
7161 int i;
7162 struct platform_info *info = pci_get_drvdata(pdev);
7163 struct dev_info *hw_priv = &info->dev_info;
7164 struct ksz_hw *hw = &hw_priv->hw;
7165
7166 pci_set_power_state(pdev, PCI_D0);
7167 pci_restore_state(pdev);
7168 pci_enable_wake(pdev, PCI_D0, 0);
7169
7170 if (hw_priv->wol_enable)
7171 hw_cfg_wol_pme(hw, 0);
7172 for (i = 0; i < hw->dev_count; i++) {
7173 if (info->netdev[i]) {
7174 struct net_device *dev = info->netdev[i];
7175
7176 if (netif_running(dev)) {
7177 netdev_open(dev);
7178 netif_device_attach(dev);
7179 }
7180 }
7181 }
7182 return 0;
7183}
7184
7185static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state)
7186{
7187 int i;
7188 struct platform_info *info = pci_get_drvdata(pdev);
7189 struct dev_info *hw_priv = &info->dev_info;
7190 struct ksz_hw *hw = &hw_priv->hw;
7191
7192 /* Need to find a way to retrieve the device IP address. */
7193 static const u8 net_addr[] = { 192, 168, 1, 1 };
7194
7195 for (i = 0; i < hw->dev_count; i++) {
7196 if (info->netdev[i]) {
7197 struct net_device *dev = info->netdev[i];
7198
7199 if (netif_running(dev)) {
7200 netif_device_detach(dev);
7201 netdev_close(dev);
7202 }
7203 }
7204 }
7205 if (hw_priv->wol_enable) {
7206 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
7207 hw_cfg_wol_pme(hw, 1);
7208 }
7209
7210 pci_save_state(pdev);
7211 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
7212 pci_set_power_state(pdev, pci_choose_state(pdev, state));
7213 return 0;
7214}
7215#endif
7216
7217static char pcidev_name[] = "ksz884xp";
7218
7219static const struct pci_device_id pcidev_table[] = {
7220 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
7221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7222 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
7223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7224 { 0 }
7225};
7226
7227MODULE_DEVICE_TABLE(pci, pcidev_table);
7228
7229static struct pci_driver pci_device_driver = {
7230#ifdef CONFIG_PM
7231 .suspend = pcidev_suspend,
7232 .resume = pcidev_resume,
7233#endif
7234 .name = pcidev_name,
7235 .id_table = pcidev_table,
7236 .probe = pcidev_init,
7237 .remove = pcidev_exit
7238};
7239
7240module_pci_driver(pci_device_driver);
7241
7242MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
7243MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
7244MODULE_LICENSE("GPL");
7245
7246module_param_named(message, msg_enable, int, 0);
7247MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
7248
7249module_param(macaddr, charp, 0);
7250module_param(mac1addr, charp, 0);
7251module_param(fast_aging, int, 0);
7252module_param(multi_dev, int, 0);
7253module_param(stp, int, 0);
7254MODULE_PARM_DESC(macaddr, "MAC address");
7255MODULE_PARM_DESC(mac1addr, "Second MAC address");
7256MODULE_PARM_DESC(fast_aging, "Fast aging");
7257MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
7258MODULE_PARM_DESC(stp, "STP support");