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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
4 *
5 * Copyright (c) 2009-2010 Micrel, Inc.
6 * Tristram Ha <Tristram.Ha@micrel.com>
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/ioport.h>
16#include <linux/pci.h>
17#include <linux/proc_fs.h>
18#include <linux/mii.h>
19#include <linux/platform_device.h>
20#include <linux/ethtool.h>
21#include <linux/etherdevice.h>
22#include <linux/in.h>
23#include <linux/ip.h>
24#include <linux/if_vlan.h>
25#include <linux/crc32.h>
26#include <linux/sched.h>
27#include <linux/slab.h>
28#include <linux/micrel_phy.h>
29
30
31/* DMA Registers */
32
33#define KS_DMA_TX_CTRL 0x0000
34#define DMA_TX_ENABLE 0x00000001
35#define DMA_TX_CRC_ENABLE 0x00000002
36#define DMA_TX_PAD_ENABLE 0x00000004
37#define DMA_TX_LOOPBACK 0x00000100
38#define DMA_TX_FLOW_ENABLE 0x00000200
39#define DMA_TX_CSUM_IP 0x00010000
40#define DMA_TX_CSUM_TCP 0x00020000
41#define DMA_TX_CSUM_UDP 0x00040000
42#define DMA_TX_BURST_SIZE 0x3F000000
43
44#define KS_DMA_RX_CTRL 0x0004
45#define DMA_RX_ENABLE 0x00000001
46#define KS884X_DMA_RX_MULTICAST 0x00000002
47#define DMA_RX_PROMISCUOUS 0x00000004
48#define DMA_RX_ERROR 0x00000008
49#define DMA_RX_UNICAST 0x00000010
50#define DMA_RX_ALL_MULTICAST 0x00000020
51#define DMA_RX_BROADCAST 0x00000040
52#define DMA_RX_FLOW_ENABLE 0x00000200
53#define DMA_RX_CSUM_IP 0x00010000
54#define DMA_RX_CSUM_TCP 0x00020000
55#define DMA_RX_CSUM_UDP 0x00040000
56#define DMA_RX_BURST_SIZE 0x3F000000
57
58#define DMA_BURST_SHIFT 24
59#define DMA_BURST_DEFAULT 8
60
61#define KS_DMA_TX_START 0x0008
62#define KS_DMA_RX_START 0x000C
63#define DMA_START 0x00000001
64
65#define KS_DMA_TX_ADDR 0x0010
66#define KS_DMA_RX_ADDR 0x0014
67
68#define DMA_ADDR_LIST_MASK 0xFFFFFFFC
69#define DMA_ADDR_LIST_SHIFT 2
70
71/* MTR0 */
72#define KS884X_MULTICAST_0_OFFSET 0x0020
73#define KS884X_MULTICAST_1_OFFSET 0x0021
74#define KS884X_MULTICAST_2_OFFSET 0x0022
75#define KS884x_MULTICAST_3_OFFSET 0x0023
76/* MTR1 */
77#define KS884X_MULTICAST_4_OFFSET 0x0024
78#define KS884X_MULTICAST_5_OFFSET 0x0025
79#define KS884X_MULTICAST_6_OFFSET 0x0026
80#define KS884X_MULTICAST_7_OFFSET 0x0027
81
82/* Interrupt Registers */
83
84/* INTEN */
85#define KS884X_INTERRUPTS_ENABLE 0x0028
86/* INTST */
87#define KS884X_INTERRUPTS_STATUS 0x002C
88
89#define KS884X_INT_RX_STOPPED 0x02000000
90#define KS884X_INT_TX_STOPPED 0x04000000
91#define KS884X_INT_RX_OVERRUN 0x08000000
92#define KS884X_INT_TX_EMPTY 0x10000000
93#define KS884X_INT_RX 0x20000000
94#define KS884X_INT_TX 0x40000000
95#define KS884X_INT_PHY 0x80000000
96
97#define KS884X_INT_RX_MASK \
98 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
99#define KS884X_INT_TX_MASK \
100 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
101#define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
102
103/* MAC Additional Station Address */
104
105/* MAAL0 */
106#define KS_ADD_ADDR_0_LO 0x0080
107/* MAAH0 */
108#define KS_ADD_ADDR_0_HI 0x0084
109/* MAAL1 */
110#define KS_ADD_ADDR_1_LO 0x0088
111/* MAAH1 */
112#define KS_ADD_ADDR_1_HI 0x008C
113/* MAAL2 */
114#define KS_ADD_ADDR_2_LO 0x0090
115/* MAAH2 */
116#define KS_ADD_ADDR_2_HI 0x0094
117/* MAAL3 */
118#define KS_ADD_ADDR_3_LO 0x0098
119/* MAAH3 */
120#define KS_ADD_ADDR_3_HI 0x009C
121/* MAAL4 */
122#define KS_ADD_ADDR_4_LO 0x00A0
123/* MAAH4 */
124#define KS_ADD_ADDR_4_HI 0x00A4
125/* MAAL5 */
126#define KS_ADD_ADDR_5_LO 0x00A8
127/* MAAH5 */
128#define KS_ADD_ADDR_5_HI 0x00AC
129/* MAAL6 */
130#define KS_ADD_ADDR_6_LO 0x00B0
131/* MAAH6 */
132#define KS_ADD_ADDR_6_HI 0x00B4
133/* MAAL7 */
134#define KS_ADD_ADDR_7_LO 0x00B8
135/* MAAH7 */
136#define KS_ADD_ADDR_7_HI 0x00BC
137/* MAAL8 */
138#define KS_ADD_ADDR_8_LO 0x00C0
139/* MAAH8 */
140#define KS_ADD_ADDR_8_HI 0x00C4
141/* MAAL9 */
142#define KS_ADD_ADDR_9_LO 0x00C8
143/* MAAH9 */
144#define KS_ADD_ADDR_9_HI 0x00CC
145/* MAAL10 */
146#define KS_ADD_ADDR_A_LO 0x00D0
147/* MAAH10 */
148#define KS_ADD_ADDR_A_HI 0x00D4
149/* MAAL11 */
150#define KS_ADD_ADDR_B_LO 0x00D8
151/* MAAH11 */
152#define KS_ADD_ADDR_B_HI 0x00DC
153/* MAAL12 */
154#define KS_ADD_ADDR_C_LO 0x00E0
155/* MAAH12 */
156#define KS_ADD_ADDR_C_HI 0x00E4
157/* MAAL13 */
158#define KS_ADD_ADDR_D_LO 0x00E8
159/* MAAH13 */
160#define KS_ADD_ADDR_D_HI 0x00EC
161/* MAAL14 */
162#define KS_ADD_ADDR_E_LO 0x00F0
163/* MAAH14 */
164#define KS_ADD_ADDR_E_HI 0x00F4
165/* MAAL15 */
166#define KS_ADD_ADDR_F_LO 0x00F8
167/* MAAH15 */
168#define KS_ADD_ADDR_F_HI 0x00FC
169
170#define ADD_ADDR_HI_MASK 0x0000FFFF
171#define ADD_ADDR_ENABLE 0x80000000
172#define ADD_ADDR_INCR 8
173
174/* Miscellaneous Registers */
175
176/* MARL */
177#define KS884X_ADDR_0_OFFSET 0x0200
178#define KS884X_ADDR_1_OFFSET 0x0201
179/* MARM */
180#define KS884X_ADDR_2_OFFSET 0x0202
181#define KS884X_ADDR_3_OFFSET 0x0203
182/* MARH */
183#define KS884X_ADDR_4_OFFSET 0x0204
184#define KS884X_ADDR_5_OFFSET 0x0205
185
186/* OBCR */
187#define KS884X_BUS_CTRL_OFFSET 0x0210
188
189#define BUS_SPEED_125_MHZ 0x0000
190#define BUS_SPEED_62_5_MHZ 0x0001
191#define BUS_SPEED_41_66_MHZ 0x0002
192#define BUS_SPEED_25_MHZ 0x0003
193
194/* EEPCR */
195#define KS884X_EEPROM_CTRL_OFFSET 0x0212
196
197#define EEPROM_CHIP_SELECT 0x0001
198#define EEPROM_SERIAL_CLOCK 0x0002
199#define EEPROM_DATA_OUT 0x0004
200#define EEPROM_DATA_IN 0x0008
201#define EEPROM_ACCESS_ENABLE 0x0010
202
203/* MBIR */
204#define KS884X_MEM_INFO_OFFSET 0x0214
205
206#define RX_MEM_TEST_FAILED 0x0008
207#define RX_MEM_TEST_FINISHED 0x0010
208#define TX_MEM_TEST_FAILED 0x0800
209#define TX_MEM_TEST_FINISHED 0x1000
210
211/* GCR */
212#define KS884X_GLOBAL_CTRL_OFFSET 0x0216
213#define GLOBAL_SOFTWARE_RESET 0x0001
214
215#define KS8841_POWER_MANAGE_OFFSET 0x0218
216
217/* WFCR */
218#define KS8841_WOL_CTRL_OFFSET 0x021A
219#define KS8841_WOL_MAGIC_ENABLE 0x0080
220#define KS8841_WOL_FRAME3_ENABLE 0x0008
221#define KS8841_WOL_FRAME2_ENABLE 0x0004
222#define KS8841_WOL_FRAME1_ENABLE 0x0002
223#define KS8841_WOL_FRAME0_ENABLE 0x0001
224
225/* WF0 */
226#define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
227#define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
228#define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
229
230/* IACR */
231#define KS884X_IACR_P 0x04A0
232#define KS884X_IACR_OFFSET KS884X_IACR_P
233
234/* IADR1 */
235#define KS884X_IADR1_P 0x04A2
236#define KS884X_IADR2_P 0x04A4
237#define KS884X_IADR3_P 0x04A6
238#define KS884X_IADR4_P 0x04A8
239#define KS884X_IADR5_P 0x04AA
240
241#define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
242#define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
243
244#define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
245#define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
246#define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
247#define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
248#define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
249#define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
250#define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
251#define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
252#define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
253
254/* P1MBCR */
255#define KS884X_P1MBCR_P 0x04D0
256#define KS884X_P1MBSR_P 0x04D2
257#define KS884X_PHY1ILR_P 0x04D4
258#define KS884X_PHY1IHR_P 0x04D6
259#define KS884X_P1ANAR_P 0x04D8
260#define KS884X_P1ANLPR_P 0x04DA
261
262/* P2MBCR */
263#define KS884X_P2MBCR_P 0x04E0
264#define KS884X_P2MBSR_P 0x04E2
265#define KS884X_PHY2ILR_P 0x04E4
266#define KS884X_PHY2IHR_P 0x04E6
267#define KS884X_P2ANAR_P 0x04E8
268#define KS884X_P2ANLPR_P 0x04EA
269
270#define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
271#define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
272
273#define KS884X_PHY_CTRL_OFFSET 0x00
274
275#define KS884X_PHY_STATUS_OFFSET 0x02
276
277#define KS884X_PHY_ID_1_OFFSET 0x04
278#define KS884X_PHY_ID_2_OFFSET 0x06
279
280#define KS884X_PHY_AUTO_NEG_OFFSET 0x08
281
282#define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
283
284/* P1VCT */
285#define KS884X_P1VCT_P 0x04F0
286#define KS884X_P1PHYCTRL_P 0x04F2
287
288/* P2VCT */
289#define KS884X_P2VCT_P 0x04F4
290#define KS884X_P2PHYCTRL_P 0x04F6
291
292#define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
293#define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
294
295#define KS884X_PHY_LINK_MD_OFFSET 0x00
296
297#define PHY_START_CABLE_DIAG 0x8000
298#define PHY_CABLE_DIAG_RESULT 0x6000
299#define PHY_CABLE_STAT_NORMAL 0x0000
300#define PHY_CABLE_STAT_OPEN 0x2000
301#define PHY_CABLE_STAT_SHORT 0x4000
302#define PHY_CABLE_STAT_FAILED 0x6000
303#define PHY_CABLE_10M_SHORT 0x1000
304#define PHY_CABLE_FAULT_COUNTER 0x01FF
305
306#define KS884X_PHY_PHY_CTRL_OFFSET 0x02
307
308#define PHY_STAT_REVERSED_POLARITY 0x0020
309#define PHY_STAT_MDIX 0x0010
310#define PHY_FORCE_LINK 0x0008
311#define PHY_POWER_SAVING_DISABLE 0x0004
312#define PHY_REMOTE_LOOPBACK 0x0002
313
314/* SIDER */
315#define KS884X_SIDER_P 0x0400
316#define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
317#define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
318
319#define REG_FAMILY_ID 0x88
320
321#define REG_CHIP_ID_41 0x8810
322#define REG_CHIP_ID_42 0x8800
323
324#define KS884X_CHIP_ID_MASK_41 0xFF10
325#define KS884X_CHIP_ID_MASK 0xFFF0
326#define KS884X_CHIP_ID_SHIFT 4
327#define KS884X_REVISION_MASK 0x000E
328#define KS884X_REVISION_SHIFT 1
329#define KS8842_START 0x0001
330
331#define CHIP_IP_41_M 0x8810
332#define CHIP_IP_42_M 0x8800
333#define CHIP_IP_61_M 0x8890
334#define CHIP_IP_62_M 0x8880
335
336#define CHIP_IP_41_P 0x8850
337#define CHIP_IP_42_P 0x8840
338#define CHIP_IP_61_P 0x88D0
339#define CHIP_IP_62_P 0x88C0
340
341/* SGCR1 */
342#define KS8842_SGCR1_P 0x0402
343#define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
344
345#define SWITCH_PASS_ALL 0x8000
346#define SWITCH_TX_FLOW_CTRL 0x2000
347#define SWITCH_RX_FLOW_CTRL 0x1000
348#define SWITCH_CHECK_LENGTH 0x0800
349#define SWITCH_AGING_ENABLE 0x0400
350#define SWITCH_FAST_AGING 0x0200
351#define SWITCH_AGGR_BACKOFF 0x0100
352#define SWITCH_PASS_PAUSE 0x0008
353#define SWITCH_LINK_AUTO_AGING 0x0001
354
355/* SGCR2 */
356#define KS8842_SGCR2_P 0x0404
357#define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
358
359#define SWITCH_VLAN_ENABLE 0x8000
360#define SWITCH_IGMP_SNOOP 0x4000
361#define IPV6_MLD_SNOOP_ENABLE 0x2000
362#define IPV6_MLD_SNOOP_OPTION 0x1000
363#define PRIORITY_SCHEME_SELECT 0x0800
364#define SWITCH_MIRROR_RX_TX 0x0100
365#define UNICAST_VLAN_BOUNDARY 0x0080
366#define MULTICAST_STORM_DISABLE 0x0040
367#define SWITCH_BACK_PRESSURE 0x0020
368#define FAIR_FLOW_CTRL 0x0010
369#define NO_EXC_COLLISION_DROP 0x0008
370#define SWITCH_HUGE_PACKET 0x0004
371#define SWITCH_LEGAL_PACKET 0x0002
372#define SWITCH_BUF_RESERVE 0x0001
373
374/* SGCR3 */
375#define KS8842_SGCR3_P 0x0406
376#define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
377
378#define BROADCAST_STORM_RATE_LO 0xFF00
379#define SWITCH_REPEATER 0x0080
380#define SWITCH_HALF_DUPLEX 0x0040
381#define SWITCH_FLOW_CTRL 0x0020
382#define SWITCH_10_MBIT 0x0010
383#define SWITCH_REPLACE_NULL_VID 0x0008
384#define BROADCAST_STORM_RATE_HI 0x0007
385
386#define BROADCAST_STORM_RATE 0x07FF
387
388/* SGCR4 */
389#define KS8842_SGCR4_P 0x0408
390
391/* SGCR5 */
392#define KS8842_SGCR5_P 0x040A
393#define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
394
395#define LED_MODE 0x8200
396#define LED_SPEED_DUPLEX_ACT 0x0000
397#define LED_SPEED_DUPLEX_LINK_ACT 0x8000
398#define LED_DUPLEX_10_100 0x0200
399
400/* SGCR6 */
401#define KS8842_SGCR6_P 0x0410
402#define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
403
404#define KS8842_PRIORITY_MASK 3
405#define KS8842_PRIORITY_SHIFT 2
406
407/* SGCR7 */
408#define KS8842_SGCR7_P 0x0412
409#define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
410
411#define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
412#define SWITCH_UNK_DEF_PORT_3 0x0004
413#define SWITCH_UNK_DEF_PORT_2 0x0002
414#define SWITCH_UNK_DEF_PORT_1 0x0001
415
416/* MACAR1 */
417#define KS8842_MACAR1_P 0x0470
418#define KS8842_MACAR2_P 0x0472
419#define KS8842_MACAR3_P 0x0474
420#define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
421#define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
422#define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
423#define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
424#define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
425#define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
426
427/* TOSR1 */
428#define KS8842_TOSR1_P 0x0480
429#define KS8842_TOSR2_P 0x0482
430#define KS8842_TOSR3_P 0x0484
431#define KS8842_TOSR4_P 0x0486
432#define KS8842_TOSR5_P 0x0488
433#define KS8842_TOSR6_P 0x048A
434#define KS8842_TOSR7_P 0x0490
435#define KS8842_TOSR8_P 0x0492
436#define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
437#define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
438#define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
439#define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
440#define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
441#define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
442
443#define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
444#define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
445
446/* P1CR1 */
447#define KS8842_P1CR1_P 0x0500
448#define KS8842_P1CR2_P 0x0502
449#define KS8842_P1VIDR_P 0x0504
450#define KS8842_P1CR3_P 0x0506
451#define KS8842_P1IRCR_P 0x0508
452#define KS8842_P1ERCR_P 0x050A
453#define KS884X_P1SCSLMD_P 0x0510
454#define KS884X_P1CR4_P 0x0512
455#define KS884X_P1SR_P 0x0514
456
457/* P2CR1 */
458#define KS8842_P2CR1_P 0x0520
459#define KS8842_P2CR2_P 0x0522
460#define KS8842_P2VIDR_P 0x0524
461#define KS8842_P2CR3_P 0x0526
462#define KS8842_P2IRCR_P 0x0528
463#define KS8842_P2ERCR_P 0x052A
464#define KS884X_P2SCSLMD_P 0x0530
465#define KS884X_P2CR4_P 0x0532
466#define KS884X_P2SR_P 0x0534
467
468/* P3CR1 */
469#define KS8842_P3CR1_P 0x0540
470#define KS8842_P3CR2_P 0x0542
471#define KS8842_P3VIDR_P 0x0544
472#define KS8842_P3CR3_P 0x0546
473#define KS8842_P3IRCR_P 0x0548
474#define KS8842_P3ERCR_P 0x054A
475
476#define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
477#define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
478#define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
479
480#define PORT_CTRL_ADDR(port, addr) \
481 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
482 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
483
484#define KS8842_PORT_CTRL_1_OFFSET 0x00
485
486#define PORT_BROADCAST_STORM 0x0080
487#define PORT_DIFFSERV_ENABLE 0x0040
488#define PORT_802_1P_ENABLE 0x0020
489#define PORT_BASED_PRIORITY_MASK 0x0018
490#define PORT_BASED_PRIORITY_BASE 0x0003
491#define PORT_BASED_PRIORITY_SHIFT 3
492#define PORT_BASED_PRIORITY_0 0x0000
493#define PORT_BASED_PRIORITY_1 0x0008
494#define PORT_BASED_PRIORITY_2 0x0010
495#define PORT_BASED_PRIORITY_3 0x0018
496#define PORT_INSERT_TAG 0x0004
497#define PORT_REMOVE_TAG 0x0002
498#define PORT_PRIO_QUEUE_ENABLE 0x0001
499
500#define KS8842_PORT_CTRL_2_OFFSET 0x02
501
502#define PORT_INGRESS_VLAN_FILTER 0x4000
503#define PORT_DISCARD_NON_VID 0x2000
504#define PORT_FORCE_FLOW_CTRL 0x1000
505#define PORT_BACK_PRESSURE 0x0800
506#define PORT_TX_ENABLE 0x0400
507#define PORT_RX_ENABLE 0x0200
508#define PORT_LEARN_DISABLE 0x0100
509#define PORT_MIRROR_SNIFFER 0x0080
510#define PORT_MIRROR_RX 0x0040
511#define PORT_MIRROR_TX 0x0020
512#define PORT_USER_PRIORITY_CEILING 0x0008
513#define PORT_VLAN_MEMBERSHIP 0x0007
514
515#define KS8842_PORT_CTRL_VID_OFFSET 0x04
516
517#define PORT_DEFAULT_VID 0x0001
518
519#define KS8842_PORT_CTRL_3_OFFSET 0x06
520
521#define PORT_INGRESS_LIMIT_MODE 0x000C
522#define PORT_INGRESS_ALL 0x0000
523#define PORT_INGRESS_UNICAST 0x0004
524#define PORT_INGRESS_MULTICAST 0x0008
525#define PORT_INGRESS_BROADCAST 0x000C
526#define PORT_COUNT_IFG 0x0002
527#define PORT_COUNT_PREAMBLE 0x0001
528
529#define KS8842_PORT_IN_RATE_OFFSET 0x08
530#define KS8842_PORT_OUT_RATE_OFFSET 0x0A
531
532#define PORT_PRIORITY_RATE 0x0F
533#define PORT_PRIORITY_RATE_SHIFT 4
534
535#define KS884X_PORT_LINK_MD 0x10
536
537#define PORT_CABLE_10M_SHORT 0x8000
538#define PORT_CABLE_DIAG_RESULT 0x6000
539#define PORT_CABLE_STAT_NORMAL 0x0000
540#define PORT_CABLE_STAT_OPEN 0x2000
541#define PORT_CABLE_STAT_SHORT 0x4000
542#define PORT_CABLE_STAT_FAILED 0x6000
543#define PORT_START_CABLE_DIAG 0x1000
544#define PORT_FORCE_LINK 0x0800
545#define PORT_POWER_SAVING_DISABLE 0x0400
546#define PORT_PHY_REMOTE_LOOPBACK 0x0200
547#define PORT_CABLE_FAULT_COUNTER 0x01FF
548
549#define KS884X_PORT_CTRL_4_OFFSET 0x12
550
551#define PORT_LED_OFF 0x8000
552#define PORT_TX_DISABLE 0x4000
553#define PORT_AUTO_NEG_RESTART 0x2000
554#define PORT_REMOTE_FAULT_DISABLE 0x1000
555#define PORT_POWER_DOWN 0x0800
556#define PORT_AUTO_MDIX_DISABLE 0x0400
557#define PORT_FORCE_MDIX 0x0200
558#define PORT_LOOPBACK 0x0100
559#define PORT_AUTO_NEG_ENABLE 0x0080
560#define PORT_FORCE_100_MBIT 0x0040
561#define PORT_FORCE_FULL_DUPLEX 0x0020
562#define PORT_AUTO_NEG_SYM_PAUSE 0x0010
563#define PORT_AUTO_NEG_100BTX_FD 0x0008
564#define PORT_AUTO_NEG_100BTX 0x0004
565#define PORT_AUTO_NEG_10BT_FD 0x0002
566#define PORT_AUTO_NEG_10BT 0x0001
567
568#define KS884X_PORT_STATUS_OFFSET 0x14
569
570#define PORT_HP_MDIX 0x8000
571#define PORT_REVERSED_POLARITY 0x2000
572#define PORT_RX_FLOW_CTRL 0x0800
573#define PORT_TX_FLOW_CTRL 0x1000
574#define PORT_STATUS_SPEED_100MBIT 0x0400
575#define PORT_STATUS_FULL_DUPLEX 0x0200
576#define PORT_REMOTE_FAULT 0x0100
577#define PORT_MDIX_STATUS 0x0080
578#define PORT_AUTO_NEG_COMPLETE 0x0040
579#define PORT_STATUS_LINK_GOOD 0x0020
580#define PORT_REMOTE_SYM_PAUSE 0x0010
581#define PORT_REMOTE_100BTX_FD 0x0008
582#define PORT_REMOTE_100BTX 0x0004
583#define PORT_REMOTE_10BT_FD 0x0002
584#define PORT_REMOTE_10BT 0x0001
585
586/*
587#define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
588#define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
589#define STATIC_MAC_TABLE_VALID 00-00080000-00000000
590#define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
591#define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
592#define STATIC_MAC_TABLE_FID 00-03C00000-00000000
593*/
594
595#define STATIC_MAC_TABLE_ADDR 0x0000FFFF
596#define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
597#define STATIC_MAC_TABLE_VALID 0x00080000
598#define STATIC_MAC_TABLE_OVERRIDE 0x00100000
599#define STATIC_MAC_TABLE_USE_FID 0x00200000
600#define STATIC_MAC_TABLE_FID 0x03C00000
601
602#define STATIC_MAC_FWD_PORTS_SHIFT 16
603#define STATIC_MAC_FID_SHIFT 22
604
605/*
606#define VLAN_TABLE_VID 00-00000000-00000FFF
607#define VLAN_TABLE_FID 00-00000000-0000F000
608#define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
609#define VLAN_TABLE_VALID 00-00000000-00080000
610*/
611
612#define VLAN_TABLE_VID 0x00000FFF
613#define VLAN_TABLE_FID 0x0000F000
614#define VLAN_TABLE_MEMBERSHIP 0x00070000
615#define VLAN_TABLE_VALID 0x00080000
616
617#define VLAN_TABLE_FID_SHIFT 12
618#define VLAN_TABLE_MEMBERSHIP_SHIFT 16
619
620/*
621#define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
622#define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
623#define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
624#define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
625#define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
626#define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
627#define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
628#define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
629*/
630
631#define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
632#define DYNAMIC_MAC_TABLE_FID 0x000F0000
633#define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
634#define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
635#define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
636
637#define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
638#define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
639#define DYNAMIC_MAC_TABLE_RESERVED 0x78
640#define DYNAMIC_MAC_TABLE_NOT_READY 0x80
641
642#define DYNAMIC_MAC_FID_SHIFT 16
643#define DYNAMIC_MAC_SRC_PORT_SHIFT 20
644#define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
645#define DYNAMIC_MAC_ENTRIES_SHIFT 24
646#define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
647
648/*
649#define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
650#define MIB_COUNTER_VALID 00-00000000-40000000
651#define MIB_COUNTER_OVERFLOW 00-00000000-80000000
652*/
653
654#define MIB_COUNTER_VALUE 0x3FFFFFFF
655#define MIB_COUNTER_VALID 0x40000000
656#define MIB_COUNTER_OVERFLOW 0x80000000
657
658#define MIB_PACKET_DROPPED 0x0000FFFF
659
660#define KS_MIB_PACKET_DROPPED_TX_0 0x100
661#define KS_MIB_PACKET_DROPPED_TX_1 0x101
662#define KS_MIB_PACKET_DROPPED_TX 0x102
663#define KS_MIB_PACKET_DROPPED_RX_0 0x103
664#define KS_MIB_PACKET_DROPPED_RX_1 0x104
665#define KS_MIB_PACKET_DROPPED_RX 0x105
666
667/* Change default LED mode. */
668#define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
669
670#define MAC_ADDR_ORDER(i) (ETH_ALEN - 1 - (i))
671
672#define MAX_ETHERNET_BODY_SIZE 1500
673#define ETHERNET_HEADER_SIZE (14 + VLAN_HLEN)
674
675#define MAX_ETHERNET_PACKET_SIZE \
676 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
677
678#define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
679#define MAX_RX_BUF_SIZE (1912 + 4)
680
681#define ADDITIONAL_ENTRIES 16
682#define MAX_MULTICAST_LIST 32
683
684#define HW_MULTICAST_SIZE 8
685
686#define HW_TO_DEV_PORT(port) (port - 1)
687
688enum {
689 media_connected,
690 media_disconnected
691};
692
693enum {
694 OID_COUNTER_UNKOWN,
695
696 OID_COUNTER_FIRST,
697
698 /* total transmit errors */
699 OID_COUNTER_XMIT_ERROR,
700
701 /* total receive errors */
702 OID_COUNTER_RCV_ERROR,
703
704 OID_COUNTER_LAST
705};
706
707/*
708 * Hardware descriptor definitions
709 */
710
711#define DESC_ALIGNMENT 16
712#define BUFFER_ALIGNMENT 8
713
714#define NUM_OF_RX_DESC 64
715#define NUM_OF_TX_DESC 64
716
717#define KS_DESC_RX_FRAME_LEN 0x000007FF
718#define KS_DESC_RX_FRAME_TYPE 0x00008000
719#define KS_DESC_RX_ERROR_CRC 0x00010000
720#define KS_DESC_RX_ERROR_RUNT 0x00020000
721#define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
722#define KS_DESC_RX_ERROR_PHY 0x00080000
723#define KS884X_DESC_RX_PORT_MASK 0x00300000
724#define KS_DESC_RX_MULTICAST 0x01000000
725#define KS_DESC_RX_ERROR 0x02000000
726#define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
727#define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
728#define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
729#define KS_DESC_RX_LAST 0x20000000
730#define KS_DESC_RX_FIRST 0x40000000
731#define KS_DESC_RX_ERROR_COND \
732 (KS_DESC_RX_ERROR_CRC | \
733 KS_DESC_RX_ERROR_RUNT | \
734 KS_DESC_RX_ERROR_PHY | \
735 KS_DESC_RX_ERROR_TOO_LONG)
736
737#define KS_DESC_HW_OWNED 0x80000000
738
739#define KS_DESC_BUF_SIZE 0x000007FF
740#define KS884X_DESC_TX_PORT_MASK 0x00300000
741#define KS_DESC_END_OF_RING 0x02000000
742#define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
743#define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
744#define KS_DESC_TX_CSUM_GEN_IP 0x10000000
745#define KS_DESC_TX_LAST 0x20000000
746#define KS_DESC_TX_FIRST 0x40000000
747#define KS_DESC_TX_INTERRUPT 0x80000000
748
749#define KS_DESC_PORT_SHIFT 20
750
751#define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
752
753#define KS_DESC_TX_MASK \
754 (KS_DESC_TX_INTERRUPT | \
755 KS_DESC_TX_FIRST | \
756 KS_DESC_TX_LAST | \
757 KS_DESC_TX_CSUM_GEN_IP | \
758 KS_DESC_TX_CSUM_GEN_TCP | \
759 KS_DESC_TX_CSUM_GEN_UDP | \
760 KS_DESC_BUF_SIZE)
761
762struct ksz_desc_rx_stat {
763#ifdef __BIG_ENDIAN_BITFIELD
764 u32 hw_owned:1;
765 u32 first_desc:1;
766 u32 last_desc:1;
767 u32 csum_err_ip:1;
768 u32 csum_err_tcp:1;
769 u32 csum_err_udp:1;
770 u32 error:1;
771 u32 multicast:1;
772 u32 src_port:4;
773 u32 err_phy:1;
774 u32 err_too_long:1;
775 u32 err_runt:1;
776 u32 err_crc:1;
777 u32 frame_type:1;
778 u32 reserved1:4;
779 u32 frame_len:11;
780#else
781 u32 frame_len:11;
782 u32 reserved1:4;
783 u32 frame_type:1;
784 u32 err_crc:1;
785 u32 err_runt:1;
786 u32 err_too_long:1;
787 u32 err_phy:1;
788 u32 src_port:4;
789 u32 multicast:1;
790 u32 error:1;
791 u32 csum_err_udp:1;
792 u32 csum_err_tcp:1;
793 u32 csum_err_ip:1;
794 u32 last_desc:1;
795 u32 first_desc:1;
796 u32 hw_owned:1;
797#endif
798};
799
800struct ksz_desc_tx_stat {
801#ifdef __BIG_ENDIAN_BITFIELD
802 u32 hw_owned:1;
803 u32 reserved1:31;
804#else
805 u32 reserved1:31;
806 u32 hw_owned:1;
807#endif
808};
809
810struct ksz_desc_rx_buf {
811#ifdef __BIG_ENDIAN_BITFIELD
812 u32 reserved4:6;
813 u32 end_of_ring:1;
814 u32 reserved3:14;
815 u32 buf_size:11;
816#else
817 u32 buf_size:11;
818 u32 reserved3:14;
819 u32 end_of_ring:1;
820 u32 reserved4:6;
821#endif
822};
823
824struct ksz_desc_tx_buf {
825#ifdef __BIG_ENDIAN_BITFIELD
826 u32 intr:1;
827 u32 first_seg:1;
828 u32 last_seg:1;
829 u32 csum_gen_ip:1;
830 u32 csum_gen_tcp:1;
831 u32 csum_gen_udp:1;
832 u32 end_of_ring:1;
833 u32 reserved4:1;
834 u32 dest_port:4;
835 u32 reserved3:9;
836 u32 buf_size:11;
837#else
838 u32 buf_size:11;
839 u32 reserved3:9;
840 u32 dest_port:4;
841 u32 reserved4:1;
842 u32 end_of_ring:1;
843 u32 csum_gen_udp:1;
844 u32 csum_gen_tcp:1;
845 u32 csum_gen_ip:1;
846 u32 last_seg:1;
847 u32 first_seg:1;
848 u32 intr:1;
849#endif
850};
851
852union desc_stat {
853 struct ksz_desc_rx_stat rx;
854 struct ksz_desc_tx_stat tx;
855 u32 data;
856};
857
858union desc_buf {
859 struct ksz_desc_rx_buf rx;
860 struct ksz_desc_tx_buf tx;
861 u32 data;
862};
863
864/**
865 * struct ksz_hw_desc - Hardware descriptor data structure
866 * @ctrl: Descriptor control value.
867 * @buf: Descriptor buffer value.
868 * @addr: Physical address of memory buffer.
869 * @next: Pointer to next hardware descriptor.
870 */
871struct ksz_hw_desc {
872 union desc_stat ctrl;
873 union desc_buf buf;
874 u32 addr;
875 u32 next;
876};
877
878/**
879 * struct ksz_sw_desc - Software descriptor data structure
880 * @ctrl: Descriptor control value.
881 * @buf: Descriptor buffer value.
882 * @buf_size: Current buffers size value in hardware descriptor.
883 */
884struct ksz_sw_desc {
885 union desc_stat ctrl;
886 union desc_buf buf;
887 u32 buf_size;
888};
889
890/**
891 * struct ksz_dma_buf - OS dependent DMA buffer data structure
892 * @skb: Associated socket buffer.
893 * @dma: Associated physical DMA address.
894 * @len: Actual len used.
895 */
896struct ksz_dma_buf {
897 struct sk_buff *skb;
898 dma_addr_t dma;
899 int len;
900};
901
902/**
903 * struct ksz_desc - Descriptor structure
904 * @phw: Hardware descriptor pointer to uncached physical memory.
905 * @sw: Cached memory to hold hardware descriptor values for
906 * manipulation.
907 * @dma_buf: Operating system dependent data structure to hold physical
908 * memory buffer allocation information.
909 */
910struct ksz_desc {
911 struct ksz_hw_desc *phw;
912 struct ksz_sw_desc sw;
913 struct ksz_dma_buf dma_buf;
914};
915
916#define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
917
918/**
919 * struct ksz_desc_info - Descriptor information data structure
920 * @ring: First descriptor in the ring.
921 * @cur: Current descriptor being manipulated.
922 * @ring_virt: First hardware descriptor in the ring.
923 * @ring_phys: The physical address of the first descriptor of the ring.
924 * @size: Size of hardware descriptor.
925 * @alloc: Number of descriptors allocated.
926 * @avail: Number of descriptors available for use.
927 * @last: Index for last descriptor released to hardware.
928 * @next: Index for next descriptor available for use.
929 * @mask: Mask for index wrapping.
930 */
931struct ksz_desc_info {
932 struct ksz_desc *ring;
933 struct ksz_desc *cur;
934 struct ksz_hw_desc *ring_virt;
935 u32 ring_phys;
936 int size;
937 int alloc;
938 int avail;
939 int last;
940 int next;
941 int mask;
942};
943
944/*
945 * KSZ8842 switch definitions
946 */
947
948enum {
949 TABLE_STATIC_MAC = 0,
950 TABLE_VLAN,
951 TABLE_DYNAMIC_MAC,
952 TABLE_MIB
953};
954
955#define LEARNED_MAC_TABLE_ENTRIES 1024
956#define STATIC_MAC_TABLE_ENTRIES 8
957
958/**
959 * struct ksz_mac_table - Static MAC table data structure
960 * @mac_addr: MAC address to filter.
961 * @vid: VID value.
962 * @fid: FID value.
963 * @ports: Port membership.
964 * @override: Override setting.
965 * @use_fid: FID use setting.
966 * @valid: Valid setting indicating the entry is being used.
967 */
968struct ksz_mac_table {
969 u8 mac_addr[ETH_ALEN];
970 u16 vid;
971 u8 fid;
972 u8 ports;
973 u8 override:1;
974 u8 use_fid:1;
975 u8 valid:1;
976};
977
978#define VLAN_TABLE_ENTRIES 16
979
980/**
981 * struct ksz_vlan_table - VLAN table data structure
982 * @vid: VID value.
983 * @fid: FID value.
984 * @member: Port membership.
985 */
986struct ksz_vlan_table {
987 u16 vid;
988 u8 fid;
989 u8 member;
990};
991
992#define DIFFSERV_ENTRIES 64
993#define PRIO_802_1P_ENTRIES 8
994#define PRIO_QUEUES 4
995
996#define SWITCH_PORT_NUM 2
997#define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
998#define HOST_MASK (1 << SWITCH_PORT_NUM)
999#define PORT_MASK 7
1000
1001#define MAIN_PORT 0
1002#define OTHER_PORT 1
1003#define HOST_PORT SWITCH_PORT_NUM
1004
1005#define PORT_COUNTER_NUM 0x20
1006#define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1007
1008#define MIB_COUNTER_RX_LO_PRIORITY 0x00
1009#define MIB_COUNTER_RX_HI_PRIORITY 0x01
1010#define MIB_COUNTER_RX_UNDERSIZE 0x02
1011#define MIB_COUNTER_RX_FRAGMENT 0x03
1012#define MIB_COUNTER_RX_OVERSIZE 0x04
1013#define MIB_COUNTER_RX_JABBER 0x05
1014#define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1015#define MIB_COUNTER_RX_CRC_ERR 0x07
1016#define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1017#define MIB_COUNTER_RX_CTRL_8808 0x09
1018#define MIB_COUNTER_RX_PAUSE 0x0A
1019#define MIB_COUNTER_RX_BROADCAST 0x0B
1020#define MIB_COUNTER_RX_MULTICAST 0x0C
1021#define MIB_COUNTER_RX_UNICAST 0x0D
1022#define MIB_COUNTER_RX_OCTET_64 0x0E
1023#define MIB_COUNTER_RX_OCTET_65_127 0x0F
1024#define MIB_COUNTER_RX_OCTET_128_255 0x10
1025#define MIB_COUNTER_RX_OCTET_256_511 0x11
1026#define MIB_COUNTER_RX_OCTET_512_1023 0x12
1027#define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1028#define MIB_COUNTER_TX_LO_PRIORITY 0x14
1029#define MIB_COUNTER_TX_HI_PRIORITY 0x15
1030#define MIB_COUNTER_TX_LATE_COLLISION 0x16
1031#define MIB_COUNTER_TX_PAUSE 0x17
1032#define MIB_COUNTER_TX_BROADCAST 0x18
1033#define MIB_COUNTER_TX_MULTICAST 0x19
1034#define MIB_COUNTER_TX_UNICAST 0x1A
1035#define MIB_COUNTER_TX_DEFERRED 0x1B
1036#define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1037#define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1038#define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1039#define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1040
1041#define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1042#define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1043
1044/**
1045 * struct ksz_port_mib - Port MIB data structure
1046 * @cnt_ptr: Current pointer to MIB counter index.
1047 * @link_down: Indication the link has just gone down.
1048 * @state: Connection status of the port.
1049 * @mib_start: The starting counter index. Some ports do not start at 0.
1050 * @counter: 64-bit MIB counter value.
1051 * @dropped: Temporary buffer to remember last read packet dropped values.
1052 *
1053 * MIB counters needs to be read periodically so that counters do not get
1054 * overflowed and give incorrect values. A right balance is needed to
1055 * satisfy this condition and not waste too much CPU time.
1056 *
1057 * It is pointless to read MIB counters when the port is disconnected. The
1058 * @state provides the connection status so that MIB counters are read only
1059 * when the port is connected. The @link_down indicates the port is just
1060 * disconnected so that all MIB counters are read one last time to update the
1061 * information.
1062 */
1063struct ksz_port_mib {
1064 u8 cnt_ptr;
1065 u8 link_down;
1066 u8 state;
1067 u8 mib_start;
1068
1069 u64 counter[TOTAL_PORT_COUNTER_NUM];
1070 u32 dropped[2];
1071};
1072
1073/**
1074 * struct ksz_port_cfg - Port configuration data structure
1075 * @vid: VID value.
1076 * @member: Port membership.
1077 * @port_prio: Port priority.
1078 * @rx_rate: Receive priority rate.
1079 * @tx_rate: Transmit priority rate.
1080 * @stp_state: Current Spanning Tree Protocol state.
1081 */
1082struct ksz_port_cfg {
1083 u16 vid;
1084 u8 member;
1085 u8 port_prio;
1086 u32 rx_rate[PRIO_QUEUES];
1087 u32 tx_rate[PRIO_QUEUES];
1088 int stp_state;
1089};
1090
1091/**
1092 * struct ksz_switch - KSZ8842 switch data structure
1093 * @mac_table: MAC table entries information.
1094 * @vlan_table: VLAN table entries information.
1095 * @port_cfg: Port configuration information.
1096 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1097 * (bit7 ~ bit2) field.
1098 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1099 * Tag priority field.
1100 * @br_addr: Bridge address. Used for STP.
1101 * @other_addr: Other MAC address. Used for multiple network device mode.
1102 * @broad_per: Broadcast storm percentage.
1103 * @member: Current port membership. Used for STP.
1104 */
1105struct ksz_switch {
1106 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1107 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1108 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1109
1110 u8 diffserv[DIFFSERV_ENTRIES];
1111 u8 p_802_1p[PRIO_802_1P_ENTRIES];
1112
1113 u8 br_addr[ETH_ALEN];
1114 u8 other_addr[ETH_ALEN];
1115
1116 u8 broad_per;
1117 u8 member;
1118};
1119
1120#define TX_RATE_UNIT 10000
1121
1122/**
1123 * struct ksz_port_info - Port information data structure
1124 * @state: Connection status of the port.
1125 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1126 * @duplex: Duplex mode.
1127 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1128 * @partner: Auto-negotiation partner setting. Used to determine link.
1129 * @port_id: Port index to access actual hardware register.
1130 * @pdev: Pointer to OS dependent network device.
1131 */
1132struct ksz_port_info {
1133 uint state;
1134 uint tx_rate;
1135 u8 duplex;
1136 u8 advertised;
1137 u8 partner;
1138 u8 port_id;
1139 void *pdev;
1140};
1141
1142#define MAX_TX_HELD_SIZE 52000
1143
1144/* Hardware features and bug fixes. */
1145#define LINK_INT_WORKING (1 << 0)
1146#define SMALL_PACKET_TX_BUG (1 << 1)
1147#define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1148#define RX_HUGE_FRAME (1 << 4)
1149#define STP_SUPPORT (1 << 8)
1150
1151/* Software overrides. */
1152#define PAUSE_FLOW_CTRL (1 << 0)
1153#define FAST_AGING (1 << 1)
1154
1155/**
1156 * struct ksz_hw - KSZ884X hardware data structure
1157 * @io: Virtual address assigned.
1158 * @ksz_switch: Pointer to KSZ8842 switch.
1159 * @port_info: Port information.
1160 * @port_mib: Port MIB information.
1161 * @dev_count: Number of network devices this hardware supports.
1162 * @dst_ports: Destination ports in switch for transmission.
1163 * @id: Hardware ID. Used for display only.
1164 * @mib_cnt: Number of MIB counters this hardware has.
1165 * @mib_port_cnt: Number of ports with MIB counters.
1166 * @tx_cfg: Cached transmit control settings.
1167 * @rx_cfg: Cached receive control settings.
1168 * @intr_mask: Current interrupt mask.
1169 * @intr_set: Current interrup set.
1170 * @intr_blocked: Interrupt blocked.
1171 * @rx_desc_info: Receive descriptor information.
1172 * @tx_desc_info: Transmit descriptor information.
1173 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1174 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1175 * @tx_size: Transmit data size. Used for TX optimization.
1176 * The maximum is defined by MAX_TX_HELD_SIZE.
1177 * @perm_addr: Permanent MAC address.
1178 * @override_addr: Overridden MAC address.
1179 * @address: Additional MAC address entries.
1180 * @addr_list_size: Additional MAC address list size.
1181 * @mac_override: Indication of MAC address overridden.
1182 * @promiscuous: Counter to keep track of promiscuous mode set.
1183 * @all_multi: Counter to keep track of all multicast mode set.
1184 * @multi_list: Multicast address entries.
1185 * @multi_bits: Cached multicast hash table settings.
1186 * @multi_list_size: Multicast address list size.
1187 * @enabled: Indication of hardware enabled.
1188 * @rx_stop: Indication of receive process stop.
1189 * @reserved2: none
1190 * @features: Hardware features to enable.
1191 * @overrides: Hardware features to override.
1192 * @parent: Pointer to parent, network device private structure.
1193 */
1194struct ksz_hw {
1195 void __iomem *io;
1196
1197 struct ksz_switch *ksz_switch;
1198 struct ksz_port_info port_info[SWITCH_PORT_NUM];
1199 struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1200 int dev_count;
1201 int dst_ports;
1202 int id;
1203 int mib_cnt;
1204 int mib_port_cnt;
1205
1206 u32 tx_cfg;
1207 u32 rx_cfg;
1208 u32 intr_mask;
1209 u32 intr_set;
1210 uint intr_blocked;
1211
1212 struct ksz_desc_info rx_desc_info;
1213 struct ksz_desc_info tx_desc_info;
1214
1215 int tx_int_cnt;
1216 int tx_int_mask;
1217 int tx_size;
1218
1219 u8 perm_addr[ETH_ALEN];
1220 u8 override_addr[ETH_ALEN];
1221 u8 address[ADDITIONAL_ENTRIES][ETH_ALEN];
1222 u8 addr_list_size;
1223 u8 mac_override;
1224 u8 promiscuous;
1225 u8 all_multi;
1226 u8 multi_list[MAX_MULTICAST_LIST][ETH_ALEN];
1227 u8 multi_bits[HW_MULTICAST_SIZE];
1228 u8 multi_list_size;
1229
1230 u8 enabled;
1231 u8 rx_stop;
1232 u8 reserved2[1];
1233
1234 uint features;
1235 uint overrides;
1236
1237 void *parent;
1238};
1239
1240enum {
1241 PHY_NO_FLOW_CTRL,
1242 PHY_FLOW_CTRL,
1243 PHY_TX_ONLY,
1244 PHY_RX_ONLY
1245};
1246
1247/**
1248 * struct ksz_port - Virtual port data structure
1249 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1250 * duplex, and 0 for auto, which normally results in full
1251 * duplex.
1252 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1253 * 0 for auto, which normally results in 100 Mbit.
1254 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1255 * force.
1256 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1257 * control, and PHY_FLOW_CTRL for flow control.
1258 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1259 * Mbit PHY.
1260 * @first_port: Index of first port this port supports.
1261 * @mib_port_cnt: Number of ports with MIB counters.
1262 * @port_cnt: Number of ports this port supports.
1263 * @counter: Port statistics counter.
1264 * @hw: Pointer to hardware structure.
1265 * @linked: Pointer to port information linked to this port.
1266 */
1267struct ksz_port {
1268 u8 duplex;
1269 u8 speed;
1270 u8 force_link;
1271 u8 flow_ctrl;
1272
1273 int first_port;
1274 int mib_port_cnt;
1275 int port_cnt;
1276 u64 counter[OID_COUNTER_LAST];
1277
1278 struct ksz_hw *hw;
1279 struct ksz_port_info *linked;
1280};
1281
1282/**
1283 * struct ksz_timer_info - Timer information data structure
1284 * @timer: Kernel timer.
1285 * @cnt: Running timer counter.
1286 * @max: Number of times to run timer; -1 for infinity.
1287 * @period: Timer period in jiffies.
1288 */
1289struct ksz_timer_info {
1290 struct timer_list timer;
1291 int cnt;
1292 int max;
1293 int period;
1294};
1295
1296/**
1297 * struct ksz_shared_mem - OS dependent shared memory data structure
1298 * @dma_addr: Physical DMA address allocated.
1299 * @alloc_size: Allocation size.
1300 * @phys: Actual physical address used.
1301 * @alloc_virt: Virtual address allocated.
1302 * @virt: Actual virtual address used.
1303 */
1304struct ksz_shared_mem {
1305 dma_addr_t dma_addr;
1306 uint alloc_size;
1307 uint phys;
1308 u8 *alloc_virt;
1309 u8 *virt;
1310};
1311
1312/**
1313 * struct ksz_counter_info - OS dependent counter information data structure
1314 * @counter: Wait queue to wakeup after counters are read.
1315 * @time: Next time in jiffies to read counter.
1316 * @read: Indication of counters read in full or not.
1317 */
1318struct ksz_counter_info {
1319 wait_queue_head_t counter;
1320 unsigned long time;
1321 int read;
1322};
1323
1324/**
1325 * struct dev_info - Network device information data structure
1326 * @dev: Pointer to network device.
1327 * @pdev: Pointer to PCI device.
1328 * @hw: Hardware structure.
1329 * @desc_pool: Physical memory used for descriptor pool.
1330 * @hwlock: Spinlock to prevent hardware from accessing.
1331 * @lock: Mutex lock to prevent device from accessing.
1332 * @dev_rcv: Receive process function used.
1333 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1334 * @skb_index: Buffer index for receiving fragments.
1335 * @skb_len: Buffer length for receiving fragments.
1336 * @mib_read: Workqueue to read MIB counters.
1337 * @mib_timer_info: Timer to read MIB counters.
1338 * @counter: Used for MIB reading.
1339 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1340 * the maximum is MAX_RX_BUF_SIZE.
1341 * @opened: Counter to keep track of device open.
1342 * @rx_tasklet: Receive processing tasklet.
1343 * @tx_tasklet: Transmit processing tasklet.
1344 * @wol_enable: Wake-on-LAN enable set by ethtool.
1345 * @wol_support: Wake-on-LAN support used by ethtool.
1346 * @pme_wait: Used for KSZ8841 power management.
1347 */
1348struct dev_info {
1349 struct net_device *dev;
1350 struct pci_dev *pdev;
1351
1352 struct ksz_hw hw;
1353 struct ksz_shared_mem desc_pool;
1354
1355 spinlock_t hwlock;
1356 struct mutex lock;
1357
1358 int (*dev_rcv)(struct dev_info *);
1359
1360 struct sk_buff *last_skb;
1361 int skb_index;
1362 int skb_len;
1363
1364 struct work_struct mib_read;
1365 struct ksz_timer_info mib_timer_info;
1366 struct ksz_counter_info counter[TOTAL_PORT_NUM];
1367
1368 int mtu;
1369 int opened;
1370
1371 struct tasklet_struct rx_tasklet;
1372 struct tasklet_struct tx_tasklet;
1373
1374 int wol_enable;
1375 int wol_support;
1376 unsigned long pme_wait;
1377};
1378
1379/**
1380 * struct dev_priv - Network device private data structure
1381 * @adapter: Adapter device information.
1382 * @port: Port information.
1383 * @monitor_timer_info: Timer to monitor ports.
1384 * @proc_sem: Semaphore for proc accessing.
1385 * @id: Device ID.
1386 * @mii_if: MII interface information.
1387 * @advertising: Temporary variable to store advertised settings.
1388 * @msg_enable: The message flags controlling driver output.
1389 * @media_state: The connection status of the device.
1390 * @multicast: The all multicast state of the device.
1391 * @promiscuous: The promiscuous state of the device.
1392 */
1393struct dev_priv {
1394 struct dev_info *adapter;
1395 struct ksz_port port;
1396 struct ksz_timer_info monitor_timer_info;
1397
1398 struct semaphore proc_sem;
1399 int id;
1400
1401 struct mii_if_info mii_if;
1402 u32 advertising;
1403
1404 u32 msg_enable;
1405 int media_state;
1406 int multicast;
1407 int promiscuous;
1408};
1409
1410#define DRV_NAME "KSZ884X PCI"
1411#define DEVICE_NAME "KSZ884x PCI"
1412#define DRV_VERSION "1.0.0"
1413#define DRV_RELDATE "Feb 8, 2010"
1414
1415static char version[] =
1416 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1417
1418static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1419
1420/*
1421 * Interrupt processing primary routines
1422 */
1423
1424static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1425{
1426 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1427}
1428
1429static inline void hw_dis_intr(struct ksz_hw *hw)
1430{
1431 hw->intr_blocked = hw->intr_mask;
1432 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1433 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1434}
1435
1436static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1437{
1438 hw->intr_set = interrupt;
1439 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1440}
1441
1442static inline void hw_ena_intr(struct ksz_hw *hw)
1443{
1444 hw->intr_blocked = 0;
1445 hw_set_intr(hw, hw->intr_mask);
1446}
1447
1448static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1449{
1450 hw->intr_mask &= ~(bit);
1451}
1452
1453static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1454{
1455 u32 read_intr;
1456
1457 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1458 hw->intr_set = read_intr & ~interrupt;
1459 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1460 hw_dis_intr_bit(hw, interrupt);
1461}
1462
1463/**
1464 * hw_turn_on_intr - turn on specified interrupts
1465 * @hw: The hardware instance.
1466 * @bit: The interrupt bits to be on.
1467 *
1468 * This routine turns on the specified interrupts in the interrupt mask so that
1469 * those interrupts will be enabled.
1470 */
1471static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1472{
1473 hw->intr_mask |= bit;
1474
1475 if (!hw->intr_blocked)
1476 hw_set_intr(hw, hw->intr_mask);
1477}
1478
1479static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1480{
1481 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1482 *status = *status & hw->intr_set;
1483}
1484
1485static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1486{
1487 if (interrupt)
1488 hw_ena_intr(hw);
1489}
1490
1491/**
1492 * hw_block_intr - block hardware interrupts
1493 * @hw: The hardware instance.
1494 *
1495 * This function blocks all interrupts of the hardware and returns the current
1496 * interrupt enable mask so that interrupts can be restored later.
1497 *
1498 * Return the current interrupt enable mask.
1499 */
1500static uint hw_block_intr(struct ksz_hw *hw)
1501{
1502 uint interrupt = 0;
1503
1504 if (!hw->intr_blocked) {
1505 hw_dis_intr(hw);
1506 interrupt = hw->intr_blocked;
1507 }
1508 return interrupt;
1509}
1510
1511/*
1512 * Hardware descriptor routines
1513 */
1514
1515static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1516{
1517 status.rx.hw_owned = 0;
1518 desc->phw->ctrl.data = cpu_to_le32(status.data);
1519}
1520
1521static inline void release_desc(struct ksz_desc *desc)
1522{
1523 desc->sw.ctrl.tx.hw_owned = 1;
1524 if (desc->sw.buf_size != desc->sw.buf.data) {
1525 desc->sw.buf_size = desc->sw.buf.data;
1526 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1527 }
1528 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1529}
1530
1531static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1532{
1533 *desc = &info->ring[info->last];
1534 info->last++;
1535 info->last &= info->mask;
1536 info->avail--;
1537 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1538}
1539
1540static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1541{
1542 desc->phw->addr = cpu_to_le32(addr);
1543}
1544
1545static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1546{
1547 desc->sw.buf.rx.buf_size = len;
1548}
1549
1550static inline void get_tx_pkt(struct ksz_desc_info *info,
1551 struct ksz_desc **desc)
1552{
1553 *desc = &info->ring[info->next];
1554 info->next++;
1555 info->next &= info->mask;
1556 info->avail--;
1557 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1558}
1559
1560static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1561{
1562 desc->phw->addr = cpu_to_le32(addr);
1563}
1564
1565static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1566{
1567 desc->sw.buf.tx.buf_size = len;
1568}
1569
1570/* Switch functions */
1571
1572#define TABLE_READ 0x10
1573#define TABLE_SEL_SHIFT 2
1574
1575#define HW_DELAY(hw, reg) \
1576 do { \
1577 readw(hw->io + reg); \
1578 } while (0)
1579
1580/**
1581 * sw_r_table - read 4 bytes of data from switch table
1582 * @hw: The hardware instance.
1583 * @table: The table selector.
1584 * @addr: The address of the table entry.
1585 * @data: Buffer to store the read data.
1586 *
1587 * This routine reads 4 bytes of data from the table of the switch.
1588 * Hardware interrupts are disabled to minimize corruption of read data.
1589 */
1590static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1591{
1592 u16 ctrl_addr;
1593 uint interrupt;
1594
1595 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1596
1597 interrupt = hw_block_intr(hw);
1598
1599 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1600 HW_DELAY(hw, KS884X_IACR_OFFSET);
1601 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1602
1603 hw_restore_intr(hw, interrupt);
1604}
1605
1606/**
1607 * sw_w_table_64 - write 8 bytes of data to the switch table
1608 * @hw: The hardware instance.
1609 * @table: The table selector.
1610 * @addr: The address of the table entry.
1611 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1612 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1613 *
1614 * This routine writes 8 bytes of data to the table of the switch.
1615 * Hardware interrupts are disabled to minimize corruption of written data.
1616 */
1617static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1618 u32 data_lo)
1619{
1620 u16 ctrl_addr;
1621 uint interrupt;
1622
1623 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1624
1625 interrupt = hw_block_intr(hw);
1626
1627 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1628 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1629
1630 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1631 HW_DELAY(hw, KS884X_IACR_OFFSET);
1632
1633 hw_restore_intr(hw, interrupt);
1634}
1635
1636/**
1637 * sw_w_sta_mac_table - write to the static MAC table
1638 * @hw: The hardware instance.
1639 * @addr: The address of the table entry.
1640 * @mac_addr: The MAC address.
1641 * @ports: The port members.
1642 * @override: The flag to override the port receive/transmit settings.
1643 * @valid: The flag to indicate entry is valid.
1644 * @use_fid: The flag to indicate the FID is valid.
1645 * @fid: The FID value.
1646 *
1647 * This routine writes an entry of the static MAC table of the switch. It
1648 * calls sw_w_table_64() to write the data.
1649 */
1650static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1651 u8 ports, int override, int valid, int use_fid, u8 fid)
1652{
1653 u32 data_hi;
1654 u32 data_lo;
1655
1656 data_lo = ((u32) mac_addr[2] << 24) |
1657 ((u32) mac_addr[3] << 16) |
1658 ((u32) mac_addr[4] << 8) | mac_addr[5];
1659 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1660 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1661
1662 if (override)
1663 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1664 if (use_fid) {
1665 data_hi |= STATIC_MAC_TABLE_USE_FID;
1666 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1667 }
1668 if (valid)
1669 data_hi |= STATIC_MAC_TABLE_VALID;
1670
1671 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1672}
1673
1674/**
1675 * sw_r_vlan_table - read from the VLAN table
1676 * @hw: The hardware instance.
1677 * @addr: The address of the table entry.
1678 * @vid: Buffer to store the VID.
1679 * @fid: Buffer to store the VID.
1680 * @member: Buffer to store the port membership.
1681 *
1682 * This function reads an entry of the VLAN table of the switch. It calls
1683 * sw_r_table() to get the data.
1684 *
1685 * Return 0 if the entry is valid; otherwise -1.
1686 */
1687static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1688 u8 *member)
1689{
1690 u32 data;
1691
1692 sw_r_table(hw, TABLE_VLAN, addr, &data);
1693 if (data & VLAN_TABLE_VALID) {
1694 *vid = (u16)(data & VLAN_TABLE_VID);
1695 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1696 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1697 VLAN_TABLE_MEMBERSHIP_SHIFT);
1698 return 0;
1699 }
1700 return -1;
1701}
1702
1703/**
1704 * port_r_mib_cnt - read MIB counter
1705 * @hw: The hardware instance.
1706 * @port: The port index.
1707 * @addr: The address of the counter.
1708 * @cnt: Buffer to store the counter.
1709 *
1710 * This routine reads a MIB counter of the port.
1711 * Hardware interrupts are disabled to minimize corruption of read data.
1712 */
1713static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1714{
1715 u32 data;
1716 u16 ctrl_addr;
1717 uint interrupt;
1718 int timeout;
1719
1720 ctrl_addr = addr + PORT_COUNTER_NUM * port;
1721
1722 interrupt = hw_block_intr(hw);
1723
1724 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1725 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1726 HW_DELAY(hw, KS884X_IACR_OFFSET);
1727
1728 for (timeout = 100; timeout > 0; timeout--) {
1729 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1730
1731 if (data & MIB_COUNTER_VALID) {
1732 if (data & MIB_COUNTER_OVERFLOW)
1733 *cnt += MIB_COUNTER_VALUE + 1;
1734 *cnt += data & MIB_COUNTER_VALUE;
1735 break;
1736 }
1737 }
1738
1739 hw_restore_intr(hw, interrupt);
1740}
1741
1742/**
1743 * port_r_mib_pkt - read dropped packet counts
1744 * @hw: The hardware instance.
1745 * @port: The port index.
1746 * @last: last one
1747 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1748 *
1749 * This routine reads the dropped packet counts of the port.
1750 * Hardware interrupts are disabled to minimize corruption of read data.
1751 */
1752static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1753{
1754 u32 cur;
1755 u32 data;
1756 u16 ctrl_addr;
1757 uint interrupt;
1758 int index;
1759
1760 index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1761 do {
1762 interrupt = hw_block_intr(hw);
1763
1764 ctrl_addr = (u16) index;
1765 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1766 << 8);
1767 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1768 HW_DELAY(hw, KS884X_IACR_OFFSET);
1769 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1770
1771 hw_restore_intr(hw, interrupt);
1772
1773 data &= MIB_PACKET_DROPPED;
1774 cur = *last;
1775 if (data != cur) {
1776 *last = data;
1777 if (data < cur)
1778 data += MIB_PACKET_DROPPED + 1;
1779 data -= cur;
1780 *cnt += data;
1781 }
1782 ++last;
1783 ++cnt;
1784 index -= KS_MIB_PACKET_DROPPED_TX -
1785 KS_MIB_PACKET_DROPPED_TX_0 + 1;
1786 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1787}
1788
1789/**
1790 * port_r_cnt - read MIB counters periodically
1791 * @hw: The hardware instance.
1792 * @port: The port index.
1793 *
1794 * This routine is used to read the counters of the port periodically to avoid
1795 * counter overflow. The hardware should be acquired first before calling this
1796 * routine.
1797 *
1798 * Return non-zero when not all counters not read.
1799 */
1800static int port_r_cnt(struct ksz_hw *hw, int port)
1801{
1802 struct ksz_port_mib *mib = &hw->port_mib[port];
1803
1804 if (mib->mib_start < PORT_COUNTER_NUM)
1805 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1806 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1807 &mib->counter[mib->cnt_ptr]);
1808 ++mib->cnt_ptr;
1809 }
1810 if (hw->mib_cnt > PORT_COUNTER_NUM)
1811 port_r_mib_pkt(hw, port, mib->dropped,
1812 &mib->counter[PORT_COUNTER_NUM]);
1813 mib->cnt_ptr = 0;
1814 return 0;
1815}
1816
1817/**
1818 * port_init_cnt - initialize MIB counter values
1819 * @hw: The hardware instance.
1820 * @port: The port index.
1821 *
1822 * This routine is used to initialize all counters to zero if the hardware
1823 * cannot do it after reset.
1824 */
1825static void port_init_cnt(struct ksz_hw *hw, int port)
1826{
1827 struct ksz_port_mib *mib = &hw->port_mib[port];
1828
1829 mib->cnt_ptr = 0;
1830 if (mib->mib_start < PORT_COUNTER_NUM)
1831 do {
1832 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1833 &mib->counter[mib->cnt_ptr]);
1834 ++mib->cnt_ptr;
1835 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1836 if (hw->mib_cnt > PORT_COUNTER_NUM)
1837 port_r_mib_pkt(hw, port, mib->dropped,
1838 &mib->counter[PORT_COUNTER_NUM]);
1839 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1840 mib->cnt_ptr = 0;
1841}
1842
1843/*
1844 * Port functions
1845 */
1846
1847/**
1848 * port_cfg - set port register bits
1849 * @hw: The hardware instance.
1850 * @port: The port index.
1851 * @offset: The offset of the port register.
1852 * @bits: The data bits to set.
1853 * @set: The flag indicating whether the bits are to be set or not.
1854 *
1855 * This routine sets or resets the specified bits of the port register.
1856 */
1857static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1858 int set)
1859{
1860 u32 addr;
1861 u16 data;
1862
1863 PORT_CTRL_ADDR(port, addr);
1864 addr += offset;
1865 data = readw(hw->io + addr);
1866 if (set)
1867 data |= bits;
1868 else
1869 data &= ~bits;
1870 writew(data, hw->io + addr);
1871}
1872
1873/**
1874 * port_r8 - read byte from port register
1875 * @hw: The hardware instance.
1876 * @port: The port index.
1877 * @offset: The offset of the port register.
1878 * @data: Buffer to store the data.
1879 *
1880 * This routine reads a byte from the port register.
1881 */
1882static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
1883{
1884 u32 addr;
1885
1886 PORT_CTRL_ADDR(port, addr);
1887 addr += offset;
1888 *data = readb(hw->io + addr);
1889}
1890
1891/**
1892 * port_r16 - read word from port register.
1893 * @hw: The hardware instance.
1894 * @port: The port index.
1895 * @offset: The offset of the port register.
1896 * @data: Buffer to store the data.
1897 *
1898 * This routine reads a word from the port register.
1899 */
1900static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
1901{
1902 u32 addr;
1903
1904 PORT_CTRL_ADDR(port, addr);
1905 addr += offset;
1906 *data = readw(hw->io + addr);
1907}
1908
1909/**
1910 * port_w16 - write word to port register.
1911 * @hw: The hardware instance.
1912 * @port: The port index.
1913 * @offset: The offset of the port register.
1914 * @data: Data to write.
1915 *
1916 * This routine writes a word to the port register.
1917 */
1918static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
1919{
1920 u32 addr;
1921
1922 PORT_CTRL_ADDR(port, addr);
1923 addr += offset;
1924 writew(data, hw->io + addr);
1925}
1926
1927/**
1928 * sw_chk - check switch register bits
1929 * @hw: The hardware instance.
1930 * @addr: The address of the switch register.
1931 * @bits: The data bits to check.
1932 *
1933 * This function checks whether the specified bits of the switch register are
1934 * set or not.
1935 *
1936 * Return 0 if the bits are not set.
1937 */
1938static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
1939{
1940 u16 data;
1941
1942 data = readw(hw->io + addr);
1943 return (data & bits) == bits;
1944}
1945
1946/**
1947 * sw_cfg - set switch register bits
1948 * @hw: The hardware instance.
1949 * @addr: The address of the switch register.
1950 * @bits: The data bits to set.
1951 * @set: The flag indicating whether the bits are to be set or not.
1952 *
1953 * This function sets or resets the specified bits of the switch register.
1954 */
1955static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
1956{
1957 u16 data;
1958
1959 data = readw(hw->io + addr);
1960 if (set)
1961 data |= bits;
1962 else
1963 data &= ~bits;
1964 writew(data, hw->io + addr);
1965}
1966
1967/* Bandwidth */
1968
1969static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
1970{
1971 port_cfg(hw, p,
1972 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
1973}
1974
1975/* Driver set switch broadcast storm protection at 10% rate. */
1976#define BROADCAST_STORM_PROTECTION_RATE 10
1977
1978/* 148,800 frames * 67 ms / 100 */
1979#define BROADCAST_STORM_VALUE 9969
1980
1981/**
1982 * sw_cfg_broad_storm - configure broadcast storm threshold
1983 * @hw: The hardware instance.
1984 * @percent: Broadcast storm threshold in percent of transmit rate.
1985 *
1986 * This routine configures the broadcast storm threshold of the switch.
1987 */
1988static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
1989{
1990 u16 data;
1991 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
1992
1993 if (value > BROADCAST_STORM_RATE)
1994 value = BROADCAST_STORM_RATE;
1995
1996 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
1997 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
1998 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
1999 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2000}
2001
2002/**
2003 * sw_get_broad_storm - get broadcast storm threshold
2004 * @hw: The hardware instance.
2005 * @percent: Buffer to store the broadcast storm threshold percentage.
2006 *
2007 * This routine retrieves the broadcast storm threshold of the switch.
2008 */
2009static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2010{
2011 int num;
2012 u16 data;
2013
2014 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2015 num = (data & BROADCAST_STORM_RATE_HI);
2016 num <<= 8;
2017 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2018 num = DIV_ROUND_CLOSEST(num * 100, BROADCAST_STORM_VALUE);
2019 *percent = (u8) num;
2020}
2021
2022/**
2023 * sw_dis_broad_storm - disable broadstorm
2024 * @hw: The hardware instance.
2025 * @port: The port index.
2026 *
2027 * This routine disables the broadcast storm limit function of the switch.
2028 */
2029static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2030{
2031 port_cfg_broad_storm(hw, port, 0);
2032}
2033
2034/**
2035 * sw_ena_broad_storm - enable broadcast storm
2036 * @hw: The hardware instance.
2037 * @port: The port index.
2038 *
2039 * This routine enables the broadcast storm limit function of the switch.
2040 */
2041static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2042{
2043 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2044 port_cfg_broad_storm(hw, port, 1);
2045}
2046
2047/**
2048 * sw_init_broad_storm - initialize broadcast storm
2049 * @hw: The hardware instance.
2050 *
2051 * This routine initializes the broadcast storm limit function of the switch.
2052 */
2053static void sw_init_broad_storm(struct ksz_hw *hw)
2054{
2055 int port;
2056
2057 hw->ksz_switch->broad_per = 1;
2058 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2059 for (port = 0; port < TOTAL_PORT_NUM; port++)
2060 sw_dis_broad_storm(hw, port);
2061 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2062}
2063
2064/**
2065 * hw_cfg_broad_storm - configure broadcast storm
2066 * @hw: The hardware instance.
2067 * @percent: Broadcast storm threshold in percent of transmit rate.
2068 *
2069 * This routine configures the broadcast storm threshold of the switch.
2070 * It is called by user functions. The hardware should be acquired first.
2071 */
2072static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2073{
2074 if (percent > 100)
2075 percent = 100;
2076
2077 sw_cfg_broad_storm(hw, percent);
2078 sw_get_broad_storm(hw, &percent);
2079 hw->ksz_switch->broad_per = percent;
2080}
2081
2082/**
2083 * sw_dis_prio_rate - disable switch priority rate
2084 * @hw: The hardware instance.
2085 * @port: The port index.
2086 *
2087 * This routine disables the priority rate function of the switch.
2088 */
2089static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2090{
2091 u32 addr;
2092
2093 PORT_CTRL_ADDR(port, addr);
2094 addr += KS8842_PORT_IN_RATE_OFFSET;
2095 writel(0, hw->io + addr);
2096}
2097
2098/**
2099 * sw_init_prio_rate - initialize switch prioirty rate
2100 * @hw: The hardware instance.
2101 *
2102 * This routine initializes the priority rate function of the switch.
2103 */
2104static void sw_init_prio_rate(struct ksz_hw *hw)
2105{
2106 int port;
2107 int prio;
2108 struct ksz_switch *sw = hw->ksz_switch;
2109
2110 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2111 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2112 sw->port_cfg[port].rx_rate[prio] =
2113 sw->port_cfg[port].tx_rate[prio] = 0;
2114 }
2115 sw_dis_prio_rate(hw, port);
2116 }
2117}
2118
2119/* Communication */
2120
2121static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2122{
2123 port_cfg(hw, p,
2124 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2125}
2126
2127/* Mirroring */
2128
2129static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2130{
2131 port_cfg(hw, p,
2132 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2133}
2134
2135static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2136{
2137 port_cfg(hw, p,
2138 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2139}
2140
2141static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2142{
2143 port_cfg(hw, p,
2144 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2145}
2146
2147static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2148{
2149 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2150}
2151
2152static void sw_init_mirror(struct ksz_hw *hw)
2153{
2154 int port;
2155
2156 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2157 port_cfg_mirror_sniffer(hw, port, 0);
2158 port_cfg_mirror_rx(hw, port, 0);
2159 port_cfg_mirror_tx(hw, port, 0);
2160 }
2161 sw_cfg_mirror_rx_tx(hw, 0);
2162}
2163
2164/* Priority */
2165
2166static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2167{
2168 port_cfg(hw, p,
2169 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2170}
2171
2172static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2173{
2174 port_cfg(hw, p,
2175 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2176}
2177
2178static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2179{
2180 port_cfg(hw, p,
2181 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2182}
2183
2184static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2185{
2186 port_cfg(hw, p,
2187 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2188}
2189
2190/**
2191 * sw_dis_diffserv - disable switch DiffServ priority
2192 * @hw: The hardware instance.
2193 * @port: The port index.
2194 *
2195 * This routine disables the DiffServ priority function of the switch.
2196 */
2197static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2198{
2199 port_cfg_diffserv(hw, port, 0);
2200}
2201
2202/**
2203 * sw_dis_802_1p - disable switch 802.1p priority
2204 * @hw: The hardware instance.
2205 * @port: The port index.
2206 *
2207 * This routine disables the 802.1p priority function of the switch.
2208 */
2209static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2210{
2211 port_cfg_802_1p(hw, port, 0);
2212}
2213
2214/**
2215 * sw_cfg_replace_null_vid -
2216 * @hw: The hardware instance.
2217 * @set: The flag to disable or enable.
2218 *
2219 */
2220static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2221{
2222 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2223}
2224
2225/**
2226 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2227 * @hw: The hardware instance.
2228 * @port: The port index.
2229 * @set: The flag to disable or enable.
2230 *
2231 * This routine enables the 802.1p priority re-mapping function of the switch.
2232 * That allows 802.1p priority field to be replaced with the port's default
2233 * tag's priority value if the ingress packet's 802.1p priority has a higher
2234 * priority than port's default tag's priority.
2235 */
2236static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2237{
2238 port_cfg_replace_vid(hw, port, set);
2239}
2240
2241/**
2242 * sw_cfg_port_based - configure switch port based priority
2243 * @hw: The hardware instance.
2244 * @port: The port index.
2245 * @prio: The priority to set.
2246 *
2247 * This routine configures the port based priority of the switch.
2248 */
2249static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2250{
2251 u16 data;
2252
2253 if (prio > PORT_BASED_PRIORITY_BASE)
2254 prio = PORT_BASED_PRIORITY_BASE;
2255
2256 hw->ksz_switch->port_cfg[port].port_prio = prio;
2257
2258 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2259 data &= ~PORT_BASED_PRIORITY_MASK;
2260 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2261 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2262}
2263
2264/**
2265 * sw_dis_multi_queue - disable transmit multiple queues
2266 * @hw: The hardware instance.
2267 * @port: The port index.
2268 *
2269 * This routine disables the transmit multiple queues selection of the switch
2270 * port. Only single transmit queue on the port.
2271 */
2272static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2273{
2274 port_cfg_prio(hw, port, 0);
2275}
2276
2277/**
2278 * sw_init_prio - initialize switch priority
2279 * @hw: The hardware instance.
2280 *
2281 * This routine initializes the switch QoS priority functions.
2282 */
2283static void sw_init_prio(struct ksz_hw *hw)
2284{
2285 int port;
2286 int tos;
2287 struct ksz_switch *sw = hw->ksz_switch;
2288
2289 /*
2290 * Init all the 802.1p tag priority value to be assigned to different
2291 * priority queue.
2292 */
2293 sw->p_802_1p[0] = 0;
2294 sw->p_802_1p[1] = 0;
2295 sw->p_802_1p[2] = 1;
2296 sw->p_802_1p[3] = 1;
2297 sw->p_802_1p[4] = 2;
2298 sw->p_802_1p[5] = 2;
2299 sw->p_802_1p[6] = 3;
2300 sw->p_802_1p[7] = 3;
2301
2302 /*
2303 * Init all the DiffServ priority value to be assigned to priority
2304 * queue 0.
2305 */
2306 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2307 sw->diffserv[tos] = 0;
2308
2309 /* All QoS functions disabled. */
2310 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2311 sw_dis_multi_queue(hw, port);
2312 sw_dis_diffserv(hw, port);
2313 sw_dis_802_1p(hw, port);
2314 sw_cfg_replace_vid(hw, port, 0);
2315
2316 sw->port_cfg[port].port_prio = 0;
2317 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2318 }
2319 sw_cfg_replace_null_vid(hw, 0);
2320}
2321
2322/**
2323 * port_get_def_vid - get port default VID.
2324 * @hw: The hardware instance.
2325 * @port: The port index.
2326 * @vid: Buffer to store the VID.
2327 *
2328 * This routine retrieves the default VID of the port.
2329 */
2330static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2331{
2332 u32 addr;
2333
2334 PORT_CTRL_ADDR(port, addr);
2335 addr += KS8842_PORT_CTRL_VID_OFFSET;
2336 *vid = readw(hw->io + addr);
2337}
2338
2339/**
2340 * sw_init_vlan - initialize switch VLAN
2341 * @hw: The hardware instance.
2342 *
2343 * This routine initializes the VLAN function of the switch.
2344 */
2345static void sw_init_vlan(struct ksz_hw *hw)
2346{
2347 int port;
2348 int entry;
2349 struct ksz_switch *sw = hw->ksz_switch;
2350
2351 /* Read 16 VLAN entries from device's VLAN table. */
2352 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2353 sw_r_vlan_table(hw, entry,
2354 &sw->vlan_table[entry].vid,
2355 &sw->vlan_table[entry].fid,
2356 &sw->vlan_table[entry].member);
2357 }
2358
2359 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2360 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2361 sw->port_cfg[port].member = PORT_MASK;
2362 }
2363}
2364
2365/**
2366 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2367 * @hw: The hardware instance.
2368 * @port: The port index.
2369 * @member: The port-based VLAN membership.
2370 *
2371 * This routine configures the port-based VLAN membership of the port.
2372 */
2373static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2374{
2375 u32 addr;
2376 u8 data;
2377
2378 PORT_CTRL_ADDR(port, addr);
2379 addr += KS8842_PORT_CTRL_2_OFFSET;
2380
2381 data = readb(hw->io + addr);
2382 data &= ~PORT_VLAN_MEMBERSHIP;
2383 data |= (member & PORT_MASK);
2384 writeb(data, hw->io + addr);
2385
2386 hw->ksz_switch->port_cfg[port].member = member;
2387}
2388
2389/**
2390 * sw_set_addr - configure switch MAC address
2391 * @hw: The hardware instance.
2392 * @mac_addr: The MAC address.
2393 *
2394 * This function configures the MAC address of the switch.
2395 */
2396static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2397{
2398 int i;
2399
2400 for (i = 0; i < 6; i += 2) {
2401 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2402 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2403 }
2404}
2405
2406/**
2407 * sw_set_global_ctrl - set switch global control
2408 * @hw: The hardware instance.
2409 *
2410 * This routine sets the global control of the switch function.
2411 */
2412static void sw_set_global_ctrl(struct ksz_hw *hw)
2413{
2414 u16 data;
2415
2416 /* Enable switch MII flow control. */
2417 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2418 data |= SWITCH_FLOW_CTRL;
2419 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2420
2421 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2422
2423 /* Enable aggressive back off algorithm in half duplex mode. */
2424 data |= SWITCH_AGGR_BACKOFF;
2425
2426 /* Enable automatic fast aging when link changed detected. */
2427 data |= SWITCH_AGING_ENABLE;
2428 data |= SWITCH_LINK_AUTO_AGING;
2429
2430 if (hw->overrides & FAST_AGING)
2431 data |= SWITCH_FAST_AGING;
2432 else
2433 data &= ~SWITCH_FAST_AGING;
2434 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2435
2436 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2437
2438 /* Enable no excessive collision drop. */
2439 data |= NO_EXC_COLLISION_DROP;
2440 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2441}
2442
2443enum {
2444 STP_STATE_DISABLED = 0,
2445 STP_STATE_LISTENING,
2446 STP_STATE_LEARNING,
2447 STP_STATE_FORWARDING,
2448 STP_STATE_BLOCKED,
2449 STP_STATE_SIMPLE
2450};
2451
2452/**
2453 * port_set_stp_state - configure port spanning tree state
2454 * @hw: The hardware instance.
2455 * @port: The port index.
2456 * @state: The spanning tree state.
2457 *
2458 * This routine configures the spanning tree state of the port.
2459 */
2460static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2461{
2462 u16 data;
2463
2464 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2465 switch (state) {
2466 case STP_STATE_DISABLED:
2467 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2468 data |= PORT_LEARN_DISABLE;
2469 break;
2470 case STP_STATE_LISTENING:
2471/*
2472 * No need to turn on transmit because of port direct mode.
2473 * Turning on receive is required if static MAC table is not setup.
2474 */
2475 data &= ~PORT_TX_ENABLE;
2476 data |= PORT_RX_ENABLE;
2477 data |= PORT_LEARN_DISABLE;
2478 break;
2479 case STP_STATE_LEARNING:
2480 data &= ~PORT_TX_ENABLE;
2481 data |= PORT_RX_ENABLE;
2482 data &= ~PORT_LEARN_DISABLE;
2483 break;
2484 case STP_STATE_FORWARDING:
2485 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2486 data &= ~PORT_LEARN_DISABLE;
2487 break;
2488 case STP_STATE_BLOCKED:
2489/*
2490 * Need to setup static MAC table with override to keep receiving BPDU
2491 * messages. See sw_init_stp routine.
2492 */
2493 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2494 data |= PORT_LEARN_DISABLE;
2495 break;
2496 case STP_STATE_SIMPLE:
2497 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2498 data |= PORT_LEARN_DISABLE;
2499 break;
2500 }
2501 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2502 hw->ksz_switch->port_cfg[port].stp_state = state;
2503}
2504
2505#define STP_ENTRY 0
2506#define BROADCAST_ENTRY 1
2507#define BRIDGE_ADDR_ENTRY 2
2508#define IPV6_ADDR_ENTRY 3
2509
2510/**
2511 * sw_clr_sta_mac_table - clear static MAC table
2512 * @hw: The hardware instance.
2513 *
2514 * This routine clears the static MAC table.
2515 */
2516static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2517{
2518 struct ksz_mac_table *entry;
2519 int i;
2520
2521 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2522 entry = &hw->ksz_switch->mac_table[i];
2523 sw_w_sta_mac_table(hw, i,
2524 entry->mac_addr, entry->ports,
2525 entry->override, 0,
2526 entry->use_fid, entry->fid);
2527 }
2528}
2529
2530/**
2531 * sw_init_stp - initialize switch spanning tree support
2532 * @hw: The hardware instance.
2533 *
2534 * This routine initializes the spanning tree support of the switch.
2535 */
2536static void sw_init_stp(struct ksz_hw *hw)
2537{
2538 struct ksz_mac_table *entry;
2539
2540 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2541 entry->mac_addr[0] = 0x01;
2542 entry->mac_addr[1] = 0x80;
2543 entry->mac_addr[2] = 0xC2;
2544 entry->mac_addr[3] = 0x00;
2545 entry->mac_addr[4] = 0x00;
2546 entry->mac_addr[5] = 0x00;
2547 entry->ports = HOST_MASK;
2548 entry->override = 1;
2549 entry->valid = 1;
2550 sw_w_sta_mac_table(hw, STP_ENTRY,
2551 entry->mac_addr, entry->ports,
2552 entry->override, entry->valid,
2553 entry->use_fid, entry->fid);
2554}
2555
2556/**
2557 * sw_block_addr - block certain packets from the host port
2558 * @hw: The hardware instance.
2559 *
2560 * This routine blocks certain packets from reaching to the host port.
2561 */
2562static void sw_block_addr(struct ksz_hw *hw)
2563{
2564 struct ksz_mac_table *entry;
2565 int i;
2566
2567 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2568 entry = &hw->ksz_switch->mac_table[i];
2569 entry->valid = 0;
2570 sw_w_sta_mac_table(hw, i,
2571 entry->mac_addr, entry->ports,
2572 entry->override, entry->valid,
2573 entry->use_fid, entry->fid);
2574 }
2575}
2576
2577static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2578{
2579 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2580}
2581
2582static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2583{
2584 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2585}
2586
2587/**
2588 * hw_r_phy - read data from PHY register
2589 * @hw: The hardware instance.
2590 * @port: Port to read.
2591 * @reg: PHY register to read.
2592 * @val: Buffer to store the read data.
2593 *
2594 * This routine reads data from the PHY register.
2595 */
2596static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2597{
2598 int phy;
2599
2600 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2601 *val = readw(hw->io + phy);
2602}
2603
2604/**
2605 * hw_w_phy - write data to PHY register
2606 * @hw: The hardware instance.
2607 * @port: Port to write.
2608 * @reg: PHY register to write.
2609 * @val: Word data to write.
2610 *
2611 * This routine writes data to the PHY register.
2612 */
2613static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
2614{
2615 int phy;
2616
2617 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2618 writew(val, hw->io + phy);
2619}
2620
2621/*
2622 * EEPROM access functions
2623 */
2624
2625#define AT93C_CODE 0
2626#define AT93C_WR_OFF 0x00
2627#define AT93C_WR_ALL 0x10
2628#define AT93C_ER_ALL 0x20
2629#define AT93C_WR_ON 0x30
2630
2631#define AT93C_WRITE 1
2632#define AT93C_READ 2
2633#define AT93C_ERASE 3
2634
2635#define EEPROM_DELAY 4
2636
2637static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
2638{
2639 u16 data;
2640
2641 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
2642 data &= ~gpio;
2643 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
2644}
2645
2646static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
2647{
2648 u16 data;
2649
2650 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
2651 data |= gpio;
2652 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
2653}
2654
2655static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
2656{
2657 u16 data;
2658
2659 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
2660 return (u8)(data & gpio);
2661}
2662
2663static void eeprom_clk(struct ksz_hw *hw)
2664{
2665 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
2666 udelay(EEPROM_DELAY);
2667 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
2668 udelay(EEPROM_DELAY);
2669}
2670
2671static u16 spi_r(struct ksz_hw *hw)
2672{
2673 int i;
2674 u16 temp = 0;
2675
2676 for (i = 15; i >= 0; i--) {
2677 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
2678 udelay(EEPROM_DELAY);
2679
2680 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
2681
2682 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
2683 udelay(EEPROM_DELAY);
2684 }
2685 return temp;
2686}
2687
2688static void spi_w(struct ksz_hw *hw, u16 data)
2689{
2690 int i;
2691
2692 for (i = 15; i >= 0; i--) {
2693 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
2694 drop_gpio(hw, EEPROM_DATA_OUT);
2695 eeprom_clk(hw);
2696 }
2697}
2698
2699static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
2700{
2701 int i;
2702
2703 /* Initial start bit */
2704 raise_gpio(hw, EEPROM_DATA_OUT);
2705 eeprom_clk(hw);
2706
2707 /* AT93C operation */
2708 for (i = 1; i >= 0; i--) {
2709 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
2710 drop_gpio(hw, EEPROM_DATA_OUT);
2711 eeprom_clk(hw);
2712 }
2713
2714 /* Address location */
2715 for (i = 5; i >= 0; i--) {
2716 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
2717 drop_gpio(hw, EEPROM_DATA_OUT);
2718 eeprom_clk(hw);
2719 }
2720}
2721
2722#define EEPROM_DATA_RESERVED 0
2723#define EEPROM_DATA_MAC_ADDR_0 1
2724#define EEPROM_DATA_MAC_ADDR_1 2
2725#define EEPROM_DATA_MAC_ADDR_2 3
2726#define EEPROM_DATA_SUBSYS_ID 4
2727#define EEPROM_DATA_SUBSYS_VEN_ID 5
2728#define EEPROM_DATA_PM_CAP 6
2729
2730/* User defined EEPROM data */
2731#define EEPROM_DATA_OTHER_MAC_ADDR 9
2732
2733/**
2734 * eeprom_read - read from AT93C46 EEPROM
2735 * @hw: The hardware instance.
2736 * @reg: The register offset.
2737 *
2738 * This function reads a word from the AT93C46 EEPROM.
2739 *
2740 * Return the data value.
2741 */
2742static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
2743{
2744 u16 data;
2745
2746 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
2747
2748 spi_reg(hw, AT93C_READ, reg);
2749 data = spi_r(hw);
2750
2751 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
2752
2753 return data;
2754}
2755
2756/**
2757 * eeprom_write - write to AT93C46 EEPROM
2758 * @hw: The hardware instance.
2759 * @reg: The register offset.
2760 * @data: The data value.
2761 *
2762 * This procedure writes a word to the AT93C46 EEPROM.
2763 */
2764static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
2765{
2766 int timeout;
2767
2768 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
2769
2770 /* Enable write. */
2771 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
2772 drop_gpio(hw, EEPROM_CHIP_SELECT);
2773 udelay(1);
2774
2775 /* Erase the register. */
2776 raise_gpio(hw, EEPROM_CHIP_SELECT);
2777 spi_reg(hw, AT93C_ERASE, reg);
2778 drop_gpio(hw, EEPROM_CHIP_SELECT);
2779 udelay(1);
2780
2781 /* Check operation complete. */
2782 raise_gpio(hw, EEPROM_CHIP_SELECT);
2783 timeout = 8;
2784 mdelay(2);
2785 do {
2786 mdelay(1);
2787 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
2788 drop_gpio(hw, EEPROM_CHIP_SELECT);
2789 udelay(1);
2790
2791 /* Write the register. */
2792 raise_gpio(hw, EEPROM_CHIP_SELECT);
2793 spi_reg(hw, AT93C_WRITE, reg);
2794 spi_w(hw, data);
2795 drop_gpio(hw, EEPROM_CHIP_SELECT);
2796 udelay(1);
2797
2798 /* Check operation complete. */
2799 raise_gpio(hw, EEPROM_CHIP_SELECT);
2800 timeout = 8;
2801 mdelay(2);
2802 do {
2803 mdelay(1);
2804 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
2805 drop_gpio(hw, EEPROM_CHIP_SELECT);
2806 udelay(1);
2807
2808 /* Disable write. */
2809 raise_gpio(hw, EEPROM_CHIP_SELECT);
2810 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
2811
2812 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
2813}
2814
2815/*
2816 * Link detection routines
2817 */
2818
2819static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
2820{
2821 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
2822 switch (port->flow_ctrl) {
2823 case PHY_FLOW_CTRL:
2824 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
2825 break;
2826 /* Not supported. */
2827 case PHY_TX_ONLY:
2828 case PHY_RX_ONLY:
2829 default:
2830 break;
2831 }
2832 return ctrl;
2833}
2834
2835static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
2836{
2837 u32 rx_cfg;
2838 u32 tx_cfg;
2839
2840 rx_cfg = hw->rx_cfg;
2841 tx_cfg = hw->tx_cfg;
2842 if (rx)
2843 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
2844 else
2845 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
2846 if (tx)
2847 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
2848 else
2849 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
2850 if (hw->enabled) {
2851 if (rx_cfg != hw->rx_cfg)
2852 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
2853 if (tx_cfg != hw->tx_cfg)
2854 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
2855 }
2856}
2857
2858static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
2859 u16 local, u16 remote)
2860{
2861 int rx;
2862 int tx;
2863
2864 if (hw->overrides & PAUSE_FLOW_CTRL)
2865 return;
2866
2867 rx = tx = 0;
2868 if (port->force_link)
2869 rx = tx = 1;
2870 if (remote & LPA_PAUSE_CAP) {
2871 if (local & ADVERTISE_PAUSE_CAP) {
2872 rx = tx = 1;
2873 } else if ((remote & LPA_PAUSE_ASYM) &&
2874 (local &
2875 (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) ==
2876 ADVERTISE_PAUSE_ASYM) {
2877 tx = 1;
2878 }
2879 } else if (remote & LPA_PAUSE_ASYM) {
2880 if ((local & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM))
2881 == (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM))
2882 rx = 1;
2883 }
2884 if (!hw->ksz_switch)
2885 set_flow_ctrl(hw, rx, tx);
2886}
2887
2888static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
2889 struct ksz_port_info *info, u16 link_status)
2890{
2891 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
2892 !(hw->overrides & PAUSE_FLOW_CTRL)) {
2893 u32 cfg = hw->tx_cfg;
2894
2895 /* Disable flow control in the half duplex mode. */
2896 if (1 == info->duplex)
2897 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
2898 if (hw->enabled && cfg != hw->tx_cfg)
2899 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
2900 }
2901}
2902
2903/**
2904 * port_get_link_speed - get current link status
2905 * @port: The port instance.
2906 *
2907 * This routine reads PHY registers to determine the current link status of the
2908 * switch ports.
2909 */
2910static void port_get_link_speed(struct ksz_port *port)
2911{
2912 uint interrupt;
2913 struct ksz_port_info *info;
2914 struct ksz_port_info *linked = NULL;
2915 struct ksz_hw *hw = port->hw;
2916 u16 data;
2917 u16 status;
2918 u8 local;
2919 u8 remote;
2920 int i;
2921 int p;
2922
2923 interrupt = hw_block_intr(hw);
2924
2925 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
2926 info = &hw->port_info[p];
2927 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
2928 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
2929
2930 /*
2931 * Link status is changing all the time even when there is no
2932 * cable connection!
2933 */
2934 remote = status & (PORT_AUTO_NEG_COMPLETE |
2935 PORT_STATUS_LINK_GOOD);
2936 local = (u8) data;
2937
2938 /* No change to status. */
2939 if (local == info->advertised && remote == info->partner)
2940 continue;
2941
2942 info->advertised = local;
2943 info->partner = remote;
2944 if (status & PORT_STATUS_LINK_GOOD) {
2945
2946 /* Remember the first linked port. */
2947 if (!linked)
2948 linked = info;
2949
2950 info->tx_rate = 10 * TX_RATE_UNIT;
2951 if (status & PORT_STATUS_SPEED_100MBIT)
2952 info->tx_rate = 100 * TX_RATE_UNIT;
2953
2954 info->duplex = 1;
2955 if (status & PORT_STATUS_FULL_DUPLEX)
2956 info->duplex = 2;
2957
2958 if (media_connected != info->state) {
2959 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
2960 &data);
2961 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
2962 &status);
2963 determine_flow_ctrl(hw, port, data, status);
2964 if (hw->ksz_switch) {
2965 port_cfg_back_pressure(hw, p,
2966 (1 == info->duplex));
2967 }
2968 port_cfg_change(hw, port, info, status);
2969 }
2970 info->state = media_connected;
2971 } else {
2972 /* Indicate the link just goes down. */
2973 if (media_disconnected != info->state)
2974 hw->port_mib[p].link_down = 1;
2975
2976 info->state = media_disconnected;
2977 }
2978 hw->port_mib[p].state = (u8) info->state;
2979 }
2980
2981 if (linked && media_disconnected == port->linked->state)
2982 port->linked = linked;
2983
2984 hw_restore_intr(hw, interrupt);
2985}
2986
2987#define PHY_RESET_TIMEOUT 10
2988
2989/**
2990 * port_set_link_speed - set port speed
2991 * @port: The port instance.
2992 *
2993 * This routine sets the link speed of the switch ports.
2994 */
2995static void port_set_link_speed(struct ksz_port *port)
2996{
2997 struct ksz_hw *hw = port->hw;
2998 u16 data;
2999 u16 cfg;
3000 u8 status;
3001 int i;
3002 int p;
3003
3004 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3005 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3006 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3007
3008 cfg = 0;
3009 if (status & PORT_STATUS_LINK_GOOD)
3010 cfg = data;
3011
3012 data |= PORT_AUTO_NEG_ENABLE;
3013 data = advertised_flow_ctrl(port, data);
3014
3015 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3016 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3017
3018 /* Check if manual configuration is specified by the user. */
3019 if (port->speed || port->duplex) {
3020 if (10 == port->speed)
3021 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3022 PORT_AUTO_NEG_100BTX);
3023 else if (100 == port->speed)
3024 data &= ~(PORT_AUTO_NEG_10BT_FD |
3025 PORT_AUTO_NEG_10BT);
3026 if (1 == port->duplex)
3027 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3028 PORT_AUTO_NEG_10BT_FD);
3029 else if (2 == port->duplex)
3030 data &= ~(PORT_AUTO_NEG_100BTX |
3031 PORT_AUTO_NEG_10BT);
3032 }
3033 if (data != cfg) {
3034 data |= PORT_AUTO_NEG_RESTART;
3035 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3036 }
3037 }
3038}
3039
3040/**
3041 * port_force_link_speed - force port speed
3042 * @port: The port instance.
3043 *
3044 * This routine forces the link speed of the switch ports.
3045 */
3046static void port_force_link_speed(struct ksz_port *port)
3047{
3048 struct ksz_hw *hw = port->hw;
3049 u16 data;
3050 int i;
3051 int phy;
3052 int p;
3053
3054 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3055 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3056 hw_r_phy_ctrl(hw, phy, &data);
3057
3058 data &= ~BMCR_ANENABLE;
3059
3060 if (10 == port->speed)
3061 data &= ~BMCR_SPEED100;
3062 else if (100 == port->speed)
3063 data |= BMCR_SPEED100;
3064 if (1 == port->duplex)
3065 data &= ~BMCR_FULLDPLX;
3066 else if (2 == port->duplex)
3067 data |= BMCR_FULLDPLX;
3068 hw_w_phy_ctrl(hw, phy, data);
3069 }
3070}
3071
3072static void port_set_power_saving(struct ksz_port *port, int enable)
3073{
3074 struct ksz_hw *hw = port->hw;
3075 int i;
3076 int p;
3077
3078 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3079 port_cfg(hw, p,
3080 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3081}
3082
3083/*
3084 * KSZ8841 power management functions
3085 */
3086
3087/**
3088 * hw_chk_wol_pme_status - check PMEN pin
3089 * @hw: The hardware instance.
3090 *
3091 * This function is used to check PMEN pin is asserted.
3092 *
3093 * Return 1 if PMEN pin is asserted; otherwise, 0.
3094 */
3095static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3096{
3097 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3098 struct pci_dev *pdev = hw_priv->pdev;
3099 u16 data;
3100
3101 if (!pdev->pm_cap)
3102 return 0;
3103 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3104 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3105}
3106
3107/**
3108 * hw_clr_wol_pme_status - clear PMEN pin
3109 * @hw: The hardware instance.
3110 *
3111 * This routine is used to clear PME_Status to deassert PMEN pin.
3112 */
3113static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3114{
3115 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3116 struct pci_dev *pdev = hw_priv->pdev;
3117 u16 data;
3118
3119 if (!pdev->pm_cap)
3120 return;
3121
3122 /* Clear PME_Status to deassert PMEN pin. */
3123 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3124 data |= PCI_PM_CTRL_PME_STATUS;
3125 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3126}
3127
3128/**
3129 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3130 * @hw: The hardware instance.
3131 * @set: The flag indicating whether to enable or disable.
3132 *
3133 * This routine is used to enable or disable Wake-on-LAN.
3134 */
3135static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3136{
3137 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3138 struct pci_dev *pdev = hw_priv->pdev;
3139 u16 data;
3140
3141 if (!pdev->pm_cap)
3142 return;
3143 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3144 data &= ~PCI_PM_CTRL_STATE_MASK;
3145 if (set)
3146 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3147 else
3148 data &= ~PCI_PM_CTRL_PME_ENABLE;
3149 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3150}
3151
3152/**
3153 * hw_cfg_wol - configure Wake-on-LAN features
3154 * @hw: The hardware instance.
3155 * @frame: The pattern frame bit.
3156 * @set: The flag indicating whether to enable or disable.
3157 *
3158 * This routine is used to enable or disable certain Wake-on-LAN features.
3159 */
3160static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3161{
3162 u16 data;
3163
3164 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3165 if (set)
3166 data |= frame;
3167 else
3168 data &= ~frame;
3169 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3170}
3171
3172/**
3173 * hw_set_wol_frame - program Wake-on-LAN pattern
3174 * @hw: The hardware instance.
3175 * @i: The frame index.
3176 * @mask_size: The size of the mask.
3177 * @mask: Mask to ignore certain bytes in the pattern.
3178 * @frame_size: The size of the frame.
3179 * @pattern: The frame data.
3180 *
3181 * This routine is used to program Wake-on-LAN pattern.
3182 */
3183static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3184 const u8 *mask, uint frame_size, const u8 *pattern)
3185{
3186 int bits;
3187 int from;
3188 int len;
3189 int to;
3190 u32 crc;
3191 u8 data[64];
3192 u8 val = 0;
3193
3194 if (frame_size > mask_size * 8)
3195 frame_size = mask_size * 8;
3196 if (frame_size > 64)
3197 frame_size = 64;
3198
3199 i *= 0x10;
3200 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3201 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3202
3203 bits = len = from = to = 0;
3204 do {
3205 if (bits) {
3206 if ((val & 1))
3207 data[to++] = pattern[from];
3208 val >>= 1;
3209 ++from;
3210 --bits;
3211 } else {
3212 val = mask[len];
3213 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3214 + len);
3215 ++len;
3216 if (val)
3217 bits = 8;
3218 else
3219 from += 8;
3220 }
3221 } while (from < (int) frame_size);
3222 if (val) {
3223 bits = mask[len - 1];
3224 val <<= (from % 8);
3225 bits &= ~val;
3226 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3227 1);
3228 }
3229 crc = ether_crc(to, data);
3230 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3231}
3232
3233/**
3234 * hw_add_wol_arp - add ARP pattern
3235 * @hw: The hardware instance.
3236 * @ip_addr: The IPv4 address assigned to the device.
3237 *
3238 * This routine is used to add ARP pattern for waking up the host.
3239 */
3240static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
3241{
3242 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3243 u8 pattern[42] = {
3244 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3245 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3246 0x08, 0x06,
3247 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3248 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3249 0x00, 0x00, 0x00, 0x00,
3250 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3251 0x00, 0x00, 0x00, 0x00 };
3252
3253 memcpy(&pattern[38], ip_addr, 4);
3254 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3255}
3256
3257/**
3258 * hw_add_wol_bcast - add broadcast pattern
3259 * @hw: The hardware instance.
3260 *
3261 * This routine is used to add broadcast pattern for waking up the host.
3262 */
3263static void hw_add_wol_bcast(struct ksz_hw *hw)
3264{
3265 static const u8 mask[] = { 0x3F };
3266 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3267
3268 hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern);
3269}
3270
3271/**
3272 * hw_add_wol_mcast - add multicast pattern
3273 * @hw: The hardware instance.
3274 *
3275 * This routine is used to add multicast pattern for waking up the host.
3276 *
3277 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3278 * by IPv6 ping command. Note that multicast packets are filtred through the
3279 * multicast hash table, so not all multicast packets can wake up the host.
3280 */
3281static void hw_add_wol_mcast(struct ksz_hw *hw)
3282{
3283 static const u8 mask[] = { 0x3F };
3284 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3285
3286 memcpy(&pattern[3], &hw->override_addr[3], 3);
3287 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3288}
3289
3290/**
3291 * hw_add_wol_ucast - add unicast pattern
3292 * @hw: The hardware instance.
3293 *
3294 * This routine is used to add unicast pattern to wakeup the host.
3295 *
3296 * It is assumed the unicast packet is directed to the device, as the hardware
3297 * can only receive them in normal case.
3298 */
3299static void hw_add_wol_ucast(struct ksz_hw *hw)
3300{
3301 static const u8 mask[] = { 0x3F };
3302
3303 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr);
3304}
3305
3306/**
3307 * hw_enable_wol - enable Wake-on-LAN
3308 * @hw: The hardware instance.
3309 * @wol_enable: The Wake-on-LAN settings.
3310 * @net_addr: The IPv4 address assigned to the device.
3311 *
3312 * This routine is used to enable Wake-on-LAN depending on driver settings.
3313 */
3314static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
3315{
3316 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3317 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3318 hw_add_wol_ucast(hw);
3319 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3320 hw_add_wol_mcast(hw);
3321 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3322 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3323 hw_add_wol_arp(hw, net_addr);
3324}
3325
3326/**
3327 * hw_init - check driver is correct for the hardware
3328 * @hw: The hardware instance.
3329 *
3330 * This function checks the hardware is correct for this driver and sets the
3331 * hardware up for proper initialization.
3332 *
3333 * Return number of ports or 0 if not right.
3334 */
3335static int hw_init(struct ksz_hw *hw)
3336{
3337 int rc = 0;
3338 u16 data;
3339 u16 revision;
3340
3341 /* Set bus speed to 125MHz. */
3342 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3343
3344 /* Check KSZ884x chip ID. */
3345 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3346
3347 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3348 data &= KS884X_CHIP_ID_MASK_41;
3349 if (REG_CHIP_ID_41 == data)
3350 rc = 1;
3351 else if (REG_CHIP_ID_42 == data)
3352 rc = 2;
3353 else
3354 return 0;
3355
3356 /* Setup hardware features or bug workarounds. */
3357 if (revision <= 1) {
3358 hw->features |= SMALL_PACKET_TX_BUG;
3359 if (1 == rc)
3360 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3361 }
3362 return rc;
3363}
3364
3365/**
3366 * hw_reset - reset the hardware
3367 * @hw: The hardware instance.
3368 *
3369 * This routine resets the hardware.
3370 */
3371static void hw_reset(struct ksz_hw *hw)
3372{
3373 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3374
3375 /* Wait for device to reset. */
3376 mdelay(10);
3377
3378 /* Write 0 to clear device reset. */
3379 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3380}
3381
3382/**
3383 * hw_setup - setup the hardware
3384 * @hw: The hardware instance.
3385 *
3386 * This routine setup the hardware for proper operation.
3387 */
3388static void hw_setup(struct ksz_hw *hw)
3389{
3390#if SET_DEFAULT_LED
3391 u16 data;
3392
3393 /* Change default LED mode. */
3394 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3395 data &= ~LED_MODE;
3396 data |= SET_DEFAULT_LED;
3397 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3398#endif
3399
3400 /* Setup transmit control. */
3401 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3402 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3403
3404 /* Setup receive control. */
3405 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3406 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3407 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3408
3409 /* Hardware cannot handle UDP packet in IP fragments. */
3410 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3411
3412 if (hw->all_multi)
3413 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3414 if (hw->promiscuous)
3415 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3416}
3417
3418/**
3419 * hw_setup_intr - setup interrupt mask
3420 * @hw: The hardware instance.
3421 *
3422 * This routine setup the interrupt mask for proper operation.
3423 */
3424static void hw_setup_intr(struct ksz_hw *hw)
3425{
3426 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3427}
3428
3429static void ksz_check_desc_num(struct ksz_desc_info *info)
3430{
3431#define MIN_DESC_SHIFT 2
3432
3433 int alloc = info->alloc;
3434 int shift;
3435
3436 shift = 0;
3437 while (!(alloc & 1)) {
3438 shift++;
3439 alloc >>= 1;
3440 }
3441 if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3442 pr_alert("Hardware descriptor numbers not right!\n");
3443 while (alloc) {
3444 shift++;
3445 alloc >>= 1;
3446 }
3447 if (shift < MIN_DESC_SHIFT)
3448 shift = MIN_DESC_SHIFT;
3449 alloc = 1 << shift;
3450 info->alloc = alloc;
3451 }
3452 info->mask = info->alloc - 1;
3453}
3454
3455static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3456{
3457 int i;
3458 u32 phys = desc_info->ring_phys;
3459 struct ksz_hw_desc *desc = desc_info->ring_virt;
3460 struct ksz_desc *cur = desc_info->ring;
3461 struct ksz_desc *previous = NULL;
3462
3463 for (i = 0; i < desc_info->alloc; i++) {
3464 cur->phw = desc++;
3465 phys += desc_info->size;
3466 previous = cur++;
3467 previous->phw->next = cpu_to_le32(phys);
3468 }
3469 previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3470 previous->sw.buf.rx.end_of_ring = 1;
3471 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3472
3473 desc_info->avail = desc_info->alloc;
3474 desc_info->last = desc_info->next = 0;
3475
3476 desc_info->cur = desc_info->ring;
3477}
3478
3479/**
3480 * hw_set_desc_base - set descriptor base addresses
3481 * @hw: The hardware instance.
3482 * @tx_addr: The transmit descriptor base.
3483 * @rx_addr: The receive descriptor base.
3484 *
3485 * This routine programs the descriptor base addresses after reset.
3486 */
3487static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3488{
3489 /* Set base address of Tx/Rx descriptors. */
3490 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3491 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3492}
3493
3494static void hw_reset_pkts(struct ksz_desc_info *info)
3495{
3496 info->cur = info->ring;
3497 info->avail = info->alloc;
3498 info->last = info->next = 0;
3499}
3500
3501static inline void hw_resume_rx(struct ksz_hw *hw)
3502{
3503 writel(DMA_START, hw->io + KS_DMA_RX_START);
3504}
3505
3506/**
3507 * hw_start_rx - start receiving
3508 * @hw: The hardware instance.
3509 *
3510 * This routine starts the receive function of the hardware.
3511 */
3512static void hw_start_rx(struct ksz_hw *hw)
3513{
3514 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3515
3516 /* Notify when the receive stops. */
3517 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3518
3519 writel(DMA_START, hw->io + KS_DMA_RX_START);
3520 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3521 hw->rx_stop++;
3522
3523 /* Variable overflows. */
3524 if (0 == hw->rx_stop)
3525 hw->rx_stop = 2;
3526}
3527
3528/**
3529 * hw_stop_rx - stop receiving
3530 * @hw: The hardware instance.
3531 *
3532 * This routine stops the receive function of the hardware.
3533 */
3534static void hw_stop_rx(struct ksz_hw *hw)
3535{
3536 hw->rx_stop = 0;
3537 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3538 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3539}
3540
3541/**
3542 * hw_start_tx - start transmitting
3543 * @hw: The hardware instance.
3544 *
3545 * This routine starts the transmit function of the hardware.
3546 */
3547static void hw_start_tx(struct ksz_hw *hw)
3548{
3549 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3550}
3551
3552/**
3553 * hw_stop_tx - stop transmitting
3554 * @hw: The hardware instance.
3555 *
3556 * This routine stops the transmit function of the hardware.
3557 */
3558static void hw_stop_tx(struct ksz_hw *hw)
3559{
3560 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3561}
3562
3563/**
3564 * hw_disable - disable hardware
3565 * @hw: The hardware instance.
3566 *
3567 * This routine disables the hardware.
3568 */
3569static void hw_disable(struct ksz_hw *hw)
3570{
3571 hw_stop_rx(hw);
3572 hw_stop_tx(hw);
3573 hw->enabled = 0;
3574}
3575
3576/**
3577 * hw_enable - enable hardware
3578 * @hw: The hardware instance.
3579 *
3580 * This routine enables the hardware.
3581 */
3582static void hw_enable(struct ksz_hw *hw)
3583{
3584 hw_start_tx(hw);
3585 hw_start_rx(hw);
3586 hw->enabled = 1;
3587}
3588
3589/**
3590 * hw_alloc_pkt - allocate enough descriptors for transmission
3591 * @hw: The hardware instance.
3592 * @length: The length of the packet.
3593 * @physical: Number of descriptors required.
3594 *
3595 * This function allocates descriptors for transmission.
3596 *
3597 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3598 */
3599static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3600{
3601 /* Always leave one descriptor free. */
3602 if (hw->tx_desc_info.avail <= 1)
3603 return 0;
3604
3605 /* Allocate a descriptor for transmission and mark it current. */
3606 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3607 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
3608
3609 /* Keep track of number of transmit descriptors used so far. */
3610 ++hw->tx_int_cnt;
3611 hw->tx_size += length;
3612
3613 /* Cannot hold on too much data. */
3614 if (hw->tx_size >= MAX_TX_HELD_SIZE)
3615 hw->tx_int_cnt = hw->tx_int_mask + 1;
3616
3617 if (physical > hw->tx_desc_info.avail)
3618 return 1;
3619
3620 return hw->tx_desc_info.avail;
3621}
3622
3623/**
3624 * hw_send_pkt - mark packet for transmission
3625 * @hw: The hardware instance.
3626 *
3627 * This routine marks the packet for transmission in PCI version.
3628 */
3629static void hw_send_pkt(struct ksz_hw *hw)
3630{
3631 struct ksz_desc *cur = hw->tx_desc_info.cur;
3632
3633 cur->sw.buf.tx.last_seg = 1;
3634
3635 /* Interrupt only after specified number of descriptors used. */
3636 if (hw->tx_int_cnt > hw->tx_int_mask) {
3637 cur->sw.buf.tx.intr = 1;
3638 hw->tx_int_cnt = 0;
3639 hw->tx_size = 0;
3640 }
3641
3642 /* KSZ8842 supports port directed transmission. */
3643 cur->sw.buf.tx.dest_port = hw->dst_ports;
3644
3645 release_desc(cur);
3646
3647 writel(0, hw->io + KS_DMA_TX_START);
3648}
3649
3650static int empty_addr(u8 *addr)
3651{
3652 u32 *addr1 = (u32 *) addr;
3653 u16 *addr2 = (u16 *) &addr[4];
3654
3655 return 0 == *addr1 && 0 == *addr2;
3656}
3657
3658/**
3659 * hw_set_addr - set MAC address
3660 * @hw: The hardware instance.
3661 *
3662 * This routine programs the MAC address of the hardware when the address is
3663 * overridden.
3664 */
3665static void hw_set_addr(struct ksz_hw *hw)
3666{
3667 int i;
3668
3669 for (i = 0; i < ETH_ALEN; i++)
3670 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
3671 hw->io + KS884X_ADDR_0_OFFSET + i);
3672
3673 sw_set_addr(hw, hw->override_addr);
3674}
3675
3676/**
3677 * hw_read_addr - read MAC address
3678 * @hw: The hardware instance.
3679 *
3680 * This routine retrieves the MAC address of the hardware.
3681 */
3682static void hw_read_addr(struct ksz_hw *hw)
3683{
3684 int i;
3685
3686 for (i = 0; i < ETH_ALEN; i++)
3687 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
3688 KS884X_ADDR_0_OFFSET + i);
3689
3690 if (!hw->mac_override) {
3691 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN);
3692 if (empty_addr(hw->override_addr)) {
3693 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN);
3694 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
3695 ETH_ALEN);
3696 hw->override_addr[5] += hw->id;
3697 hw_set_addr(hw);
3698 }
3699 }
3700}
3701
3702static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
3703{
3704 int i;
3705 u32 mac_addr_lo;
3706 u32 mac_addr_hi;
3707
3708 mac_addr_hi = 0;
3709 for (i = 0; i < 2; i++) {
3710 mac_addr_hi <<= 8;
3711 mac_addr_hi |= mac_addr[i];
3712 }
3713 mac_addr_hi |= ADD_ADDR_ENABLE;
3714 mac_addr_lo = 0;
3715 for (i = 2; i < 6; i++) {
3716 mac_addr_lo <<= 8;
3717 mac_addr_lo |= mac_addr[i];
3718 }
3719 index *= ADD_ADDR_INCR;
3720
3721 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
3722 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
3723}
3724
3725static void hw_set_add_addr(struct ksz_hw *hw)
3726{
3727 int i;
3728
3729 for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
3730 if (empty_addr(hw->address[i]))
3731 writel(0, hw->io + ADD_ADDR_INCR * i +
3732 KS_ADD_ADDR_0_HI);
3733 else
3734 hw_ena_add_addr(hw, i, hw->address[i]);
3735 }
3736}
3737
3738static int hw_add_addr(struct ksz_hw *hw, const u8 *mac_addr)
3739{
3740 int i;
3741 int j = ADDITIONAL_ENTRIES;
3742
3743 if (ether_addr_equal(hw->override_addr, mac_addr))
3744 return 0;
3745 for (i = 0; i < hw->addr_list_size; i++) {
3746 if (ether_addr_equal(hw->address[i], mac_addr))
3747 return 0;
3748 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
3749 j = i;
3750 }
3751 if (j < ADDITIONAL_ENTRIES) {
3752 memcpy(hw->address[j], mac_addr, ETH_ALEN);
3753 hw_ena_add_addr(hw, j, hw->address[j]);
3754 return 0;
3755 }
3756 return -1;
3757}
3758
3759static int hw_del_addr(struct ksz_hw *hw, const u8 *mac_addr)
3760{
3761 int i;
3762
3763 for (i = 0; i < hw->addr_list_size; i++) {
3764 if (ether_addr_equal(hw->address[i], mac_addr)) {
3765 eth_zero_addr(hw->address[i]);
3766 writel(0, hw->io + ADD_ADDR_INCR * i +
3767 KS_ADD_ADDR_0_HI);
3768 return 0;
3769 }
3770 }
3771 return -1;
3772}
3773
3774/**
3775 * hw_clr_multicast - clear multicast addresses
3776 * @hw: The hardware instance.
3777 *
3778 * This routine removes all multicast addresses set in the hardware.
3779 */
3780static void hw_clr_multicast(struct ksz_hw *hw)
3781{
3782 int i;
3783
3784 for (i = 0; i < HW_MULTICAST_SIZE; i++) {
3785 hw->multi_bits[i] = 0;
3786
3787 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
3788 }
3789}
3790
3791/**
3792 * hw_set_grp_addr - set multicast addresses
3793 * @hw: The hardware instance.
3794 *
3795 * This routine programs multicast addresses for the hardware to accept those
3796 * addresses.
3797 */
3798static void hw_set_grp_addr(struct ksz_hw *hw)
3799{
3800 int i;
3801 int index;
3802 int position;
3803 int value;
3804
3805 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
3806
3807 for (i = 0; i < hw->multi_list_size; i++) {
3808 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
3809 index = position >> 3;
3810 value = 1 << (position & 7);
3811 hw->multi_bits[index] |= (u8) value;
3812 }
3813
3814 for (i = 0; i < HW_MULTICAST_SIZE; i++)
3815 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
3816 i);
3817}
3818
3819/**
3820 * hw_set_multicast - enable or disable all multicast receiving
3821 * @hw: The hardware instance.
3822 * @multicast: To turn on or off the all multicast feature.
3823 *
3824 * This routine enables/disables the hardware to accept all multicast packets.
3825 */
3826static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
3827{
3828 /* Stop receiving for reconfiguration. */
3829 hw_stop_rx(hw);
3830
3831 if (multicast)
3832 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3833 else
3834 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
3835
3836 if (hw->enabled)
3837 hw_start_rx(hw);
3838}
3839
3840/**
3841 * hw_set_promiscuous - enable or disable promiscuous receiving
3842 * @hw: The hardware instance.
3843 * @prom: To turn on or off the promiscuous feature.
3844 *
3845 * This routine enables/disables the hardware to accept all packets.
3846 */
3847static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
3848{
3849 /* Stop receiving for reconfiguration. */
3850 hw_stop_rx(hw);
3851
3852 if (prom)
3853 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3854 else
3855 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
3856
3857 if (hw->enabled)
3858 hw_start_rx(hw);
3859}
3860
3861/**
3862 * sw_enable - enable the switch
3863 * @hw: The hardware instance.
3864 * @enable: The flag to enable or disable the switch
3865 *
3866 * This routine is used to enable/disable the switch in KSZ8842.
3867 */
3868static void sw_enable(struct ksz_hw *hw, int enable)
3869{
3870 int port;
3871
3872 for (port = 0; port < SWITCH_PORT_NUM; port++) {
3873 if (hw->dev_count > 1) {
3874 /* Set port-base vlan membership with host port. */
3875 sw_cfg_port_base_vlan(hw, port,
3876 HOST_MASK | (1 << port));
3877 port_set_stp_state(hw, port, STP_STATE_DISABLED);
3878 } else {
3879 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
3880 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
3881 }
3882 }
3883 if (hw->dev_count > 1)
3884 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
3885 else
3886 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
3887
3888 if (enable)
3889 enable = KS8842_START;
3890 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
3891}
3892
3893/**
3894 * sw_setup - setup the switch
3895 * @hw: The hardware instance.
3896 *
3897 * This routine setup the hardware switch engine for default operation.
3898 */
3899static void sw_setup(struct ksz_hw *hw)
3900{
3901 int port;
3902
3903 sw_set_global_ctrl(hw);
3904
3905 /* Enable switch broadcast storm protection at 10% percent rate. */
3906 sw_init_broad_storm(hw);
3907 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
3908 for (port = 0; port < SWITCH_PORT_NUM; port++)
3909 sw_ena_broad_storm(hw, port);
3910
3911 sw_init_prio(hw);
3912
3913 sw_init_mirror(hw);
3914
3915 sw_init_prio_rate(hw);
3916
3917 sw_init_vlan(hw);
3918
3919 if (hw->features & STP_SUPPORT)
3920 sw_init_stp(hw);
3921 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
3922 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
3923 hw->overrides |= PAUSE_FLOW_CTRL;
3924 sw_enable(hw, 1);
3925}
3926
3927/**
3928 * ksz_start_timer - start kernel timer
3929 * @info: Kernel timer information.
3930 * @time: The time tick.
3931 *
3932 * This routine starts the kernel timer after the specified time tick.
3933 */
3934static void ksz_start_timer(struct ksz_timer_info *info, int time)
3935{
3936 info->cnt = 0;
3937 info->timer.expires = jiffies + time;
3938 add_timer(&info->timer);
3939
3940 /* infinity */
3941 info->max = -1;
3942}
3943
3944/**
3945 * ksz_stop_timer - stop kernel timer
3946 * @info: Kernel timer information.
3947 *
3948 * This routine stops the kernel timer.
3949 */
3950static void ksz_stop_timer(struct ksz_timer_info *info)
3951{
3952 if (info->max) {
3953 info->max = 0;
3954 del_timer_sync(&info->timer);
3955 }
3956}
3957
3958static void ksz_init_timer(struct ksz_timer_info *info, int period,
3959 void (*function)(struct timer_list *))
3960{
3961 info->max = 0;
3962 info->period = period;
3963 timer_setup(&info->timer, function, 0);
3964}
3965
3966static void ksz_update_timer(struct ksz_timer_info *info)
3967{
3968 ++info->cnt;
3969 if (info->max > 0) {
3970 if (info->cnt < info->max) {
3971 info->timer.expires = jiffies + info->period;
3972 add_timer(&info->timer);
3973 } else
3974 info->max = 0;
3975 } else if (info->max < 0) {
3976 info->timer.expires = jiffies + info->period;
3977 add_timer(&info->timer);
3978 }
3979}
3980
3981/**
3982 * ksz_alloc_soft_desc - allocate software descriptors
3983 * @desc_info: Descriptor information structure.
3984 * @transmit: Indication that descriptors are for transmit.
3985 *
3986 * This local function allocates software descriptors for manipulation in
3987 * memory.
3988 *
3989 * Return 0 if successful.
3990 */
3991static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
3992{
3993 desc_info->ring = kcalloc(desc_info->alloc, sizeof(struct ksz_desc),
3994 GFP_KERNEL);
3995 if (!desc_info->ring)
3996 return 1;
3997 hw_init_desc(desc_info, transmit);
3998 return 0;
3999}
4000
4001/**
4002 * ksz_alloc_desc - allocate hardware descriptors
4003 * @adapter: Adapter information structure.
4004 *
4005 * This local function allocates hardware descriptors for receiving and
4006 * transmitting.
4007 *
4008 * Return 0 if successful.
4009 */
4010static int ksz_alloc_desc(struct dev_info *adapter)
4011{
4012 struct ksz_hw *hw = &adapter->hw;
4013 int offset;
4014
4015 /* Allocate memory for RX & TX descriptors. */
4016 adapter->desc_pool.alloc_size =
4017 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4018 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4019 DESC_ALIGNMENT;
4020
4021 adapter->desc_pool.alloc_virt =
4022 dma_alloc_coherent(&adapter->pdev->dev,
4023 adapter->desc_pool.alloc_size,
4024 &adapter->desc_pool.dma_addr, GFP_KERNEL);
4025 if (adapter->desc_pool.alloc_virt == NULL) {
4026 adapter->desc_pool.alloc_size = 0;
4027 return 1;
4028 }
4029
4030 /* Align to the next cache line boundary. */
4031 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4032 (DESC_ALIGNMENT -
4033 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4034 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4035 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4036
4037 /* Allocate receive/transmit descriptors. */
4038 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4039 adapter->desc_pool.virt;
4040 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4041 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4042 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4043 (adapter->desc_pool.virt + offset);
4044 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4045
4046 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4047 return 1;
4048 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4049 return 1;
4050
4051 return 0;
4052}
4053
4054/**
4055 * free_dma_buf - release DMA buffer resources
4056 * @adapter: Adapter information structure.
4057 * @dma_buf: pointer to buf
4058 * @direction: to or from device
4059 *
4060 * This routine is just a helper function to release the DMA buffer resources.
4061 */
4062static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4063 int direction)
4064{
4065 dma_unmap_single(&adapter->pdev->dev, dma_buf->dma, dma_buf->len,
4066 direction);
4067 dev_kfree_skb(dma_buf->skb);
4068 dma_buf->skb = NULL;
4069 dma_buf->dma = 0;
4070}
4071
4072/**
4073 * ksz_init_rx_buffers - initialize receive descriptors
4074 * @adapter: Adapter information structure.
4075 *
4076 * This routine initializes DMA buffers for receiving.
4077 */
4078static void ksz_init_rx_buffers(struct dev_info *adapter)
4079{
4080 int i;
4081 struct ksz_desc *desc;
4082 struct ksz_dma_buf *dma_buf;
4083 struct ksz_hw *hw = &adapter->hw;
4084 struct ksz_desc_info *info = &hw->rx_desc_info;
4085
4086 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4087 get_rx_pkt(info, &desc);
4088
4089 dma_buf = DMA_BUFFER(desc);
4090 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4091 free_dma_buf(adapter, dma_buf, DMA_FROM_DEVICE);
4092 dma_buf->len = adapter->mtu;
4093 if (!dma_buf->skb)
4094 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4095 if (dma_buf->skb && !dma_buf->dma)
4096 dma_buf->dma = dma_map_single(&adapter->pdev->dev,
4097 skb_tail_pointer(dma_buf->skb),
4098 dma_buf->len,
4099 DMA_FROM_DEVICE);
4100
4101 /* Set descriptor. */
4102 set_rx_buf(desc, dma_buf->dma);
4103 set_rx_len(desc, dma_buf->len);
4104 release_desc(desc);
4105 }
4106}
4107
4108/**
4109 * ksz_alloc_mem - allocate memory for hardware descriptors
4110 * @adapter: Adapter information structure.
4111 *
4112 * This function allocates memory for use by hardware descriptors for receiving
4113 * and transmitting.
4114 *
4115 * Return 0 if successful.
4116 */
4117static int ksz_alloc_mem(struct dev_info *adapter)
4118{
4119 struct ksz_hw *hw = &adapter->hw;
4120
4121 /* Determine the number of receive and transmit descriptors. */
4122 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4123 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4124
4125 /* Determine how many descriptors to skip transmit interrupt. */
4126 hw->tx_int_cnt = 0;
4127 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4128 if (hw->tx_int_mask > 8)
4129 hw->tx_int_mask = 8;
4130 while (hw->tx_int_mask) {
4131 hw->tx_int_cnt++;
4132 hw->tx_int_mask >>= 1;
4133 }
4134 if (hw->tx_int_cnt) {
4135 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4136 hw->tx_int_cnt = 0;
4137 }
4138
4139 /* Determine the descriptor size. */
4140 hw->rx_desc_info.size =
4141 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4142 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4143 hw->tx_desc_info.size =
4144 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4145 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4146 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4147 pr_alert("Hardware descriptor size not right!\n");
4148 ksz_check_desc_num(&hw->rx_desc_info);
4149 ksz_check_desc_num(&hw->tx_desc_info);
4150
4151 /* Allocate descriptors. */
4152 if (ksz_alloc_desc(adapter))
4153 return 1;
4154
4155 return 0;
4156}
4157
4158/**
4159 * ksz_free_desc - free software and hardware descriptors
4160 * @adapter: Adapter information structure.
4161 *
4162 * This local routine frees the software and hardware descriptors allocated by
4163 * ksz_alloc_desc().
4164 */
4165static void ksz_free_desc(struct dev_info *adapter)
4166{
4167 struct ksz_hw *hw = &adapter->hw;
4168
4169 /* Reset descriptor. */
4170 hw->rx_desc_info.ring_virt = NULL;
4171 hw->tx_desc_info.ring_virt = NULL;
4172 hw->rx_desc_info.ring_phys = 0;
4173 hw->tx_desc_info.ring_phys = 0;
4174
4175 /* Free memory. */
4176 if (adapter->desc_pool.alloc_virt)
4177 dma_free_coherent(&adapter->pdev->dev,
4178 adapter->desc_pool.alloc_size,
4179 adapter->desc_pool.alloc_virt,
4180 adapter->desc_pool.dma_addr);
4181
4182 /* Reset resource pool. */
4183 adapter->desc_pool.alloc_size = 0;
4184 adapter->desc_pool.alloc_virt = NULL;
4185
4186 kfree(hw->rx_desc_info.ring);
4187 hw->rx_desc_info.ring = NULL;
4188 kfree(hw->tx_desc_info.ring);
4189 hw->tx_desc_info.ring = NULL;
4190}
4191
4192/**
4193 * ksz_free_buffers - free buffers used in the descriptors
4194 * @adapter: Adapter information structure.
4195 * @desc_info: Descriptor information structure.
4196 * @direction: to or from device
4197 *
4198 * This local routine frees buffers used in the DMA buffers.
4199 */
4200static void ksz_free_buffers(struct dev_info *adapter,
4201 struct ksz_desc_info *desc_info, int direction)
4202{
4203 int i;
4204 struct ksz_dma_buf *dma_buf;
4205 struct ksz_desc *desc = desc_info->ring;
4206
4207 for (i = 0; i < desc_info->alloc; i++) {
4208 dma_buf = DMA_BUFFER(desc);
4209 if (dma_buf->skb)
4210 free_dma_buf(adapter, dma_buf, direction);
4211 desc++;
4212 }
4213}
4214
4215/**
4216 * ksz_free_mem - free all resources used by descriptors
4217 * @adapter: Adapter information structure.
4218 *
4219 * This local routine frees all the resources allocated by ksz_alloc_mem().
4220 */
4221static void ksz_free_mem(struct dev_info *adapter)
4222{
4223 /* Free transmit buffers. */
4224 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info, DMA_TO_DEVICE);
4225
4226 /* Free receive buffers. */
4227 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info, DMA_FROM_DEVICE);
4228
4229 /* Free descriptors. */
4230 ksz_free_desc(adapter);
4231}
4232
4233static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4234 u64 *counter)
4235{
4236 int i;
4237 int mib;
4238 int port;
4239 struct ksz_port_mib *port_mib;
4240
4241 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4242 for (i = 0, port = first; i < cnt; i++, port++) {
4243 port_mib = &hw->port_mib[port];
4244 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4245 counter[mib] += port_mib->counter[mib];
4246 }
4247}
4248
4249/**
4250 * send_packet - send packet
4251 * @skb: Socket buffer.
4252 * @dev: Network device.
4253 *
4254 * This routine is used to send a packet out to the network.
4255 */
4256static void send_packet(struct sk_buff *skb, struct net_device *dev)
4257{
4258 struct ksz_desc *desc;
4259 struct ksz_desc *first;
4260 struct dev_priv *priv = netdev_priv(dev);
4261 struct dev_info *hw_priv = priv->adapter;
4262 struct ksz_hw *hw = &hw_priv->hw;
4263 struct ksz_desc_info *info = &hw->tx_desc_info;
4264 struct ksz_dma_buf *dma_buf;
4265 int len;
4266 int last_frag = skb_shinfo(skb)->nr_frags;
4267
4268 /*
4269 * KSZ8842 with multiple device interfaces needs to be told which port
4270 * to send.
4271 */
4272 if (hw->dev_count > 1)
4273 hw->dst_ports = 1 << priv->port.first_port;
4274
4275 /* Hardware will pad the length to 60. */
4276 len = skb->len;
4277
4278 /* Remember the very first descriptor. */
4279 first = info->cur;
4280 desc = first;
4281
4282 dma_buf = DMA_BUFFER(desc);
4283 if (last_frag) {
4284 int frag;
4285 skb_frag_t *this_frag;
4286
4287 dma_buf->len = skb_headlen(skb);
4288
4289 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev, skb->data,
4290 dma_buf->len, DMA_TO_DEVICE);
4291 set_tx_buf(desc, dma_buf->dma);
4292 set_tx_len(desc, dma_buf->len);
4293
4294 frag = 0;
4295 do {
4296 this_frag = &skb_shinfo(skb)->frags[frag];
4297
4298 /* Get a new descriptor. */
4299 get_tx_pkt(info, &desc);
4300
4301 /* Keep track of descriptors used so far. */
4302 ++hw->tx_int_cnt;
4303
4304 dma_buf = DMA_BUFFER(desc);
4305 dma_buf->len = skb_frag_size(this_frag);
4306
4307 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev,
4308 skb_frag_address(this_frag),
4309 dma_buf->len,
4310 DMA_TO_DEVICE);
4311 set_tx_buf(desc, dma_buf->dma);
4312 set_tx_len(desc, dma_buf->len);
4313
4314 frag++;
4315 if (frag == last_frag)
4316 break;
4317
4318 /* Do not release the last descriptor here. */
4319 release_desc(desc);
4320 } while (1);
4321
4322 /* current points to the last descriptor. */
4323 info->cur = desc;
4324
4325 /* Release the first descriptor. */
4326 release_desc(first);
4327 } else {
4328 dma_buf->len = len;
4329
4330 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev, skb->data,
4331 dma_buf->len, DMA_TO_DEVICE);
4332 set_tx_buf(desc, dma_buf->dma);
4333 set_tx_len(desc, dma_buf->len);
4334 }
4335
4336 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4337 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4338 (desc)->sw.buf.tx.csum_gen_udp = 1;
4339 }
4340
4341 /*
4342 * The last descriptor holds the packet so that it can be returned to
4343 * network subsystem after all descriptors are transmitted.
4344 */
4345 dma_buf->skb = skb;
4346
4347 hw_send_pkt(hw);
4348
4349 /* Update transmit statistics. */
4350 dev->stats.tx_packets++;
4351 dev->stats.tx_bytes += len;
4352}
4353
4354/**
4355 * transmit_cleanup - clean up transmit descriptors
4356 * @hw_priv: Network device.
4357 * @normal: break if owned
4358 *
4359 * This routine is called to clean up the transmitted buffers.
4360 */
4361static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4362{
4363 int last;
4364 union desc_stat status;
4365 struct ksz_hw *hw = &hw_priv->hw;
4366 struct ksz_desc_info *info = &hw->tx_desc_info;
4367 struct ksz_desc *desc;
4368 struct ksz_dma_buf *dma_buf;
4369 struct net_device *dev = NULL;
4370
4371 spin_lock_irq(&hw_priv->hwlock);
4372 last = info->last;
4373
4374 while (info->avail < info->alloc) {
4375 /* Get next descriptor which is not hardware owned. */
4376 desc = &info->ring[last];
4377 status.data = le32_to_cpu(desc->phw->ctrl.data);
4378 if (status.tx.hw_owned) {
4379 if (normal)
4380 break;
4381 else
4382 reset_desc(desc, status);
4383 }
4384
4385 dma_buf = DMA_BUFFER(desc);
4386 dma_unmap_single(&hw_priv->pdev->dev, dma_buf->dma,
4387 dma_buf->len, DMA_TO_DEVICE);
4388
4389 /* This descriptor contains the last buffer in the packet. */
4390 if (dma_buf->skb) {
4391 dev = dma_buf->skb->dev;
4392
4393 /* Release the packet back to network subsystem. */
4394 dev_kfree_skb_irq(dma_buf->skb);
4395 dma_buf->skb = NULL;
4396 }
4397
4398 /* Free the transmitted descriptor. */
4399 last++;
4400 last &= info->mask;
4401 info->avail++;
4402 }
4403 info->last = last;
4404 spin_unlock_irq(&hw_priv->hwlock);
4405
4406 /* Notify the network subsystem that the packet has been sent. */
4407 if (dev)
4408 netif_trans_update(dev);
4409}
4410
4411/**
4412 * tx_done - transmit done processing
4413 * @hw_priv: Network device.
4414 *
4415 * This routine is called when the transmit interrupt is triggered, indicating
4416 * either a packet is sent successfully or there are transmit errors.
4417 */
4418static void tx_done(struct dev_info *hw_priv)
4419{
4420 struct ksz_hw *hw = &hw_priv->hw;
4421 int port;
4422
4423 transmit_cleanup(hw_priv, 1);
4424
4425 for (port = 0; port < hw->dev_count; port++) {
4426 struct net_device *dev = hw->port_info[port].pdev;
4427
4428 if (netif_running(dev) && netif_queue_stopped(dev))
4429 netif_wake_queue(dev);
4430 }
4431}
4432
4433static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4434{
4435 skb->dev = old->dev;
4436 skb->protocol = old->protocol;
4437 skb->ip_summed = old->ip_summed;
4438 skb->csum = old->csum;
4439 skb_set_network_header(skb, ETH_HLEN);
4440
4441 dev_consume_skb_any(old);
4442}
4443
4444/**
4445 * netdev_tx - send out packet
4446 * @skb: Socket buffer.
4447 * @dev: Network device.
4448 *
4449 * This function is used by the upper network layer to send out a packet.
4450 *
4451 * Return 0 if successful; otherwise an error code indicating failure.
4452 */
4453static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev)
4454{
4455 struct dev_priv *priv = netdev_priv(dev);
4456 struct dev_info *hw_priv = priv->adapter;
4457 struct ksz_hw *hw = &hw_priv->hw;
4458 int left;
4459 int num = 1;
4460 int rc = 0;
4461
4462 if (hw->features & SMALL_PACKET_TX_BUG) {
4463 struct sk_buff *org_skb = skb;
4464
4465 if (skb->len <= 48) {
4466 if (skb_end_pointer(skb) - skb->data >= 50) {
4467 memset(&skb->data[skb->len], 0, 50 - skb->len);
4468 skb->len = 50;
4469 } else {
4470 skb = netdev_alloc_skb(dev, 50);
4471 if (!skb)
4472 return NETDEV_TX_BUSY;
4473 memcpy(skb->data, org_skb->data, org_skb->len);
4474 memset(&skb->data[org_skb->len], 0,
4475 50 - org_skb->len);
4476 skb->len = 50;
4477 copy_old_skb(org_skb, skb);
4478 }
4479 }
4480 }
4481
4482 spin_lock_irq(&hw_priv->hwlock);
4483
4484 num = skb_shinfo(skb)->nr_frags + 1;
4485 left = hw_alloc_pkt(hw, skb->len, num);
4486 if (left) {
4487 if (left < num ||
4488 (CHECKSUM_PARTIAL == skb->ip_summed &&
4489 skb->protocol == htons(ETH_P_IPV6))) {
4490 struct sk_buff *org_skb = skb;
4491
4492 skb = netdev_alloc_skb(dev, org_skb->len);
4493 if (!skb) {
4494 rc = NETDEV_TX_BUSY;
4495 goto unlock;
4496 }
4497 skb_copy_and_csum_dev(org_skb, skb->data);
4498 org_skb->ip_summed = CHECKSUM_NONE;
4499 skb->len = org_skb->len;
4500 copy_old_skb(org_skb, skb);
4501 }
4502 send_packet(skb, dev);
4503 if (left <= num)
4504 netif_stop_queue(dev);
4505 } else {
4506 /* Stop the transmit queue until packet is allocated. */
4507 netif_stop_queue(dev);
4508 rc = NETDEV_TX_BUSY;
4509 }
4510unlock:
4511 spin_unlock_irq(&hw_priv->hwlock);
4512
4513 return rc;
4514}
4515
4516/**
4517 * netdev_tx_timeout - transmit timeout processing
4518 * @dev: Network device.
4519 * @txqueue: index of hanging queue
4520 *
4521 * This routine is called when the transmit timer expires. That indicates the
4522 * hardware is not running correctly because transmit interrupts are not
4523 * triggered to free up resources so that the transmit routine can continue
4524 * sending out packets. The hardware is reset to correct the problem.
4525 */
4526static void netdev_tx_timeout(struct net_device *dev, unsigned int txqueue)
4527{
4528 static unsigned long last_reset;
4529
4530 struct dev_priv *priv = netdev_priv(dev);
4531 struct dev_info *hw_priv = priv->adapter;
4532 struct ksz_hw *hw = &hw_priv->hw;
4533 int port;
4534
4535 if (hw->dev_count > 1) {
4536 /*
4537 * Only reset the hardware if time between calls is long
4538 * enough.
4539 */
4540 if (time_before_eq(jiffies, last_reset + dev->watchdog_timeo))
4541 hw_priv = NULL;
4542 }
4543
4544 last_reset = jiffies;
4545 if (hw_priv) {
4546 hw_dis_intr(hw);
4547 hw_disable(hw);
4548
4549 transmit_cleanup(hw_priv, 0);
4550 hw_reset_pkts(&hw->rx_desc_info);
4551 hw_reset_pkts(&hw->tx_desc_info);
4552 ksz_init_rx_buffers(hw_priv);
4553
4554 hw_reset(hw);
4555
4556 hw_set_desc_base(hw,
4557 hw->tx_desc_info.ring_phys,
4558 hw->rx_desc_info.ring_phys);
4559 hw_set_addr(hw);
4560 if (hw->all_multi)
4561 hw_set_multicast(hw, hw->all_multi);
4562 else if (hw->multi_list_size)
4563 hw_set_grp_addr(hw);
4564
4565 if (hw->dev_count > 1) {
4566 hw_set_add_addr(hw);
4567 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4568 struct net_device *port_dev;
4569
4570 port_set_stp_state(hw, port,
4571 STP_STATE_DISABLED);
4572
4573 port_dev = hw->port_info[port].pdev;
4574 if (netif_running(port_dev))
4575 port_set_stp_state(hw, port,
4576 STP_STATE_SIMPLE);
4577 }
4578 }
4579
4580 hw_enable(hw);
4581 hw_ena_intr(hw);
4582 }
4583
4584 netif_trans_update(dev);
4585 netif_wake_queue(dev);
4586}
4587
4588static inline void csum_verified(struct sk_buff *skb)
4589{
4590 unsigned short protocol;
4591 struct iphdr *iph;
4592
4593 protocol = skb->protocol;
4594 skb_reset_network_header(skb);
4595 iph = (struct iphdr *) skb_network_header(skb);
4596 if (protocol == htons(ETH_P_8021Q)) {
4597 protocol = iph->tot_len;
4598 skb_set_network_header(skb, VLAN_HLEN);
4599 iph = (struct iphdr *) skb_network_header(skb);
4600 }
4601 if (protocol == htons(ETH_P_IP)) {
4602 if (iph->protocol == IPPROTO_TCP)
4603 skb->ip_summed = CHECKSUM_UNNECESSARY;
4604 }
4605}
4606
4607static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
4608 struct ksz_desc *desc, union desc_stat status)
4609{
4610 int packet_len;
4611 struct dev_priv *priv = netdev_priv(dev);
4612 struct dev_info *hw_priv = priv->adapter;
4613 struct ksz_dma_buf *dma_buf;
4614 struct sk_buff *skb;
4615
4616 /* Received length includes 4-byte CRC. */
4617 packet_len = status.rx.frame_len - 4;
4618
4619 dma_buf = DMA_BUFFER(desc);
4620 dma_sync_single_for_cpu(&hw_priv->pdev->dev, dma_buf->dma,
4621 packet_len + 4, DMA_FROM_DEVICE);
4622
4623 do {
4624 /* skb->data != skb->head */
4625 skb = netdev_alloc_skb(dev, packet_len + 2);
4626 if (!skb) {
4627 dev->stats.rx_dropped++;
4628 return -ENOMEM;
4629 }
4630
4631 /*
4632 * Align socket buffer in 4-byte boundary for better
4633 * performance.
4634 */
4635 skb_reserve(skb, 2);
4636
4637 skb_put_data(skb, dma_buf->skb->data, packet_len);
4638 } while (0);
4639
4640 skb->protocol = eth_type_trans(skb, dev);
4641
4642 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
4643 csum_verified(skb);
4644
4645 /* Update receive statistics. */
4646 dev->stats.rx_packets++;
4647 dev->stats.rx_bytes += packet_len;
4648
4649 /* Notify upper layer for received packet. */
4650 netif_rx(skb);
4651
4652 return 0;
4653}
4654
4655static int dev_rcv_packets(struct dev_info *hw_priv)
4656{
4657 int next;
4658 union desc_stat status;
4659 struct ksz_hw *hw = &hw_priv->hw;
4660 struct net_device *dev = hw->port_info[0].pdev;
4661 struct ksz_desc_info *info = &hw->rx_desc_info;
4662 int left = info->alloc;
4663 struct ksz_desc *desc;
4664 int received = 0;
4665
4666 next = info->next;
4667 while (left--) {
4668 /* Get next descriptor which is not hardware owned. */
4669 desc = &info->ring[next];
4670 status.data = le32_to_cpu(desc->phw->ctrl.data);
4671 if (status.rx.hw_owned)
4672 break;
4673
4674 /* Status valid only when last descriptor bit is set. */
4675 if (status.rx.last_desc && status.rx.first_desc) {
4676 if (rx_proc(dev, hw, desc, status))
4677 goto release_packet;
4678 received++;
4679 }
4680
4681release_packet:
4682 release_desc(desc);
4683 next++;
4684 next &= info->mask;
4685 }
4686 info->next = next;
4687
4688 return received;
4689}
4690
4691static int port_rcv_packets(struct dev_info *hw_priv)
4692{
4693 int next;
4694 union desc_stat status;
4695 struct ksz_hw *hw = &hw_priv->hw;
4696 struct net_device *dev = hw->port_info[0].pdev;
4697 struct ksz_desc_info *info = &hw->rx_desc_info;
4698 int left = info->alloc;
4699 struct ksz_desc *desc;
4700 int received = 0;
4701
4702 next = info->next;
4703 while (left--) {
4704 /* Get next descriptor which is not hardware owned. */
4705 desc = &info->ring[next];
4706 status.data = le32_to_cpu(desc->phw->ctrl.data);
4707 if (status.rx.hw_owned)
4708 break;
4709
4710 if (hw->dev_count > 1) {
4711 /* Get received port number. */
4712 int p = HW_TO_DEV_PORT(status.rx.src_port);
4713
4714 dev = hw->port_info[p].pdev;
4715 if (!netif_running(dev))
4716 goto release_packet;
4717 }
4718
4719 /* Status valid only when last descriptor bit is set. */
4720 if (status.rx.last_desc && status.rx.first_desc) {
4721 if (rx_proc(dev, hw, desc, status))
4722 goto release_packet;
4723 received++;
4724 }
4725
4726release_packet:
4727 release_desc(desc);
4728 next++;
4729 next &= info->mask;
4730 }
4731 info->next = next;
4732
4733 return received;
4734}
4735
4736static int dev_rcv_special(struct dev_info *hw_priv)
4737{
4738 int next;
4739 union desc_stat status;
4740 struct ksz_hw *hw = &hw_priv->hw;
4741 struct net_device *dev = hw->port_info[0].pdev;
4742 struct ksz_desc_info *info = &hw->rx_desc_info;
4743 int left = info->alloc;
4744 struct ksz_desc *desc;
4745 int received = 0;
4746
4747 next = info->next;
4748 while (left--) {
4749 /* Get next descriptor which is not hardware owned. */
4750 desc = &info->ring[next];
4751 status.data = le32_to_cpu(desc->phw->ctrl.data);
4752 if (status.rx.hw_owned)
4753 break;
4754
4755 if (hw->dev_count > 1) {
4756 /* Get received port number. */
4757 int p = HW_TO_DEV_PORT(status.rx.src_port);
4758
4759 dev = hw->port_info[p].pdev;
4760 if (!netif_running(dev))
4761 goto release_packet;
4762 }
4763
4764 /* Status valid only when last descriptor bit is set. */
4765 if (status.rx.last_desc && status.rx.first_desc) {
4766 /*
4767 * Receive without error. With receive errors
4768 * disabled, packets with receive errors will be
4769 * dropped, so no need to check the error bit.
4770 */
4771 if (!status.rx.error || (status.data &
4772 KS_DESC_RX_ERROR_COND) ==
4773 KS_DESC_RX_ERROR_TOO_LONG) {
4774 if (rx_proc(dev, hw, desc, status))
4775 goto release_packet;
4776 received++;
4777 } else {
4778 struct dev_priv *priv = netdev_priv(dev);
4779
4780 /* Update receive error statistics. */
4781 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
4782 }
4783 }
4784
4785release_packet:
4786 release_desc(desc);
4787 next++;
4788 next &= info->mask;
4789 }
4790 info->next = next;
4791
4792 return received;
4793}
4794
4795static void rx_proc_task(struct tasklet_struct *t)
4796{
4797 struct dev_info *hw_priv = from_tasklet(hw_priv, t, rx_tasklet);
4798 struct ksz_hw *hw = &hw_priv->hw;
4799
4800 if (!hw->enabled)
4801 return;
4802 if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
4803
4804 /* In case receive process is suspended because of overrun. */
4805 hw_resume_rx(hw);
4806
4807 /* tasklets are interruptible. */
4808 spin_lock_irq(&hw_priv->hwlock);
4809 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
4810 spin_unlock_irq(&hw_priv->hwlock);
4811 } else {
4812 hw_ack_intr(hw, KS884X_INT_RX);
4813 tasklet_schedule(&hw_priv->rx_tasklet);
4814 }
4815}
4816
4817static void tx_proc_task(struct tasklet_struct *t)
4818{
4819 struct dev_info *hw_priv = from_tasklet(hw_priv, t, tx_tasklet);
4820 struct ksz_hw *hw = &hw_priv->hw;
4821
4822 hw_ack_intr(hw, KS884X_INT_TX_MASK);
4823
4824 tx_done(hw_priv);
4825
4826 /* tasklets are interruptible. */
4827 spin_lock_irq(&hw_priv->hwlock);
4828 hw_turn_on_intr(hw, KS884X_INT_TX);
4829 spin_unlock_irq(&hw_priv->hwlock);
4830}
4831
4832static inline void handle_rx_stop(struct ksz_hw *hw)
4833{
4834 /* Receive just has been stopped. */
4835 if (0 == hw->rx_stop)
4836 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
4837 else if (hw->rx_stop > 1) {
4838 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
4839 hw_start_rx(hw);
4840 } else {
4841 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
4842 hw->rx_stop = 0;
4843 }
4844 } else
4845 /* Receive just has been started. */
4846 hw->rx_stop++;
4847}
4848
4849/**
4850 * netdev_intr - interrupt handling
4851 * @irq: Interrupt number.
4852 * @dev_id: Network device.
4853 *
4854 * This function is called by upper network layer to signal interrupt.
4855 *
4856 * Return IRQ_HANDLED if interrupt is handled.
4857 */
4858static irqreturn_t netdev_intr(int irq, void *dev_id)
4859{
4860 uint int_enable = 0;
4861 struct net_device *dev = (struct net_device *) dev_id;
4862 struct dev_priv *priv = netdev_priv(dev);
4863 struct dev_info *hw_priv = priv->adapter;
4864 struct ksz_hw *hw = &hw_priv->hw;
4865
4866 spin_lock(&hw_priv->hwlock);
4867
4868 hw_read_intr(hw, &int_enable);
4869
4870 /* Not our interrupt! */
4871 if (!int_enable) {
4872 spin_unlock(&hw_priv->hwlock);
4873 return IRQ_NONE;
4874 }
4875
4876 do {
4877 hw_ack_intr(hw, int_enable);
4878 int_enable &= hw->intr_mask;
4879
4880 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
4881 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
4882 tasklet_schedule(&hw_priv->tx_tasklet);
4883 }
4884
4885 if (likely(int_enable & KS884X_INT_RX)) {
4886 hw_dis_intr_bit(hw, KS884X_INT_RX);
4887 tasklet_schedule(&hw_priv->rx_tasklet);
4888 }
4889
4890 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
4891 dev->stats.rx_fifo_errors++;
4892 hw_resume_rx(hw);
4893 }
4894
4895 if (unlikely(int_enable & KS884X_INT_PHY)) {
4896 struct ksz_port *port = &priv->port;
4897
4898 hw->features |= LINK_INT_WORKING;
4899 port_get_link_speed(port);
4900 }
4901
4902 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
4903 handle_rx_stop(hw);
4904 break;
4905 }
4906
4907 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
4908 u32 data;
4909
4910 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
4911 pr_info("Tx stopped\n");
4912 data = readl(hw->io + KS_DMA_TX_CTRL);
4913 if (!(data & DMA_TX_ENABLE))
4914 pr_info("Tx disabled\n");
4915 break;
4916 }
4917 } while (0);
4918
4919 hw_ena_intr(hw);
4920
4921 spin_unlock(&hw_priv->hwlock);
4922
4923 return IRQ_HANDLED;
4924}
4925
4926/*
4927 * Linux network device functions
4928 */
4929
4930
4931#ifdef CONFIG_NET_POLL_CONTROLLER
4932static void netdev_netpoll(struct net_device *dev)
4933{
4934 struct dev_priv *priv = netdev_priv(dev);
4935 struct dev_info *hw_priv = priv->adapter;
4936
4937 hw_dis_intr(&hw_priv->hw);
4938 netdev_intr(dev->irq, dev);
4939}
4940#endif
4941
4942static void bridge_change(struct ksz_hw *hw)
4943{
4944 int port;
4945 u8 member;
4946 struct ksz_switch *sw = hw->ksz_switch;
4947
4948 /* No ports in forwarding state. */
4949 if (!sw->member) {
4950 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4951 sw_block_addr(hw);
4952 }
4953 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4954 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
4955 member = HOST_MASK | sw->member;
4956 else
4957 member = HOST_MASK | (1 << port);
4958 if (member != sw->port_cfg[port].member)
4959 sw_cfg_port_base_vlan(hw, port, member);
4960 }
4961}
4962
4963/**
4964 * netdev_close - close network device
4965 * @dev: Network device.
4966 *
4967 * This function process the close operation of network device. This is caused
4968 * by the user command "ifconfig ethX down."
4969 *
4970 * Return 0 if successful; otherwise an error code indicating failure.
4971 */
4972static int netdev_close(struct net_device *dev)
4973{
4974 struct dev_priv *priv = netdev_priv(dev);
4975 struct dev_info *hw_priv = priv->adapter;
4976 struct ksz_port *port = &priv->port;
4977 struct ksz_hw *hw = &hw_priv->hw;
4978 int pi;
4979
4980 netif_stop_queue(dev);
4981
4982 ksz_stop_timer(&priv->monitor_timer_info);
4983
4984 /* Need to shut the port manually in multiple device interfaces mode. */
4985 if (hw->dev_count > 1) {
4986 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
4987
4988 /* Port is closed. Need to change bridge setting. */
4989 if (hw->features & STP_SUPPORT) {
4990 pi = 1 << port->first_port;
4991 if (hw->ksz_switch->member & pi) {
4992 hw->ksz_switch->member &= ~pi;
4993 bridge_change(hw);
4994 }
4995 }
4996 }
4997 if (port->first_port > 0)
4998 hw_del_addr(hw, dev->dev_addr);
4999 if (!hw_priv->wol_enable)
5000 port_set_power_saving(port, true);
5001
5002 if (priv->multicast)
5003 --hw->all_multi;
5004 if (priv->promiscuous)
5005 --hw->promiscuous;
5006
5007 hw_priv->opened--;
5008 if (!(hw_priv->opened)) {
5009 ksz_stop_timer(&hw_priv->mib_timer_info);
5010 flush_work(&hw_priv->mib_read);
5011
5012 hw_dis_intr(hw);
5013 hw_disable(hw);
5014 hw_clr_multicast(hw);
5015
5016 /* Delay for receive task to stop scheduling itself. */
5017 msleep(2000 / HZ);
5018
5019 tasklet_kill(&hw_priv->rx_tasklet);
5020 tasklet_kill(&hw_priv->tx_tasklet);
5021 free_irq(dev->irq, hw_priv->dev);
5022
5023 transmit_cleanup(hw_priv, 0);
5024 hw_reset_pkts(&hw->rx_desc_info);
5025 hw_reset_pkts(&hw->tx_desc_info);
5026
5027 /* Clean out static MAC table when the switch is shutdown. */
5028 if (hw->features & STP_SUPPORT)
5029 sw_clr_sta_mac_table(hw);
5030 }
5031
5032 return 0;
5033}
5034
5035static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5036{
5037 if (hw->ksz_switch) {
5038 u32 data;
5039
5040 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5041 if (hw->features & RX_HUGE_FRAME)
5042 data |= SWITCH_HUGE_PACKET;
5043 else
5044 data &= ~SWITCH_HUGE_PACKET;
5045 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5046 }
5047 if (hw->features & RX_HUGE_FRAME) {
5048 hw->rx_cfg |= DMA_RX_ERROR;
5049 hw_priv->dev_rcv = dev_rcv_special;
5050 } else {
5051 hw->rx_cfg &= ~DMA_RX_ERROR;
5052 if (hw->dev_count > 1)
5053 hw_priv->dev_rcv = port_rcv_packets;
5054 else
5055 hw_priv->dev_rcv = dev_rcv_packets;
5056 }
5057}
5058
5059static int prepare_hardware(struct net_device *dev)
5060{
5061 struct dev_priv *priv = netdev_priv(dev);
5062 struct dev_info *hw_priv = priv->adapter;
5063 struct ksz_hw *hw = &hw_priv->hw;
5064 int rc = 0;
5065
5066 /* Remember the network device that requests interrupts. */
5067 hw_priv->dev = dev;
5068 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5069 if (rc)
5070 return rc;
5071 tasklet_setup(&hw_priv->rx_tasklet, rx_proc_task);
5072 tasklet_setup(&hw_priv->tx_tasklet, tx_proc_task);
5073
5074 hw->promiscuous = 0;
5075 hw->all_multi = 0;
5076 hw->multi_list_size = 0;
5077
5078 hw_reset(hw);
5079
5080 hw_set_desc_base(hw,
5081 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5082 hw_set_addr(hw);
5083 hw_cfg_huge_frame(hw_priv, hw);
5084 ksz_init_rx_buffers(hw_priv);
5085 return 0;
5086}
5087
5088static void set_media_state(struct net_device *dev, int media_state)
5089{
5090 struct dev_priv *priv = netdev_priv(dev);
5091
5092 if (media_state == priv->media_state)
5093 netif_carrier_on(dev);
5094 else
5095 netif_carrier_off(dev);
5096 netif_info(priv, link, dev, "link %s\n",
5097 media_state == priv->media_state ? "on" : "off");
5098}
5099
5100/**
5101 * netdev_open - open network device
5102 * @dev: Network device.
5103 *
5104 * This function process the open operation of network device. This is caused
5105 * by the user command "ifconfig ethX up."
5106 *
5107 * Return 0 if successful; otherwise an error code indicating failure.
5108 */
5109static int netdev_open(struct net_device *dev)
5110{
5111 struct dev_priv *priv = netdev_priv(dev);
5112 struct dev_info *hw_priv = priv->adapter;
5113 struct ksz_hw *hw = &hw_priv->hw;
5114 struct ksz_port *port = &priv->port;
5115 unsigned long next_jiffies;
5116 int i;
5117 int p;
5118 int rc = 0;
5119
5120 next_jiffies = jiffies + HZ * 2;
5121 priv->multicast = 0;
5122 priv->promiscuous = 0;
5123
5124 /* Reset device statistics. */
5125 memset(&dev->stats, 0, sizeof(struct net_device_stats));
5126 memset((void *) port->counter, 0,
5127 (sizeof(u64) * OID_COUNTER_LAST));
5128
5129 if (!(hw_priv->opened)) {
5130 rc = prepare_hardware(dev);
5131 if (rc)
5132 return rc;
5133 for (i = 0; i < hw->mib_port_cnt; i++) {
5134 next_jiffies += HZ * 1;
5135 hw_priv->counter[i].time = next_jiffies;
5136 hw->port_mib[i].state = media_disconnected;
5137 port_init_cnt(hw, i);
5138 }
5139 if (hw->ksz_switch)
5140 hw->port_mib[HOST_PORT].state = media_connected;
5141 else {
5142 hw_add_wol_bcast(hw);
5143 hw_cfg_wol_pme(hw, 0);
5144 hw_clr_wol_pme_status(&hw_priv->hw);
5145 }
5146 }
5147 port_set_power_saving(port, false);
5148
5149 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5150 /*
5151 * Initialize to invalid value so that link detection
5152 * is done.
5153 */
5154 hw->port_info[p].partner = 0xFF;
5155 hw->port_info[p].state = media_disconnected;
5156 }
5157
5158 /* Need to open the port in multiple device interfaces mode. */
5159 if (hw->dev_count > 1) {
5160 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5161 if (port->first_port > 0)
5162 hw_add_addr(hw, dev->dev_addr);
5163 }
5164
5165 port_get_link_speed(port);
5166 if (port->force_link)
5167 port_force_link_speed(port);
5168 else
5169 port_set_link_speed(port);
5170
5171 if (!(hw_priv->opened)) {
5172 hw_setup_intr(hw);
5173 hw_enable(hw);
5174 hw_ena_intr(hw);
5175
5176 if (hw->mib_port_cnt)
5177 ksz_start_timer(&hw_priv->mib_timer_info,
5178 hw_priv->mib_timer_info.period);
5179 }
5180
5181 hw_priv->opened++;
5182
5183 ksz_start_timer(&priv->monitor_timer_info,
5184 priv->monitor_timer_info.period);
5185
5186 priv->media_state = port->linked->state;
5187
5188 set_media_state(dev, media_connected);
5189 netif_start_queue(dev);
5190
5191 return 0;
5192}
5193
5194/* RX errors = rx_errors */
5195/* RX dropped = rx_dropped */
5196/* RX overruns = rx_fifo_errors */
5197/* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5198/* TX errors = tx_errors */
5199/* TX dropped = tx_dropped */
5200/* TX overruns = tx_fifo_errors */
5201/* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5202/* collisions = collisions */
5203
5204/**
5205 * netdev_query_statistics - query network device statistics
5206 * @dev: Network device.
5207 *
5208 * This function returns the statistics of the network device. The device
5209 * needs not be opened.
5210 *
5211 * Return network device statistics.
5212 */
5213static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5214{
5215 struct dev_priv *priv = netdev_priv(dev);
5216 struct ksz_port *port = &priv->port;
5217 struct ksz_hw *hw = &priv->adapter->hw;
5218 struct ksz_port_mib *mib;
5219 int i;
5220 int p;
5221
5222 dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5223 dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5224
5225 /* Reset to zero to add count later. */
5226 dev->stats.multicast = 0;
5227 dev->stats.collisions = 0;
5228 dev->stats.rx_length_errors = 0;
5229 dev->stats.rx_crc_errors = 0;
5230 dev->stats.rx_frame_errors = 0;
5231 dev->stats.tx_window_errors = 0;
5232
5233 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5234 mib = &hw->port_mib[p];
5235
5236 dev->stats.multicast += (unsigned long)
5237 mib->counter[MIB_COUNTER_RX_MULTICAST];
5238
5239 dev->stats.collisions += (unsigned long)
5240 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5241
5242 dev->stats.rx_length_errors += (unsigned long)(
5243 mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5244 mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5245 mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5246 mib->counter[MIB_COUNTER_RX_JABBER]);
5247 dev->stats.rx_crc_errors += (unsigned long)
5248 mib->counter[MIB_COUNTER_RX_CRC_ERR];
5249 dev->stats.rx_frame_errors += (unsigned long)(
5250 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5251 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5252
5253 dev->stats.tx_window_errors += (unsigned long)
5254 mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5255 }
5256
5257 return &dev->stats;
5258}
5259
5260/**
5261 * netdev_set_mac_address - set network device MAC address
5262 * @dev: Network device.
5263 * @addr: Buffer of MAC address.
5264 *
5265 * This function is used to set the MAC address of the network device.
5266 *
5267 * Return 0 to indicate success.
5268 */
5269static int netdev_set_mac_address(struct net_device *dev, void *addr)
5270{
5271 struct dev_priv *priv = netdev_priv(dev);
5272 struct dev_info *hw_priv = priv->adapter;
5273 struct ksz_hw *hw = &hw_priv->hw;
5274 struct sockaddr *mac = addr;
5275 uint interrupt;
5276
5277 if (priv->port.first_port > 0)
5278 hw_del_addr(hw, dev->dev_addr);
5279 else {
5280 hw->mac_override = 1;
5281 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN);
5282 }
5283
5284 eth_hw_addr_set(dev, mac->sa_data);
5285
5286 interrupt = hw_block_intr(hw);
5287
5288 if (priv->port.first_port > 0)
5289 hw_add_addr(hw, dev->dev_addr);
5290 else
5291 hw_set_addr(hw);
5292 hw_restore_intr(hw, interrupt);
5293
5294 return 0;
5295}
5296
5297static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5298 struct ksz_hw *hw, int promiscuous)
5299{
5300 if (promiscuous != priv->promiscuous) {
5301 u8 prev_state = hw->promiscuous;
5302
5303 if (promiscuous)
5304 ++hw->promiscuous;
5305 else
5306 --hw->promiscuous;
5307 priv->promiscuous = promiscuous;
5308
5309 /* Turn on/off promiscuous mode. */
5310 if (hw->promiscuous <= 1 && prev_state <= 1)
5311 hw_set_promiscuous(hw, hw->promiscuous);
5312
5313 /*
5314 * Port is not in promiscuous mode, meaning it is released
5315 * from the bridge.
5316 */
5317 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5318 netif_is_bridge_port(dev)) {
5319 struct ksz_switch *sw = hw->ksz_switch;
5320 int port = priv->port.first_port;
5321
5322 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5323 port = 1 << port;
5324 if (sw->member & port) {
5325 sw->member &= ~port;
5326 bridge_change(hw);
5327 }
5328 }
5329 }
5330}
5331
5332static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5333 int multicast)
5334{
5335 if (multicast != priv->multicast) {
5336 u8 all_multi = hw->all_multi;
5337
5338 if (multicast)
5339 ++hw->all_multi;
5340 else
5341 --hw->all_multi;
5342 priv->multicast = multicast;
5343
5344 /* Turn on/off all multicast mode. */
5345 if (hw->all_multi <= 1 && all_multi <= 1)
5346 hw_set_multicast(hw, hw->all_multi);
5347 }
5348}
5349
5350/**
5351 * netdev_set_rx_mode
5352 * @dev: Network device.
5353 *
5354 * This routine is used to set multicast addresses or put the network device
5355 * into promiscuous mode.
5356 */
5357static void netdev_set_rx_mode(struct net_device *dev)
5358{
5359 struct dev_priv *priv = netdev_priv(dev);
5360 struct dev_info *hw_priv = priv->adapter;
5361 struct ksz_hw *hw = &hw_priv->hw;
5362 struct netdev_hw_addr *ha;
5363 int multicast = (dev->flags & IFF_ALLMULTI);
5364
5365 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5366
5367 if (hw_priv->hw.dev_count > 1)
5368 multicast |= (dev->flags & IFF_MULTICAST);
5369 dev_set_multicast(priv, hw, multicast);
5370
5371 /* Cannot use different hashes in multiple device interfaces mode. */
5372 if (hw_priv->hw.dev_count > 1)
5373 return;
5374
5375 if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
5376 int i = 0;
5377
5378 /* List too big to support so turn on all multicast mode. */
5379 if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) {
5380 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5381 hw->multi_list_size = MAX_MULTICAST_LIST;
5382 ++hw->all_multi;
5383 hw_set_multicast(hw, hw->all_multi);
5384 }
5385 return;
5386 }
5387
5388 netdev_for_each_mc_addr(ha, dev) {
5389 if (i >= MAX_MULTICAST_LIST)
5390 break;
5391 memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN);
5392 }
5393 hw->multi_list_size = (u8) i;
5394 hw_set_grp_addr(hw);
5395 } else {
5396 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5397 --hw->all_multi;
5398 hw_set_multicast(hw, hw->all_multi);
5399 }
5400 hw->multi_list_size = 0;
5401 hw_clr_multicast(hw);
5402 }
5403}
5404
5405static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5406{
5407 struct dev_priv *priv = netdev_priv(dev);
5408 struct dev_info *hw_priv = priv->adapter;
5409 struct ksz_hw *hw = &hw_priv->hw;
5410 int hw_mtu;
5411
5412 if (netif_running(dev))
5413 return -EBUSY;
5414
5415 /* Cannot use different MTU in multiple device interfaces mode. */
5416 if (hw->dev_count > 1)
5417 if (dev != hw_priv->dev)
5418 return 0;
5419
5420 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5421 if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5422 hw->features |= RX_HUGE_FRAME;
5423 hw_mtu = MAX_RX_BUF_SIZE;
5424 } else {
5425 hw->features &= ~RX_HUGE_FRAME;
5426 hw_mtu = REGULAR_RX_BUF_SIZE;
5427 }
5428 hw_mtu = (hw_mtu + 3) & ~3;
5429 hw_priv->mtu = hw_mtu;
5430 dev->mtu = new_mtu;
5431
5432 return 0;
5433}
5434
5435/**
5436 * netdev_ioctl - I/O control processing
5437 * @dev: Network device.
5438 * @ifr: Interface request structure.
5439 * @cmd: I/O control code.
5440 *
5441 * This function is used to process I/O control calls.
5442 *
5443 * Return 0 to indicate success.
5444 */
5445static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5446{
5447 struct dev_priv *priv = netdev_priv(dev);
5448 struct dev_info *hw_priv = priv->adapter;
5449 struct ksz_hw *hw = &hw_priv->hw;
5450 struct ksz_port *port = &priv->port;
5451 int result = 0;
5452 struct mii_ioctl_data *data = if_mii(ifr);
5453
5454 if (down_interruptible(&priv->proc_sem))
5455 return -ERESTARTSYS;
5456
5457 switch (cmd) {
5458 /* Get address of MII PHY in use. */
5459 case SIOCGMIIPHY:
5460 data->phy_id = priv->id;
5461 fallthrough;
5462
5463 /* Read MII PHY register. */
5464 case SIOCGMIIREG:
5465 if (data->phy_id != priv->id || data->reg_num >= 6)
5466 result = -EIO;
5467 else
5468 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5469 &data->val_out);
5470 break;
5471
5472 /* Write MII PHY register. */
5473 case SIOCSMIIREG:
5474 if (!capable(CAP_NET_ADMIN))
5475 result = -EPERM;
5476 else if (data->phy_id != priv->id || data->reg_num >= 6)
5477 result = -EIO;
5478 else
5479 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5480 data->val_in);
5481 break;
5482
5483 default:
5484 result = -EOPNOTSUPP;
5485 }
5486
5487 up(&priv->proc_sem);
5488
5489 return result;
5490}
5491
5492/*
5493 * MII support
5494 */
5495
5496/**
5497 * mdio_read - read PHY register
5498 * @dev: Network device.
5499 * @phy_id: The PHY id.
5500 * @reg_num: The register number.
5501 *
5502 * This function returns the PHY register value.
5503 *
5504 * Return the register value.
5505 */
5506static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5507{
5508 struct dev_priv *priv = netdev_priv(dev);
5509 struct ksz_port *port = &priv->port;
5510 struct ksz_hw *hw = port->hw;
5511 u16 val_out;
5512
5513 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5514 return val_out;
5515}
5516
5517/**
5518 * mdio_write - set PHY register
5519 * @dev: Network device.
5520 * @phy_id: The PHY id.
5521 * @reg_num: The register number.
5522 * @val: The register value.
5523 *
5524 * This procedure sets the PHY register value.
5525 */
5526static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5527{
5528 struct dev_priv *priv = netdev_priv(dev);
5529 struct ksz_port *port = &priv->port;
5530 struct ksz_hw *hw = port->hw;
5531 int i;
5532 int pi;
5533
5534 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5535 hw_w_phy(hw, pi, reg_num << 1, val);
5536}
5537
5538/*
5539 * ethtool support
5540 */
5541
5542#define EEPROM_SIZE 0x40
5543
5544static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5545
5546#define ADVERTISED_ALL \
5547 (ADVERTISED_10baseT_Half | \
5548 ADVERTISED_10baseT_Full | \
5549 ADVERTISED_100baseT_Half | \
5550 ADVERTISED_100baseT_Full)
5551
5552/* These functions use the MII functions in mii.c. */
5553
5554/**
5555 * netdev_get_link_ksettings - get network device settings
5556 * @dev: Network device.
5557 * @cmd: Ethtool command.
5558 *
5559 * This function queries the PHY and returns its state in the ethtool command.
5560 *
5561 * Return 0 if successful; otherwise an error code.
5562 */
5563static int netdev_get_link_ksettings(struct net_device *dev,
5564 struct ethtool_link_ksettings *cmd)
5565{
5566 struct dev_priv *priv = netdev_priv(dev);
5567 struct dev_info *hw_priv = priv->adapter;
5568
5569 mutex_lock(&hw_priv->lock);
5570 mii_ethtool_get_link_ksettings(&priv->mii_if, cmd);
5571 ethtool_link_ksettings_add_link_mode(cmd, advertising, TP);
5572 mutex_unlock(&hw_priv->lock);
5573
5574 /* Save advertised settings for workaround in next function. */
5575 ethtool_convert_link_mode_to_legacy_u32(&priv->advertising,
5576 cmd->link_modes.advertising);
5577
5578 return 0;
5579}
5580
5581/**
5582 * netdev_set_link_ksettings - set network device settings
5583 * @dev: Network device.
5584 * @cmd: Ethtool command.
5585 *
5586 * This function sets the PHY according to the ethtool command.
5587 *
5588 * Return 0 if successful; otherwise an error code.
5589 */
5590static int netdev_set_link_ksettings(struct net_device *dev,
5591 const struct ethtool_link_ksettings *cmd)
5592{
5593 struct dev_priv *priv = netdev_priv(dev);
5594 struct dev_info *hw_priv = priv->adapter;
5595 struct ksz_port *port = &priv->port;
5596 struct ethtool_link_ksettings copy_cmd;
5597 u32 speed = cmd->base.speed;
5598 u32 advertising;
5599 int rc;
5600
5601 ethtool_convert_link_mode_to_legacy_u32(&advertising,
5602 cmd->link_modes.advertising);
5603
5604 /*
5605 * ethtool utility does not change advertised setting if auto
5606 * negotiation is not specified explicitly.
5607 */
5608 if (cmd->base.autoneg && priv->advertising == advertising) {
5609 advertising |= ADVERTISED_ALL;
5610 if (10 == speed)
5611 advertising &=
5612 ~(ADVERTISED_100baseT_Full |
5613 ADVERTISED_100baseT_Half);
5614 else if (100 == speed)
5615 advertising &=
5616 ~(ADVERTISED_10baseT_Full |
5617 ADVERTISED_10baseT_Half);
5618 if (0 == cmd->base.duplex)
5619 advertising &=
5620 ~(ADVERTISED_100baseT_Full |
5621 ADVERTISED_10baseT_Full);
5622 else if (1 == cmd->base.duplex)
5623 advertising &=
5624 ~(ADVERTISED_100baseT_Half |
5625 ADVERTISED_10baseT_Half);
5626 }
5627 mutex_lock(&hw_priv->lock);
5628 if (cmd->base.autoneg &&
5629 (advertising & ADVERTISED_ALL) == ADVERTISED_ALL) {
5630 port->duplex = 0;
5631 port->speed = 0;
5632 port->force_link = 0;
5633 } else {
5634 port->duplex = cmd->base.duplex + 1;
5635 if (1000 != speed)
5636 port->speed = speed;
5637 if (cmd->base.autoneg)
5638 port->force_link = 0;
5639 else
5640 port->force_link = 1;
5641 }
5642
5643 memcpy(©_cmd, cmd, sizeof(copy_cmd));
5644 ethtool_convert_legacy_u32_to_link_mode(copy_cmd.link_modes.advertising,
5645 advertising);
5646 rc = mii_ethtool_set_link_ksettings(
5647 &priv->mii_if,
5648 (const struct ethtool_link_ksettings *)©_cmd);
5649 mutex_unlock(&hw_priv->lock);
5650 return rc;
5651}
5652
5653/**
5654 * netdev_nway_reset - restart auto-negotiation
5655 * @dev: Network device.
5656 *
5657 * This function restarts the PHY for auto-negotiation.
5658 *
5659 * Return 0 if successful; otherwise an error code.
5660 */
5661static int netdev_nway_reset(struct net_device *dev)
5662{
5663 struct dev_priv *priv = netdev_priv(dev);
5664 struct dev_info *hw_priv = priv->adapter;
5665 int rc;
5666
5667 mutex_lock(&hw_priv->lock);
5668 rc = mii_nway_restart(&priv->mii_if);
5669 mutex_unlock(&hw_priv->lock);
5670 return rc;
5671}
5672
5673/**
5674 * netdev_get_link - get network device link status
5675 * @dev: Network device.
5676 *
5677 * This function gets the link status from the PHY.
5678 *
5679 * Return true if PHY is linked and false otherwise.
5680 */
5681static u32 netdev_get_link(struct net_device *dev)
5682{
5683 struct dev_priv *priv = netdev_priv(dev);
5684 int rc;
5685
5686 rc = mii_link_ok(&priv->mii_if);
5687 return rc;
5688}
5689
5690/**
5691 * netdev_get_drvinfo - get network driver information
5692 * @dev: Network device.
5693 * @info: Ethtool driver info data structure.
5694 *
5695 * This procedure returns the driver information.
5696 */
5697static void netdev_get_drvinfo(struct net_device *dev,
5698 struct ethtool_drvinfo *info)
5699{
5700 struct dev_priv *priv = netdev_priv(dev);
5701 struct dev_info *hw_priv = priv->adapter;
5702
5703 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
5704 strscpy(info->version, DRV_VERSION, sizeof(info->version));
5705 strscpy(info->bus_info, pci_name(hw_priv->pdev),
5706 sizeof(info->bus_info));
5707}
5708
5709static struct hw_regs {
5710 int start;
5711 int end;
5712} hw_regs_range[] = {
5713 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS },
5714 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI },
5715 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
5716 { KS884X_SIDER_P, KS8842_SGCR7_P },
5717 { KS8842_MACAR1_P, KS8842_TOSR8_P },
5718 { KS884X_P1MBCR_P, KS8842_P3ERCR_P },
5719 { 0, 0 }
5720};
5721
5722/**
5723 * netdev_get_regs_len - get length of register dump
5724 * @dev: Network device.
5725 *
5726 * This function returns the length of the register dump.
5727 *
5728 * Return length of the register dump.
5729 */
5730static int netdev_get_regs_len(struct net_device *dev)
5731{
5732 struct hw_regs *range = hw_regs_range;
5733 int regs_len = 0x10 * sizeof(u32);
5734
5735 while (range->end > range->start) {
5736 regs_len += (range->end - range->start + 3) / 4 * 4;
5737 range++;
5738 }
5739 return regs_len;
5740}
5741
5742/**
5743 * netdev_get_regs - get register dump
5744 * @dev: Network device.
5745 * @regs: Ethtool registers data structure.
5746 * @ptr: Buffer to store the register values.
5747 *
5748 * This procedure dumps the register values in the provided buffer.
5749 */
5750static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
5751 void *ptr)
5752{
5753 struct dev_priv *priv = netdev_priv(dev);
5754 struct dev_info *hw_priv = priv->adapter;
5755 struct ksz_hw *hw = &hw_priv->hw;
5756 int *buf = (int *) ptr;
5757 struct hw_regs *range = hw_regs_range;
5758 int len;
5759
5760 mutex_lock(&hw_priv->lock);
5761 regs->version = 0;
5762 for (len = 0; len < 0x40; len += 4) {
5763 pci_read_config_dword(hw_priv->pdev, len, buf);
5764 buf++;
5765 }
5766 while (range->end > range->start) {
5767 for (len = range->start; len < range->end; len += 4) {
5768 *buf = readl(hw->io + len);
5769 buf++;
5770 }
5771 range++;
5772 }
5773 mutex_unlock(&hw_priv->lock);
5774}
5775
5776#define WOL_SUPPORT \
5777 (WAKE_PHY | WAKE_MAGIC | \
5778 WAKE_UCAST | WAKE_MCAST | \
5779 WAKE_BCAST | WAKE_ARP)
5780
5781/**
5782 * netdev_get_wol - get Wake-on-LAN support
5783 * @dev: Network device.
5784 * @wol: Ethtool Wake-on-LAN data structure.
5785 *
5786 * This procedure returns Wake-on-LAN support.
5787 */
5788static void netdev_get_wol(struct net_device *dev,
5789 struct ethtool_wolinfo *wol)
5790{
5791 struct dev_priv *priv = netdev_priv(dev);
5792 struct dev_info *hw_priv = priv->adapter;
5793
5794 wol->supported = hw_priv->wol_support;
5795 wol->wolopts = hw_priv->wol_enable;
5796 memset(&wol->sopass, 0, sizeof(wol->sopass));
5797}
5798
5799/**
5800 * netdev_set_wol - set Wake-on-LAN support
5801 * @dev: Network device.
5802 * @wol: Ethtool Wake-on-LAN data structure.
5803 *
5804 * This function sets Wake-on-LAN support.
5805 *
5806 * Return 0 if successful; otherwise an error code.
5807 */
5808static int netdev_set_wol(struct net_device *dev,
5809 struct ethtool_wolinfo *wol)
5810{
5811 struct dev_priv *priv = netdev_priv(dev);
5812 struct dev_info *hw_priv = priv->adapter;
5813
5814 /* Need to find a way to retrieve the device IP address. */
5815 static const u8 net_addr[] = { 192, 168, 1, 1 };
5816
5817 if (wol->wolopts & ~hw_priv->wol_support)
5818 return -EINVAL;
5819
5820 hw_priv->wol_enable = wol->wolopts;
5821
5822 /* Link wakeup cannot really be disabled. */
5823 if (wol->wolopts)
5824 hw_priv->wol_enable |= WAKE_PHY;
5825 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
5826 return 0;
5827}
5828
5829/**
5830 * netdev_get_msglevel - get debug message level
5831 * @dev: Network device.
5832 *
5833 * This function returns current debug message level.
5834 *
5835 * Return current debug message flags.
5836 */
5837static u32 netdev_get_msglevel(struct net_device *dev)
5838{
5839 struct dev_priv *priv = netdev_priv(dev);
5840
5841 return priv->msg_enable;
5842}
5843
5844/**
5845 * netdev_set_msglevel - set debug message level
5846 * @dev: Network device.
5847 * @value: Debug message flags.
5848 *
5849 * This procedure sets debug message level.
5850 */
5851static void netdev_set_msglevel(struct net_device *dev, u32 value)
5852{
5853 struct dev_priv *priv = netdev_priv(dev);
5854
5855 priv->msg_enable = value;
5856}
5857
5858/**
5859 * netdev_get_eeprom_len - get EEPROM length
5860 * @dev: Network device.
5861 *
5862 * This function returns the length of the EEPROM.
5863 *
5864 * Return length of the EEPROM.
5865 */
5866static int netdev_get_eeprom_len(struct net_device *dev)
5867{
5868 return EEPROM_SIZE * 2;
5869}
5870
5871#define EEPROM_MAGIC 0x10A18842
5872
5873/**
5874 * netdev_get_eeprom - get EEPROM data
5875 * @dev: Network device.
5876 * @eeprom: Ethtool EEPROM data structure.
5877 * @data: Buffer to store the EEPROM data.
5878 *
5879 * This function dumps the EEPROM data in the provided buffer.
5880 *
5881 * Return 0 if successful; otherwise an error code.
5882 */
5883static int netdev_get_eeprom(struct net_device *dev,
5884 struct ethtool_eeprom *eeprom, u8 *data)
5885{
5886 struct dev_priv *priv = netdev_priv(dev);
5887 struct dev_info *hw_priv = priv->adapter;
5888 u8 *eeprom_byte = (u8 *) eeprom_data;
5889 int i;
5890 int len;
5891
5892 len = (eeprom->offset + eeprom->len + 1) / 2;
5893 for (i = eeprom->offset / 2; i < len; i++)
5894 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
5895 eeprom->magic = EEPROM_MAGIC;
5896 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
5897
5898 return 0;
5899}
5900
5901/**
5902 * netdev_set_eeprom - write EEPROM data
5903 * @dev: Network device.
5904 * @eeprom: Ethtool EEPROM data structure.
5905 * @data: Data buffer.
5906 *
5907 * This function modifies the EEPROM data one byte at a time.
5908 *
5909 * Return 0 if successful; otherwise an error code.
5910 */
5911static int netdev_set_eeprom(struct net_device *dev,
5912 struct ethtool_eeprom *eeprom, u8 *data)
5913{
5914 struct dev_priv *priv = netdev_priv(dev);
5915 struct dev_info *hw_priv = priv->adapter;
5916 u16 eeprom_word[EEPROM_SIZE];
5917 u8 *eeprom_byte = (u8 *) eeprom_word;
5918 int i;
5919 int len;
5920
5921 if (eeprom->magic != EEPROM_MAGIC)
5922 return -EINVAL;
5923
5924 len = (eeprom->offset + eeprom->len + 1) / 2;
5925 for (i = eeprom->offset / 2; i < len; i++)
5926 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
5927 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
5928 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
5929 for (i = 0; i < EEPROM_SIZE; i++)
5930 if (eeprom_word[i] != eeprom_data[i]) {
5931 eeprom_data[i] = eeprom_word[i];
5932 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
5933 }
5934
5935 return 0;
5936}
5937
5938/**
5939 * netdev_get_pauseparam - get flow control parameters
5940 * @dev: Network device.
5941 * @pause: Ethtool PAUSE settings data structure.
5942 *
5943 * This procedure returns the PAUSE control flow settings.
5944 */
5945static void netdev_get_pauseparam(struct net_device *dev,
5946 struct ethtool_pauseparam *pause)
5947{
5948 struct dev_priv *priv = netdev_priv(dev);
5949 struct dev_info *hw_priv = priv->adapter;
5950 struct ksz_hw *hw = &hw_priv->hw;
5951
5952 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
5953 if (!hw->ksz_switch) {
5954 pause->rx_pause =
5955 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
5956 pause->tx_pause =
5957 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
5958 } else {
5959 pause->rx_pause =
5960 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
5961 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
5962 pause->tx_pause =
5963 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
5964 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
5965 }
5966}
5967
5968/**
5969 * netdev_set_pauseparam - set flow control parameters
5970 * @dev: Network device.
5971 * @pause: Ethtool PAUSE settings data structure.
5972 *
5973 * This function sets the PAUSE control flow settings.
5974 * Not implemented yet.
5975 *
5976 * Return 0 if successful; otherwise an error code.
5977 */
5978static int netdev_set_pauseparam(struct net_device *dev,
5979 struct ethtool_pauseparam *pause)
5980{
5981 struct dev_priv *priv = netdev_priv(dev);
5982 struct dev_info *hw_priv = priv->adapter;
5983 struct ksz_hw *hw = &hw_priv->hw;
5984 struct ksz_port *port = &priv->port;
5985
5986 mutex_lock(&hw_priv->lock);
5987 if (pause->autoneg) {
5988 if (!pause->rx_pause && !pause->tx_pause)
5989 port->flow_ctrl = PHY_NO_FLOW_CTRL;
5990 else
5991 port->flow_ctrl = PHY_FLOW_CTRL;
5992 hw->overrides &= ~PAUSE_FLOW_CTRL;
5993 port->force_link = 0;
5994 if (hw->ksz_switch) {
5995 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
5996 SWITCH_RX_FLOW_CTRL, 1);
5997 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
5998 SWITCH_TX_FLOW_CTRL, 1);
5999 }
6000 port_set_link_speed(port);
6001 } else {
6002 hw->overrides |= PAUSE_FLOW_CTRL;
6003 if (hw->ksz_switch) {
6004 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6005 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6006 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6007 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6008 } else
6009 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6010 }
6011 mutex_unlock(&hw_priv->lock);
6012
6013 return 0;
6014}
6015
6016/**
6017 * netdev_get_ringparam - get tx/rx ring parameters
6018 * @dev: Network device.
6019 * @ring: Ethtool RING settings data structure.
6020 * @kernel_ring: Ethtool external RING settings data structure.
6021 * @extack: Netlink handle.
6022 *
6023 * This procedure returns the TX/RX ring settings.
6024 */
6025static void netdev_get_ringparam(struct net_device *dev,
6026 struct ethtool_ringparam *ring,
6027 struct kernel_ethtool_ringparam *kernel_ring,
6028 struct netlink_ext_ack *extack)
6029{
6030 struct dev_priv *priv = netdev_priv(dev);
6031 struct dev_info *hw_priv = priv->adapter;
6032 struct ksz_hw *hw = &hw_priv->hw;
6033
6034 ring->tx_max_pending = (1 << 9);
6035 ring->tx_pending = hw->tx_desc_info.alloc;
6036 ring->rx_max_pending = (1 << 9);
6037 ring->rx_pending = hw->rx_desc_info.alloc;
6038}
6039
6040#define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6041
6042static struct {
6043 char string[ETH_GSTRING_LEN];
6044} ethtool_stats_keys[STATS_LEN] = {
6045 { "rx_lo_priority_octets" },
6046 { "rx_hi_priority_octets" },
6047 { "rx_undersize_packets" },
6048 { "rx_fragments" },
6049 { "rx_oversize_packets" },
6050 { "rx_jabbers" },
6051 { "rx_symbol_errors" },
6052 { "rx_crc_errors" },
6053 { "rx_align_errors" },
6054 { "rx_mac_ctrl_packets" },
6055 { "rx_pause_packets" },
6056 { "rx_bcast_packets" },
6057 { "rx_mcast_packets" },
6058 { "rx_ucast_packets" },
6059 { "rx_64_or_less_octet_packets" },
6060 { "rx_65_to_127_octet_packets" },
6061 { "rx_128_to_255_octet_packets" },
6062 { "rx_256_to_511_octet_packets" },
6063 { "rx_512_to_1023_octet_packets" },
6064 { "rx_1024_to_1522_octet_packets" },
6065
6066 { "tx_lo_priority_octets" },
6067 { "tx_hi_priority_octets" },
6068 { "tx_late_collisions" },
6069 { "tx_pause_packets" },
6070 { "tx_bcast_packets" },
6071 { "tx_mcast_packets" },
6072 { "tx_ucast_packets" },
6073 { "tx_deferred" },
6074 { "tx_total_collisions" },
6075 { "tx_excessive_collisions" },
6076 { "tx_single_collisions" },
6077 { "tx_mult_collisions" },
6078
6079 { "rx_discards" },
6080 { "tx_discards" },
6081};
6082
6083/**
6084 * netdev_get_strings - get statistics identity strings
6085 * @dev: Network device.
6086 * @stringset: String set identifier.
6087 * @buf: Buffer to store the strings.
6088 *
6089 * This procedure returns the strings used to identify the statistics.
6090 */
6091static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6092{
6093 struct dev_priv *priv = netdev_priv(dev);
6094 struct dev_info *hw_priv = priv->adapter;
6095 struct ksz_hw *hw = &hw_priv->hw;
6096
6097 if (ETH_SS_STATS == stringset)
6098 memcpy(buf, ðtool_stats_keys,
6099 ETH_GSTRING_LEN * hw->mib_cnt);
6100}
6101
6102/**
6103 * netdev_get_sset_count - get statistics size
6104 * @dev: Network device.
6105 * @sset: The statistics set number.
6106 *
6107 * This function returns the size of the statistics to be reported.
6108 *
6109 * Return size of the statistics to be reported.
6110 */
6111static int netdev_get_sset_count(struct net_device *dev, int sset)
6112{
6113 struct dev_priv *priv = netdev_priv(dev);
6114 struct dev_info *hw_priv = priv->adapter;
6115 struct ksz_hw *hw = &hw_priv->hw;
6116
6117 switch (sset) {
6118 case ETH_SS_STATS:
6119 return hw->mib_cnt;
6120 default:
6121 return -EOPNOTSUPP;
6122 }
6123}
6124
6125/**
6126 * netdev_get_ethtool_stats - get network device statistics
6127 * @dev: Network device.
6128 * @stats: Ethtool statistics data structure.
6129 * @data: Buffer to store the statistics.
6130 *
6131 * This procedure returns the statistics.
6132 */
6133static void netdev_get_ethtool_stats(struct net_device *dev,
6134 struct ethtool_stats *stats, u64 *data)
6135{
6136 struct dev_priv *priv = netdev_priv(dev);
6137 struct dev_info *hw_priv = priv->adapter;
6138 struct ksz_hw *hw = &hw_priv->hw;
6139 struct ksz_port *port = &priv->port;
6140 int n_stats = stats->n_stats;
6141 int i;
6142 int n;
6143 int p;
6144 u64 counter[TOTAL_PORT_COUNTER_NUM];
6145
6146 mutex_lock(&hw_priv->lock);
6147 n = SWITCH_PORT_NUM;
6148 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6149 if (media_connected == hw->port_mib[p].state) {
6150 hw_priv->counter[p].read = 1;
6151
6152 /* Remember first port that requests read. */
6153 if (n == SWITCH_PORT_NUM)
6154 n = p;
6155 }
6156 }
6157 mutex_unlock(&hw_priv->lock);
6158
6159 if (n < SWITCH_PORT_NUM)
6160 schedule_work(&hw_priv->mib_read);
6161
6162 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6163 p = n;
6164 wait_event_interruptible_timeout(
6165 hw_priv->counter[p].counter,
6166 2 == hw_priv->counter[p].read,
6167 HZ * 1);
6168 } else
6169 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6170 if (0 == i) {
6171 wait_event_interruptible_timeout(
6172 hw_priv->counter[p].counter,
6173 2 == hw_priv->counter[p].read,
6174 HZ * 2);
6175 } else if (hw->port_mib[p].cnt_ptr) {
6176 wait_event_interruptible_timeout(
6177 hw_priv->counter[p].counter,
6178 2 == hw_priv->counter[p].read,
6179 HZ * 1);
6180 }
6181 }
6182
6183 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6184 n = hw->mib_cnt;
6185 if (n > n_stats)
6186 n = n_stats;
6187 n_stats -= n;
6188 for (i = 0; i < n; i++)
6189 *data++ = counter[i];
6190}
6191
6192/**
6193 * netdev_set_features - set receive checksum support
6194 * @dev: Network device.
6195 * @features: New device features (offloads).
6196 *
6197 * This function sets receive checksum support setting.
6198 *
6199 * Return 0 if successful; otherwise an error code.
6200 */
6201static int netdev_set_features(struct net_device *dev,
6202 netdev_features_t features)
6203{
6204 struct dev_priv *priv = netdev_priv(dev);
6205 struct dev_info *hw_priv = priv->adapter;
6206 struct ksz_hw *hw = &hw_priv->hw;
6207
6208 mutex_lock(&hw_priv->lock);
6209
6210 /* see note in hw_setup() */
6211 if (features & NETIF_F_RXCSUM)
6212 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6213 else
6214 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6215
6216 if (hw->enabled)
6217 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6218
6219 mutex_unlock(&hw_priv->lock);
6220
6221 return 0;
6222}
6223
6224static const struct ethtool_ops netdev_ethtool_ops = {
6225 .nway_reset = netdev_nway_reset,
6226 .get_link = netdev_get_link,
6227 .get_drvinfo = netdev_get_drvinfo,
6228 .get_regs_len = netdev_get_regs_len,
6229 .get_regs = netdev_get_regs,
6230 .get_wol = netdev_get_wol,
6231 .set_wol = netdev_set_wol,
6232 .get_msglevel = netdev_get_msglevel,
6233 .set_msglevel = netdev_set_msglevel,
6234 .get_eeprom_len = netdev_get_eeprom_len,
6235 .get_eeprom = netdev_get_eeprom,
6236 .set_eeprom = netdev_set_eeprom,
6237 .get_pauseparam = netdev_get_pauseparam,
6238 .set_pauseparam = netdev_set_pauseparam,
6239 .get_ringparam = netdev_get_ringparam,
6240 .get_strings = netdev_get_strings,
6241 .get_sset_count = netdev_get_sset_count,
6242 .get_ethtool_stats = netdev_get_ethtool_stats,
6243 .get_link_ksettings = netdev_get_link_ksettings,
6244 .set_link_ksettings = netdev_set_link_ksettings,
6245};
6246
6247/*
6248 * Hardware monitoring
6249 */
6250
6251static void update_link(struct net_device *dev, struct dev_priv *priv,
6252 struct ksz_port *port)
6253{
6254 if (priv->media_state != port->linked->state) {
6255 priv->media_state = port->linked->state;
6256 if (netif_running(dev))
6257 set_media_state(dev, media_connected);
6258 }
6259}
6260
6261static void mib_read_work(struct work_struct *work)
6262{
6263 struct dev_info *hw_priv =
6264 container_of(work, struct dev_info, mib_read);
6265 struct ksz_hw *hw = &hw_priv->hw;
6266 unsigned long next_jiffies;
6267 struct ksz_port_mib *mib;
6268 int i;
6269
6270 next_jiffies = jiffies;
6271 for (i = 0; i < hw->mib_port_cnt; i++) {
6272 mib = &hw->port_mib[i];
6273
6274 /* Reading MIB counters or requested to read. */
6275 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6276
6277 /* Need to process receive interrupt. */
6278 if (port_r_cnt(hw, i))
6279 break;
6280 hw_priv->counter[i].read = 0;
6281
6282 /* Finish reading counters. */
6283 if (0 == mib->cnt_ptr) {
6284 hw_priv->counter[i].read = 2;
6285 wake_up_interruptible(
6286 &hw_priv->counter[i].counter);
6287 }
6288 } else if (time_after_eq(jiffies, hw_priv->counter[i].time)) {
6289 /* Only read MIB counters when the port is connected. */
6290 if (media_connected == mib->state)
6291 hw_priv->counter[i].read = 1;
6292 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6293 hw_priv->counter[i].time = next_jiffies;
6294
6295 /* Port is just disconnected. */
6296 } else if (mib->link_down) {
6297 mib->link_down = 0;
6298
6299 /* Read counters one last time after link is lost. */
6300 hw_priv->counter[i].read = 1;
6301 }
6302 }
6303}
6304
6305static void mib_monitor(struct timer_list *t)
6306{
6307 struct dev_info *hw_priv = from_timer(hw_priv, t, mib_timer_info.timer);
6308
6309 mib_read_work(&hw_priv->mib_read);
6310
6311 /* This is used to verify Wake-on-LAN is working. */
6312 if (hw_priv->pme_wait) {
6313 if (time_is_before_eq_jiffies(hw_priv->pme_wait)) {
6314 hw_clr_wol_pme_status(&hw_priv->hw);
6315 hw_priv->pme_wait = 0;
6316 }
6317 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6318
6319 /* PME is asserted. Wait 2 seconds to clear it. */
6320 hw_priv->pme_wait = jiffies + HZ * 2;
6321 }
6322
6323 ksz_update_timer(&hw_priv->mib_timer_info);
6324}
6325
6326/**
6327 * dev_monitor - periodic monitoring
6328 * @t: timer list containing a network device pointer.
6329 *
6330 * This routine is run in a kernel timer to monitor the network device.
6331 */
6332static void dev_monitor(struct timer_list *t)
6333{
6334 struct dev_priv *priv = from_timer(priv, t, monitor_timer_info.timer);
6335 struct net_device *dev = priv->mii_if.dev;
6336 struct dev_info *hw_priv = priv->adapter;
6337 struct ksz_hw *hw = &hw_priv->hw;
6338 struct ksz_port *port = &priv->port;
6339
6340 if (!(hw->features & LINK_INT_WORKING))
6341 port_get_link_speed(port);
6342 update_link(dev, priv, port);
6343
6344 ksz_update_timer(&priv->monitor_timer_info);
6345}
6346
6347/*
6348 * Linux network device interface functions
6349 */
6350
6351/* Driver exported variables */
6352
6353static int msg_enable;
6354
6355static char *macaddr = ":";
6356static char *mac1addr = ":";
6357
6358/*
6359 * This enables multiple network device mode for KSZ8842, which contains a
6360 * switch with two physical ports. Some users like to take control of the
6361 * ports for running Spanning Tree Protocol. The driver will create an
6362 * additional eth? device for the other port.
6363 *
6364 * Some limitations are the network devices cannot have different MTU and
6365 * multicast hash tables.
6366 */
6367static int multi_dev;
6368
6369/*
6370 * As most users select multiple network device mode to use Spanning Tree
6371 * Protocol, this enables a feature in which most unicast and multicast packets
6372 * are forwarded inside the switch and not passed to the host. Only packets
6373 * that need the host's attention are passed to it. This prevents the host
6374 * wasting CPU time to examine each and every incoming packets and do the
6375 * forwarding itself.
6376 *
6377 * As the hack requires the private bridge header, the driver cannot compile
6378 * with just the kernel headers.
6379 *
6380 * Enabling STP support also turns on multiple network device mode.
6381 */
6382static int stp;
6383
6384/*
6385 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6386 * needs that. However, fast aging is used to flush the dynamic MAC table when
6387 * STP support is enabled.
6388 */
6389static int fast_aging;
6390
6391/**
6392 * netdev_init - initialize network device.
6393 * @dev: Network device.
6394 *
6395 * This function initializes the network device.
6396 *
6397 * Return 0 if successful; otherwise an error code indicating failure.
6398 */
6399static int __init netdev_init(struct net_device *dev)
6400{
6401 struct dev_priv *priv = netdev_priv(dev);
6402
6403 /* 500 ms timeout */
6404 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6405 dev_monitor);
6406
6407 /* 500 ms timeout */
6408 dev->watchdog_timeo = HZ / 2;
6409
6410 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_RXCSUM;
6411
6412 /*
6413 * Hardware does not really support IPv6 checksum generation, but
6414 * driver actually runs faster with this on.
6415 */
6416 dev->hw_features |= NETIF_F_IPV6_CSUM;
6417
6418 dev->features |= dev->hw_features;
6419
6420 sema_init(&priv->proc_sem, 1);
6421
6422 priv->mii_if.phy_id_mask = 0x1;
6423 priv->mii_if.reg_num_mask = 0x7;
6424 priv->mii_if.dev = dev;
6425 priv->mii_if.mdio_read = mdio_read;
6426 priv->mii_if.mdio_write = mdio_write;
6427 priv->mii_if.phy_id = priv->port.first_port + 1;
6428
6429 priv->msg_enable = netif_msg_init(msg_enable,
6430 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6431
6432 return 0;
6433}
6434
6435static const struct net_device_ops netdev_ops = {
6436 .ndo_init = netdev_init,
6437 .ndo_open = netdev_open,
6438 .ndo_stop = netdev_close,
6439 .ndo_get_stats = netdev_query_statistics,
6440 .ndo_start_xmit = netdev_tx,
6441 .ndo_tx_timeout = netdev_tx_timeout,
6442 .ndo_change_mtu = netdev_change_mtu,
6443 .ndo_set_features = netdev_set_features,
6444 .ndo_set_mac_address = netdev_set_mac_address,
6445 .ndo_validate_addr = eth_validate_addr,
6446 .ndo_eth_ioctl = netdev_ioctl,
6447 .ndo_set_rx_mode = netdev_set_rx_mode,
6448#ifdef CONFIG_NET_POLL_CONTROLLER
6449 .ndo_poll_controller = netdev_netpoll,
6450#endif
6451};
6452
6453static void netdev_free(struct net_device *dev)
6454{
6455 if (dev->watchdog_timeo)
6456 unregister_netdev(dev);
6457
6458 free_netdev(dev);
6459}
6460
6461struct platform_info {
6462 struct dev_info dev_info;
6463 struct net_device *netdev[SWITCH_PORT_NUM];
6464};
6465
6466static int net_device_present;
6467
6468static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6469{
6470 int i;
6471 int j;
6472 int got_num;
6473 int num;
6474
6475 i = j = num = got_num = 0;
6476 while (j < ETH_ALEN) {
6477 if (macaddr[i]) {
6478 int digit;
6479
6480 got_num = 1;
6481 digit = hex_to_bin(macaddr[i]);
6482 if (digit >= 0)
6483 num = num * 16 + digit;
6484 else if (':' == macaddr[i])
6485 got_num = 2;
6486 else
6487 break;
6488 } else if (got_num)
6489 got_num = 2;
6490 else
6491 break;
6492 if (2 == got_num) {
6493 if (MAIN_PORT == port) {
6494 hw_priv->hw.override_addr[j++] = (u8) num;
6495 hw_priv->hw.override_addr[5] +=
6496 hw_priv->hw.id;
6497 } else {
6498 hw_priv->hw.ksz_switch->other_addr[j++] =
6499 (u8) num;
6500 hw_priv->hw.ksz_switch->other_addr[5] +=
6501 hw_priv->hw.id;
6502 }
6503 num = got_num = 0;
6504 }
6505 i++;
6506 }
6507 if (ETH_ALEN == j) {
6508 if (MAIN_PORT == port)
6509 hw_priv->hw.mac_override = 1;
6510 }
6511}
6512
6513#define KS884X_DMA_MASK (~0x0UL)
6514
6515static void read_other_addr(struct ksz_hw *hw)
6516{
6517 int i;
6518 u16 data[3];
6519 struct ksz_switch *sw = hw->ksz_switch;
6520
6521 for (i = 0; i < 3; i++)
6522 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6523 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6524 sw->other_addr[5] = (u8) data[0];
6525 sw->other_addr[4] = (u8)(data[0] >> 8);
6526 sw->other_addr[3] = (u8) data[1];
6527 sw->other_addr[2] = (u8)(data[1] >> 8);
6528 sw->other_addr[1] = (u8) data[2];
6529 sw->other_addr[0] = (u8)(data[2] >> 8);
6530 }
6531}
6532
6533#ifndef PCI_VENDOR_ID_MICREL_KS
6534#define PCI_VENDOR_ID_MICREL_KS 0x16c6
6535#endif
6536
6537static int pcidev_init(struct pci_dev *pdev, const struct pci_device_id *id)
6538{
6539 struct net_device *dev;
6540 struct dev_priv *priv;
6541 struct dev_info *hw_priv;
6542 struct ksz_hw *hw;
6543 struct platform_info *info;
6544 struct ksz_port *port;
6545 unsigned long reg_base;
6546 unsigned long reg_len;
6547 int cnt;
6548 int i;
6549 int mib_port_count;
6550 int pi;
6551 int port_count;
6552 int result;
6553 char banner[sizeof(version)];
6554 struct ksz_switch *sw = NULL;
6555
6556 result = pcim_enable_device(pdev);
6557 if (result)
6558 return result;
6559
6560 result = -ENODEV;
6561
6562 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)) ||
6563 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)))
6564 return result;
6565
6566 reg_base = pci_resource_start(pdev, 0);
6567 reg_len = pci_resource_len(pdev, 0);
6568 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
6569 return result;
6570
6571 if (!request_mem_region(reg_base, reg_len, DRV_NAME))
6572 return result;
6573 pci_set_master(pdev);
6574
6575 result = -ENOMEM;
6576
6577 info = kzalloc(sizeof(struct platform_info), GFP_KERNEL);
6578 if (!info)
6579 goto pcidev_init_dev_err;
6580
6581 hw_priv = &info->dev_info;
6582 hw_priv->pdev = pdev;
6583
6584 hw = &hw_priv->hw;
6585
6586 hw->io = ioremap(reg_base, reg_len);
6587 if (!hw->io)
6588 goto pcidev_init_io_err;
6589
6590 cnt = hw_init(hw);
6591 if (!cnt) {
6592 if (msg_enable & NETIF_MSG_PROBE)
6593 pr_alert("chip not detected\n");
6594 result = -ENODEV;
6595 goto pcidev_init_alloc_err;
6596 }
6597
6598 snprintf(banner, sizeof(banner), "%s", version);
6599 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */
6600 dev_info(&hw_priv->pdev->dev, "%s\n", banner);
6601 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
6602
6603 /* Assume device is KSZ8841. */
6604 hw->dev_count = 1;
6605 port_count = 1;
6606 mib_port_count = 1;
6607 hw->addr_list_size = 0;
6608 hw->mib_cnt = PORT_COUNTER_NUM;
6609 hw->mib_port_cnt = 1;
6610
6611 /* KSZ8842 has a switch with multiple ports. */
6612 if (2 == cnt) {
6613 if (fast_aging)
6614 hw->overrides |= FAST_AGING;
6615
6616 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
6617
6618 /* Multiple network device interfaces are required. */
6619 if (multi_dev) {
6620 hw->dev_count = SWITCH_PORT_NUM;
6621 hw->addr_list_size = SWITCH_PORT_NUM - 1;
6622 }
6623
6624 /* Single network device has multiple ports. */
6625 if (1 == hw->dev_count) {
6626 port_count = SWITCH_PORT_NUM;
6627 mib_port_count = SWITCH_PORT_NUM;
6628 }
6629 hw->mib_port_cnt = TOTAL_PORT_NUM;
6630 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL);
6631 if (!hw->ksz_switch)
6632 goto pcidev_init_alloc_err;
6633
6634 sw = hw->ksz_switch;
6635 }
6636 for (i = 0; i < hw->mib_port_cnt; i++)
6637 hw->port_mib[i].mib_start = 0;
6638
6639 hw->parent = hw_priv;
6640
6641 /* Default MTU is 1500. */
6642 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
6643
6644 if (ksz_alloc_mem(hw_priv))
6645 goto pcidev_init_mem_err;
6646
6647 hw_priv->hw.id = net_device_present;
6648
6649 spin_lock_init(&hw_priv->hwlock);
6650 mutex_init(&hw_priv->lock);
6651
6652 for (i = 0; i < TOTAL_PORT_NUM; i++)
6653 init_waitqueue_head(&hw_priv->counter[i].counter);
6654
6655 if (macaddr[0] != ':')
6656 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
6657
6658 /* Read MAC address and initialize override address if not overridden. */
6659 hw_read_addr(hw);
6660
6661 /* Multiple device interfaces mode requires a second MAC address. */
6662 if (hw->dev_count > 1) {
6663 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN);
6664 read_other_addr(hw);
6665 if (mac1addr[0] != ':')
6666 get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
6667 }
6668
6669 hw_setup(hw);
6670 if (hw->ksz_switch)
6671 sw_setup(hw);
6672 else {
6673 hw_priv->wol_support = WOL_SUPPORT;
6674 hw_priv->wol_enable = 0;
6675 }
6676
6677 INIT_WORK(&hw_priv->mib_read, mib_read_work);
6678
6679 /* 500 ms timeout */
6680 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
6681 mib_monitor);
6682
6683 for (i = 0; i < hw->dev_count; i++) {
6684 dev = alloc_etherdev(sizeof(struct dev_priv));
6685 if (!dev)
6686 goto pcidev_init_reg_err;
6687 SET_NETDEV_DEV(dev, &pdev->dev);
6688 info->netdev[i] = dev;
6689
6690 priv = netdev_priv(dev);
6691 priv->adapter = hw_priv;
6692 priv->id = net_device_present++;
6693
6694 port = &priv->port;
6695 port->port_cnt = port_count;
6696 port->mib_port_cnt = mib_port_count;
6697 port->first_port = i;
6698 port->flow_ctrl = PHY_FLOW_CTRL;
6699
6700 port->hw = hw;
6701 port->linked = &hw->port_info[port->first_port];
6702
6703 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
6704 hw->port_info[pi].port_id = pi;
6705 hw->port_info[pi].pdev = dev;
6706 hw->port_info[pi].state = media_disconnected;
6707 }
6708
6709 dev->mem_start = (unsigned long) hw->io;
6710 dev->mem_end = dev->mem_start + reg_len - 1;
6711 dev->irq = pdev->irq;
6712 if (MAIN_PORT == i)
6713 eth_hw_addr_set(dev, hw_priv->hw.override_addr);
6714 else {
6715 u8 addr[ETH_ALEN];
6716
6717 ether_addr_copy(addr, sw->other_addr);
6718 if (ether_addr_equal(sw->other_addr, hw->override_addr))
6719 addr[5] += port->first_port;
6720 eth_hw_addr_set(dev, addr);
6721 }
6722
6723 dev->netdev_ops = &netdev_ops;
6724 dev->ethtool_ops = &netdev_ethtool_ops;
6725
6726 /* MTU range: 60 - 1894 */
6727 dev->min_mtu = ETH_ZLEN;
6728 dev->max_mtu = MAX_RX_BUF_SIZE -
6729 (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
6730
6731 if (register_netdev(dev))
6732 goto pcidev_init_reg_err;
6733 port_set_power_saving(port, true);
6734 }
6735
6736 pci_dev_get(hw_priv->pdev);
6737 pci_set_drvdata(pdev, info);
6738 return 0;
6739
6740pcidev_init_reg_err:
6741 for (i = 0; i < hw->dev_count; i++) {
6742 if (info->netdev[i]) {
6743 netdev_free(info->netdev[i]);
6744 info->netdev[i] = NULL;
6745 }
6746 }
6747
6748pcidev_init_mem_err:
6749 ksz_free_mem(hw_priv);
6750 kfree(hw->ksz_switch);
6751
6752pcidev_init_alloc_err:
6753 iounmap(hw->io);
6754
6755pcidev_init_io_err:
6756 kfree(info);
6757
6758pcidev_init_dev_err:
6759 release_mem_region(reg_base, reg_len);
6760
6761 return result;
6762}
6763
6764static void pcidev_exit(struct pci_dev *pdev)
6765{
6766 int i;
6767 struct platform_info *info = pci_get_drvdata(pdev);
6768 struct dev_info *hw_priv = &info->dev_info;
6769
6770 release_mem_region(pci_resource_start(pdev, 0),
6771 pci_resource_len(pdev, 0));
6772 for (i = 0; i < hw_priv->hw.dev_count; i++) {
6773 if (info->netdev[i])
6774 netdev_free(info->netdev[i]);
6775 }
6776 if (hw_priv->hw.io)
6777 iounmap(hw_priv->hw.io);
6778 ksz_free_mem(hw_priv);
6779 kfree(hw_priv->hw.ksz_switch);
6780 pci_dev_put(hw_priv->pdev);
6781 kfree(info);
6782}
6783
6784static int __maybe_unused pcidev_resume(struct device *dev_d)
6785{
6786 int i;
6787 struct platform_info *info = dev_get_drvdata(dev_d);
6788 struct dev_info *hw_priv = &info->dev_info;
6789 struct ksz_hw *hw = &hw_priv->hw;
6790
6791 device_wakeup_disable(dev_d);
6792
6793 if (hw_priv->wol_enable)
6794 hw_cfg_wol_pme(hw, 0);
6795 for (i = 0; i < hw->dev_count; i++) {
6796 if (info->netdev[i]) {
6797 struct net_device *dev = info->netdev[i];
6798
6799 if (netif_running(dev)) {
6800 netdev_open(dev);
6801 netif_device_attach(dev);
6802 }
6803 }
6804 }
6805 return 0;
6806}
6807
6808static int __maybe_unused pcidev_suspend(struct device *dev_d)
6809{
6810 int i;
6811 struct platform_info *info = dev_get_drvdata(dev_d);
6812 struct dev_info *hw_priv = &info->dev_info;
6813 struct ksz_hw *hw = &hw_priv->hw;
6814
6815 /* Need to find a way to retrieve the device IP address. */
6816 static const u8 net_addr[] = { 192, 168, 1, 1 };
6817
6818 for (i = 0; i < hw->dev_count; i++) {
6819 if (info->netdev[i]) {
6820 struct net_device *dev = info->netdev[i];
6821
6822 if (netif_running(dev)) {
6823 netif_device_detach(dev);
6824 netdev_close(dev);
6825 }
6826 }
6827 }
6828 if (hw_priv->wol_enable) {
6829 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
6830 hw_cfg_wol_pme(hw, 1);
6831 }
6832
6833 device_wakeup_enable(dev_d);
6834 return 0;
6835}
6836
6837static char pcidev_name[] = "ksz884xp";
6838
6839static const struct pci_device_id pcidev_table[] = {
6840 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
6841 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
6842 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
6843 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
6844 { 0 }
6845};
6846
6847MODULE_DEVICE_TABLE(pci, pcidev_table);
6848
6849static SIMPLE_DEV_PM_OPS(pcidev_pm_ops, pcidev_suspend, pcidev_resume);
6850
6851static struct pci_driver pci_device_driver = {
6852 .driver.pm = &pcidev_pm_ops,
6853 .name = pcidev_name,
6854 .id_table = pcidev_table,
6855 .probe = pcidev_init,
6856 .remove = pcidev_exit
6857};
6858
6859module_pci_driver(pci_device_driver);
6860
6861MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
6862MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
6863MODULE_LICENSE("GPL");
6864
6865module_param_named(message, msg_enable, int, 0);
6866MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
6867
6868module_param(macaddr, charp, 0);
6869module_param(mac1addr, charp, 0);
6870module_param(fast_aging, int, 0);
6871module_param(multi_dev, int, 0);
6872module_param(stp, int, 0);
6873MODULE_PARM_DESC(macaddr, "MAC address");
6874MODULE_PARM_DESC(mac1addr, "Second MAC address");
6875MODULE_PARM_DESC(fast_aging, "Fast aging");
6876MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
6877MODULE_PARM_DESC(stp, "STP support");
1/**
2 * drivers/net/ethernet/micrel/ksx884x.c - Micrel KSZ8841/2 PCI Ethernet driver
3 *
4 * Copyright (c) 2009-2010 Micrel, Inc.
5 * Tristram Ha <Tristram.Ha@micrel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/ioport.h>
24#include <linux/pci.h>
25#include <linux/proc_fs.h>
26#include <linux/mii.h>
27#include <linux/platform_device.h>
28#include <linux/ethtool.h>
29#include <linux/etherdevice.h>
30#include <linux/in.h>
31#include <linux/ip.h>
32#include <linux/if_vlan.h>
33#include <linux/crc32.h>
34#include <linux/sched.h>
35#include <linux/slab.h>
36
37
38/* DMA Registers */
39
40#define KS_DMA_TX_CTRL 0x0000
41#define DMA_TX_ENABLE 0x00000001
42#define DMA_TX_CRC_ENABLE 0x00000002
43#define DMA_TX_PAD_ENABLE 0x00000004
44#define DMA_TX_LOOPBACK 0x00000100
45#define DMA_TX_FLOW_ENABLE 0x00000200
46#define DMA_TX_CSUM_IP 0x00010000
47#define DMA_TX_CSUM_TCP 0x00020000
48#define DMA_TX_CSUM_UDP 0x00040000
49#define DMA_TX_BURST_SIZE 0x3F000000
50
51#define KS_DMA_RX_CTRL 0x0004
52#define DMA_RX_ENABLE 0x00000001
53#define KS884X_DMA_RX_MULTICAST 0x00000002
54#define DMA_RX_PROMISCUOUS 0x00000004
55#define DMA_RX_ERROR 0x00000008
56#define DMA_RX_UNICAST 0x00000010
57#define DMA_RX_ALL_MULTICAST 0x00000020
58#define DMA_RX_BROADCAST 0x00000040
59#define DMA_RX_FLOW_ENABLE 0x00000200
60#define DMA_RX_CSUM_IP 0x00010000
61#define DMA_RX_CSUM_TCP 0x00020000
62#define DMA_RX_CSUM_UDP 0x00040000
63#define DMA_RX_BURST_SIZE 0x3F000000
64
65#define DMA_BURST_SHIFT 24
66#define DMA_BURST_DEFAULT 8
67
68#define KS_DMA_TX_START 0x0008
69#define KS_DMA_RX_START 0x000C
70#define DMA_START 0x00000001
71
72#define KS_DMA_TX_ADDR 0x0010
73#define KS_DMA_RX_ADDR 0x0014
74
75#define DMA_ADDR_LIST_MASK 0xFFFFFFFC
76#define DMA_ADDR_LIST_SHIFT 2
77
78/* MTR0 */
79#define KS884X_MULTICAST_0_OFFSET 0x0020
80#define KS884X_MULTICAST_1_OFFSET 0x0021
81#define KS884X_MULTICAST_2_OFFSET 0x0022
82#define KS884x_MULTICAST_3_OFFSET 0x0023
83/* MTR1 */
84#define KS884X_MULTICAST_4_OFFSET 0x0024
85#define KS884X_MULTICAST_5_OFFSET 0x0025
86#define KS884X_MULTICAST_6_OFFSET 0x0026
87#define KS884X_MULTICAST_7_OFFSET 0x0027
88
89/* Interrupt Registers */
90
91/* INTEN */
92#define KS884X_INTERRUPTS_ENABLE 0x0028
93/* INTST */
94#define KS884X_INTERRUPTS_STATUS 0x002C
95
96#define KS884X_INT_RX_STOPPED 0x02000000
97#define KS884X_INT_TX_STOPPED 0x04000000
98#define KS884X_INT_RX_OVERRUN 0x08000000
99#define KS884X_INT_TX_EMPTY 0x10000000
100#define KS884X_INT_RX 0x20000000
101#define KS884X_INT_TX 0x40000000
102#define KS884X_INT_PHY 0x80000000
103
104#define KS884X_INT_RX_MASK \
105 (KS884X_INT_RX | KS884X_INT_RX_OVERRUN)
106#define KS884X_INT_TX_MASK \
107 (KS884X_INT_TX | KS884X_INT_TX_EMPTY)
108#define KS884X_INT_MASK (KS884X_INT_RX | KS884X_INT_TX | KS884X_INT_PHY)
109
110/* MAC Additional Station Address */
111
112/* MAAL0 */
113#define KS_ADD_ADDR_0_LO 0x0080
114/* MAAH0 */
115#define KS_ADD_ADDR_0_HI 0x0084
116/* MAAL1 */
117#define KS_ADD_ADDR_1_LO 0x0088
118/* MAAH1 */
119#define KS_ADD_ADDR_1_HI 0x008C
120/* MAAL2 */
121#define KS_ADD_ADDR_2_LO 0x0090
122/* MAAH2 */
123#define KS_ADD_ADDR_2_HI 0x0094
124/* MAAL3 */
125#define KS_ADD_ADDR_3_LO 0x0098
126/* MAAH3 */
127#define KS_ADD_ADDR_3_HI 0x009C
128/* MAAL4 */
129#define KS_ADD_ADDR_4_LO 0x00A0
130/* MAAH4 */
131#define KS_ADD_ADDR_4_HI 0x00A4
132/* MAAL5 */
133#define KS_ADD_ADDR_5_LO 0x00A8
134/* MAAH5 */
135#define KS_ADD_ADDR_5_HI 0x00AC
136/* MAAL6 */
137#define KS_ADD_ADDR_6_LO 0x00B0
138/* MAAH6 */
139#define KS_ADD_ADDR_6_HI 0x00B4
140/* MAAL7 */
141#define KS_ADD_ADDR_7_LO 0x00B8
142/* MAAH7 */
143#define KS_ADD_ADDR_7_HI 0x00BC
144/* MAAL8 */
145#define KS_ADD_ADDR_8_LO 0x00C0
146/* MAAH8 */
147#define KS_ADD_ADDR_8_HI 0x00C4
148/* MAAL9 */
149#define KS_ADD_ADDR_9_LO 0x00C8
150/* MAAH9 */
151#define KS_ADD_ADDR_9_HI 0x00CC
152/* MAAL10 */
153#define KS_ADD_ADDR_A_LO 0x00D0
154/* MAAH10 */
155#define KS_ADD_ADDR_A_HI 0x00D4
156/* MAAL11 */
157#define KS_ADD_ADDR_B_LO 0x00D8
158/* MAAH11 */
159#define KS_ADD_ADDR_B_HI 0x00DC
160/* MAAL12 */
161#define KS_ADD_ADDR_C_LO 0x00E0
162/* MAAH12 */
163#define KS_ADD_ADDR_C_HI 0x00E4
164/* MAAL13 */
165#define KS_ADD_ADDR_D_LO 0x00E8
166/* MAAH13 */
167#define KS_ADD_ADDR_D_HI 0x00EC
168/* MAAL14 */
169#define KS_ADD_ADDR_E_LO 0x00F0
170/* MAAH14 */
171#define KS_ADD_ADDR_E_HI 0x00F4
172/* MAAL15 */
173#define KS_ADD_ADDR_F_LO 0x00F8
174/* MAAH15 */
175#define KS_ADD_ADDR_F_HI 0x00FC
176
177#define ADD_ADDR_HI_MASK 0x0000FFFF
178#define ADD_ADDR_ENABLE 0x80000000
179#define ADD_ADDR_INCR 8
180
181/* Miscellaneous Registers */
182
183/* MARL */
184#define KS884X_ADDR_0_OFFSET 0x0200
185#define KS884X_ADDR_1_OFFSET 0x0201
186/* MARM */
187#define KS884X_ADDR_2_OFFSET 0x0202
188#define KS884X_ADDR_3_OFFSET 0x0203
189/* MARH */
190#define KS884X_ADDR_4_OFFSET 0x0204
191#define KS884X_ADDR_5_OFFSET 0x0205
192
193/* OBCR */
194#define KS884X_BUS_CTRL_OFFSET 0x0210
195
196#define BUS_SPEED_125_MHZ 0x0000
197#define BUS_SPEED_62_5_MHZ 0x0001
198#define BUS_SPEED_41_66_MHZ 0x0002
199#define BUS_SPEED_25_MHZ 0x0003
200
201/* EEPCR */
202#define KS884X_EEPROM_CTRL_OFFSET 0x0212
203
204#define EEPROM_CHIP_SELECT 0x0001
205#define EEPROM_SERIAL_CLOCK 0x0002
206#define EEPROM_DATA_OUT 0x0004
207#define EEPROM_DATA_IN 0x0008
208#define EEPROM_ACCESS_ENABLE 0x0010
209
210/* MBIR */
211#define KS884X_MEM_INFO_OFFSET 0x0214
212
213#define RX_MEM_TEST_FAILED 0x0008
214#define RX_MEM_TEST_FINISHED 0x0010
215#define TX_MEM_TEST_FAILED 0x0800
216#define TX_MEM_TEST_FINISHED 0x1000
217
218/* GCR */
219#define KS884X_GLOBAL_CTRL_OFFSET 0x0216
220#define GLOBAL_SOFTWARE_RESET 0x0001
221
222#define KS8841_POWER_MANAGE_OFFSET 0x0218
223
224/* WFCR */
225#define KS8841_WOL_CTRL_OFFSET 0x021A
226#define KS8841_WOL_MAGIC_ENABLE 0x0080
227#define KS8841_WOL_FRAME3_ENABLE 0x0008
228#define KS8841_WOL_FRAME2_ENABLE 0x0004
229#define KS8841_WOL_FRAME1_ENABLE 0x0002
230#define KS8841_WOL_FRAME0_ENABLE 0x0001
231
232/* WF0 */
233#define KS8841_WOL_FRAME_CRC_OFFSET 0x0220
234#define KS8841_WOL_FRAME_BYTE0_OFFSET 0x0224
235#define KS8841_WOL_FRAME_BYTE2_OFFSET 0x0228
236
237/* IACR */
238#define KS884X_IACR_P 0x04A0
239#define KS884X_IACR_OFFSET KS884X_IACR_P
240
241/* IADR1 */
242#define KS884X_IADR1_P 0x04A2
243#define KS884X_IADR2_P 0x04A4
244#define KS884X_IADR3_P 0x04A6
245#define KS884X_IADR4_P 0x04A8
246#define KS884X_IADR5_P 0x04AA
247
248#define KS884X_ACC_CTRL_SEL_OFFSET KS884X_IACR_P
249#define KS884X_ACC_CTRL_INDEX_OFFSET (KS884X_ACC_CTRL_SEL_OFFSET + 1)
250
251#define KS884X_ACC_DATA_0_OFFSET KS884X_IADR4_P
252#define KS884X_ACC_DATA_1_OFFSET (KS884X_ACC_DATA_0_OFFSET + 1)
253#define KS884X_ACC_DATA_2_OFFSET KS884X_IADR5_P
254#define KS884X_ACC_DATA_3_OFFSET (KS884X_ACC_DATA_2_OFFSET + 1)
255#define KS884X_ACC_DATA_4_OFFSET KS884X_IADR2_P
256#define KS884X_ACC_DATA_5_OFFSET (KS884X_ACC_DATA_4_OFFSET + 1)
257#define KS884X_ACC_DATA_6_OFFSET KS884X_IADR3_P
258#define KS884X_ACC_DATA_7_OFFSET (KS884X_ACC_DATA_6_OFFSET + 1)
259#define KS884X_ACC_DATA_8_OFFSET KS884X_IADR1_P
260
261/* P1MBCR */
262#define KS884X_P1MBCR_P 0x04D0
263#define KS884X_P1MBSR_P 0x04D2
264#define KS884X_PHY1ILR_P 0x04D4
265#define KS884X_PHY1IHR_P 0x04D6
266#define KS884X_P1ANAR_P 0x04D8
267#define KS884X_P1ANLPR_P 0x04DA
268
269/* P2MBCR */
270#define KS884X_P2MBCR_P 0x04E0
271#define KS884X_P2MBSR_P 0x04E2
272#define KS884X_PHY2ILR_P 0x04E4
273#define KS884X_PHY2IHR_P 0x04E6
274#define KS884X_P2ANAR_P 0x04E8
275#define KS884X_P2ANLPR_P 0x04EA
276
277#define KS884X_PHY_1_CTRL_OFFSET KS884X_P1MBCR_P
278#define PHY_CTRL_INTERVAL (KS884X_P2MBCR_P - KS884X_P1MBCR_P)
279
280#define KS884X_PHY_CTRL_OFFSET 0x00
281
282/* Mode Control Register */
283#define PHY_REG_CTRL 0
284
285#define PHY_RESET 0x8000
286#define PHY_LOOPBACK 0x4000
287#define PHY_SPEED_100MBIT 0x2000
288#define PHY_AUTO_NEG_ENABLE 0x1000
289#define PHY_POWER_DOWN 0x0800
290#define PHY_MII_DISABLE 0x0400
291#define PHY_AUTO_NEG_RESTART 0x0200
292#define PHY_FULL_DUPLEX 0x0100
293#define PHY_COLLISION_TEST 0x0080
294#define PHY_HP_MDIX 0x0020
295#define PHY_FORCE_MDIX 0x0010
296#define PHY_AUTO_MDIX_DISABLE 0x0008
297#define PHY_REMOTE_FAULT_DISABLE 0x0004
298#define PHY_TRANSMIT_DISABLE 0x0002
299#define PHY_LED_DISABLE 0x0001
300
301#define KS884X_PHY_STATUS_OFFSET 0x02
302
303/* Mode Status Register */
304#define PHY_REG_STATUS 1
305
306#define PHY_100BT4_CAPABLE 0x8000
307#define PHY_100BTX_FD_CAPABLE 0x4000
308#define PHY_100BTX_CAPABLE 0x2000
309#define PHY_10BT_FD_CAPABLE 0x1000
310#define PHY_10BT_CAPABLE 0x0800
311#define PHY_MII_SUPPRESS_CAPABLE 0x0040
312#define PHY_AUTO_NEG_ACKNOWLEDGE 0x0020
313#define PHY_REMOTE_FAULT 0x0010
314#define PHY_AUTO_NEG_CAPABLE 0x0008
315#define PHY_LINK_STATUS 0x0004
316#define PHY_JABBER_DETECT 0x0002
317#define PHY_EXTENDED_CAPABILITY 0x0001
318
319#define KS884X_PHY_ID_1_OFFSET 0x04
320#define KS884X_PHY_ID_2_OFFSET 0x06
321
322/* PHY Identifier Registers */
323#define PHY_REG_ID_1 2
324#define PHY_REG_ID_2 3
325
326#define KS884X_PHY_AUTO_NEG_OFFSET 0x08
327
328/* Auto-Negotiation Advertisement Register */
329#define PHY_REG_AUTO_NEGOTIATION 4
330
331#define PHY_AUTO_NEG_NEXT_PAGE 0x8000
332#define PHY_AUTO_NEG_REMOTE_FAULT 0x2000
333/* Not supported. */
334#define PHY_AUTO_NEG_ASYM_PAUSE 0x0800
335#define PHY_AUTO_NEG_SYM_PAUSE 0x0400
336#define PHY_AUTO_NEG_100BT4 0x0200
337#define PHY_AUTO_NEG_100BTX_FD 0x0100
338#define PHY_AUTO_NEG_100BTX 0x0080
339#define PHY_AUTO_NEG_10BT_FD 0x0040
340#define PHY_AUTO_NEG_10BT 0x0020
341#define PHY_AUTO_NEG_SELECTOR 0x001F
342#define PHY_AUTO_NEG_802_3 0x0001
343
344#define PHY_AUTO_NEG_PAUSE (PHY_AUTO_NEG_SYM_PAUSE | PHY_AUTO_NEG_ASYM_PAUSE)
345
346#define KS884X_PHY_REMOTE_CAP_OFFSET 0x0A
347
348/* Auto-Negotiation Link Partner Ability Register */
349#define PHY_REG_REMOTE_CAPABILITY 5
350
351#define PHY_REMOTE_NEXT_PAGE 0x8000
352#define PHY_REMOTE_ACKNOWLEDGE 0x4000
353#define PHY_REMOTE_REMOTE_FAULT 0x2000
354#define PHY_REMOTE_SYM_PAUSE 0x0400
355#define PHY_REMOTE_100BTX_FD 0x0100
356#define PHY_REMOTE_100BTX 0x0080
357#define PHY_REMOTE_10BT_FD 0x0040
358#define PHY_REMOTE_10BT 0x0020
359
360/* P1VCT */
361#define KS884X_P1VCT_P 0x04F0
362#define KS884X_P1PHYCTRL_P 0x04F2
363
364/* P2VCT */
365#define KS884X_P2VCT_P 0x04F4
366#define KS884X_P2PHYCTRL_P 0x04F6
367
368#define KS884X_PHY_SPECIAL_OFFSET KS884X_P1VCT_P
369#define PHY_SPECIAL_INTERVAL (KS884X_P2VCT_P - KS884X_P1VCT_P)
370
371#define KS884X_PHY_LINK_MD_OFFSET 0x00
372
373#define PHY_START_CABLE_DIAG 0x8000
374#define PHY_CABLE_DIAG_RESULT 0x6000
375#define PHY_CABLE_STAT_NORMAL 0x0000
376#define PHY_CABLE_STAT_OPEN 0x2000
377#define PHY_CABLE_STAT_SHORT 0x4000
378#define PHY_CABLE_STAT_FAILED 0x6000
379#define PHY_CABLE_10M_SHORT 0x1000
380#define PHY_CABLE_FAULT_COUNTER 0x01FF
381
382#define KS884X_PHY_PHY_CTRL_OFFSET 0x02
383
384#define PHY_STAT_REVERSED_POLARITY 0x0020
385#define PHY_STAT_MDIX 0x0010
386#define PHY_FORCE_LINK 0x0008
387#define PHY_POWER_SAVING_DISABLE 0x0004
388#define PHY_REMOTE_LOOPBACK 0x0002
389
390/* SIDER */
391#define KS884X_SIDER_P 0x0400
392#define KS884X_CHIP_ID_OFFSET KS884X_SIDER_P
393#define KS884X_FAMILY_ID_OFFSET (KS884X_CHIP_ID_OFFSET + 1)
394
395#define REG_FAMILY_ID 0x88
396
397#define REG_CHIP_ID_41 0x8810
398#define REG_CHIP_ID_42 0x8800
399
400#define KS884X_CHIP_ID_MASK_41 0xFF10
401#define KS884X_CHIP_ID_MASK 0xFFF0
402#define KS884X_CHIP_ID_SHIFT 4
403#define KS884X_REVISION_MASK 0x000E
404#define KS884X_REVISION_SHIFT 1
405#define KS8842_START 0x0001
406
407#define CHIP_IP_41_M 0x8810
408#define CHIP_IP_42_M 0x8800
409#define CHIP_IP_61_M 0x8890
410#define CHIP_IP_62_M 0x8880
411
412#define CHIP_IP_41_P 0x8850
413#define CHIP_IP_42_P 0x8840
414#define CHIP_IP_61_P 0x88D0
415#define CHIP_IP_62_P 0x88C0
416
417/* SGCR1 */
418#define KS8842_SGCR1_P 0x0402
419#define KS8842_SWITCH_CTRL_1_OFFSET KS8842_SGCR1_P
420
421#define SWITCH_PASS_ALL 0x8000
422#define SWITCH_TX_FLOW_CTRL 0x2000
423#define SWITCH_RX_FLOW_CTRL 0x1000
424#define SWITCH_CHECK_LENGTH 0x0800
425#define SWITCH_AGING_ENABLE 0x0400
426#define SWITCH_FAST_AGING 0x0200
427#define SWITCH_AGGR_BACKOFF 0x0100
428#define SWITCH_PASS_PAUSE 0x0008
429#define SWITCH_LINK_AUTO_AGING 0x0001
430
431/* SGCR2 */
432#define KS8842_SGCR2_P 0x0404
433#define KS8842_SWITCH_CTRL_2_OFFSET KS8842_SGCR2_P
434
435#define SWITCH_VLAN_ENABLE 0x8000
436#define SWITCH_IGMP_SNOOP 0x4000
437#define IPV6_MLD_SNOOP_ENABLE 0x2000
438#define IPV6_MLD_SNOOP_OPTION 0x1000
439#define PRIORITY_SCHEME_SELECT 0x0800
440#define SWITCH_MIRROR_RX_TX 0x0100
441#define UNICAST_VLAN_BOUNDARY 0x0080
442#define MULTICAST_STORM_DISABLE 0x0040
443#define SWITCH_BACK_PRESSURE 0x0020
444#define FAIR_FLOW_CTRL 0x0010
445#define NO_EXC_COLLISION_DROP 0x0008
446#define SWITCH_HUGE_PACKET 0x0004
447#define SWITCH_LEGAL_PACKET 0x0002
448#define SWITCH_BUF_RESERVE 0x0001
449
450/* SGCR3 */
451#define KS8842_SGCR3_P 0x0406
452#define KS8842_SWITCH_CTRL_3_OFFSET KS8842_SGCR3_P
453
454#define BROADCAST_STORM_RATE_LO 0xFF00
455#define SWITCH_REPEATER 0x0080
456#define SWITCH_HALF_DUPLEX 0x0040
457#define SWITCH_FLOW_CTRL 0x0020
458#define SWITCH_10_MBIT 0x0010
459#define SWITCH_REPLACE_NULL_VID 0x0008
460#define BROADCAST_STORM_RATE_HI 0x0007
461
462#define BROADCAST_STORM_RATE 0x07FF
463
464/* SGCR4 */
465#define KS8842_SGCR4_P 0x0408
466
467/* SGCR5 */
468#define KS8842_SGCR5_P 0x040A
469#define KS8842_SWITCH_CTRL_5_OFFSET KS8842_SGCR5_P
470
471#define LED_MODE 0x8200
472#define LED_SPEED_DUPLEX_ACT 0x0000
473#define LED_SPEED_DUPLEX_LINK_ACT 0x8000
474#define LED_DUPLEX_10_100 0x0200
475
476/* SGCR6 */
477#define KS8842_SGCR6_P 0x0410
478#define KS8842_SWITCH_CTRL_6_OFFSET KS8842_SGCR6_P
479
480#define KS8842_PRIORITY_MASK 3
481#define KS8842_PRIORITY_SHIFT 2
482
483/* SGCR7 */
484#define KS8842_SGCR7_P 0x0412
485#define KS8842_SWITCH_CTRL_7_OFFSET KS8842_SGCR7_P
486
487#define SWITCH_UNK_DEF_PORT_ENABLE 0x0008
488#define SWITCH_UNK_DEF_PORT_3 0x0004
489#define SWITCH_UNK_DEF_PORT_2 0x0002
490#define SWITCH_UNK_DEF_PORT_1 0x0001
491
492/* MACAR1 */
493#define KS8842_MACAR1_P 0x0470
494#define KS8842_MACAR2_P 0x0472
495#define KS8842_MACAR3_P 0x0474
496#define KS8842_MAC_ADDR_1_OFFSET KS8842_MACAR1_P
497#define KS8842_MAC_ADDR_0_OFFSET (KS8842_MAC_ADDR_1_OFFSET + 1)
498#define KS8842_MAC_ADDR_3_OFFSET KS8842_MACAR2_P
499#define KS8842_MAC_ADDR_2_OFFSET (KS8842_MAC_ADDR_3_OFFSET + 1)
500#define KS8842_MAC_ADDR_5_OFFSET KS8842_MACAR3_P
501#define KS8842_MAC_ADDR_4_OFFSET (KS8842_MAC_ADDR_5_OFFSET + 1)
502
503/* TOSR1 */
504#define KS8842_TOSR1_P 0x0480
505#define KS8842_TOSR2_P 0x0482
506#define KS8842_TOSR3_P 0x0484
507#define KS8842_TOSR4_P 0x0486
508#define KS8842_TOSR5_P 0x0488
509#define KS8842_TOSR6_P 0x048A
510#define KS8842_TOSR7_P 0x0490
511#define KS8842_TOSR8_P 0x0492
512#define KS8842_TOS_1_OFFSET KS8842_TOSR1_P
513#define KS8842_TOS_2_OFFSET KS8842_TOSR2_P
514#define KS8842_TOS_3_OFFSET KS8842_TOSR3_P
515#define KS8842_TOS_4_OFFSET KS8842_TOSR4_P
516#define KS8842_TOS_5_OFFSET KS8842_TOSR5_P
517#define KS8842_TOS_6_OFFSET KS8842_TOSR6_P
518
519#define KS8842_TOS_7_OFFSET KS8842_TOSR7_P
520#define KS8842_TOS_8_OFFSET KS8842_TOSR8_P
521
522/* P1CR1 */
523#define KS8842_P1CR1_P 0x0500
524#define KS8842_P1CR2_P 0x0502
525#define KS8842_P1VIDR_P 0x0504
526#define KS8842_P1CR3_P 0x0506
527#define KS8842_P1IRCR_P 0x0508
528#define KS8842_P1ERCR_P 0x050A
529#define KS884X_P1SCSLMD_P 0x0510
530#define KS884X_P1CR4_P 0x0512
531#define KS884X_P1SR_P 0x0514
532
533/* P2CR1 */
534#define KS8842_P2CR1_P 0x0520
535#define KS8842_P2CR2_P 0x0522
536#define KS8842_P2VIDR_P 0x0524
537#define KS8842_P2CR3_P 0x0526
538#define KS8842_P2IRCR_P 0x0528
539#define KS8842_P2ERCR_P 0x052A
540#define KS884X_P2SCSLMD_P 0x0530
541#define KS884X_P2CR4_P 0x0532
542#define KS884X_P2SR_P 0x0534
543
544/* P3CR1 */
545#define KS8842_P3CR1_P 0x0540
546#define KS8842_P3CR2_P 0x0542
547#define KS8842_P3VIDR_P 0x0544
548#define KS8842_P3CR3_P 0x0546
549#define KS8842_P3IRCR_P 0x0548
550#define KS8842_P3ERCR_P 0x054A
551
552#define KS8842_PORT_1_CTRL_1 KS8842_P1CR1_P
553#define KS8842_PORT_2_CTRL_1 KS8842_P2CR1_P
554#define KS8842_PORT_3_CTRL_1 KS8842_P3CR1_P
555
556#define PORT_CTRL_ADDR(port, addr) \
557 (addr = KS8842_PORT_1_CTRL_1 + (port) * \
558 (KS8842_PORT_2_CTRL_1 - KS8842_PORT_1_CTRL_1))
559
560#define KS8842_PORT_CTRL_1_OFFSET 0x00
561
562#define PORT_BROADCAST_STORM 0x0080
563#define PORT_DIFFSERV_ENABLE 0x0040
564#define PORT_802_1P_ENABLE 0x0020
565#define PORT_BASED_PRIORITY_MASK 0x0018
566#define PORT_BASED_PRIORITY_BASE 0x0003
567#define PORT_BASED_PRIORITY_SHIFT 3
568#define PORT_BASED_PRIORITY_0 0x0000
569#define PORT_BASED_PRIORITY_1 0x0008
570#define PORT_BASED_PRIORITY_2 0x0010
571#define PORT_BASED_PRIORITY_3 0x0018
572#define PORT_INSERT_TAG 0x0004
573#define PORT_REMOVE_TAG 0x0002
574#define PORT_PRIO_QUEUE_ENABLE 0x0001
575
576#define KS8842_PORT_CTRL_2_OFFSET 0x02
577
578#define PORT_INGRESS_VLAN_FILTER 0x4000
579#define PORT_DISCARD_NON_VID 0x2000
580#define PORT_FORCE_FLOW_CTRL 0x1000
581#define PORT_BACK_PRESSURE 0x0800
582#define PORT_TX_ENABLE 0x0400
583#define PORT_RX_ENABLE 0x0200
584#define PORT_LEARN_DISABLE 0x0100
585#define PORT_MIRROR_SNIFFER 0x0080
586#define PORT_MIRROR_RX 0x0040
587#define PORT_MIRROR_TX 0x0020
588#define PORT_USER_PRIORITY_CEILING 0x0008
589#define PORT_VLAN_MEMBERSHIP 0x0007
590
591#define KS8842_PORT_CTRL_VID_OFFSET 0x04
592
593#define PORT_DEFAULT_VID 0x0001
594
595#define KS8842_PORT_CTRL_3_OFFSET 0x06
596
597#define PORT_INGRESS_LIMIT_MODE 0x000C
598#define PORT_INGRESS_ALL 0x0000
599#define PORT_INGRESS_UNICAST 0x0004
600#define PORT_INGRESS_MULTICAST 0x0008
601#define PORT_INGRESS_BROADCAST 0x000C
602#define PORT_COUNT_IFG 0x0002
603#define PORT_COUNT_PREAMBLE 0x0001
604
605#define KS8842_PORT_IN_RATE_OFFSET 0x08
606#define KS8842_PORT_OUT_RATE_OFFSET 0x0A
607
608#define PORT_PRIORITY_RATE 0x0F
609#define PORT_PRIORITY_RATE_SHIFT 4
610
611#define KS884X_PORT_LINK_MD 0x10
612
613#define PORT_CABLE_10M_SHORT 0x8000
614#define PORT_CABLE_DIAG_RESULT 0x6000
615#define PORT_CABLE_STAT_NORMAL 0x0000
616#define PORT_CABLE_STAT_OPEN 0x2000
617#define PORT_CABLE_STAT_SHORT 0x4000
618#define PORT_CABLE_STAT_FAILED 0x6000
619#define PORT_START_CABLE_DIAG 0x1000
620#define PORT_FORCE_LINK 0x0800
621#define PORT_POWER_SAVING_DISABLE 0x0400
622#define PORT_PHY_REMOTE_LOOPBACK 0x0200
623#define PORT_CABLE_FAULT_COUNTER 0x01FF
624
625#define KS884X_PORT_CTRL_4_OFFSET 0x12
626
627#define PORT_LED_OFF 0x8000
628#define PORT_TX_DISABLE 0x4000
629#define PORT_AUTO_NEG_RESTART 0x2000
630#define PORT_REMOTE_FAULT_DISABLE 0x1000
631#define PORT_POWER_DOWN 0x0800
632#define PORT_AUTO_MDIX_DISABLE 0x0400
633#define PORT_FORCE_MDIX 0x0200
634#define PORT_LOOPBACK 0x0100
635#define PORT_AUTO_NEG_ENABLE 0x0080
636#define PORT_FORCE_100_MBIT 0x0040
637#define PORT_FORCE_FULL_DUPLEX 0x0020
638#define PORT_AUTO_NEG_SYM_PAUSE 0x0010
639#define PORT_AUTO_NEG_100BTX_FD 0x0008
640#define PORT_AUTO_NEG_100BTX 0x0004
641#define PORT_AUTO_NEG_10BT_FD 0x0002
642#define PORT_AUTO_NEG_10BT 0x0001
643
644#define KS884X_PORT_STATUS_OFFSET 0x14
645
646#define PORT_HP_MDIX 0x8000
647#define PORT_REVERSED_POLARITY 0x2000
648#define PORT_RX_FLOW_CTRL 0x0800
649#define PORT_TX_FLOW_CTRL 0x1000
650#define PORT_STATUS_SPEED_100MBIT 0x0400
651#define PORT_STATUS_FULL_DUPLEX 0x0200
652#define PORT_REMOTE_FAULT 0x0100
653#define PORT_MDIX_STATUS 0x0080
654#define PORT_AUTO_NEG_COMPLETE 0x0040
655#define PORT_STATUS_LINK_GOOD 0x0020
656#define PORT_REMOTE_SYM_PAUSE 0x0010
657#define PORT_REMOTE_100BTX_FD 0x0008
658#define PORT_REMOTE_100BTX 0x0004
659#define PORT_REMOTE_10BT_FD 0x0002
660#define PORT_REMOTE_10BT 0x0001
661
662/*
663#define STATIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
664#define STATIC_MAC_TABLE_FWD_PORTS 00-00070000-00000000
665#define STATIC_MAC_TABLE_VALID 00-00080000-00000000
666#define STATIC_MAC_TABLE_OVERRIDE 00-00100000-00000000
667#define STATIC_MAC_TABLE_USE_FID 00-00200000-00000000
668#define STATIC_MAC_TABLE_FID 00-03C00000-00000000
669*/
670
671#define STATIC_MAC_TABLE_ADDR 0x0000FFFF
672#define STATIC_MAC_TABLE_FWD_PORTS 0x00070000
673#define STATIC_MAC_TABLE_VALID 0x00080000
674#define STATIC_MAC_TABLE_OVERRIDE 0x00100000
675#define STATIC_MAC_TABLE_USE_FID 0x00200000
676#define STATIC_MAC_TABLE_FID 0x03C00000
677
678#define STATIC_MAC_FWD_PORTS_SHIFT 16
679#define STATIC_MAC_FID_SHIFT 22
680
681/*
682#define VLAN_TABLE_VID 00-00000000-00000FFF
683#define VLAN_TABLE_FID 00-00000000-0000F000
684#define VLAN_TABLE_MEMBERSHIP 00-00000000-00070000
685#define VLAN_TABLE_VALID 00-00000000-00080000
686*/
687
688#define VLAN_TABLE_VID 0x00000FFF
689#define VLAN_TABLE_FID 0x0000F000
690#define VLAN_TABLE_MEMBERSHIP 0x00070000
691#define VLAN_TABLE_VALID 0x00080000
692
693#define VLAN_TABLE_FID_SHIFT 12
694#define VLAN_TABLE_MEMBERSHIP_SHIFT 16
695
696/*
697#define DYNAMIC_MAC_TABLE_ADDR 00-0000FFFF-FFFFFFFF
698#define DYNAMIC_MAC_TABLE_FID 00-000F0000-00000000
699#define DYNAMIC_MAC_TABLE_SRC_PORT 00-00300000-00000000
700#define DYNAMIC_MAC_TABLE_TIMESTAMP 00-00C00000-00000000
701#define DYNAMIC_MAC_TABLE_ENTRIES 03-FF000000-00000000
702#define DYNAMIC_MAC_TABLE_MAC_EMPTY 04-00000000-00000000
703#define DYNAMIC_MAC_TABLE_RESERVED 78-00000000-00000000
704#define DYNAMIC_MAC_TABLE_NOT_READY 80-00000000-00000000
705*/
706
707#define DYNAMIC_MAC_TABLE_ADDR 0x0000FFFF
708#define DYNAMIC_MAC_TABLE_FID 0x000F0000
709#define DYNAMIC_MAC_TABLE_SRC_PORT 0x00300000
710#define DYNAMIC_MAC_TABLE_TIMESTAMP 0x00C00000
711#define DYNAMIC_MAC_TABLE_ENTRIES 0xFF000000
712
713#define DYNAMIC_MAC_TABLE_ENTRIES_H 0x03
714#define DYNAMIC_MAC_TABLE_MAC_EMPTY 0x04
715#define DYNAMIC_MAC_TABLE_RESERVED 0x78
716#define DYNAMIC_MAC_TABLE_NOT_READY 0x80
717
718#define DYNAMIC_MAC_FID_SHIFT 16
719#define DYNAMIC_MAC_SRC_PORT_SHIFT 20
720#define DYNAMIC_MAC_TIMESTAMP_SHIFT 22
721#define DYNAMIC_MAC_ENTRIES_SHIFT 24
722#define DYNAMIC_MAC_ENTRIES_H_SHIFT 8
723
724/*
725#define MIB_COUNTER_VALUE 00-00000000-3FFFFFFF
726#define MIB_COUNTER_VALID 00-00000000-40000000
727#define MIB_COUNTER_OVERFLOW 00-00000000-80000000
728*/
729
730#define MIB_COUNTER_VALUE 0x3FFFFFFF
731#define MIB_COUNTER_VALID 0x40000000
732#define MIB_COUNTER_OVERFLOW 0x80000000
733
734#define MIB_PACKET_DROPPED 0x0000FFFF
735
736#define KS_MIB_PACKET_DROPPED_TX_0 0x100
737#define KS_MIB_PACKET_DROPPED_TX_1 0x101
738#define KS_MIB_PACKET_DROPPED_TX 0x102
739#define KS_MIB_PACKET_DROPPED_RX_0 0x103
740#define KS_MIB_PACKET_DROPPED_RX_1 0x104
741#define KS_MIB_PACKET_DROPPED_RX 0x105
742
743/* Change default LED mode. */
744#define SET_DEFAULT_LED LED_SPEED_DUPLEX_ACT
745
746#define MAC_ADDR_ORDER(i) (ETH_ALEN - 1 - (i))
747
748#define MAX_ETHERNET_BODY_SIZE 1500
749#define ETHERNET_HEADER_SIZE (14 + VLAN_HLEN)
750
751#define MAX_ETHERNET_PACKET_SIZE \
752 (MAX_ETHERNET_BODY_SIZE + ETHERNET_HEADER_SIZE)
753
754#define REGULAR_RX_BUF_SIZE (MAX_ETHERNET_PACKET_SIZE + 4)
755#define MAX_RX_BUF_SIZE (1912 + 4)
756
757#define ADDITIONAL_ENTRIES 16
758#define MAX_MULTICAST_LIST 32
759
760#define HW_MULTICAST_SIZE 8
761
762#define HW_TO_DEV_PORT(port) (port - 1)
763
764enum {
765 media_connected,
766 media_disconnected
767};
768
769enum {
770 OID_COUNTER_UNKOWN,
771
772 OID_COUNTER_FIRST,
773
774 /* total transmit errors */
775 OID_COUNTER_XMIT_ERROR,
776
777 /* total receive errors */
778 OID_COUNTER_RCV_ERROR,
779
780 OID_COUNTER_LAST
781};
782
783/*
784 * Hardware descriptor definitions
785 */
786
787#define DESC_ALIGNMENT 16
788#define BUFFER_ALIGNMENT 8
789
790#define NUM_OF_RX_DESC 64
791#define NUM_OF_TX_DESC 64
792
793#define KS_DESC_RX_FRAME_LEN 0x000007FF
794#define KS_DESC_RX_FRAME_TYPE 0x00008000
795#define KS_DESC_RX_ERROR_CRC 0x00010000
796#define KS_DESC_RX_ERROR_RUNT 0x00020000
797#define KS_DESC_RX_ERROR_TOO_LONG 0x00040000
798#define KS_DESC_RX_ERROR_PHY 0x00080000
799#define KS884X_DESC_RX_PORT_MASK 0x00300000
800#define KS_DESC_RX_MULTICAST 0x01000000
801#define KS_DESC_RX_ERROR 0x02000000
802#define KS_DESC_RX_ERROR_CSUM_UDP 0x04000000
803#define KS_DESC_RX_ERROR_CSUM_TCP 0x08000000
804#define KS_DESC_RX_ERROR_CSUM_IP 0x10000000
805#define KS_DESC_RX_LAST 0x20000000
806#define KS_DESC_RX_FIRST 0x40000000
807#define KS_DESC_RX_ERROR_COND \
808 (KS_DESC_RX_ERROR_CRC | \
809 KS_DESC_RX_ERROR_RUNT | \
810 KS_DESC_RX_ERROR_PHY | \
811 KS_DESC_RX_ERROR_TOO_LONG)
812
813#define KS_DESC_HW_OWNED 0x80000000
814
815#define KS_DESC_BUF_SIZE 0x000007FF
816#define KS884X_DESC_TX_PORT_MASK 0x00300000
817#define KS_DESC_END_OF_RING 0x02000000
818#define KS_DESC_TX_CSUM_GEN_UDP 0x04000000
819#define KS_DESC_TX_CSUM_GEN_TCP 0x08000000
820#define KS_DESC_TX_CSUM_GEN_IP 0x10000000
821#define KS_DESC_TX_LAST 0x20000000
822#define KS_DESC_TX_FIRST 0x40000000
823#define KS_DESC_TX_INTERRUPT 0x80000000
824
825#define KS_DESC_PORT_SHIFT 20
826
827#define KS_DESC_RX_MASK (KS_DESC_BUF_SIZE)
828
829#define KS_DESC_TX_MASK \
830 (KS_DESC_TX_INTERRUPT | \
831 KS_DESC_TX_FIRST | \
832 KS_DESC_TX_LAST | \
833 KS_DESC_TX_CSUM_GEN_IP | \
834 KS_DESC_TX_CSUM_GEN_TCP | \
835 KS_DESC_TX_CSUM_GEN_UDP | \
836 KS_DESC_BUF_SIZE)
837
838struct ksz_desc_rx_stat {
839#ifdef __BIG_ENDIAN_BITFIELD
840 u32 hw_owned:1;
841 u32 first_desc:1;
842 u32 last_desc:1;
843 u32 csum_err_ip:1;
844 u32 csum_err_tcp:1;
845 u32 csum_err_udp:1;
846 u32 error:1;
847 u32 multicast:1;
848 u32 src_port:4;
849 u32 err_phy:1;
850 u32 err_too_long:1;
851 u32 err_runt:1;
852 u32 err_crc:1;
853 u32 frame_type:1;
854 u32 reserved1:4;
855 u32 frame_len:11;
856#else
857 u32 frame_len:11;
858 u32 reserved1:4;
859 u32 frame_type:1;
860 u32 err_crc:1;
861 u32 err_runt:1;
862 u32 err_too_long:1;
863 u32 err_phy:1;
864 u32 src_port:4;
865 u32 multicast:1;
866 u32 error:1;
867 u32 csum_err_udp:1;
868 u32 csum_err_tcp:1;
869 u32 csum_err_ip:1;
870 u32 last_desc:1;
871 u32 first_desc:1;
872 u32 hw_owned:1;
873#endif
874};
875
876struct ksz_desc_tx_stat {
877#ifdef __BIG_ENDIAN_BITFIELD
878 u32 hw_owned:1;
879 u32 reserved1:31;
880#else
881 u32 reserved1:31;
882 u32 hw_owned:1;
883#endif
884};
885
886struct ksz_desc_rx_buf {
887#ifdef __BIG_ENDIAN_BITFIELD
888 u32 reserved4:6;
889 u32 end_of_ring:1;
890 u32 reserved3:14;
891 u32 buf_size:11;
892#else
893 u32 buf_size:11;
894 u32 reserved3:14;
895 u32 end_of_ring:1;
896 u32 reserved4:6;
897#endif
898};
899
900struct ksz_desc_tx_buf {
901#ifdef __BIG_ENDIAN_BITFIELD
902 u32 intr:1;
903 u32 first_seg:1;
904 u32 last_seg:1;
905 u32 csum_gen_ip:1;
906 u32 csum_gen_tcp:1;
907 u32 csum_gen_udp:1;
908 u32 end_of_ring:1;
909 u32 reserved4:1;
910 u32 dest_port:4;
911 u32 reserved3:9;
912 u32 buf_size:11;
913#else
914 u32 buf_size:11;
915 u32 reserved3:9;
916 u32 dest_port:4;
917 u32 reserved4:1;
918 u32 end_of_ring:1;
919 u32 csum_gen_udp:1;
920 u32 csum_gen_tcp:1;
921 u32 csum_gen_ip:1;
922 u32 last_seg:1;
923 u32 first_seg:1;
924 u32 intr:1;
925#endif
926};
927
928union desc_stat {
929 struct ksz_desc_rx_stat rx;
930 struct ksz_desc_tx_stat tx;
931 u32 data;
932};
933
934union desc_buf {
935 struct ksz_desc_rx_buf rx;
936 struct ksz_desc_tx_buf tx;
937 u32 data;
938};
939
940/**
941 * struct ksz_hw_desc - Hardware descriptor data structure
942 * @ctrl: Descriptor control value.
943 * @buf: Descriptor buffer value.
944 * @addr: Physical address of memory buffer.
945 * @next: Pointer to next hardware descriptor.
946 */
947struct ksz_hw_desc {
948 union desc_stat ctrl;
949 union desc_buf buf;
950 u32 addr;
951 u32 next;
952};
953
954/**
955 * struct ksz_sw_desc - Software descriptor data structure
956 * @ctrl: Descriptor control value.
957 * @buf: Descriptor buffer value.
958 * @buf_size: Current buffers size value in hardware descriptor.
959 */
960struct ksz_sw_desc {
961 union desc_stat ctrl;
962 union desc_buf buf;
963 u32 buf_size;
964};
965
966/**
967 * struct ksz_dma_buf - OS dependent DMA buffer data structure
968 * @skb: Associated socket buffer.
969 * @dma: Associated physical DMA address.
970 * len: Actual len used.
971 */
972struct ksz_dma_buf {
973 struct sk_buff *skb;
974 dma_addr_t dma;
975 int len;
976};
977
978/**
979 * struct ksz_desc - Descriptor structure
980 * @phw: Hardware descriptor pointer to uncached physical memory.
981 * @sw: Cached memory to hold hardware descriptor values for
982 * manipulation.
983 * @dma_buf: Operating system dependent data structure to hold physical
984 * memory buffer allocation information.
985 */
986struct ksz_desc {
987 struct ksz_hw_desc *phw;
988 struct ksz_sw_desc sw;
989 struct ksz_dma_buf dma_buf;
990};
991
992#define DMA_BUFFER(desc) ((struct ksz_dma_buf *)(&(desc)->dma_buf))
993
994/**
995 * struct ksz_desc_info - Descriptor information data structure
996 * @ring: First descriptor in the ring.
997 * @cur: Current descriptor being manipulated.
998 * @ring_virt: First hardware descriptor in the ring.
999 * @ring_phys: The physical address of the first descriptor of the ring.
1000 * @size: Size of hardware descriptor.
1001 * @alloc: Number of descriptors allocated.
1002 * @avail: Number of descriptors available for use.
1003 * @last: Index for last descriptor released to hardware.
1004 * @next: Index for next descriptor available for use.
1005 * @mask: Mask for index wrapping.
1006 */
1007struct ksz_desc_info {
1008 struct ksz_desc *ring;
1009 struct ksz_desc *cur;
1010 struct ksz_hw_desc *ring_virt;
1011 u32 ring_phys;
1012 int size;
1013 int alloc;
1014 int avail;
1015 int last;
1016 int next;
1017 int mask;
1018};
1019
1020/*
1021 * KSZ8842 switch definitions
1022 */
1023
1024enum {
1025 TABLE_STATIC_MAC = 0,
1026 TABLE_VLAN,
1027 TABLE_DYNAMIC_MAC,
1028 TABLE_MIB
1029};
1030
1031#define LEARNED_MAC_TABLE_ENTRIES 1024
1032#define STATIC_MAC_TABLE_ENTRIES 8
1033
1034/**
1035 * struct ksz_mac_table - Static MAC table data structure
1036 * @mac_addr: MAC address to filter.
1037 * @vid: VID value.
1038 * @fid: FID value.
1039 * @ports: Port membership.
1040 * @override: Override setting.
1041 * @use_fid: FID use setting.
1042 * @valid: Valid setting indicating the entry is being used.
1043 */
1044struct ksz_mac_table {
1045 u8 mac_addr[ETH_ALEN];
1046 u16 vid;
1047 u8 fid;
1048 u8 ports;
1049 u8 override:1;
1050 u8 use_fid:1;
1051 u8 valid:1;
1052};
1053
1054#define VLAN_TABLE_ENTRIES 16
1055
1056/**
1057 * struct ksz_vlan_table - VLAN table data structure
1058 * @vid: VID value.
1059 * @fid: FID value.
1060 * @member: Port membership.
1061 */
1062struct ksz_vlan_table {
1063 u16 vid;
1064 u8 fid;
1065 u8 member;
1066};
1067
1068#define DIFFSERV_ENTRIES 64
1069#define PRIO_802_1P_ENTRIES 8
1070#define PRIO_QUEUES 4
1071
1072#define SWITCH_PORT_NUM 2
1073#define TOTAL_PORT_NUM (SWITCH_PORT_NUM + 1)
1074#define HOST_MASK (1 << SWITCH_PORT_NUM)
1075#define PORT_MASK 7
1076
1077#define MAIN_PORT 0
1078#define OTHER_PORT 1
1079#define HOST_PORT SWITCH_PORT_NUM
1080
1081#define PORT_COUNTER_NUM 0x20
1082#define TOTAL_PORT_COUNTER_NUM (PORT_COUNTER_NUM + 2)
1083
1084#define MIB_COUNTER_RX_LO_PRIORITY 0x00
1085#define MIB_COUNTER_RX_HI_PRIORITY 0x01
1086#define MIB_COUNTER_RX_UNDERSIZE 0x02
1087#define MIB_COUNTER_RX_FRAGMENT 0x03
1088#define MIB_COUNTER_RX_OVERSIZE 0x04
1089#define MIB_COUNTER_RX_JABBER 0x05
1090#define MIB_COUNTER_RX_SYMBOL_ERR 0x06
1091#define MIB_COUNTER_RX_CRC_ERR 0x07
1092#define MIB_COUNTER_RX_ALIGNMENT_ERR 0x08
1093#define MIB_COUNTER_RX_CTRL_8808 0x09
1094#define MIB_COUNTER_RX_PAUSE 0x0A
1095#define MIB_COUNTER_RX_BROADCAST 0x0B
1096#define MIB_COUNTER_RX_MULTICAST 0x0C
1097#define MIB_COUNTER_RX_UNICAST 0x0D
1098#define MIB_COUNTER_RX_OCTET_64 0x0E
1099#define MIB_COUNTER_RX_OCTET_65_127 0x0F
1100#define MIB_COUNTER_RX_OCTET_128_255 0x10
1101#define MIB_COUNTER_RX_OCTET_256_511 0x11
1102#define MIB_COUNTER_RX_OCTET_512_1023 0x12
1103#define MIB_COUNTER_RX_OCTET_1024_1522 0x13
1104#define MIB_COUNTER_TX_LO_PRIORITY 0x14
1105#define MIB_COUNTER_TX_HI_PRIORITY 0x15
1106#define MIB_COUNTER_TX_LATE_COLLISION 0x16
1107#define MIB_COUNTER_TX_PAUSE 0x17
1108#define MIB_COUNTER_TX_BROADCAST 0x18
1109#define MIB_COUNTER_TX_MULTICAST 0x19
1110#define MIB_COUNTER_TX_UNICAST 0x1A
1111#define MIB_COUNTER_TX_DEFERRED 0x1B
1112#define MIB_COUNTER_TX_TOTAL_COLLISION 0x1C
1113#define MIB_COUNTER_TX_EXCESS_COLLISION 0x1D
1114#define MIB_COUNTER_TX_SINGLE_COLLISION 0x1E
1115#define MIB_COUNTER_TX_MULTI_COLLISION 0x1F
1116
1117#define MIB_COUNTER_RX_DROPPED_PACKET 0x20
1118#define MIB_COUNTER_TX_DROPPED_PACKET 0x21
1119
1120/**
1121 * struct ksz_port_mib - Port MIB data structure
1122 * @cnt_ptr: Current pointer to MIB counter index.
1123 * @link_down: Indication the link has just gone down.
1124 * @state: Connection status of the port.
1125 * @mib_start: The starting counter index. Some ports do not start at 0.
1126 * @counter: 64-bit MIB counter value.
1127 * @dropped: Temporary buffer to remember last read packet dropped values.
1128 *
1129 * MIB counters needs to be read periodically so that counters do not get
1130 * overflowed and give incorrect values. A right balance is needed to
1131 * satisfy this condition and not waste too much CPU time.
1132 *
1133 * It is pointless to read MIB counters when the port is disconnected. The
1134 * @state provides the connection status so that MIB counters are read only
1135 * when the port is connected. The @link_down indicates the port is just
1136 * disconnected so that all MIB counters are read one last time to update the
1137 * information.
1138 */
1139struct ksz_port_mib {
1140 u8 cnt_ptr;
1141 u8 link_down;
1142 u8 state;
1143 u8 mib_start;
1144
1145 u64 counter[TOTAL_PORT_COUNTER_NUM];
1146 u32 dropped[2];
1147};
1148
1149/**
1150 * struct ksz_port_cfg - Port configuration data structure
1151 * @vid: VID value.
1152 * @member: Port membership.
1153 * @port_prio: Port priority.
1154 * @rx_rate: Receive priority rate.
1155 * @tx_rate: Transmit priority rate.
1156 * @stp_state: Current Spanning Tree Protocol state.
1157 */
1158struct ksz_port_cfg {
1159 u16 vid;
1160 u8 member;
1161 u8 port_prio;
1162 u32 rx_rate[PRIO_QUEUES];
1163 u32 tx_rate[PRIO_QUEUES];
1164 int stp_state;
1165};
1166
1167/**
1168 * struct ksz_switch - KSZ8842 switch data structure
1169 * @mac_table: MAC table entries information.
1170 * @vlan_table: VLAN table entries information.
1171 * @port_cfg: Port configuration information.
1172 * @diffserv: DiffServ priority settings. Possible values from 6-bit of ToS
1173 * (bit7 ~ bit2) field.
1174 * @p_802_1p: 802.1P priority settings. Possible values from 3-bit of 802.1p
1175 * Tag priority field.
1176 * @br_addr: Bridge address. Used for STP.
1177 * @other_addr: Other MAC address. Used for multiple network device mode.
1178 * @broad_per: Broadcast storm percentage.
1179 * @member: Current port membership. Used for STP.
1180 */
1181struct ksz_switch {
1182 struct ksz_mac_table mac_table[STATIC_MAC_TABLE_ENTRIES];
1183 struct ksz_vlan_table vlan_table[VLAN_TABLE_ENTRIES];
1184 struct ksz_port_cfg port_cfg[TOTAL_PORT_NUM];
1185
1186 u8 diffserv[DIFFSERV_ENTRIES];
1187 u8 p_802_1p[PRIO_802_1P_ENTRIES];
1188
1189 u8 br_addr[ETH_ALEN];
1190 u8 other_addr[ETH_ALEN];
1191
1192 u8 broad_per;
1193 u8 member;
1194};
1195
1196#define TX_RATE_UNIT 10000
1197
1198/**
1199 * struct ksz_port_info - Port information data structure
1200 * @state: Connection status of the port.
1201 * @tx_rate: Transmit rate divided by 10000 to get Mbit.
1202 * @duplex: Duplex mode.
1203 * @advertised: Advertised auto-negotiation setting. Used to determine link.
1204 * @partner: Auto-negotiation partner setting. Used to determine link.
1205 * @port_id: Port index to access actual hardware register.
1206 * @pdev: Pointer to OS dependent network device.
1207 */
1208struct ksz_port_info {
1209 uint state;
1210 uint tx_rate;
1211 u8 duplex;
1212 u8 advertised;
1213 u8 partner;
1214 u8 port_id;
1215 void *pdev;
1216};
1217
1218#define MAX_TX_HELD_SIZE 52000
1219
1220/* Hardware features and bug fixes. */
1221#define LINK_INT_WORKING (1 << 0)
1222#define SMALL_PACKET_TX_BUG (1 << 1)
1223#define HALF_DUPLEX_SIGNAL_BUG (1 << 2)
1224#define RX_HUGE_FRAME (1 << 4)
1225#define STP_SUPPORT (1 << 8)
1226
1227/* Software overrides. */
1228#define PAUSE_FLOW_CTRL (1 << 0)
1229#define FAST_AGING (1 << 1)
1230
1231/**
1232 * struct ksz_hw - KSZ884X hardware data structure
1233 * @io: Virtual address assigned.
1234 * @ksz_switch: Pointer to KSZ8842 switch.
1235 * @port_info: Port information.
1236 * @port_mib: Port MIB information.
1237 * @dev_count: Number of network devices this hardware supports.
1238 * @dst_ports: Destination ports in switch for transmission.
1239 * @id: Hardware ID. Used for display only.
1240 * @mib_cnt: Number of MIB counters this hardware has.
1241 * @mib_port_cnt: Number of ports with MIB counters.
1242 * @tx_cfg: Cached transmit control settings.
1243 * @rx_cfg: Cached receive control settings.
1244 * @intr_mask: Current interrupt mask.
1245 * @intr_set: Current interrup set.
1246 * @intr_blocked: Interrupt blocked.
1247 * @rx_desc_info: Receive descriptor information.
1248 * @tx_desc_info: Transmit descriptor information.
1249 * @tx_int_cnt: Transmit interrupt count. Used for TX optimization.
1250 * @tx_int_mask: Transmit interrupt mask. Used for TX optimization.
1251 * @tx_size: Transmit data size. Used for TX optimization.
1252 * The maximum is defined by MAX_TX_HELD_SIZE.
1253 * @perm_addr: Permanent MAC address.
1254 * @override_addr: Overrided MAC address.
1255 * @address: Additional MAC address entries.
1256 * @addr_list_size: Additional MAC address list size.
1257 * @mac_override: Indication of MAC address overrided.
1258 * @promiscuous: Counter to keep track of promiscuous mode set.
1259 * @all_multi: Counter to keep track of all multicast mode set.
1260 * @multi_list: Multicast address entries.
1261 * @multi_bits: Cached multicast hash table settings.
1262 * @multi_list_size: Multicast address list size.
1263 * @enabled: Indication of hardware enabled.
1264 * @rx_stop: Indication of receive process stop.
1265 * @features: Hardware features to enable.
1266 * @overrides: Hardware features to override.
1267 * @parent: Pointer to parent, network device private structure.
1268 */
1269struct ksz_hw {
1270 void __iomem *io;
1271
1272 struct ksz_switch *ksz_switch;
1273 struct ksz_port_info port_info[SWITCH_PORT_NUM];
1274 struct ksz_port_mib port_mib[TOTAL_PORT_NUM];
1275 int dev_count;
1276 int dst_ports;
1277 int id;
1278 int mib_cnt;
1279 int mib_port_cnt;
1280
1281 u32 tx_cfg;
1282 u32 rx_cfg;
1283 u32 intr_mask;
1284 u32 intr_set;
1285 uint intr_blocked;
1286
1287 struct ksz_desc_info rx_desc_info;
1288 struct ksz_desc_info tx_desc_info;
1289
1290 int tx_int_cnt;
1291 int tx_int_mask;
1292 int tx_size;
1293
1294 u8 perm_addr[ETH_ALEN];
1295 u8 override_addr[ETH_ALEN];
1296 u8 address[ADDITIONAL_ENTRIES][ETH_ALEN];
1297 u8 addr_list_size;
1298 u8 mac_override;
1299 u8 promiscuous;
1300 u8 all_multi;
1301 u8 multi_list[MAX_MULTICAST_LIST][ETH_ALEN];
1302 u8 multi_bits[HW_MULTICAST_SIZE];
1303 u8 multi_list_size;
1304
1305 u8 enabled;
1306 u8 rx_stop;
1307 u8 reserved2[1];
1308
1309 uint features;
1310 uint overrides;
1311
1312 void *parent;
1313};
1314
1315enum {
1316 PHY_NO_FLOW_CTRL,
1317 PHY_FLOW_CTRL,
1318 PHY_TX_ONLY,
1319 PHY_RX_ONLY
1320};
1321
1322/**
1323 * struct ksz_port - Virtual port data structure
1324 * @duplex: Duplex mode setting. 1 for half duplex, 2 for full
1325 * duplex, and 0 for auto, which normally results in full
1326 * duplex.
1327 * @speed: Speed setting. 10 for 10 Mbit, 100 for 100 Mbit, and
1328 * 0 for auto, which normally results in 100 Mbit.
1329 * @force_link: Force link setting. 0 for auto-negotiation, and 1 for
1330 * force.
1331 * @flow_ctrl: Flow control setting. PHY_NO_FLOW_CTRL for no flow
1332 * control, and PHY_FLOW_CTRL for flow control.
1333 * PHY_TX_ONLY and PHY_RX_ONLY are not supported for 100
1334 * Mbit PHY.
1335 * @first_port: Index of first port this port supports.
1336 * @mib_port_cnt: Number of ports with MIB counters.
1337 * @port_cnt: Number of ports this port supports.
1338 * @counter: Port statistics counter.
1339 * @hw: Pointer to hardware structure.
1340 * @linked: Pointer to port information linked to this port.
1341 */
1342struct ksz_port {
1343 u8 duplex;
1344 u8 speed;
1345 u8 force_link;
1346 u8 flow_ctrl;
1347
1348 int first_port;
1349 int mib_port_cnt;
1350 int port_cnt;
1351 u64 counter[OID_COUNTER_LAST];
1352
1353 struct ksz_hw *hw;
1354 struct ksz_port_info *linked;
1355};
1356
1357/**
1358 * struct ksz_timer_info - Timer information data structure
1359 * @timer: Kernel timer.
1360 * @cnt: Running timer counter.
1361 * @max: Number of times to run timer; -1 for infinity.
1362 * @period: Timer period in jiffies.
1363 */
1364struct ksz_timer_info {
1365 struct timer_list timer;
1366 int cnt;
1367 int max;
1368 int period;
1369};
1370
1371/**
1372 * struct ksz_shared_mem - OS dependent shared memory data structure
1373 * @dma_addr: Physical DMA address allocated.
1374 * @alloc_size: Allocation size.
1375 * @phys: Actual physical address used.
1376 * @alloc_virt: Virtual address allocated.
1377 * @virt: Actual virtual address used.
1378 */
1379struct ksz_shared_mem {
1380 dma_addr_t dma_addr;
1381 uint alloc_size;
1382 uint phys;
1383 u8 *alloc_virt;
1384 u8 *virt;
1385};
1386
1387/**
1388 * struct ksz_counter_info - OS dependent counter information data structure
1389 * @counter: Wait queue to wakeup after counters are read.
1390 * @time: Next time in jiffies to read counter.
1391 * @read: Indication of counters read in full or not.
1392 */
1393struct ksz_counter_info {
1394 wait_queue_head_t counter;
1395 unsigned long time;
1396 int read;
1397};
1398
1399/**
1400 * struct dev_info - Network device information data structure
1401 * @dev: Pointer to network device.
1402 * @pdev: Pointer to PCI device.
1403 * @hw: Hardware structure.
1404 * @desc_pool: Physical memory used for descriptor pool.
1405 * @hwlock: Spinlock to prevent hardware from accessing.
1406 * @lock: Mutex lock to prevent device from accessing.
1407 * @dev_rcv: Receive process function used.
1408 * @last_skb: Socket buffer allocated for descriptor rx fragments.
1409 * @skb_index: Buffer index for receiving fragments.
1410 * @skb_len: Buffer length for receiving fragments.
1411 * @mib_read: Workqueue to read MIB counters.
1412 * @mib_timer_info: Timer to read MIB counters.
1413 * @counter: Used for MIB reading.
1414 * @mtu: Current MTU used. The default is REGULAR_RX_BUF_SIZE;
1415 * the maximum is MAX_RX_BUF_SIZE.
1416 * @opened: Counter to keep track of device open.
1417 * @rx_tasklet: Receive processing tasklet.
1418 * @tx_tasklet: Transmit processing tasklet.
1419 * @wol_enable: Wake-on-LAN enable set by ethtool.
1420 * @wol_support: Wake-on-LAN support used by ethtool.
1421 * @pme_wait: Used for KSZ8841 power management.
1422 */
1423struct dev_info {
1424 struct net_device *dev;
1425 struct pci_dev *pdev;
1426
1427 struct ksz_hw hw;
1428 struct ksz_shared_mem desc_pool;
1429
1430 spinlock_t hwlock;
1431 struct mutex lock;
1432
1433 int (*dev_rcv)(struct dev_info *);
1434
1435 struct sk_buff *last_skb;
1436 int skb_index;
1437 int skb_len;
1438
1439 struct work_struct mib_read;
1440 struct ksz_timer_info mib_timer_info;
1441 struct ksz_counter_info counter[TOTAL_PORT_NUM];
1442
1443 int mtu;
1444 int opened;
1445
1446 struct tasklet_struct rx_tasklet;
1447 struct tasklet_struct tx_tasklet;
1448
1449 int wol_enable;
1450 int wol_support;
1451 unsigned long pme_wait;
1452};
1453
1454/**
1455 * struct dev_priv - Network device private data structure
1456 * @adapter: Adapter device information.
1457 * @port: Port information.
1458 * @monitor_time_info: Timer to monitor ports.
1459 * @proc_sem: Semaphore for proc accessing.
1460 * @id: Device ID.
1461 * @mii_if: MII interface information.
1462 * @advertising: Temporary variable to store advertised settings.
1463 * @msg_enable: The message flags controlling driver output.
1464 * @media_state: The connection status of the device.
1465 * @multicast: The all multicast state of the device.
1466 * @promiscuous: The promiscuous state of the device.
1467 */
1468struct dev_priv {
1469 struct dev_info *adapter;
1470 struct ksz_port port;
1471 struct ksz_timer_info monitor_timer_info;
1472
1473 struct semaphore proc_sem;
1474 int id;
1475
1476 struct mii_if_info mii_if;
1477 u32 advertising;
1478
1479 u32 msg_enable;
1480 int media_state;
1481 int multicast;
1482 int promiscuous;
1483};
1484
1485#define DRV_NAME "KSZ884X PCI"
1486#define DEVICE_NAME "KSZ884x PCI"
1487#define DRV_VERSION "1.0.0"
1488#define DRV_RELDATE "Feb 8, 2010"
1489
1490static char version[] =
1491 "Micrel " DEVICE_NAME " " DRV_VERSION " (" DRV_RELDATE ")";
1492
1493static u8 DEFAULT_MAC_ADDRESS[] = { 0x00, 0x10, 0xA1, 0x88, 0x42, 0x01 };
1494
1495/*
1496 * Interrupt processing primary routines
1497 */
1498
1499static inline void hw_ack_intr(struct ksz_hw *hw, uint interrupt)
1500{
1501 writel(interrupt, hw->io + KS884X_INTERRUPTS_STATUS);
1502}
1503
1504static inline void hw_dis_intr(struct ksz_hw *hw)
1505{
1506 hw->intr_blocked = hw->intr_mask;
1507 writel(0, hw->io + KS884X_INTERRUPTS_ENABLE);
1508 hw->intr_set = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1509}
1510
1511static inline void hw_set_intr(struct ksz_hw *hw, uint interrupt)
1512{
1513 hw->intr_set = interrupt;
1514 writel(interrupt, hw->io + KS884X_INTERRUPTS_ENABLE);
1515}
1516
1517static inline void hw_ena_intr(struct ksz_hw *hw)
1518{
1519 hw->intr_blocked = 0;
1520 hw_set_intr(hw, hw->intr_mask);
1521}
1522
1523static inline void hw_dis_intr_bit(struct ksz_hw *hw, uint bit)
1524{
1525 hw->intr_mask &= ~(bit);
1526}
1527
1528static inline void hw_turn_off_intr(struct ksz_hw *hw, uint interrupt)
1529{
1530 u32 read_intr;
1531
1532 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1533 hw->intr_set = read_intr & ~interrupt;
1534 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1535 hw_dis_intr_bit(hw, interrupt);
1536}
1537
1538/**
1539 * hw_turn_on_intr - turn on specified interrupts
1540 * @hw: The hardware instance.
1541 * @bit: The interrupt bits to be on.
1542 *
1543 * This routine turns on the specified interrupts in the interrupt mask so that
1544 * those interrupts will be enabled.
1545 */
1546static void hw_turn_on_intr(struct ksz_hw *hw, u32 bit)
1547{
1548 hw->intr_mask |= bit;
1549
1550 if (!hw->intr_blocked)
1551 hw_set_intr(hw, hw->intr_mask);
1552}
1553
1554static inline void hw_ena_intr_bit(struct ksz_hw *hw, uint interrupt)
1555{
1556 u32 read_intr;
1557
1558 read_intr = readl(hw->io + KS884X_INTERRUPTS_ENABLE);
1559 hw->intr_set = read_intr | interrupt;
1560 writel(hw->intr_set, hw->io + KS884X_INTERRUPTS_ENABLE);
1561}
1562
1563static inline void hw_read_intr(struct ksz_hw *hw, uint *status)
1564{
1565 *status = readl(hw->io + KS884X_INTERRUPTS_STATUS);
1566 *status = *status & hw->intr_set;
1567}
1568
1569static inline void hw_restore_intr(struct ksz_hw *hw, uint interrupt)
1570{
1571 if (interrupt)
1572 hw_ena_intr(hw);
1573}
1574
1575/**
1576 * hw_block_intr - block hardware interrupts
1577 *
1578 * This function blocks all interrupts of the hardware and returns the current
1579 * interrupt enable mask so that interrupts can be restored later.
1580 *
1581 * Return the current interrupt enable mask.
1582 */
1583static uint hw_block_intr(struct ksz_hw *hw)
1584{
1585 uint interrupt = 0;
1586
1587 if (!hw->intr_blocked) {
1588 hw_dis_intr(hw);
1589 interrupt = hw->intr_blocked;
1590 }
1591 return interrupt;
1592}
1593
1594/*
1595 * Hardware descriptor routines
1596 */
1597
1598static inline void reset_desc(struct ksz_desc *desc, union desc_stat status)
1599{
1600 status.rx.hw_owned = 0;
1601 desc->phw->ctrl.data = cpu_to_le32(status.data);
1602}
1603
1604static inline void release_desc(struct ksz_desc *desc)
1605{
1606 desc->sw.ctrl.tx.hw_owned = 1;
1607 if (desc->sw.buf_size != desc->sw.buf.data) {
1608 desc->sw.buf_size = desc->sw.buf.data;
1609 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1610 }
1611 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1612}
1613
1614static void get_rx_pkt(struct ksz_desc_info *info, struct ksz_desc **desc)
1615{
1616 *desc = &info->ring[info->last];
1617 info->last++;
1618 info->last &= info->mask;
1619 info->avail--;
1620 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1621}
1622
1623static inline void set_rx_buf(struct ksz_desc *desc, u32 addr)
1624{
1625 desc->phw->addr = cpu_to_le32(addr);
1626}
1627
1628static inline void set_rx_len(struct ksz_desc *desc, u32 len)
1629{
1630 desc->sw.buf.rx.buf_size = len;
1631}
1632
1633static inline void get_tx_pkt(struct ksz_desc_info *info,
1634 struct ksz_desc **desc)
1635{
1636 *desc = &info->ring[info->next];
1637 info->next++;
1638 info->next &= info->mask;
1639 info->avail--;
1640 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1641}
1642
1643static inline void set_tx_buf(struct ksz_desc *desc, u32 addr)
1644{
1645 desc->phw->addr = cpu_to_le32(addr);
1646}
1647
1648static inline void set_tx_len(struct ksz_desc *desc, u32 len)
1649{
1650 desc->sw.buf.tx.buf_size = len;
1651}
1652
1653/* Switch functions */
1654
1655#define TABLE_READ 0x10
1656#define TABLE_SEL_SHIFT 2
1657
1658#define HW_DELAY(hw, reg) \
1659 do { \
1660 u16 dummy; \
1661 dummy = readw(hw->io + reg); \
1662 } while (0)
1663
1664/**
1665 * sw_r_table - read 4 bytes of data from switch table
1666 * @hw: The hardware instance.
1667 * @table: The table selector.
1668 * @addr: The address of the table entry.
1669 * @data: Buffer to store the read data.
1670 *
1671 * This routine reads 4 bytes of data from the table of the switch.
1672 * Hardware interrupts are disabled to minimize corruption of read data.
1673 */
1674static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1675{
1676 u16 ctrl_addr;
1677 uint interrupt;
1678
1679 ctrl_addr = (((table << TABLE_SEL_SHIFT) | TABLE_READ) << 8) | addr;
1680
1681 interrupt = hw_block_intr(hw);
1682
1683 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1684 HW_DELAY(hw, KS884X_IACR_OFFSET);
1685 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1686
1687 hw_restore_intr(hw, interrupt);
1688}
1689
1690/**
1691 * sw_w_table_64 - write 8 bytes of data to the switch table
1692 * @hw: The hardware instance.
1693 * @table: The table selector.
1694 * @addr: The address of the table entry.
1695 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1696 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1697 *
1698 * This routine writes 8 bytes of data to the table of the switch.
1699 * Hardware interrupts are disabled to minimize corruption of written data.
1700 */
1701static void sw_w_table_64(struct ksz_hw *hw, int table, u16 addr, u32 data_hi,
1702 u32 data_lo)
1703{
1704 u16 ctrl_addr;
1705 uint interrupt;
1706
1707 ctrl_addr = ((table << TABLE_SEL_SHIFT) << 8) | addr;
1708
1709 interrupt = hw_block_intr(hw);
1710
1711 writel(data_hi, hw->io + KS884X_ACC_DATA_4_OFFSET);
1712 writel(data_lo, hw->io + KS884X_ACC_DATA_0_OFFSET);
1713
1714 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1715 HW_DELAY(hw, KS884X_IACR_OFFSET);
1716
1717 hw_restore_intr(hw, interrupt);
1718}
1719
1720/**
1721 * sw_w_sta_mac_table - write to the static MAC table
1722 * @hw: The hardware instance.
1723 * @addr: The address of the table entry.
1724 * @mac_addr: The MAC address.
1725 * @ports: The port members.
1726 * @override: The flag to override the port receive/transmit settings.
1727 * @valid: The flag to indicate entry is valid.
1728 * @use_fid: The flag to indicate the FID is valid.
1729 * @fid: The FID value.
1730 *
1731 * This routine writes an entry of the static MAC table of the switch. It
1732 * calls sw_w_table_64() to write the data.
1733 */
1734static void sw_w_sta_mac_table(struct ksz_hw *hw, u16 addr, u8 *mac_addr,
1735 u8 ports, int override, int valid, int use_fid, u8 fid)
1736{
1737 u32 data_hi;
1738 u32 data_lo;
1739
1740 data_lo = ((u32) mac_addr[2] << 24) |
1741 ((u32) mac_addr[3] << 16) |
1742 ((u32) mac_addr[4] << 8) | mac_addr[5];
1743 data_hi = ((u32) mac_addr[0] << 8) | mac_addr[1];
1744 data_hi |= (u32) ports << STATIC_MAC_FWD_PORTS_SHIFT;
1745
1746 if (override)
1747 data_hi |= STATIC_MAC_TABLE_OVERRIDE;
1748 if (use_fid) {
1749 data_hi |= STATIC_MAC_TABLE_USE_FID;
1750 data_hi |= (u32) fid << STATIC_MAC_FID_SHIFT;
1751 }
1752 if (valid)
1753 data_hi |= STATIC_MAC_TABLE_VALID;
1754
1755 sw_w_table_64(hw, TABLE_STATIC_MAC, addr, data_hi, data_lo);
1756}
1757
1758/**
1759 * sw_r_vlan_table - read from the VLAN table
1760 * @hw: The hardware instance.
1761 * @addr: The address of the table entry.
1762 * @vid: Buffer to store the VID.
1763 * @fid: Buffer to store the VID.
1764 * @member: Buffer to store the port membership.
1765 *
1766 * This function reads an entry of the VLAN table of the switch. It calls
1767 * sw_r_table() to get the data.
1768 *
1769 * Return 0 if the entry is valid; otherwise -1.
1770 */
1771static int sw_r_vlan_table(struct ksz_hw *hw, u16 addr, u16 *vid, u8 *fid,
1772 u8 *member)
1773{
1774 u32 data;
1775
1776 sw_r_table(hw, TABLE_VLAN, addr, &data);
1777 if (data & VLAN_TABLE_VALID) {
1778 *vid = (u16)(data & VLAN_TABLE_VID);
1779 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1780 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1781 VLAN_TABLE_MEMBERSHIP_SHIFT);
1782 return 0;
1783 }
1784 return -1;
1785}
1786
1787/**
1788 * port_r_mib_cnt - read MIB counter
1789 * @hw: The hardware instance.
1790 * @port: The port index.
1791 * @addr: The address of the counter.
1792 * @cnt: Buffer to store the counter.
1793 *
1794 * This routine reads a MIB counter of the port.
1795 * Hardware interrupts are disabled to minimize corruption of read data.
1796 */
1797static void port_r_mib_cnt(struct ksz_hw *hw, int port, u16 addr, u64 *cnt)
1798{
1799 u32 data;
1800 u16 ctrl_addr;
1801 uint interrupt;
1802 int timeout;
1803
1804 ctrl_addr = addr + PORT_COUNTER_NUM * port;
1805
1806 interrupt = hw_block_intr(hw);
1807
1808 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ) << 8);
1809 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1810 HW_DELAY(hw, KS884X_IACR_OFFSET);
1811
1812 for (timeout = 100; timeout > 0; timeout--) {
1813 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1814
1815 if (data & MIB_COUNTER_VALID) {
1816 if (data & MIB_COUNTER_OVERFLOW)
1817 *cnt += MIB_COUNTER_VALUE + 1;
1818 *cnt += data & MIB_COUNTER_VALUE;
1819 break;
1820 }
1821 }
1822
1823 hw_restore_intr(hw, interrupt);
1824}
1825
1826/**
1827 * port_r_mib_pkt - read dropped packet counts
1828 * @hw: The hardware instance.
1829 * @port: The port index.
1830 * @cnt: Buffer to store the receive and transmit dropped packet counts.
1831 *
1832 * This routine reads the dropped packet counts of the port.
1833 * Hardware interrupts are disabled to minimize corruption of read data.
1834 */
1835static void port_r_mib_pkt(struct ksz_hw *hw, int port, u32 *last, u64 *cnt)
1836{
1837 u32 cur;
1838 u32 data;
1839 u16 ctrl_addr;
1840 uint interrupt;
1841 int index;
1842
1843 index = KS_MIB_PACKET_DROPPED_RX_0 + port;
1844 do {
1845 interrupt = hw_block_intr(hw);
1846
1847 ctrl_addr = (u16) index;
1848 ctrl_addr |= (((TABLE_MIB << TABLE_SEL_SHIFT) | TABLE_READ)
1849 << 8);
1850 writew(ctrl_addr, hw->io + KS884X_IACR_OFFSET);
1851 HW_DELAY(hw, KS884X_IACR_OFFSET);
1852 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1853
1854 hw_restore_intr(hw, interrupt);
1855
1856 data &= MIB_PACKET_DROPPED;
1857 cur = *last;
1858 if (data != cur) {
1859 *last = data;
1860 if (data < cur)
1861 data += MIB_PACKET_DROPPED + 1;
1862 data -= cur;
1863 *cnt += data;
1864 }
1865 ++last;
1866 ++cnt;
1867 index -= KS_MIB_PACKET_DROPPED_TX -
1868 KS_MIB_PACKET_DROPPED_TX_0 + 1;
1869 } while (index >= KS_MIB_PACKET_DROPPED_TX_0 + port);
1870}
1871
1872/**
1873 * port_r_cnt - read MIB counters periodically
1874 * @hw: The hardware instance.
1875 * @port: The port index.
1876 *
1877 * This routine is used to read the counters of the port periodically to avoid
1878 * counter overflow. The hardware should be acquired first before calling this
1879 * routine.
1880 *
1881 * Return non-zero when not all counters not read.
1882 */
1883static int port_r_cnt(struct ksz_hw *hw, int port)
1884{
1885 struct ksz_port_mib *mib = &hw->port_mib[port];
1886
1887 if (mib->mib_start < PORT_COUNTER_NUM)
1888 while (mib->cnt_ptr < PORT_COUNTER_NUM) {
1889 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1890 &mib->counter[mib->cnt_ptr]);
1891 ++mib->cnt_ptr;
1892 }
1893 if (hw->mib_cnt > PORT_COUNTER_NUM)
1894 port_r_mib_pkt(hw, port, mib->dropped,
1895 &mib->counter[PORT_COUNTER_NUM]);
1896 mib->cnt_ptr = 0;
1897 return 0;
1898}
1899
1900/**
1901 * port_init_cnt - initialize MIB counter values
1902 * @hw: The hardware instance.
1903 * @port: The port index.
1904 *
1905 * This routine is used to initialize all counters to zero if the hardware
1906 * cannot do it after reset.
1907 */
1908static void port_init_cnt(struct ksz_hw *hw, int port)
1909{
1910 struct ksz_port_mib *mib = &hw->port_mib[port];
1911
1912 mib->cnt_ptr = 0;
1913 if (mib->mib_start < PORT_COUNTER_NUM)
1914 do {
1915 port_r_mib_cnt(hw, port, mib->cnt_ptr,
1916 &mib->counter[mib->cnt_ptr]);
1917 ++mib->cnt_ptr;
1918 } while (mib->cnt_ptr < PORT_COUNTER_NUM);
1919 if (hw->mib_cnt > PORT_COUNTER_NUM)
1920 port_r_mib_pkt(hw, port, mib->dropped,
1921 &mib->counter[PORT_COUNTER_NUM]);
1922 memset((void *) mib->counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
1923 mib->cnt_ptr = 0;
1924}
1925
1926/*
1927 * Port functions
1928 */
1929
1930/**
1931 * port_chk - check port register bits
1932 * @hw: The hardware instance.
1933 * @port: The port index.
1934 * @offset: The offset of the port register.
1935 * @bits: The data bits to check.
1936 *
1937 * This function checks whether the specified bits of the port register are set
1938 * or not.
1939 *
1940 * Return 0 if the bits are not set.
1941 */
1942static int port_chk(struct ksz_hw *hw, int port, int offset, u16 bits)
1943{
1944 u32 addr;
1945 u16 data;
1946
1947 PORT_CTRL_ADDR(port, addr);
1948 addr += offset;
1949 data = readw(hw->io + addr);
1950 return (data & bits) == bits;
1951}
1952
1953/**
1954 * port_cfg - set port register bits
1955 * @hw: The hardware instance.
1956 * @port: The port index.
1957 * @offset: The offset of the port register.
1958 * @bits: The data bits to set.
1959 * @set: The flag indicating whether the bits are to be set or not.
1960 *
1961 * This routine sets or resets the specified bits of the port register.
1962 */
1963static void port_cfg(struct ksz_hw *hw, int port, int offset, u16 bits,
1964 int set)
1965{
1966 u32 addr;
1967 u16 data;
1968
1969 PORT_CTRL_ADDR(port, addr);
1970 addr += offset;
1971 data = readw(hw->io + addr);
1972 if (set)
1973 data |= bits;
1974 else
1975 data &= ~bits;
1976 writew(data, hw->io + addr);
1977}
1978
1979/**
1980 * port_chk_shift - check port bit
1981 * @hw: The hardware instance.
1982 * @port: The port index.
1983 * @offset: The offset of the register.
1984 * @shift: Number of bits to shift.
1985 *
1986 * This function checks whether the specified port is set in the register or
1987 * not.
1988 *
1989 * Return 0 if the port is not set.
1990 */
1991static int port_chk_shift(struct ksz_hw *hw, int port, u32 addr, int shift)
1992{
1993 u16 data;
1994 u16 bit = 1 << port;
1995
1996 data = readw(hw->io + addr);
1997 data >>= shift;
1998 return (data & bit) == bit;
1999}
2000
2001/**
2002 * port_cfg_shift - set port bit
2003 * @hw: The hardware instance.
2004 * @port: The port index.
2005 * @offset: The offset of the register.
2006 * @shift: Number of bits to shift.
2007 * @set: The flag indicating whether the port is to be set or not.
2008 *
2009 * This routine sets or resets the specified port in the register.
2010 */
2011static void port_cfg_shift(struct ksz_hw *hw, int port, u32 addr, int shift,
2012 int set)
2013{
2014 u16 data;
2015 u16 bits = 1 << port;
2016
2017 data = readw(hw->io + addr);
2018 bits <<= shift;
2019 if (set)
2020 data |= bits;
2021 else
2022 data &= ~bits;
2023 writew(data, hw->io + addr);
2024}
2025
2026/**
2027 * port_r8 - read byte from port register
2028 * @hw: The hardware instance.
2029 * @port: The port index.
2030 * @offset: The offset of the port register.
2031 * @data: Buffer to store the data.
2032 *
2033 * This routine reads a byte from the port register.
2034 */
2035static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
2036{
2037 u32 addr;
2038
2039 PORT_CTRL_ADDR(port, addr);
2040 addr += offset;
2041 *data = readb(hw->io + addr);
2042}
2043
2044/**
2045 * port_r16 - read word from port register.
2046 * @hw: The hardware instance.
2047 * @port: The port index.
2048 * @offset: The offset of the port register.
2049 * @data: Buffer to store the data.
2050 *
2051 * This routine reads a word from the port register.
2052 */
2053static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
2054{
2055 u32 addr;
2056
2057 PORT_CTRL_ADDR(port, addr);
2058 addr += offset;
2059 *data = readw(hw->io + addr);
2060}
2061
2062/**
2063 * port_w16 - write word to port register.
2064 * @hw: The hardware instance.
2065 * @port: The port index.
2066 * @offset: The offset of the port register.
2067 * @data: Data to write.
2068 *
2069 * This routine writes a word to the port register.
2070 */
2071static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2072{
2073 u32 addr;
2074
2075 PORT_CTRL_ADDR(port, addr);
2076 addr += offset;
2077 writew(data, hw->io + addr);
2078}
2079
2080/**
2081 * sw_chk - check switch register bits
2082 * @hw: The hardware instance.
2083 * @addr: The address of the switch register.
2084 * @bits: The data bits to check.
2085 *
2086 * This function checks whether the specified bits of the switch register are
2087 * set or not.
2088 *
2089 * Return 0 if the bits are not set.
2090 */
2091static int sw_chk(struct ksz_hw *hw, u32 addr, u16 bits)
2092{
2093 u16 data;
2094
2095 data = readw(hw->io + addr);
2096 return (data & bits) == bits;
2097}
2098
2099/**
2100 * sw_cfg - set switch register bits
2101 * @hw: The hardware instance.
2102 * @addr: The address of the switch register.
2103 * @bits: The data bits to set.
2104 * @set: The flag indicating whether the bits are to be set or not.
2105 *
2106 * This function sets or resets the specified bits of the switch register.
2107 */
2108static void sw_cfg(struct ksz_hw *hw, u32 addr, u16 bits, int set)
2109{
2110 u16 data;
2111
2112 data = readw(hw->io + addr);
2113 if (set)
2114 data |= bits;
2115 else
2116 data &= ~bits;
2117 writew(data, hw->io + addr);
2118}
2119
2120/* Bandwidth */
2121
2122static inline void port_cfg_broad_storm(struct ksz_hw *hw, int p, int set)
2123{
2124 port_cfg(hw, p,
2125 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM, set);
2126}
2127
2128static inline int port_chk_broad_storm(struct ksz_hw *hw, int p)
2129{
2130 return port_chk(hw, p,
2131 KS8842_PORT_CTRL_1_OFFSET, PORT_BROADCAST_STORM);
2132}
2133
2134/* Driver set switch broadcast storm protection at 10% rate. */
2135#define BROADCAST_STORM_PROTECTION_RATE 10
2136
2137/* 148,800 frames * 67 ms / 100 */
2138#define BROADCAST_STORM_VALUE 9969
2139
2140/**
2141 * sw_cfg_broad_storm - configure broadcast storm threshold
2142 * @hw: The hardware instance.
2143 * @percent: Broadcast storm threshold in percent of transmit rate.
2144 *
2145 * This routine configures the broadcast storm threshold of the switch.
2146 */
2147static void sw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2148{
2149 u16 data;
2150 u32 value = ((u32) BROADCAST_STORM_VALUE * (u32) percent / 100);
2151
2152 if (value > BROADCAST_STORM_RATE)
2153 value = BROADCAST_STORM_RATE;
2154
2155 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2156 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
2157 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
2158 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2159}
2160
2161/**
2162 * sw_get_board_storm - get broadcast storm threshold
2163 * @hw: The hardware instance.
2164 * @percent: Buffer to store the broadcast storm threshold percentage.
2165 *
2166 * This routine retrieves the broadcast storm threshold of the switch.
2167 */
2168static void sw_get_broad_storm(struct ksz_hw *hw, u8 *percent)
2169{
2170 int num;
2171 u16 data;
2172
2173 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2174 num = (data & BROADCAST_STORM_RATE_HI);
2175 num <<= 8;
2176 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2177 num = (num * 100 + BROADCAST_STORM_VALUE / 2) / BROADCAST_STORM_VALUE;
2178 *percent = (u8) num;
2179}
2180
2181/**
2182 * sw_dis_broad_storm - disable broadstorm
2183 * @hw: The hardware instance.
2184 * @port: The port index.
2185 *
2186 * This routine disables the broadcast storm limit function of the switch.
2187 */
2188static void sw_dis_broad_storm(struct ksz_hw *hw, int port)
2189{
2190 port_cfg_broad_storm(hw, port, 0);
2191}
2192
2193/**
2194 * sw_ena_broad_storm - enable broadcast storm
2195 * @hw: The hardware instance.
2196 * @port: The port index.
2197 *
2198 * This routine enables the broadcast storm limit function of the switch.
2199 */
2200static void sw_ena_broad_storm(struct ksz_hw *hw, int port)
2201{
2202 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2203 port_cfg_broad_storm(hw, port, 1);
2204}
2205
2206/**
2207 * sw_init_broad_storm - initialize broadcast storm
2208 * @hw: The hardware instance.
2209 *
2210 * This routine initializes the broadcast storm limit function of the switch.
2211 */
2212static void sw_init_broad_storm(struct ksz_hw *hw)
2213{
2214 int port;
2215
2216 hw->ksz_switch->broad_per = 1;
2217 sw_cfg_broad_storm(hw, hw->ksz_switch->broad_per);
2218 for (port = 0; port < TOTAL_PORT_NUM; port++)
2219 sw_dis_broad_storm(hw, port);
2220 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, MULTICAST_STORM_DISABLE, 1);
2221}
2222
2223/**
2224 * hw_cfg_broad_storm - configure broadcast storm
2225 * @hw: The hardware instance.
2226 * @percent: Broadcast storm threshold in percent of transmit rate.
2227 *
2228 * This routine configures the broadcast storm threshold of the switch.
2229 * It is called by user functions. The hardware should be acquired first.
2230 */
2231static void hw_cfg_broad_storm(struct ksz_hw *hw, u8 percent)
2232{
2233 if (percent > 100)
2234 percent = 100;
2235
2236 sw_cfg_broad_storm(hw, percent);
2237 sw_get_broad_storm(hw, &percent);
2238 hw->ksz_switch->broad_per = percent;
2239}
2240
2241/**
2242 * sw_dis_prio_rate - disable switch priority rate
2243 * @hw: The hardware instance.
2244 * @port: The port index.
2245 *
2246 * This routine disables the priority rate function of the switch.
2247 */
2248static void sw_dis_prio_rate(struct ksz_hw *hw, int port)
2249{
2250 u32 addr;
2251
2252 PORT_CTRL_ADDR(port, addr);
2253 addr += KS8842_PORT_IN_RATE_OFFSET;
2254 writel(0, hw->io + addr);
2255}
2256
2257/**
2258 * sw_init_prio_rate - initialize switch prioirty rate
2259 * @hw: The hardware instance.
2260 *
2261 * This routine initializes the priority rate function of the switch.
2262 */
2263static void sw_init_prio_rate(struct ksz_hw *hw)
2264{
2265 int port;
2266 int prio;
2267 struct ksz_switch *sw = hw->ksz_switch;
2268
2269 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2270 for (prio = 0; prio < PRIO_QUEUES; prio++) {
2271 sw->port_cfg[port].rx_rate[prio] =
2272 sw->port_cfg[port].tx_rate[prio] = 0;
2273 }
2274 sw_dis_prio_rate(hw, port);
2275 }
2276}
2277
2278/* Communication */
2279
2280static inline void port_cfg_back_pressure(struct ksz_hw *hw, int p, int set)
2281{
2282 port_cfg(hw, p,
2283 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE, set);
2284}
2285
2286static inline void port_cfg_force_flow_ctrl(struct ksz_hw *hw, int p, int set)
2287{
2288 port_cfg(hw, p,
2289 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL, set);
2290}
2291
2292static inline int port_chk_back_pressure(struct ksz_hw *hw, int p)
2293{
2294 return port_chk(hw, p,
2295 KS8842_PORT_CTRL_2_OFFSET, PORT_BACK_PRESSURE);
2296}
2297
2298static inline int port_chk_force_flow_ctrl(struct ksz_hw *hw, int p)
2299{
2300 return port_chk(hw, p,
2301 KS8842_PORT_CTRL_2_OFFSET, PORT_FORCE_FLOW_CTRL);
2302}
2303
2304/* Spanning Tree */
2305
2306static inline void port_cfg_dis_learn(struct ksz_hw *hw, int p, int set)
2307{
2308 port_cfg(hw, p,
2309 KS8842_PORT_CTRL_2_OFFSET, PORT_LEARN_DISABLE, set);
2310}
2311
2312static inline void port_cfg_rx(struct ksz_hw *hw, int p, int set)
2313{
2314 port_cfg(hw, p,
2315 KS8842_PORT_CTRL_2_OFFSET, PORT_RX_ENABLE, set);
2316}
2317
2318static inline void port_cfg_tx(struct ksz_hw *hw, int p, int set)
2319{
2320 port_cfg(hw, p,
2321 KS8842_PORT_CTRL_2_OFFSET, PORT_TX_ENABLE, set);
2322}
2323
2324static inline void sw_cfg_fast_aging(struct ksz_hw *hw, int set)
2325{
2326 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET, SWITCH_FAST_AGING, set);
2327}
2328
2329static inline void sw_flush_dyn_mac_table(struct ksz_hw *hw)
2330{
2331 if (!(hw->overrides & FAST_AGING)) {
2332 sw_cfg_fast_aging(hw, 1);
2333 mdelay(1);
2334 sw_cfg_fast_aging(hw, 0);
2335 }
2336}
2337
2338/* VLAN */
2339
2340static inline void port_cfg_ins_tag(struct ksz_hw *hw, int p, int insert)
2341{
2342 port_cfg(hw, p,
2343 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG, insert);
2344}
2345
2346static inline void port_cfg_rmv_tag(struct ksz_hw *hw, int p, int remove)
2347{
2348 port_cfg(hw, p,
2349 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG, remove);
2350}
2351
2352static inline int port_chk_ins_tag(struct ksz_hw *hw, int p)
2353{
2354 return port_chk(hw, p,
2355 KS8842_PORT_CTRL_1_OFFSET, PORT_INSERT_TAG);
2356}
2357
2358static inline int port_chk_rmv_tag(struct ksz_hw *hw, int p)
2359{
2360 return port_chk(hw, p,
2361 KS8842_PORT_CTRL_1_OFFSET, PORT_REMOVE_TAG);
2362}
2363
2364static inline void port_cfg_dis_non_vid(struct ksz_hw *hw, int p, int set)
2365{
2366 port_cfg(hw, p,
2367 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID, set);
2368}
2369
2370static inline void port_cfg_in_filter(struct ksz_hw *hw, int p, int set)
2371{
2372 port_cfg(hw, p,
2373 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER, set);
2374}
2375
2376static inline int port_chk_dis_non_vid(struct ksz_hw *hw, int p)
2377{
2378 return port_chk(hw, p,
2379 KS8842_PORT_CTRL_2_OFFSET, PORT_DISCARD_NON_VID);
2380}
2381
2382static inline int port_chk_in_filter(struct ksz_hw *hw, int p)
2383{
2384 return port_chk(hw, p,
2385 KS8842_PORT_CTRL_2_OFFSET, PORT_INGRESS_VLAN_FILTER);
2386}
2387
2388/* Mirroring */
2389
2390static inline void port_cfg_mirror_sniffer(struct ksz_hw *hw, int p, int set)
2391{
2392 port_cfg(hw, p,
2393 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_SNIFFER, set);
2394}
2395
2396static inline void port_cfg_mirror_rx(struct ksz_hw *hw, int p, int set)
2397{
2398 port_cfg(hw, p,
2399 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_RX, set);
2400}
2401
2402static inline void port_cfg_mirror_tx(struct ksz_hw *hw, int p, int set)
2403{
2404 port_cfg(hw, p,
2405 KS8842_PORT_CTRL_2_OFFSET, PORT_MIRROR_TX, set);
2406}
2407
2408static inline void sw_cfg_mirror_rx_tx(struct ksz_hw *hw, int set)
2409{
2410 sw_cfg(hw, KS8842_SWITCH_CTRL_2_OFFSET, SWITCH_MIRROR_RX_TX, set);
2411}
2412
2413static void sw_init_mirror(struct ksz_hw *hw)
2414{
2415 int port;
2416
2417 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2418 port_cfg_mirror_sniffer(hw, port, 0);
2419 port_cfg_mirror_rx(hw, port, 0);
2420 port_cfg_mirror_tx(hw, port, 0);
2421 }
2422 sw_cfg_mirror_rx_tx(hw, 0);
2423}
2424
2425static inline void sw_cfg_unk_def_deliver(struct ksz_hw *hw, int set)
2426{
2427 sw_cfg(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2428 SWITCH_UNK_DEF_PORT_ENABLE, set);
2429}
2430
2431static inline int sw_cfg_chk_unk_def_deliver(struct ksz_hw *hw)
2432{
2433 return sw_chk(hw, KS8842_SWITCH_CTRL_7_OFFSET,
2434 SWITCH_UNK_DEF_PORT_ENABLE);
2435}
2436
2437static inline void sw_cfg_unk_def_port(struct ksz_hw *hw, int port, int set)
2438{
2439 port_cfg_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0, set);
2440}
2441
2442static inline int sw_chk_unk_def_port(struct ksz_hw *hw, int port)
2443{
2444 return port_chk_shift(hw, port, KS8842_SWITCH_CTRL_7_OFFSET, 0);
2445}
2446
2447/* Priority */
2448
2449static inline void port_cfg_diffserv(struct ksz_hw *hw, int p, int set)
2450{
2451 port_cfg(hw, p,
2452 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE, set);
2453}
2454
2455static inline void port_cfg_802_1p(struct ksz_hw *hw, int p, int set)
2456{
2457 port_cfg(hw, p,
2458 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE, set);
2459}
2460
2461static inline void port_cfg_replace_vid(struct ksz_hw *hw, int p, int set)
2462{
2463 port_cfg(hw, p,
2464 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING, set);
2465}
2466
2467static inline void port_cfg_prio(struct ksz_hw *hw, int p, int set)
2468{
2469 port_cfg(hw, p,
2470 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE, set);
2471}
2472
2473static inline int port_chk_diffserv(struct ksz_hw *hw, int p)
2474{
2475 return port_chk(hw, p,
2476 KS8842_PORT_CTRL_1_OFFSET, PORT_DIFFSERV_ENABLE);
2477}
2478
2479static inline int port_chk_802_1p(struct ksz_hw *hw, int p)
2480{
2481 return port_chk(hw, p,
2482 KS8842_PORT_CTRL_1_OFFSET, PORT_802_1P_ENABLE);
2483}
2484
2485static inline int port_chk_replace_vid(struct ksz_hw *hw, int p)
2486{
2487 return port_chk(hw, p,
2488 KS8842_PORT_CTRL_2_OFFSET, PORT_USER_PRIORITY_CEILING);
2489}
2490
2491static inline int port_chk_prio(struct ksz_hw *hw, int p)
2492{
2493 return port_chk(hw, p,
2494 KS8842_PORT_CTRL_1_OFFSET, PORT_PRIO_QUEUE_ENABLE);
2495}
2496
2497/**
2498 * sw_dis_diffserv - disable switch DiffServ priority
2499 * @hw: The hardware instance.
2500 * @port: The port index.
2501 *
2502 * This routine disables the DiffServ priority function of the switch.
2503 */
2504static void sw_dis_diffserv(struct ksz_hw *hw, int port)
2505{
2506 port_cfg_diffserv(hw, port, 0);
2507}
2508
2509/**
2510 * sw_dis_802_1p - disable switch 802.1p priority
2511 * @hw: The hardware instance.
2512 * @port: The port index.
2513 *
2514 * This routine disables the 802.1p priority function of the switch.
2515 */
2516static void sw_dis_802_1p(struct ksz_hw *hw, int port)
2517{
2518 port_cfg_802_1p(hw, port, 0);
2519}
2520
2521/**
2522 * sw_cfg_replace_null_vid -
2523 * @hw: The hardware instance.
2524 * @set: The flag to disable or enable.
2525 *
2526 */
2527static void sw_cfg_replace_null_vid(struct ksz_hw *hw, int set)
2528{
2529 sw_cfg(hw, KS8842_SWITCH_CTRL_3_OFFSET, SWITCH_REPLACE_NULL_VID, set);
2530}
2531
2532/**
2533 * sw_cfg_replace_vid - enable switch 802.10 priority re-mapping
2534 * @hw: The hardware instance.
2535 * @port: The port index.
2536 * @set: The flag to disable or enable.
2537 *
2538 * This routine enables the 802.1p priority re-mapping function of the switch.
2539 * That allows 802.1p priority field to be replaced with the port's default
2540 * tag's priority value if the ingress packet's 802.1p priority has a higher
2541 * priority than port's default tag's priority.
2542 */
2543static void sw_cfg_replace_vid(struct ksz_hw *hw, int port, int set)
2544{
2545 port_cfg_replace_vid(hw, port, set);
2546}
2547
2548/**
2549 * sw_cfg_port_based - configure switch port based priority
2550 * @hw: The hardware instance.
2551 * @port: The port index.
2552 * @prio: The priority to set.
2553 *
2554 * This routine configures the port based priority of the switch.
2555 */
2556static void sw_cfg_port_based(struct ksz_hw *hw, int port, u8 prio)
2557{
2558 u16 data;
2559
2560 if (prio > PORT_BASED_PRIORITY_BASE)
2561 prio = PORT_BASED_PRIORITY_BASE;
2562
2563 hw->ksz_switch->port_cfg[port].port_prio = prio;
2564
2565 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2566 data &= ~PORT_BASED_PRIORITY_MASK;
2567 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2568 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2569}
2570
2571/**
2572 * sw_dis_multi_queue - disable transmit multiple queues
2573 * @hw: The hardware instance.
2574 * @port: The port index.
2575 *
2576 * This routine disables the transmit multiple queues selection of the switch
2577 * port. Only single transmit queue on the port.
2578 */
2579static void sw_dis_multi_queue(struct ksz_hw *hw, int port)
2580{
2581 port_cfg_prio(hw, port, 0);
2582}
2583
2584/**
2585 * sw_init_prio - initialize switch priority
2586 * @hw: The hardware instance.
2587 *
2588 * This routine initializes the switch QoS priority functions.
2589 */
2590static void sw_init_prio(struct ksz_hw *hw)
2591{
2592 int port;
2593 int tos;
2594 struct ksz_switch *sw = hw->ksz_switch;
2595
2596 /*
2597 * Init all the 802.1p tag priority value to be assigned to different
2598 * priority queue.
2599 */
2600 sw->p_802_1p[0] = 0;
2601 sw->p_802_1p[1] = 0;
2602 sw->p_802_1p[2] = 1;
2603 sw->p_802_1p[3] = 1;
2604 sw->p_802_1p[4] = 2;
2605 sw->p_802_1p[5] = 2;
2606 sw->p_802_1p[6] = 3;
2607 sw->p_802_1p[7] = 3;
2608
2609 /*
2610 * Init all the DiffServ priority value to be assigned to priority
2611 * queue 0.
2612 */
2613 for (tos = 0; tos < DIFFSERV_ENTRIES; tos++)
2614 sw->diffserv[tos] = 0;
2615
2616 /* All QoS functions disabled. */
2617 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2618 sw_dis_multi_queue(hw, port);
2619 sw_dis_diffserv(hw, port);
2620 sw_dis_802_1p(hw, port);
2621 sw_cfg_replace_vid(hw, port, 0);
2622
2623 sw->port_cfg[port].port_prio = 0;
2624 sw_cfg_port_based(hw, port, sw->port_cfg[port].port_prio);
2625 }
2626 sw_cfg_replace_null_vid(hw, 0);
2627}
2628
2629/**
2630 * port_get_def_vid - get port default VID.
2631 * @hw: The hardware instance.
2632 * @port: The port index.
2633 * @vid: Buffer to store the VID.
2634 *
2635 * This routine retrieves the default VID of the port.
2636 */
2637static void port_get_def_vid(struct ksz_hw *hw, int port, u16 *vid)
2638{
2639 u32 addr;
2640
2641 PORT_CTRL_ADDR(port, addr);
2642 addr += KS8842_PORT_CTRL_VID_OFFSET;
2643 *vid = readw(hw->io + addr);
2644}
2645
2646/**
2647 * sw_init_vlan - initialize switch VLAN
2648 * @hw: The hardware instance.
2649 *
2650 * This routine initializes the VLAN function of the switch.
2651 */
2652static void sw_init_vlan(struct ksz_hw *hw)
2653{
2654 int port;
2655 int entry;
2656 struct ksz_switch *sw = hw->ksz_switch;
2657
2658 /* Read 16 VLAN entries from device's VLAN table. */
2659 for (entry = 0; entry < VLAN_TABLE_ENTRIES; entry++) {
2660 sw_r_vlan_table(hw, entry,
2661 &sw->vlan_table[entry].vid,
2662 &sw->vlan_table[entry].fid,
2663 &sw->vlan_table[entry].member);
2664 }
2665
2666 for (port = 0; port < TOTAL_PORT_NUM; port++) {
2667 port_get_def_vid(hw, port, &sw->port_cfg[port].vid);
2668 sw->port_cfg[port].member = PORT_MASK;
2669 }
2670}
2671
2672/**
2673 * sw_cfg_port_base_vlan - configure port-based VLAN membership
2674 * @hw: The hardware instance.
2675 * @port: The port index.
2676 * @member: The port-based VLAN membership.
2677 *
2678 * This routine configures the port-based VLAN membership of the port.
2679 */
2680static void sw_cfg_port_base_vlan(struct ksz_hw *hw, int port, u8 member)
2681{
2682 u32 addr;
2683 u8 data;
2684
2685 PORT_CTRL_ADDR(port, addr);
2686 addr += KS8842_PORT_CTRL_2_OFFSET;
2687
2688 data = readb(hw->io + addr);
2689 data &= ~PORT_VLAN_MEMBERSHIP;
2690 data |= (member & PORT_MASK);
2691 writeb(data, hw->io + addr);
2692
2693 hw->ksz_switch->port_cfg[port].member = member;
2694}
2695
2696/**
2697 * sw_get_addr - get the switch MAC address.
2698 * @hw: The hardware instance.
2699 * @mac_addr: Buffer to store the MAC address.
2700 *
2701 * This function retrieves the MAC address of the switch.
2702 */
2703static inline void sw_get_addr(struct ksz_hw *hw, u8 *mac_addr)
2704{
2705 int i;
2706
2707 for (i = 0; i < 6; i += 2) {
2708 mac_addr[i] = readb(hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2709 mac_addr[1 + i] = readb(hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2710 }
2711}
2712
2713/**
2714 * sw_set_addr - configure switch MAC address
2715 * @hw: The hardware instance.
2716 * @mac_addr: The MAC address.
2717 *
2718 * This function configures the MAC address of the switch.
2719 */
2720static void sw_set_addr(struct ksz_hw *hw, u8 *mac_addr)
2721{
2722 int i;
2723
2724 for (i = 0; i < 6; i += 2) {
2725 writeb(mac_addr[i], hw->io + KS8842_MAC_ADDR_0_OFFSET + i);
2726 writeb(mac_addr[1 + i], hw->io + KS8842_MAC_ADDR_1_OFFSET + i);
2727 }
2728}
2729
2730/**
2731 * sw_set_global_ctrl - set switch global control
2732 * @hw: The hardware instance.
2733 *
2734 * This routine sets the global control of the switch function.
2735 */
2736static void sw_set_global_ctrl(struct ksz_hw *hw)
2737{
2738 u16 data;
2739
2740 /* Enable switch MII flow control. */
2741 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2742 data |= SWITCH_FLOW_CTRL;
2743 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2744
2745 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2746
2747 /* Enable aggressive back off algorithm in half duplex mode. */
2748 data |= SWITCH_AGGR_BACKOFF;
2749
2750 /* Enable automatic fast aging when link changed detected. */
2751 data |= SWITCH_AGING_ENABLE;
2752 data |= SWITCH_LINK_AUTO_AGING;
2753
2754 if (hw->overrides & FAST_AGING)
2755 data |= SWITCH_FAST_AGING;
2756 else
2757 data &= ~SWITCH_FAST_AGING;
2758 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2759
2760 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2761
2762 /* Enable no excessive collision drop. */
2763 data |= NO_EXC_COLLISION_DROP;
2764 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2765}
2766
2767enum {
2768 STP_STATE_DISABLED = 0,
2769 STP_STATE_LISTENING,
2770 STP_STATE_LEARNING,
2771 STP_STATE_FORWARDING,
2772 STP_STATE_BLOCKED,
2773 STP_STATE_SIMPLE
2774};
2775
2776/**
2777 * port_set_stp_state - configure port spanning tree state
2778 * @hw: The hardware instance.
2779 * @port: The port index.
2780 * @state: The spanning tree state.
2781 *
2782 * This routine configures the spanning tree state of the port.
2783 */
2784static void port_set_stp_state(struct ksz_hw *hw, int port, int state)
2785{
2786 u16 data;
2787
2788 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2789 switch (state) {
2790 case STP_STATE_DISABLED:
2791 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2792 data |= PORT_LEARN_DISABLE;
2793 break;
2794 case STP_STATE_LISTENING:
2795/*
2796 * No need to turn on transmit because of port direct mode.
2797 * Turning on receive is required if static MAC table is not setup.
2798 */
2799 data &= ~PORT_TX_ENABLE;
2800 data |= PORT_RX_ENABLE;
2801 data |= PORT_LEARN_DISABLE;
2802 break;
2803 case STP_STATE_LEARNING:
2804 data &= ~PORT_TX_ENABLE;
2805 data |= PORT_RX_ENABLE;
2806 data &= ~PORT_LEARN_DISABLE;
2807 break;
2808 case STP_STATE_FORWARDING:
2809 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2810 data &= ~PORT_LEARN_DISABLE;
2811 break;
2812 case STP_STATE_BLOCKED:
2813/*
2814 * Need to setup static MAC table with override to keep receiving BPDU
2815 * messages. See sw_init_stp routine.
2816 */
2817 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2818 data |= PORT_LEARN_DISABLE;
2819 break;
2820 case STP_STATE_SIMPLE:
2821 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2822 data |= PORT_LEARN_DISABLE;
2823 break;
2824 }
2825 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2826 hw->ksz_switch->port_cfg[port].stp_state = state;
2827}
2828
2829#define STP_ENTRY 0
2830#define BROADCAST_ENTRY 1
2831#define BRIDGE_ADDR_ENTRY 2
2832#define IPV6_ADDR_ENTRY 3
2833
2834/**
2835 * sw_clr_sta_mac_table - clear static MAC table
2836 * @hw: The hardware instance.
2837 *
2838 * This routine clears the static MAC table.
2839 */
2840static void sw_clr_sta_mac_table(struct ksz_hw *hw)
2841{
2842 struct ksz_mac_table *entry;
2843 int i;
2844
2845 for (i = 0; i < STATIC_MAC_TABLE_ENTRIES; i++) {
2846 entry = &hw->ksz_switch->mac_table[i];
2847 sw_w_sta_mac_table(hw, i,
2848 entry->mac_addr, entry->ports,
2849 entry->override, 0,
2850 entry->use_fid, entry->fid);
2851 }
2852}
2853
2854/**
2855 * sw_init_stp - initialize switch spanning tree support
2856 * @hw: The hardware instance.
2857 *
2858 * This routine initializes the spanning tree support of the switch.
2859 */
2860static void sw_init_stp(struct ksz_hw *hw)
2861{
2862 struct ksz_mac_table *entry;
2863
2864 entry = &hw->ksz_switch->mac_table[STP_ENTRY];
2865 entry->mac_addr[0] = 0x01;
2866 entry->mac_addr[1] = 0x80;
2867 entry->mac_addr[2] = 0xC2;
2868 entry->mac_addr[3] = 0x00;
2869 entry->mac_addr[4] = 0x00;
2870 entry->mac_addr[5] = 0x00;
2871 entry->ports = HOST_MASK;
2872 entry->override = 1;
2873 entry->valid = 1;
2874 sw_w_sta_mac_table(hw, STP_ENTRY,
2875 entry->mac_addr, entry->ports,
2876 entry->override, entry->valid,
2877 entry->use_fid, entry->fid);
2878}
2879
2880/**
2881 * sw_block_addr - block certain packets from the host port
2882 * @hw: The hardware instance.
2883 *
2884 * This routine blocks certain packets from reaching to the host port.
2885 */
2886static void sw_block_addr(struct ksz_hw *hw)
2887{
2888 struct ksz_mac_table *entry;
2889 int i;
2890
2891 for (i = BROADCAST_ENTRY; i <= IPV6_ADDR_ENTRY; i++) {
2892 entry = &hw->ksz_switch->mac_table[i];
2893 entry->valid = 0;
2894 sw_w_sta_mac_table(hw, i,
2895 entry->mac_addr, entry->ports,
2896 entry->override, entry->valid,
2897 entry->use_fid, entry->fid);
2898 }
2899}
2900
2901#define PHY_LINK_SUPPORT \
2902 (PHY_AUTO_NEG_ASYM_PAUSE | \
2903 PHY_AUTO_NEG_SYM_PAUSE | \
2904 PHY_AUTO_NEG_100BT4 | \
2905 PHY_AUTO_NEG_100BTX_FD | \
2906 PHY_AUTO_NEG_100BTX | \
2907 PHY_AUTO_NEG_10BT_FD | \
2908 PHY_AUTO_NEG_10BT)
2909
2910static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2911{
2912 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2913}
2914
2915static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2916{
2917 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2918}
2919
2920static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2921{
2922 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2923}
2924
2925static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2926{
2927 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2928}
2929
2930static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2931{
2932 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2933}
2934
2935static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2936{
2937 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2938}
2939
2940static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2941{
2942 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2943}
2944
2945static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2946{
2947 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2948}
2949
2950static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2951{
2952 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2953}
2954
2955static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2956{
2957 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2958}
2959
2960static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2961{
2962 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2963}
2964
2965static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2966{
2967 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2968}
2969
2970/**
2971 * hw_r_phy - read data from PHY register
2972 * @hw: The hardware instance.
2973 * @port: Port to read.
2974 * @reg: PHY register to read.
2975 * @val: Buffer to store the read data.
2976 *
2977 * This routine reads data from the PHY register.
2978 */
2979static void hw_r_phy(struct ksz_hw *hw, int port, u16 reg, u16 *val)
2980{
2981 int phy;
2982
2983 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
2984 *val = readw(hw->io + phy);
2985}
2986
2987/**
2988 * port_w_phy - write data to PHY register
2989 * @hw: The hardware instance.
2990 * @port: Port to write.
2991 * @reg: PHY register to write.
2992 * @val: Word data to write.
2993 *
2994 * This routine writes data to the PHY register.
2995 */
2996static void hw_w_phy(struct ksz_hw *hw, int port, u16 reg, u16 val)
2997{
2998 int phy;
2999
3000 phy = KS884X_PHY_1_CTRL_OFFSET + port * PHY_CTRL_INTERVAL + reg;
3001 writew(val, hw->io + phy);
3002}
3003
3004/*
3005 * EEPROM access functions
3006 */
3007
3008#define AT93C_CODE 0
3009#define AT93C_WR_OFF 0x00
3010#define AT93C_WR_ALL 0x10
3011#define AT93C_ER_ALL 0x20
3012#define AT93C_WR_ON 0x30
3013
3014#define AT93C_WRITE 1
3015#define AT93C_READ 2
3016#define AT93C_ERASE 3
3017
3018#define EEPROM_DELAY 4
3019
3020static inline void drop_gpio(struct ksz_hw *hw, u8 gpio)
3021{
3022 u16 data;
3023
3024 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3025 data &= ~gpio;
3026 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3027}
3028
3029static inline void raise_gpio(struct ksz_hw *hw, u8 gpio)
3030{
3031 u16 data;
3032
3033 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3034 data |= gpio;
3035 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3036}
3037
3038static inline u8 state_gpio(struct ksz_hw *hw, u8 gpio)
3039{
3040 u16 data;
3041
3042 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3043 return (u8)(data & gpio);
3044}
3045
3046static void eeprom_clk(struct ksz_hw *hw)
3047{
3048 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3049 udelay(EEPROM_DELAY);
3050 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3051 udelay(EEPROM_DELAY);
3052}
3053
3054static u16 spi_r(struct ksz_hw *hw)
3055{
3056 int i;
3057 u16 temp = 0;
3058
3059 for (i = 15; i >= 0; i--) {
3060 raise_gpio(hw, EEPROM_SERIAL_CLOCK);
3061 udelay(EEPROM_DELAY);
3062
3063 temp |= (state_gpio(hw, EEPROM_DATA_IN)) ? 1 << i : 0;
3064
3065 drop_gpio(hw, EEPROM_SERIAL_CLOCK);
3066 udelay(EEPROM_DELAY);
3067 }
3068 return temp;
3069}
3070
3071static void spi_w(struct ksz_hw *hw, u16 data)
3072{
3073 int i;
3074
3075 for (i = 15; i >= 0; i--) {
3076 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3077 drop_gpio(hw, EEPROM_DATA_OUT);
3078 eeprom_clk(hw);
3079 }
3080}
3081
3082static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
3083{
3084 int i;
3085
3086 /* Initial start bit */
3087 raise_gpio(hw, EEPROM_DATA_OUT);
3088 eeprom_clk(hw);
3089
3090 /* AT93C operation */
3091 for (i = 1; i >= 0; i--) {
3092 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3093 drop_gpio(hw, EEPROM_DATA_OUT);
3094 eeprom_clk(hw);
3095 }
3096
3097 /* Address location */
3098 for (i = 5; i >= 0; i--) {
3099 (reg & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3100 drop_gpio(hw, EEPROM_DATA_OUT);
3101 eeprom_clk(hw);
3102 }
3103}
3104
3105#define EEPROM_DATA_RESERVED 0
3106#define EEPROM_DATA_MAC_ADDR_0 1
3107#define EEPROM_DATA_MAC_ADDR_1 2
3108#define EEPROM_DATA_MAC_ADDR_2 3
3109#define EEPROM_DATA_SUBSYS_ID 4
3110#define EEPROM_DATA_SUBSYS_VEN_ID 5
3111#define EEPROM_DATA_PM_CAP 6
3112
3113/* User defined EEPROM data */
3114#define EEPROM_DATA_OTHER_MAC_ADDR 9
3115
3116/**
3117 * eeprom_read - read from AT93C46 EEPROM
3118 * @hw: The hardware instance.
3119 * @reg: The register offset.
3120 *
3121 * This function reads a word from the AT93C46 EEPROM.
3122 *
3123 * Return the data value.
3124 */
3125static u16 eeprom_read(struct ksz_hw *hw, u8 reg)
3126{
3127 u16 data;
3128
3129 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3130
3131 spi_reg(hw, AT93C_READ, reg);
3132 data = spi_r(hw);
3133
3134 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3135
3136 return data;
3137}
3138
3139/**
3140 * eeprom_write - write to AT93C46 EEPROM
3141 * @hw: The hardware instance.
3142 * @reg: The register offset.
3143 * @data: The data value.
3144 *
3145 * This procedure writes a word to the AT93C46 EEPROM.
3146 */
3147static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3148{
3149 int timeout;
3150
3151 raise_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3152
3153 /* Enable write. */
3154 spi_reg(hw, AT93C_CODE, AT93C_WR_ON);
3155 drop_gpio(hw, EEPROM_CHIP_SELECT);
3156 udelay(1);
3157
3158 /* Erase the register. */
3159 raise_gpio(hw, EEPROM_CHIP_SELECT);
3160 spi_reg(hw, AT93C_ERASE, reg);
3161 drop_gpio(hw, EEPROM_CHIP_SELECT);
3162 udelay(1);
3163
3164 /* Check operation complete. */
3165 raise_gpio(hw, EEPROM_CHIP_SELECT);
3166 timeout = 8;
3167 mdelay(2);
3168 do {
3169 mdelay(1);
3170 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3171 drop_gpio(hw, EEPROM_CHIP_SELECT);
3172 udelay(1);
3173
3174 /* Write the register. */
3175 raise_gpio(hw, EEPROM_CHIP_SELECT);
3176 spi_reg(hw, AT93C_WRITE, reg);
3177 spi_w(hw, data);
3178 drop_gpio(hw, EEPROM_CHIP_SELECT);
3179 udelay(1);
3180
3181 /* Check operation complete. */
3182 raise_gpio(hw, EEPROM_CHIP_SELECT);
3183 timeout = 8;
3184 mdelay(2);
3185 do {
3186 mdelay(1);
3187 } while (!state_gpio(hw, EEPROM_DATA_IN) && --timeout);
3188 drop_gpio(hw, EEPROM_CHIP_SELECT);
3189 udelay(1);
3190
3191 /* Disable write. */
3192 raise_gpio(hw, EEPROM_CHIP_SELECT);
3193 spi_reg(hw, AT93C_CODE, AT93C_WR_OFF);
3194
3195 drop_gpio(hw, EEPROM_ACCESS_ENABLE | EEPROM_CHIP_SELECT);
3196}
3197
3198/*
3199 * Link detection routines
3200 */
3201
3202static u16 advertised_flow_ctrl(struct ksz_port *port, u16 ctrl)
3203{
3204 ctrl &= ~PORT_AUTO_NEG_SYM_PAUSE;
3205 switch (port->flow_ctrl) {
3206 case PHY_FLOW_CTRL:
3207 ctrl |= PORT_AUTO_NEG_SYM_PAUSE;
3208 break;
3209 /* Not supported. */
3210 case PHY_TX_ONLY:
3211 case PHY_RX_ONLY:
3212 default:
3213 break;
3214 }
3215 return ctrl;
3216}
3217
3218static void set_flow_ctrl(struct ksz_hw *hw, int rx, int tx)
3219{
3220 u32 rx_cfg;
3221 u32 tx_cfg;
3222
3223 rx_cfg = hw->rx_cfg;
3224 tx_cfg = hw->tx_cfg;
3225 if (rx)
3226 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3227 else
3228 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3229 if (tx)
3230 hw->tx_cfg |= DMA_TX_FLOW_ENABLE;
3231 else
3232 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3233 if (hw->enabled) {
3234 if (rx_cfg != hw->rx_cfg)
3235 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3236 if (tx_cfg != hw->tx_cfg)
3237 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3238 }
3239}
3240
3241static void determine_flow_ctrl(struct ksz_hw *hw, struct ksz_port *port,
3242 u16 local, u16 remote)
3243{
3244 int rx;
3245 int tx;
3246
3247 if (hw->overrides & PAUSE_FLOW_CTRL)
3248 return;
3249
3250 rx = tx = 0;
3251 if (port->force_link)
3252 rx = tx = 1;
3253 if (remote & PHY_AUTO_NEG_SYM_PAUSE) {
3254 if (local & PHY_AUTO_NEG_SYM_PAUSE) {
3255 rx = tx = 1;
3256 } else if ((remote & PHY_AUTO_NEG_ASYM_PAUSE) &&
3257 (local & PHY_AUTO_NEG_PAUSE) ==
3258 PHY_AUTO_NEG_ASYM_PAUSE) {
3259 tx = 1;
3260 }
3261 } else if (remote & PHY_AUTO_NEG_ASYM_PAUSE) {
3262 if ((local & PHY_AUTO_NEG_PAUSE) == PHY_AUTO_NEG_PAUSE)
3263 rx = 1;
3264 }
3265 if (!hw->ksz_switch)
3266 set_flow_ctrl(hw, rx, tx);
3267}
3268
3269static inline void port_cfg_change(struct ksz_hw *hw, struct ksz_port *port,
3270 struct ksz_port_info *info, u16 link_status)
3271{
3272 if ((hw->features & HALF_DUPLEX_SIGNAL_BUG) &&
3273 !(hw->overrides & PAUSE_FLOW_CTRL)) {
3274 u32 cfg = hw->tx_cfg;
3275
3276 /* Disable flow control in the half duplex mode. */
3277 if (1 == info->duplex)
3278 hw->tx_cfg &= ~DMA_TX_FLOW_ENABLE;
3279 if (hw->enabled && cfg != hw->tx_cfg)
3280 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3281 }
3282}
3283
3284/**
3285 * port_get_link_speed - get current link status
3286 * @port: The port instance.
3287 *
3288 * This routine reads PHY registers to determine the current link status of the
3289 * switch ports.
3290 */
3291static void port_get_link_speed(struct ksz_port *port)
3292{
3293 uint interrupt;
3294 struct ksz_port_info *info;
3295 struct ksz_port_info *linked = NULL;
3296 struct ksz_hw *hw = port->hw;
3297 u16 data;
3298 u16 status;
3299 u8 local;
3300 u8 remote;
3301 int i;
3302 int p;
3303 int change = 0;
3304
3305 interrupt = hw_block_intr(hw);
3306
3307 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3308 info = &hw->port_info[p];
3309 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3310 port_r16(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3311
3312 /*
3313 * Link status is changing all the time even when there is no
3314 * cable connection!
3315 */
3316 remote = status & (PORT_AUTO_NEG_COMPLETE |
3317 PORT_STATUS_LINK_GOOD);
3318 local = (u8) data;
3319
3320 /* No change to status. */
3321 if (local == info->advertised && remote == info->partner)
3322 continue;
3323
3324 info->advertised = local;
3325 info->partner = remote;
3326 if (status & PORT_STATUS_LINK_GOOD) {
3327
3328 /* Remember the first linked port. */
3329 if (!linked)
3330 linked = info;
3331
3332 info->tx_rate = 10 * TX_RATE_UNIT;
3333 if (status & PORT_STATUS_SPEED_100MBIT)
3334 info->tx_rate = 100 * TX_RATE_UNIT;
3335
3336 info->duplex = 1;
3337 if (status & PORT_STATUS_FULL_DUPLEX)
3338 info->duplex = 2;
3339
3340 if (media_connected != info->state) {
3341 hw_r_phy(hw, p, KS884X_PHY_AUTO_NEG_OFFSET,
3342 &data);
3343 hw_r_phy(hw, p, KS884X_PHY_REMOTE_CAP_OFFSET,
3344 &status);
3345 determine_flow_ctrl(hw, port, data, status);
3346 if (hw->ksz_switch) {
3347 port_cfg_back_pressure(hw, p,
3348 (1 == info->duplex));
3349 }
3350 change |= 1 << i;
3351 port_cfg_change(hw, port, info, status);
3352 }
3353 info->state = media_connected;
3354 } else {
3355 if (media_disconnected != info->state) {
3356 change |= 1 << i;
3357
3358 /* Indicate the link just goes down. */
3359 hw->port_mib[p].link_down = 1;
3360 }
3361 info->state = media_disconnected;
3362 }
3363 hw->port_mib[p].state = (u8) info->state;
3364 }
3365
3366 if (linked && media_disconnected == port->linked->state)
3367 port->linked = linked;
3368
3369 hw_restore_intr(hw, interrupt);
3370}
3371
3372#define PHY_RESET_TIMEOUT 10
3373
3374/**
3375 * port_set_link_speed - set port speed
3376 * @port: The port instance.
3377 *
3378 * This routine sets the link speed of the switch ports.
3379 */
3380static void port_set_link_speed(struct ksz_port *port)
3381{
3382 struct ksz_port_info *info;
3383 struct ksz_hw *hw = port->hw;
3384 u16 data;
3385 u16 cfg;
3386 u8 status;
3387 int i;
3388 int p;
3389
3390 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3391 info = &hw->port_info[p];
3392
3393 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3394 port_r8(hw, p, KS884X_PORT_STATUS_OFFSET, &status);
3395
3396 cfg = 0;
3397 if (status & PORT_STATUS_LINK_GOOD)
3398 cfg = data;
3399
3400 data |= PORT_AUTO_NEG_ENABLE;
3401 data = advertised_flow_ctrl(port, data);
3402
3403 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3404 PORT_AUTO_NEG_10BT_FD | PORT_AUTO_NEG_10BT;
3405
3406 /* Check if manual configuration is specified by the user. */
3407 if (port->speed || port->duplex) {
3408 if (10 == port->speed)
3409 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3410 PORT_AUTO_NEG_100BTX);
3411 else if (100 == port->speed)
3412 data &= ~(PORT_AUTO_NEG_10BT_FD |
3413 PORT_AUTO_NEG_10BT);
3414 if (1 == port->duplex)
3415 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3416 PORT_AUTO_NEG_10BT_FD);
3417 else if (2 == port->duplex)
3418 data &= ~(PORT_AUTO_NEG_100BTX |
3419 PORT_AUTO_NEG_10BT);
3420 }
3421 if (data != cfg) {
3422 data |= PORT_AUTO_NEG_RESTART;
3423 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3424 }
3425 }
3426}
3427
3428/**
3429 * port_force_link_speed - force port speed
3430 * @port: The port instance.
3431 *
3432 * This routine forces the link speed of the switch ports.
3433 */
3434static void port_force_link_speed(struct ksz_port *port)
3435{
3436 struct ksz_hw *hw = port->hw;
3437 u16 data;
3438 int i;
3439 int phy;
3440 int p;
3441
3442 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
3443 phy = KS884X_PHY_1_CTRL_OFFSET + p * PHY_CTRL_INTERVAL;
3444 hw_r_phy_ctrl(hw, phy, &data);
3445
3446 data &= ~PHY_AUTO_NEG_ENABLE;
3447
3448 if (10 == port->speed)
3449 data &= ~PHY_SPEED_100MBIT;
3450 else if (100 == port->speed)
3451 data |= PHY_SPEED_100MBIT;
3452 if (1 == port->duplex)
3453 data &= ~PHY_FULL_DUPLEX;
3454 else if (2 == port->duplex)
3455 data |= PHY_FULL_DUPLEX;
3456 hw_w_phy_ctrl(hw, phy, data);
3457 }
3458}
3459
3460static void port_set_power_saving(struct ksz_port *port, int enable)
3461{
3462 struct ksz_hw *hw = port->hw;
3463 int i;
3464 int p;
3465
3466 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++)
3467 port_cfg(hw, p,
3468 KS884X_PORT_CTRL_4_OFFSET, PORT_POWER_DOWN, enable);
3469}
3470
3471/*
3472 * KSZ8841 power management functions
3473 */
3474
3475/**
3476 * hw_chk_wol_pme_status - check PMEN pin
3477 * @hw: The hardware instance.
3478 *
3479 * This function is used to check PMEN pin is asserted.
3480 *
3481 * Return 1 if PMEN pin is asserted; otherwise, 0.
3482 */
3483static int hw_chk_wol_pme_status(struct ksz_hw *hw)
3484{
3485 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3486 struct pci_dev *pdev = hw_priv->pdev;
3487 u16 data;
3488
3489 if (!pdev->pm_cap)
3490 return 0;
3491 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3492 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3493}
3494
3495/**
3496 * hw_clr_wol_pme_status - clear PMEN pin
3497 * @hw: The hardware instance.
3498 *
3499 * This routine is used to clear PME_Status to deassert PMEN pin.
3500 */
3501static void hw_clr_wol_pme_status(struct ksz_hw *hw)
3502{
3503 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3504 struct pci_dev *pdev = hw_priv->pdev;
3505 u16 data;
3506
3507 if (!pdev->pm_cap)
3508 return;
3509
3510 /* Clear PME_Status to deassert PMEN pin. */
3511 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3512 data |= PCI_PM_CTRL_PME_STATUS;
3513 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3514}
3515
3516/**
3517 * hw_cfg_wol_pme - enable or disable Wake-on-LAN
3518 * @hw: The hardware instance.
3519 * @set: The flag indicating whether to enable or disable.
3520 *
3521 * This routine is used to enable or disable Wake-on-LAN.
3522 */
3523static void hw_cfg_wol_pme(struct ksz_hw *hw, int set)
3524{
3525 struct dev_info *hw_priv = container_of(hw, struct dev_info, hw);
3526 struct pci_dev *pdev = hw_priv->pdev;
3527 u16 data;
3528
3529 if (!pdev->pm_cap)
3530 return;
3531 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3532 data &= ~PCI_PM_CTRL_STATE_MASK;
3533 if (set)
3534 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3535 else
3536 data &= ~PCI_PM_CTRL_PME_ENABLE;
3537 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3538}
3539
3540/**
3541 * hw_cfg_wol - configure Wake-on-LAN features
3542 * @hw: The hardware instance.
3543 * @frame: The pattern frame bit.
3544 * @set: The flag indicating whether to enable or disable.
3545 *
3546 * This routine is used to enable or disable certain Wake-on-LAN features.
3547 */
3548static void hw_cfg_wol(struct ksz_hw *hw, u16 frame, int set)
3549{
3550 u16 data;
3551
3552 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3553 if (set)
3554 data |= frame;
3555 else
3556 data &= ~frame;
3557 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3558}
3559
3560/**
3561 * hw_set_wol_frame - program Wake-on-LAN pattern
3562 * @hw: The hardware instance.
3563 * @i: The frame index.
3564 * @mask_size: The size of the mask.
3565 * @mask: Mask to ignore certain bytes in the pattern.
3566 * @frame_size: The size of the frame.
3567 * @pattern: The frame data.
3568 *
3569 * This routine is used to program Wake-on-LAN pattern.
3570 */
3571static void hw_set_wol_frame(struct ksz_hw *hw, int i, uint mask_size,
3572 const u8 *mask, uint frame_size, const u8 *pattern)
3573{
3574 int bits;
3575 int from;
3576 int len;
3577 int to;
3578 u32 crc;
3579 u8 data[64];
3580 u8 val = 0;
3581
3582 if (frame_size > mask_size * 8)
3583 frame_size = mask_size * 8;
3584 if (frame_size > 64)
3585 frame_size = 64;
3586
3587 i *= 0x10;
3588 writel(0, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i);
3589 writel(0, hw->io + KS8841_WOL_FRAME_BYTE2_OFFSET + i);
3590
3591 bits = len = from = to = 0;
3592 do {
3593 if (bits) {
3594 if ((val & 1))
3595 data[to++] = pattern[from];
3596 val >>= 1;
3597 ++from;
3598 --bits;
3599 } else {
3600 val = mask[len];
3601 writeb(val, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i
3602 + len);
3603 ++len;
3604 if (val)
3605 bits = 8;
3606 else
3607 from += 8;
3608 }
3609 } while (from < (int) frame_size);
3610 if (val) {
3611 bits = mask[len - 1];
3612 val <<= (from % 8);
3613 bits &= ~val;
3614 writeb(bits, hw->io + KS8841_WOL_FRAME_BYTE0_OFFSET + i + len -
3615 1);
3616 }
3617 crc = ether_crc(to, data);
3618 writel(crc, hw->io + KS8841_WOL_FRAME_CRC_OFFSET + i);
3619}
3620
3621/**
3622 * hw_add_wol_arp - add ARP pattern
3623 * @hw: The hardware instance.
3624 * @ip_addr: The IPv4 address assigned to the device.
3625 *
3626 * This routine is used to add ARP pattern for waking up the host.
3627 */
3628static void hw_add_wol_arp(struct ksz_hw *hw, const u8 *ip_addr)
3629{
3630 static const u8 mask[6] = { 0x3F, 0xF0, 0x3F, 0x00, 0xC0, 0x03 };
3631 u8 pattern[42] = {
3632 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
3633 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3634 0x08, 0x06,
3635 0x00, 0x01, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01,
3636 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3637 0x00, 0x00, 0x00, 0x00,
3638 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
3639 0x00, 0x00, 0x00, 0x00 };
3640
3641 memcpy(&pattern[38], ip_addr, 4);
3642 hw_set_wol_frame(hw, 3, 6, mask, 42, pattern);
3643}
3644
3645/**
3646 * hw_add_wol_bcast - add broadcast pattern
3647 * @hw: The hardware instance.
3648 *
3649 * This routine is used to add broadcast pattern for waking up the host.
3650 */
3651static void hw_add_wol_bcast(struct ksz_hw *hw)
3652{
3653 static const u8 mask[] = { 0x3F };
3654 static const u8 pattern[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
3655
3656 hw_set_wol_frame(hw, 2, 1, mask, ETH_ALEN, pattern);
3657}
3658
3659/**
3660 * hw_add_wol_mcast - add multicast pattern
3661 * @hw: The hardware instance.
3662 *
3663 * This routine is used to add multicast pattern for waking up the host.
3664 *
3665 * It is assumed the multicast packet is the ICMPv6 neighbor solicitation used
3666 * by IPv6 ping command. Note that multicast packets are filtred through the
3667 * multicast hash table, so not all multicast packets can wake up the host.
3668 */
3669static void hw_add_wol_mcast(struct ksz_hw *hw)
3670{
3671 static const u8 mask[] = { 0x3F };
3672 u8 pattern[] = { 0x33, 0x33, 0xFF, 0x00, 0x00, 0x00 };
3673
3674 memcpy(&pattern[3], &hw->override_addr[3], 3);
3675 hw_set_wol_frame(hw, 1, 1, mask, 6, pattern);
3676}
3677
3678/**
3679 * hw_add_wol_ucast - add unicast pattern
3680 * @hw: The hardware instance.
3681 *
3682 * This routine is used to add unicast pattern to wakeup the host.
3683 *
3684 * It is assumed the unicast packet is directed to the device, as the hardware
3685 * can only receive them in normal case.
3686 */
3687static void hw_add_wol_ucast(struct ksz_hw *hw)
3688{
3689 static const u8 mask[] = { 0x3F };
3690
3691 hw_set_wol_frame(hw, 0, 1, mask, ETH_ALEN, hw->override_addr);
3692}
3693
3694/**
3695 * hw_enable_wol - enable Wake-on-LAN
3696 * @hw: The hardware instance.
3697 * @wol_enable: The Wake-on-LAN settings.
3698 * @net_addr: The IPv4 address assigned to the device.
3699 *
3700 * This routine is used to enable Wake-on-LAN depending on driver settings.
3701 */
3702static void hw_enable_wol(struct ksz_hw *hw, u32 wol_enable, const u8 *net_addr)
3703{
3704 hw_cfg_wol(hw, KS8841_WOL_MAGIC_ENABLE, (wol_enable & WAKE_MAGIC));
3705 hw_cfg_wol(hw, KS8841_WOL_FRAME0_ENABLE, (wol_enable & WAKE_UCAST));
3706 hw_add_wol_ucast(hw);
3707 hw_cfg_wol(hw, KS8841_WOL_FRAME1_ENABLE, (wol_enable & WAKE_MCAST));
3708 hw_add_wol_mcast(hw);
3709 hw_cfg_wol(hw, KS8841_WOL_FRAME2_ENABLE, (wol_enable & WAKE_BCAST));
3710 hw_cfg_wol(hw, KS8841_WOL_FRAME3_ENABLE, (wol_enable & WAKE_ARP));
3711 hw_add_wol_arp(hw, net_addr);
3712}
3713
3714/**
3715 * hw_init - check driver is correct for the hardware
3716 * @hw: The hardware instance.
3717 *
3718 * This function checks the hardware is correct for this driver and sets the
3719 * hardware up for proper initialization.
3720 *
3721 * Return number of ports or 0 if not right.
3722 */
3723static int hw_init(struct ksz_hw *hw)
3724{
3725 int rc = 0;
3726 u16 data;
3727 u16 revision;
3728
3729 /* Set bus speed to 125MHz. */
3730 writew(BUS_SPEED_125_MHZ, hw->io + KS884X_BUS_CTRL_OFFSET);
3731
3732 /* Check KSZ884x chip ID. */
3733 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3734
3735 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3736 data &= KS884X_CHIP_ID_MASK_41;
3737 if (REG_CHIP_ID_41 == data)
3738 rc = 1;
3739 else if (REG_CHIP_ID_42 == data)
3740 rc = 2;
3741 else
3742 return 0;
3743
3744 /* Setup hardware features or bug workarounds. */
3745 if (revision <= 1) {
3746 hw->features |= SMALL_PACKET_TX_BUG;
3747 if (1 == rc)
3748 hw->features |= HALF_DUPLEX_SIGNAL_BUG;
3749 }
3750 return rc;
3751}
3752
3753/**
3754 * hw_reset - reset the hardware
3755 * @hw: The hardware instance.
3756 *
3757 * This routine resets the hardware.
3758 */
3759static void hw_reset(struct ksz_hw *hw)
3760{
3761 writew(GLOBAL_SOFTWARE_RESET, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3762
3763 /* Wait for device to reset. */
3764 mdelay(10);
3765
3766 /* Write 0 to clear device reset. */
3767 writew(0, hw->io + KS884X_GLOBAL_CTRL_OFFSET);
3768}
3769
3770/**
3771 * hw_setup - setup the hardware
3772 * @hw: The hardware instance.
3773 *
3774 * This routine setup the hardware for proper operation.
3775 */
3776static void hw_setup(struct ksz_hw *hw)
3777{
3778#if SET_DEFAULT_LED
3779 u16 data;
3780
3781 /* Change default LED mode. */
3782 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3783 data &= ~LED_MODE;
3784 data |= SET_DEFAULT_LED;
3785 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3786#endif
3787
3788 /* Setup transmit control. */
3789 hw->tx_cfg = (DMA_TX_PAD_ENABLE | DMA_TX_CRC_ENABLE |
3790 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_TX_ENABLE);
3791
3792 /* Setup receive control. */
3793 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3794 (DMA_BURST_DEFAULT << DMA_BURST_SHIFT) | DMA_RX_ENABLE);
3795 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3796
3797 /* Hardware cannot handle UDP packet in IP fragments. */
3798 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3799
3800 if (hw->all_multi)
3801 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3802 if (hw->promiscuous)
3803 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3804}
3805
3806/**
3807 * hw_setup_intr - setup interrupt mask
3808 * @hw: The hardware instance.
3809 *
3810 * This routine setup the interrupt mask for proper operation.
3811 */
3812static void hw_setup_intr(struct ksz_hw *hw)
3813{
3814 hw->intr_mask = KS884X_INT_MASK | KS884X_INT_RX_OVERRUN;
3815}
3816
3817static void ksz_check_desc_num(struct ksz_desc_info *info)
3818{
3819#define MIN_DESC_SHIFT 2
3820
3821 int alloc = info->alloc;
3822 int shift;
3823
3824 shift = 0;
3825 while (!(alloc & 1)) {
3826 shift++;
3827 alloc >>= 1;
3828 }
3829 if (alloc != 1 || shift < MIN_DESC_SHIFT) {
3830 pr_alert("Hardware descriptor numbers not right!\n");
3831 while (alloc) {
3832 shift++;
3833 alloc >>= 1;
3834 }
3835 if (shift < MIN_DESC_SHIFT)
3836 shift = MIN_DESC_SHIFT;
3837 alloc = 1 << shift;
3838 info->alloc = alloc;
3839 }
3840 info->mask = info->alloc - 1;
3841}
3842
3843static void hw_init_desc(struct ksz_desc_info *desc_info, int transmit)
3844{
3845 int i;
3846 u32 phys = desc_info->ring_phys;
3847 struct ksz_hw_desc *desc = desc_info->ring_virt;
3848 struct ksz_desc *cur = desc_info->ring;
3849 struct ksz_desc *previous = NULL;
3850
3851 for (i = 0; i < desc_info->alloc; i++) {
3852 cur->phw = desc++;
3853 phys += desc_info->size;
3854 previous = cur++;
3855 previous->phw->next = cpu_to_le32(phys);
3856 }
3857 previous->phw->next = cpu_to_le32(desc_info->ring_phys);
3858 previous->sw.buf.rx.end_of_ring = 1;
3859 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3860
3861 desc_info->avail = desc_info->alloc;
3862 desc_info->last = desc_info->next = 0;
3863
3864 desc_info->cur = desc_info->ring;
3865}
3866
3867/**
3868 * hw_set_desc_base - set descriptor base addresses
3869 * @hw: The hardware instance.
3870 * @tx_addr: The transmit descriptor base.
3871 * @rx_addr: The receive descriptor base.
3872 *
3873 * This routine programs the descriptor base addresses after reset.
3874 */
3875static void hw_set_desc_base(struct ksz_hw *hw, u32 tx_addr, u32 rx_addr)
3876{
3877 /* Set base address of Tx/Rx descriptors. */
3878 writel(tx_addr, hw->io + KS_DMA_TX_ADDR);
3879 writel(rx_addr, hw->io + KS_DMA_RX_ADDR);
3880}
3881
3882static void hw_reset_pkts(struct ksz_desc_info *info)
3883{
3884 info->cur = info->ring;
3885 info->avail = info->alloc;
3886 info->last = info->next = 0;
3887}
3888
3889static inline void hw_resume_rx(struct ksz_hw *hw)
3890{
3891 writel(DMA_START, hw->io + KS_DMA_RX_START);
3892}
3893
3894/**
3895 * hw_start_rx - start receiving
3896 * @hw: The hardware instance.
3897 *
3898 * This routine starts the receive function of the hardware.
3899 */
3900static void hw_start_rx(struct ksz_hw *hw)
3901{
3902 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3903
3904 /* Notify when the receive stops. */
3905 hw->intr_mask |= KS884X_INT_RX_STOPPED;
3906
3907 writel(DMA_START, hw->io + KS_DMA_RX_START);
3908 hw_ack_intr(hw, KS884X_INT_RX_STOPPED);
3909 hw->rx_stop++;
3910
3911 /* Variable overflows. */
3912 if (0 == hw->rx_stop)
3913 hw->rx_stop = 2;
3914}
3915
3916/**
3917 * hw_stop_rx - stop receiving
3918 * @hw: The hardware instance.
3919 *
3920 * This routine stops the receive function of the hardware.
3921 */
3922static void hw_stop_rx(struct ksz_hw *hw)
3923{
3924 hw->rx_stop = 0;
3925 hw_turn_off_intr(hw, KS884X_INT_RX_STOPPED);
3926 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
3927}
3928
3929/**
3930 * hw_start_tx - start transmitting
3931 * @hw: The hardware instance.
3932 *
3933 * This routine starts the transmit function of the hardware.
3934 */
3935static void hw_start_tx(struct ksz_hw *hw)
3936{
3937 writel(hw->tx_cfg, hw->io + KS_DMA_TX_CTRL);
3938}
3939
3940/**
3941 * hw_stop_tx - stop transmitting
3942 * @hw: The hardware instance.
3943 *
3944 * This routine stops the transmit function of the hardware.
3945 */
3946static void hw_stop_tx(struct ksz_hw *hw)
3947{
3948 writel((hw->tx_cfg & ~DMA_TX_ENABLE), hw->io + KS_DMA_TX_CTRL);
3949}
3950
3951/**
3952 * hw_disable - disable hardware
3953 * @hw: The hardware instance.
3954 *
3955 * This routine disables the hardware.
3956 */
3957static void hw_disable(struct ksz_hw *hw)
3958{
3959 hw_stop_rx(hw);
3960 hw_stop_tx(hw);
3961 hw->enabled = 0;
3962}
3963
3964/**
3965 * hw_enable - enable hardware
3966 * @hw: The hardware instance.
3967 *
3968 * This routine enables the hardware.
3969 */
3970static void hw_enable(struct ksz_hw *hw)
3971{
3972 hw_start_tx(hw);
3973 hw_start_rx(hw);
3974 hw->enabled = 1;
3975}
3976
3977/**
3978 * hw_alloc_pkt - allocate enough descriptors for transmission
3979 * @hw: The hardware instance.
3980 * @length: The length of the packet.
3981 * @physical: Number of descriptors required.
3982 *
3983 * This function allocates descriptors for transmission.
3984 *
3985 * Return 0 if not successful; 1 for buffer copy; or number of descriptors.
3986 */
3987static int hw_alloc_pkt(struct ksz_hw *hw, int length, int physical)
3988{
3989 /* Always leave one descriptor free. */
3990 if (hw->tx_desc_info.avail <= 1)
3991 return 0;
3992
3993 /* Allocate a descriptor for transmission and mark it current. */
3994 get_tx_pkt(&hw->tx_desc_info, &hw->tx_desc_info.cur);
3995 hw->tx_desc_info.cur->sw.buf.tx.first_seg = 1;
3996
3997 /* Keep track of number of transmit descriptors used so far. */
3998 ++hw->tx_int_cnt;
3999 hw->tx_size += length;
4000
4001 /* Cannot hold on too much data. */
4002 if (hw->tx_size >= MAX_TX_HELD_SIZE)
4003 hw->tx_int_cnt = hw->tx_int_mask + 1;
4004
4005 if (physical > hw->tx_desc_info.avail)
4006 return 1;
4007
4008 return hw->tx_desc_info.avail;
4009}
4010
4011/**
4012 * hw_send_pkt - mark packet for transmission
4013 * @hw: The hardware instance.
4014 *
4015 * This routine marks the packet for transmission in PCI version.
4016 */
4017static void hw_send_pkt(struct ksz_hw *hw)
4018{
4019 struct ksz_desc *cur = hw->tx_desc_info.cur;
4020
4021 cur->sw.buf.tx.last_seg = 1;
4022
4023 /* Interrupt only after specified number of descriptors used. */
4024 if (hw->tx_int_cnt > hw->tx_int_mask) {
4025 cur->sw.buf.tx.intr = 1;
4026 hw->tx_int_cnt = 0;
4027 hw->tx_size = 0;
4028 }
4029
4030 /* KSZ8842 supports port directed transmission. */
4031 cur->sw.buf.tx.dest_port = hw->dst_ports;
4032
4033 release_desc(cur);
4034
4035 writel(0, hw->io + KS_DMA_TX_START);
4036}
4037
4038static int empty_addr(u8 *addr)
4039{
4040 u32 *addr1 = (u32 *) addr;
4041 u16 *addr2 = (u16 *) &addr[4];
4042
4043 return 0 == *addr1 && 0 == *addr2;
4044}
4045
4046/**
4047 * hw_set_addr - set MAC address
4048 * @hw: The hardware instance.
4049 *
4050 * This routine programs the MAC address of the hardware when the address is
4051 * overrided.
4052 */
4053static void hw_set_addr(struct ksz_hw *hw)
4054{
4055 int i;
4056
4057 for (i = 0; i < ETH_ALEN; i++)
4058 writeb(hw->override_addr[MAC_ADDR_ORDER(i)],
4059 hw->io + KS884X_ADDR_0_OFFSET + i);
4060
4061 sw_set_addr(hw, hw->override_addr);
4062}
4063
4064/**
4065 * hw_read_addr - read MAC address
4066 * @hw: The hardware instance.
4067 *
4068 * This routine retrieves the MAC address of the hardware.
4069 */
4070static void hw_read_addr(struct ksz_hw *hw)
4071{
4072 int i;
4073
4074 for (i = 0; i < ETH_ALEN; i++)
4075 hw->perm_addr[MAC_ADDR_ORDER(i)] = readb(hw->io +
4076 KS884X_ADDR_0_OFFSET + i);
4077
4078 if (!hw->mac_override) {
4079 memcpy(hw->override_addr, hw->perm_addr, ETH_ALEN);
4080 if (empty_addr(hw->override_addr)) {
4081 memcpy(hw->perm_addr, DEFAULT_MAC_ADDRESS, ETH_ALEN);
4082 memcpy(hw->override_addr, DEFAULT_MAC_ADDRESS,
4083 ETH_ALEN);
4084 hw->override_addr[5] += hw->id;
4085 hw_set_addr(hw);
4086 }
4087 }
4088}
4089
4090static void hw_ena_add_addr(struct ksz_hw *hw, int index, u8 *mac_addr)
4091{
4092 int i;
4093 u32 mac_addr_lo;
4094 u32 mac_addr_hi;
4095
4096 mac_addr_hi = 0;
4097 for (i = 0; i < 2; i++) {
4098 mac_addr_hi <<= 8;
4099 mac_addr_hi |= mac_addr[i];
4100 }
4101 mac_addr_hi |= ADD_ADDR_ENABLE;
4102 mac_addr_lo = 0;
4103 for (i = 2; i < 6; i++) {
4104 mac_addr_lo <<= 8;
4105 mac_addr_lo |= mac_addr[i];
4106 }
4107 index *= ADD_ADDR_INCR;
4108
4109 writel(mac_addr_lo, hw->io + index + KS_ADD_ADDR_0_LO);
4110 writel(mac_addr_hi, hw->io + index + KS_ADD_ADDR_0_HI);
4111}
4112
4113static void hw_set_add_addr(struct ksz_hw *hw)
4114{
4115 int i;
4116
4117 for (i = 0; i < ADDITIONAL_ENTRIES; i++) {
4118 if (empty_addr(hw->address[i]))
4119 writel(0, hw->io + ADD_ADDR_INCR * i +
4120 KS_ADD_ADDR_0_HI);
4121 else
4122 hw_ena_add_addr(hw, i, hw->address[i]);
4123 }
4124}
4125
4126static int hw_add_addr(struct ksz_hw *hw, u8 *mac_addr)
4127{
4128 int i;
4129 int j = ADDITIONAL_ENTRIES;
4130
4131 if (ether_addr_equal(hw->override_addr, mac_addr))
4132 return 0;
4133 for (i = 0; i < hw->addr_list_size; i++) {
4134 if (ether_addr_equal(hw->address[i], mac_addr))
4135 return 0;
4136 if (ADDITIONAL_ENTRIES == j && empty_addr(hw->address[i]))
4137 j = i;
4138 }
4139 if (j < ADDITIONAL_ENTRIES) {
4140 memcpy(hw->address[j], mac_addr, ETH_ALEN);
4141 hw_ena_add_addr(hw, j, hw->address[j]);
4142 return 0;
4143 }
4144 return -1;
4145}
4146
4147static int hw_del_addr(struct ksz_hw *hw, u8 *mac_addr)
4148{
4149 int i;
4150
4151 for (i = 0; i < hw->addr_list_size; i++) {
4152 if (ether_addr_equal(hw->address[i], mac_addr)) {
4153 memset(hw->address[i], 0, ETH_ALEN);
4154 writel(0, hw->io + ADD_ADDR_INCR * i +
4155 KS_ADD_ADDR_0_HI);
4156 return 0;
4157 }
4158 }
4159 return -1;
4160}
4161
4162/**
4163 * hw_clr_multicast - clear multicast addresses
4164 * @hw: The hardware instance.
4165 *
4166 * This routine removes all multicast addresses set in the hardware.
4167 */
4168static void hw_clr_multicast(struct ksz_hw *hw)
4169{
4170 int i;
4171
4172 for (i = 0; i < HW_MULTICAST_SIZE; i++) {
4173 hw->multi_bits[i] = 0;
4174
4175 writeb(0, hw->io + KS884X_MULTICAST_0_OFFSET + i);
4176 }
4177}
4178
4179/**
4180 * hw_set_grp_addr - set multicast addresses
4181 * @hw: The hardware instance.
4182 *
4183 * This routine programs multicast addresses for the hardware to accept those
4184 * addresses.
4185 */
4186static void hw_set_grp_addr(struct ksz_hw *hw)
4187{
4188 int i;
4189 int index;
4190 int position;
4191 int value;
4192
4193 memset(hw->multi_bits, 0, sizeof(u8) * HW_MULTICAST_SIZE);
4194
4195 for (i = 0; i < hw->multi_list_size; i++) {
4196 position = (ether_crc(6, hw->multi_list[i]) >> 26) & 0x3f;
4197 index = position >> 3;
4198 value = 1 << (position & 7);
4199 hw->multi_bits[index] |= (u8) value;
4200 }
4201
4202 for (i = 0; i < HW_MULTICAST_SIZE; i++)
4203 writeb(hw->multi_bits[i], hw->io + KS884X_MULTICAST_0_OFFSET +
4204 i);
4205}
4206
4207/**
4208 * hw_set_multicast - enable or disable all multicast receiving
4209 * @hw: The hardware instance.
4210 * @multicast: To turn on or off the all multicast feature.
4211 *
4212 * This routine enables/disables the hardware to accept all multicast packets.
4213 */
4214static void hw_set_multicast(struct ksz_hw *hw, u8 multicast)
4215{
4216 /* Stop receiving for reconfiguration. */
4217 hw_stop_rx(hw);
4218
4219 if (multicast)
4220 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4221 else
4222 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4223
4224 if (hw->enabled)
4225 hw_start_rx(hw);
4226}
4227
4228/**
4229 * hw_set_promiscuous - enable or disable promiscuous receiving
4230 * @hw: The hardware instance.
4231 * @prom: To turn on or off the promiscuous feature.
4232 *
4233 * This routine enables/disables the hardware to accept all packets.
4234 */
4235static void hw_set_promiscuous(struct ksz_hw *hw, u8 prom)
4236{
4237 /* Stop receiving for reconfiguration. */
4238 hw_stop_rx(hw);
4239
4240 if (prom)
4241 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4242 else
4243 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
4244
4245 if (hw->enabled)
4246 hw_start_rx(hw);
4247}
4248
4249/**
4250 * sw_enable - enable the switch
4251 * @hw: The hardware instance.
4252 * @enable: The flag to enable or disable the switch
4253 *
4254 * This routine is used to enable/disable the switch in KSZ8842.
4255 */
4256static void sw_enable(struct ksz_hw *hw, int enable)
4257{
4258 int port;
4259
4260 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4261 if (hw->dev_count > 1) {
4262 /* Set port-base vlan membership with host port. */
4263 sw_cfg_port_base_vlan(hw, port,
4264 HOST_MASK | (1 << port));
4265 port_set_stp_state(hw, port, STP_STATE_DISABLED);
4266 } else {
4267 sw_cfg_port_base_vlan(hw, port, PORT_MASK);
4268 port_set_stp_state(hw, port, STP_STATE_FORWARDING);
4269 }
4270 }
4271 if (hw->dev_count > 1)
4272 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
4273 else
4274 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_FORWARDING);
4275
4276 if (enable)
4277 enable = KS8842_START;
4278 writew(enable, hw->io + KS884X_CHIP_ID_OFFSET);
4279}
4280
4281/**
4282 * sw_setup - setup the switch
4283 * @hw: The hardware instance.
4284 *
4285 * This routine setup the hardware switch engine for default operation.
4286 */
4287static void sw_setup(struct ksz_hw *hw)
4288{
4289 int port;
4290
4291 sw_set_global_ctrl(hw);
4292
4293 /* Enable switch broadcast storm protection at 10% percent rate. */
4294 sw_init_broad_storm(hw);
4295 hw_cfg_broad_storm(hw, BROADCAST_STORM_PROTECTION_RATE);
4296 for (port = 0; port < SWITCH_PORT_NUM; port++)
4297 sw_ena_broad_storm(hw, port);
4298
4299 sw_init_prio(hw);
4300
4301 sw_init_mirror(hw);
4302
4303 sw_init_prio_rate(hw);
4304
4305 sw_init_vlan(hw);
4306
4307 if (hw->features & STP_SUPPORT)
4308 sw_init_stp(hw);
4309 if (!sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
4310 SWITCH_TX_FLOW_CTRL | SWITCH_RX_FLOW_CTRL))
4311 hw->overrides |= PAUSE_FLOW_CTRL;
4312 sw_enable(hw, 1);
4313}
4314
4315/**
4316 * ksz_start_timer - start kernel timer
4317 * @info: Kernel timer information.
4318 * @time: The time tick.
4319 *
4320 * This routine starts the kernel timer after the specified time tick.
4321 */
4322static void ksz_start_timer(struct ksz_timer_info *info, int time)
4323{
4324 info->cnt = 0;
4325 info->timer.expires = jiffies + time;
4326 add_timer(&info->timer);
4327
4328 /* infinity */
4329 info->max = -1;
4330}
4331
4332/**
4333 * ksz_stop_timer - stop kernel timer
4334 * @info: Kernel timer information.
4335 *
4336 * This routine stops the kernel timer.
4337 */
4338static void ksz_stop_timer(struct ksz_timer_info *info)
4339{
4340 if (info->max) {
4341 info->max = 0;
4342 del_timer_sync(&info->timer);
4343 }
4344}
4345
4346static void ksz_init_timer(struct ksz_timer_info *info, int period,
4347 void (*function)(unsigned long), void *data)
4348{
4349 info->max = 0;
4350 info->period = period;
4351 init_timer(&info->timer);
4352 info->timer.function = function;
4353 info->timer.data = (unsigned long) data;
4354}
4355
4356static void ksz_update_timer(struct ksz_timer_info *info)
4357{
4358 ++info->cnt;
4359 if (info->max > 0) {
4360 if (info->cnt < info->max) {
4361 info->timer.expires = jiffies + info->period;
4362 add_timer(&info->timer);
4363 } else
4364 info->max = 0;
4365 } else if (info->max < 0) {
4366 info->timer.expires = jiffies + info->period;
4367 add_timer(&info->timer);
4368 }
4369}
4370
4371/**
4372 * ksz_alloc_soft_desc - allocate software descriptors
4373 * @desc_info: Descriptor information structure.
4374 * @transmit: Indication that descriptors are for transmit.
4375 *
4376 * This local function allocates software descriptors for manipulation in
4377 * memory.
4378 *
4379 * Return 0 if successful.
4380 */
4381static int ksz_alloc_soft_desc(struct ksz_desc_info *desc_info, int transmit)
4382{
4383 desc_info->ring = kzalloc(sizeof(struct ksz_desc) * desc_info->alloc,
4384 GFP_KERNEL);
4385 if (!desc_info->ring)
4386 return 1;
4387 hw_init_desc(desc_info, transmit);
4388 return 0;
4389}
4390
4391/**
4392 * ksz_alloc_desc - allocate hardware descriptors
4393 * @adapter: Adapter information structure.
4394 *
4395 * This local function allocates hardware descriptors for receiving and
4396 * transmitting.
4397 *
4398 * Return 0 if successful.
4399 */
4400static int ksz_alloc_desc(struct dev_info *adapter)
4401{
4402 struct ksz_hw *hw = &adapter->hw;
4403 int offset;
4404
4405 /* Allocate memory for RX & TX descriptors. */
4406 adapter->desc_pool.alloc_size =
4407 hw->rx_desc_info.size * hw->rx_desc_info.alloc +
4408 hw->tx_desc_info.size * hw->tx_desc_info.alloc +
4409 DESC_ALIGNMENT;
4410
4411 adapter->desc_pool.alloc_virt =
4412 pci_alloc_consistent(
4413 adapter->pdev, adapter->desc_pool.alloc_size,
4414 &adapter->desc_pool.dma_addr);
4415 if (adapter->desc_pool.alloc_virt == NULL) {
4416 adapter->desc_pool.alloc_size = 0;
4417 return 1;
4418 }
4419 memset(adapter->desc_pool.alloc_virt, 0, adapter->desc_pool.alloc_size);
4420
4421 /* Align to the next cache line boundary. */
4422 offset = (((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT) ?
4423 (DESC_ALIGNMENT -
4424 ((ulong) adapter->desc_pool.alloc_virt % DESC_ALIGNMENT)) : 0);
4425 adapter->desc_pool.virt = adapter->desc_pool.alloc_virt + offset;
4426 adapter->desc_pool.phys = adapter->desc_pool.dma_addr + offset;
4427
4428 /* Allocate receive/transmit descriptors. */
4429 hw->rx_desc_info.ring_virt = (struct ksz_hw_desc *)
4430 adapter->desc_pool.virt;
4431 hw->rx_desc_info.ring_phys = adapter->desc_pool.phys;
4432 offset = hw->rx_desc_info.alloc * hw->rx_desc_info.size;
4433 hw->tx_desc_info.ring_virt = (struct ksz_hw_desc *)
4434 (adapter->desc_pool.virt + offset);
4435 hw->tx_desc_info.ring_phys = adapter->desc_pool.phys + offset;
4436
4437 if (ksz_alloc_soft_desc(&hw->rx_desc_info, 0))
4438 return 1;
4439 if (ksz_alloc_soft_desc(&hw->tx_desc_info, 1))
4440 return 1;
4441
4442 return 0;
4443}
4444
4445/**
4446 * free_dma_buf - release DMA buffer resources
4447 * @adapter: Adapter information structure.
4448 *
4449 * This routine is just a helper function to release the DMA buffer resources.
4450 */
4451static void free_dma_buf(struct dev_info *adapter, struct ksz_dma_buf *dma_buf,
4452 int direction)
4453{
4454 pci_unmap_single(adapter->pdev, dma_buf->dma, dma_buf->len, direction);
4455 dev_kfree_skb(dma_buf->skb);
4456 dma_buf->skb = NULL;
4457 dma_buf->dma = 0;
4458}
4459
4460/**
4461 * ksz_init_rx_buffers - initialize receive descriptors
4462 * @adapter: Adapter information structure.
4463 *
4464 * This routine initializes DMA buffers for receiving.
4465 */
4466static void ksz_init_rx_buffers(struct dev_info *adapter)
4467{
4468 int i;
4469 struct ksz_desc *desc;
4470 struct ksz_dma_buf *dma_buf;
4471 struct ksz_hw *hw = &adapter->hw;
4472 struct ksz_desc_info *info = &hw->rx_desc_info;
4473
4474 for (i = 0; i < hw->rx_desc_info.alloc; i++) {
4475 get_rx_pkt(info, &desc);
4476
4477 dma_buf = DMA_BUFFER(desc);
4478 if (dma_buf->skb && dma_buf->len != adapter->mtu)
4479 free_dma_buf(adapter, dma_buf, PCI_DMA_FROMDEVICE);
4480 dma_buf->len = adapter->mtu;
4481 if (!dma_buf->skb)
4482 dma_buf->skb = alloc_skb(dma_buf->len, GFP_ATOMIC);
4483 if (dma_buf->skb && !dma_buf->dma)
4484 dma_buf->dma = pci_map_single(
4485 adapter->pdev,
4486 skb_tail_pointer(dma_buf->skb),
4487 dma_buf->len,
4488 PCI_DMA_FROMDEVICE);
4489
4490 /* Set descriptor. */
4491 set_rx_buf(desc, dma_buf->dma);
4492 set_rx_len(desc, dma_buf->len);
4493 release_desc(desc);
4494 }
4495}
4496
4497/**
4498 * ksz_alloc_mem - allocate memory for hardware descriptors
4499 * @adapter: Adapter information structure.
4500 *
4501 * This function allocates memory for use by hardware descriptors for receiving
4502 * and transmitting.
4503 *
4504 * Return 0 if successful.
4505 */
4506static int ksz_alloc_mem(struct dev_info *adapter)
4507{
4508 struct ksz_hw *hw = &adapter->hw;
4509
4510 /* Determine the number of receive and transmit descriptors. */
4511 hw->rx_desc_info.alloc = NUM_OF_RX_DESC;
4512 hw->tx_desc_info.alloc = NUM_OF_TX_DESC;
4513
4514 /* Determine how many descriptors to skip transmit interrupt. */
4515 hw->tx_int_cnt = 0;
4516 hw->tx_int_mask = NUM_OF_TX_DESC / 4;
4517 if (hw->tx_int_mask > 8)
4518 hw->tx_int_mask = 8;
4519 while (hw->tx_int_mask) {
4520 hw->tx_int_cnt++;
4521 hw->tx_int_mask >>= 1;
4522 }
4523 if (hw->tx_int_cnt) {
4524 hw->tx_int_mask = (1 << (hw->tx_int_cnt - 1)) - 1;
4525 hw->tx_int_cnt = 0;
4526 }
4527
4528 /* Determine the descriptor size. */
4529 hw->rx_desc_info.size =
4530 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4531 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4532 hw->tx_desc_info.size =
4533 (((sizeof(struct ksz_hw_desc) + DESC_ALIGNMENT - 1) /
4534 DESC_ALIGNMENT) * DESC_ALIGNMENT);
4535 if (hw->rx_desc_info.size != sizeof(struct ksz_hw_desc))
4536 pr_alert("Hardware descriptor size not right!\n");
4537 ksz_check_desc_num(&hw->rx_desc_info);
4538 ksz_check_desc_num(&hw->tx_desc_info);
4539
4540 /* Allocate descriptors. */
4541 if (ksz_alloc_desc(adapter))
4542 return 1;
4543
4544 return 0;
4545}
4546
4547/**
4548 * ksz_free_desc - free software and hardware descriptors
4549 * @adapter: Adapter information structure.
4550 *
4551 * This local routine frees the software and hardware descriptors allocated by
4552 * ksz_alloc_desc().
4553 */
4554static void ksz_free_desc(struct dev_info *adapter)
4555{
4556 struct ksz_hw *hw = &adapter->hw;
4557
4558 /* Reset descriptor. */
4559 hw->rx_desc_info.ring_virt = NULL;
4560 hw->tx_desc_info.ring_virt = NULL;
4561 hw->rx_desc_info.ring_phys = 0;
4562 hw->tx_desc_info.ring_phys = 0;
4563
4564 /* Free memory. */
4565 if (adapter->desc_pool.alloc_virt)
4566 pci_free_consistent(
4567 adapter->pdev,
4568 adapter->desc_pool.alloc_size,
4569 adapter->desc_pool.alloc_virt,
4570 adapter->desc_pool.dma_addr);
4571
4572 /* Reset resource pool. */
4573 adapter->desc_pool.alloc_size = 0;
4574 adapter->desc_pool.alloc_virt = NULL;
4575
4576 kfree(hw->rx_desc_info.ring);
4577 hw->rx_desc_info.ring = NULL;
4578 kfree(hw->tx_desc_info.ring);
4579 hw->tx_desc_info.ring = NULL;
4580}
4581
4582/**
4583 * ksz_free_buffers - free buffers used in the descriptors
4584 * @adapter: Adapter information structure.
4585 * @desc_info: Descriptor information structure.
4586 *
4587 * This local routine frees buffers used in the DMA buffers.
4588 */
4589static void ksz_free_buffers(struct dev_info *adapter,
4590 struct ksz_desc_info *desc_info, int direction)
4591{
4592 int i;
4593 struct ksz_dma_buf *dma_buf;
4594 struct ksz_desc *desc = desc_info->ring;
4595
4596 for (i = 0; i < desc_info->alloc; i++) {
4597 dma_buf = DMA_BUFFER(desc);
4598 if (dma_buf->skb)
4599 free_dma_buf(adapter, dma_buf, direction);
4600 desc++;
4601 }
4602}
4603
4604/**
4605 * ksz_free_mem - free all resources used by descriptors
4606 * @adapter: Adapter information structure.
4607 *
4608 * This local routine frees all the resources allocated by ksz_alloc_mem().
4609 */
4610static void ksz_free_mem(struct dev_info *adapter)
4611{
4612 /* Free transmit buffers. */
4613 ksz_free_buffers(adapter, &adapter->hw.tx_desc_info,
4614 PCI_DMA_TODEVICE);
4615
4616 /* Free receive buffers. */
4617 ksz_free_buffers(adapter, &adapter->hw.rx_desc_info,
4618 PCI_DMA_FROMDEVICE);
4619
4620 /* Free descriptors. */
4621 ksz_free_desc(adapter);
4622}
4623
4624static void get_mib_counters(struct ksz_hw *hw, int first, int cnt,
4625 u64 *counter)
4626{
4627 int i;
4628 int mib;
4629 int port;
4630 struct ksz_port_mib *port_mib;
4631
4632 memset(counter, 0, sizeof(u64) * TOTAL_PORT_COUNTER_NUM);
4633 for (i = 0, port = first; i < cnt; i++, port++) {
4634 port_mib = &hw->port_mib[port];
4635 for (mib = port_mib->mib_start; mib < hw->mib_cnt; mib++)
4636 counter[mib] += port_mib->counter[mib];
4637 }
4638}
4639
4640/**
4641 * send_packet - send packet
4642 * @skb: Socket buffer.
4643 * @dev: Network device.
4644 *
4645 * This routine is used to send a packet out to the network.
4646 */
4647static void send_packet(struct sk_buff *skb, struct net_device *dev)
4648{
4649 struct ksz_desc *desc;
4650 struct ksz_desc *first;
4651 struct dev_priv *priv = netdev_priv(dev);
4652 struct dev_info *hw_priv = priv->adapter;
4653 struct ksz_hw *hw = &hw_priv->hw;
4654 struct ksz_desc_info *info = &hw->tx_desc_info;
4655 struct ksz_dma_buf *dma_buf;
4656 int len;
4657 int last_frag = skb_shinfo(skb)->nr_frags;
4658
4659 /*
4660 * KSZ8842 with multiple device interfaces needs to be told which port
4661 * to send.
4662 */
4663 if (hw->dev_count > 1)
4664 hw->dst_ports = 1 << priv->port.first_port;
4665
4666 /* Hardware will pad the length to 60. */
4667 len = skb->len;
4668
4669 /* Remember the very first descriptor. */
4670 first = info->cur;
4671 desc = first;
4672
4673 dma_buf = DMA_BUFFER(desc);
4674 if (last_frag) {
4675 int frag;
4676 skb_frag_t *this_frag;
4677
4678 dma_buf->len = skb_headlen(skb);
4679
4680 dma_buf->dma = pci_map_single(
4681 hw_priv->pdev, skb->data, dma_buf->len,
4682 PCI_DMA_TODEVICE);
4683 set_tx_buf(desc, dma_buf->dma);
4684 set_tx_len(desc, dma_buf->len);
4685
4686 frag = 0;
4687 do {
4688 this_frag = &skb_shinfo(skb)->frags[frag];
4689
4690 /* Get a new descriptor. */
4691 get_tx_pkt(info, &desc);
4692
4693 /* Keep track of descriptors used so far. */
4694 ++hw->tx_int_cnt;
4695
4696 dma_buf = DMA_BUFFER(desc);
4697 dma_buf->len = skb_frag_size(this_frag);
4698
4699 dma_buf->dma = pci_map_single(
4700 hw_priv->pdev,
4701 skb_frag_address(this_frag),
4702 dma_buf->len,
4703 PCI_DMA_TODEVICE);
4704 set_tx_buf(desc, dma_buf->dma);
4705 set_tx_len(desc, dma_buf->len);
4706
4707 frag++;
4708 if (frag == last_frag)
4709 break;
4710
4711 /* Do not release the last descriptor here. */
4712 release_desc(desc);
4713 } while (1);
4714
4715 /* current points to the last descriptor. */
4716 info->cur = desc;
4717
4718 /* Release the first descriptor. */
4719 release_desc(first);
4720 } else {
4721 dma_buf->len = len;
4722
4723 dma_buf->dma = pci_map_single(
4724 hw_priv->pdev, skb->data, dma_buf->len,
4725 PCI_DMA_TODEVICE);
4726 set_tx_buf(desc, dma_buf->dma);
4727 set_tx_len(desc, dma_buf->len);
4728 }
4729
4730 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4731 (desc)->sw.buf.tx.csum_gen_tcp = 1;
4732 (desc)->sw.buf.tx.csum_gen_udp = 1;
4733 }
4734
4735 /*
4736 * The last descriptor holds the packet so that it can be returned to
4737 * network subsystem after all descriptors are transmitted.
4738 */
4739 dma_buf->skb = skb;
4740
4741 hw_send_pkt(hw);
4742
4743 /* Update transmit statistics. */
4744 dev->stats.tx_packets++;
4745 dev->stats.tx_bytes += len;
4746}
4747
4748/**
4749 * transmit_cleanup - clean up transmit descriptors
4750 * @dev: Network device.
4751 *
4752 * This routine is called to clean up the transmitted buffers.
4753 */
4754static void transmit_cleanup(struct dev_info *hw_priv, int normal)
4755{
4756 int last;
4757 union desc_stat status;
4758 struct ksz_hw *hw = &hw_priv->hw;
4759 struct ksz_desc_info *info = &hw->tx_desc_info;
4760 struct ksz_desc *desc;
4761 struct ksz_dma_buf *dma_buf;
4762 struct net_device *dev = NULL;
4763
4764 spin_lock_irq(&hw_priv->hwlock);
4765 last = info->last;
4766
4767 while (info->avail < info->alloc) {
4768 /* Get next descriptor which is not hardware owned. */
4769 desc = &info->ring[last];
4770 status.data = le32_to_cpu(desc->phw->ctrl.data);
4771 if (status.tx.hw_owned) {
4772 if (normal)
4773 break;
4774 else
4775 reset_desc(desc, status);
4776 }
4777
4778 dma_buf = DMA_BUFFER(desc);
4779 pci_unmap_single(
4780 hw_priv->pdev, dma_buf->dma, dma_buf->len,
4781 PCI_DMA_TODEVICE);
4782
4783 /* This descriptor contains the last buffer in the packet. */
4784 if (dma_buf->skb) {
4785 dev = dma_buf->skb->dev;
4786
4787 /* Release the packet back to network subsystem. */
4788 dev_kfree_skb_irq(dma_buf->skb);
4789 dma_buf->skb = NULL;
4790 }
4791
4792 /* Free the transmitted descriptor. */
4793 last++;
4794 last &= info->mask;
4795 info->avail++;
4796 }
4797 info->last = last;
4798 spin_unlock_irq(&hw_priv->hwlock);
4799
4800 /* Notify the network subsystem that the packet has been sent. */
4801 if (dev)
4802 dev->trans_start = jiffies;
4803}
4804
4805/**
4806 * transmit_done - transmit done processing
4807 * @dev: Network device.
4808 *
4809 * This routine is called when the transmit interrupt is triggered, indicating
4810 * either a packet is sent successfully or there are transmit errors.
4811 */
4812static void tx_done(struct dev_info *hw_priv)
4813{
4814 struct ksz_hw *hw = &hw_priv->hw;
4815 int port;
4816
4817 transmit_cleanup(hw_priv, 1);
4818
4819 for (port = 0; port < hw->dev_count; port++) {
4820 struct net_device *dev = hw->port_info[port].pdev;
4821
4822 if (netif_running(dev) && netif_queue_stopped(dev))
4823 netif_wake_queue(dev);
4824 }
4825}
4826
4827static inline void copy_old_skb(struct sk_buff *old, struct sk_buff *skb)
4828{
4829 skb->dev = old->dev;
4830 skb->protocol = old->protocol;
4831 skb->ip_summed = old->ip_summed;
4832 skb->csum = old->csum;
4833 skb_set_network_header(skb, ETH_HLEN);
4834
4835 dev_consume_skb_any(old);
4836}
4837
4838/**
4839 * netdev_tx - send out packet
4840 * @skb: Socket buffer.
4841 * @dev: Network device.
4842 *
4843 * This function is used by the upper network layer to send out a packet.
4844 *
4845 * Return 0 if successful; otherwise an error code indicating failure.
4846 */
4847static netdev_tx_t netdev_tx(struct sk_buff *skb, struct net_device *dev)
4848{
4849 struct dev_priv *priv = netdev_priv(dev);
4850 struct dev_info *hw_priv = priv->adapter;
4851 struct ksz_hw *hw = &hw_priv->hw;
4852 int left;
4853 int num = 1;
4854 int rc = 0;
4855
4856 if (hw->features & SMALL_PACKET_TX_BUG) {
4857 struct sk_buff *org_skb = skb;
4858
4859 if (skb->len <= 48) {
4860 if (skb_end_pointer(skb) - skb->data >= 50) {
4861 memset(&skb->data[skb->len], 0, 50 - skb->len);
4862 skb->len = 50;
4863 } else {
4864 skb = netdev_alloc_skb(dev, 50);
4865 if (!skb)
4866 return NETDEV_TX_BUSY;
4867 memcpy(skb->data, org_skb->data, org_skb->len);
4868 memset(&skb->data[org_skb->len], 0,
4869 50 - org_skb->len);
4870 skb->len = 50;
4871 copy_old_skb(org_skb, skb);
4872 }
4873 }
4874 }
4875
4876 spin_lock_irq(&hw_priv->hwlock);
4877
4878 num = skb_shinfo(skb)->nr_frags + 1;
4879 left = hw_alloc_pkt(hw, skb->len, num);
4880 if (left) {
4881 if (left < num ||
4882 (CHECKSUM_PARTIAL == skb->ip_summed &&
4883 skb->protocol == htons(ETH_P_IPV6))) {
4884 struct sk_buff *org_skb = skb;
4885
4886 skb = netdev_alloc_skb(dev, org_skb->len);
4887 if (!skb) {
4888 rc = NETDEV_TX_BUSY;
4889 goto unlock;
4890 }
4891 skb_copy_and_csum_dev(org_skb, skb->data);
4892 org_skb->ip_summed = CHECKSUM_NONE;
4893 skb->len = org_skb->len;
4894 copy_old_skb(org_skb, skb);
4895 }
4896 send_packet(skb, dev);
4897 if (left <= num)
4898 netif_stop_queue(dev);
4899 } else {
4900 /* Stop the transmit queue until packet is allocated. */
4901 netif_stop_queue(dev);
4902 rc = NETDEV_TX_BUSY;
4903 }
4904unlock:
4905 spin_unlock_irq(&hw_priv->hwlock);
4906
4907 return rc;
4908}
4909
4910/**
4911 * netdev_tx_timeout - transmit timeout processing
4912 * @dev: Network device.
4913 *
4914 * This routine is called when the transmit timer expires. That indicates the
4915 * hardware is not running correctly because transmit interrupts are not
4916 * triggered to free up resources so that the transmit routine can continue
4917 * sending out packets. The hardware is reset to correct the problem.
4918 */
4919static void netdev_tx_timeout(struct net_device *dev)
4920{
4921 static unsigned long last_reset;
4922
4923 struct dev_priv *priv = netdev_priv(dev);
4924 struct dev_info *hw_priv = priv->adapter;
4925 struct ksz_hw *hw = &hw_priv->hw;
4926 int port;
4927
4928 if (hw->dev_count > 1) {
4929 /*
4930 * Only reset the hardware if time between calls is long
4931 * enough.
4932 */
4933 if (jiffies - last_reset <= dev->watchdog_timeo)
4934 hw_priv = NULL;
4935 }
4936
4937 last_reset = jiffies;
4938 if (hw_priv) {
4939 hw_dis_intr(hw);
4940 hw_disable(hw);
4941
4942 transmit_cleanup(hw_priv, 0);
4943 hw_reset_pkts(&hw->rx_desc_info);
4944 hw_reset_pkts(&hw->tx_desc_info);
4945 ksz_init_rx_buffers(hw_priv);
4946
4947 hw_reset(hw);
4948
4949 hw_set_desc_base(hw,
4950 hw->tx_desc_info.ring_phys,
4951 hw->rx_desc_info.ring_phys);
4952 hw_set_addr(hw);
4953 if (hw->all_multi)
4954 hw_set_multicast(hw, hw->all_multi);
4955 else if (hw->multi_list_size)
4956 hw_set_grp_addr(hw);
4957
4958 if (hw->dev_count > 1) {
4959 hw_set_add_addr(hw);
4960 for (port = 0; port < SWITCH_PORT_NUM; port++) {
4961 struct net_device *port_dev;
4962
4963 port_set_stp_state(hw, port,
4964 STP_STATE_DISABLED);
4965
4966 port_dev = hw->port_info[port].pdev;
4967 if (netif_running(port_dev))
4968 port_set_stp_state(hw, port,
4969 STP_STATE_SIMPLE);
4970 }
4971 }
4972
4973 hw_enable(hw);
4974 hw_ena_intr(hw);
4975 }
4976
4977 dev->trans_start = jiffies;
4978 netif_wake_queue(dev);
4979}
4980
4981static inline void csum_verified(struct sk_buff *skb)
4982{
4983 unsigned short protocol;
4984 struct iphdr *iph;
4985
4986 protocol = skb->protocol;
4987 skb_reset_network_header(skb);
4988 iph = (struct iphdr *) skb_network_header(skb);
4989 if (protocol == htons(ETH_P_8021Q)) {
4990 protocol = iph->tot_len;
4991 skb_set_network_header(skb, VLAN_HLEN);
4992 iph = (struct iphdr *) skb_network_header(skb);
4993 }
4994 if (protocol == htons(ETH_P_IP)) {
4995 if (iph->protocol == IPPROTO_TCP)
4996 skb->ip_summed = CHECKSUM_UNNECESSARY;
4997 }
4998}
4999
5000static inline int rx_proc(struct net_device *dev, struct ksz_hw* hw,
5001 struct ksz_desc *desc, union desc_stat status)
5002{
5003 int packet_len;
5004 struct dev_priv *priv = netdev_priv(dev);
5005 struct dev_info *hw_priv = priv->adapter;
5006 struct ksz_dma_buf *dma_buf;
5007 struct sk_buff *skb;
5008 int rx_status;
5009
5010 /* Received length includes 4-byte CRC. */
5011 packet_len = status.rx.frame_len - 4;
5012
5013 dma_buf = DMA_BUFFER(desc);
5014 pci_dma_sync_single_for_cpu(
5015 hw_priv->pdev, dma_buf->dma, packet_len + 4,
5016 PCI_DMA_FROMDEVICE);
5017
5018 do {
5019 /* skb->data != skb->head */
5020 skb = netdev_alloc_skb(dev, packet_len + 2);
5021 if (!skb) {
5022 dev->stats.rx_dropped++;
5023 return -ENOMEM;
5024 }
5025
5026 /*
5027 * Align socket buffer in 4-byte boundary for better
5028 * performance.
5029 */
5030 skb_reserve(skb, 2);
5031
5032 memcpy(skb_put(skb, packet_len),
5033 dma_buf->skb->data, packet_len);
5034 } while (0);
5035
5036 skb->protocol = eth_type_trans(skb, dev);
5037
5038 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5039 csum_verified(skb);
5040
5041 /* Update receive statistics. */
5042 dev->stats.rx_packets++;
5043 dev->stats.rx_bytes += packet_len;
5044
5045 /* Notify upper layer for received packet. */
5046 rx_status = netif_rx(skb);
5047
5048 return 0;
5049}
5050
5051static int dev_rcv_packets(struct dev_info *hw_priv)
5052{
5053 int next;
5054 union desc_stat status;
5055 struct ksz_hw *hw = &hw_priv->hw;
5056 struct net_device *dev = hw->port_info[0].pdev;
5057 struct ksz_desc_info *info = &hw->rx_desc_info;
5058 int left = info->alloc;
5059 struct ksz_desc *desc;
5060 int received = 0;
5061
5062 next = info->next;
5063 while (left--) {
5064 /* Get next descriptor which is not hardware owned. */
5065 desc = &info->ring[next];
5066 status.data = le32_to_cpu(desc->phw->ctrl.data);
5067 if (status.rx.hw_owned)
5068 break;
5069
5070 /* Status valid only when last descriptor bit is set. */
5071 if (status.rx.last_desc && status.rx.first_desc) {
5072 if (rx_proc(dev, hw, desc, status))
5073 goto release_packet;
5074 received++;
5075 }
5076
5077release_packet:
5078 release_desc(desc);
5079 next++;
5080 next &= info->mask;
5081 }
5082 info->next = next;
5083
5084 return received;
5085}
5086
5087static int port_rcv_packets(struct dev_info *hw_priv)
5088{
5089 int next;
5090 union desc_stat status;
5091 struct ksz_hw *hw = &hw_priv->hw;
5092 struct net_device *dev = hw->port_info[0].pdev;
5093 struct ksz_desc_info *info = &hw->rx_desc_info;
5094 int left = info->alloc;
5095 struct ksz_desc *desc;
5096 int received = 0;
5097
5098 next = info->next;
5099 while (left--) {
5100 /* Get next descriptor which is not hardware owned. */
5101 desc = &info->ring[next];
5102 status.data = le32_to_cpu(desc->phw->ctrl.data);
5103 if (status.rx.hw_owned)
5104 break;
5105
5106 if (hw->dev_count > 1) {
5107 /* Get received port number. */
5108 int p = HW_TO_DEV_PORT(status.rx.src_port);
5109
5110 dev = hw->port_info[p].pdev;
5111 if (!netif_running(dev))
5112 goto release_packet;
5113 }
5114
5115 /* Status valid only when last descriptor bit is set. */
5116 if (status.rx.last_desc && status.rx.first_desc) {
5117 if (rx_proc(dev, hw, desc, status))
5118 goto release_packet;
5119 received++;
5120 }
5121
5122release_packet:
5123 release_desc(desc);
5124 next++;
5125 next &= info->mask;
5126 }
5127 info->next = next;
5128
5129 return received;
5130}
5131
5132static int dev_rcv_special(struct dev_info *hw_priv)
5133{
5134 int next;
5135 union desc_stat status;
5136 struct ksz_hw *hw = &hw_priv->hw;
5137 struct net_device *dev = hw->port_info[0].pdev;
5138 struct ksz_desc_info *info = &hw->rx_desc_info;
5139 int left = info->alloc;
5140 struct ksz_desc *desc;
5141 int received = 0;
5142
5143 next = info->next;
5144 while (left--) {
5145 /* Get next descriptor which is not hardware owned. */
5146 desc = &info->ring[next];
5147 status.data = le32_to_cpu(desc->phw->ctrl.data);
5148 if (status.rx.hw_owned)
5149 break;
5150
5151 if (hw->dev_count > 1) {
5152 /* Get received port number. */
5153 int p = HW_TO_DEV_PORT(status.rx.src_port);
5154
5155 dev = hw->port_info[p].pdev;
5156 if (!netif_running(dev))
5157 goto release_packet;
5158 }
5159
5160 /* Status valid only when last descriptor bit is set. */
5161 if (status.rx.last_desc && status.rx.first_desc) {
5162 /*
5163 * Receive without error. With receive errors
5164 * disabled, packets with receive errors will be
5165 * dropped, so no need to check the error bit.
5166 */
5167 if (!status.rx.error || (status.data &
5168 KS_DESC_RX_ERROR_COND) ==
5169 KS_DESC_RX_ERROR_TOO_LONG) {
5170 if (rx_proc(dev, hw, desc, status))
5171 goto release_packet;
5172 received++;
5173 } else {
5174 struct dev_priv *priv = netdev_priv(dev);
5175
5176 /* Update receive error statistics. */
5177 priv->port.counter[OID_COUNTER_RCV_ERROR]++;
5178 }
5179 }
5180
5181release_packet:
5182 release_desc(desc);
5183 next++;
5184 next &= info->mask;
5185 }
5186 info->next = next;
5187
5188 return received;
5189}
5190
5191static void rx_proc_task(unsigned long data)
5192{
5193 struct dev_info *hw_priv = (struct dev_info *) data;
5194 struct ksz_hw *hw = &hw_priv->hw;
5195
5196 if (!hw->enabled)
5197 return;
5198 if (unlikely(!hw_priv->dev_rcv(hw_priv))) {
5199
5200 /* In case receive process is suspended because of overrun. */
5201 hw_resume_rx(hw);
5202
5203 /* tasklets are interruptible. */
5204 spin_lock_irq(&hw_priv->hwlock);
5205 hw_turn_on_intr(hw, KS884X_INT_RX_MASK);
5206 spin_unlock_irq(&hw_priv->hwlock);
5207 } else {
5208 hw_ack_intr(hw, KS884X_INT_RX);
5209 tasklet_schedule(&hw_priv->rx_tasklet);
5210 }
5211}
5212
5213static void tx_proc_task(unsigned long data)
5214{
5215 struct dev_info *hw_priv = (struct dev_info *) data;
5216 struct ksz_hw *hw = &hw_priv->hw;
5217
5218 hw_ack_intr(hw, KS884X_INT_TX_MASK);
5219
5220 tx_done(hw_priv);
5221
5222 /* tasklets are interruptible. */
5223 spin_lock_irq(&hw_priv->hwlock);
5224 hw_turn_on_intr(hw, KS884X_INT_TX);
5225 spin_unlock_irq(&hw_priv->hwlock);
5226}
5227
5228static inline void handle_rx_stop(struct ksz_hw *hw)
5229{
5230 /* Receive just has been stopped. */
5231 if (0 == hw->rx_stop)
5232 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5233 else if (hw->rx_stop > 1) {
5234 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5235 hw_start_rx(hw);
5236 } else {
5237 hw->intr_mask &= ~KS884X_INT_RX_STOPPED;
5238 hw->rx_stop = 0;
5239 }
5240 } else
5241 /* Receive just has been started. */
5242 hw->rx_stop++;
5243}
5244
5245/**
5246 * netdev_intr - interrupt handling
5247 * @irq: Interrupt number.
5248 * @dev_id: Network device.
5249 *
5250 * This function is called by upper network layer to signal interrupt.
5251 *
5252 * Return IRQ_HANDLED if interrupt is handled.
5253 */
5254static irqreturn_t netdev_intr(int irq, void *dev_id)
5255{
5256 uint int_enable = 0;
5257 struct net_device *dev = (struct net_device *) dev_id;
5258 struct dev_priv *priv = netdev_priv(dev);
5259 struct dev_info *hw_priv = priv->adapter;
5260 struct ksz_hw *hw = &hw_priv->hw;
5261
5262 spin_lock(&hw_priv->hwlock);
5263
5264 hw_read_intr(hw, &int_enable);
5265
5266 /* Not our interrupt! */
5267 if (!int_enable) {
5268 spin_unlock(&hw_priv->hwlock);
5269 return IRQ_NONE;
5270 }
5271
5272 do {
5273 hw_ack_intr(hw, int_enable);
5274 int_enable &= hw->intr_mask;
5275
5276 if (unlikely(int_enable & KS884X_INT_TX_MASK)) {
5277 hw_dis_intr_bit(hw, KS884X_INT_TX_MASK);
5278 tasklet_schedule(&hw_priv->tx_tasklet);
5279 }
5280
5281 if (likely(int_enable & KS884X_INT_RX)) {
5282 hw_dis_intr_bit(hw, KS884X_INT_RX);
5283 tasklet_schedule(&hw_priv->rx_tasklet);
5284 }
5285
5286 if (unlikely(int_enable & KS884X_INT_RX_OVERRUN)) {
5287 dev->stats.rx_fifo_errors++;
5288 hw_resume_rx(hw);
5289 }
5290
5291 if (unlikely(int_enable & KS884X_INT_PHY)) {
5292 struct ksz_port *port = &priv->port;
5293
5294 hw->features |= LINK_INT_WORKING;
5295 port_get_link_speed(port);
5296 }
5297
5298 if (unlikely(int_enable & KS884X_INT_RX_STOPPED)) {
5299 handle_rx_stop(hw);
5300 break;
5301 }
5302
5303 if (unlikely(int_enable & KS884X_INT_TX_STOPPED)) {
5304 u32 data;
5305
5306 hw->intr_mask &= ~KS884X_INT_TX_STOPPED;
5307 pr_info("Tx stopped\n");
5308 data = readl(hw->io + KS_DMA_TX_CTRL);
5309 if (!(data & DMA_TX_ENABLE))
5310 pr_info("Tx disabled\n");
5311 break;
5312 }
5313 } while (0);
5314
5315 hw_ena_intr(hw);
5316
5317 spin_unlock(&hw_priv->hwlock);
5318
5319 return IRQ_HANDLED;
5320}
5321
5322/*
5323 * Linux network device functions
5324 */
5325
5326static unsigned long next_jiffies;
5327
5328#ifdef CONFIG_NET_POLL_CONTROLLER
5329static void netdev_netpoll(struct net_device *dev)
5330{
5331 struct dev_priv *priv = netdev_priv(dev);
5332 struct dev_info *hw_priv = priv->adapter;
5333
5334 hw_dis_intr(&hw_priv->hw);
5335 netdev_intr(dev->irq, dev);
5336}
5337#endif
5338
5339static void bridge_change(struct ksz_hw *hw)
5340{
5341 int port;
5342 u8 member;
5343 struct ksz_switch *sw = hw->ksz_switch;
5344
5345 /* No ports in forwarding state. */
5346 if (!sw->member) {
5347 port_set_stp_state(hw, SWITCH_PORT_NUM, STP_STATE_SIMPLE);
5348 sw_block_addr(hw);
5349 }
5350 for (port = 0; port < SWITCH_PORT_NUM; port++) {
5351 if (STP_STATE_FORWARDING == sw->port_cfg[port].stp_state)
5352 member = HOST_MASK | sw->member;
5353 else
5354 member = HOST_MASK | (1 << port);
5355 if (member != sw->port_cfg[port].member)
5356 sw_cfg_port_base_vlan(hw, port, member);
5357 }
5358}
5359
5360/**
5361 * netdev_close - close network device
5362 * @dev: Network device.
5363 *
5364 * This function process the close operation of network device. This is caused
5365 * by the user command "ifconfig ethX down."
5366 *
5367 * Return 0 if successful; otherwise an error code indicating failure.
5368 */
5369static int netdev_close(struct net_device *dev)
5370{
5371 struct dev_priv *priv = netdev_priv(dev);
5372 struct dev_info *hw_priv = priv->adapter;
5373 struct ksz_port *port = &priv->port;
5374 struct ksz_hw *hw = &hw_priv->hw;
5375 int pi;
5376
5377 netif_stop_queue(dev);
5378
5379 ksz_stop_timer(&priv->monitor_timer_info);
5380
5381 /* Need to shut the port manually in multiple device interfaces mode. */
5382 if (hw->dev_count > 1) {
5383 port_set_stp_state(hw, port->first_port, STP_STATE_DISABLED);
5384
5385 /* Port is closed. Need to change bridge setting. */
5386 if (hw->features & STP_SUPPORT) {
5387 pi = 1 << port->first_port;
5388 if (hw->ksz_switch->member & pi) {
5389 hw->ksz_switch->member &= ~pi;
5390 bridge_change(hw);
5391 }
5392 }
5393 }
5394 if (port->first_port > 0)
5395 hw_del_addr(hw, dev->dev_addr);
5396 if (!hw_priv->wol_enable)
5397 port_set_power_saving(port, true);
5398
5399 if (priv->multicast)
5400 --hw->all_multi;
5401 if (priv->promiscuous)
5402 --hw->promiscuous;
5403
5404 hw_priv->opened--;
5405 if (!(hw_priv->opened)) {
5406 ksz_stop_timer(&hw_priv->mib_timer_info);
5407 flush_work(&hw_priv->mib_read);
5408
5409 hw_dis_intr(hw);
5410 hw_disable(hw);
5411 hw_clr_multicast(hw);
5412
5413 /* Delay for receive task to stop scheduling itself. */
5414 msleep(2000 / HZ);
5415
5416 tasklet_kill(&hw_priv->rx_tasklet);
5417 tasklet_kill(&hw_priv->tx_tasklet);
5418 free_irq(dev->irq, hw_priv->dev);
5419
5420 transmit_cleanup(hw_priv, 0);
5421 hw_reset_pkts(&hw->rx_desc_info);
5422 hw_reset_pkts(&hw->tx_desc_info);
5423
5424 /* Clean out static MAC table when the switch is shutdown. */
5425 if (hw->features & STP_SUPPORT)
5426 sw_clr_sta_mac_table(hw);
5427 }
5428
5429 return 0;
5430}
5431
5432static void hw_cfg_huge_frame(struct dev_info *hw_priv, struct ksz_hw *hw)
5433{
5434 if (hw->ksz_switch) {
5435 u32 data;
5436
5437 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5438 if (hw->features & RX_HUGE_FRAME)
5439 data |= SWITCH_HUGE_PACKET;
5440 else
5441 data &= ~SWITCH_HUGE_PACKET;
5442 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5443 }
5444 if (hw->features & RX_HUGE_FRAME) {
5445 hw->rx_cfg |= DMA_RX_ERROR;
5446 hw_priv->dev_rcv = dev_rcv_special;
5447 } else {
5448 hw->rx_cfg &= ~DMA_RX_ERROR;
5449 if (hw->dev_count > 1)
5450 hw_priv->dev_rcv = port_rcv_packets;
5451 else
5452 hw_priv->dev_rcv = dev_rcv_packets;
5453 }
5454}
5455
5456static int prepare_hardware(struct net_device *dev)
5457{
5458 struct dev_priv *priv = netdev_priv(dev);
5459 struct dev_info *hw_priv = priv->adapter;
5460 struct ksz_hw *hw = &hw_priv->hw;
5461 int rc = 0;
5462
5463 /* Remember the network device that requests interrupts. */
5464 hw_priv->dev = dev;
5465 rc = request_irq(dev->irq, netdev_intr, IRQF_SHARED, dev->name, dev);
5466 if (rc)
5467 return rc;
5468 tasklet_init(&hw_priv->rx_tasklet, rx_proc_task,
5469 (unsigned long) hw_priv);
5470 tasklet_init(&hw_priv->tx_tasklet, tx_proc_task,
5471 (unsigned long) hw_priv);
5472
5473 hw->promiscuous = 0;
5474 hw->all_multi = 0;
5475 hw->multi_list_size = 0;
5476
5477 hw_reset(hw);
5478
5479 hw_set_desc_base(hw,
5480 hw->tx_desc_info.ring_phys, hw->rx_desc_info.ring_phys);
5481 hw_set_addr(hw);
5482 hw_cfg_huge_frame(hw_priv, hw);
5483 ksz_init_rx_buffers(hw_priv);
5484 return 0;
5485}
5486
5487static void set_media_state(struct net_device *dev, int media_state)
5488{
5489 struct dev_priv *priv = netdev_priv(dev);
5490
5491 if (media_state == priv->media_state)
5492 netif_carrier_on(dev);
5493 else
5494 netif_carrier_off(dev);
5495 netif_info(priv, link, dev, "link %s\n",
5496 media_state == priv->media_state ? "on" : "off");
5497}
5498
5499/**
5500 * netdev_open - open network device
5501 * @dev: Network device.
5502 *
5503 * This function process the open operation of network device. This is caused
5504 * by the user command "ifconfig ethX up."
5505 *
5506 * Return 0 if successful; otherwise an error code indicating failure.
5507 */
5508static int netdev_open(struct net_device *dev)
5509{
5510 struct dev_priv *priv = netdev_priv(dev);
5511 struct dev_info *hw_priv = priv->adapter;
5512 struct ksz_hw *hw = &hw_priv->hw;
5513 struct ksz_port *port = &priv->port;
5514 int i;
5515 int p;
5516 int rc = 0;
5517
5518 priv->multicast = 0;
5519 priv->promiscuous = 0;
5520
5521 /* Reset device statistics. */
5522 memset(&dev->stats, 0, sizeof(struct net_device_stats));
5523 memset((void *) port->counter, 0,
5524 (sizeof(u64) * OID_COUNTER_LAST));
5525
5526 if (!(hw_priv->opened)) {
5527 rc = prepare_hardware(dev);
5528 if (rc)
5529 return rc;
5530 for (i = 0; i < hw->mib_port_cnt; i++) {
5531 if (next_jiffies < jiffies)
5532 next_jiffies = jiffies + HZ * 2;
5533 else
5534 next_jiffies += HZ * 1;
5535 hw_priv->counter[i].time = next_jiffies;
5536 hw->port_mib[i].state = media_disconnected;
5537 port_init_cnt(hw, i);
5538 }
5539 if (hw->ksz_switch)
5540 hw->port_mib[HOST_PORT].state = media_connected;
5541 else {
5542 hw_add_wol_bcast(hw);
5543 hw_cfg_wol_pme(hw, 0);
5544 hw_clr_wol_pme_status(&hw_priv->hw);
5545 }
5546 }
5547 port_set_power_saving(port, false);
5548
5549 for (i = 0, p = port->first_port; i < port->port_cnt; i++, p++) {
5550 /*
5551 * Initialize to invalid value so that link detection
5552 * is done.
5553 */
5554 hw->port_info[p].partner = 0xFF;
5555 hw->port_info[p].state = media_disconnected;
5556 }
5557
5558 /* Need to open the port in multiple device interfaces mode. */
5559 if (hw->dev_count > 1) {
5560 port_set_stp_state(hw, port->first_port, STP_STATE_SIMPLE);
5561 if (port->first_port > 0)
5562 hw_add_addr(hw, dev->dev_addr);
5563 }
5564
5565 port_get_link_speed(port);
5566 if (port->force_link)
5567 port_force_link_speed(port);
5568 else
5569 port_set_link_speed(port);
5570
5571 if (!(hw_priv->opened)) {
5572 hw_setup_intr(hw);
5573 hw_enable(hw);
5574 hw_ena_intr(hw);
5575
5576 if (hw->mib_port_cnt)
5577 ksz_start_timer(&hw_priv->mib_timer_info,
5578 hw_priv->mib_timer_info.period);
5579 }
5580
5581 hw_priv->opened++;
5582
5583 ksz_start_timer(&priv->monitor_timer_info,
5584 priv->monitor_timer_info.period);
5585
5586 priv->media_state = port->linked->state;
5587
5588 set_media_state(dev, media_connected);
5589 netif_start_queue(dev);
5590
5591 return 0;
5592}
5593
5594/* RX errors = rx_errors */
5595/* RX dropped = rx_dropped */
5596/* RX overruns = rx_fifo_errors */
5597/* RX frame = rx_crc_errors + rx_frame_errors + rx_length_errors */
5598/* TX errors = tx_errors */
5599/* TX dropped = tx_dropped */
5600/* TX overruns = tx_fifo_errors */
5601/* TX carrier = tx_aborted_errors + tx_carrier_errors + tx_window_errors */
5602/* collisions = collisions */
5603
5604/**
5605 * netdev_query_statistics - query network device statistics
5606 * @dev: Network device.
5607 *
5608 * This function returns the statistics of the network device. The device
5609 * needs not be opened.
5610 *
5611 * Return network device statistics.
5612 */
5613static struct net_device_stats *netdev_query_statistics(struct net_device *dev)
5614{
5615 struct dev_priv *priv = netdev_priv(dev);
5616 struct ksz_port *port = &priv->port;
5617 struct ksz_hw *hw = &priv->adapter->hw;
5618 struct ksz_port_mib *mib;
5619 int i;
5620 int p;
5621
5622 dev->stats.rx_errors = port->counter[OID_COUNTER_RCV_ERROR];
5623 dev->stats.tx_errors = port->counter[OID_COUNTER_XMIT_ERROR];
5624
5625 /* Reset to zero to add count later. */
5626 dev->stats.multicast = 0;
5627 dev->stats.collisions = 0;
5628 dev->stats.rx_length_errors = 0;
5629 dev->stats.rx_crc_errors = 0;
5630 dev->stats.rx_frame_errors = 0;
5631 dev->stats.tx_window_errors = 0;
5632
5633 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
5634 mib = &hw->port_mib[p];
5635
5636 dev->stats.multicast += (unsigned long)
5637 mib->counter[MIB_COUNTER_RX_MULTICAST];
5638
5639 dev->stats.collisions += (unsigned long)
5640 mib->counter[MIB_COUNTER_TX_TOTAL_COLLISION];
5641
5642 dev->stats.rx_length_errors += (unsigned long)(
5643 mib->counter[MIB_COUNTER_RX_UNDERSIZE] +
5644 mib->counter[MIB_COUNTER_RX_FRAGMENT] +
5645 mib->counter[MIB_COUNTER_RX_OVERSIZE] +
5646 mib->counter[MIB_COUNTER_RX_JABBER]);
5647 dev->stats.rx_crc_errors += (unsigned long)
5648 mib->counter[MIB_COUNTER_RX_CRC_ERR];
5649 dev->stats.rx_frame_errors += (unsigned long)(
5650 mib->counter[MIB_COUNTER_RX_ALIGNMENT_ERR] +
5651 mib->counter[MIB_COUNTER_RX_SYMBOL_ERR]);
5652
5653 dev->stats.tx_window_errors += (unsigned long)
5654 mib->counter[MIB_COUNTER_TX_LATE_COLLISION];
5655 }
5656
5657 return &dev->stats;
5658}
5659
5660/**
5661 * netdev_set_mac_address - set network device MAC address
5662 * @dev: Network device.
5663 * @addr: Buffer of MAC address.
5664 *
5665 * This function is used to set the MAC address of the network device.
5666 *
5667 * Return 0 to indicate success.
5668 */
5669static int netdev_set_mac_address(struct net_device *dev, void *addr)
5670{
5671 struct dev_priv *priv = netdev_priv(dev);
5672 struct dev_info *hw_priv = priv->adapter;
5673 struct ksz_hw *hw = &hw_priv->hw;
5674 struct sockaddr *mac = addr;
5675 uint interrupt;
5676
5677 if (priv->port.first_port > 0)
5678 hw_del_addr(hw, dev->dev_addr);
5679 else {
5680 hw->mac_override = 1;
5681 memcpy(hw->override_addr, mac->sa_data, ETH_ALEN);
5682 }
5683
5684 memcpy(dev->dev_addr, mac->sa_data, ETH_ALEN);
5685
5686 interrupt = hw_block_intr(hw);
5687
5688 if (priv->port.first_port > 0)
5689 hw_add_addr(hw, dev->dev_addr);
5690 else
5691 hw_set_addr(hw);
5692 hw_restore_intr(hw, interrupt);
5693
5694 return 0;
5695}
5696
5697static void dev_set_promiscuous(struct net_device *dev, struct dev_priv *priv,
5698 struct ksz_hw *hw, int promiscuous)
5699{
5700 if (promiscuous != priv->promiscuous) {
5701 u8 prev_state = hw->promiscuous;
5702
5703 if (promiscuous)
5704 ++hw->promiscuous;
5705 else
5706 --hw->promiscuous;
5707 priv->promiscuous = promiscuous;
5708
5709 /* Turn on/off promiscuous mode. */
5710 if (hw->promiscuous <= 1 && prev_state <= 1)
5711 hw_set_promiscuous(hw, hw->promiscuous);
5712
5713 /*
5714 * Port is not in promiscuous mode, meaning it is released
5715 * from the bridge.
5716 */
5717 if ((hw->features & STP_SUPPORT) && !promiscuous &&
5718 (dev->priv_flags & IFF_BRIDGE_PORT)) {
5719 struct ksz_switch *sw = hw->ksz_switch;
5720 int port = priv->port.first_port;
5721
5722 port_set_stp_state(hw, port, STP_STATE_DISABLED);
5723 port = 1 << port;
5724 if (sw->member & port) {
5725 sw->member &= ~port;
5726 bridge_change(hw);
5727 }
5728 }
5729 }
5730}
5731
5732static void dev_set_multicast(struct dev_priv *priv, struct ksz_hw *hw,
5733 int multicast)
5734{
5735 if (multicast != priv->multicast) {
5736 u8 all_multi = hw->all_multi;
5737
5738 if (multicast)
5739 ++hw->all_multi;
5740 else
5741 --hw->all_multi;
5742 priv->multicast = multicast;
5743
5744 /* Turn on/off all multicast mode. */
5745 if (hw->all_multi <= 1 && all_multi <= 1)
5746 hw_set_multicast(hw, hw->all_multi);
5747 }
5748}
5749
5750/**
5751 * netdev_set_rx_mode
5752 * @dev: Network device.
5753 *
5754 * This routine is used to set multicast addresses or put the network device
5755 * into promiscuous mode.
5756 */
5757static void netdev_set_rx_mode(struct net_device *dev)
5758{
5759 struct dev_priv *priv = netdev_priv(dev);
5760 struct dev_info *hw_priv = priv->adapter;
5761 struct ksz_hw *hw = &hw_priv->hw;
5762 struct netdev_hw_addr *ha;
5763 int multicast = (dev->flags & IFF_ALLMULTI);
5764
5765 dev_set_promiscuous(dev, priv, hw, (dev->flags & IFF_PROMISC));
5766
5767 if (hw_priv->hw.dev_count > 1)
5768 multicast |= (dev->flags & IFF_MULTICAST);
5769 dev_set_multicast(priv, hw, multicast);
5770
5771 /* Cannot use different hashes in multiple device interfaces mode. */
5772 if (hw_priv->hw.dev_count > 1)
5773 return;
5774
5775 if ((dev->flags & IFF_MULTICAST) && !netdev_mc_empty(dev)) {
5776 int i = 0;
5777
5778 /* List too big to support so turn on all multicast mode. */
5779 if (netdev_mc_count(dev) > MAX_MULTICAST_LIST) {
5780 if (MAX_MULTICAST_LIST != hw->multi_list_size) {
5781 hw->multi_list_size = MAX_MULTICAST_LIST;
5782 ++hw->all_multi;
5783 hw_set_multicast(hw, hw->all_multi);
5784 }
5785 return;
5786 }
5787
5788 netdev_for_each_mc_addr(ha, dev) {
5789 if (i >= MAX_MULTICAST_LIST)
5790 break;
5791 memcpy(hw->multi_list[i++], ha->addr, ETH_ALEN);
5792 }
5793 hw->multi_list_size = (u8) i;
5794 hw_set_grp_addr(hw);
5795 } else {
5796 if (MAX_MULTICAST_LIST == hw->multi_list_size) {
5797 --hw->all_multi;
5798 hw_set_multicast(hw, hw->all_multi);
5799 }
5800 hw->multi_list_size = 0;
5801 hw_clr_multicast(hw);
5802 }
5803}
5804
5805static int netdev_change_mtu(struct net_device *dev, int new_mtu)
5806{
5807 struct dev_priv *priv = netdev_priv(dev);
5808 struct dev_info *hw_priv = priv->adapter;
5809 struct ksz_hw *hw = &hw_priv->hw;
5810 int hw_mtu;
5811
5812 if (netif_running(dev))
5813 return -EBUSY;
5814
5815 /* Cannot use different MTU in multiple device interfaces mode. */
5816 if (hw->dev_count > 1)
5817 if (dev != hw_priv->dev)
5818 return 0;
5819 if (new_mtu < 60)
5820 return -EINVAL;
5821
5822 if (dev->mtu != new_mtu) {
5823 hw_mtu = new_mtu + ETHERNET_HEADER_SIZE + 4;
5824 if (hw_mtu > MAX_RX_BUF_SIZE)
5825 return -EINVAL;
5826 if (hw_mtu > REGULAR_RX_BUF_SIZE) {
5827 hw->features |= RX_HUGE_FRAME;
5828 hw_mtu = MAX_RX_BUF_SIZE;
5829 } else {
5830 hw->features &= ~RX_HUGE_FRAME;
5831 hw_mtu = REGULAR_RX_BUF_SIZE;
5832 }
5833 hw_mtu = (hw_mtu + 3) & ~3;
5834 hw_priv->mtu = hw_mtu;
5835 dev->mtu = new_mtu;
5836 }
5837 return 0;
5838}
5839
5840/**
5841 * netdev_ioctl - I/O control processing
5842 * @dev: Network device.
5843 * @ifr: Interface request structure.
5844 * @cmd: I/O control code.
5845 *
5846 * This function is used to process I/O control calls.
5847 *
5848 * Return 0 to indicate success.
5849 */
5850static int netdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5851{
5852 struct dev_priv *priv = netdev_priv(dev);
5853 struct dev_info *hw_priv = priv->adapter;
5854 struct ksz_hw *hw = &hw_priv->hw;
5855 struct ksz_port *port = &priv->port;
5856 int result = 0;
5857 struct mii_ioctl_data *data = if_mii(ifr);
5858
5859 if (down_interruptible(&priv->proc_sem))
5860 return -ERESTARTSYS;
5861
5862 switch (cmd) {
5863 /* Get address of MII PHY in use. */
5864 case SIOCGMIIPHY:
5865 data->phy_id = priv->id;
5866
5867 /* Fallthrough... */
5868
5869 /* Read MII PHY register. */
5870 case SIOCGMIIREG:
5871 if (data->phy_id != priv->id || data->reg_num >= 6)
5872 result = -EIO;
5873 else
5874 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5875 &data->val_out);
5876 break;
5877
5878 /* Write MII PHY register. */
5879 case SIOCSMIIREG:
5880 if (!capable(CAP_NET_ADMIN))
5881 result = -EPERM;
5882 else if (data->phy_id != priv->id || data->reg_num >= 6)
5883 result = -EIO;
5884 else
5885 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5886 data->val_in);
5887 break;
5888
5889 default:
5890 result = -EOPNOTSUPP;
5891 }
5892
5893 up(&priv->proc_sem);
5894
5895 return result;
5896}
5897
5898/*
5899 * MII support
5900 */
5901
5902/**
5903 * mdio_read - read PHY register
5904 * @dev: Network device.
5905 * @phy_id: The PHY id.
5906 * @reg_num: The register number.
5907 *
5908 * This function returns the PHY register value.
5909 *
5910 * Return the register value.
5911 */
5912static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
5913{
5914 struct dev_priv *priv = netdev_priv(dev);
5915 struct ksz_port *port = &priv->port;
5916 struct ksz_hw *hw = port->hw;
5917 u16 val_out;
5918
5919 hw_r_phy(hw, port->linked->port_id, reg_num << 1, &val_out);
5920 return val_out;
5921}
5922
5923/**
5924 * mdio_write - set PHY register
5925 * @dev: Network device.
5926 * @phy_id: The PHY id.
5927 * @reg_num: The register number.
5928 * @val: The register value.
5929 *
5930 * This procedure sets the PHY register value.
5931 */
5932static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
5933{
5934 struct dev_priv *priv = netdev_priv(dev);
5935 struct ksz_port *port = &priv->port;
5936 struct ksz_hw *hw = port->hw;
5937 int i;
5938 int pi;
5939
5940 for (i = 0, pi = port->first_port; i < port->port_cnt; i++, pi++)
5941 hw_w_phy(hw, pi, reg_num << 1, val);
5942}
5943
5944/*
5945 * ethtool support
5946 */
5947
5948#define EEPROM_SIZE 0x40
5949
5950static u16 eeprom_data[EEPROM_SIZE] = { 0 };
5951
5952#define ADVERTISED_ALL \
5953 (ADVERTISED_10baseT_Half | \
5954 ADVERTISED_10baseT_Full | \
5955 ADVERTISED_100baseT_Half | \
5956 ADVERTISED_100baseT_Full)
5957
5958/* These functions use the MII functions in mii.c. */
5959
5960/**
5961 * netdev_get_settings - get network device settings
5962 * @dev: Network device.
5963 * @cmd: Ethtool command.
5964 *
5965 * This function queries the PHY and returns its state in the ethtool command.
5966 *
5967 * Return 0 if successful; otherwise an error code.
5968 */
5969static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5970{
5971 struct dev_priv *priv = netdev_priv(dev);
5972 struct dev_info *hw_priv = priv->adapter;
5973
5974 mutex_lock(&hw_priv->lock);
5975 mii_ethtool_gset(&priv->mii_if, cmd);
5976 cmd->advertising |= SUPPORTED_TP;
5977 mutex_unlock(&hw_priv->lock);
5978
5979 /* Save advertised settings for workaround in next function. */
5980 priv->advertising = cmd->advertising;
5981 return 0;
5982}
5983
5984/**
5985 * netdev_set_settings - set network device settings
5986 * @dev: Network device.
5987 * @cmd: Ethtool command.
5988 *
5989 * This function sets the PHY according to the ethtool command.
5990 *
5991 * Return 0 if successful; otherwise an error code.
5992 */
5993static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
5994{
5995 struct dev_priv *priv = netdev_priv(dev);
5996 struct dev_info *hw_priv = priv->adapter;
5997 struct ksz_port *port = &priv->port;
5998 u32 speed = ethtool_cmd_speed(cmd);
5999 int rc;
6000
6001 /*
6002 * ethtool utility does not change advertised setting if auto
6003 * negotiation is not specified explicitly.
6004 */
6005 if (cmd->autoneg && priv->advertising == cmd->advertising) {
6006 cmd->advertising |= ADVERTISED_ALL;
6007 if (10 == speed)
6008 cmd->advertising &=
6009 ~(ADVERTISED_100baseT_Full |
6010 ADVERTISED_100baseT_Half);
6011 else if (100 == speed)
6012 cmd->advertising &=
6013 ~(ADVERTISED_10baseT_Full |
6014 ADVERTISED_10baseT_Half);
6015 if (0 == cmd->duplex)
6016 cmd->advertising &=
6017 ~(ADVERTISED_100baseT_Full |
6018 ADVERTISED_10baseT_Full);
6019 else if (1 == cmd->duplex)
6020 cmd->advertising &=
6021 ~(ADVERTISED_100baseT_Half |
6022 ADVERTISED_10baseT_Half);
6023 }
6024 mutex_lock(&hw_priv->lock);
6025 if (cmd->autoneg &&
6026 (cmd->advertising & ADVERTISED_ALL) ==
6027 ADVERTISED_ALL) {
6028 port->duplex = 0;
6029 port->speed = 0;
6030 port->force_link = 0;
6031 } else {
6032 port->duplex = cmd->duplex + 1;
6033 if (1000 != speed)
6034 port->speed = speed;
6035 if (cmd->autoneg)
6036 port->force_link = 0;
6037 else
6038 port->force_link = 1;
6039 }
6040 rc = mii_ethtool_sset(&priv->mii_if, cmd);
6041 mutex_unlock(&hw_priv->lock);
6042 return rc;
6043}
6044
6045/**
6046 * netdev_nway_reset - restart auto-negotiation
6047 * @dev: Network device.
6048 *
6049 * This function restarts the PHY for auto-negotiation.
6050 *
6051 * Return 0 if successful; otherwise an error code.
6052 */
6053static int netdev_nway_reset(struct net_device *dev)
6054{
6055 struct dev_priv *priv = netdev_priv(dev);
6056 struct dev_info *hw_priv = priv->adapter;
6057 int rc;
6058
6059 mutex_lock(&hw_priv->lock);
6060 rc = mii_nway_restart(&priv->mii_if);
6061 mutex_unlock(&hw_priv->lock);
6062 return rc;
6063}
6064
6065/**
6066 * netdev_get_link - get network device link status
6067 * @dev: Network device.
6068 *
6069 * This function gets the link status from the PHY.
6070 *
6071 * Return true if PHY is linked and false otherwise.
6072 */
6073static u32 netdev_get_link(struct net_device *dev)
6074{
6075 struct dev_priv *priv = netdev_priv(dev);
6076 int rc;
6077
6078 rc = mii_link_ok(&priv->mii_if);
6079 return rc;
6080}
6081
6082/**
6083 * netdev_get_drvinfo - get network driver information
6084 * @dev: Network device.
6085 * @info: Ethtool driver info data structure.
6086 *
6087 * This procedure returns the driver information.
6088 */
6089static void netdev_get_drvinfo(struct net_device *dev,
6090 struct ethtool_drvinfo *info)
6091{
6092 struct dev_priv *priv = netdev_priv(dev);
6093 struct dev_info *hw_priv = priv->adapter;
6094
6095 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
6096 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
6097 strlcpy(info->bus_info, pci_name(hw_priv->pdev),
6098 sizeof(info->bus_info));
6099}
6100
6101/**
6102 * netdev_get_regs_len - get length of register dump
6103 * @dev: Network device.
6104 *
6105 * This function returns the length of the register dump.
6106 *
6107 * Return length of the register dump.
6108 */
6109static struct hw_regs {
6110 int start;
6111 int end;
6112} hw_regs_range[] = {
6113 { KS_DMA_TX_CTRL, KS884X_INTERRUPTS_STATUS },
6114 { KS_ADD_ADDR_0_LO, KS_ADD_ADDR_F_HI },
6115 { KS884X_ADDR_0_OFFSET, KS8841_WOL_FRAME_BYTE2_OFFSET },
6116 { KS884X_SIDER_P, KS8842_SGCR7_P },
6117 { KS8842_MACAR1_P, KS8842_TOSR8_P },
6118 { KS884X_P1MBCR_P, KS8842_P3ERCR_P },
6119 { 0, 0 }
6120};
6121
6122static int netdev_get_regs_len(struct net_device *dev)
6123{
6124 struct hw_regs *range = hw_regs_range;
6125 int regs_len = 0x10 * sizeof(u32);
6126
6127 while (range->end > range->start) {
6128 regs_len += (range->end - range->start + 3) / 4 * 4;
6129 range++;
6130 }
6131 return regs_len;
6132}
6133
6134/**
6135 * netdev_get_regs - get register dump
6136 * @dev: Network device.
6137 * @regs: Ethtool registers data structure.
6138 * @ptr: Buffer to store the register values.
6139 *
6140 * This procedure dumps the register values in the provided buffer.
6141 */
6142static void netdev_get_regs(struct net_device *dev, struct ethtool_regs *regs,
6143 void *ptr)
6144{
6145 struct dev_priv *priv = netdev_priv(dev);
6146 struct dev_info *hw_priv = priv->adapter;
6147 struct ksz_hw *hw = &hw_priv->hw;
6148 int *buf = (int *) ptr;
6149 struct hw_regs *range = hw_regs_range;
6150 int len;
6151
6152 mutex_lock(&hw_priv->lock);
6153 regs->version = 0;
6154 for (len = 0; len < 0x40; len += 4) {
6155 pci_read_config_dword(hw_priv->pdev, len, buf);
6156 buf++;
6157 }
6158 while (range->end > range->start) {
6159 for (len = range->start; len < range->end; len += 4) {
6160 *buf = readl(hw->io + len);
6161 buf++;
6162 }
6163 range++;
6164 }
6165 mutex_unlock(&hw_priv->lock);
6166}
6167
6168#define WOL_SUPPORT \
6169 (WAKE_PHY | WAKE_MAGIC | \
6170 WAKE_UCAST | WAKE_MCAST | \
6171 WAKE_BCAST | WAKE_ARP)
6172
6173/**
6174 * netdev_get_wol - get Wake-on-LAN support
6175 * @dev: Network device.
6176 * @wol: Ethtool Wake-on-LAN data structure.
6177 *
6178 * This procedure returns Wake-on-LAN support.
6179 */
6180static void netdev_get_wol(struct net_device *dev,
6181 struct ethtool_wolinfo *wol)
6182{
6183 struct dev_priv *priv = netdev_priv(dev);
6184 struct dev_info *hw_priv = priv->adapter;
6185
6186 wol->supported = hw_priv->wol_support;
6187 wol->wolopts = hw_priv->wol_enable;
6188 memset(&wol->sopass, 0, sizeof(wol->sopass));
6189}
6190
6191/**
6192 * netdev_set_wol - set Wake-on-LAN support
6193 * @dev: Network device.
6194 * @wol: Ethtool Wake-on-LAN data structure.
6195 *
6196 * This function sets Wake-on-LAN support.
6197 *
6198 * Return 0 if successful; otherwise an error code.
6199 */
6200static int netdev_set_wol(struct net_device *dev,
6201 struct ethtool_wolinfo *wol)
6202{
6203 struct dev_priv *priv = netdev_priv(dev);
6204 struct dev_info *hw_priv = priv->adapter;
6205
6206 /* Need to find a way to retrieve the device IP address. */
6207 static const u8 net_addr[] = { 192, 168, 1, 1 };
6208
6209 if (wol->wolopts & ~hw_priv->wol_support)
6210 return -EINVAL;
6211
6212 hw_priv->wol_enable = wol->wolopts;
6213
6214 /* Link wakeup cannot really be disabled. */
6215 if (wol->wolopts)
6216 hw_priv->wol_enable |= WAKE_PHY;
6217 hw_enable_wol(&hw_priv->hw, hw_priv->wol_enable, net_addr);
6218 return 0;
6219}
6220
6221/**
6222 * netdev_get_msglevel - get debug message level
6223 * @dev: Network device.
6224 *
6225 * This function returns current debug message level.
6226 *
6227 * Return current debug message flags.
6228 */
6229static u32 netdev_get_msglevel(struct net_device *dev)
6230{
6231 struct dev_priv *priv = netdev_priv(dev);
6232
6233 return priv->msg_enable;
6234}
6235
6236/**
6237 * netdev_set_msglevel - set debug message level
6238 * @dev: Network device.
6239 * @value: Debug message flags.
6240 *
6241 * This procedure sets debug message level.
6242 */
6243static void netdev_set_msglevel(struct net_device *dev, u32 value)
6244{
6245 struct dev_priv *priv = netdev_priv(dev);
6246
6247 priv->msg_enable = value;
6248}
6249
6250/**
6251 * netdev_get_eeprom_len - get EEPROM length
6252 * @dev: Network device.
6253 *
6254 * This function returns the length of the EEPROM.
6255 *
6256 * Return length of the EEPROM.
6257 */
6258static int netdev_get_eeprom_len(struct net_device *dev)
6259{
6260 return EEPROM_SIZE * 2;
6261}
6262
6263/**
6264 * netdev_get_eeprom - get EEPROM data
6265 * @dev: Network device.
6266 * @eeprom: Ethtool EEPROM data structure.
6267 * @data: Buffer to store the EEPROM data.
6268 *
6269 * This function dumps the EEPROM data in the provided buffer.
6270 *
6271 * Return 0 if successful; otherwise an error code.
6272 */
6273#define EEPROM_MAGIC 0x10A18842
6274
6275static int netdev_get_eeprom(struct net_device *dev,
6276 struct ethtool_eeprom *eeprom, u8 *data)
6277{
6278 struct dev_priv *priv = netdev_priv(dev);
6279 struct dev_info *hw_priv = priv->adapter;
6280 u8 *eeprom_byte = (u8 *) eeprom_data;
6281 int i;
6282 int len;
6283
6284 len = (eeprom->offset + eeprom->len + 1) / 2;
6285 for (i = eeprom->offset / 2; i < len; i++)
6286 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6287 eeprom->magic = EEPROM_MAGIC;
6288 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
6289
6290 return 0;
6291}
6292
6293/**
6294 * netdev_set_eeprom - write EEPROM data
6295 * @dev: Network device.
6296 * @eeprom: Ethtool EEPROM data structure.
6297 * @data: Data buffer.
6298 *
6299 * This function modifies the EEPROM data one byte at a time.
6300 *
6301 * Return 0 if successful; otherwise an error code.
6302 */
6303static int netdev_set_eeprom(struct net_device *dev,
6304 struct ethtool_eeprom *eeprom, u8 *data)
6305{
6306 struct dev_priv *priv = netdev_priv(dev);
6307 struct dev_info *hw_priv = priv->adapter;
6308 u16 eeprom_word[EEPROM_SIZE];
6309 u8 *eeprom_byte = (u8 *) eeprom_word;
6310 int i;
6311 int len;
6312
6313 if (eeprom->magic != EEPROM_MAGIC)
6314 return -EINVAL;
6315
6316 len = (eeprom->offset + eeprom->len + 1) / 2;
6317 for (i = eeprom->offset / 2; i < len; i++)
6318 eeprom_data[i] = eeprom_read(&hw_priv->hw, i);
6319 memcpy(eeprom_word, eeprom_data, EEPROM_SIZE * 2);
6320 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
6321 for (i = 0; i < EEPROM_SIZE; i++)
6322 if (eeprom_word[i] != eeprom_data[i]) {
6323 eeprom_data[i] = eeprom_word[i];
6324 eeprom_write(&hw_priv->hw, i, eeprom_data[i]);
6325 }
6326
6327 return 0;
6328}
6329
6330/**
6331 * netdev_get_pauseparam - get flow control parameters
6332 * @dev: Network device.
6333 * @pause: Ethtool PAUSE settings data structure.
6334 *
6335 * This procedure returns the PAUSE control flow settings.
6336 */
6337static void netdev_get_pauseparam(struct net_device *dev,
6338 struct ethtool_pauseparam *pause)
6339{
6340 struct dev_priv *priv = netdev_priv(dev);
6341 struct dev_info *hw_priv = priv->adapter;
6342 struct ksz_hw *hw = &hw_priv->hw;
6343
6344 pause->autoneg = (hw->overrides & PAUSE_FLOW_CTRL) ? 0 : 1;
6345 if (!hw->ksz_switch) {
6346 pause->rx_pause =
6347 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6348 pause->tx_pause =
6349 (hw->tx_cfg & DMA_TX_FLOW_ENABLE) ? 1 : 0;
6350 } else {
6351 pause->rx_pause =
6352 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6353 SWITCH_RX_FLOW_CTRL)) ? 1 : 0;
6354 pause->tx_pause =
6355 (sw_chk(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6356 SWITCH_TX_FLOW_CTRL)) ? 1 : 0;
6357 }
6358}
6359
6360/**
6361 * netdev_set_pauseparam - set flow control parameters
6362 * @dev: Network device.
6363 * @pause: Ethtool PAUSE settings data structure.
6364 *
6365 * This function sets the PAUSE control flow settings.
6366 * Not implemented yet.
6367 *
6368 * Return 0 if successful; otherwise an error code.
6369 */
6370static int netdev_set_pauseparam(struct net_device *dev,
6371 struct ethtool_pauseparam *pause)
6372{
6373 struct dev_priv *priv = netdev_priv(dev);
6374 struct dev_info *hw_priv = priv->adapter;
6375 struct ksz_hw *hw = &hw_priv->hw;
6376 struct ksz_port *port = &priv->port;
6377
6378 mutex_lock(&hw_priv->lock);
6379 if (pause->autoneg) {
6380 if (!pause->rx_pause && !pause->tx_pause)
6381 port->flow_ctrl = PHY_NO_FLOW_CTRL;
6382 else
6383 port->flow_ctrl = PHY_FLOW_CTRL;
6384 hw->overrides &= ~PAUSE_FLOW_CTRL;
6385 port->force_link = 0;
6386 if (hw->ksz_switch) {
6387 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6388 SWITCH_RX_FLOW_CTRL, 1);
6389 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6390 SWITCH_TX_FLOW_CTRL, 1);
6391 }
6392 port_set_link_speed(port);
6393 } else {
6394 hw->overrides |= PAUSE_FLOW_CTRL;
6395 if (hw->ksz_switch) {
6396 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6397 SWITCH_RX_FLOW_CTRL, pause->rx_pause);
6398 sw_cfg(hw, KS8842_SWITCH_CTRL_1_OFFSET,
6399 SWITCH_TX_FLOW_CTRL, pause->tx_pause);
6400 } else
6401 set_flow_ctrl(hw, pause->rx_pause, pause->tx_pause);
6402 }
6403 mutex_unlock(&hw_priv->lock);
6404
6405 return 0;
6406}
6407
6408/**
6409 * netdev_get_ringparam - get tx/rx ring parameters
6410 * @dev: Network device.
6411 * @pause: Ethtool RING settings data structure.
6412 *
6413 * This procedure returns the TX/RX ring settings.
6414 */
6415static void netdev_get_ringparam(struct net_device *dev,
6416 struct ethtool_ringparam *ring)
6417{
6418 struct dev_priv *priv = netdev_priv(dev);
6419 struct dev_info *hw_priv = priv->adapter;
6420 struct ksz_hw *hw = &hw_priv->hw;
6421
6422 ring->tx_max_pending = (1 << 9);
6423 ring->tx_pending = hw->tx_desc_info.alloc;
6424 ring->rx_max_pending = (1 << 9);
6425 ring->rx_pending = hw->rx_desc_info.alloc;
6426}
6427
6428#define STATS_LEN (TOTAL_PORT_COUNTER_NUM)
6429
6430static struct {
6431 char string[ETH_GSTRING_LEN];
6432} ethtool_stats_keys[STATS_LEN] = {
6433 { "rx_lo_priority_octets" },
6434 { "rx_hi_priority_octets" },
6435 { "rx_undersize_packets" },
6436 { "rx_fragments" },
6437 { "rx_oversize_packets" },
6438 { "rx_jabbers" },
6439 { "rx_symbol_errors" },
6440 { "rx_crc_errors" },
6441 { "rx_align_errors" },
6442 { "rx_mac_ctrl_packets" },
6443 { "rx_pause_packets" },
6444 { "rx_bcast_packets" },
6445 { "rx_mcast_packets" },
6446 { "rx_ucast_packets" },
6447 { "rx_64_or_less_octet_packets" },
6448 { "rx_65_to_127_octet_packets" },
6449 { "rx_128_to_255_octet_packets" },
6450 { "rx_256_to_511_octet_packets" },
6451 { "rx_512_to_1023_octet_packets" },
6452 { "rx_1024_to_1522_octet_packets" },
6453
6454 { "tx_lo_priority_octets" },
6455 { "tx_hi_priority_octets" },
6456 { "tx_late_collisions" },
6457 { "tx_pause_packets" },
6458 { "tx_bcast_packets" },
6459 { "tx_mcast_packets" },
6460 { "tx_ucast_packets" },
6461 { "tx_deferred" },
6462 { "tx_total_collisions" },
6463 { "tx_excessive_collisions" },
6464 { "tx_single_collisions" },
6465 { "tx_mult_collisions" },
6466
6467 { "rx_discards" },
6468 { "tx_discards" },
6469};
6470
6471/**
6472 * netdev_get_strings - get statistics identity strings
6473 * @dev: Network device.
6474 * @stringset: String set identifier.
6475 * @buf: Buffer to store the strings.
6476 *
6477 * This procedure returns the strings used to identify the statistics.
6478 */
6479static void netdev_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
6480{
6481 struct dev_priv *priv = netdev_priv(dev);
6482 struct dev_info *hw_priv = priv->adapter;
6483 struct ksz_hw *hw = &hw_priv->hw;
6484
6485 if (ETH_SS_STATS == stringset)
6486 memcpy(buf, ðtool_stats_keys,
6487 ETH_GSTRING_LEN * hw->mib_cnt);
6488}
6489
6490/**
6491 * netdev_get_sset_count - get statistics size
6492 * @dev: Network device.
6493 * @sset: The statistics set number.
6494 *
6495 * This function returns the size of the statistics to be reported.
6496 *
6497 * Return size of the statistics to be reported.
6498 */
6499static int netdev_get_sset_count(struct net_device *dev, int sset)
6500{
6501 struct dev_priv *priv = netdev_priv(dev);
6502 struct dev_info *hw_priv = priv->adapter;
6503 struct ksz_hw *hw = &hw_priv->hw;
6504
6505 switch (sset) {
6506 case ETH_SS_STATS:
6507 return hw->mib_cnt;
6508 default:
6509 return -EOPNOTSUPP;
6510 }
6511}
6512
6513/**
6514 * netdev_get_ethtool_stats - get network device statistics
6515 * @dev: Network device.
6516 * @stats: Ethtool statistics data structure.
6517 * @data: Buffer to store the statistics.
6518 *
6519 * This procedure returns the statistics.
6520 */
6521static void netdev_get_ethtool_stats(struct net_device *dev,
6522 struct ethtool_stats *stats, u64 *data)
6523{
6524 struct dev_priv *priv = netdev_priv(dev);
6525 struct dev_info *hw_priv = priv->adapter;
6526 struct ksz_hw *hw = &hw_priv->hw;
6527 struct ksz_port *port = &priv->port;
6528 int n_stats = stats->n_stats;
6529 int i;
6530 int n;
6531 int p;
6532 int rc;
6533 u64 counter[TOTAL_PORT_COUNTER_NUM];
6534
6535 mutex_lock(&hw_priv->lock);
6536 n = SWITCH_PORT_NUM;
6537 for (i = 0, p = port->first_port; i < port->mib_port_cnt; i++, p++) {
6538 if (media_connected == hw->port_mib[p].state) {
6539 hw_priv->counter[p].read = 1;
6540
6541 /* Remember first port that requests read. */
6542 if (n == SWITCH_PORT_NUM)
6543 n = p;
6544 }
6545 }
6546 mutex_unlock(&hw_priv->lock);
6547
6548 if (n < SWITCH_PORT_NUM)
6549 schedule_work(&hw_priv->mib_read);
6550
6551 if (1 == port->mib_port_cnt && n < SWITCH_PORT_NUM) {
6552 p = n;
6553 rc = wait_event_interruptible_timeout(
6554 hw_priv->counter[p].counter,
6555 2 == hw_priv->counter[p].read,
6556 HZ * 1);
6557 } else
6558 for (i = 0, p = n; i < port->mib_port_cnt - n; i++, p++) {
6559 if (0 == i) {
6560 rc = wait_event_interruptible_timeout(
6561 hw_priv->counter[p].counter,
6562 2 == hw_priv->counter[p].read,
6563 HZ * 2);
6564 } else if (hw->port_mib[p].cnt_ptr) {
6565 rc = wait_event_interruptible_timeout(
6566 hw_priv->counter[p].counter,
6567 2 == hw_priv->counter[p].read,
6568 HZ * 1);
6569 }
6570 }
6571
6572 get_mib_counters(hw, port->first_port, port->mib_port_cnt, counter);
6573 n = hw->mib_cnt;
6574 if (n > n_stats)
6575 n = n_stats;
6576 n_stats -= n;
6577 for (i = 0; i < n; i++)
6578 *data++ = counter[i];
6579}
6580
6581/**
6582 * netdev_set_features - set receive checksum support
6583 * @dev: Network device.
6584 * @features: New device features (offloads).
6585 *
6586 * This function sets receive checksum support setting.
6587 *
6588 * Return 0 if successful; otherwise an error code.
6589 */
6590static int netdev_set_features(struct net_device *dev,
6591 netdev_features_t features)
6592{
6593 struct dev_priv *priv = netdev_priv(dev);
6594 struct dev_info *hw_priv = priv->adapter;
6595 struct ksz_hw *hw = &hw_priv->hw;
6596
6597 mutex_lock(&hw_priv->lock);
6598
6599 /* see note in hw_setup() */
6600 if (features & NETIF_F_RXCSUM)
6601 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6602 else
6603 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6604
6605 if (hw->enabled)
6606 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
6607
6608 mutex_unlock(&hw_priv->lock);
6609
6610 return 0;
6611}
6612
6613static const struct ethtool_ops netdev_ethtool_ops = {
6614 .get_settings = netdev_get_settings,
6615 .set_settings = netdev_set_settings,
6616 .nway_reset = netdev_nway_reset,
6617 .get_link = netdev_get_link,
6618 .get_drvinfo = netdev_get_drvinfo,
6619 .get_regs_len = netdev_get_regs_len,
6620 .get_regs = netdev_get_regs,
6621 .get_wol = netdev_get_wol,
6622 .set_wol = netdev_set_wol,
6623 .get_msglevel = netdev_get_msglevel,
6624 .set_msglevel = netdev_set_msglevel,
6625 .get_eeprom_len = netdev_get_eeprom_len,
6626 .get_eeprom = netdev_get_eeprom,
6627 .set_eeprom = netdev_set_eeprom,
6628 .get_pauseparam = netdev_get_pauseparam,
6629 .set_pauseparam = netdev_set_pauseparam,
6630 .get_ringparam = netdev_get_ringparam,
6631 .get_strings = netdev_get_strings,
6632 .get_sset_count = netdev_get_sset_count,
6633 .get_ethtool_stats = netdev_get_ethtool_stats,
6634};
6635
6636/*
6637 * Hardware monitoring
6638 */
6639
6640static void update_link(struct net_device *dev, struct dev_priv *priv,
6641 struct ksz_port *port)
6642{
6643 if (priv->media_state != port->linked->state) {
6644 priv->media_state = port->linked->state;
6645 if (netif_running(dev))
6646 set_media_state(dev, media_connected);
6647 }
6648}
6649
6650static void mib_read_work(struct work_struct *work)
6651{
6652 struct dev_info *hw_priv =
6653 container_of(work, struct dev_info, mib_read);
6654 struct ksz_hw *hw = &hw_priv->hw;
6655 struct ksz_port_mib *mib;
6656 int i;
6657
6658 next_jiffies = jiffies;
6659 for (i = 0; i < hw->mib_port_cnt; i++) {
6660 mib = &hw->port_mib[i];
6661
6662 /* Reading MIB counters or requested to read. */
6663 if (mib->cnt_ptr || 1 == hw_priv->counter[i].read) {
6664
6665 /* Need to process receive interrupt. */
6666 if (port_r_cnt(hw, i))
6667 break;
6668 hw_priv->counter[i].read = 0;
6669
6670 /* Finish reading counters. */
6671 if (0 == mib->cnt_ptr) {
6672 hw_priv->counter[i].read = 2;
6673 wake_up_interruptible(
6674 &hw_priv->counter[i].counter);
6675 }
6676 } else if (jiffies >= hw_priv->counter[i].time) {
6677 /* Only read MIB counters when the port is connected. */
6678 if (media_connected == mib->state)
6679 hw_priv->counter[i].read = 1;
6680 next_jiffies += HZ * 1 * hw->mib_port_cnt;
6681 hw_priv->counter[i].time = next_jiffies;
6682
6683 /* Port is just disconnected. */
6684 } else if (mib->link_down) {
6685 mib->link_down = 0;
6686
6687 /* Read counters one last time after link is lost. */
6688 hw_priv->counter[i].read = 1;
6689 }
6690 }
6691}
6692
6693static void mib_monitor(unsigned long ptr)
6694{
6695 struct dev_info *hw_priv = (struct dev_info *) ptr;
6696
6697 mib_read_work(&hw_priv->mib_read);
6698
6699 /* This is used to verify Wake-on-LAN is working. */
6700 if (hw_priv->pme_wait) {
6701 if (hw_priv->pme_wait <= jiffies) {
6702 hw_clr_wol_pme_status(&hw_priv->hw);
6703 hw_priv->pme_wait = 0;
6704 }
6705 } else if (hw_chk_wol_pme_status(&hw_priv->hw)) {
6706
6707 /* PME is asserted. Wait 2 seconds to clear it. */
6708 hw_priv->pme_wait = jiffies + HZ * 2;
6709 }
6710
6711 ksz_update_timer(&hw_priv->mib_timer_info);
6712}
6713
6714/**
6715 * dev_monitor - periodic monitoring
6716 * @ptr: Network device pointer.
6717 *
6718 * This routine is run in a kernel timer to monitor the network device.
6719 */
6720static void dev_monitor(unsigned long ptr)
6721{
6722 struct net_device *dev = (struct net_device *) ptr;
6723 struct dev_priv *priv = netdev_priv(dev);
6724 struct dev_info *hw_priv = priv->adapter;
6725 struct ksz_hw *hw = &hw_priv->hw;
6726 struct ksz_port *port = &priv->port;
6727
6728 if (!(hw->features & LINK_INT_WORKING))
6729 port_get_link_speed(port);
6730 update_link(dev, priv, port);
6731
6732 ksz_update_timer(&priv->monitor_timer_info);
6733}
6734
6735/*
6736 * Linux network device interface functions
6737 */
6738
6739/* Driver exported variables */
6740
6741static int msg_enable;
6742
6743static char *macaddr = ":";
6744static char *mac1addr = ":";
6745
6746/*
6747 * This enables multiple network device mode for KSZ8842, which contains a
6748 * switch with two physical ports. Some users like to take control of the
6749 * ports for running Spanning Tree Protocol. The driver will create an
6750 * additional eth? device for the other port.
6751 *
6752 * Some limitations are the network devices cannot have different MTU and
6753 * multicast hash tables.
6754 */
6755static int multi_dev;
6756
6757/*
6758 * As most users select multiple network device mode to use Spanning Tree
6759 * Protocol, this enables a feature in which most unicast and multicast packets
6760 * are forwarded inside the switch and not passed to the host. Only packets
6761 * that need the host's attention are passed to it. This prevents the host
6762 * wasting CPU time to examine each and every incoming packets and do the
6763 * forwarding itself.
6764 *
6765 * As the hack requires the private bridge header, the driver cannot compile
6766 * with just the kernel headers.
6767 *
6768 * Enabling STP support also turns on multiple network device mode.
6769 */
6770static int stp;
6771
6772/*
6773 * This enables fast aging in the KSZ8842 switch. Not sure what situation
6774 * needs that. However, fast aging is used to flush the dynamic MAC table when
6775 * STP support is enabled.
6776 */
6777static int fast_aging;
6778
6779/**
6780 * netdev_init - initialize network device.
6781 * @dev: Network device.
6782 *
6783 * This function initializes the network device.
6784 *
6785 * Return 0 if successful; otherwise an error code indicating failure.
6786 */
6787static int __init netdev_init(struct net_device *dev)
6788{
6789 struct dev_priv *priv = netdev_priv(dev);
6790
6791 /* 500 ms timeout */
6792 ksz_init_timer(&priv->monitor_timer_info, 500 * HZ / 1000,
6793 dev_monitor, dev);
6794
6795 /* 500 ms timeout */
6796 dev->watchdog_timeo = HZ / 2;
6797
6798 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_RXCSUM;
6799
6800 /*
6801 * Hardware does not really support IPv6 checksum generation, but
6802 * driver actually runs faster with this on.
6803 */
6804 dev->hw_features |= NETIF_F_IPV6_CSUM;
6805
6806 dev->features |= dev->hw_features;
6807
6808 sema_init(&priv->proc_sem, 1);
6809
6810 priv->mii_if.phy_id_mask = 0x1;
6811 priv->mii_if.reg_num_mask = 0x7;
6812 priv->mii_if.dev = dev;
6813 priv->mii_if.mdio_read = mdio_read;
6814 priv->mii_if.mdio_write = mdio_write;
6815 priv->mii_if.phy_id = priv->port.first_port + 1;
6816
6817 priv->msg_enable = netif_msg_init(msg_enable,
6818 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK));
6819
6820 return 0;
6821}
6822
6823static const struct net_device_ops netdev_ops = {
6824 .ndo_init = netdev_init,
6825 .ndo_open = netdev_open,
6826 .ndo_stop = netdev_close,
6827 .ndo_get_stats = netdev_query_statistics,
6828 .ndo_start_xmit = netdev_tx,
6829 .ndo_tx_timeout = netdev_tx_timeout,
6830 .ndo_change_mtu = netdev_change_mtu,
6831 .ndo_set_features = netdev_set_features,
6832 .ndo_set_mac_address = netdev_set_mac_address,
6833 .ndo_validate_addr = eth_validate_addr,
6834 .ndo_do_ioctl = netdev_ioctl,
6835 .ndo_set_rx_mode = netdev_set_rx_mode,
6836#ifdef CONFIG_NET_POLL_CONTROLLER
6837 .ndo_poll_controller = netdev_netpoll,
6838#endif
6839};
6840
6841static void netdev_free(struct net_device *dev)
6842{
6843 if (dev->watchdog_timeo)
6844 unregister_netdev(dev);
6845
6846 free_netdev(dev);
6847}
6848
6849struct platform_info {
6850 struct dev_info dev_info;
6851 struct net_device *netdev[SWITCH_PORT_NUM];
6852};
6853
6854static int net_device_present;
6855
6856static void get_mac_addr(struct dev_info *hw_priv, u8 *macaddr, int port)
6857{
6858 int i;
6859 int j;
6860 int got_num;
6861 int num;
6862
6863 i = j = num = got_num = 0;
6864 while (j < ETH_ALEN) {
6865 if (macaddr[i]) {
6866 int digit;
6867
6868 got_num = 1;
6869 digit = hex_to_bin(macaddr[i]);
6870 if (digit >= 0)
6871 num = num * 16 + digit;
6872 else if (':' == macaddr[i])
6873 got_num = 2;
6874 else
6875 break;
6876 } else if (got_num)
6877 got_num = 2;
6878 else
6879 break;
6880 if (2 == got_num) {
6881 if (MAIN_PORT == port) {
6882 hw_priv->hw.override_addr[j++] = (u8) num;
6883 hw_priv->hw.override_addr[5] +=
6884 hw_priv->hw.id;
6885 } else {
6886 hw_priv->hw.ksz_switch->other_addr[j++] =
6887 (u8) num;
6888 hw_priv->hw.ksz_switch->other_addr[5] +=
6889 hw_priv->hw.id;
6890 }
6891 num = got_num = 0;
6892 }
6893 i++;
6894 }
6895 if (ETH_ALEN == j) {
6896 if (MAIN_PORT == port)
6897 hw_priv->hw.mac_override = 1;
6898 }
6899}
6900
6901#define KS884X_DMA_MASK (~0x0UL)
6902
6903static void read_other_addr(struct ksz_hw *hw)
6904{
6905 int i;
6906 u16 data[3];
6907 struct ksz_switch *sw = hw->ksz_switch;
6908
6909 for (i = 0; i < 3; i++)
6910 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6911 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6912 sw->other_addr[5] = (u8) data[0];
6913 sw->other_addr[4] = (u8)(data[0] >> 8);
6914 sw->other_addr[3] = (u8) data[1];
6915 sw->other_addr[2] = (u8)(data[1] >> 8);
6916 sw->other_addr[1] = (u8) data[2];
6917 sw->other_addr[0] = (u8)(data[2] >> 8);
6918 }
6919}
6920
6921#ifndef PCI_VENDOR_ID_MICREL_KS
6922#define PCI_VENDOR_ID_MICREL_KS 0x16c6
6923#endif
6924
6925static int pcidev_init(struct pci_dev *pdev, const struct pci_device_id *id)
6926{
6927 struct net_device *dev;
6928 struct dev_priv *priv;
6929 struct dev_info *hw_priv;
6930 struct ksz_hw *hw;
6931 struct platform_info *info;
6932 struct ksz_port *port;
6933 unsigned long reg_base;
6934 unsigned long reg_len;
6935 int cnt;
6936 int i;
6937 int mib_port_count;
6938 int pi;
6939 int port_count;
6940 int result;
6941 char banner[sizeof(version)];
6942 struct ksz_switch *sw = NULL;
6943
6944 result = pci_enable_device(pdev);
6945 if (result)
6946 return result;
6947
6948 result = -ENODEV;
6949
6950 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) ||
6951 pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
6952 return result;
6953
6954 reg_base = pci_resource_start(pdev, 0);
6955 reg_len = pci_resource_len(pdev, 0);
6956 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0)
6957 return result;
6958
6959 if (!request_mem_region(reg_base, reg_len, DRV_NAME))
6960 return result;
6961 pci_set_master(pdev);
6962
6963 result = -ENOMEM;
6964
6965 info = kzalloc(sizeof(struct platform_info), GFP_KERNEL);
6966 if (!info)
6967 goto pcidev_init_dev_err;
6968
6969 hw_priv = &info->dev_info;
6970 hw_priv->pdev = pdev;
6971
6972 hw = &hw_priv->hw;
6973
6974 hw->io = ioremap(reg_base, reg_len);
6975 if (!hw->io)
6976 goto pcidev_init_io_err;
6977
6978 cnt = hw_init(hw);
6979 if (!cnt) {
6980 if (msg_enable & NETIF_MSG_PROBE)
6981 pr_alert("chip not detected\n");
6982 result = -ENODEV;
6983 goto pcidev_init_alloc_err;
6984 }
6985
6986 snprintf(banner, sizeof(banner), "%s", version);
6987 banner[13] = cnt + '0'; /* Replace x in "Micrel KSZ884x" */
6988 dev_info(&hw_priv->pdev->dev, "%s\n", banner);
6989 dev_dbg(&hw_priv->pdev->dev, "Mem = %p; IRQ = %d\n", hw->io, pdev->irq);
6990
6991 /* Assume device is KSZ8841. */
6992 hw->dev_count = 1;
6993 port_count = 1;
6994 mib_port_count = 1;
6995 hw->addr_list_size = 0;
6996 hw->mib_cnt = PORT_COUNTER_NUM;
6997 hw->mib_port_cnt = 1;
6998
6999 /* KSZ8842 has a switch with multiple ports. */
7000 if (2 == cnt) {
7001 if (fast_aging)
7002 hw->overrides |= FAST_AGING;
7003
7004 hw->mib_cnt = TOTAL_PORT_COUNTER_NUM;
7005
7006 /* Multiple network device interfaces are required. */
7007 if (multi_dev) {
7008 hw->dev_count = SWITCH_PORT_NUM;
7009 hw->addr_list_size = SWITCH_PORT_NUM - 1;
7010 }
7011
7012 /* Single network device has multiple ports. */
7013 if (1 == hw->dev_count) {
7014 port_count = SWITCH_PORT_NUM;
7015 mib_port_count = SWITCH_PORT_NUM;
7016 }
7017 hw->mib_port_cnt = TOTAL_PORT_NUM;
7018 hw->ksz_switch = kzalloc(sizeof(struct ksz_switch), GFP_KERNEL);
7019 if (!hw->ksz_switch)
7020 goto pcidev_init_alloc_err;
7021
7022 sw = hw->ksz_switch;
7023 }
7024 for (i = 0; i < hw->mib_port_cnt; i++)
7025 hw->port_mib[i].mib_start = 0;
7026
7027 hw->parent = hw_priv;
7028
7029 /* Default MTU is 1500. */
7030 hw_priv->mtu = (REGULAR_RX_BUF_SIZE + 3) & ~3;
7031
7032 if (ksz_alloc_mem(hw_priv))
7033 goto pcidev_init_mem_err;
7034
7035 hw_priv->hw.id = net_device_present;
7036
7037 spin_lock_init(&hw_priv->hwlock);
7038 mutex_init(&hw_priv->lock);
7039
7040 for (i = 0; i < TOTAL_PORT_NUM; i++)
7041 init_waitqueue_head(&hw_priv->counter[i].counter);
7042
7043 if (macaddr[0] != ':')
7044 get_mac_addr(hw_priv, macaddr, MAIN_PORT);
7045
7046 /* Read MAC address and initialize override address if not overrided. */
7047 hw_read_addr(hw);
7048
7049 /* Multiple device interfaces mode requires a second MAC address. */
7050 if (hw->dev_count > 1) {
7051 memcpy(sw->other_addr, hw->override_addr, ETH_ALEN);
7052 read_other_addr(hw);
7053 if (mac1addr[0] != ':')
7054 get_mac_addr(hw_priv, mac1addr, OTHER_PORT);
7055 }
7056
7057 hw_setup(hw);
7058 if (hw->ksz_switch)
7059 sw_setup(hw);
7060 else {
7061 hw_priv->wol_support = WOL_SUPPORT;
7062 hw_priv->wol_enable = 0;
7063 }
7064
7065 INIT_WORK(&hw_priv->mib_read, mib_read_work);
7066
7067 /* 500 ms timeout */
7068 ksz_init_timer(&hw_priv->mib_timer_info, 500 * HZ / 1000,
7069 mib_monitor, hw_priv);
7070
7071 for (i = 0; i < hw->dev_count; i++) {
7072 dev = alloc_etherdev(sizeof(struct dev_priv));
7073 if (!dev)
7074 goto pcidev_init_reg_err;
7075 info->netdev[i] = dev;
7076
7077 priv = netdev_priv(dev);
7078 priv->adapter = hw_priv;
7079 priv->id = net_device_present++;
7080
7081 port = &priv->port;
7082 port->port_cnt = port_count;
7083 port->mib_port_cnt = mib_port_count;
7084 port->first_port = i;
7085 port->flow_ctrl = PHY_FLOW_CTRL;
7086
7087 port->hw = hw;
7088 port->linked = &hw->port_info[port->first_port];
7089
7090 for (cnt = 0, pi = i; cnt < port_count; cnt++, pi++) {
7091 hw->port_info[pi].port_id = pi;
7092 hw->port_info[pi].pdev = dev;
7093 hw->port_info[pi].state = media_disconnected;
7094 }
7095
7096 dev->mem_start = (unsigned long) hw->io;
7097 dev->mem_end = dev->mem_start + reg_len - 1;
7098 dev->irq = pdev->irq;
7099 if (MAIN_PORT == i)
7100 memcpy(dev->dev_addr, hw_priv->hw.override_addr,
7101 ETH_ALEN);
7102 else {
7103 memcpy(dev->dev_addr, sw->other_addr, ETH_ALEN);
7104 if (ether_addr_equal(sw->other_addr, hw->override_addr))
7105 dev->dev_addr[5] += port->first_port;
7106 }
7107
7108 dev->netdev_ops = &netdev_ops;
7109 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
7110 if (register_netdev(dev))
7111 goto pcidev_init_reg_err;
7112 port_set_power_saving(port, true);
7113 }
7114
7115 pci_dev_get(hw_priv->pdev);
7116 pci_set_drvdata(pdev, info);
7117 return 0;
7118
7119pcidev_init_reg_err:
7120 for (i = 0; i < hw->dev_count; i++) {
7121 if (info->netdev[i]) {
7122 netdev_free(info->netdev[i]);
7123 info->netdev[i] = NULL;
7124 }
7125 }
7126
7127pcidev_init_mem_err:
7128 ksz_free_mem(hw_priv);
7129 kfree(hw->ksz_switch);
7130
7131pcidev_init_alloc_err:
7132 iounmap(hw->io);
7133
7134pcidev_init_io_err:
7135 kfree(info);
7136
7137pcidev_init_dev_err:
7138 release_mem_region(reg_base, reg_len);
7139
7140 return result;
7141}
7142
7143static void pcidev_exit(struct pci_dev *pdev)
7144{
7145 int i;
7146 struct platform_info *info = pci_get_drvdata(pdev);
7147 struct dev_info *hw_priv = &info->dev_info;
7148
7149 release_mem_region(pci_resource_start(pdev, 0),
7150 pci_resource_len(pdev, 0));
7151 for (i = 0; i < hw_priv->hw.dev_count; i++) {
7152 if (info->netdev[i])
7153 netdev_free(info->netdev[i]);
7154 }
7155 if (hw_priv->hw.io)
7156 iounmap(hw_priv->hw.io);
7157 ksz_free_mem(hw_priv);
7158 kfree(hw_priv->hw.ksz_switch);
7159 pci_dev_put(hw_priv->pdev);
7160 kfree(info);
7161}
7162
7163#ifdef CONFIG_PM
7164static int pcidev_resume(struct pci_dev *pdev)
7165{
7166 int i;
7167 struct platform_info *info = pci_get_drvdata(pdev);
7168 struct dev_info *hw_priv = &info->dev_info;
7169 struct ksz_hw *hw = &hw_priv->hw;
7170
7171 pci_set_power_state(pdev, PCI_D0);
7172 pci_restore_state(pdev);
7173 pci_enable_wake(pdev, PCI_D0, 0);
7174
7175 if (hw_priv->wol_enable)
7176 hw_cfg_wol_pme(hw, 0);
7177 for (i = 0; i < hw->dev_count; i++) {
7178 if (info->netdev[i]) {
7179 struct net_device *dev = info->netdev[i];
7180
7181 if (netif_running(dev)) {
7182 netdev_open(dev);
7183 netif_device_attach(dev);
7184 }
7185 }
7186 }
7187 return 0;
7188}
7189
7190static int pcidev_suspend(struct pci_dev *pdev, pm_message_t state)
7191{
7192 int i;
7193 struct platform_info *info = pci_get_drvdata(pdev);
7194 struct dev_info *hw_priv = &info->dev_info;
7195 struct ksz_hw *hw = &hw_priv->hw;
7196
7197 /* Need to find a way to retrieve the device IP address. */
7198 static const u8 net_addr[] = { 192, 168, 1, 1 };
7199
7200 for (i = 0; i < hw->dev_count; i++) {
7201 if (info->netdev[i]) {
7202 struct net_device *dev = info->netdev[i];
7203
7204 if (netif_running(dev)) {
7205 netif_device_detach(dev);
7206 netdev_close(dev);
7207 }
7208 }
7209 }
7210 if (hw_priv->wol_enable) {
7211 hw_enable_wol(hw, hw_priv->wol_enable, net_addr);
7212 hw_cfg_wol_pme(hw, 1);
7213 }
7214
7215 pci_save_state(pdev);
7216 pci_enable_wake(pdev, pci_choose_state(pdev, state), 1);
7217 pci_set_power_state(pdev, pci_choose_state(pdev, state));
7218 return 0;
7219}
7220#endif
7221
7222static char pcidev_name[] = "ksz884xp";
7223
7224static DEFINE_PCI_DEVICE_TABLE(pcidev_table) = {
7225 { PCI_VENDOR_ID_MICREL_KS, 0x8841,
7226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7227 { PCI_VENDOR_ID_MICREL_KS, 0x8842,
7228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
7229 { 0 }
7230};
7231
7232MODULE_DEVICE_TABLE(pci, pcidev_table);
7233
7234static struct pci_driver pci_device_driver = {
7235#ifdef CONFIG_PM
7236 .suspend = pcidev_suspend,
7237 .resume = pcidev_resume,
7238#endif
7239 .name = pcidev_name,
7240 .id_table = pcidev_table,
7241 .probe = pcidev_init,
7242 .remove = pcidev_exit
7243};
7244
7245module_pci_driver(pci_device_driver);
7246
7247MODULE_DESCRIPTION("KSZ8841/2 PCI network driver");
7248MODULE_AUTHOR("Tristram Ha <Tristram.Ha@micrel.com>");
7249MODULE_LICENSE("GPL");
7250
7251module_param_named(message, msg_enable, int, 0);
7252MODULE_PARM_DESC(message, "Message verbosity level (0=none, 31=all)");
7253
7254module_param(macaddr, charp, 0);
7255module_param(mac1addr, charp, 0);
7256module_param(fast_aging, int, 0);
7257module_param(multi_dev, int, 0);
7258module_param(stp, int, 0);
7259MODULE_PARM_DESC(macaddr, "MAC address");
7260MODULE_PARM_DESC(mac1addr, "Second MAC address");
7261MODULE_PARM_DESC(fast_aging, "Fast aging");
7262MODULE_PARM_DESC(multi_dev, "Multiple device interfaces");
7263MODULE_PARM_DESC(stp, "STP support");