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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * linux/arch/alpha/kernel/sys_sio.c
4 *
5 * Copyright (C) 1995 David A Rusling
6 * Copyright (C) 1996 Jay A Estabrook
7 * Copyright (C) 1998, 1999 Richard Henderson
8 *
9 * Code for all boards that route the PCI interrupts through the SIO
10 * PCI/ISA bridge. This includes Noname (AXPpci33), Multia (UDB),
11 * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/screen_info.h>
21
22#include <asm/compiler.h>
23#include <asm/ptrace.h>
24#include <asm/dma.h>
25#include <asm/irq.h>
26#include <asm/mmu_context.h>
27#include <asm/io.h>
28#include <asm/core_apecs.h>
29#include <asm/core_lca.h>
30#include <asm/tlbflush.h>
31
32#include "proto.h"
33#include "irq_impl.h"
34#include "pci_impl.h"
35#include "machvec_impl.h"
36#include "pc873xx.h"
37
38#if defined(ALPHA_RESTORE_SRM_SETUP)
39/* Save LCA configuration data as the console had it set up. */
40struct
41{
42 unsigned int orig_route_tab; /* for SAVE/RESTORE */
43} saved_config __attribute((common));
44#endif
45
46
47static void __init
48sio_init_irq(void)
49{
50 if (alpha_using_srm)
51 alpha_mv.device_interrupt = srm_device_interrupt;
52
53 init_i8259a_irqs();
54 common_init_isa_dma();
55}
56
57static inline void __init
58alphabook1_init_arch(void)
59{
60#ifdef CONFIG_VGA_CONSOLE
61 /* The AlphaBook1 has LCD video fixed at 800x600,
62 37 rows and 100 cols. */
63 vgacon_screen_info.orig_y = 37;
64 vgacon_screen_info.orig_video_cols = 100;
65 vgacon_screen_info.orig_video_lines = 37;
66#endif
67
68 lca_init_arch();
69}
70
71
72/*
73 * sio_route_tab selects irq routing in PCI/ISA bridge so that:
74 * PIRQ0 -> irq 15
75 * PIRQ1 -> irq 9
76 * PIRQ2 -> irq 10
77 * PIRQ3 -> irq 11
78 *
79 * This probably ought to be configurable via MILO. For
80 * example, sound boards seem to like using IRQ 9.
81 *
82 * This is NOT how we should do it. PIRQ0-X should have
83 * their own IRQs, the way intel uses the IO-APIC IRQs.
84 */
85
86static void __init
87sio_pci_route(void)
88{
89 unsigned int orig_route_tab;
90
91 /* First, ALWAYS read and print the original setting. */
92 pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
93 &orig_route_tab);
94 printk("%s: PIRQ original 0x%x new 0x%x\n", __func__,
95 orig_route_tab, alpha_mv.sys.sio.route_tab);
96
97#if defined(ALPHA_RESTORE_SRM_SETUP)
98 saved_config.orig_route_tab = orig_route_tab;
99#endif
100
101 /* Now override with desired setting. */
102 pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
103 alpha_mv.sys.sio.route_tab);
104}
105
106static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
107{
108 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
109 (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
110 return false;
111
112 return true;
113}
114
115static unsigned int __init
116sio_collect_irq_levels(void)
117{
118 unsigned int level_bits = 0;
119 struct pci_dev *dev = NULL;
120
121 /* Iterate through the devices, collecting IRQ levels. */
122 for_each_pci_dev(dev) {
123 if (!sio_pci_dev_irq_needs_level(dev))
124 continue;
125
126 if (dev->irq)
127 level_bits |= (1 << dev->irq);
128 }
129 return level_bits;
130}
131
132static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
133{
134 unsigned int old_level_bits;
135
136 /*
137 * Now, make all PCI interrupts level sensitive. Notice:
138 * these registers must be accessed byte-wise. inw()/outw()
139 * don't work.
140 *
141 * Make sure to turn off any level bits set for IRQs 9,10,11,15,
142 * so that the only bits getting set are for devices actually found.
143 * Note that we do preserve the remainder of the bits, which we hope
144 * will be set correctly by ARC/SRM.
145 *
146 * Note: we at least preserve any level-set bits on AlphaBook1
147 */
148 old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
149
150 if (reset)
151 old_level_bits &= 0x71ff;
152
153 level_bits |= old_level_bits;
154
155 outb((level_bits >> 0) & 0xff, 0x4d0);
156 outb((level_bits >> 8) & 0xff, 0x4d1);
157}
158
159static inline void
160sio_fixup_irq_levels(unsigned int level_bits)
161{
162 __sio_fixup_irq_levels(level_bits, true);
163}
164
165static inline int
166noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
167{
168 /*
169 * The Noname board has 5 PCI slots with each of the 4
170 * interrupt pins routed to different pins on the PCI/ISA
171 * bridge (PIRQ0-PIRQ3). The table below is based on
172 * information available at:
173 *
174 * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
175 *
176 * I have no information on the Avanti interrupt routing, but
177 * the routing seems to be identical to the Noname except
178 * that the Avanti has an additional slot whose routing I'm
179 * unsure of.
180 *
181 * pirq_tab[0] is a fake entry to deal with old PCI boards
182 * that have the interrupt pin number hardwired to 0 (meaning
183 * that they use the default INTA line, if they are interrupt
184 * driven at all).
185 */
186 static char irq_tab[][5] = {
187 /*INT A B C D */
188 { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
189 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
190 { 2, 2, -1, -1, -1}, /* idsel 8 (Hack: slot closest ISA) */
191 {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
192 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
193 { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
194 { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
195 { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
196 { 0, 0, 0, 0, 0}, /* idsel 14 AS255 TULIP */
197 };
198 const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
199 int irq = COMMON_TABLE_LOOKUP, tmp;
200 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
201
202 irq = irq >= 0 ? tmp : -1;
203
204 /* Fixup IRQ level if an actual IRQ mapping is detected */
205 if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
206 __sio_fixup_irq_levels(1 << irq, false);
207
208 return irq;
209}
210
211static inline int
212p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
213{
214 static char irq_tab[][5] = {
215 /*INT A B C D */
216 { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
217 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
218 { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
219 { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
220 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
221 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
222 { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
223 };
224 const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
225 int irq = COMMON_TABLE_LOOKUP, tmp;
226 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
227 return irq >= 0 ? tmp : -1;
228}
229
230static inline void __init
231noname_init_pci(void)
232{
233 common_init_pci();
234 sio_pci_route();
235 sio_fixup_irq_levels(sio_collect_irq_levels());
236
237 if (pc873xx_probe() == -1) {
238 printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
239 } else {
240 printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
241 pc873xx_get_model(), pc873xx_get_base());
242
243 /* Enabling things in the Super IO chip doesn't actually
244 * configure and enable things, the legacy drivers still
245 * need to do the actual configuration and enabling.
246 * This only unblocks them.
247 */
248
249#if !defined(CONFIG_ALPHA_AVANTI)
250 /* Don't bother on the Avanti family.
251 * None of them had on-board IDE.
252 */
253 pc873xx_enable_ide();
254#endif
255 pc873xx_enable_epp19();
256 }
257}
258
259static inline void __init
260alphabook1_init_pci(void)
261{
262 struct pci_dev *dev;
263 unsigned char orig, config;
264
265 common_init_pci();
266 sio_pci_route();
267
268 /*
269 * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
270 * is sensitive to PCI bus bursts, so we must DISABLE
271 * burst mode for the NCR 8xx SCSI... :-(
272 *
273 * Note that the NCR810 SCSI driver must preserve the
274 * setting of the bit in order for this to work. At the
275 * moment (2.0.29), ncr53c8xx.c does NOT do this, but
276 * 53c7,8xx.c DOES.
277 */
278
279 dev = NULL;
280 while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
281 if (dev->device == PCI_DEVICE_ID_NCR_53C810
282 || dev->device == PCI_DEVICE_ID_NCR_53C815
283 || dev->device == PCI_DEVICE_ID_NCR_53C820
284 || dev->device == PCI_DEVICE_ID_NCR_53C825) {
285 unsigned long io_port;
286 unsigned char ctest4;
287
288 io_port = dev->resource[0].start;
289 ctest4 = inb(io_port+0x21);
290 if (!(ctest4 & 0x80)) {
291 printk("AlphaBook1 NCR init: setting"
292 " burst disable\n");
293 outb(ctest4 | 0x80, io_port+0x21);
294 }
295 }
296 }
297
298 /* Do not set *ANY* level triggers for AlphaBook1. */
299 sio_fixup_irq_levels(0);
300
301 /* Make sure that register PR1 indicates 1Mb mem */
302 outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */
303 outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */
304 outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
305 if ((config & 0xc0) != 0xc0) {
306 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
307 config |= 0xc0;
308 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
309 }
310 outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
311}
312
313void
314sio_kill_arch(int mode)
315{
316#if defined(ALPHA_RESTORE_SRM_SETUP)
317 /* Since we cannot read the PCI DMA Window CSRs, we
318 * cannot restore them here.
319 *
320 * However, we CAN read the PIRQ route register, so restore it
321 * now...
322 */
323 pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
324 saved_config.orig_route_tab);
325#endif
326}
327
328
329/*
330 * The System Vectors
331 */
332
333#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
334struct alpha_machine_vector alphabook1_mv __initmv = {
335 .vector_name = "AlphaBook1",
336 DO_EV4_MMU,
337 DO_DEFAULT_RTC,
338 DO_LCA_IO,
339 .machine_check = lca_machine_check,
340 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
341 .min_io_address = DEFAULT_IO_BASE,
342 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
343
344 .nr_irqs = 16,
345 .device_interrupt = isa_device_interrupt,
346
347 .init_arch = alphabook1_init_arch,
348 .init_irq = sio_init_irq,
349 .init_rtc = common_init_rtc,
350 .init_pci = alphabook1_init_pci,
351 .kill_arch = sio_kill_arch,
352 .pci_map_irq = noname_map_irq,
353 .pci_swizzle = common_swizzle,
354
355 .sys = { .sio = {
356 /* NCR810 SCSI is 14, PCMCIA controller is 15. */
357 .route_tab = 0x0e0f0a0a,
358 }}
359};
360ALIAS_MV(alphabook1)
361#endif
362
363#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
364struct alpha_machine_vector avanti_mv __initmv = {
365 .vector_name = "Avanti",
366 DO_EV4_MMU,
367 DO_DEFAULT_RTC,
368 DO_APECS_IO,
369 .machine_check = apecs_machine_check,
370 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
371 .min_io_address = DEFAULT_IO_BASE,
372 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
373
374 .nr_irqs = 16,
375 .device_interrupt = isa_device_interrupt,
376
377 .init_arch = apecs_init_arch,
378 .init_irq = sio_init_irq,
379 .init_rtc = common_init_rtc,
380 .init_pci = noname_init_pci,
381 .kill_arch = sio_kill_arch,
382 .pci_map_irq = noname_map_irq,
383 .pci_swizzle = common_swizzle,
384
385 .sys = { .sio = {
386 .route_tab = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */
387 }}
388};
389ALIAS_MV(avanti)
390#endif
391
392#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
393struct alpha_machine_vector noname_mv __initmv = {
394 .vector_name = "Noname",
395 DO_EV4_MMU,
396 DO_DEFAULT_RTC,
397 DO_LCA_IO,
398 .machine_check = lca_machine_check,
399 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
400 .min_io_address = DEFAULT_IO_BASE,
401 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
402
403 .nr_irqs = 16,
404 .device_interrupt = srm_device_interrupt,
405
406 .init_arch = lca_init_arch,
407 .init_irq = sio_init_irq,
408 .init_rtc = common_init_rtc,
409 .init_pci = noname_init_pci,
410 .kill_arch = sio_kill_arch,
411 .pci_map_irq = noname_map_irq,
412 .pci_swizzle = common_swizzle,
413
414 .sys = { .sio = {
415 /* For UDB, the only available PCI slot must not map to IRQ 9,
416 since that's the builtin MSS sound chip. That PCI slot
417 will map to PIRQ1 (for INTA at least), so we give it IRQ 15
418 instead.
419
420 Unfortunately we have to do this for NONAME as well, since
421 they are co-indicated when the platform type "Noname" is
422 selected... :-( */
423
424 .route_tab = 0x0b0a0f0d,
425 }}
426};
427ALIAS_MV(noname)
428#endif
429
430#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
431struct alpha_machine_vector p2k_mv __initmv = {
432 .vector_name = "Platform2000",
433 DO_EV4_MMU,
434 DO_DEFAULT_RTC,
435 DO_LCA_IO,
436 .machine_check = lca_machine_check,
437 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
438 .min_io_address = DEFAULT_IO_BASE,
439 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
440
441 .nr_irqs = 16,
442 .device_interrupt = srm_device_interrupt,
443
444 .init_arch = lca_init_arch,
445 .init_irq = sio_init_irq,
446 .init_rtc = common_init_rtc,
447 .init_pci = noname_init_pci,
448 .kill_arch = sio_kill_arch,
449 .pci_map_irq = p2k_map_irq,
450 .pci_swizzle = common_swizzle,
451
452 .sys = { .sio = {
453 .route_tab = 0x0b0a090f,
454 }}
455};
456ALIAS_MV(p2k)
457#endif
458
459#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
460struct alpha_machine_vector xl_mv __initmv = {
461 .vector_name = "XL",
462 DO_EV4_MMU,
463 DO_DEFAULT_RTC,
464 DO_APECS_IO,
465 .machine_check = apecs_machine_check,
466 .max_isa_dma_address = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
467 .min_io_address = DEFAULT_IO_BASE,
468 .min_mem_address = XL_DEFAULT_MEM_BASE,
469
470 .nr_irqs = 16,
471 .device_interrupt = isa_device_interrupt,
472
473 .init_arch = apecs_init_arch,
474 .init_irq = sio_init_irq,
475 .init_rtc = common_init_rtc,
476 .init_pci = noname_init_pci,
477 .kill_arch = sio_kill_arch,
478 .pci_map_irq = noname_map_irq,
479 .pci_swizzle = common_swizzle,
480
481 .sys = { .sio = {
482 .route_tab = 0x0b0a090f,
483 }}
484};
485ALIAS_MV(xl)
486#endif
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * linux/arch/alpha/kernel/sys_sio.c
4 *
5 * Copyright (C) 1995 David A Rusling
6 * Copyright (C) 1996 Jay A Estabrook
7 * Copyright (C) 1998, 1999 Richard Henderson
8 *
9 * Code for all boards that route the PCI interrupts through the SIO
10 * PCI/ISA bridge. This includes Noname (AXPpci33), Multia (UDB),
11 * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/screen_info.h>
21
22#include <asm/compiler.h>
23#include <asm/ptrace.h>
24#include <asm/dma.h>
25#include <asm/irq.h>
26#include <asm/mmu_context.h>
27#include <asm/io.h>
28#include <asm/pgtable.h>
29#include <asm/core_apecs.h>
30#include <asm/core_lca.h>
31#include <asm/tlbflush.h>
32
33#include "proto.h"
34#include "irq_impl.h"
35#include "pci_impl.h"
36#include "machvec_impl.h"
37#include "pc873xx.h"
38
39#if defined(ALPHA_RESTORE_SRM_SETUP)
40/* Save LCA configuration data as the console had it set up. */
41struct
42{
43 unsigned int orig_route_tab; /* for SAVE/RESTORE */
44} saved_config __attribute((common));
45#endif
46
47
48static void __init
49sio_init_irq(void)
50{
51 if (alpha_using_srm)
52 alpha_mv.device_interrupt = srm_device_interrupt;
53
54 init_i8259a_irqs();
55 common_init_isa_dma();
56}
57
58static inline void __init
59alphabook1_init_arch(void)
60{
61 /* The AlphaBook1 has LCD video fixed at 800x600,
62 37 rows and 100 cols. */
63 screen_info.orig_y = 37;
64 screen_info.orig_video_cols = 100;
65 screen_info.orig_video_lines = 37;
66
67 lca_init_arch();
68}
69
70
71/*
72 * sio_route_tab selects irq routing in PCI/ISA bridge so that:
73 * PIRQ0 -> irq 15
74 * PIRQ1 -> irq 9
75 * PIRQ2 -> irq 10
76 * PIRQ3 -> irq 11
77 *
78 * This probably ought to be configurable via MILO. For
79 * example, sound boards seem to like using IRQ 9.
80 *
81 * This is NOT how we should do it. PIRQ0-X should have
82 * their own IRQs, the way intel uses the IO-APIC IRQs.
83 */
84
85static void __init
86sio_pci_route(void)
87{
88 unsigned int orig_route_tab;
89
90 /* First, ALWAYS read and print the original setting. */
91 pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
92 &orig_route_tab);
93 printk("%s: PIRQ original 0x%x new 0x%x\n", __func__,
94 orig_route_tab, alpha_mv.sys.sio.route_tab);
95
96#if defined(ALPHA_RESTORE_SRM_SETUP)
97 saved_config.orig_route_tab = orig_route_tab;
98#endif
99
100 /* Now override with desired setting. */
101 pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
102 alpha_mv.sys.sio.route_tab);
103}
104
105static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
106{
107 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
108 (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
109 return false;
110
111 return true;
112}
113
114static unsigned int __init
115sio_collect_irq_levels(void)
116{
117 unsigned int level_bits = 0;
118 struct pci_dev *dev = NULL;
119
120 /* Iterate through the devices, collecting IRQ levels. */
121 for_each_pci_dev(dev) {
122 if (!sio_pci_dev_irq_needs_level(dev))
123 continue;
124
125 if (dev->irq)
126 level_bits |= (1 << dev->irq);
127 }
128 return level_bits;
129}
130
131static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
132{
133 unsigned int old_level_bits;
134
135 /*
136 * Now, make all PCI interrupts level sensitive. Notice:
137 * these registers must be accessed byte-wise. inw()/outw()
138 * don't work.
139 *
140 * Make sure to turn off any level bits set for IRQs 9,10,11,15,
141 * so that the only bits getting set are for devices actually found.
142 * Note that we do preserve the remainder of the bits, which we hope
143 * will be set correctly by ARC/SRM.
144 *
145 * Note: we at least preserve any level-set bits on AlphaBook1
146 */
147 old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
148
149 if (reset)
150 old_level_bits &= 0x71ff;
151
152 level_bits |= old_level_bits;
153
154 outb((level_bits >> 0) & 0xff, 0x4d0);
155 outb((level_bits >> 8) & 0xff, 0x4d1);
156}
157
158static inline void
159sio_fixup_irq_levels(unsigned int level_bits)
160{
161 __sio_fixup_irq_levels(level_bits, true);
162}
163
164static inline int
165noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
166{
167 /*
168 * The Noname board has 5 PCI slots with each of the 4
169 * interrupt pins routed to different pins on the PCI/ISA
170 * bridge (PIRQ0-PIRQ3). The table below is based on
171 * information available at:
172 *
173 * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
174 *
175 * I have no information on the Avanti interrupt routing, but
176 * the routing seems to be identical to the Noname except
177 * that the Avanti has an additional slot whose routing I'm
178 * unsure of.
179 *
180 * pirq_tab[0] is a fake entry to deal with old PCI boards
181 * that have the interrupt pin number hardwired to 0 (meaning
182 * that they use the default INTA line, if they are interrupt
183 * driven at all).
184 */
185 static char irq_tab[][5] = {
186 /*INT A B C D */
187 { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
188 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
189 { 2, 2, -1, -1, -1}, /* idsel 8 (Hack: slot closest ISA) */
190 {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
191 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
192 { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
193 { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
194 { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
195 { 0, 0, 0, 0, 0}, /* idsel 14 AS255 TULIP */
196 };
197 const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
198 int irq = COMMON_TABLE_LOOKUP, tmp;
199 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
200
201 irq = irq >= 0 ? tmp : -1;
202
203 /* Fixup IRQ level if an actual IRQ mapping is detected */
204 if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
205 __sio_fixup_irq_levels(1 << irq, false);
206
207 return irq;
208}
209
210static inline int
211p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
212{
213 static char irq_tab[][5] = {
214 /*INT A B C D */
215 { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
216 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
217 { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
218 { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
219 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
220 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
221 { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
222 };
223 const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
224 int irq = COMMON_TABLE_LOOKUP, tmp;
225 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
226 return irq >= 0 ? tmp : -1;
227}
228
229static inline void __init
230noname_init_pci(void)
231{
232 common_init_pci();
233 sio_pci_route();
234 sio_fixup_irq_levels(sio_collect_irq_levels());
235
236 if (pc873xx_probe() == -1) {
237 printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
238 } else {
239 printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
240 pc873xx_get_model(), pc873xx_get_base());
241
242 /* Enabling things in the Super IO chip doesn't actually
243 * configure and enable things, the legacy drivers still
244 * need to do the actual configuration and enabling.
245 * This only unblocks them.
246 */
247
248#if !defined(CONFIG_ALPHA_AVANTI)
249 /* Don't bother on the Avanti family.
250 * None of them had on-board IDE.
251 */
252 pc873xx_enable_ide();
253#endif
254 pc873xx_enable_epp19();
255 }
256}
257
258static inline void __init
259alphabook1_init_pci(void)
260{
261 struct pci_dev *dev;
262 unsigned char orig, config;
263
264 common_init_pci();
265 sio_pci_route();
266
267 /*
268 * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
269 * is sensitive to PCI bus bursts, so we must DISABLE
270 * burst mode for the NCR 8xx SCSI... :-(
271 *
272 * Note that the NCR810 SCSI driver must preserve the
273 * setting of the bit in order for this to work. At the
274 * moment (2.0.29), ncr53c8xx.c does NOT do this, but
275 * 53c7,8xx.c DOES.
276 */
277
278 dev = NULL;
279 while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
280 if (dev->device == PCI_DEVICE_ID_NCR_53C810
281 || dev->device == PCI_DEVICE_ID_NCR_53C815
282 || dev->device == PCI_DEVICE_ID_NCR_53C820
283 || dev->device == PCI_DEVICE_ID_NCR_53C825) {
284 unsigned long io_port;
285 unsigned char ctest4;
286
287 io_port = dev->resource[0].start;
288 ctest4 = inb(io_port+0x21);
289 if (!(ctest4 & 0x80)) {
290 printk("AlphaBook1 NCR init: setting"
291 " burst disable\n");
292 outb(ctest4 | 0x80, io_port+0x21);
293 }
294 }
295 }
296
297 /* Do not set *ANY* level triggers for AlphaBook1. */
298 sio_fixup_irq_levels(0);
299
300 /* Make sure that register PR1 indicates 1Mb mem */
301 outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */
302 outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */
303 outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
304 if ((config & 0xc0) != 0xc0) {
305 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
306 config |= 0xc0;
307 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
308 }
309 outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
310}
311
312void
313sio_kill_arch(int mode)
314{
315#if defined(ALPHA_RESTORE_SRM_SETUP)
316 /* Since we cannot read the PCI DMA Window CSRs, we
317 * cannot restore them here.
318 *
319 * However, we CAN read the PIRQ route register, so restore it
320 * now...
321 */
322 pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
323 saved_config.orig_route_tab);
324#endif
325}
326
327
328/*
329 * The System Vectors
330 */
331
332#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
333struct alpha_machine_vector alphabook1_mv __initmv = {
334 .vector_name = "AlphaBook1",
335 DO_EV4_MMU,
336 DO_DEFAULT_RTC,
337 DO_LCA_IO,
338 .machine_check = lca_machine_check,
339 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
340 .min_io_address = DEFAULT_IO_BASE,
341 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
342
343 .nr_irqs = 16,
344 .device_interrupt = isa_device_interrupt,
345
346 .init_arch = alphabook1_init_arch,
347 .init_irq = sio_init_irq,
348 .init_rtc = common_init_rtc,
349 .init_pci = alphabook1_init_pci,
350 .kill_arch = sio_kill_arch,
351 .pci_map_irq = noname_map_irq,
352 .pci_swizzle = common_swizzle,
353
354 .sys = { .sio = {
355 /* NCR810 SCSI is 14, PCMCIA controller is 15. */
356 .route_tab = 0x0e0f0a0a,
357 }}
358};
359ALIAS_MV(alphabook1)
360#endif
361
362#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
363struct alpha_machine_vector avanti_mv __initmv = {
364 .vector_name = "Avanti",
365 DO_EV4_MMU,
366 DO_DEFAULT_RTC,
367 DO_APECS_IO,
368 .machine_check = apecs_machine_check,
369 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
370 .min_io_address = DEFAULT_IO_BASE,
371 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
372
373 .nr_irqs = 16,
374 .device_interrupt = isa_device_interrupt,
375
376 .init_arch = apecs_init_arch,
377 .init_irq = sio_init_irq,
378 .init_rtc = common_init_rtc,
379 .init_pci = noname_init_pci,
380 .kill_arch = sio_kill_arch,
381 .pci_map_irq = noname_map_irq,
382 .pci_swizzle = common_swizzle,
383
384 .sys = { .sio = {
385 .route_tab = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */
386 }}
387};
388ALIAS_MV(avanti)
389#endif
390
391#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
392struct alpha_machine_vector noname_mv __initmv = {
393 .vector_name = "Noname",
394 DO_EV4_MMU,
395 DO_DEFAULT_RTC,
396 DO_LCA_IO,
397 .machine_check = lca_machine_check,
398 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
399 .min_io_address = DEFAULT_IO_BASE,
400 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
401
402 .nr_irqs = 16,
403 .device_interrupt = srm_device_interrupt,
404
405 .init_arch = lca_init_arch,
406 .init_irq = sio_init_irq,
407 .init_rtc = common_init_rtc,
408 .init_pci = noname_init_pci,
409 .kill_arch = sio_kill_arch,
410 .pci_map_irq = noname_map_irq,
411 .pci_swizzle = common_swizzle,
412
413 .sys = { .sio = {
414 /* For UDB, the only available PCI slot must not map to IRQ 9,
415 since that's the builtin MSS sound chip. That PCI slot
416 will map to PIRQ1 (for INTA at least), so we give it IRQ 15
417 instead.
418
419 Unfortunately we have to do this for NONAME as well, since
420 they are co-indicated when the platform type "Noname" is
421 selected... :-( */
422
423 .route_tab = 0x0b0a0f0d,
424 }}
425};
426ALIAS_MV(noname)
427#endif
428
429#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
430struct alpha_machine_vector p2k_mv __initmv = {
431 .vector_name = "Platform2000",
432 DO_EV4_MMU,
433 DO_DEFAULT_RTC,
434 DO_LCA_IO,
435 .machine_check = lca_machine_check,
436 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
437 .min_io_address = DEFAULT_IO_BASE,
438 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
439
440 .nr_irqs = 16,
441 .device_interrupt = srm_device_interrupt,
442
443 .init_arch = lca_init_arch,
444 .init_irq = sio_init_irq,
445 .init_rtc = common_init_rtc,
446 .init_pci = noname_init_pci,
447 .kill_arch = sio_kill_arch,
448 .pci_map_irq = p2k_map_irq,
449 .pci_swizzle = common_swizzle,
450
451 .sys = { .sio = {
452 .route_tab = 0x0b0a090f,
453 }}
454};
455ALIAS_MV(p2k)
456#endif
457
458#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
459struct alpha_machine_vector xl_mv __initmv = {
460 .vector_name = "XL",
461 DO_EV4_MMU,
462 DO_DEFAULT_RTC,
463 DO_APECS_IO,
464 .machine_check = apecs_machine_check,
465 .max_isa_dma_address = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
466 .min_io_address = DEFAULT_IO_BASE,
467 .min_mem_address = XL_DEFAULT_MEM_BASE,
468
469 .nr_irqs = 16,
470 .device_interrupt = isa_device_interrupt,
471
472 .init_arch = apecs_init_arch,
473 .init_irq = sio_init_irq,
474 .init_rtc = common_init_rtc,
475 .init_pci = noname_init_pci,
476 .kill_arch = sio_kill_arch,
477 .pci_map_irq = noname_map_irq,
478 .pci_swizzle = common_swizzle,
479
480 .sys = { .sio = {
481 .route_tab = 0x0b0a090f,
482 }}
483};
484ALIAS_MV(xl)
485#endif