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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * linux/arch/alpha/kernel/sys_sio.c
4 *
5 * Copyright (C) 1995 David A Rusling
6 * Copyright (C) 1996 Jay A Estabrook
7 * Copyright (C) 1998, 1999 Richard Henderson
8 *
9 * Code for all boards that route the PCI interrupts through the SIO
10 * PCI/ISA bridge. This includes Noname (AXPpci33), Multia (UDB),
11 * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
12 */
13
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/mm.h>
17#include <linux/sched.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/screen_info.h>
21
22#include <asm/compiler.h>
23#include <asm/ptrace.h>
24#include <asm/dma.h>
25#include <asm/irq.h>
26#include <asm/mmu_context.h>
27#include <asm/io.h>
28#include <asm/core_apecs.h>
29#include <asm/core_lca.h>
30#include <asm/tlbflush.h>
31
32#include "proto.h"
33#include "irq_impl.h"
34#include "pci_impl.h"
35#include "machvec_impl.h"
36#include "pc873xx.h"
37
38#if defined(ALPHA_RESTORE_SRM_SETUP)
39/* Save LCA configuration data as the console had it set up. */
40struct
41{
42 unsigned int orig_route_tab; /* for SAVE/RESTORE */
43} saved_config __attribute((common));
44#endif
45
46
47static void __init
48sio_init_irq(void)
49{
50 if (alpha_using_srm)
51 alpha_mv.device_interrupt = srm_device_interrupt;
52
53 init_i8259a_irqs();
54 common_init_isa_dma();
55}
56
57static inline void __init
58alphabook1_init_arch(void)
59{
60#ifdef CONFIG_VGA_CONSOLE
61 /* The AlphaBook1 has LCD video fixed at 800x600,
62 37 rows and 100 cols. */
63 vgacon_screen_info.orig_y = 37;
64 vgacon_screen_info.orig_video_cols = 100;
65 vgacon_screen_info.orig_video_lines = 37;
66#endif
67
68 lca_init_arch();
69}
70
71
72/*
73 * sio_route_tab selects irq routing in PCI/ISA bridge so that:
74 * PIRQ0 -> irq 15
75 * PIRQ1 -> irq 9
76 * PIRQ2 -> irq 10
77 * PIRQ3 -> irq 11
78 *
79 * This probably ought to be configurable via MILO. For
80 * example, sound boards seem to like using IRQ 9.
81 *
82 * This is NOT how we should do it. PIRQ0-X should have
83 * their own IRQs, the way intel uses the IO-APIC IRQs.
84 */
85
86static void __init
87sio_pci_route(void)
88{
89 unsigned int orig_route_tab;
90
91 /* First, ALWAYS read and print the original setting. */
92 pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
93 &orig_route_tab);
94 printk("%s: PIRQ original 0x%x new 0x%x\n", __func__,
95 orig_route_tab, alpha_mv.sys.sio.route_tab);
96
97#if defined(ALPHA_RESTORE_SRM_SETUP)
98 saved_config.orig_route_tab = orig_route_tab;
99#endif
100
101 /* Now override with desired setting. */
102 pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
103 alpha_mv.sys.sio.route_tab);
104}
105
106static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
107{
108 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
109 (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
110 return false;
111
112 return true;
113}
114
115static unsigned int __init
116sio_collect_irq_levels(void)
117{
118 unsigned int level_bits = 0;
119 struct pci_dev *dev = NULL;
120
121 /* Iterate through the devices, collecting IRQ levels. */
122 for_each_pci_dev(dev) {
123 if (!sio_pci_dev_irq_needs_level(dev))
124 continue;
125
126 if (dev->irq)
127 level_bits |= (1 << dev->irq);
128 }
129 return level_bits;
130}
131
132static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
133{
134 unsigned int old_level_bits;
135
136 /*
137 * Now, make all PCI interrupts level sensitive. Notice:
138 * these registers must be accessed byte-wise. inw()/outw()
139 * don't work.
140 *
141 * Make sure to turn off any level bits set for IRQs 9,10,11,15,
142 * so that the only bits getting set are for devices actually found.
143 * Note that we do preserve the remainder of the bits, which we hope
144 * will be set correctly by ARC/SRM.
145 *
146 * Note: we at least preserve any level-set bits on AlphaBook1
147 */
148 old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
149
150 if (reset)
151 old_level_bits &= 0x71ff;
152
153 level_bits |= old_level_bits;
154
155 outb((level_bits >> 0) & 0xff, 0x4d0);
156 outb((level_bits >> 8) & 0xff, 0x4d1);
157}
158
159static inline void
160sio_fixup_irq_levels(unsigned int level_bits)
161{
162 __sio_fixup_irq_levels(level_bits, true);
163}
164
165static inline int
166noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
167{
168 /*
169 * The Noname board has 5 PCI slots with each of the 4
170 * interrupt pins routed to different pins on the PCI/ISA
171 * bridge (PIRQ0-PIRQ3). The table below is based on
172 * information available at:
173 *
174 * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
175 *
176 * I have no information on the Avanti interrupt routing, but
177 * the routing seems to be identical to the Noname except
178 * that the Avanti has an additional slot whose routing I'm
179 * unsure of.
180 *
181 * pirq_tab[0] is a fake entry to deal with old PCI boards
182 * that have the interrupt pin number hardwired to 0 (meaning
183 * that they use the default INTA line, if they are interrupt
184 * driven at all).
185 */
186 static char irq_tab[][5] = {
187 /*INT A B C D */
188 { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
189 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
190 { 2, 2, -1, -1, -1}, /* idsel 8 (Hack: slot closest ISA) */
191 {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
192 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
193 { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
194 { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
195 { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
196 { 0, 0, 0, 0, 0}, /* idsel 14 AS255 TULIP */
197 };
198 const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
199 int irq = COMMON_TABLE_LOOKUP, tmp;
200 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
201
202 irq = irq >= 0 ? tmp : -1;
203
204 /* Fixup IRQ level if an actual IRQ mapping is detected */
205 if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
206 __sio_fixup_irq_levels(1 << irq, false);
207
208 return irq;
209}
210
211static inline int
212p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
213{
214 static char irq_tab[][5] = {
215 /*INT A B C D */
216 { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
217 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
218 { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
219 { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
220 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
221 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
222 { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
223 };
224 const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
225 int irq = COMMON_TABLE_LOOKUP, tmp;
226 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
227 return irq >= 0 ? tmp : -1;
228}
229
230static inline void __init
231noname_init_pci(void)
232{
233 common_init_pci();
234 sio_pci_route();
235 sio_fixup_irq_levels(sio_collect_irq_levels());
236
237 if (pc873xx_probe() == -1) {
238 printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
239 } else {
240 printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
241 pc873xx_get_model(), pc873xx_get_base());
242
243 /* Enabling things in the Super IO chip doesn't actually
244 * configure and enable things, the legacy drivers still
245 * need to do the actual configuration and enabling.
246 * This only unblocks them.
247 */
248
249#if !defined(CONFIG_ALPHA_AVANTI)
250 /* Don't bother on the Avanti family.
251 * None of them had on-board IDE.
252 */
253 pc873xx_enable_ide();
254#endif
255 pc873xx_enable_epp19();
256 }
257}
258
259static inline void __init
260alphabook1_init_pci(void)
261{
262 struct pci_dev *dev;
263 unsigned char orig, config;
264
265 common_init_pci();
266 sio_pci_route();
267
268 /*
269 * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
270 * is sensitive to PCI bus bursts, so we must DISABLE
271 * burst mode for the NCR 8xx SCSI... :-(
272 *
273 * Note that the NCR810 SCSI driver must preserve the
274 * setting of the bit in order for this to work. At the
275 * moment (2.0.29), ncr53c8xx.c does NOT do this, but
276 * 53c7,8xx.c DOES.
277 */
278
279 dev = NULL;
280 while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
281 if (dev->device == PCI_DEVICE_ID_NCR_53C810
282 || dev->device == PCI_DEVICE_ID_NCR_53C815
283 || dev->device == PCI_DEVICE_ID_NCR_53C820
284 || dev->device == PCI_DEVICE_ID_NCR_53C825) {
285 unsigned long io_port;
286 unsigned char ctest4;
287
288 io_port = dev->resource[0].start;
289 ctest4 = inb(io_port+0x21);
290 if (!(ctest4 & 0x80)) {
291 printk("AlphaBook1 NCR init: setting"
292 " burst disable\n");
293 outb(ctest4 | 0x80, io_port+0x21);
294 }
295 }
296 }
297
298 /* Do not set *ANY* level triggers for AlphaBook1. */
299 sio_fixup_irq_levels(0);
300
301 /* Make sure that register PR1 indicates 1Mb mem */
302 outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */
303 outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */
304 outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
305 if ((config & 0xc0) != 0xc0) {
306 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
307 config |= 0xc0;
308 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
309 }
310 outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
311}
312
313void
314sio_kill_arch(int mode)
315{
316#if defined(ALPHA_RESTORE_SRM_SETUP)
317 /* Since we cannot read the PCI DMA Window CSRs, we
318 * cannot restore them here.
319 *
320 * However, we CAN read the PIRQ route register, so restore it
321 * now...
322 */
323 pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
324 saved_config.orig_route_tab);
325#endif
326}
327
328
329/*
330 * The System Vectors
331 */
332
333#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
334struct alpha_machine_vector alphabook1_mv __initmv = {
335 .vector_name = "AlphaBook1",
336 DO_EV4_MMU,
337 DO_DEFAULT_RTC,
338 DO_LCA_IO,
339 .machine_check = lca_machine_check,
340 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
341 .min_io_address = DEFAULT_IO_BASE,
342 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
343
344 .nr_irqs = 16,
345 .device_interrupt = isa_device_interrupt,
346
347 .init_arch = alphabook1_init_arch,
348 .init_irq = sio_init_irq,
349 .init_rtc = common_init_rtc,
350 .init_pci = alphabook1_init_pci,
351 .kill_arch = sio_kill_arch,
352 .pci_map_irq = noname_map_irq,
353 .pci_swizzle = common_swizzle,
354
355 .sys = { .sio = {
356 /* NCR810 SCSI is 14, PCMCIA controller is 15. */
357 .route_tab = 0x0e0f0a0a,
358 }}
359};
360ALIAS_MV(alphabook1)
361#endif
362
363#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
364struct alpha_machine_vector avanti_mv __initmv = {
365 .vector_name = "Avanti",
366 DO_EV4_MMU,
367 DO_DEFAULT_RTC,
368 DO_APECS_IO,
369 .machine_check = apecs_machine_check,
370 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
371 .min_io_address = DEFAULT_IO_BASE,
372 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
373
374 .nr_irqs = 16,
375 .device_interrupt = isa_device_interrupt,
376
377 .init_arch = apecs_init_arch,
378 .init_irq = sio_init_irq,
379 .init_rtc = common_init_rtc,
380 .init_pci = noname_init_pci,
381 .kill_arch = sio_kill_arch,
382 .pci_map_irq = noname_map_irq,
383 .pci_swizzle = common_swizzle,
384
385 .sys = { .sio = {
386 .route_tab = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */
387 }}
388};
389ALIAS_MV(avanti)
390#endif
391
392#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
393struct alpha_machine_vector noname_mv __initmv = {
394 .vector_name = "Noname",
395 DO_EV4_MMU,
396 DO_DEFAULT_RTC,
397 DO_LCA_IO,
398 .machine_check = lca_machine_check,
399 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
400 .min_io_address = DEFAULT_IO_BASE,
401 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
402
403 .nr_irqs = 16,
404 .device_interrupt = srm_device_interrupt,
405
406 .init_arch = lca_init_arch,
407 .init_irq = sio_init_irq,
408 .init_rtc = common_init_rtc,
409 .init_pci = noname_init_pci,
410 .kill_arch = sio_kill_arch,
411 .pci_map_irq = noname_map_irq,
412 .pci_swizzle = common_swizzle,
413
414 .sys = { .sio = {
415 /* For UDB, the only available PCI slot must not map to IRQ 9,
416 since that's the builtin MSS sound chip. That PCI slot
417 will map to PIRQ1 (for INTA at least), so we give it IRQ 15
418 instead.
419
420 Unfortunately we have to do this for NONAME as well, since
421 they are co-indicated when the platform type "Noname" is
422 selected... :-( */
423
424 .route_tab = 0x0b0a0f0d,
425 }}
426};
427ALIAS_MV(noname)
428#endif
429
430#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
431struct alpha_machine_vector p2k_mv __initmv = {
432 .vector_name = "Platform2000",
433 DO_EV4_MMU,
434 DO_DEFAULT_RTC,
435 DO_LCA_IO,
436 .machine_check = lca_machine_check,
437 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
438 .min_io_address = DEFAULT_IO_BASE,
439 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
440
441 .nr_irqs = 16,
442 .device_interrupt = srm_device_interrupt,
443
444 .init_arch = lca_init_arch,
445 .init_irq = sio_init_irq,
446 .init_rtc = common_init_rtc,
447 .init_pci = noname_init_pci,
448 .kill_arch = sio_kill_arch,
449 .pci_map_irq = p2k_map_irq,
450 .pci_swizzle = common_swizzle,
451
452 .sys = { .sio = {
453 .route_tab = 0x0b0a090f,
454 }}
455};
456ALIAS_MV(p2k)
457#endif
458
459#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
460struct alpha_machine_vector xl_mv __initmv = {
461 .vector_name = "XL",
462 DO_EV4_MMU,
463 DO_DEFAULT_RTC,
464 DO_APECS_IO,
465 .machine_check = apecs_machine_check,
466 .max_isa_dma_address = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
467 .min_io_address = DEFAULT_IO_BASE,
468 .min_mem_address = XL_DEFAULT_MEM_BASE,
469
470 .nr_irqs = 16,
471 .device_interrupt = isa_device_interrupt,
472
473 .init_arch = apecs_init_arch,
474 .init_irq = sio_init_irq,
475 .init_rtc = common_init_rtc,
476 .init_pci = noname_init_pci,
477 .kill_arch = sio_kill_arch,
478 .pci_map_irq = noname_map_irq,
479 .pci_swizzle = common_swizzle,
480
481 .sys = { .sio = {
482 .route_tab = 0x0b0a090f,
483 }}
484};
485ALIAS_MV(xl)
486#endif
1/*
2 * linux/arch/alpha/kernel/sys_sio.c
3 *
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
7 *
8 * Code for all boards that route the PCI interrupts through the SIO
9 * PCI/ISA bridge. This includes Noname (AXPpci33), Multia (UDB),
10 * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/mm.h>
16#include <linux/sched.h>
17#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/screen_info.h>
20
21#include <asm/compiler.h>
22#include <asm/ptrace.h>
23#include <asm/system.h>
24#include <asm/dma.h>
25#include <asm/irq.h>
26#include <asm/mmu_context.h>
27#include <asm/io.h>
28#include <asm/pgtable.h>
29#include <asm/core_apecs.h>
30#include <asm/core_lca.h>
31#include <asm/tlbflush.h>
32
33#include "proto.h"
34#include "irq_impl.h"
35#include "pci_impl.h"
36#include "machvec_impl.h"
37#include "pc873xx.h"
38
39#if defined(ALPHA_RESTORE_SRM_SETUP)
40/* Save LCA configuration data as the console had it set up. */
41struct
42{
43 unsigned int orig_route_tab; /* for SAVE/RESTORE */
44} saved_config __attribute((common));
45#endif
46
47
48static void __init
49sio_init_irq(void)
50{
51 if (alpha_using_srm)
52 alpha_mv.device_interrupt = srm_device_interrupt;
53
54 init_i8259a_irqs();
55 common_init_isa_dma();
56}
57
58static inline void __init
59alphabook1_init_arch(void)
60{
61 /* The AlphaBook1 has LCD video fixed at 800x600,
62 37 rows and 100 cols. */
63 screen_info.orig_y = 37;
64 screen_info.orig_video_cols = 100;
65 screen_info.orig_video_lines = 37;
66
67 lca_init_arch();
68}
69
70
71/*
72 * sio_route_tab selects irq routing in PCI/ISA bridge so that:
73 * PIRQ0 -> irq 15
74 * PIRQ1 -> irq 9
75 * PIRQ2 -> irq 10
76 * PIRQ3 -> irq 11
77 *
78 * This probably ought to be configurable via MILO. For
79 * example, sound boards seem to like using IRQ 9.
80 *
81 * This is NOT how we should do it. PIRQ0-X should have
82 * their own IRQs, the way intel uses the IO-APIC IRQs.
83 */
84
85static void __init
86sio_pci_route(void)
87{
88 unsigned int orig_route_tab;
89
90 /* First, ALWAYS read and print the original setting. */
91 pci_bus_read_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
92 &orig_route_tab);
93 printk("%s: PIRQ original 0x%x new 0x%x\n", __func__,
94 orig_route_tab, alpha_mv.sys.sio.route_tab);
95
96#if defined(ALPHA_RESTORE_SRM_SETUP)
97 saved_config.orig_route_tab = orig_route_tab;
98#endif
99
100 /* Now override with desired setting. */
101 pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
102 alpha_mv.sys.sio.route_tab);
103}
104
105static unsigned int __init
106sio_collect_irq_levels(void)
107{
108 unsigned int level_bits = 0;
109 struct pci_dev *dev = NULL;
110
111 /* Iterate through the devices, collecting IRQ levels. */
112 for_each_pci_dev(dev) {
113 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
114 (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
115 continue;
116
117 if (dev->irq)
118 level_bits |= (1 << dev->irq);
119 }
120 return level_bits;
121}
122
123static void __init
124sio_fixup_irq_levels(unsigned int level_bits)
125{
126 unsigned int old_level_bits;
127
128 /*
129 * Now, make all PCI interrupts level sensitive. Notice:
130 * these registers must be accessed byte-wise. inw()/outw()
131 * don't work.
132 *
133 * Make sure to turn off any level bits set for IRQs 9,10,11,15,
134 * so that the only bits getting set are for devices actually found.
135 * Note that we do preserve the remainder of the bits, which we hope
136 * will be set correctly by ARC/SRM.
137 *
138 * Note: we at least preserve any level-set bits on AlphaBook1
139 */
140 old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
141
142 level_bits |= (old_level_bits & 0x71ff);
143
144 outb((level_bits >> 0) & 0xff, 0x4d0);
145 outb((level_bits >> 8) & 0xff, 0x4d1);
146}
147
148static inline int __init
149noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
150{
151 /*
152 * The Noname board has 5 PCI slots with each of the 4
153 * interrupt pins routed to different pins on the PCI/ISA
154 * bridge (PIRQ0-PIRQ3). The table below is based on
155 * information available at:
156 *
157 * http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
158 *
159 * I have no information on the Avanti interrupt routing, but
160 * the routing seems to be identical to the Noname except
161 * that the Avanti has an additional slot whose routing I'm
162 * unsure of.
163 *
164 * pirq_tab[0] is a fake entry to deal with old PCI boards
165 * that have the interrupt pin number hardwired to 0 (meaning
166 * that they use the default INTA line, if they are interrupt
167 * driven at all).
168 */
169 static char irq_tab[][5] __initdata = {
170 /*INT A B C D */
171 { 3, 3, 3, 3, 3}, /* idsel 6 (53c810) */
172 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
173 { 2, 2, -1, -1, -1}, /* idsel 8 (Hack: slot closest ISA) */
174 {-1, -1, -1, -1, -1}, /* idsel 9 (unused) */
175 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
176 { 0, 0, 2, 1, 0}, /* idsel 11 KN25_PCI_SLOT0 */
177 { 1, 1, 0, 2, 1}, /* idsel 12 KN25_PCI_SLOT1 */
178 { 2, 2, 1, 0, 2}, /* idsel 13 KN25_PCI_SLOT2 */
179 { 0, 0, 0, 0, 0}, /* idsel 14 AS255 TULIP */
180 };
181 const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
182 int irq = COMMON_TABLE_LOOKUP, tmp;
183 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
184 return irq >= 0 ? tmp : -1;
185}
186
187static inline int __init
188p2k_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
189{
190 static char irq_tab[][5] __initdata = {
191 /*INT A B C D */
192 { 0, 0, -1, -1, -1}, /* idsel 6 (53c810) */
193 {-1, -1, -1, -1, -1}, /* idsel 7 (SIO: PCI/ISA bridge) */
194 { 1, 1, 2, 3, 0}, /* idsel 8 (slot A) */
195 { 2, 2, 3, 0, 1}, /* idsel 9 (slot B) */
196 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
197 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
198 { 3, 3, -1, -1, -1}, /* idsel 12 (CMD0646) */
199 };
200 const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
201 int irq = COMMON_TABLE_LOOKUP, tmp;
202 tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
203 return irq >= 0 ? tmp : -1;
204}
205
206static inline void __init
207noname_init_pci(void)
208{
209 common_init_pci();
210 sio_pci_route();
211 sio_fixup_irq_levels(sio_collect_irq_levels());
212
213 if (pc873xx_probe() == -1) {
214 printk(KERN_ERR "Probing for PC873xx Super IO chip failed.\n");
215 } else {
216 printk(KERN_INFO "Found %s Super IO chip at 0x%x\n",
217 pc873xx_get_model(), pc873xx_get_base());
218
219 /* Enabling things in the Super IO chip doesn't actually
220 * configure and enable things, the legacy drivers still
221 * need to do the actual configuration and enabling.
222 * This only unblocks them.
223 */
224
225#if !defined(CONFIG_ALPHA_AVANTI)
226 /* Don't bother on the Avanti family.
227 * None of them had on-board IDE.
228 */
229 pc873xx_enable_ide();
230#endif
231 pc873xx_enable_epp19();
232 }
233}
234
235static inline void __init
236alphabook1_init_pci(void)
237{
238 struct pci_dev *dev;
239 unsigned char orig, config;
240
241 common_init_pci();
242 sio_pci_route();
243
244 /*
245 * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
246 * is sensitive to PCI bus bursts, so we must DISABLE
247 * burst mode for the NCR 8xx SCSI... :-(
248 *
249 * Note that the NCR810 SCSI driver must preserve the
250 * setting of the bit in order for this to work. At the
251 * moment (2.0.29), ncr53c8xx.c does NOT do this, but
252 * 53c7,8xx.c DOES.
253 */
254
255 dev = NULL;
256 while ((dev = pci_get_device(PCI_VENDOR_ID_NCR, PCI_ANY_ID, dev))) {
257 if (dev->device == PCI_DEVICE_ID_NCR_53C810
258 || dev->device == PCI_DEVICE_ID_NCR_53C815
259 || dev->device == PCI_DEVICE_ID_NCR_53C820
260 || dev->device == PCI_DEVICE_ID_NCR_53C825) {
261 unsigned long io_port;
262 unsigned char ctest4;
263
264 io_port = dev->resource[0].start;
265 ctest4 = inb(io_port+0x21);
266 if (!(ctest4 & 0x80)) {
267 printk("AlphaBook1 NCR init: setting"
268 " burst disable\n");
269 outb(ctest4 | 0x80, io_port+0x21);
270 }
271 }
272 }
273
274 /* Do not set *ANY* level triggers for AlphaBook1. */
275 sio_fixup_irq_levels(0);
276
277 /* Make sure that register PR1 indicates 1Mb mem */
278 outb(0x0f, 0x3ce); orig = inb(0x3cf); /* read PR5 */
279 outb(0x0f, 0x3ce); outb(0x05, 0x3cf); /* unlock PR0-4 */
280 outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
281 if ((config & 0xc0) != 0xc0) {
282 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
283 config |= 0xc0;
284 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
285 }
286 outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
287}
288
289void
290sio_kill_arch(int mode)
291{
292#if defined(ALPHA_RESTORE_SRM_SETUP)
293 /* Since we cannot read the PCI DMA Window CSRs, we
294 * cannot restore them here.
295 *
296 * However, we CAN read the PIRQ route register, so restore it
297 * now...
298 */
299 pci_bus_write_config_dword(pci_isa_hose->bus, PCI_DEVFN(7, 0), 0x60,
300 saved_config.orig_route_tab);
301#endif
302}
303
304
305/*
306 * The System Vectors
307 */
308
309#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
310struct alpha_machine_vector alphabook1_mv __initmv = {
311 .vector_name = "AlphaBook1",
312 DO_EV4_MMU,
313 DO_DEFAULT_RTC,
314 DO_LCA_IO,
315 .machine_check = lca_machine_check,
316 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
317 .min_io_address = DEFAULT_IO_BASE,
318 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
319
320 .nr_irqs = 16,
321 .device_interrupt = isa_device_interrupt,
322
323 .init_arch = alphabook1_init_arch,
324 .init_irq = sio_init_irq,
325 .init_rtc = common_init_rtc,
326 .init_pci = alphabook1_init_pci,
327 .kill_arch = sio_kill_arch,
328 .pci_map_irq = noname_map_irq,
329 .pci_swizzle = common_swizzle,
330
331 .sys = { .sio = {
332 /* NCR810 SCSI is 14, PCMCIA controller is 15. */
333 .route_tab = 0x0e0f0a0a,
334 }}
335};
336ALIAS_MV(alphabook1)
337#endif
338
339#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
340struct alpha_machine_vector avanti_mv __initmv = {
341 .vector_name = "Avanti",
342 DO_EV4_MMU,
343 DO_DEFAULT_RTC,
344 DO_APECS_IO,
345 .machine_check = apecs_machine_check,
346 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
347 .min_io_address = DEFAULT_IO_BASE,
348 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
349
350 .nr_irqs = 16,
351 .device_interrupt = isa_device_interrupt,
352
353 .init_arch = apecs_init_arch,
354 .init_irq = sio_init_irq,
355 .init_rtc = common_init_rtc,
356 .init_pci = noname_init_pci,
357 .kill_arch = sio_kill_arch,
358 .pci_map_irq = noname_map_irq,
359 .pci_swizzle = common_swizzle,
360
361 .sys = { .sio = {
362 .route_tab = 0x0b0a050f, /* leave 14 for IDE, 9 for SND */
363 }}
364};
365ALIAS_MV(avanti)
366#endif
367
368#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
369struct alpha_machine_vector noname_mv __initmv = {
370 .vector_name = "Noname",
371 DO_EV4_MMU,
372 DO_DEFAULT_RTC,
373 DO_LCA_IO,
374 .machine_check = lca_machine_check,
375 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
376 .min_io_address = DEFAULT_IO_BASE,
377 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
378
379 .nr_irqs = 16,
380 .device_interrupt = srm_device_interrupt,
381
382 .init_arch = lca_init_arch,
383 .init_irq = sio_init_irq,
384 .init_rtc = common_init_rtc,
385 .init_pci = noname_init_pci,
386 .kill_arch = sio_kill_arch,
387 .pci_map_irq = noname_map_irq,
388 .pci_swizzle = common_swizzle,
389
390 .sys = { .sio = {
391 /* For UDB, the only available PCI slot must not map to IRQ 9,
392 since that's the builtin MSS sound chip. That PCI slot
393 will map to PIRQ1 (for INTA at least), so we give it IRQ 15
394 instead.
395
396 Unfortunately we have to do this for NONAME as well, since
397 they are co-indicated when the platform type "Noname" is
398 selected... :-( */
399
400 .route_tab = 0x0b0a0f0d,
401 }}
402};
403ALIAS_MV(noname)
404#endif
405
406#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
407struct alpha_machine_vector p2k_mv __initmv = {
408 .vector_name = "Platform2000",
409 DO_EV4_MMU,
410 DO_DEFAULT_RTC,
411 DO_LCA_IO,
412 .machine_check = lca_machine_check,
413 .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
414 .min_io_address = DEFAULT_IO_BASE,
415 .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
416
417 .nr_irqs = 16,
418 .device_interrupt = srm_device_interrupt,
419
420 .init_arch = lca_init_arch,
421 .init_irq = sio_init_irq,
422 .init_rtc = common_init_rtc,
423 .init_pci = noname_init_pci,
424 .kill_arch = sio_kill_arch,
425 .pci_map_irq = p2k_map_irq,
426 .pci_swizzle = common_swizzle,
427
428 .sys = { .sio = {
429 .route_tab = 0x0b0a090f,
430 }}
431};
432ALIAS_MV(p2k)
433#endif
434
435#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
436struct alpha_machine_vector xl_mv __initmv = {
437 .vector_name = "XL",
438 DO_EV4_MMU,
439 DO_DEFAULT_RTC,
440 DO_APECS_IO,
441 .machine_check = apecs_machine_check,
442 .max_isa_dma_address = ALPHA_XL_MAX_ISA_DMA_ADDRESS,
443 .min_io_address = DEFAULT_IO_BASE,
444 .min_mem_address = XL_DEFAULT_MEM_BASE,
445
446 .nr_irqs = 16,
447 .device_interrupt = isa_device_interrupt,
448
449 .init_arch = apecs_init_arch,
450 .init_irq = sio_init_irq,
451 .init_rtc = common_init_rtc,
452 .init_pci = noname_init_pci,
453 .kill_arch = sio_kill_arch,
454 .pci_map_irq = noname_map_irq,
455 .pci_swizzle = common_swizzle,
456
457 .sys = { .sio = {
458 .route_tab = 0x0b0a090f,
459 }}
460};
461ALIAS_MV(xl)
462#endif