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1// SPDX-License-Identifier: GPL-2.0
2#include <linux/pci.h>
3#include <linux/module.h>
4#include <linux/slab.h>
5#include <linux/ioport.h>
6#include <linux/wait.h>
7
8#include "pci.h"
9
10/*
11 * This interrupt-safe spinlock protects all accesses to PCI
12 * configuration space.
13 */
14
15DEFINE_RAW_SPINLOCK(pci_lock);
16
17/*
18 * Wrappers for all PCI configuration access functions. They just check
19 * alignment, do locking and call the low-level functions pointed to
20 * by pci_dev->ops.
21 */
22
23#define PCI_byte_BAD 0
24#define PCI_word_BAD (pos & 1)
25#define PCI_dword_BAD (pos & 3)
26
27#ifdef CONFIG_PCI_LOCKLESS_CONFIG
28# define pci_lock_config(f) do { (void)(f); } while (0)
29# define pci_unlock_config(f) do { (void)(f); } while (0)
30#else
31# define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
32# define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
33#endif
34
35#define PCI_OP_READ(size, type, len) \
36int noinline pci_bus_read_config_##size \
37 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
38{ \
39 int res; \
40 unsigned long flags; \
41 u32 data = 0; \
42 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
43 pci_lock_config(flags); \
44 res = bus->ops->read(bus, devfn, pos, len, &data); \
45 if (res) \
46 PCI_SET_ERROR_RESPONSE(value); \
47 else \
48 *value = (type)data; \
49 pci_unlock_config(flags); \
50 return res; \
51}
52
53#define PCI_OP_WRITE(size, type, len) \
54int noinline pci_bus_write_config_##size \
55 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
56{ \
57 int res; \
58 unsigned long flags; \
59 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
60 pci_lock_config(flags); \
61 res = bus->ops->write(bus, devfn, pos, len, value); \
62 pci_unlock_config(flags); \
63 return res; \
64}
65
66PCI_OP_READ(byte, u8, 1)
67PCI_OP_READ(word, u16, 2)
68PCI_OP_READ(dword, u32, 4)
69PCI_OP_WRITE(byte, u8, 1)
70PCI_OP_WRITE(word, u16, 2)
71PCI_OP_WRITE(dword, u32, 4)
72
73EXPORT_SYMBOL(pci_bus_read_config_byte);
74EXPORT_SYMBOL(pci_bus_read_config_word);
75EXPORT_SYMBOL(pci_bus_read_config_dword);
76EXPORT_SYMBOL(pci_bus_write_config_byte);
77EXPORT_SYMBOL(pci_bus_write_config_word);
78EXPORT_SYMBOL(pci_bus_write_config_dword);
79
80int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
81 int where, int size, u32 *val)
82{
83 void __iomem *addr;
84
85 addr = bus->ops->map_bus(bus, devfn, where);
86 if (!addr)
87 return PCIBIOS_DEVICE_NOT_FOUND;
88
89 if (size == 1)
90 *val = readb(addr);
91 else if (size == 2)
92 *val = readw(addr);
93 else
94 *val = readl(addr);
95
96 return PCIBIOS_SUCCESSFUL;
97}
98EXPORT_SYMBOL_GPL(pci_generic_config_read);
99
100int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
101 int where, int size, u32 val)
102{
103 void __iomem *addr;
104
105 addr = bus->ops->map_bus(bus, devfn, where);
106 if (!addr)
107 return PCIBIOS_DEVICE_NOT_FOUND;
108
109 if (size == 1)
110 writeb(val, addr);
111 else if (size == 2)
112 writew(val, addr);
113 else
114 writel(val, addr);
115
116 return PCIBIOS_SUCCESSFUL;
117}
118EXPORT_SYMBOL_GPL(pci_generic_config_write);
119
120int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 *val)
122{
123 void __iomem *addr;
124
125 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
126 if (!addr)
127 return PCIBIOS_DEVICE_NOT_FOUND;
128
129 *val = readl(addr);
130
131 if (size <= 2)
132 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
133
134 return PCIBIOS_SUCCESSFUL;
135}
136EXPORT_SYMBOL_GPL(pci_generic_config_read32);
137
138int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
139 int where, int size, u32 val)
140{
141 void __iomem *addr;
142 u32 mask, tmp;
143
144 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
145 if (!addr)
146 return PCIBIOS_DEVICE_NOT_FOUND;
147
148 if (size == 4) {
149 writel(val, addr);
150 return PCIBIOS_SUCCESSFUL;
151 }
152
153 /*
154 * In general, hardware that supports only 32-bit writes on PCI is
155 * not spec-compliant. For example, software may perform a 16-bit
156 * write. If the hardware only supports 32-bit accesses, we must
157 * do a 32-bit read, merge in the 16 bits we intend to write,
158 * followed by a 32-bit write. If the 16 bits we *don't* intend to
159 * write happen to have any RW1C (write-one-to-clear) bits set, we
160 * just inadvertently cleared something we shouldn't have.
161 */
162 if (!bus->unsafe_warn) {
163 dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
164 size, pci_domain_nr(bus), bus->number,
165 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
166 bus->unsafe_warn = 1;
167 }
168
169 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
170 tmp = readl(addr) & mask;
171 tmp |= val << ((where & 0x3) * 8);
172 writel(tmp, addr);
173
174 return PCIBIOS_SUCCESSFUL;
175}
176EXPORT_SYMBOL_GPL(pci_generic_config_write32);
177
178/**
179 * pci_bus_set_ops - Set raw operations of pci bus
180 * @bus: pci bus struct
181 * @ops: new raw operations
182 *
183 * Return previous raw operations
184 */
185struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
186{
187 struct pci_ops *old_ops;
188 unsigned long flags;
189
190 raw_spin_lock_irqsave(&pci_lock, flags);
191 old_ops = bus->ops;
192 bus->ops = ops;
193 raw_spin_unlock_irqrestore(&pci_lock, flags);
194 return old_ops;
195}
196EXPORT_SYMBOL(pci_bus_set_ops);
197
198/*
199 * The following routines are to prevent the user from accessing PCI config
200 * space when it's unsafe to do so. Some devices require this during BIST and
201 * we're required to prevent it during D-state transitions.
202 *
203 * We have a bit per device to indicate it's blocked and a global wait queue
204 * for callers to sleep on until devices are unblocked.
205 */
206static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
207
208static noinline void pci_wait_cfg(struct pci_dev *dev)
209 __must_hold(&pci_lock)
210{
211 do {
212 raw_spin_unlock_irq(&pci_lock);
213 wait_event(pci_cfg_wait, !dev->block_cfg_access);
214 raw_spin_lock_irq(&pci_lock);
215 } while (dev->block_cfg_access);
216}
217
218/* Returns 0 on success, negative values indicate error. */
219#define PCI_USER_READ_CONFIG(size, type) \
220int pci_user_read_config_##size \
221 (struct pci_dev *dev, int pos, type *val) \
222{ \
223 int ret = PCIBIOS_SUCCESSFUL; \
224 u32 data = -1; \
225 if (PCI_##size##_BAD) \
226 return -EINVAL; \
227 raw_spin_lock_irq(&pci_lock); \
228 if (unlikely(dev->block_cfg_access)) \
229 pci_wait_cfg(dev); \
230 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
231 pos, sizeof(type), &data); \
232 raw_spin_unlock_irq(&pci_lock); \
233 if (ret) \
234 PCI_SET_ERROR_RESPONSE(val); \
235 else \
236 *val = (type)data; \
237 return pcibios_err_to_errno(ret); \
238} \
239EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
240
241/* Returns 0 on success, negative values indicate error. */
242#define PCI_USER_WRITE_CONFIG(size, type) \
243int pci_user_write_config_##size \
244 (struct pci_dev *dev, int pos, type val) \
245{ \
246 int ret = PCIBIOS_SUCCESSFUL; \
247 if (PCI_##size##_BAD) \
248 return -EINVAL; \
249 raw_spin_lock_irq(&pci_lock); \
250 if (unlikely(dev->block_cfg_access)) \
251 pci_wait_cfg(dev); \
252 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
253 pos, sizeof(type), val); \
254 raw_spin_unlock_irq(&pci_lock); \
255 return pcibios_err_to_errno(ret); \
256} \
257EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
258
259PCI_USER_READ_CONFIG(byte, u8)
260PCI_USER_READ_CONFIG(word, u16)
261PCI_USER_READ_CONFIG(dword, u32)
262PCI_USER_WRITE_CONFIG(byte, u8)
263PCI_USER_WRITE_CONFIG(word, u16)
264PCI_USER_WRITE_CONFIG(dword, u32)
265
266/**
267 * pci_cfg_access_lock - Lock PCI config reads/writes
268 * @dev: pci device struct
269 *
270 * When access is locked, any userspace reads or writes to config
271 * space and concurrent lock requests will sleep until access is
272 * allowed via pci_cfg_access_unlock() again.
273 */
274void pci_cfg_access_lock(struct pci_dev *dev)
275{
276 might_sleep();
277
278 raw_spin_lock_irq(&pci_lock);
279 if (dev->block_cfg_access)
280 pci_wait_cfg(dev);
281 dev->block_cfg_access = 1;
282 raw_spin_unlock_irq(&pci_lock);
283}
284EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
285
286/**
287 * pci_cfg_access_trylock - try to lock PCI config reads/writes
288 * @dev: pci device struct
289 *
290 * Same as pci_cfg_access_lock, but will return 0 if access is
291 * already locked, 1 otherwise. This function can be used from
292 * atomic contexts.
293 */
294bool pci_cfg_access_trylock(struct pci_dev *dev)
295{
296 unsigned long flags;
297 bool locked = true;
298
299 raw_spin_lock_irqsave(&pci_lock, flags);
300 if (dev->block_cfg_access)
301 locked = false;
302 else
303 dev->block_cfg_access = 1;
304 raw_spin_unlock_irqrestore(&pci_lock, flags);
305
306 return locked;
307}
308EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
309
310/**
311 * pci_cfg_access_unlock - Unlock PCI config reads/writes
312 * @dev: pci device struct
313 *
314 * This function allows PCI config accesses to resume.
315 */
316void pci_cfg_access_unlock(struct pci_dev *dev)
317{
318 unsigned long flags;
319
320 raw_spin_lock_irqsave(&pci_lock, flags);
321
322 /*
323 * This indicates a problem in the caller, but we don't need
324 * to kill them, unlike a double-block above.
325 */
326 WARN_ON(!dev->block_cfg_access);
327
328 dev->block_cfg_access = 0;
329 raw_spin_unlock_irqrestore(&pci_lock, flags);
330
331 wake_up_all(&pci_cfg_wait);
332}
333EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
334
335static inline int pcie_cap_version(const struct pci_dev *dev)
336{
337 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
338}
339
340bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
341{
342 int type = pci_pcie_type(dev);
343
344 return type == PCI_EXP_TYPE_ENDPOINT ||
345 type == PCI_EXP_TYPE_LEG_END ||
346 type == PCI_EXP_TYPE_ROOT_PORT ||
347 type == PCI_EXP_TYPE_UPSTREAM ||
348 type == PCI_EXP_TYPE_DOWNSTREAM ||
349 type == PCI_EXP_TYPE_PCI_BRIDGE ||
350 type == PCI_EXP_TYPE_PCIE_BRIDGE;
351}
352
353bool pcie_cap_has_lnkctl2(const struct pci_dev *dev)
354{
355 return pcie_cap_has_lnkctl(dev) && pcie_cap_version(dev) > 1;
356}
357
358static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
359{
360 return pcie_downstream_port(dev) &&
361 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
362}
363
364bool pcie_cap_has_rtctl(const struct pci_dev *dev)
365{
366 int type = pci_pcie_type(dev);
367
368 return type == PCI_EXP_TYPE_ROOT_PORT ||
369 type == PCI_EXP_TYPE_RC_EC;
370}
371
372static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
373{
374 if (!pci_is_pcie(dev))
375 return false;
376
377 switch (pos) {
378 case PCI_EXP_FLAGS:
379 return true;
380 case PCI_EXP_DEVCAP:
381 case PCI_EXP_DEVCTL:
382 case PCI_EXP_DEVSTA:
383 return true;
384 case PCI_EXP_LNKCAP:
385 case PCI_EXP_LNKCTL:
386 case PCI_EXP_LNKSTA:
387 return pcie_cap_has_lnkctl(dev);
388 case PCI_EXP_SLTCAP:
389 case PCI_EXP_SLTCTL:
390 case PCI_EXP_SLTSTA:
391 return pcie_cap_has_sltctl(dev);
392 case PCI_EXP_RTCTL:
393 case PCI_EXP_RTCAP:
394 case PCI_EXP_RTSTA:
395 return pcie_cap_has_rtctl(dev);
396 case PCI_EXP_DEVCAP2:
397 case PCI_EXP_DEVCTL2:
398 return pcie_cap_version(dev) > 1;
399 case PCI_EXP_LNKCAP2:
400 case PCI_EXP_LNKCTL2:
401 case PCI_EXP_LNKSTA2:
402 return pcie_cap_has_lnkctl2(dev);
403 default:
404 return false;
405 }
406}
407
408/*
409 * Note that these accessor functions are only for the "PCI Express
410 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
411 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
412 */
413int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
414{
415 int ret;
416
417 *val = 0;
418 if (pos & 1)
419 return PCIBIOS_BAD_REGISTER_NUMBER;
420
421 if (pcie_capability_reg_implemented(dev, pos)) {
422 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
423 /*
424 * Reset *val to 0 if pci_read_config_word() fails; it may
425 * have been written as 0xFFFF (PCI_ERROR_RESPONSE) if the
426 * config read failed on PCI.
427 */
428 if (ret)
429 *val = 0;
430 return ret;
431 }
432
433 /*
434 * For Functions that do not implement the Slot Capabilities,
435 * Slot Status, and Slot Control registers, these spaces must
436 * be hardwired to 0b, with the exception of the Presence Detect
437 * State bit in the Slot Status register of Downstream Ports,
438 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
439 */
440 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
441 pos == PCI_EXP_SLTSTA)
442 *val = PCI_EXP_SLTSTA_PDS;
443
444 return 0;
445}
446EXPORT_SYMBOL(pcie_capability_read_word);
447
448int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
449{
450 int ret;
451
452 *val = 0;
453 if (pos & 3)
454 return PCIBIOS_BAD_REGISTER_NUMBER;
455
456 if (pcie_capability_reg_implemented(dev, pos)) {
457 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
458 /*
459 * Reset *val to 0 if pci_read_config_dword() fails; it may
460 * have been written as 0xFFFFFFFF (PCI_ERROR_RESPONSE) if
461 * the config read failed on PCI.
462 */
463 if (ret)
464 *val = 0;
465 return ret;
466 }
467
468 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
469 pos == PCI_EXP_SLTSTA)
470 *val = PCI_EXP_SLTSTA_PDS;
471
472 return 0;
473}
474EXPORT_SYMBOL(pcie_capability_read_dword);
475
476int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
477{
478 if (pos & 1)
479 return PCIBIOS_BAD_REGISTER_NUMBER;
480
481 if (!pcie_capability_reg_implemented(dev, pos))
482 return 0;
483
484 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
485}
486EXPORT_SYMBOL(pcie_capability_write_word);
487
488int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
489{
490 if (pos & 3)
491 return PCIBIOS_BAD_REGISTER_NUMBER;
492
493 if (!pcie_capability_reg_implemented(dev, pos))
494 return 0;
495
496 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
497}
498EXPORT_SYMBOL(pcie_capability_write_dword);
499
500int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
501 u16 clear, u16 set)
502{
503 int ret;
504 u16 val;
505
506 ret = pcie_capability_read_word(dev, pos, &val);
507 if (ret)
508 return ret;
509
510 val &= ~clear;
511 val |= set;
512 return pcie_capability_write_word(dev, pos, val);
513}
514EXPORT_SYMBOL(pcie_capability_clear_and_set_word_unlocked);
515
516int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
517 u16 clear, u16 set)
518{
519 unsigned long flags;
520 int ret;
521
522 spin_lock_irqsave(&dev->pcie_cap_lock, flags);
523 ret = pcie_capability_clear_and_set_word_unlocked(dev, pos, clear, set);
524 spin_unlock_irqrestore(&dev->pcie_cap_lock, flags);
525
526 return ret;
527}
528EXPORT_SYMBOL(pcie_capability_clear_and_set_word_locked);
529
530int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
531 u32 clear, u32 set)
532{
533 int ret;
534 u32 val;
535
536 ret = pcie_capability_read_dword(dev, pos, &val);
537 if (ret)
538 return ret;
539
540 val &= ~clear;
541 val |= set;
542 return pcie_capability_write_dword(dev, pos, val);
543}
544EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
545
546int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
547{
548 if (pci_dev_is_disconnected(dev)) {
549 PCI_SET_ERROR_RESPONSE(val);
550 return PCIBIOS_DEVICE_NOT_FOUND;
551 }
552 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
553}
554EXPORT_SYMBOL(pci_read_config_byte);
555
556int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
557{
558 if (pci_dev_is_disconnected(dev)) {
559 PCI_SET_ERROR_RESPONSE(val);
560 return PCIBIOS_DEVICE_NOT_FOUND;
561 }
562 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
563}
564EXPORT_SYMBOL(pci_read_config_word);
565
566int pci_read_config_dword(const struct pci_dev *dev, int where,
567 u32 *val)
568{
569 if (pci_dev_is_disconnected(dev)) {
570 PCI_SET_ERROR_RESPONSE(val);
571 return PCIBIOS_DEVICE_NOT_FOUND;
572 }
573 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
574}
575EXPORT_SYMBOL(pci_read_config_dword);
576
577int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
578{
579 if (pci_dev_is_disconnected(dev))
580 return PCIBIOS_DEVICE_NOT_FOUND;
581 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
582}
583EXPORT_SYMBOL(pci_write_config_byte);
584
585int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
586{
587 if (pci_dev_is_disconnected(dev))
588 return PCIBIOS_DEVICE_NOT_FOUND;
589 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
590}
591EXPORT_SYMBOL(pci_write_config_word);
592
593int pci_write_config_dword(const struct pci_dev *dev, int where,
594 u32 val)
595{
596 if (pci_dev_is_disconnected(dev))
597 return PCIBIOS_DEVICE_NOT_FOUND;
598 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
599}
600EXPORT_SYMBOL(pci_write_config_dword);
601
602void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
603 u32 clear, u32 set)
604{
605 u32 val;
606
607 pci_read_config_dword(dev, pos, &val);
608 val &= ~clear;
609 val |= set;
610 pci_write_config_dword(dev, pos, val);
611}
612EXPORT_SYMBOL(pci_clear_and_set_config_dword);
1// SPDX-License-Identifier: GPL-2.0
2#include <linux/pci.h>
3#include <linux/module.h>
4#include <linux/slab.h>
5#include <linux/ioport.h>
6#include <linux/wait.h>
7
8#include "pci.h"
9
10/*
11 * This interrupt-safe spinlock protects all accesses to PCI
12 * configuration space.
13 */
14
15DEFINE_RAW_SPINLOCK(pci_lock);
16
17/*
18 * Wrappers for all PCI configuration access functions. They just check
19 * alignment, do locking and call the low-level functions pointed to
20 * by pci_dev->ops.
21 */
22
23#define PCI_byte_BAD 0
24#define PCI_word_BAD (pos & 1)
25#define PCI_dword_BAD (pos & 3)
26
27#ifdef CONFIG_PCI_LOCKLESS_CONFIG
28# define pci_lock_config(f) do { (void)(f); } while (0)
29# define pci_unlock_config(f) do { (void)(f); } while (0)
30#else
31# define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
32# define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
33#endif
34
35#define PCI_OP_READ(size, type, len) \
36int noinline pci_bus_read_config_##size \
37 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
38{ \
39 int res; \
40 unsigned long flags; \
41 u32 data = 0; \
42 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
43 pci_lock_config(flags); \
44 res = bus->ops->read(bus, devfn, pos, len, &data); \
45 *value = (type)data; \
46 pci_unlock_config(flags); \
47 return res; \
48}
49
50#define PCI_OP_WRITE(size, type, len) \
51int noinline pci_bus_write_config_##size \
52 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
53{ \
54 int res; \
55 unsigned long flags; \
56 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
57 pci_lock_config(flags); \
58 res = bus->ops->write(bus, devfn, pos, len, value); \
59 pci_unlock_config(flags); \
60 return res; \
61}
62
63PCI_OP_READ(byte, u8, 1)
64PCI_OP_READ(word, u16, 2)
65PCI_OP_READ(dword, u32, 4)
66PCI_OP_WRITE(byte, u8, 1)
67PCI_OP_WRITE(word, u16, 2)
68PCI_OP_WRITE(dword, u32, 4)
69
70EXPORT_SYMBOL(pci_bus_read_config_byte);
71EXPORT_SYMBOL(pci_bus_read_config_word);
72EXPORT_SYMBOL(pci_bus_read_config_dword);
73EXPORT_SYMBOL(pci_bus_write_config_byte);
74EXPORT_SYMBOL(pci_bus_write_config_word);
75EXPORT_SYMBOL(pci_bus_write_config_dword);
76
77int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
78 int where, int size, u32 *val)
79{
80 void __iomem *addr;
81
82 addr = bus->ops->map_bus(bus, devfn, where);
83 if (!addr) {
84 *val = ~0;
85 return PCIBIOS_DEVICE_NOT_FOUND;
86 }
87
88 if (size == 1)
89 *val = readb(addr);
90 else if (size == 2)
91 *val = readw(addr);
92 else
93 *val = readl(addr);
94
95 return PCIBIOS_SUCCESSFUL;
96}
97EXPORT_SYMBOL_GPL(pci_generic_config_read);
98
99int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
100 int where, int size, u32 val)
101{
102 void __iomem *addr;
103
104 addr = bus->ops->map_bus(bus, devfn, where);
105 if (!addr)
106 return PCIBIOS_DEVICE_NOT_FOUND;
107
108 if (size == 1)
109 writeb(val, addr);
110 else if (size == 2)
111 writew(val, addr);
112 else
113 writel(val, addr);
114
115 return PCIBIOS_SUCCESSFUL;
116}
117EXPORT_SYMBOL_GPL(pci_generic_config_write);
118
119int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
120 int where, int size, u32 *val)
121{
122 void __iomem *addr;
123
124 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
125 if (!addr) {
126 *val = ~0;
127 return PCIBIOS_DEVICE_NOT_FOUND;
128 }
129
130 *val = readl(addr);
131
132 if (size <= 2)
133 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
134
135 return PCIBIOS_SUCCESSFUL;
136}
137EXPORT_SYMBOL_GPL(pci_generic_config_read32);
138
139int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
140 int where, int size, u32 val)
141{
142 void __iomem *addr;
143 u32 mask, tmp;
144
145 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
146 if (!addr)
147 return PCIBIOS_DEVICE_NOT_FOUND;
148
149 if (size == 4) {
150 writel(val, addr);
151 return PCIBIOS_SUCCESSFUL;
152 }
153
154 /*
155 * In general, hardware that supports only 32-bit writes on PCI is
156 * not spec-compliant. For example, software may perform a 16-bit
157 * write. If the hardware only supports 32-bit accesses, we must
158 * do a 32-bit read, merge in the 16 bits we intend to write,
159 * followed by a 32-bit write. If the 16 bits we *don't* intend to
160 * write happen to have any RW1C (write-one-to-clear) bits set, we
161 * just inadvertently cleared something we shouldn't have.
162 */
163 dev_warn_ratelimited(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
164 size, pci_domain_nr(bus), bus->number,
165 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
166
167 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
168 tmp = readl(addr) & mask;
169 tmp |= val << ((where & 0x3) * 8);
170 writel(tmp, addr);
171
172 return PCIBIOS_SUCCESSFUL;
173}
174EXPORT_SYMBOL_GPL(pci_generic_config_write32);
175
176/**
177 * pci_bus_set_ops - Set raw operations of pci bus
178 * @bus: pci bus struct
179 * @ops: new raw operations
180 *
181 * Return previous raw operations
182 */
183struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
184{
185 struct pci_ops *old_ops;
186 unsigned long flags;
187
188 raw_spin_lock_irqsave(&pci_lock, flags);
189 old_ops = bus->ops;
190 bus->ops = ops;
191 raw_spin_unlock_irqrestore(&pci_lock, flags);
192 return old_ops;
193}
194EXPORT_SYMBOL(pci_bus_set_ops);
195
196/*
197 * The following routines are to prevent the user from accessing PCI config
198 * space when it's unsafe to do so. Some devices require this during BIST and
199 * we're required to prevent it during D-state transitions.
200 *
201 * We have a bit per device to indicate it's blocked and a global wait queue
202 * for callers to sleep on until devices are unblocked.
203 */
204static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
205
206static noinline void pci_wait_cfg(struct pci_dev *dev)
207 __must_hold(&pci_lock)
208{
209 do {
210 raw_spin_unlock_irq(&pci_lock);
211 wait_event(pci_cfg_wait, !dev->block_cfg_access);
212 raw_spin_lock_irq(&pci_lock);
213 } while (dev->block_cfg_access);
214}
215
216/* Returns 0 on success, negative values indicate error. */
217#define PCI_USER_READ_CONFIG(size, type) \
218int pci_user_read_config_##size \
219 (struct pci_dev *dev, int pos, type *val) \
220{ \
221 int ret = PCIBIOS_SUCCESSFUL; \
222 u32 data = -1; \
223 if (PCI_##size##_BAD) \
224 return -EINVAL; \
225 raw_spin_lock_irq(&pci_lock); \
226 if (unlikely(dev->block_cfg_access)) \
227 pci_wait_cfg(dev); \
228 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
229 pos, sizeof(type), &data); \
230 raw_spin_unlock_irq(&pci_lock); \
231 *val = (type)data; \
232 return pcibios_err_to_errno(ret); \
233} \
234EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
235
236/* Returns 0 on success, negative values indicate error. */
237#define PCI_USER_WRITE_CONFIG(size, type) \
238int pci_user_write_config_##size \
239 (struct pci_dev *dev, int pos, type val) \
240{ \
241 int ret = PCIBIOS_SUCCESSFUL; \
242 if (PCI_##size##_BAD) \
243 return -EINVAL; \
244 raw_spin_lock_irq(&pci_lock); \
245 if (unlikely(dev->block_cfg_access)) \
246 pci_wait_cfg(dev); \
247 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
248 pos, sizeof(type), val); \
249 raw_spin_unlock_irq(&pci_lock); \
250 return pcibios_err_to_errno(ret); \
251} \
252EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
253
254PCI_USER_READ_CONFIG(byte, u8)
255PCI_USER_READ_CONFIG(word, u16)
256PCI_USER_READ_CONFIG(dword, u32)
257PCI_USER_WRITE_CONFIG(byte, u8)
258PCI_USER_WRITE_CONFIG(word, u16)
259PCI_USER_WRITE_CONFIG(dword, u32)
260
261/**
262 * pci_cfg_access_lock - Lock PCI config reads/writes
263 * @dev: pci device struct
264 *
265 * When access is locked, any userspace reads or writes to config
266 * space and concurrent lock requests will sleep until access is
267 * allowed via pci_cfg_access_unlock() again.
268 */
269void pci_cfg_access_lock(struct pci_dev *dev)
270{
271 might_sleep();
272
273 raw_spin_lock_irq(&pci_lock);
274 if (dev->block_cfg_access)
275 pci_wait_cfg(dev);
276 dev->block_cfg_access = 1;
277 raw_spin_unlock_irq(&pci_lock);
278}
279EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
280
281/**
282 * pci_cfg_access_trylock - try to lock PCI config reads/writes
283 * @dev: pci device struct
284 *
285 * Same as pci_cfg_access_lock, but will return 0 if access is
286 * already locked, 1 otherwise. This function can be used from
287 * atomic contexts.
288 */
289bool pci_cfg_access_trylock(struct pci_dev *dev)
290{
291 unsigned long flags;
292 bool locked = true;
293
294 raw_spin_lock_irqsave(&pci_lock, flags);
295 if (dev->block_cfg_access)
296 locked = false;
297 else
298 dev->block_cfg_access = 1;
299 raw_spin_unlock_irqrestore(&pci_lock, flags);
300
301 return locked;
302}
303EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
304
305/**
306 * pci_cfg_access_unlock - Unlock PCI config reads/writes
307 * @dev: pci device struct
308 *
309 * This function allows PCI config accesses to resume.
310 */
311void pci_cfg_access_unlock(struct pci_dev *dev)
312{
313 unsigned long flags;
314
315 raw_spin_lock_irqsave(&pci_lock, flags);
316
317 /*
318 * This indicates a problem in the caller, but we don't need
319 * to kill them, unlike a double-block above.
320 */
321 WARN_ON(!dev->block_cfg_access);
322
323 dev->block_cfg_access = 0;
324 raw_spin_unlock_irqrestore(&pci_lock, flags);
325
326 wake_up_all(&pci_cfg_wait);
327}
328EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
329
330static inline int pcie_cap_version(const struct pci_dev *dev)
331{
332 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
333}
334
335bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
336{
337 int type = pci_pcie_type(dev);
338
339 return type == PCI_EXP_TYPE_ENDPOINT ||
340 type == PCI_EXP_TYPE_LEG_END ||
341 type == PCI_EXP_TYPE_ROOT_PORT ||
342 type == PCI_EXP_TYPE_UPSTREAM ||
343 type == PCI_EXP_TYPE_DOWNSTREAM ||
344 type == PCI_EXP_TYPE_PCI_BRIDGE ||
345 type == PCI_EXP_TYPE_PCIE_BRIDGE;
346}
347
348static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
349{
350 return pcie_downstream_port(dev) &&
351 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
352}
353
354bool pcie_cap_has_rtctl(const struct pci_dev *dev)
355{
356 int type = pci_pcie_type(dev);
357
358 return type == PCI_EXP_TYPE_ROOT_PORT ||
359 type == PCI_EXP_TYPE_RC_EC;
360}
361
362static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
363{
364 if (!pci_is_pcie(dev))
365 return false;
366
367 switch (pos) {
368 case PCI_EXP_FLAGS:
369 return true;
370 case PCI_EXP_DEVCAP:
371 case PCI_EXP_DEVCTL:
372 case PCI_EXP_DEVSTA:
373 return true;
374 case PCI_EXP_LNKCAP:
375 case PCI_EXP_LNKCTL:
376 case PCI_EXP_LNKSTA:
377 return pcie_cap_has_lnkctl(dev);
378 case PCI_EXP_SLTCAP:
379 case PCI_EXP_SLTCTL:
380 case PCI_EXP_SLTSTA:
381 return pcie_cap_has_sltctl(dev);
382 case PCI_EXP_RTCTL:
383 case PCI_EXP_RTCAP:
384 case PCI_EXP_RTSTA:
385 return pcie_cap_has_rtctl(dev);
386 case PCI_EXP_DEVCAP2:
387 case PCI_EXP_DEVCTL2:
388 case PCI_EXP_LNKCAP2:
389 case PCI_EXP_LNKCTL2:
390 case PCI_EXP_LNKSTA2:
391 return pcie_cap_version(dev) > 1;
392 default:
393 return false;
394 }
395}
396
397/*
398 * Note that these accessor functions are only for the "PCI Express
399 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
400 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
401 */
402int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
403{
404 int ret;
405
406 *val = 0;
407 if (pos & 1)
408 return PCIBIOS_BAD_REGISTER_NUMBER;
409
410 if (pcie_capability_reg_implemented(dev, pos)) {
411 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
412 /*
413 * Reset *val to 0 if pci_read_config_word() fails, it may
414 * have been written as 0xFFFF if hardware error happens
415 * during pci_read_config_word().
416 */
417 if (ret)
418 *val = 0;
419 return ret;
420 }
421
422 /*
423 * For Functions that do not implement the Slot Capabilities,
424 * Slot Status, and Slot Control registers, these spaces must
425 * be hardwired to 0b, with the exception of the Presence Detect
426 * State bit in the Slot Status register of Downstream Ports,
427 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
428 */
429 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
430 pos == PCI_EXP_SLTSTA)
431 *val = PCI_EXP_SLTSTA_PDS;
432
433 return 0;
434}
435EXPORT_SYMBOL(pcie_capability_read_word);
436
437int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
438{
439 int ret;
440
441 *val = 0;
442 if (pos & 3)
443 return PCIBIOS_BAD_REGISTER_NUMBER;
444
445 if (pcie_capability_reg_implemented(dev, pos)) {
446 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
447 /*
448 * Reset *val to 0 if pci_read_config_dword() fails, it may
449 * have been written as 0xFFFFFFFF if hardware error happens
450 * during pci_read_config_dword().
451 */
452 if (ret)
453 *val = 0;
454 return ret;
455 }
456
457 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
458 pos == PCI_EXP_SLTSTA)
459 *val = PCI_EXP_SLTSTA_PDS;
460
461 return 0;
462}
463EXPORT_SYMBOL(pcie_capability_read_dword);
464
465int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
466{
467 if (pos & 1)
468 return PCIBIOS_BAD_REGISTER_NUMBER;
469
470 if (!pcie_capability_reg_implemented(dev, pos))
471 return 0;
472
473 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
474}
475EXPORT_SYMBOL(pcie_capability_write_word);
476
477int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
478{
479 if (pos & 3)
480 return PCIBIOS_BAD_REGISTER_NUMBER;
481
482 if (!pcie_capability_reg_implemented(dev, pos))
483 return 0;
484
485 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
486}
487EXPORT_SYMBOL(pcie_capability_write_dword);
488
489int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
490 u16 clear, u16 set)
491{
492 int ret;
493 u16 val;
494
495 ret = pcie_capability_read_word(dev, pos, &val);
496 if (!ret) {
497 val &= ~clear;
498 val |= set;
499 ret = pcie_capability_write_word(dev, pos, val);
500 }
501
502 return ret;
503}
504EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
505
506int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
507 u32 clear, u32 set)
508{
509 int ret;
510 u32 val;
511
512 ret = pcie_capability_read_dword(dev, pos, &val);
513 if (!ret) {
514 val &= ~clear;
515 val |= set;
516 ret = pcie_capability_write_dword(dev, pos, val);
517 }
518
519 return ret;
520}
521EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
522
523int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
524{
525 if (pci_dev_is_disconnected(dev)) {
526 *val = ~0;
527 return PCIBIOS_DEVICE_NOT_FOUND;
528 }
529 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
530}
531EXPORT_SYMBOL(pci_read_config_byte);
532
533int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
534{
535 if (pci_dev_is_disconnected(dev)) {
536 *val = ~0;
537 return PCIBIOS_DEVICE_NOT_FOUND;
538 }
539 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
540}
541EXPORT_SYMBOL(pci_read_config_word);
542
543int pci_read_config_dword(const struct pci_dev *dev, int where,
544 u32 *val)
545{
546 if (pci_dev_is_disconnected(dev)) {
547 *val = ~0;
548 return PCIBIOS_DEVICE_NOT_FOUND;
549 }
550 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
551}
552EXPORT_SYMBOL(pci_read_config_dword);
553
554int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
555{
556 if (pci_dev_is_disconnected(dev))
557 return PCIBIOS_DEVICE_NOT_FOUND;
558 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
559}
560EXPORT_SYMBOL(pci_write_config_byte);
561
562int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
563{
564 if (pci_dev_is_disconnected(dev))
565 return PCIBIOS_DEVICE_NOT_FOUND;
566 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
567}
568EXPORT_SYMBOL(pci_write_config_word);
569
570int pci_write_config_dword(const struct pci_dev *dev, int where,
571 u32 val)
572{
573 if (pci_dev_is_disconnected(dev))
574 return PCIBIOS_DEVICE_NOT_FOUND;
575 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
576}
577EXPORT_SYMBOL(pci_write_config_dword);