Loading...
1// SPDX-License-Identifier: GPL-2.0
2#include <linux/pci.h>
3#include <linux/module.h>
4#include <linux/slab.h>
5#include <linux/ioport.h>
6#include <linux/wait.h>
7
8#include "pci.h"
9
10/*
11 * This interrupt-safe spinlock protects all accesses to PCI
12 * configuration space.
13 */
14
15DEFINE_RAW_SPINLOCK(pci_lock);
16
17/*
18 * Wrappers for all PCI configuration access functions. They just check
19 * alignment, do locking and call the low-level functions pointed to
20 * by pci_dev->ops.
21 */
22
23#define PCI_byte_BAD 0
24#define PCI_word_BAD (pos & 1)
25#define PCI_dword_BAD (pos & 3)
26
27#ifdef CONFIG_PCI_LOCKLESS_CONFIG
28# define pci_lock_config(f) do { (void)(f); } while (0)
29# define pci_unlock_config(f) do { (void)(f); } while (0)
30#else
31# define pci_lock_config(f) raw_spin_lock_irqsave(&pci_lock, f)
32# define pci_unlock_config(f) raw_spin_unlock_irqrestore(&pci_lock, f)
33#endif
34
35#define PCI_OP_READ(size, type, len) \
36int noinline pci_bus_read_config_##size \
37 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
38{ \
39 int res; \
40 unsigned long flags; \
41 u32 data = 0; \
42 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
43 pci_lock_config(flags); \
44 res = bus->ops->read(bus, devfn, pos, len, &data); \
45 if (res) \
46 PCI_SET_ERROR_RESPONSE(value); \
47 else \
48 *value = (type)data; \
49 pci_unlock_config(flags); \
50 return res; \
51}
52
53#define PCI_OP_WRITE(size, type, len) \
54int noinline pci_bus_write_config_##size \
55 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
56{ \
57 int res; \
58 unsigned long flags; \
59 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
60 pci_lock_config(flags); \
61 res = bus->ops->write(bus, devfn, pos, len, value); \
62 pci_unlock_config(flags); \
63 return res; \
64}
65
66PCI_OP_READ(byte, u8, 1)
67PCI_OP_READ(word, u16, 2)
68PCI_OP_READ(dword, u32, 4)
69PCI_OP_WRITE(byte, u8, 1)
70PCI_OP_WRITE(word, u16, 2)
71PCI_OP_WRITE(dword, u32, 4)
72
73EXPORT_SYMBOL(pci_bus_read_config_byte);
74EXPORT_SYMBOL(pci_bus_read_config_word);
75EXPORT_SYMBOL(pci_bus_read_config_dword);
76EXPORT_SYMBOL(pci_bus_write_config_byte);
77EXPORT_SYMBOL(pci_bus_write_config_word);
78EXPORT_SYMBOL(pci_bus_write_config_dword);
79
80int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
81 int where, int size, u32 *val)
82{
83 void __iomem *addr;
84
85 addr = bus->ops->map_bus(bus, devfn, where);
86 if (!addr)
87 return PCIBIOS_DEVICE_NOT_FOUND;
88
89 if (size == 1)
90 *val = readb(addr);
91 else if (size == 2)
92 *val = readw(addr);
93 else
94 *val = readl(addr);
95
96 return PCIBIOS_SUCCESSFUL;
97}
98EXPORT_SYMBOL_GPL(pci_generic_config_read);
99
100int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
101 int where, int size, u32 val)
102{
103 void __iomem *addr;
104
105 addr = bus->ops->map_bus(bus, devfn, where);
106 if (!addr)
107 return PCIBIOS_DEVICE_NOT_FOUND;
108
109 if (size == 1)
110 writeb(val, addr);
111 else if (size == 2)
112 writew(val, addr);
113 else
114 writel(val, addr);
115
116 return PCIBIOS_SUCCESSFUL;
117}
118EXPORT_SYMBOL_GPL(pci_generic_config_write);
119
120int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
121 int where, int size, u32 *val)
122{
123 void __iomem *addr;
124
125 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
126 if (!addr)
127 return PCIBIOS_DEVICE_NOT_FOUND;
128
129 *val = readl(addr);
130
131 if (size <= 2)
132 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
133
134 return PCIBIOS_SUCCESSFUL;
135}
136EXPORT_SYMBOL_GPL(pci_generic_config_read32);
137
138int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
139 int where, int size, u32 val)
140{
141 void __iomem *addr;
142 u32 mask, tmp;
143
144 addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
145 if (!addr)
146 return PCIBIOS_DEVICE_NOT_FOUND;
147
148 if (size == 4) {
149 writel(val, addr);
150 return PCIBIOS_SUCCESSFUL;
151 }
152
153 /*
154 * In general, hardware that supports only 32-bit writes on PCI is
155 * not spec-compliant. For example, software may perform a 16-bit
156 * write. If the hardware only supports 32-bit accesses, we must
157 * do a 32-bit read, merge in the 16 bits we intend to write,
158 * followed by a 32-bit write. If the 16 bits we *don't* intend to
159 * write happen to have any RW1C (write-one-to-clear) bits set, we
160 * just inadvertently cleared something we shouldn't have.
161 */
162 if (!bus->unsafe_warn) {
163 dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n",
164 size, pci_domain_nr(bus), bus->number,
165 PCI_SLOT(devfn), PCI_FUNC(devfn), where);
166 bus->unsafe_warn = 1;
167 }
168
169 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
170 tmp = readl(addr) & mask;
171 tmp |= val << ((where & 0x3) * 8);
172 writel(tmp, addr);
173
174 return PCIBIOS_SUCCESSFUL;
175}
176EXPORT_SYMBOL_GPL(pci_generic_config_write32);
177
178/**
179 * pci_bus_set_ops - Set raw operations of pci bus
180 * @bus: pci bus struct
181 * @ops: new raw operations
182 *
183 * Return previous raw operations
184 */
185struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
186{
187 struct pci_ops *old_ops;
188 unsigned long flags;
189
190 raw_spin_lock_irqsave(&pci_lock, flags);
191 old_ops = bus->ops;
192 bus->ops = ops;
193 raw_spin_unlock_irqrestore(&pci_lock, flags);
194 return old_ops;
195}
196EXPORT_SYMBOL(pci_bus_set_ops);
197
198/*
199 * The following routines are to prevent the user from accessing PCI config
200 * space when it's unsafe to do so. Some devices require this during BIST and
201 * we're required to prevent it during D-state transitions.
202 *
203 * We have a bit per device to indicate it's blocked and a global wait queue
204 * for callers to sleep on until devices are unblocked.
205 */
206static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
207
208static noinline void pci_wait_cfg(struct pci_dev *dev)
209 __must_hold(&pci_lock)
210{
211 do {
212 raw_spin_unlock_irq(&pci_lock);
213 wait_event(pci_cfg_wait, !dev->block_cfg_access);
214 raw_spin_lock_irq(&pci_lock);
215 } while (dev->block_cfg_access);
216}
217
218/* Returns 0 on success, negative values indicate error. */
219#define PCI_USER_READ_CONFIG(size, type) \
220int pci_user_read_config_##size \
221 (struct pci_dev *dev, int pos, type *val) \
222{ \
223 int ret = PCIBIOS_SUCCESSFUL; \
224 u32 data = -1; \
225 if (PCI_##size##_BAD) \
226 return -EINVAL; \
227 raw_spin_lock_irq(&pci_lock); \
228 if (unlikely(dev->block_cfg_access)) \
229 pci_wait_cfg(dev); \
230 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
231 pos, sizeof(type), &data); \
232 raw_spin_unlock_irq(&pci_lock); \
233 if (ret) \
234 PCI_SET_ERROR_RESPONSE(val); \
235 else \
236 *val = (type)data; \
237 return pcibios_err_to_errno(ret); \
238} \
239EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
240
241/* Returns 0 on success, negative values indicate error. */
242#define PCI_USER_WRITE_CONFIG(size, type) \
243int pci_user_write_config_##size \
244 (struct pci_dev *dev, int pos, type val) \
245{ \
246 int ret = PCIBIOS_SUCCESSFUL; \
247 if (PCI_##size##_BAD) \
248 return -EINVAL; \
249 raw_spin_lock_irq(&pci_lock); \
250 if (unlikely(dev->block_cfg_access)) \
251 pci_wait_cfg(dev); \
252 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
253 pos, sizeof(type), val); \
254 raw_spin_unlock_irq(&pci_lock); \
255 return pcibios_err_to_errno(ret); \
256} \
257EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
258
259PCI_USER_READ_CONFIG(byte, u8)
260PCI_USER_READ_CONFIG(word, u16)
261PCI_USER_READ_CONFIG(dword, u32)
262PCI_USER_WRITE_CONFIG(byte, u8)
263PCI_USER_WRITE_CONFIG(word, u16)
264PCI_USER_WRITE_CONFIG(dword, u32)
265
266/**
267 * pci_cfg_access_lock - Lock PCI config reads/writes
268 * @dev: pci device struct
269 *
270 * When access is locked, any userspace reads or writes to config
271 * space and concurrent lock requests will sleep until access is
272 * allowed via pci_cfg_access_unlock() again.
273 */
274void pci_cfg_access_lock(struct pci_dev *dev)
275{
276 might_sleep();
277
278 raw_spin_lock_irq(&pci_lock);
279 if (dev->block_cfg_access)
280 pci_wait_cfg(dev);
281 dev->block_cfg_access = 1;
282 raw_spin_unlock_irq(&pci_lock);
283}
284EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
285
286/**
287 * pci_cfg_access_trylock - try to lock PCI config reads/writes
288 * @dev: pci device struct
289 *
290 * Same as pci_cfg_access_lock, but will return 0 if access is
291 * already locked, 1 otherwise. This function can be used from
292 * atomic contexts.
293 */
294bool pci_cfg_access_trylock(struct pci_dev *dev)
295{
296 unsigned long flags;
297 bool locked = true;
298
299 raw_spin_lock_irqsave(&pci_lock, flags);
300 if (dev->block_cfg_access)
301 locked = false;
302 else
303 dev->block_cfg_access = 1;
304 raw_spin_unlock_irqrestore(&pci_lock, flags);
305
306 return locked;
307}
308EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
309
310/**
311 * pci_cfg_access_unlock - Unlock PCI config reads/writes
312 * @dev: pci device struct
313 *
314 * This function allows PCI config accesses to resume.
315 */
316void pci_cfg_access_unlock(struct pci_dev *dev)
317{
318 unsigned long flags;
319
320 raw_spin_lock_irqsave(&pci_lock, flags);
321
322 /*
323 * This indicates a problem in the caller, but we don't need
324 * to kill them, unlike a double-block above.
325 */
326 WARN_ON(!dev->block_cfg_access);
327
328 dev->block_cfg_access = 0;
329 raw_spin_unlock_irqrestore(&pci_lock, flags);
330
331 wake_up_all(&pci_cfg_wait);
332}
333EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
334
335static inline int pcie_cap_version(const struct pci_dev *dev)
336{
337 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
338}
339
340bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
341{
342 int type = pci_pcie_type(dev);
343
344 return type == PCI_EXP_TYPE_ENDPOINT ||
345 type == PCI_EXP_TYPE_LEG_END ||
346 type == PCI_EXP_TYPE_ROOT_PORT ||
347 type == PCI_EXP_TYPE_UPSTREAM ||
348 type == PCI_EXP_TYPE_DOWNSTREAM ||
349 type == PCI_EXP_TYPE_PCI_BRIDGE ||
350 type == PCI_EXP_TYPE_PCIE_BRIDGE;
351}
352
353bool pcie_cap_has_lnkctl2(const struct pci_dev *dev)
354{
355 return pcie_cap_has_lnkctl(dev) && pcie_cap_version(dev) > 1;
356}
357
358static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
359{
360 return pcie_downstream_port(dev) &&
361 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
362}
363
364bool pcie_cap_has_rtctl(const struct pci_dev *dev)
365{
366 int type = pci_pcie_type(dev);
367
368 return type == PCI_EXP_TYPE_ROOT_PORT ||
369 type == PCI_EXP_TYPE_RC_EC;
370}
371
372static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
373{
374 if (!pci_is_pcie(dev))
375 return false;
376
377 switch (pos) {
378 case PCI_EXP_FLAGS:
379 return true;
380 case PCI_EXP_DEVCAP:
381 case PCI_EXP_DEVCTL:
382 case PCI_EXP_DEVSTA:
383 return true;
384 case PCI_EXP_LNKCAP:
385 case PCI_EXP_LNKCTL:
386 case PCI_EXP_LNKSTA:
387 return pcie_cap_has_lnkctl(dev);
388 case PCI_EXP_SLTCAP:
389 case PCI_EXP_SLTCTL:
390 case PCI_EXP_SLTSTA:
391 return pcie_cap_has_sltctl(dev);
392 case PCI_EXP_RTCTL:
393 case PCI_EXP_RTCAP:
394 case PCI_EXP_RTSTA:
395 return pcie_cap_has_rtctl(dev);
396 case PCI_EXP_DEVCAP2:
397 case PCI_EXP_DEVCTL2:
398 return pcie_cap_version(dev) > 1;
399 case PCI_EXP_LNKCAP2:
400 case PCI_EXP_LNKCTL2:
401 case PCI_EXP_LNKSTA2:
402 return pcie_cap_has_lnkctl2(dev);
403 default:
404 return false;
405 }
406}
407
408/*
409 * Note that these accessor functions are only for the "PCI Express
410 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
411 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
412 */
413int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
414{
415 int ret;
416
417 *val = 0;
418 if (pos & 1)
419 return PCIBIOS_BAD_REGISTER_NUMBER;
420
421 if (pcie_capability_reg_implemented(dev, pos)) {
422 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
423 /*
424 * Reset *val to 0 if pci_read_config_word() fails; it may
425 * have been written as 0xFFFF (PCI_ERROR_RESPONSE) if the
426 * config read failed on PCI.
427 */
428 if (ret)
429 *val = 0;
430 return ret;
431 }
432
433 /*
434 * For Functions that do not implement the Slot Capabilities,
435 * Slot Status, and Slot Control registers, these spaces must
436 * be hardwired to 0b, with the exception of the Presence Detect
437 * State bit in the Slot Status register of Downstream Ports,
438 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
439 */
440 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
441 pos == PCI_EXP_SLTSTA)
442 *val = PCI_EXP_SLTSTA_PDS;
443
444 return 0;
445}
446EXPORT_SYMBOL(pcie_capability_read_word);
447
448int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
449{
450 int ret;
451
452 *val = 0;
453 if (pos & 3)
454 return PCIBIOS_BAD_REGISTER_NUMBER;
455
456 if (pcie_capability_reg_implemented(dev, pos)) {
457 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
458 /*
459 * Reset *val to 0 if pci_read_config_dword() fails; it may
460 * have been written as 0xFFFFFFFF (PCI_ERROR_RESPONSE) if
461 * the config read failed on PCI.
462 */
463 if (ret)
464 *val = 0;
465 return ret;
466 }
467
468 if (pci_is_pcie(dev) && pcie_downstream_port(dev) &&
469 pos == PCI_EXP_SLTSTA)
470 *val = PCI_EXP_SLTSTA_PDS;
471
472 return 0;
473}
474EXPORT_SYMBOL(pcie_capability_read_dword);
475
476int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
477{
478 if (pos & 1)
479 return PCIBIOS_BAD_REGISTER_NUMBER;
480
481 if (!pcie_capability_reg_implemented(dev, pos))
482 return 0;
483
484 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
485}
486EXPORT_SYMBOL(pcie_capability_write_word);
487
488int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
489{
490 if (pos & 3)
491 return PCIBIOS_BAD_REGISTER_NUMBER;
492
493 if (!pcie_capability_reg_implemented(dev, pos))
494 return 0;
495
496 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
497}
498EXPORT_SYMBOL(pcie_capability_write_dword);
499
500int pcie_capability_clear_and_set_word_unlocked(struct pci_dev *dev, int pos,
501 u16 clear, u16 set)
502{
503 int ret;
504 u16 val;
505
506 ret = pcie_capability_read_word(dev, pos, &val);
507 if (ret)
508 return ret;
509
510 val &= ~clear;
511 val |= set;
512 return pcie_capability_write_word(dev, pos, val);
513}
514EXPORT_SYMBOL(pcie_capability_clear_and_set_word_unlocked);
515
516int pcie_capability_clear_and_set_word_locked(struct pci_dev *dev, int pos,
517 u16 clear, u16 set)
518{
519 unsigned long flags;
520 int ret;
521
522 spin_lock_irqsave(&dev->pcie_cap_lock, flags);
523 ret = pcie_capability_clear_and_set_word_unlocked(dev, pos, clear, set);
524 spin_unlock_irqrestore(&dev->pcie_cap_lock, flags);
525
526 return ret;
527}
528EXPORT_SYMBOL(pcie_capability_clear_and_set_word_locked);
529
530int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
531 u32 clear, u32 set)
532{
533 int ret;
534 u32 val;
535
536 ret = pcie_capability_read_dword(dev, pos, &val);
537 if (ret)
538 return ret;
539
540 val &= ~clear;
541 val |= set;
542 return pcie_capability_write_dword(dev, pos, val);
543}
544EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);
545
546int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val)
547{
548 if (pci_dev_is_disconnected(dev)) {
549 PCI_SET_ERROR_RESPONSE(val);
550 return PCIBIOS_DEVICE_NOT_FOUND;
551 }
552 return pci_bus_read_config_byte(dev->bus, dev->devfn, where, val);
553}
554EXPORT_SYMBOL(pci_read_config_byte);
555
556int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val)
557{
558 if (pci_dev_is_disconnected(dev)) {
559 PCI_SET_ERROR_RESPONSE(val);
560 return PCIBIOS_DEVICE_NOT_FOUND;
561 }
562 return pci_bus_read_config_word(dev->bus, dev->devfn, where, val);
563}
564EXPORT_SYMBOL(pci_read_config_word);
565
566int pci_read_config_dword(const struct pci_dev *dev, int where,
567 u32 *val)
568{
569 if (pci_dev_is_disconnected(dev)) {
570 PCI_SET_ERROR_RESPONSE(val);
571 return PCIBIOS_DEVICE_NOT_FOUND;
572 }
573 return pci_bus_read_config_dword(dev->bus, dev->devfn, where, val);
574}
575EXPORT_SYMBOL(pci_read_config_dword);
576
577int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val)
578{
579 if (pci_dev_is_disconnected(dev))
580 return PCIBIOS_DEVICE_NOT_FOUND;
581 return pci_bus_write_config_byte(dev->bus, dev->devfn, where, val);
582}
583EXPORT_SYMBOL(pci_write_config_byte);
584
585int pci_write_config_word(const struct pci_dev *dev, int where, u16 val)
586{
587 if (pci_dev_is_disconnected(dev))
588 return PCIBIOS_DEVICE_NOT_FOUND;
589 return pci_bus_write_config_word(dev->bus, dev->devfn, where, val);
590}
591EXPORT_SYMBOL(pci_write_config_word);
592
593int pci_write_config_dword(const struct pci_dev *dev, int where,
594 u32 val)
595{
596 if (pci_dev_is_disconnected(dev))
597 return PCIBIOS_DEVICE_NOT_FOUND;
598 return pci_bus_write_config_dword(dev->bus, dev->devfn, where, val);
599}
600EXPORT_SYMBOL(pci_write_config_dword);
601
602void pci_clear_and_set_config_dword(const struct pci_dev *dev, int pos,
603 u32 clear, u32 set)
604{
605 u32 val;
606
607 pci_read_config_dword(dev, pos, &val);
608 val &= ~clear;
609 val |= set;
610 pci_write_config_dword(dev, pos, val);
611}
612EXPORT_SYMBOL(pci_clear_and_set_config_dword);
1#include <linux/delay.h>
2#include <linux/pci.h>
3#include <linux/module.h>
4#include <linux/sched.h>
5#include <linux/slab.h>
6#include <linux/ioport.h>
7#include <linux/wait.h>
8
9#include "pci.h"
10
11/*
12 * This interrupt-safe spinlock protects all accesses to PCI
13 * configuration space.
14 */
15
16DEFINE_RAW_SPINLOCK(pci_lock);
17
18/*
19 * Wrappers for all PCI configuration access functions. They just check
20 * alignment, do locking and call the low-level functions pointed to
21 * by pci_dev->ops.
22 */
23
24#define PCI_byte_BAD 0
25#define PCI_word_BAD (pos & 1)
26#define PCI_dword_BAD (pos & 3)
27
28#define PCI_OP_READ(size,type,len) \
29int pci_bus_read_config_##size \
30 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
31{ \
32 int res; \
33 unsigned long flags; \
34 u32 data = 0; \
35 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
36 raw_spin_lock_irqsave(&pci_lock, flags); \
37 res = bus->ops->read(bus, devfn, pos, len, &data); \
38 *value = (type)data; \
39 raw_spin_unlock_irqrestore(&pci_lock, flags); \
40 return res; \
41}
42
43#define PCI_OP_WRITE(size,type,len) \
44int pci_bus_write_config_##size \
45 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
46{ \
47 int res; \
48 unsigned long flags; \
49 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
50 raw_spin_lock_irqsave(&pci_lock, flags); \
51 res = bus->ops->write(bus, devfn, pos, len, value); \
52 raw_spin_unlock_irqrestore(&pci_lock, flags); \
53 return res; \
54}
55
56PCI_OP_READ(byte, u8, 1)
57PCI_OP_READ(word, u16, 2)
58PCI_OP_READ(dword, u32, 4)
59PCI_OP_WRITE(byte, u8, 1)
60PCI_OP_WRITE(word, u16, 2)
61PCI_OP_WRITE(dword, u32, 4)
62
63EXPORT_SYMBOL(pci_bus_read_config_byte);
64EXPORT_SYMBOL(pci_bus_read_config_word);
65EXPORT_SYMBOL(pci_bus_read_config_dword);
66EXPORT_SYMBOL(pci_bus_write_config_byte);
67EXPORT_SYMBOL(pci_bus_write_config_word);
68EXPORT_SYMBOL(pci_bus_write_config_dword);
69
70/**
71 * pci_bus_set_ops - Set raw operations of pci bus
72 * @bus: pci bus struct
73 * @ops: new raw operations
74 *
75 * Return previous raw operations
76 */
77struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops)
78{
79 struct pci_ops *old_ops;
80 unsigned long flags;
81
82 raw_spin_lock_irqsave(&pci_lock, flags);
83 old_ops = bus->ops;
84 bus->ops = ops;
85 raw_spin_unlock_irqrestore(&pci_lock, flags);
86 return old_ops;
87}
88EXPORT_SYMBOL(pci_bus_set_ops);
89
90/**
91 * pci_read_vpd - Read one entry from Vital Product Data
92 * @dev: pci device struct
93 * @pos: offset in vpd space
94 * @count: number of bytes to read
95 * @buf: pointer to where to store result
96 *
97 */
98ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
99{
100 if (!dev->vpd || !dev->vpd->ops)
101 return -ENODEV;
102 return dev->vpd->ops->read(dev, pos, count, buf);
103}
104EXPORT_SYMBOL(pci_read_vpd);
105
106/**
107 * pci_write_vpd - Write entry to Vital Product Data
108 * @dev: pci device struct
109 * @pos: offset in vpd space
110 * @count: number of bytes to write
111 * @buf: buffer containing write data
112 *
113 */
114ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
115{
116 if (!dev->vpd || !dev->vpd->ops)
117 return -ENODEV;
118 return dev->vpd->ops->write(dev, pos, count, buf);
119}
120EXPORT_SYMBOL(pci_write_vpd);
121
122/*
123 * The following routines are to prevent the user from accessing PCI config
124 * space when it's unsafe to do so. Some devices require this during BIST and
125 * we're required to prevent it during D-state transitions.
126 *
127 * We have a bit per device to indicate it's blocked and a global wait queue
128 * for callers to sleep on until devices are unblocked.
129 */
130static DECLARE_WAIT_QUEUE_HEAD(pci_cfg_wait);
131
132static noinline void pci_wait_cfg(struct pci_dev *dev)
133{
134 DECLARE_WAITQUEUE(wait, current);
135
136 __add_wait_queue(&pci_cfg_wait, &wait);
137 do {
138 set_current_state(TASK_UNINTERRUPTIBLE);
139 raw_spin_unlock_irq(&pci_lock);
140 schedule();
141 raw_spin_lock_irq(&pci_lock);
142 } while (dev->block_cfg_access);
143 __remove_wait_queue(&pci_cfg_wait, &wait);
144}
145
146/* Returns 0 on success, negative values indicate error. */
147#define PCI_USER_READ_CONFIG(size,type) \
148int pci_user_read_config_##size \
149 (struct pci_dev *dev, int pos, type *val) \
150{ \
151 int ret = 0; \
152 u32 data = -1; \
153 if (PCI_##size##_BAD) \
154 return -EINVAL; \
155 raw_spin_lock_irq(&pci_lock); \
156 if (unlikely(dev->block_cfg_access)) \
157 pci_wait_cfg(dev); \
158 ret = dev->bus->ops->read(dev->bus, dev->devfn, \
159 pos, sizeof(type), &data); \
160 raw_spin_unlock_irq(&pci_lock); \
161 *val = (type)data; \
162 if (ret > 0) \
163 ret = -EINVAL; \
164 return ret; \
165} \
166EXPORT_SYMBOL_GPL(pci_user_read_config_##size);
167
168/* Returns 0 on success, negative values indicate error. */
169#define PCI_USER_WRITE_CONFIG(size,type) \
170int pci_user_write_config_##size \
171 (struct pci_dev *dev, int pos, type val) \
172{ \
173 int ret = -EIO; \
174 if (PCI_##size##_BAD) \
175 return -EINVAL; \
176 raw_spin_lock_irq(&pci_lock); \
177 if (unlikely(dev->block_cfg_access)) \
178 pci_wait_cfg(dev); \
179 ret = dev->bus->ops->write(dev->bus, dev->devfn, \
180 pos, sizeof(type), val); \
181 raw_spin_unlock_irq(&pci_lock); \
182 if (ret > 0) \
183 ret = -EINVAL; \
184 return ret; \
185} \
186EXPORT_SYMBOL_GPL(pci_user_write_config_##size);
187
188PCI_USER_READ_CONFIG(byte, u8)
189PCI_USER_READ_CONFIG(word, u16)
190PCI_USER_READ_CONFIG(dword, u32)
191PCI_USER_WRITE_CONFIG(byte, u8)
192PCI_USER_WRITE_CONFIG(word, u16)
193PCI_USER_WRITE_CONFIG(dword, u32)
194
195/* VPD access through PCI 2.2+ VPD capability */
196
197#define PCI_VPD_PCI22_SIZE (PCI_VPD_ADDR_MASK + 1)
198
199struct pci_vpd_pci22 {
200 struct pci_vpd base;
201 struct mutex lock;
202 u16 flag;
203 bool busy;
204 u8 cap;
205};
206
207/*
208 * Wait for last operation to complete.
209 * This code has to spin since there is no other notification from the PCI
210 * hardware. Since the VPD is often implemented by serial attachment to an
211 * EEPROM, it may take many milliseconds to complete.
212 *
213 * Returns 0 on success, negative values indicate error.
214 */
215static int pci_vpd_pci22_wait(struct pci_dev *dev)
216{
217 struct pci_vpd_pci22 *vpd =
218 container_of(dev->vpd, struct pci_vpd_pci22, base);
219 unsigned long timeout = jiffies + HZ/20 + 2;
220 u16 status;
221 int ret;
222
223 if (!vpd->busy)
224 return 0;
225
226 for (;;) {
227 ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
228 &status);
229 if (ret < 0)
230 return ret;
231
232 if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
233 vpd->busy = false;
234 return 0;
235 }
236
237 if (time_after(jiffies, timeout)) {
238 dev_printk(KERN_DEBUG, &dev->dev,
239 "vpd r/w failed. This is likely a firmware "
240 "bug on this device. Contact the card "
241 "vendor for a firmware update.");
242 return -ETIMEDOUT;
243 }
244 if (fatal_signal_pending(current))
245 return -EINTR;
246 if (!cond_resched())
247 udelay(10);
248 }
249}
250
251static ssize_t pci_vpd_pci22_read(struct pci_dev *dev, loff_t pos, size_t count,
252 void *arg)
253{
254 struct pci_vpd_pci22 *vpd =
255 container_of(dev->vpd, struct pci_vpd_pci22, base);
256 int ret;
257 loff_t end = pos + count;
258 u8 *buf = arg;
259
260 if (pos < 0 || pos > vpd->base.len || end > vpd->base.len)
261 return -EINVAL;
262
263 if (mutex_lock_killable(&vpd->lock))
264 return -EINTR;
265
266 ret = pci_vpd_pci22_wait(dev);
267 if (ret < 0)
268 goto out;
269
270 while (pos < end) {
271 u32 val;
272 unsigned int i, skip;
273
274 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
275 pos & ~3);
276 if (ret < 0)
277 break;
278 vpd->busy = true;
279 vpd->flag = PCI_VPD_ADDR_F;
280 ret = pci_vpd_pci22_wait(dev);
281 if (ret < 0)
282 break;
283
284 ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
285 if (ret < 0)
286 break;
287
288 skip = pos & 3;
289 for (i = 0; i < sizeof(u32); i++) {
290 if (i >= skip) {
291 *buf++ = val;
292 if (++pos == end)
293 break;
294 }
295 val >>= 8;
296 }
297 }
298out:
299 mutex_unlock(&vpd->lock);
300 return ret ? ret : count;
301}
302
303static ssize_t pci_vpd_pci22_write(struct pci_dev *dev, loff_t pos, size_t count,
304 const void *arg)
305{
306 struct pci_vpd_pci22 *vpd =
307 container_of(dev->vpd, struct pci_vpd_pci22, base);
308 const u8 *buf = arg;
309 loff_t end = pos + count;
310 int ret = 0;
311
312 if (pos < 0 || (pos & 3) || (count & 3) || end > vpd->base.len)
313 return -EINVAL;
314
315 if (mutex_lock_killable(&vpd->lock))
316 return -EINTR;
317
318 ret = pci_vpd_pci22_wait(dev);
319 if (ret < 0)
320 goto out;
321
322 while (pos < end) {
323 u32 val;
324
325 val = *buf++;
326 val |= *buf++ << 8;
327 val |= *buf++ << 16;
328 val |= *buf++ << 24;
329
330 ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
331 if (ret < 0)
332 break;
333 ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
334 pos | PCI_VPD_ADDR_F);
335 if (ret < 0)
336 break;
337
338 vpd->busy = true;
339 vpd->flag = 0;
340 ret = pci_vpd_pci22_wait(dev);
341 if (ret < 0)
342 break;
343
344 pos += sizeof(u32);
345 }
346out:
347 mutex_unlock(&vpd->lock);
348 return ret ? ret : count;
349}
350
351static void pci_vpd_pci22_release(struct pci_dev *dev)
352{
353 kfree(container_of(dev->vpd, struct pci_vpd_pci22, base));
354}
355
356static const struct pci_vpd_ops pci_vpd_pci22_ops = {
357 .read = pci_vpd_pci22_read,
358 .write = pci_vpd_pci22_write,
359 .release = pci_vpd_pci22_release,
360};
361
362int pci_vpd_pci22_init(struct pci_dev *dev)
363{
364 struct pci_vpd_pci22 *vpd;
365 u8 cap;
366
367 cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
368 if (!cap)
369 return -ENODEV;
370 vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
371 if (!vpd)
372 return -ENOMEM;
373
374 vpd->base.len = PCI_VPD_PCI22_SIZE;
375 vpd->base.ops = &pci_vpd_pci22_ops;
376 mutex_init(&vpd->lock);
377 vpd->cap = cap;
378 vpd->busy = false;
379 dev->vpd = &vpd->base;
380 return 0;
381}
382
383/**
384 * pci_cfg_access_lock - Lock PCI config reads/writes
385 * @dev: pci device struct
386 *
387 * When access is locked, any userspace reads or writes to config
388 * space and concurrent lock requests will sleep until access is
389 * allowed via pci_cfg_access_unlocked again.
390 */
391void pci_cfg_access_lock(struct pci_dev *dev)
392{
393 might_sleep();
394
395 raw_spin_lock_irq(&pci_lock);
396 if (dev->block_cfg_access)
397 pci_wait_cfg(dev);
398 dev->block_cfg_access = 1;
399 raw_spin_unlock_irq(&pci_lock);
400}
401EXPORT_SYMBOL_GPL(pci_cfg_access_lock);
402
403/**
404 * pci_cfg_access_trylock - try to lock PCI config reads/writes
405 * @dev: pci device struct
406 *
407 * Same as pci_cfg_access_lock, but will return 0 if access is
408 * already locked, 1 otherwise. This function can be used from
409 * atomic contexts.
410 */
411bool pci_cfg_access_trylock(struct pci_dev *dev)
412{
413 unsigned long flags;
414 bool locked = true;
415
416 raw_spin_lock_irqsave(&pci_lock, flags);
417 if (dev->block_cfg_access)
418 locked = false;
419 else
420 dev->block_cfg_access = 1;
421 raw_spin_unlock_irqrestore(&pci_lock, flags);
422
423 return locked;
424}
425EXPORT_SYMBOL_GPL(pci_cfg_access_trylock);
426
427/**
428 * pci_cfg_access_unlock - Unlock PCI config reads/writes
429 * @dev: pci device struct
430 *
431 * This function allows PCI config accesses to resume.
432 */
433void pci_cfg_access_unlock(struct pci_dev *dev)
434{
435 unsigned long flags;
436
437 raw_spin_lock_irqsave(&pci_lock, flags);
438
439 /* This indicates a problem in the caller, but we don't need
440 * to kill them, unlike a double-block above. */
441 WARN_ON(!dev->block_cfg_access);
442
443 dev->block_cfg_access = 0;
444 wake_up_all(&pci_cfg_wait);
445 raw_spin_unlock_irqrestore(&pci_lock, flags);
446}
447EXPORT_SYMBOL_GPL(pci_cfg_access_unlock);
448
449static inline int pcie_cap_version(const struct pci_dev *dev)
450{
451 return pcie_caps_reg(dev) & PCI_EXP_FLAGS_VERS;
452}
453
454static inline bool pcie_cap_has_lnkctl(const struct pci_dev *dev)
455{
456 int type = pci_pcie_type(dev);
457
458 return type == PCI_EXP_TYPE_ENDPOINT ||
459 type == PCI_EXP_TYPE_LEG_END ||
460 type == PCI_EXP_TYPE_ROOT_PORT ||
461 type == PCI_EXP_TYPE_UPSTREAM ||
462 type == PCI_EXP_TYPE_DOWNSTREAM ||
463 type == PCI_EXP_TYPE_PCI_BRIDGE ||
464 type == PCI_EXP_TYPE_PCIE_BRIDGE;
465}
466
467static inline bool pcie_cap_has_sltctl(const struct pci_dev *dev)
468{
469 int type = pci_pcie_type(dev);
470
471 return (type == PCI_EXP_TYPE_ROOT_PORT ||
472 type == PCI_EXP_TYPE_DOWNSTREAM) &&
473 pcie_caps_reg(dev) & PCI_EXP_FLAGS_SLOT;
474}
475
476static inline bool pcie_cap_has_rtctl(const struct pci_dev *dev)
477{
478 int type = pci_pcie_type(dev);
479
480 return type == PCI_EXP_TYPE_ROOT_PORT ||
481 type == PCI_EXP_TYPE_RC_EC;
482}
483
484static bool pcie_capability_reg_implemented(struct pci_dev *dev, int pos)
485{
486 if (!pci_is_pcie(dev))
487 return false;
488
489 switch (pos) {
490 case PCI_EXP_FLAGS:
491 return true;
492 case PCI_EXP_DEVCAP:
493 case PCI_EXP_DEVCTL:
494 case PCI_EXP_DEVSTA:
495 return true;
496 case PCI_EXP_LNKCAP:
497 case PCI_EXP_LNKCTL:
498 case PCI_EXP_LNKSTA:
499 return pcie_cap_has_lnkctl(dev);
500 case PCI_EXP_SLTCAP:
501 case PCI_EXP_SLTCTL:
502 case PCI_EXP_SLTSTA:
503 return pcie_cap_has_sltctl(dev);
504 case PCI_EXP_RTCTL:
505 case PCI_EXP_RTCAP:
506 case PCI_EXP_RTSTA:
507 return pcie_cap_has_rtctl(dev);
508 case PCI_EXP_DEVCAP2:
509 case PCI_EXP_DEVCTL2:
510 case PCI_EXP_LNKCAP2:
511 case PCI_EXP_LNKCTL2:
512 case PCI_EXP_LNKSTA2:
513 return pcie_cap_version(dev) > 1;
514 default:
515 return false;
516 }
517}
518
519/*
520 * Note that these accessor functions are only for the "PCI Express
521 * Capability" (see PCIe spec r3.0, sec 7.8). They do not apply to the
522 * other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.)
523 */
524int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val)
525{
526 int ret;
527
528 *val = 0;
529 if (pos & 1)
530 return -EINVAL;
531
532 if (pcie_capability_reg_implemented(dev, pos)) {
533 ret = pci_read_config_word(dev, pci_pcie_cap(dev) + pos, val);
534 /*
535 * Reset *val to 0 if pci_read_config_word() fails, it may
536 * have been written as 0xFFFF if hardware error happens
537 * during pci_read_config_word().
538 */
539 if (ret)
540 *val = 0;
541 return ret;
542 }
543
544 /*
545 * For Functions that do not implement the Slot Capabilities,
546 * Slot Status, and Slot Control registers, these spaces must
547 * be hardwired to 0b, with the exception of the Presence Detect
548 * State bit in the Slot Status register of Downstream Ports,
549 * which must be hardwired to 1b. (PCIe Base Spec 3.0, sec 7.8)
550 */
551 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTSTA &&
552 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
553 *val = PCI_EXP_SLTSTA_PDS;
554 }
555
556 return 0;
557}
558EXPORT_SYMBOL(pcie_capability_read_word);
559
560int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val)
561{
562 int ret;
563
564 *val = 0;
565 if (pos & 3)
566 return -EINVAL;
567
568 if (pcie_capability_reg_implemented(dev, pos)) {
569 ret = pci_read_config_dword(dev, pci_pcie_cap(dev) + pos, val);
570 /*
571 * Reset *val to 0 if pci_read_config_dword() fails, it may
572 * have been written as 0xFFFFFFFF if hardware error happens
573 * during pci_read_config_dword().
574 */
575 if (ret)
576 *val = 0;
577 return ret;
578 }
579
580 if (pci_is_pcie(dev) && pos == PCI_EXP_SLTCTL &&
581 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM) {
582 *val = PCI_EXP_SLTSTA_PDS;
583 }
584
585 return 0;
586}
587EXPORT_SYMBOL(pcie_capability_read_dword);
588
589int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val)
590{
591 if (pos & 1)
592 return -EINVAL;
593
594 if (!pcie_capability_reg_implemented(dev, pos))
595 return 0;
596
597 return pci_write_config_word(dev, pci_pcie_cap(dev) + pos, val);
598}
599EXPORT_SYMBOL(pcie_capability_write_word);
600
601int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val)
602{
603 if (pos & 3)
604 return -EINVAL;
605
606 if (!pcie_capability_reg_implemented(dev, pos))
607 return 0;
608
609 return pci_write_config_dword(dev, pci_pcie_cap(dev) + pos, val);
610}
611EXPORT_SYMBOL(pcie_capability_write_dword);
612
613int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
614 u16 clear, u16 set)
615{
616 int ret;
617 u16 val;
618
619 ret = pcie_capability_read_word(dev, pos, &val);
620 if (!ret) {
621 val &= ~clear;
622 val |= set;
623 ret = pcie_capability_write_word(dev, pos, val);
624 }
625
626 return ret;
627}
628EXPORT_SYMBOL(pcie_capability_clear_and_set_word);
629
630int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
631 u32 clear, u32 set)
632{
633 int ret;
634 u32 val;
635
636 ret = pcie_capability_read_dword(dev, pos, &val);
637 if (!ret) {
638 val &= ~clear;
639 val |= set;
640 ret = pcie_capability_write_dword(dev, pos, val);
641 }
642
643 return ret;
644}
645EXPORT_SYMBOL(pcie_capability_clear_and_set_dword);