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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
14#include <linux/interrupt.h>
15#include <linux/tcp.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
24#include <linux/pm_qos.h>
25#include <linux/pm_runtime.h>
26#include <linux/prefetch.h>
27#include <linux/suspend.h>
28
29#include "e1000.h"
30#define CREATE_TRACE_POINTS
31#include "e1000e_trace.h"
32
33char e1000e_driver_name[] = "e1000e";
34
35#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
36static int debug = -1;
37module_param(debug, int, 0);
38MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
39
40static const struct e1000_info *e1000_info_tbl[] = {
41 [board_82571] = &e1000_82571_info,
42 [board_82572] = &e1000_82572_info,
43 [board_82573] = &e1000_82573_info,
44 [board_82574] = &e1000_82574_info,
45 [board_82583] = &e1000_82583_info,
46 [board_80003es2lan] = &e1000_es2_info,
47 [board_ich8lan] = &e1000_ich8_info,
48 [board_ich9lan] = &e1000_ich9_info,
49 [board_ich10lan] = &e1000_ich10_info,
50 [board_pchlan] = &e1000_pch_info,
51 [board_pch2lan] = &e1000_pch2_info,
52 [board_pch_lpt] = &e1000_pch_lpt_info,
53 [board_pch_spt] = &e1000_pch_spt_info,
54 [board_pch_cnp] = &e1000_pch_cnp_info,
55 [board_pch_tgp] = &e1000_pch_tgp_info,
56 [board_pch_adp] = &e1000_pch_adp_info,
57 [board_pch_mtp] = &e1000_pch_mtp_info,
58};
59
60struct e1000_reg_info {
61 u32 ofs;
62 char *name;
63};
64
65static const struct e1000_reg_info e1000_reg_info_tbl[] = {
66 /* General Registers */
67 {E1000_CTRL, "CTRL"},
68 {E1000_STATUS, "STATUS"},
69 {E1000_CTRL_EXT, "CTRL_EXT"},
70
71 /* Interrupt Registers */
72 {E1000_ICR, "ICR"},
73
74 /* Rx Registers */
75 {E1000_RCTL, "RCTL"},
76 {E1000_RDLEN(0), "RDLEN"},
77 {E1000_RDH(0), "RDH"},
78 {E1000_RDT(0), "RDT"},
79 {E1000_RDTR, "RDTR"},
80 {E1000_RXDCTL(0), "RXDCTL"},
81 {E1000_ERT, "ERT"},
82 {E1000_RDBAL(0), "RDBAL"},
83 {E1000_RDBAH(0), "RDBAH"},
84 {E1000_RDFH, "RDFH"},
85 {E1000_RDFT, "RDFT"},
86 {E1000_RDFHS, "RDFHS"},
87 {E1000_RDFTS, "RDFTS"},
88 {E1000_RDFPC, "RDFPC"},
89
90 /* Tx Registers */
91 {E1000_TCTL, "TCTL"},
92 {E1000_TDBAL(0), "TDBAL"},
93 {E1000_TDBAH(0), "TDBAH"},
94 {E1000_TDLEN(0), "TDLEN"},
95 {E1000_TDH(0), "TDH"},
96 {E1000_TDT(0), "TDT"},
97 {E1000_TIDV, "TIDV"},
98 {E1000_TXDCTL(0), "TXDCTL"},
99 {E1000_TADV, "TADV"},
100 {E1000_TARC(0), "TARC"},
101 {E1000_TDFH, "TDFH"},
102 {E1000_TDFT, "TDFT"},
103 {E1000_TDFHS, "TDFHS"},
104 {E1000_TDFTS, "TDFTS"},
105 {E1000_TDFPC, "TDFPC"},
106
107 /* List Terminator */
108 {0, NULL}
109};
110
111/**
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
113 * @hw: pointer to the HW structure
114 *
115 * When updating the MAC CSR registers, the Manageability Engine (ME) could
116 * be accessing the registers at the same time. Normally, this is handled in
117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
118 * accesses later than it should which could result in the register to have
119 * an incorrect value. Workaround this by checking the FWSM register which
120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
121 * and try again a number of times.
122 **/
123static void __ew32_prepare(struct e1000_hw *hw)
124{
125 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
126
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
128 udelay(50);
129}
130
131void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
132{
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
134 __ew32_prepare(hw);
135
136 writel(val, hw->hw_addr + reg);
137}
138
139/**
140 * e1000_regdump - register printout routine
141 * @hw: pointer to the HW structure
142 * @reginfo: pointer to the register info table
143 **/
144static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
145{
146 int n = 0;
147 char rname[16];
148 u32 regs[8];
149
150 switch (reginfo->ofs) {
151 case E1000_RXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_RXDCTL(n));
154 break;
155 case E1000_TXDCTL(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TXDCTL(n));
158 break;
159 case E1000_TARC(0):
160 for (n = 0; n < 2; n++)
161 regs[n] = __er32(hw, E1000_TARC(n));
162 break;
163 default:
164 pr_info("%-15s %08x\n",
165 reginfo->name, __er32(hw, reginfo->ofs));
166 return;
167 }
168
169 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
170 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
171}
172
173static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
174 struct e1000_buffer *bi)
175{
176 int i;
177 struct e1000_ps_page *ps_page;
178
179 for (i = 0; i < adapter->rx_ps_pages; i++) {
180 ps_page = &bi->ps_pages[i];
181
182 if (ps_page->page) {
183 pr_info("packet dump for ps_page %d:\n", i);
184 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
185 16, 1, page_address(ps_page->page),
186 PAGE_SIZE, true);
187 }
188 }
189}
190
191/**
192 * e1000e_dump - Print registers, Tx-ring and Rx-ring
193 * @adapter: board private structure
194 **/
195static void e1000e_dump(struct e1000_adapter *adapter)
196{
197 struct net_device *netdev = adapter->netdev;
198 struct e1000_hw *hw = &adapter->hw;
199 struct e1000_reg_info *reginfo;
200 struct e1000_ring *tx_ring = adapter->tx_ring;
201 struct e1000_tx_desc *tx_desc;
202 struct my_u0 {
203 __le64 a;
204 __le64 b;
205 } *u0;
206 struct e1000_buffer *buffer_info;
207 struct e1000_ring *rx_ring = adapter->rx_ring;
208 union e1000_rx_desc_packet_split *rx_desc_ps;
209 union e1000_rx_desc_extended *rx_desc;
210 struct my_u1 {
211 __le64 a;
212 __le64 b;
213 __le64 c;
214 __le64 d;
215 } *u1;
216 u32 staterr;
217 int i = 0;
218
219 if (!netif_msg_hw(adapter))
220 return;
221
222 /* Print netdevice Info */
223 if (netdev) {
224 dev_info(&adapter->pdev->dev, "Net device Info\n");
225 pr_info("Device Name state trans_start\n");
226 pr_info("%-15s %016lX %016lX\n", netdev->name,
227 netdev->state, dev_trans_start(netdev));
228 }
229
230 /* Print Registers */
231 dev_info(&adapter->pdev->dev, "Register Dump\n");
232 pr_info(" Register Name Value\n");
233 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
234 reginfo->name; reginfo++) {
235 e1000_regdump(hw, reginfo);
236 }
237
238 /* Print Tx Ring Summary */
239 if (!netdev || !netif_running(netdev))
240 return;
241
242 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
243 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
244 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
245 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
246 0, tx_ring->next_to_use, tx_ring->next_to_clean,
247 (unsigned long long)buffer_info->dma,
248 buffer_info->length,
249 buffer_info->next_to_watch,
250 (unsigned long long)buffer_info->time_stamp);
251
252 /* Print Tx Ring */
253 if (!netif_msg_tx_done(adapter))
254 goto rx_ring_summary;
255
256 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
257
258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
259 *
260 * Legacy Transmit Descriptor
261 * +--------------------------------------------------------------+
262 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
263 * +--------------------------------------------------------------+
264 * 8 | Special | CSS | Status | CMD | CSO | Length |
265 * +--------------------------------------------------------------+
266 * 63 48 47 36 35 32 31 24 23 16 15 0
267 *
268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
269 * 63 48 47 40 39 32 31 16 15 8 7 0
270 * +----------------------------------------------------------------+
271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
272 * +----------------------------------------------------------------+
273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
274 * +----------------------------------------------------------------+
275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
276 *
277 * Extended Data Descriptor (DTYP=0x1)
278 * +----------------------------------------------------------------+
279 * 0 | Buffer Address [63:0] |
280 * +----------------------------------------------------------------+
281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
282 * +----------------------------------------------------------------+
283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
284 */
285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
288 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
289 const char *next_desc;
290 tx_desc = E1000_TX_DESC(*tx_ring, i);
291 buffer_info = &tx_ring->buffer_info[i];
292 u0 = (struct my_u0 *)tx_desc;
293 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
294 next_desc = " NTC/U";
295 else if (i == tx_ring->next_to_use)
296 next_desc = " NTU";
297 else if (i == tx_ring->next_to_clean)
298 next_desc = " NTC";
299 else
300 next_desc = "";
301 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
302 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
303 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
304 i,
305 (unsigned long long)le64_to_cpu(u0->a),
306 (unsigned long long)le64_to_cpu(u0->b),
307 (unsigned long long)buffer_info->dma,
308 buffer_info->length, buffer_info->next_to_watch,
309 (unsigned long long)buffer_info->time_stamp,
310 buffer_info->skb, next_desc);
311
312 if (netif_msg_pktdata(adapter) && buffer_info->skb)
313 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
314 16, 1, buffer_info->skb->data,
315 buffer_info->skb->len, true);
316 }
317
318 /* Print Rx Ring Summary */
319rx_ring_summary:
320 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
321 pr_info("Queue [NTU] [NTC]\n");
322 pr_info(" %5d %5X %5X\n",
323 0, rx_ring->next_to_use, rx_ring->next_to_clean);
324
325 /* Print Rx Ring */
326 if (!netif_msg_rx_status(adapter))
327 return;
328
329 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
330 switch (adapter->rx_ps_pages) {
331 case 1:
332 case 2:
333 case 3:
334 /* [Extended] Packet Split Receive Descriptor Format
335 *
336 * +-----------------------------------------------------+
337 * 0 | Buffer Address 0 [63:0] |
338 * +-----------------------------------------------------+
339 * 8 | Buffer Address 1 [63:0] |
340 * +-----------------------------------------------------+
341 * 16 | Buffer Address 2 [63:0] |
342 * +-----------------------------------------------------+
343 * 24 | Buffer Address 3 [63:0] |
344 * +-----------------------------------------------------+
345 */
346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
347 /* [Extended] Receive Descriptor (Write-Back) Format
348 *
349 * 63 48 47 32 31 13 12 8 7 4 3 0
350 * +------------------------------------------------------+
351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
352 * | Checksum | Ident | | Queue | | Type |
353 * +------------------------------------------------------+
354 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
355 * +------------------------------------------------------+
356 * 63 48 47 32 31 20 19 0
357 */
358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
359 for (i = 0; i < rx_ring->count; i++) {
360 const char *next_desc;
361 buffer_info = &rx_ring->buffer_info[i];
362 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
363 u1 = (struct my_u1 *)rx_desc_ps;
364 staterr =
365 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
366
367 if (i == rx_ring->next_to_use)
368 next_desc = " NTU";
369 else if (i == rx_ring->next_to_clean)
370 next_desc = " NTC";
371 else
372 next_desc = "";
373
374 if (staterr & E1000_RXD_STAT_DD) {
375 /* Descriptor Done */
376 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
377 "RWB", i,
378 (unsigned long long)le64_to_cpu(u1->a),
379 (unsigned long long)le64_to_cpu(u1->b),
380 (unsigned long long)le64_to_cpu(u1->c),
381 (unsigned long long)le64_to_cpu(u1->d),
382 buffer_info->skb, next_desc);
383 } else {
384 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
385 "R ", i,
386 (unsigned long long)le64_to_cpu(u1->a),
387 (unsigned long long)le64_to_cpu(u1->b),
388 (unsigned long long)le64_to_cpu(u1->c),
389 (unsigned long long)le64_to_cpu(u1->d),
390 (unsigned long long)buffer_info->dma,
391 buffer_info->skb, next_desc);
392
393 if (netif_msg_pktdata(adapter))
394 e1000e_dump_ps_pages(adapter,
395 buffer_info);
396 }
397 }
398 break;
399 default:
400 case 0:
401 /* Extended Receive Descriptor (Read) Format
402 *
403 * +-----------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +-----------------------------------------------------+
406 * 8 | Reserved |
407 * +-----------------------------------------------------+
408 */
409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
410 /* Extended Receive Descriptor (Write-Back) Format
411 *
412 * 63 48 47 32 31 24 23 4 3 0
413 * +------------------------------------------------------+
414 * | RSS Hash | | | |
415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
416 * | Packet | IP | | | Type |
417 * | Checksum | Ident | | | |
418 * +------------------------------------------------------+
419 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
420 * +------------------------------------------------------+
421 * 63 48 47 32 31 20 19 0
422 */
423 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
424
425 for (i = 0; i < rx_ring->count; i++) {
426 const char *next_desc;
427
428 buffer_info = &rx_ring->buffer_info[i];
429 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
430 u1 = (struct my_u1 *)rx_desc;
431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
432
433 if (i == rx_ring->next_to_use)
434 next_desc = " NTU";
435 else if (i == rx_ring->next_to_clean)
436 next_desc = " NTC";
437 else
438 next_desc = "";
439
440 if (staterr & E1000_RXD_STAT_DD) {
441 /* Descriptor Done */
442 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
443 "RWB", i,
444 (unsigned long long)le64_to_cpu(u1->a),
445 (unsigned long long)le64_to_cpu(u1->b),
446 buffer_info->skb, next_desc);
447 } else {
448 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
449 "R ", i,
450 (unsigned long long)le64_to_cpu(u1->a),
451 (unsigned long long)le64_to_cpu(u1->b),
452 (unsigned long long)buffer_info->dma,
453 buffer_info->skb, next_desc);
454
455 if (netif_msg_pktdata(adapter) &&
456 buffer_info->skb)
457 print_hex_dump(KERN_INFO, "",
458 DUMP_PREFIX_ADDRESS, 16,
459 1,
460 buffer_info->skb->data,
461 adapter->rx_buffer_len,
462 true);
463 }
464 }
465 }
466}
467
468/**
469 * e1000_desc_unused - calculate if we have unused descriptors
470 * @ring: pointer to ring struct to perform calculation on
471 **/
472static int e1000_desc_unused(struct e1000_ring *ring)
473{
474 if (ring->next_to_clean > ring->next_to_use)
475 return ring->next_to_clean - ring->next_to_use - 1;
476
477 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478}
479
480/**
481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482 * @adapter: board private structure
483 * @hwtstamps: time stamp structure to update
484 * @systim: unsigned 64bit system time value.
485 *
486 * Convert the system time value stored in the RX/TXSTMP registers into a
487 * hwtstamp which can be used by the upper level time stamping functions.
488 *
489 * The 'systim_lock' spinlock is used to protect the consistency of the
490 * system time value. This is needed because reading the 64 bit time
491 * value involves reading two 32 bit registers. The first read latches the
492 * value.
493 **/
494static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 struct skb_shared_hwtstamps *hwtstamps,
496 u64 systim)
497{
498 u64 ns;
499 unsigned long flags;
500
501 spin_lock_irqsave(&adapter->systim_lock, flags);
502 ns = timecounter_cyc2time(&adapter->tc, systim);
503 spin_unlock_irqrestore(&adapter->systim_lock, flags);
504
505 memset(hwtstamps, 0, sizeof(*hwtstamps));
506 hwtstamps->hwtstamp = ns_to_ktime(ns);
507}
508
509/**
510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511 * @adapter: board private structure
512 * @status: descriptor extended error and status field
513 * @skb: particular skb to include time stamp
514 *
515 * If the time stamp is valid, convert it into the timecounter ns value
516 * and store that result into the shhwtstamps structure which is passed
517 * up the network stack.
518 **/
519static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 struct sk_buff *skb)
521{
522 struct e1000_hw *hw = &adapter->hw;
523 u64 rxstmp;
524
525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 !(status & E1000_RXDEXT_STATERR_TST) ||
527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 return;
529
530 /* The Rx time stamp registers contain the time stamp. No other
531 * received packet will be time stamped until the Rx time stamp
532 * registers are read. Because only one packet can be time stamped
533 * at a time, the register values must belong to this packet and
534 * therefore none of the other additional attributes need to be
535 * compared.
536 */
537 rxstmp = (u64)er32(RXSTMPL);
538 rxstmp |= (u64)er32(RXSTMPH) << 32;
539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
540
541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542}
543
544/**
545 * e1000_receive_skb - helper function to handle Rx indications
546 * @adapter: board private structure
547 * @netdev: pointer to netdev struct
548 * @staterr: descriptor extended error and status field as written by hardware
549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
550 * @skb: pointer to sk_buff to be indicated to stack
551 **/
552static void e1000_receive_skb(struct e1000_adapter *adapter,
553 struct net_device *netdev, struct sk_buff *skb,
554 u32 staterr, __le16 vlan)
555{
556 u16 tag = le16_to_cpu(vlan);
557
558 e1000e_rx_hwtstamp(adapter, staterr, skb);
559
560 skb->protocol = eth_type_trans(skb, netdev);
561
562 if (staterr & E1000_RXD_STAT_VP)
563 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
564
565 napi_gro_receive(&adapter->napi, skb);
566}
567
568/**
569 * e1000_rx_checksum - Receive Checksum Offload
570 * @adapter: board private structure
571 * @status_err: receive descriptor status and error fields
572 * @skb: socket buffer with received data
573 **/
574static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
575 struct sk_buff *skb)
576{
577 u16 status = (u16)status_err;
578 u8 errors = (u8)(status_err >> 24);
579
580 skb_checksum_none_assert(skb);
581
582 /* Rx checksum disabled */
583 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 return;
585
586 /* Ignore Checksum bit is set */
587 if (status & E1000_RXD_STAT_IXSM)
588 return;
589
590 /* TCP/UDP checksum error bit or IP checksum error bit is set */
591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
592 /* let the stack verify checksum errors */
593 adapter->hw_csum_err++;
594 return;
595 }
596
597 /* TCP/UDP Checksum has not been calculated */
598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 return;
600
601 /* It must be a TCP or UDP packet with a valid checksum */
602 skb->ip_summed = CHECKSUM_UNNECESSARY;
603 adapter->hw_csum_good++;
604}
605
606static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
607{
608 struct e1000_adapter *adapter = rx_ring->adapter;
609 struct e1000_hw *hw = &adapter->hw;
610
611 __ew32_prepare(hw);
612 writel(i, rx_ring->tail);
613
614 if (unlikely(i != readl(rx_ring->tail))) {
615 u32 rctl = er32(RCTL);
616
617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 e_err("ME firmware caused invalid RDT - resetting\n");
619 schedule_work(&adapter->reset_task);
620 }
621}
622
623static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
624{
625 struct e1000_adapter *adapter = tx_ring->adapter;
626 struct e1000_hw *hw = &adapter->hw;
627
628 __ew32_prepare(hw);
629 writel(i, tx_ring->tail);
630
631 if (unlikely(i != readl(tx_ring->tail))) {
632 u32 tctl = er32(TCTL);
633
634 ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 e_err("ME firmware caused invalid TDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638}
639
640/**
641 * e1000_alloc_rx_buffers - Replace used receive buffers
642 * @rx_ring: Rx descriptor ring
643 * @cleaned_count: number to reallocate
644 * @gfp: flags for allocation
645 **/
646static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
647 int cleaned_count, gfp_t gfp)
648{
649 struct e1000_adapter *adapter = rx_ring->adapter;
650 struct net_device *netdev = adapter->netdev;
651 struct pci_dev *pdev = adapter->pdev;
652 union e1000_rx_desc_extended *rx_desc;
653 struct e1000_buffer *buffer_info;
654 struct sk_buff *skb;
655 unsigned int i;
656 unsigned int bufsz = adapter->rx_buffer_len;
657
658 i = rx_ring->next_to_use;
659 buffer_info = &rx_ring->buffer_info[i];
660
661 while (cleaned_count--) {
662 skb = buffer_info->skb;
663 if (skb) {
664 skb_trim(skb, 0);
665 goto map_skb;
666 }
667
668 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
669 if (!skb) {
670 /* Better luck next round */
671 adapter->alloc_rx_buff_failed++;
672 break;
673 }
674
675 buffer_info->skb = skb;
676map_skb:
677 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
678 adapter->rx_buffer_len,
679 DMA_FROM_DEVICE);
680 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
681 dev_err(&pdev->dev, "Rx DMA map failed\n");
682 adapter->rx_dma_failed++;
683 break;
684 }
685
686 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
687 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
688
689 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
690 /* Force memory writes to complete before letting h/w
691 * know there are new descriptors to fetch. (Only
692 * applicable for weak-ordered memory model archs,
693 * such as IA-64).
694 */
695 wmb();
696 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
697 e1000e_update_rdt_wa(rx_ring, i);
698 else
699 writel(i, rx_ring->tail);
700 }
701 i++;
702 if (i == rx_ring->count)
703 i = 0;
704 buffer_info = &rx_ring->buffer_info[i];
705 }
706
707 rx_ring->next_to_use = i;
708}
709
710/**
711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
712 * @rx_ring: Rx descriptor ring
713 * @cleaned_count: number to reallocate
714 * @gfp: flags for allocation
715 **/
716static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
717 int cleaned_count, gfp_t gfp)
718{
719 struct e1000_adapter *adapter = rx_ring->adapter;
720 struct net_device *netdev = adapter->netdev;
721 struct pci_dev *pdev = adapter->pdev;
722 union e1000_rx_desc_packet_split *rx_desc;
723 struct e1000_buffer *buffer_info;
724 struct e1000_ps_page *ps_page;
725 struct sk_buff *skb;
726 unsigned int i, j;
727
728 i = rx_ring->next_to_use;
729 buffer_info = &rx_ring->buffer_info[i];
730
731 while (cleaned_count--) {
732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
733
734 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
735 ps_page = &buffer_info->ps_pages[j];
736 if (j >= adapter->rx_ps_pages) {
737 /* all unused desc entries get hw null ptr */
738 rx_desc->read.buffer_addr[j + 1] =
739 ~cpu_to_le64(0);
740 continue;
741 }
742 if (!ps_page->page) {
743 ps_page->page = alloc_page(gfp);
744 if (!ps_page->page) {
745 adapter->alloc_rx_buff_failed++;
746 goto no_buffers;
747 }
748 ps_page->dma = dma_map_page(&pdev->dev,
749 ps_page->page,
750 0, PAGE_SIZE,
751 DMA_FROM_DEVICE);
752 if (dma_mapping_error(&pdev->dev,
753 ps_page->dma)) {
754 dev_err(&adapter->pdev->dev,
755 "Rx DMA page map failed\n");
756 adapter->rx_dma_failed++;
757 goto no_buffers;
758 }
759 }
760 /* Refresh the desc even if buffer_addrs
761 * didn't change because each write-back
762 * erases this info.
763 */
764 rx_desc->read.buffer_addr[j + 1] =
765 cpu_to_le64(ps_page->dma);
766 }
767
768 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
769 gfp);
770
771 if (!skb) {
772 adapter->alloc_rx_buff_failed++;
773 break;
774 }
775
776 buffer_info->skb = skb;
777 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
778 adapter->rx_ps_bsize0,
779 DMA_FROM_DEVICE);
780 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
781 dev_err(&pdev->dev, "Rx DMA map failed\n");
782 adapter->rx_dma_failed++;
783 /* cleanup skb */
784 dev_kfree_skb_any(skb);
785 buffer_info->skb = NULL;
786 break;
787 }
788
789 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
790
791 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
792 /* Force memory writes to complete before letting h/w
793 * know there are new descriptors to fetch. (Only
794 * applicable for weak-ordered memory model archs,
795 * such as IA-64).
796 */
797 wmb();
798 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
799 e1000e_update_rdt_wa(rx_ring, i << 1);
800 else
801 writel(i << 1, rx_ring->tail);
802 }
803
804 i++;
805 if (i == rx_ring->count)
806 i = 0;
807 buffer_info = &rx_ring->buffer_info[i];
808 }
809
810no_buffers:
811 rx_ring->next_to_use = i;
812}
813
814/**
815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
816 * @rx_ring: Rx descriptor ring
817 * @cleaned_count: number of buffers to allocate this pass
818 * @gfp: flags for allocation
819 **/
820
821static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
822 int cleaned_count, gfp_t gfp)
823{
824 struct e1000_adapter *adapter = rx_ring->adapter;
825 struct net_device *netdev = adapter->netdev;
826 struct pci_dev *pdev = adapter->pdev;
827 union e1000_rx_desc_extended *rx_desc;
828 struct e1000_buffer *buffer_info;
829 struct sk_buff *skb;
830 unsigned int i;
831 unsigned int bufsz = 256 - 16; /* for skb_reserve */
832
833 i = rx_ring->next_to_use;
834 buffer_info = &rx_ring->buffer_info[i];
835
836 while (cleaned_count--) {
837 skb = buffer_info->skb;
838 if (skb) {
839 skb_trim(skb, 0);
840 goto check_page;
841 }
842
843 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
844 if (unlikely(!skb)) {
845 /* Better luck next round */
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849
850 buffer_info->skb = skb;
851check_page:
852 /* allocate a new page if necessary */
853 if (!buffer_info->page) {
854 buffer_info->page = alloc_page(gfp);
855 if (unlikely(!buffer_info->page)) {
856 adapter->alloc_rx_buff_failed++;
857 break;
858 }
859 }
860
861 if (!buffer_info->dma) {
862 buffer_info->dma = dma_map_page(&pdev->dev,
863 buffer_info->page, 0,
864 PAGE_SIZE,
865 DMA_FROM_DEVICE);
866 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
867 adapter->alloc_rx_buff_failed++;
868 break;
869 }
870 }
871
872 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
873 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
874
875 if (unlikely(++i == rx_ring->count))
876 i = 0;
877 buffer_info = &rx_ring->buffer_info[i];
878 }
879
880 if (likely(rx_ring->next_to_use != i)) {
881 rx_ring->next_to_use = i;
882 if (unlikely(i-- == 0))
883 i = (rx_ring->count - 1);
884
885 /* Force memory writes to complete before letting h/w
886 * know there are new descriptors to fetch. (Only
887 * applicable for weak-ordered memory model archs,
888 * such as IA-64).
889 */
890 wmb();
891 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
892 e1000e_update_rdt_wa(rx_ring, i);
893 else
894 writel(i, rx_ring->tail);
895 }
896}
897
898static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
899 struct sk_buff *skb)
900{
901 if (netdev->features & NETIF_F_RXHASH)
902 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
903}
904
905/**
906 * e1000_clean_rx_irq - Send received data up the network stack
907 * @rx_ring: Rx descriptor ring
908 * @work_done: output parameter for indicating completed work
909 * @work_to_do: how many packets we can clean
910 *
911 * the return value indicates whether actual cleaning was done, there
912 * is no guarantee that everything was cleaned
913 **/
914static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
915 int work_to_do)
916{
917 struct e1000_adapter *adapter = rx_ring->adapter;
918 struct net_device *netdev = adapter->netdev;
919 struct pci_dev *pdev = adapter->pdev;
920 struct e1000_hw *hw = &adapter->hw;
921 union e1000_rx_desc_extended *rx_desc, *next_rxd;
922 struct e1000_buffer *buffer_info, *next_buffer;
923 u32 length, staterr;
924 unsigned int i;
925 int cleaned_count = 0;
926 bool cleaned = false;
927 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
928
929 i = rx_ring->next_to_clean;
930 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
931 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
932 buffer_info = &rx_ring->buffer_info[i];
933
934 while (staterr & E1000_RXD_STAT_DD) {
935 struct sk_buff *skb;
936
937 if (*work_done >= work_to_do)
938 break;
939 (*work_done)++;
940 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
941
942 skb = buffer_info->skb;
943 buffer_info->skb = NULL;
944
945 prefetch(skb->data - NET_IP_ALIGN);
946
947 i++;
948 if (i == rx_ring->count)
949 i = 0;
950 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
951 prefetch(next_rxd);
952
953 next_buffer = &rx_ring->buffer_info[i];
954
955 cleaned = true;
956 cleaned_count++;
957 dma_unmap_single(&pdev->dev, buffer_info->dma,
958 adapter->rx_buffer_len, DMA_FROM_DEVICE);
959 buffer_info->dma = 0;
960
961 length = le16_to_cpu(rx_desc->wb.upper.length);
962
963 /* !EOP means multiple descriptors were used to store a single
964 * packet, if that's the case we need to toss it. In fact, we
965 * need to toss every packet with the EOP bit clear and the
966 * next frame that _does_ have the EOP bit set, as it is by
967 * definition only a frame fragment
968 */
969 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
970 adapter->flags2 |= FLAG2_IS_DISCARDING;
971
972 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
973 /* All receives must fit into a single buffer */
974 e_dbg("Receive packet consumed multiple buffers\n");
975 /* recycle */
976 buffer_info->skb = skb;
977 if (staterr & E1000_RXD_STAT_EOP)
978 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
979 goto next_desc;
980 }
981
982 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
983 !(netdev->features & NETIF_F_RXALL))) {
984 /* recycle */
985 buffer_info->skb = skb;
986 goto next_desc;
987 }
988
989 /* adjust length to remove Ethernet CRC */
990 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
991 /* If configured to store CRC, don't subtract FCS,
992 * but keep the FCS bytes out of the total_rx_bytes
993 * counter
994 */
995 if (netdev->features & NETIF_F_RXFCS)
996 total_rx_bytes -= 4;
997 else
998 length -= 4;
999 }
1000
1001 total_rx_bytes += length;
1002 total_rx_packets++;
1003
1004 /* code added for copybreak, this should improve
1005 * performance for small packets with large amounts
1006 * of reassembly being done in the stack
1007 */
1008 if (length < copybreak) {
1009 struct sk_buff *new_skb =
1010 napi_alloc_skb(&adapter->napi, length);
1011 if (new_skb) {
1012 skb_copy_to_linear_data_offset(new_skb,
1013 -NET_IP_ALIGN,
1014 (skb->data -
1015 NET_IP_ALIGN),
1016 (length +
1017 NET_IP_ALIGN));
1018 /* save the skb in buffer_info as good */
1019 buffer_info->skb = skb;
1020 skb = new_skb;
1021 }
1022 /* else just continue with the old one */
1023 }
1024 /* end copybreak code */
1025 skb_put(skb, length);
1026
1027 /* Receive Checksum Offload */
1028 e1000_rx_checksum(adapter, staterr, skb);
1029
1030 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1031
1032 e1000_receive_skb(adapter, netdev, skb, staterr,
1033 rx_desc->wb.upper.vlan);
1034
1035next_desc:
1036 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1037
1038 /* return some buffers to hardware, one at a time is too slow */
1039 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1040 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1041 GFP_ATOMIC);
1042 cleaned_count = 0;
1043 }
1044
1045 /* use prefetched values */
1046 rx_desc = next_rxd;
1047 buffer_info = next_buffer;
1048
1049 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1050 }
1051 rx_ring->next_to_clean = i;
1052
1053 cleaned_count = e1000_desc_unused(rx_ring);
1054 if (cleaned_count)
1055 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1056
1057 adapter->total_rx_bytes += total_rx_bytes;
1058 adapter->total_rx_packets += total_rx_packets;
1059 return cleaned;
1060}
1061
1062static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1063 struct e1000_buffer *buffer_info,
1064 bool drop)
1065{
1066 struct e1000_adapter *adapter = tx_ring->adapter;
1067
1068 if (buffer_info->dma) {
1069 if (buffer_info->mapped_as_page)
1070 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1071 buffer_info->length, DMA_TO_DEVICE);
1072 else
1073 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1074 buffer_info->length, DMA_TO_DEVICE);
1075 buffer_info->dma = 0;
1076 }
1077 if (buffer_info->skb) {
1078 if (drop)
1079 dev_kfree_skb_any(buffer_info->skb);
1080 else
1081 dev_consume_skb_any(buffer_info->skb);
1082 buffer_info->skb = NULL;
1083 }
1084 buffer_info->time_stamp = 0;
1085}
1086
1087static void e1000_print_hw_hang(struct work_struct *work)
1088{
1089 struct e1000_adapter *adapter = container_of(work,
1090 struct e1000_adapter,
1091 print_hang_task);
1092 struct net_device *netdev = adapter->netdev;
1093 struct e1000_ring *tx_ring = adapter->tx_ring;
1094 unsigned int i = tx_ring->next_to_clean;
1095 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1096 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1097 struct e1000_hw *hw = &adapter->hw;
1098 u16 phy_status, phy_1000t_status, phy_ext_status;
1099 u16 pci_status;
1100
1101 if (test_bit(__E1000_DOWN, &adapter->state))
1102 return;
1103
1104 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1105 /* May be block on write-back, flush and detect again
1106 * flush pending descriptor writebacks to memory
1107 */
1108 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1109 /* execute the writes immediately */
1110 e1e_flush();
1111 /* Due to rare timing issues, write to TIDV again to ensure
1112 * the write is successful
1113 */
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115 /* execute the writes immediately */
1116 e1e_flush();
1117 adapter->tx_hang_recheck = true;
1118 return;
1119 }
1120 adapter->tx_hang_recheck = false;
1121
1122 if (er32(TDH(0)) == er32(TDT(0))) {
1123 e_dbg("false hang detected, ignoring\n");
1124 return;
1125 }
1126
1127 /* Real hang detected */
1128 netif_stop_queue(netdev);
1129
1130 e1e_rphy(hw, MII_BMSR, &phy_status);
1131 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1132 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1133
1134 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1135
1136 /* detected Hardware unit hang */
1137 e_err("Detected Hardware Unit Hang:\n"
1138 " TDH <%x>\n"
1139 " TDT <%x>\n"
1140 " next_to_use <%x>\n"
1141 " next_to_clean <%x>\n"
1142 "buffer_info[next_to_clean]:\n"
1143 " time_stamp <%lx>\n"
1144 " next_to_watch <%x>\n"
1145 " jiffies <%lx>\n"
1146 " next_to_watch.status <%x>\n"
1147 "MAC Status <%x>\n"
1148 "PHY Status <%x>\n"
1149 "PHY 1000BASE-T Status <%x>\n"
1150 "PHY Extended Status <%x>\n"
1151 "PCI Status <%x>\n",
1152 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1153 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1154 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1155 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1156
1157 e1000e_dump(adapter);
1158
1159 /* Suggest workaround for known h/w issue */
1160 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1161 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1162}
1163
1164/**
1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1166 * @work: pointer to work struct
1167 *
1168 * This work function polls the TSYNCTXCTL valid bit to determine when a
1169 * timestamp has been taken for the current stored skb. The timestamp must
1170 * be for this skb because only one such packet is allowed in the queue.
1171 */
1172static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1173{
1174 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1175 tx_hwtstamp_work);
1176 struct e1000_hw *hw = &adapter->hw;
1177
1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1179 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1180 struct skb_shared_hwtstamps shhwtstamps;
1181 u64 txstmp;
1182
1183 txstmp = er32(TXSTMPL);
1184 txstmp |= (u64)er32(TXSTMPH) << 32;
1185
1186 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1187
1188 /* Clear the global tx_hwtstamp_skb pointer and force writes
1189 * prior to notifying the stack of a Tx timestamp.
1190 */
1191 adapter->tx_hwtstamp_skb = NULL;
1192 wmb(); /* force write prior to skb_tstamp_tx */
1193
1194 skb_tstamp_tx(skb, &shhwtstamps);
1195 dev_consume_skb_any(skb);
1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
1201 e_warn("clearing Tx timestamp hang\n");
1202 } else {
1203 /* reschedule to check later */
1204 schedule_work(&adapter->tx_hwtstamp_work);
1205 }
1206}
1207
1208/**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1210 * @tx_ring: Tx descriptor ring
1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
1215static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1216{
1217 struct e1000_adapter *adapter = tx_ring->adapter;
1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1225 unsigned int bytes_compl = 0, pkts_compl = 0;
1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
1233 bool cleaned = false;
1234
1235 dma_rmb(); /* read buffer_info after eop_desc */
1236 for (; !cleaned; count++) {
1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
1248 }
1249
1250 e1000_put_txbuf(tx_ring, buffer_info, false);
1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
1258 if (i == tx_ring->next_to_use)
1259 break;
1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1267
1268#define TX_WAKE_THRESHOLD 32
1269 if (count && netif_carrier_ok(netdev) &&
1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1274 smp_mb();
1275
1276 if (netif_queue_stopped(netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
1284 /* Detect a transmit hang in hardware, this serializes the
1285 * check with the clearing of time_stamp and movement of i
1286 */
1287 adapter->detect_tx_hung = false;
1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1290 + (adapter->tx_timeout_factor * HZ)) &&
1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
1292 schedule_work(&adapter->print_hang_task);
1293 else
1294 adapter->tx_hang_recheck = false;
1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
1298 return count < tx_ring->count;
1299}
1300
1301/**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1303 * @rx_ring: Rx descriptor ring
1304 * @work_done: output parameter for indicating completed work
1305 * @work_to_do: how many packets we can clean
1306 *
1307 * the return value indicates whether actual cleaning was done, there
1308 * is no guarantee that everything was cleaned
1309 **/
1310static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1311 int work_to_do)
1312{
1313 struct e1000_adapter *adapter = rx_ring->adapter;
1314 struct e1000_hw *hw = &adapter->hw;
1315 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1316 struct net_device *netdev = adapter->netdev;
1317 struct pci_dev *pdev = adapter->pdev;
1318 struct e1000_buffer *buffer_info, *next_buffer;
1319 struct e1000_ps_page *ps_page;
1320 struct sk_buff *skb;
1321 unsigned int i, j;
1322 u32 length, staterr;
1323 int cleaned_count = 0;
1324 bool cleaned = false;
1325 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1326
1327 i = rx_ring->next_to_clean;
1328 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1329 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1330 buffer_info = &rx_ring->buffer_info[i];
1331
1332 while (staterr & E1000_RXD_STAT_DD) {
1333 if (*work_done >= work_to_do)
1334 break;
1335 (*work_done)++;
1336 skb = buffer_info->skb;
1337 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1338
1339 /* in the packet split case this is header only */
1340 prefetch(skb->data - NET_IP_ALIGN);
1341
1342 i++;
1343 if (i == rx_ring->count)
1344 i = 0;
1345 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1346 prefetch(next_rxd);
1347
1348 next_buffer = &rx_ring->buffer_info[i];
1349
1350 cleaned = true;
1351 cleaned_count++;
1352 dma_unmap_single(&pdev->dev, buffer_info->dma,
1353 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1354 buffer_info->dma = 0;
1355
1356 /* see !EOP comment in other Rx routine */
1357 if (!(staterr & E1000_RXD_STAT_EOP))
1358 adapter->flags2 |= FLAG2_IS_DISCARDING;
1359
1360 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1361 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1362 dev_kfree_skb_irq(skb);
1363 if (staterr & E1000_RXD_STAT_EOP)
1364 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1365 goto next_desc;
1366 }
1367
1368 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1369 !(netdev->features & NETIF_F_RXALL))) {
1370 dev_kfree_skb_irq(skb);
1371 goto next_desc;
1372 }
1373
1374 length = le16_to_cpu(rx_desc->wb.middle.length0);
1375
1376 if (!length) {
1377 e_dbg("Last part of the packet spanning multiple descriptors\n");
1378 dev_kfree_skb_irq(skb);
1379 goto next_desc;
1380 }
1381
1382 /* Good Receive */
1383 skb_put(skb, length);
1384
1385 {
1386 /* this looks ugly, but it seems compiler issues make
1387 * it more efficient than reusing j
1388 */
1389 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1390
1391 /* page alloc/put takes too long and effects small
1392 * packet throughput, so unsplit small packets and
1393 * save the alloc/put
1394 */
1395 if (l1 && (l1 <= copybreak) &&
1396 ((length + l1) <= adapter->rx_ps_bsize0)) {
1397 ps_page = &buffer_info->ps_pages[0];
1398
1399 dma_sync_single_for_cpu(&pdev->dev,
1400 ps_page->dma,
1401 PAGE_SIZE,
1402 DMA_FROM_DEVICE);
1403 memcpy(skb_tail_pointer(skb),
1404 page_address(ps_page->page), l1);
1405 dma_sync_single_for_device(&pdev->dev,
1406 ps_page->dma,
1407 PAGE_SIZE,
1408 DMA_FROM_DEVICE);
1409
1410 /* remove the CRC */
1411 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1412 if (!(netdev->features & NETIF_F_RXFCS))
1413 l1 -= 4;
1414 }
1415
1416 skb_put(skb, l1);
1417 goto copydone;
1418 } /* if */
1419 }
1420
1421 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1422 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1423 if (!length)
1424 break;
1425
1426 ps_page = &buffer_info->ps_pages[j];
1427 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1428 DMA_FROM_DEVICE);
1429 ps_page->dma = 0;
1430 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1431 ps_page->page = NULL;
1432 skb->len += length;
1433 skb->data_len += length;
1434 skb->truesize += PAGE_SIZE;
1435 }
1436
1437 /* strip the ethernet crc, problem is we're using pages now so
1438 * this whole operation can get a little cpu intensive
1439 */
1440 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1441 if (!(netdev->features & NETIF_F_RXFCS))
1442 pskb_trim(skb, skb->len - 4);
1443 }
1444
1445copydone:
1446 total_rx_bytes += skb->len;
1447 total_rx_packets++;
1448
1449 e1000_rx_checksum(adapter, staterr, skb);
1450
1451 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1452
1453 if (rx_desc->wb.upper.header_status &
1454 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1455 adapter->rx_hdr_split++;
1456
1457 e1000_receive_skb(adapter, netdev, skb, staterr,
1458 rx_desc->wb.middle.vlan);
1459
1460next_desc:
1461 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1462 buffer_info->skb = NULL;
1463
1464 /* return some buffers to hardware, one at a time is too slow */
1465 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1466 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1467 GFP_ATOMIC);
1468 cleaned_count = 0;
1469 }
1470
1471 /* use prefetched values */
1472 rx_desc = next_rxd;
1473 buffer_info = next_buffer;
1474
1475 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1476 }
1477 rx_ring->next_to_clean = i;
1478
1479 cleaned_count = e1000_desc_unused(rx_ring);
1480 if (cleaned_count)
1481 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1482
1483 adapter->total_rx_bytes += total_rx_bytes;
1484 adapter->total_rx_packets += total_rx_packets;
1485 return cleaned;
1486}
1487
1488static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1489 u16 length)
1490{
1491 bi->page = NULL;
1492 skb->len += length;
1493 skb->data_len += length;
1494 skb->truesize += PAGE_SIZE;
1495}
1496
1497/**
1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1499 * @rx_ring: Rx descriptor ring
1500 * @work_done: output parameter for indicating completed work
1501 * @work_to_do: how many packets we can clean
1502 *
1503 * the return value indicates whether actual cleaning was done, there
1504 * is no guarantee that everything was cleaned
1505 **/
1506static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 int work_to_do)
1508{
1509 struct e1000_adapter *adapter = rx_ring->adapter;
1510 struct net_device *netdev = adapter->netdev;
1511 struct pci_dev *pdev = adapter->pdev;
1512 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1513 struct e1000_buffer *buffer_info, *next_buffer;
1514 u32 length, staterr;
1515 unsigned int i;
1516 int cleaned_count = 0;
1517 bool cleaned = false;
1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1519 struct skb_shared_info *shinfo;
1520
1521 i = rx_ring->next_to_clean;
1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1524 buffer_info = &rx_ring->buffer_info[i];
1525
1526 while (staterr & E1000_RXD_STAT_DD) {
1527 struct sk_buff *skb;
1528
1529 if (*work_done >= work_to_do)
1530 break;
1531 (*work_done)++;
1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1533
1534 skb = buffer_info->skb;
1535 buffer_info->skb = NULL;
1536
1537 ++i;
1538 if (i == rx_ring->count)
1539 i = 0;
1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1541 prefetch(next_rxd);
1542
1543 next_buffer = &rx_ring->buffer_info[i];
1544
1545 cleaned = true;
1546 cleaned_count++;
1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 DMA_FROM_DEVICE);
1549 buffer_info->dma = 0;
1550
1551 length = le16_to_cpu(rx_desc->wb.upper.length);
1552
1553 /* errors is only valid for DD + EOP descriptors */
1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 !(netdev->features & NETIF_F_RXALL)))) {
1557 /* recycle both page and skb */
1558 buffer_info->skb = skb;
1559 /* an error means any chain goes out the window too */
1560 if (rx_ring->rx_skb_top)
1561 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1562 rx_ring->rx_skb_top = NULL;
1563 goto next_desc;
1564 }
1565#define rxtop (rx_ring->rx_skb_top)
1566 if (!(staterr & E1000_RXD_STAT_EOP)) {
1567 /* this descriptor is only the beginning (or middle) */
1568 if (!rxtop) {
1569 /* this is the beginning of a chain */
1570 rxtop = skb;
1571 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1572 0, length);
1573 } else {
1574 /* this is the middle of a chain */
1575 shinfo = skb_shinfo(rxtop);
1576 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1577 buffer_info->page, 0,
1578 length);
1579 /* re-use the skb, only consumed the page */
1580 buffer_info->skb = skb;
1581 }
1582 e1000_consume_page(buffer_info, rxtop, length);
1583 goto next_desc;
1584 } else {
1585 if (rxtop) {
1586 /* end of the chain */
1587 shinfo = skb_shinfo(rxtop);
1588 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1589 buffer_info->page, 0,
1590 length);
1591 /* re-use the current skb, we only consumed the
1592 * page
1593 */
1594 buffer_info->skb = skb;
1595 skb = rxtop;
1596 rxtop = NULL;
1597 e1000_consume_page(buffer_info, skb, length);
1598 } else {
1599 /* no chain, got EOP, this buf is the packet
1600 * copybreak to save the put_page/alloc_page
1601 */
1602 if (length <= copybreak &&
1603 skb_tailroom(skb) >= length) {
1604 memcpy(skb_tail_pointer(skb),
1605 page_address(buffer_info->page),
1606 length);
1607 /* re-use the page, so don't erase
1608 * buffer_info->page
1609 */
1610 skb_put(skb, length);
1611 } else {
1612 skb_fill_page_desc(skb, 0,
1613 buffer_info->page, 0,
1614 length);
1615 e1000_consume_page(buffer_info, skb,
1616 length);
1617 }
1618 }
1619 }
1620
1621 /* Receive Checksum Offload */
1622 e1000_rx_checksum(adapter, staterr, skb);
1623
1624 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1625
1626 /* probably a little skewed due to removing CRC */
1627 total_rx_bytes += skb->len;
1628 total_rx_packets++;
1629
1630 /* eth type trans needs skb->data to point to something */
1631 if (!pskb_may_pull(skb, ETH_HLEN)) {
1632 e_err("pskb_may_pull failed.\n");
1633 dev_kfree_skb_irq(skb);
1634 goto next_desc;
1635 }
1636
1637 e1000_receive_skb(adapter, netdev, skb, staterr,
1638 rx_desc->wb.upper.vlan);
1639
1640next_desc:
1641 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1642
1643 /* return some buffers to hardware, one at a time is too slow */
1644 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1645 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1646 GFP_ATOMIC);
1647 cleaned_count = 0;
1648 }
1649
1650 /* use prefetched values */
1651 rx_desc = next_rxd;
1652 buffer_info = next_buffer;
1653
1654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1655 }
1656 rx_ring->next_to_clean = i;
1657
1658 cleaned_count = e1000_desc_unused(rx_ring);
1659 if (cleaned_count)
1660 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1661
1662 adapter->total_rx_bytes += total_rx_bytes;
1663 adapter->total_rx_packets += total_rx_packets;
1664 return cleaned;
1665}
1666
1667/**
1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1669 * @rx_ring: Rx descriptor ring
1670 **/
1671static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1672{
1673 struct e1000_adapter *adapter = rx_ring->adapter;
1674 struct e1000_buffer *buffer_info;
1675 struct e1000_ps_page *ps_page;
1676 struct pci_dev *pdev = adapter->pdev;
1677 unsigned int i, j;
1678
1679 /* Free all the Rx ring sk_buffs */
1680 for (i = 0; i < rx_ring->count; i++) {
1681 buffer_info = &rx_ring->buffer_info[i];
1682 if (buffer_info->dma) {
1683 if (adapter->clean_rx == e1000_clean_rx_irq)
1684 dma_unmap_single(&pdev->dev, buffer_info->dma,
1685 adapter->rx_buffer_len,
1686 DMA_FROM_DEVICE);
1687 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1688 dma_unmap_page(&pdev->dev, buffer_info->dma,
1689 PAGE_SIZE, DMA_FROM_DEVICE);
1690 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1691 dma_unmap_single(&pdev->dev, buffer_info->dma,
1692 adapter->rx_ps_bsize0,
1693 DMA_FROM_DEVICE);
1694 buffer_info->dma = 0;
1695 }
1696
1697 if (buffer_info->page) {
1698 put_page(buffer_info->page);
1699 buffer_info->page = NULL;
1700 }
1701
1702 if (buffer_info->skb) {
1703 dev_kfree_skb(buffer_info->skb);
1704 buffer_info->skb = NULL;
1705 }
1706
1707 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1708 ps_page = &buffer_info->ps_pages[j];
1709 if (!ps_page->page)
1710 break;
1711 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1712 DMA_FROM_DEVICE);
1713 ps_page->dma = 0;
1714 put_page(ps_page->page);
1715 ps_page->page = NULL;
1716 }
1717 }
1718
1719 /* there also may be some cached data from a chained receive */
1720 if (rx_ring->rx_skb_top) {
1721 dev_kfree_skb(rx_ring->rx_skb_top);
1722 rx_ring->rx_skb_top = NULL;
1723 }
1724
1725 /* Zero out the descriptor ring */
1726 memset(rx_ring->desc, 0, rx_ring->size);
1727
1728 rx_ring->next_to_clean = 0;
1729 rx_ring->next_to_use = 0;
1730 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1731}
1732
1733static void e1000e_downshift_workaround(struct work_struct *work)
1734{
1735 struct e1000_adapter *adapter = container_of(work,
1736 struct e1000_adapter,
1737 downshift_task);
1738
1739 if (test_bit(__E1000_DOWN, &adapter->state))
1740 return;
1741
1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1743}
1744
1745/**
1746 * e1000_intr_msi - Interrupt Handler
1747 * @irq: interrupt number
1748 * @data: pointer to a network interface device structure
1749 **/
1750static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1751{
1752 struct net_device *netdev = data;
1753 struct e1000_adapter *adapter = netdev_priv(netdev);
1754 struct e1000_hw *hw = &adapter->hw;
1755 u32 icr = er32(ICR);
1756
1757 /* read ICR disables interrupts using IAM */
1758 if (icr & E1000_ICR_LSC) {
1759 hw->mac.get_link_status = true;
1760 /* ICH8 workaround-- Call gig speed drop workaround on cable
1761 * disconnect (LSC) before accessing any PHY registers
1762 */
1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1764 (!(er32(STATUS) & E1000_STATUS_LU)))
1765 schedule_work(&adapter->downshift_task);
1766
1767 /* 80003ES2LAN workaround-- For packet buffer work-around on
1768 * link down event; disable receives here in the ISR and reset
1769 * adapter in watchdog
1770 */
1771 if (netif_carrier_ok(netdev) &&
1772 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1773 /* disable receives */
1774 u32 rctl = er32(RCTL);
1775
1776 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1777 adapter->flags |= FLAG_RESTART_NOW;
1778 }
1779 /* guard against interrupt when we're going down */
1780 if (!test_bit(__E1000_DOWN, &adapter->state))
1781 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1782 }
1783
1784 /* Reset on uncorrectable ECC error */
1785 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1786 u32 pbeccsts = er32(PBECCSTS);
1787
1788 adapter->corr_errors +=
1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1790 adapter->uncorr_errors +=
1791 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1792
1793 /* Do the reset outside of interrupt context */
1794 schedule_work(&adapter->reset_task);
1795
1796 /* return immediately since reset is imminent */
1797 return IRQ_HANDLED;
1798 }
1799
1800 if (napi_schedule_prep(&adapter->napi)) {
1801 adapter->total_tx_bytes = 0;
1802 adapter->total_tx_packets = 0;
1803 adapter->total_rx_bytes = 0;
1804 adapter->total_rx_packets = 0;
1805 __napi_schedule(&adapter->napi);
1806 }
1807
1808 return IRQ_HANDLED;
1809}
1810
1811/**
1812 * e1000_intr - Interrupt Handler
1813 * @irq: interrupt number
1814 * @data: pointer to a network interface device structure
1815 **/
1816static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1817{
1818 struct net_device *netdev = data;
1819 struct e1000_adapter *adapter = netdev_priv(netdev);
1820 struct e1000_hw *hw = &adapter->hw;
1821 u32 rctl, icr = er32(ICR);
1822
1823 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1824 return IRQ_NONE; /* Not our interrupt */
1825
1826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1827 * not set, then the adapter didn't send an interrupt
1828 */
1829 if (!(icr & E1000_ICR_INT_ASSERTED))
1830 return IRQ_NONE;
1831
1832 /* Interrupt Auto-Mask...upon reading ICR,
1833 * interrupts are masked. No need for the
1834 * IMC write
1835 */
1836
1837 if (icr & E1000_ICR_LSC) {
1838 hw->mac.get_link_status = true;
1839 /* ICH8 workaround-- Call gig speed drop workaround on cable
1840 * disconnect (LSC) before accessing any PHY registers
1841 */
1842 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1843 (!(er32(STATUS) & E1000_STATUS_LU)))
1844 schedule_work(&adapter->downshift_task);
1845
1846 /* 80003ES2LAN workaround--
1847 * For packet buffer work-around on link down event;
1848 * disable receives here in the ISR and
1849 * reset adapter in watchdog
1850 */
1851 if (netif_carrier_ok(netdev) &&
1852 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1853 /* disable receives */
1854 rctl = er32(RCTL);
1855 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1856 adapter->flags |= FLAG_RESTART_NOW;
1857 }
1858 /* guard against interrupt when we're going down */
1859 if (!test_bit(__E1000_DOWN, &adapter->state))
1860 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1861 }
1862
1863 /* Reset on uncorrectable ECC error */
1864 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1865 u32 pbeccsts = er32(PBECCSTS);
1866
1867 adapter->corr_errors +=
1868 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1869 adapter->uncorr_errors +=
1870 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
1871
1872 /* Do the reset outside of interrupt context */
1873 schedule_work(&adapter->reset_task);
1874
1875 /* return immediately since reset is imminent */
1876 return IRQ_HANDLED;
1877 }
1878
1879 if (napi_schedule_prep(&adapter->napi)) {
1880 adapter->total_tx_bytes = 0;
1881 adapter->total_tx_packets = 0;
1882 adapter->total_rx_bytes = 0;
1883 adapter->total_rx_packets = 0;
1884 __napi_schedule(&adapter->napi);
1885 }
1886
1887 return IRQ_HANDLED;
1888}
1889
1890static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1891{
1892 struct net_device *netdev = data;
1893 struct e1000_adapter *adapter = netdev_priv(netdev);
1894 struct e1000_hw *hw = &adapter->hw;
1895 u32 icr = er32(ICR);
1896
1897 if (icr & adapter->eiac_mask)
1898 ew32(ICS, (icr & adapter->eiac_mask));
1899
1900 if (icr & E1000_ICR_LSC) {
1901 hw->mac.get_link_status = true;
1902 /* guard against interrupt when we're going down */
1903 if (!test_bit(__E1000_DOWN, &adapter->state))
1904 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1905 }
1906
1907 if (!test_bit(__E1000_DOWN, &adapter->state))
1908 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1909
1910 return IRQ_HANDLED;
1911}
1912
1913static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1914{
1915 struct net_device *netdev = data;
1916 struct e1000_adapter *adapter = netdev_priv(netdev);
1917 struct e1000_hw *hw = &adapter->hw;
1918 struct e1000_ring *tx_ring = adapter->tx_ring;
1919
1920 adapter->total_tx_bytes = 0;
1921 adapter->total_tx_packets = 0;
1922
1923 if (!e1000_clean_tx_irq(tx_ring))
1924 /* Ring was not completely cleaned, so fire another interrupt */
1925 ew32(ICS, tx_ring->ims_val);
1926
1927 if (!test_bit(__E1000_DOWN, &adapter->state))
1928 ew32(IMS, adapter->tx_ring->ims_val);
1929
1930 return IRQ_HANDLED;
1931}
1932
1933static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1934{
1935 struct net_device *netdev = data;
1936 struct e1000_adapter *adapter = netdev_priv(netdev);
1937 struct e1000_ring *rx_ring = adapter->rx_ring;
1938
1939 /* Write the ITR value calculated at the end of the
1940 * previous interrupt.
1941 */
1942 if (rx_ring->set_itr) {
1943 u32 itr = rx_ring->itr_val ?
1944 1000000000 / (rx_ring->itr_val * 256) : 0;
1945
1946 writel(itr, rx_ring->itr_register);
1947 rx_ring->set_itr = 0;
1948 }
1949
1950 if (napi_schedule_prep(&adapter->napi)) {
1951 adapter->total_rx_bytes = 0;
1952 adapter->total_rx_packets = 0;
1953 __napi_schedule(&adapter->napi);
1954 }
1955 return IRQ_HANDLED;
1956}
1957
1958/**
1959 * e1000_configure_msix - Configure MSI-X hardware
1960 * @adapter: board private structure
1961 *
1962 * e1000_configure_msix sets up the hardware to properly
1963 * generate MSI-X interrupts.
1964 **/
1965static void e1000_configure_msix(struct e1000_adapter *adapter)
1966{
1967 struct e1000_hw *hw = &adapter->hw;
1968 struct e1000_ring *rx_ring = adapter->rx_ring;
1969 struct e1000_ring *tx_ring = adapter->tx_ring;
1970 int vector = 0;
1971 u32 ctrl_ext, ivar = 0;
1972
1973 adapter->eiac_mask = 0;
1974
1975 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1976 if (hw->mac.type == e1000_82574) {
1977 u32 rfctl = er32(RFCTL);
1978
1979 rfctl |= E1000_RFCTL_ACK_DIS;
1980 ew32(RFCTL, rfctl);
1981 }
1982
1983 /* Configure Rx vector */
1984 rx_ring->ims_val = E1000_IMS_RXQ0;
1985 adapter->eiac_mask |= rx_ring->ims_val;
1986 if (rx_ring->itr_val)
1987 writel(1000000000 / (rx_ring->itr_val * 256),
1988 rx_ring->itr_register);
1989 else
1990 writel(1, rx_ring->itr_register);
1991 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1992
1993 /* Configure Tx vector */
1994 tx_ring->ims_val = E1000_IMS_TXQ0;
1995 vector++;
1996 if (tx_ring->itr_val)
1997 writel(1000000000 / (tx_ring->itr_val * 256),
1998 tx_ring->itr_register);
1999 else
2000 writel(1, tx_ring->itr_register);
2001 adapter->eiac_mask |= tx_ring->ims_val;
2002 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2003
2004 /* set vector for Other Causes, e.g. link changes */
2005 vector++;
2006 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2007 if (rx_ring->itr_val)
2008 writel(1000000000 / (rx_ring->itr_val * 256),
2009 hw->hw_addr + E1000_EITR_82574(vector));
2010 else
2011 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2012
2013 /* Cause Tx interrupts on every write back */
2014 ivar |= BIT(31);
2015
2016 ew32(IVAR, ivar);
2017
2018 /* enable MSI-X PBA support */
2019 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2020 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2021 ew32(CTRL_EXT, ctrl_ext);
2022 e1e_flush();
2023}
2024
2025void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2026{
2027 if (adapter->msix_entries) {
2028 pci_disable_msix(adapter->pdev);
2029 kfree(adapter->msix_entries);
2030 adapter->msix_entries = NULL;
2031 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2032 pci_disable_msi(adapter->pdev);
2033 adapter->flags &= ~FLAG_MSI_ENABLED;
2034 }
2035}
2036
2037/**
2038 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2039 * @adapter: board private structure
2040 *
2041 * Attempt to configure interrupts using the best available
2042 * capabilities of the hardware and kernel.
2043 **/
2044void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2045{
2046 int err;
2047 int i;
2048
2049 switch (adapter->int_mode) {
2050 case E1000E_INT_MODE_MSIX:
2051 if (adapter->flags & FLAG_HAS_MSIX) {
2052 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2053 adapter->msix_entries = kcalloc(adapter->num_vectors,
2054 sizeof(struct
2055 msix_entry),
2056 GFP_KERNEL);
2057 if (adapter->msix_entries) {
2058 struct e1000_adapter *a = adapter;
2059
2060 for (i = 0; i < adapter->num_vectors; i++)
2061 adapter->msix_entries[i].entry = i;
2062
2063 err = pci_enable_msix_range(a->pdev,
2064 a->msix_entries,
2065 a->num_vectors,
2066 a->num_vectors);
2067 if (err > 0)
2068 return;
2069 }
2070 /* MSI-X failed, so fall through and try MSI */
2071 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2072 e1000e_reset_interrupt_capability(adapter);
2073 }
2074 adapter->int_mode = E1000E_INT_MODE_MSI;
2075 fallthrough;
2076 case E1000E_INT_MODE_MSI:
2077 if (!pci_enable_msi(adapter->pdev)) {
2078 adapter->flags |= FLAG_MSI_ENABLED;
2079 } else {
2080 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2081 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2082 }
2083 fallthrough;
2084 case E1000E_INT_MODE_LEGACY:
2085 /* Don't do anything; this is the system default */
2086 break;
2087 }
2088
2089 /* store the number of vectors being used */
2090 adapter->num_vectors = 1;
2091}
2092
2093/**
2094 * e1000_request_msix - Initialize MSI-X interrupts
2095 * @adapter: board private structure
2096 *
2097 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2098 * kernel.
2099 **/
2100static int e1000_request_msix(struct e1000_adapter *adapter)
2101{
2102 struct net_device *netdev = adapter->netdev;
2103 int err = 0, vector = 0;
2104
2105 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2106 snprintf(adapter->rx_ring->name,
2107 sizeof(adapter->rx_ring->name) - 1,
2108 "%.14s-rx-0", netdev->name);
2109 else
2110 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2111 err = request_irq(adapter->msix_entries[vector].vector,
2112 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2113 netdev);
2114 if (err)
2115 return err;
2116 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2117 E1000_EITR_82574(vector);
2118 adapter->rx_ring->itr_val = adapter->itr;
2119 vector++;
2120
2121 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2122 snprintf(adapter->tx_ring->name,
2123 sizeof(adapter->tx_ring->name) - 1,
2124 "%.14s-tx-0", netdev->name);
2125 else
2126 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2127 err = request_irq(adapter->msix_entries[vector].vector,
2128 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2129 netdev);
2130 if (err)
2131 return err;
2132 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2133 E1000_EITR_82574(vector);
2134 adapter->tx_ring->itr_val = adapter->itr;
2135 vector++;
2136
2137 err = request_irq(adapter->msix_entries[vector].vector,
2138 e1000_msix_other, 0, netdev->name, netdev);
2139 if (err)
2140 return err;
2141
2142 e1000_configure_msix(adapter);
2143
2144 return 0;
2145}
2146
2147/**
2148 * e1000_request_irq - initialize interrupts
2149 * @adapter: board private structure
2150 *
2151 * Attempts to configure interrupts using the best available
2152 * capabilities of the hardware and kernel.
2153 **/
2154static int e1000_request_irq(struct e1000_adapter *adapter)
2155{
2156 struct net_device *netdev = adapter->netdev;
2157 int err;
2158
2159 if (adapter->msix_entries) {
2160 err = e1000_request_msix(adapter);
2161 if (!err)
2162 return err;
2163 /* fall back to MSI */
2164 e1000e_reset_interrupt_capability(adapter);
2165 adapter->int_mode = E1000E_INT_MODE_MSI;
2166 e1000e_set_interrupt_capability(adapter);
2167 }
2168 if (adapter->flags & FLAG_MSI_ENABLED) {
2169 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2170 netdev->name, netdev);
2171 if (!err)
2172 return err;
2173
2174 /* fall back to legacy interrupt */
2175 e1000e_reset_interrupt_capability(adapter);
2176 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2177 }
2178
2179 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2180 netdev->name, netdev);
2181 if (err)
2182 e_err("Unable to allocate interrupt, Error: %d\n", err);
2183
2184 return err;
2185}
2186
2187static void e1000_free_irq(struct e1000_adapter *adapter)
2188{
2189 struct net_device *netdev = adapter->netdev;
2190
2191 if (adapter->msix_entries) {
2192 int vector = 0;
2193
2194 free_irq(adapter->msix_entries[vector].vector, netdev);
2195 vector++;
2196
2197 free_irq(adapter->msix_entries[vector].vector, netdev);
2198 vector++;
2199
2200 /* Other Causes interrupt vector */
2201 free_irq(adapter->msix_entries[vector].vector, netdev);
2202 return;
2203 }
2204
2205 free_irq(adapter->pdev->irq, netdev);
2206}
2207
2208/**
2209 * e1000_irq_disable - Mask off interrupt generation on the NIC
2210 * @adapter: board private structure
2211 **/
2212static void e1000_irq_disable(struct e1000_adapter *adapter)
2213{
2214 struct e1000_hw *hw = &adapter->hw;
2215
2216 ew32(IMC, ~0);
2217 if (adapter->msix_entries)
2218 ew32(EIAC_82574, 0);
2219 e1e_flush();
2220
2221 if (adapter->msix_entries) {
2222 int i;
2223
2224 for (i = 0; i < adapter->num_vectors; i++)
2225 synchronize_irq(adapter->msix_entries[i].vector);
2226 } else {
2227 synchronize_irq(adapter->pdev->irq);
2228 }
2229}
2230
2231/**
2232 * e1000_irq_enable - Enable default interrupt generation settings
2233 * @adapter: board private structure
2234 **/
2235static void e1000_irq_enable(struct e1000_adapter *adapter)
2236{
2237 struct e1000_hw *hw = &adapter->hw;
2238
2239 if (adapter->msix_entries) {
2240 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2241 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2242 IMS_OTHER_MASK);
2243 } else if (hw->mac.type >= e1000_pch_lpt) {
2244 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2245 } else {
2246 ew32(IMS, IMS_ENABLE_MASK);
2247 }
2248 e1e_flush();
2249}
2250
2251/**
2252 * e1000e_get_hw_control - get control of the h/w from f/w
2253 * @adapter: address of board private structure
2254 *
2255 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2256 * For ASF and Pass Through versions of f/w this means that
2257 * the driver is loaded. For AMT version (only with 82573)
2258 * of the f/w this means that the network i/f is open.
2259 **/
2260void e1000e_get_hw_control(struct e1000_adapter *adapter)
2261{
2262 struct e1000_hw *hw = &adapter->hw;
2263 u32 ctrl_ext;
2264 u32 swsm;
2265
2266 /* Let firmware know the driver has taken over */
2267 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2268 swsm = er32(SWSM);
2269 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2270 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2271 ctrl_ext = er32(CTRL_EXT);
2272 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2273 }
2274}
2275
2276/**
2277 * e1000e_release_hw_control - release control of the h/w to f/w
2278 * @adapter: address of board private structure
2279 *
2280 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2281 * For ASF and Pass Through versions of f/w this means that the
2282 * driver is no longer loaded. For AMT version (only with 82573) i
2283 * of the f/w this means that the network i/f is closed.
2284 *
2285 **/
2286void e1000e_release_hw_control(struct e1000_adapter *adapter)
2287{
2288 struct e1000_hw *hw = &adapter->hw;
2289 u32 ctrl_ext;
2290 u32 swsm;
2291
2292 /* Let firmware taken over control of h/w */
2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2294 swsm = er32(SWSM);
2295 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2297 ctrl_ext = er32(CTRL_EXT);
2298 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2299 }
2300}
2301
2302/**
2303 * e1000_alloc_ring_dma - allocate memory for a ring structure
2304 * @adapter: board private structure
2305 * @ring: ring struct for which to allocate dma
2306 **/
2307static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2308 struct e1000_ring *ring)
2309{
2310 struct pci_dev *pdev = adapter->pdev;
2311
2312 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2313 GFP_KERNEL);
2314 if (!ring->desc)
2315 return -ENOMEM;
2316
2317 return 0;
2318}
2319
2320/**
2321 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2322 * @tx_ring: Tx descriptor ring
2323 *
2324 * Return 0 on success, negative on failure
2325 **/
2326int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2327{
2328 struct e1000_adapter *adapter = tx_ring->adapter;
2329 int err = -ENOMEM, size;
2330
2331 size = sizeof(struct e1000_buffer) * tx_ring->count;
2332 tx_ring->buffer_info = vzalloc(size);
2333 if (!tx_ring->buffer_info)
2334 goto err;
2335
2336 /* round up to nearest 4K */
2337 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2338 tx_ring->size = ALIGN(tx_ring->size, 4096);
2339
2340 err = e1000_alloc_ring_dma(adapter, tx_ring);
2341 if (err)
2342 goto err;
2343
2344 tx_ring->next_to_use = 0;
2345 tx_ring->next_to_clean = 0;
2346
2347 return 0;
2348err:
2349 vfree(tx_ring->buffer_info);
2350 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2351 return err;
2352}
2353
2354/**
2355 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2356 * @rx_ring: Rx descriptor ring
2357 *
2358 * Returns 0 on success, negative on failure
2359 **/
2360int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2361{
2362 struct e1000_adapter *adapter = rx_ring->adapter;
2363 struct e1000_buffer *buffer_info;
2364 int i, size, desc_len, err = -ENOMEM;
2365
2366 size = sizeof(struct e1000_buffer) * rx_ring->count;
2367 rx_ring->buffer_info = vzalloc(size);
2368 if (!rx_ring->buffer_info)
2369 goto err;
2370
2371 for (i = 0; i < rx_ring->count; i++) {
2372 buffer_info = &rx_ring->buffer_info[i];
2373 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2374 sizeof(struct e1000_ps_page),
2375 GFP_KERNEL);
2376 if (!buffer_info->ps_pages)
2377 goto err_pages;
2378 }
2379
2380 desc_len = sizeof(union e1000_rx_desc_packet_split);
2381
2382 /* Round up to nearest 4K */
2383 rx_ring->size = rx_ring->count * desc_len;
2384 rx_ring->size = ALIGN(rx_ring->size, 4096);
2385
2386 err = e1000_alloc_ring_dma(adapter, rx_ring);
2387 if (err)
2388 goto err_pages;
2389
2390 rx_ring->next_to_clean = 0;
2391 rx_ring->next_to_use = 0;
2392 rx_ring->rx_skb_top = NULL;
2393
2394 return 0;
2395
2396err_pages:
2397 for (i = 0; i < rx_ring->count; i++) {
2398 buffer_info = &rx_ring->buffer_info[i];
2399 kfree(buffer_info->ps_pages);
2400 }
2401err:
2402 vfree(rx_ring->buffer_info);
2403 e_err("Unable to allocate memory for the receive descriptor ring\n");
2404 return err;
2405}
2406
2407/**
2408 * e1000_clean_tx_ring - Free Tx Buffers
2409 * @tx_ring: Tx descriptor ring
2410 **/
2411static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2412{
2413 struct e1000_adapter *adapter = tx_ring->adapter;
2414 struct e1000_buffer *buffer_info;
2415 unsigned long size;
2416 unsigned int i;
2417
2418 for (i = 0; i < tx_ring->count; i++) {
2419 buffer_info = &tx_ring->buffer_info[i];
2420 e1000_put_txbuf(tx_ring, buffer_info, false);
2421 }
2422
2423 netdev_reset_queue(adapter->netdev);
2424 size = sizeof(struct e1000_buffer) * tx_ring->count;
2425 memset(tx_ring->buffer_info, 0, size);
2426
2427 memset(tx_ring->desc, 0, tx_ring->size);
2428
2429 tx_ring->next_to_use = 0;
2430 tx_ring->next_to_clean = 0;
2431}
2432
2433/**
2434 * e1000e_free_tx_resources - Free Tx Resources per Queue
2435 * @tx_ring: Tx descriptor ring
2436 *
2437 * Free all transmit software resources
2438 **/
2439void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2440{
2441 struct e1000_adapter *adapter = tx_ring->adapter;
2442 struct pci_dev *pdev = adapter->pdev;
2443
2444 e1000_clean_tx_ring(tx_ring);
2445
2446 vfree(tx_ring->buffer_info);
2447 tx_ring->buffer_info = NULL;
2448
2449 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2450 tx_ring->dma);
2451 tx_ring->desc = NULL;
2452}
2453
2454/**
2455 * e1000e_free_rx_resources - Free Rx Resources
2456 * @rx_ring: Rx descriptor ring
2457 *
2458 * Free all receive software resources
2459 **/
2460void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2461{
2462 struct e1000_adapter *adapter = rx_ring->adapter;
2463 struct pci_dev *pdev = adapter->pdev;
2464 int i;
2465
2466 e1000_clean_rx_ring(rx_ring);
2467
2468 for (i = 0; i < rx_ring->count; i++)
2469 kfree(rx_ring->buffer_info[i].ps_pages);
2470
2471 vfree(rx_ring->buffer_info);
2472 rx_ring->buffer_info = NULL;
2473
2474 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2475 rx_ring->dma);
2476 rx_ring->desc = NULL;
2477}
2478
2479/**
2480 * e1000_update_itr - update the dynamic ITR value based on statistics
2481 * @itr_setting: current adapter->itr
2482 * @packets: the number of packets during this measurement interval
2483 * @bytes: the number of bytes during this measurement interval
2484 *
2485 * Stores a new ITR value based on packets and byte
2486 * counts during the last interrupt. The advantage of per interrupt
2487 * computation is faster updates and more accurate ITR for the current
2488 * traffic pattern. Constants in this function were computed
2489 * based on theoretical maximum wire speed and thresholds were set based
2490 * on testing data as well as attempting to minimize response time
2491 * while increasing bulk throughput. This functionality is controlled
2492 * by the InterruptThrottleRate module parameter.
2493 **/
2494static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2495{
2496 unsigned int retval = itr_setting;
2497
2498 if (packets == 0)
2499 return itr_setting;
2500
2501 switch (itr_setting) {
2502 case lowest_latency:
2503 /* handle TSO and jumbo frames */
2504 if (bytes / packets > 8000)
2505 retval = bulk_latency;
2506 else if ((packets < 5) && (bytes > 512))
2507 retval = low_latency;
2508 break;
2509 case low_latency: /* 50 usec aka 20000 ints/s */
2510 if (bytes > 10000) {
2511 /* this if handles the TSO accounting */
2512 if (bytes / packets > 8000)
2513 retval = bulk_latency;
2514 else if ((packets < 10) || ((bytes / packets) > 1200))
2515 retval = bulk_latency;
2516 else if ((packets > 35))
2517 retval = lowest_latency;
2518 } else if (bytes / packets > 2000) {
2519 retval = bulk_latency;
2520 } else if (packets <= 2 && bytes < 512) {
2521 retval = lowest_latency;
2522 }
2523 break;
2524 case bulk_latency: /* 250 usec aka 4000 ints/s */
2525 if (bytes > 25000) {
2526 if (packets > 35)
2527 retval = low_latency;
2528 } else if (bytes < 6000) {
2529 retval = low_latency;
2530 }
2531 break;
2532 }
2533
2534 return retval;
2535}
2536
2537static void e1000_set_itr(struct e1000_adapter *adapter)
2538{
2539 u16 current_itr;
2540 u32 new_itr = adapter->itr;
2541
2542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2543 if (adapter->link_speed != SPEED_1000) {
2544 new_itr = 4000;
2545 goto set_itr_now;
2546 }
2547
2548 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2549 new_itr = 0;
2550 goto set_itr_now;
2551 }
2552
2553 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2554 adapter->total_tx_packets,
2555 adapter->total_tx_bytes);
2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2557 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2558 adapter->tx_itr = low_latency;
2559
2560 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2561 adapter->total_rx_packets,
2562 adapter->total_rx_bytes);
2563 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2564 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2565 adapter->rx_itr = low_latency;
2566
2567 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2568
2569 /* counts and packets in update_itr are dependent on these numbers */
2570 switch (current_itr) {
2571 case lowest_latency:
2572 new_itr = 70000;
2573 break;
2574 case low_latency:
2575 new_itr = 20000; /* aka hwitr = ~200 */
2576 break;
2577 case bulk_latency:
2578 new_itr = 4000;
2579 break;
2580 default:
2581 break;
2582 }
2583
2584set_itr_now:
2585 if (new_itr != adapter->itr) {
2586 /* this attempts to bias the interrupt rate towards Bulk
2587 * by adding intermediate steps when interrupt rate is
2588 * increasing
2589 */
2590 new_itr = new_itr > adapter->itr ?
2591 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2592 adapter->itr = new_itr;
2593 adapter->rx_ring->itr_val = new_itr;
2594 if (adapter->msix_entries)
2595 adapter->rx_ring->set_itr = 1;
2596 else
2597 e1000e_write_itr(adapter, new_itr);
2598 }
2599}
2600
2601/**
2602 * e1000e_write_itr - write the ITR value to the appropriate registers
2603 * @adapter: address of board private structure
2604 * @itr: new ITR value to program
2605 *
2606 * e1000e_write_itr determines if the adapter is in MSI-X mode
2607 * and, if so, writes the EITR registers with the ITR value.
2608 * Otherwise, it writes the ITR value into the ITR register.
2609 **/
2610void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2611{
2612 struct e1000_hw *hw = &adapter->hw;
2613 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2614
2615 if (adapter->msix_entries) {
2616 int vector;
2617
2618 for (vector = 0; vector < adapter->num_vectors; vector++)
2619 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2620 } else {
2621 ew32(ITR, new_itr);
2622 }
2623}
2624
2625/**
2626 * e1000_alloc_queues - Allocate memory for all rings
2627 * @adapter: board private structure to initialize
2628 **/
2629static int e1000_alloc_queues(struct e1000_adapter *adapter)
2630{
2631 int size = sizeof(struct e1000_ring);
2632
2633 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2634 if (!adapter->tx_ring)
2635 goto err;
2636 adapter->tx_ring->count = adapter->tx_ring_count;
2637 adapter->tx_ring->adapter = adapter;
2638
2639 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2640 if (!adapter->rx_ring)
2641 goto err;
2642 adapter->rx_ring->count = adapter->rx_ring_count;
2643 adapter->rx_ring->adapter = adapter;
2644
2645 return 0;
2646err:
2647 e_err("Unable to allocate memory for queues\n");
2648 kfree(adapter->rx_ring);
2649 kfree(adapter->tx_ring);
2650 return -ENOMEM;
2651}
2652
2653/**
2654 * e1000e_poll - NAPI Rx polling callback
2655 * @napi: struct associated with this polling callback
2656 * @budget: number of packets driver is allowed to process this poll
2657 **/
2658static int e1000e_poll(struct napi_struct *napi, int budget)
2659{
2660 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2661 napi);
2662 struct e1000_hw *hw = &adapter->hw;
2663 struct net_device *poll_dev = adapter->netdev;
2664 int tx_cleaned = 1, work_done = 0;
2665
2666 adapter = netdev_priv(poll_dev);
2667
2668 if (!adapter->msix_entries ||
2669 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2670 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2671
2672 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2673
2674 if (!tx_cleaned || work_done == budget)
2675 return budget;
2676
2677 /* Exit the polling mode, but don't re-enable interrupts if stack might
2678 * poll us due to busy-polling
2679 */
2680 if (likely(napi_complete_done(napi, work_done))) {
2681 if (adapter->itr_setting & 3)
2682 e1000_set_itr(adapter);
2683 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2684 if (adapter->msix_entries)
2685 ew32(IMS, adapter->rx_ring->ims_val);
2686 else
2687 e1000_irq_enable(adapter);
2688 }
2689 }
2690
2691 return work_done;
2692}
2693
2694static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2695 __always_unused __be16 proto, u16 vid)
2696{
2697 struct e1000_adapter *adapter = netdev_priv(netdev);
2698 struct e1000_hw *hw = &adapter->hw;
2699 u32 vfta, index;
2700
2701 /* don't update vlan cookie if already programmed */
2702 if ((adapter->hw.mng_cookie.status &
2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2704 (vid == adapter->mng_vlan_id))
2705 return 0;
2706
2707 /* add VID to filter table */
2708 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2709 index = (vid >> 5) & 0x7F;
2710 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2711 vfta |= BIT((vid & 0x1F));
2712 hw->mac.ops.write_vfta(hw, index, vfta);
2713 }
2714
2715 set_bit(vid, adapter->active_vlans);
2716
2717 return 0;
2718}
2719
2720static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2721 __always_unused __be16 proto, u16 vid)
2722{
2723 struct e1000_adapter *adapter = netdev_priv(netdev);
2724 struct e1000_hw *hw = &adapter->hw;
2725 u32 vfta, index;
2726
2727 if ((adapter->hw.mng_cookie.status &
2728 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2729 (vid == adapter->mng_vlan_id)) {
2730 /* release control to f/w */
2731 e1000e_release_hw_control(adapter);
2732 return 0;
2733 }
2734
2735 /* remove VID from filter table */
2736 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2737 index = (vid >> 5) & 0x7F;
2738 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2739 vfta &= ~BIT((vid & 0x1F));
2740 hw->mac.ops.write_vfta(hw, index, vfta);
2741 }
2742
2743 clear_bit(vid, adapter->active_vlans);
2744
2745 return 0;
2746}
2747
2748/**
2749 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2750 * @adapter: board private structure to initialize
2751 **/
2752static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2753{
2754 struct net_device *netdev = adapter->netdev;
2755 struct e1000_hw *hw = &adapter->hw;
2756 u32 rctl;
2757
2758 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2759 /* disable VLAN receive filtering */
2760 rctl = er32(RCTL);
2761 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2762 ew32(RCTL, rctl);
2763
2764 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2765 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2766 adapter->mng_vlan_id);
2767 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2768 }
2769 }
2770}
2771
2772/**
2773 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2774 * @adapter: board private structure to initialize
2775 **/
2776static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2777{
2778 struct e1000_hw *hw = &adapter->hw;
2779 u32 rctl;
2780
2781 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2782 /* enable VLAN receive filtering */
2783 rctl = er32(RCTL);
2784 rctl |= E1000_RCTL_VFE;
2785 rctl &= ~E1000_RCTL_CFIEN;
2786 ew32(RCTL, rctl);
2787 }
2788}
2789
2790/**
2791 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2792 * @adapter: board private structure to initialize
2793 **/
2794static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2795{
2796 struct e1000_hw *hw = &adapter->hw;
2797 u32 ctrl;
2798
2799 /* disable VLAN tag insert/strip */
2800 ctrl = er32(CTRL);
2801 ctrl &= ~E1000_CTRL_VME;
2802 ew32(CTRL, ctrl);
2803}
2804
2805/**
2806 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2807 * @adapter: board private structure to initialize
2808 **/
2809static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2810{
2811 struct e1000_hw *hw = &adapter->hw;
2812 u32 ctrl;
2813
2814 /* enable VLAN tag insert/strip */
2815 ctrl = er32(CTRL);
2816 ctrl |= E1000_CTRL_VME;
2817 ew32(CTRL, ctrl);
2818}
2819
2820static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2821{
2822 struct net_device *netdev = adapter->netdev;
2823 u16 vid = adapter->hw.mng_cookie.vlan_id;
2824 u16 old_vid = adapter->mng_vlan_id;
2825
2826 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2827 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2828 adapter->mng_vlan_id = vid;
2829 }
2830
2831 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2832 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2833}
2834
2835static void e1000_restore_vlan(struct e1000_adapter *adapter)
2836{
2837 u16 vid;
2838
2839 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2840
2841 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2842 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2843}
2844
2845static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2846{
2847 struct e1000_hw *hw = &adapter->hw;
2848 u32 manc, manc2h, mdef, i, j;
2849
2850 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2851 return;
2852
2853 manc = er32(MANC);
2854
2855 /* enable receiving management packets to the host. this will probably
2856 * generate destination unreachable messages from the host OS, but
2857 * the packets will be handled on SMBUS
2858 */
2859 manc |= E1000_MANC_EN_MNG2HOST;
2860 manc2h = er32(MANC2H);
2861
2862 switch (hw->mac.type) {
2863 default:
2864 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2865 break;
2866 case e1000_82574:
2867 case e1000_82583:
2868 /* Check if IPMI pass-through decision filter already exists;
2869 * if so, enable it.
2870 */
2871 for (i = 0, j = 0; i < 8; i++) {
2872 mdef = er32(MDEF(i));
2873
2874 /* Ignore filters with anything other than IPMI ports */
2875 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2876 continue;
2877
2878 /* Enable this decision filter in MANC2H */
2879 if (mdef)
2880 manc2h |= BIT(i);
2881
2882 j |= mdef;
2883 }
2884
2885 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2886 break;
2887
2888 /* Create new decision filter in an empty filter */
2889 for (i = 0, j = 0; i < 8; i++)
2890 if (er32(MDEF(i)) == 0) {
2891 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2892 E1000_MDEF_PORT_664));
2893 manc2h |= BIT(1);
2894 j++;
2895 break;
2896 }
2897
2898 if (!j)
2899 e_warn("Unable to create IPMI pass-through filter\n");
2900 break;
2901 }
2902
2903 ew32(MANC2H, manc2h);
2904 ew32(MANC, manc);
2905}
2906
2907/**
2908 * e1000_configure_tx - Configure Transmit Unit after Reset
2909 * @adapter: board private structure
2910 *
2911 * Configure the Tx unit of the MAC after a reset.
2912 **/
2913static void e1000_configure_tx(struct e1000_adapter *adapter)
2914{
2915 struct e1000_hw *hw = &adapter->hw;
2916 struct e1000_ring *tx_ring = adapter->tx_ring;
2917 u64 tdba;
2918 u32 tdlen, tctl, tarc;
2919
2920 /* Setup the HW Tx Head and Tail descriptor pointers */
2921 tdba = tx_ring->dma;
2922 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2923 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2924 ew32(TDBAH(0), (tdba >> 32));
2925 ew32(TDLEN(0), tdlen);
2926 ew32(TDH(0), 0);
2927 ew32(TDT(0), 0);
2928 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2929 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2930
2931 writel(0, tx_ring->head);
2932 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2933 e1000e_update_tdt_wa(tx_ring, 0);
2934 else
2935 writel(0, tx_ring->tail);
2936
2937 /* Set the Tx Interrupt Delay register */
2938 ew32(TIDV, adapter->tx_int_delay);
2939 /* Tx irq moderation */
2940 ew32(TADV, adapter->tx_abs_int_delay);
2941
2942 if (adapter->flags2 & FLAG2_DMA_BURST) {
2943 u32 txdctl = er32(TXDCTL(0));
2944
2945 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2946 E1000_TXDCTL_WTHRESH);
2947 /* set up some performance related parameters to encourage the
2948 * hardware to use the bus more efficiently in bursts, depends
2949 * on the tx_int_delay to be enabled,
2950 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2951 * hthresh = 1 ==> prefetch when one or more available
2952 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2953 * BEWARE: this seems to work but should be considered first if
2954 * there are Tx hangs or other Tx related bugs
2955 */
2956 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2957 ew32(TXDCTL(0), txdctl);
2958 }
2959 /* erratum work around: set txdctl the same for both queues */
2960 ew32(TXDCTL(1), er32(TXDCTL(0)));
2961
2962 /* Program the Transmit Control Register */
2963 tctl = er32(TCTL);
2964 tctl &= ~E1000_TCTL_CT;
2965 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2966 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2967
2968 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2969 tarc = er32(TARC(0));
2970 /* set the speed mode bit, we'll clear it if we're not at
2971 * gigabit link later
2972 */
2973#define SPEED_MODE_BIT BIT(21)
2974 tarc |= SPEED_MODE_BIT;
2975 ew32(TARC(0), tarc);
2976 }
2977
2978 /* errata: program both queues to unweighted RR */
2979 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2980 tarc = er32(TARC(0));
2981 tarc |= 1;
2982 ew32(TARC(0), tarc);
2983 tarc = er32(TARC(1));
2984 tarc |= 1;
2985 ew32(TARC(1), tarc);
2986 }
2987
2988 /* Setup Transmit Descriptor Settings for eop descriptor */
2989 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2990
2991 /* only set IDE if we are delaying interrupts using the timers */
2992 if (adapter->tx_int_delay)
2993 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2994
2995 /* enable Report Status bit */
2996 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2997
2998 ew32(TCTL, tctl);
2999
3000 hw->mac.ops.config_collision_dist(hw);
3001
3002 /* SPT and KBL Si errata workaround to avoid data corruption */
3003 if (hw->mac.type == e1000_pch_spt) {
3004 u32 reg_val;
3005
3006 reg_val = er32(IOSFPC);
3007 reg_val |= E1000_RCTL_RDMTS_HEX;
3008 ew32(IOSFPC, reg_val);
3009
3010 reg_val = er32(TARC(0));
3011 /* SPT and KBL Si errata workaround to avoid Tx hang.
3012 * Dropping the number of outstanding requests from
3013 * 3 to 2 in order to avoid a buffer overrun.
3014 */
3015 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3016 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3017 ew32(TARC(0), reg_val);
3018 }
3019}
3020
3021#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3022 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3023
3024/**
3025 * e1000_setup_rctl - configure the receive control registers
3026 * @adapter: Board private structure
3027 **/
3028static void e1000_setup_rctl(struct e1000_adapter *adapter)
3029{
3030 struct e1000_hw *hw = &adapter->hw;
3031 u32 rctl, rfctl;
3032 u32 pages = 0;
3033
3034 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3035 * If jumbo frames not set, program related MAC/PHY registers
3036 * to h/w defaults
3037 */
3038 if (hw->mac.type >= e1000_pch2lan) {
3039 s32 ret_val;
3040
3041 if (adapter->netdev->mtu > ETH_DATA_LEN)
3042 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3043 else
3044 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3045
3046 if (ret_val)
3047 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3048 }
3049
3050 /* Program MC offset vector base */
3051 rctl = er32(RCTL);
3052 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3053 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3054 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3055 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3056
3057 /* Do not Store bad packets */
3058 rctl &= ~E1000_RCTL_SBP;
3059
3060 /* Enable Long Packet receive */
3061 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3062 rctl &= ~E1000_RCTL_LPE;
3063 else
3064 rctl |= E1000_RCTL_LPE;
3065
3066 /* Some systems expect that the CRC is included in SMBUS traffic. The
3067 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3068 * host memory when this is enabled
3069 */
3070 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3071 rctl |= E1000_RCTL_SECRC;
3072
3073 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3074 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3075 u16 phy_data;
3076
3077 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3078 phy_data &= 0xfff8;
3079 phy_data |= BIT(2);
3080 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3081
3082 e1e_rphy(hw, 22, &phy_data);
3083 phy_data &= 0x0fff;
3084 phy_data |= BIT(14);
3085 e1e_wphy(hw, 0x10, 0x2823);
3086 e1e_wphy(hw, 0x11, 0x0003);
3087 e1e_wphy(hw, 22, phy_data);
3088 }
3089
3090 /* Setup buffer sizes */
3091 rctl &= ~E1000_RCTL_SZ_4096;
3092 rctl |= E1000_RCTL_BSEX;
3093 switch (adapter->rx_buffer_len) {
3094 case 2048:
3095 default:
3096 rctl |= E1000_RCTL_SZ_2048;
3097 rctl &= ~E1000_RCTL_BSEX;
3098 break;
3099 case 4096:
3100 rctl |= E1000_RCTL_SZ_4096;
3101 break;
3102 case 8192:
3103 rctl |= E1000_RCTL_SZ_8192;
3104 break;
3105 case 16384:
3106 rctl |= E1000_RCTL_SZ_16384;
3107 break;
3108 }
3109
3110 /* Enable Extended Status in all Receive Descriptors */
3111 rfctl = er32(RFCTL);
3112 rfctl |= E1000_RFCTL_EXTEN;
3113 ew32(RFCTL, rfctl);
3114
3115 /* 82571 and greater support packet-split where the protocol
3116 * header is placed in skb->data and the packet data is
3117 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3118 * In the case of a non-split, skb->data is linearly filled,
3119 * followed by the page buffers. Therefore, skb->data is
3120 * sized to hold the largest protocol header.
3121 *
3122 * allocations using alloc_page take too long for regular MTU
3123 * so only enable packet split for jumbo frames
3124 *
3125 * Using pages when the page size is greater than 16k wastes
3126 * a lot of memory, since we allocate 3 pages at all times
3127 * per packet.
3128 */
3129 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3130 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3131 adapter->rx_ps_pages = pages;
3132 else
3133 adapter->rx_ps_pages = 0;
3134
3135 if (adapter->rx_ps_pages) {
3136 u32 psrctl = 0;
3137
3138 /* Enable Packet split descriptors */
3139 rctl |= E1000_RCTL_DTYP_PS;
3140
3141 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3142
3143 switch (adapter->rx_ps_pages) {
3144 case 3:
3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3146 fallthrough;
3147 case 2:
3148 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3149 fallthrough;
3150 case 1:
3151 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3152 break;
3153 }
3154
3155 ew32(PSRCTL, psrctl);
3156 }
3157
3158 /* This is useful for sniffing bad packets. */
3159 if (adapter->netdev->features & NETIF_F_RXALL) {
3160 /* UPE and MPE will be handled by normal PROMISC logic
3161 * in e1000e_set_rx_mode
3162 */
3163 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3164 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3165 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3166
3167 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3168 E1000_RCTL_DPF | /* Allow filtered pause */
3169 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3170 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3171 * and that breaks VLANs.
3172 */
3173 }
3174
3175 ew32(RCTL, rctl);
3176 /* just started the receive unit, no need to restart */
3177 adapter->flags &= ~FLAG_RESTART_NOW;
3178}
3179
3180/**
3181 * e1000_configure_rx - Configure Receive Unit after Reset
3182 * @adapter: board private structure
3183 *
3184 * Configure the Rx unit of the MAC after a reset.
3185 **/
3186static void e1000_configure_rx(struct e1000_adapter *adapter)
3187{
3188 struct e1000_hw *hw = &adapter->hw;
3189 struct e1000_ring *rx_ring = adapter->rx_ring;
3190 u64 rdba;
3191 u32 rdlen, rctl, rxcsum, ctrl_ext;
3192
3193 if (adapter->rx_ps_pages) {
3194 /* this is a 32 byte descriptor */
3195 rdlen = rx_ring->count *
3196 sizeof(union e1000_rx_desc_packet_split);
3197 adapter->clean_rx = e1000_clean_rx_irq_ps;
3198 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3199 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3200 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3201 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3202 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3203 } else {
3204 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3205 adapter->clean_rx = e1000_clean_rx_irq;
3206 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3207 }
3208
3209 /* disable receives while setting up the descriptors */
3210 rctl = er32(RCTL);
3211 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3212 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3213 e1e_flush();
3214 usleep_range(10000, 11000);
3215
3216 if (adapter->flags2 & FLAG2_DMA_BURST) {
3217 /* set the writeback threshold (only takes effect if the RDTR
3218 * is set). set GRAN=1 and write back up to 0x4 worth, and
3219 * enable prefetching of 0x20 Rx descriptors
3220 * granularity = 01
3221 * wthresh = 04,
3222 * hthresh = 04,
3223 * pthresh = 0x20
3224 */
3225 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3226 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3227 }
3228
3229 /* set the Receive Delay Timer Register */
3230 ew32(RDTR, adapter->rx_int_delay);
3231
3232 /* irq moderation */
3233 ew32(RADV, adapter->rx_abs_int_delay);
3234 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3235 e1000e_write_itr(adapter, adapter->itr);
3236
3237 ctrl_ext = er32(CTRL_EXT);
3238 /* Auto-Mask interrupts upon ICR access */
3239 ctrl_ext |= E1000_CTRL_EXT_IAME;
3240 ew32(IAM, 0xffffffff);
3241 ew32(CTRL_EXT, ctrl_ext);
3242 e1e_flush();
3243
3244 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3245 * the Base and Length of the Rx Descriptor Ring
3246 */
3247 rdba = rx_ring->dma;
3248 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3249 ew32(RDBAH(0), (rdba >> 32));
3250 ew32(RDLEN(0), rdlen);
3251 ew32(RDH(0), 0);
3252 ew32(RDT(0), 0);
3253 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3254 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3255
3256 writel(0, rx_ring->head);
3257 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3258 e1000e_update_rdt_wa(rx_ring, 0);
3259 else
3260 writel(0, rx_ring->tail);
3261
3262 /* Enable Receive Checksum Offload for TCP and UDP */
3263 rxcsum = er32(RXCSUM);
3264 if (adapter->netdev->features & NETIF_F_RXCSUM)
3265 rxcsum |= E1000_RXCSUM_TUOFL;
3266 else
3267 rxcsum &= ~E1000_RXCSUM_TUOFL;
3268 ew32(RXCSUM, rxcsum);
3269
3270 /* With jumbo frames, excessive C-state transition latencies result
3271 * in dropped transactions.
3272 */
3273 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3274 u32 lat =
3275 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3276 adapter->max_frame_size) * 8 / 1000;
3277
3278 if (adapter->flags & FLAG_IS_ICH) {
3279 u32 rxdctl = er32(RXDCTL(0));
3280
3281 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3282 }
3283
3284 dev_info(&adapter->pdev->dev,
3285 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3286 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
3287 } else {
3288 cpu_latency_qos_update_request(&adapter->pm_qos_req,
3289 PM_QOS_DEFAULT_VALUE);
3290 }
3291
3292 /* Enable Receives */
3293 ew32(RCTL, rctl);
3294}
3295
3296/**
3297 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3298 * @netdev: network interface device structure
3299 *
3300 * Writes multicast address list to the MTA hash table.
3301 * Returns: -ENOMEM on failure
3302 * 0 on no addresses written
3303 * X on writing X addresses to MTA
3304 */
3305static int e1000e_write_mc_addr_list(struct net_device *netdev)
3306{
3307 struct e1000_adapter *adapter = netdev_priv(netdev);
3308 struct e1000_hw *hw = &adapter->hw;
3309 struct netdev_hw_addr *ha;
3310 u8 *mta_list;
3311 int i;
3312
3313 if (netdev_mc_empty(netdev)) {
3314 /* nothing to program, so clear mc list */
3315 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3316 return 0;
3317 }
3318
3319 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3320 if (!mta_list)
3321 return -ENOMEM;
3322
3323 /* update_mc_addr_list expects a packed array of only addresses. */
3324 i = 0;
3325 netdev_for_each_mc_addr(ha, netdev)
3326 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3327
3328 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3329 kfree(mta_list);
3330
3331 return netdev_mc_count(netdev);
3332}
3333
3334/**
3335 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3336 * @netdev: network interface device structure
3337 *
3338 * Writes unicast address list to the RAR table.
3339 * Returns: -ENOMEM on failure/insufficient address space
3340 * 0 on no addresses written
3341 * X on writing X addresses to the RAR table
3342 **/
3343static int e1000e_write_uc_addr_list(struct net_device *netdev)
3344{
3345 struct e1000_adapter *adapter = netdev_priv(netdev);
3346 struct e1000_hw *hw = &adapter->hw;
3347 unsigned int rar_entries;
3348 int count = 0;
3349
3350 rar_entries = hw->mac.ops.rar_get_count(hw);
3351
3352 /* save a rar entry for our hardware address */
3353 rar_entries--;
3354
3355 /* save a rar entry for the LAA workaround */
3356 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3357 rar_entries--;
3358
3359 /* return ENOMEM indicating insufficient memory for addresses */
3360 if (netdev_uc_count(netdev) > rar_entries)
3361 return -ENOMEM;
3362
3363 if (!netdev_uc_empty(netdev) && rar_entries) {
3364 struct netdev_hw_addr *ha;
3365
3366 /* write the addresses in reverse order to avoid write
3367 * combining
3368 */
3369 netdev_for_each_uc_addr(ha, netdev) {
3370 int ret_val;
3371
3372 if (!rar_entries)
3373 break;
3374 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3375 if (ret_val < 0)
3376 return -ENOMEM;
3377 count++;
3378 }
3379 }
3380
3381 /* zero out the remaining RAR entries not used above */
3382 for (; rar_entries > 0; rar_entries--) {
3383 ew32(RAH(rar_entries), 0);
3384 ew32(RAL(rar_entries), 0);
3385 }
3386 e1e_flush();
3387
3388 return count;
3389}
3390
3391/**
3392 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3393 * @netdev: network interface device structure
3394 *
3395 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3396 * address list or the network interface flags are updated. This routine is
3397 * responsible for configuring the hardware for proper unicast, multicast,
3398 * promiscuous mode, and all-multi behavior.
3399 **/
3400static void e1000e_set_rx_mode(struct net_device *netdev)
3401{
3402 struct e1000_adapter *adapter = netdev_priv(netdev);
3403 struct e1000_hw *hw = &adapter->hw;
3404 u32 rctl;
3405
3406 if (pm_runtime_suspended(netdev->dev.parent))
3407 return;
3408
3409 /* Check for Promiscuous and All Multicast modes */
3410 rctl = er32(RCTL);
3411
3412 /* clear the affected bits */
3413 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3414
3415 if (netdev->flags & IFF_PROMISC) {
3416 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3417 /* Do not hardware filter VLANs in promisc mode */
3418 e1000e_vlan_filter_disable(adapter);
3419 } else {
3420 int count;
3421
3422 if (netdev->flags & IFF_ALLMULTI) {
3423 rctl |= E1000_RCTL_MPE;
3424 } else {
3425 /* Write addresses to the MTA, if the attempt fails
3426 * then we should just turn on promiscuous mode so
3427 * that we can at least receive multicast traffic
3428 */
3429 count = e1000e_write_mc_addr_list(netdev);
3430 if (count < 0)
3431 rctl |= E1000_RCTL_MPE;
3432 }
3433 e1000e_vlan_filter_enable(adapter);
3434 /* Write addresses to available RAR registers, if there is not
3435 * sufficient space to store all the addresses then enable
3436 * unicast promiscuous mode
3437 */
3438 count = e1000e_write_uc_addr_list(netdev);
3439 if (count < 0)
3440 rctl |= E1000_RCTL_UPE;
3441 }
3442
3443 ew32(RCTL, rctl);
3444
3445 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3446 e1000e_vlan_strip_enable(adapter);
3447 else
3448 e1000e_vlan_strip_disable(adapter);
3449}
3450
3451static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3452{
3453 struct e1000_hw *hw = &adapter->hw;
3454 u32 mrqc, rxcsum;
3455 u32 rss_key[10];
3456 int i;
3457
3458 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3459 for (i = 0; i < 10; i++)
3460 ew32(RSSRK(i), rss_key[i]);
3461
3462 /* Direct all traffic to queue 0 */
3463 for (i = 0; i < 32; i++)
3464 ew32(RETA(i), 0);
3465
3466 /* Disable raw packet checksumming so that RSS hash is placed in
3467 * descriptor on writeback.
3468 */
3469 rxcsum = er32(RXCSUM);
3470 rxcsum |= E1000_RXCSUM_PCSD;
3471
3472 ew32(RXCSUM, rxcsum);
3473
3474 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3475 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3476 E1000_MRQC_RSS_FIELD_IPV6 |
3477 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3478 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3479
3480 ew32(MRQC, mrqc);
3481}
3482
3483/**
3484 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3485 * @adapter: board private structure
3486 * @timinca: pointer to returned time increment attributes
3487 *
3488 * Get attributes for incrementing the System Time Register SYSTIML/H at
3489 * the default base frequency, and set the cyclecounter shift value.
3490 **/
3491s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3492{
3493 struct e1000_hw *hw = &adapter->hw;
3494 u32 incvalue, incperiod, shift;
3495
3496 /* Make sure clock is enabled on I217/I218/I219 before checking
3497 * the frequency
3498 */
3499 if ((hw->mac.type >= e1000_pch_lpt) &&
3500 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3501 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3502 u32 fextnvm7 = er32(FEXTNVM7);
3503
3504 if (!(fextnvm7 & BIT(0))) {
3505 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3506 e1e_flush();
3507 }
3508 }
3509
3510 switch (hw->mac.type) {
3511 case e1000_pch2lan:
3512 /* Stable 96MHz frequency */
3513 incperiod = INCPERIOD_96MHZ;
3514 incvalue = INCVALUE_96MHZ;
3515 shift = INCVALUE_SHIFT_96MHZ;
3516 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3517 break;
3518 case e1000_pch_lpt:
3519 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3520 /* Stable 96MHz frequency */
3521 incperiod = INCPERIOD_96MHZ;
3522 incvalue = INCVALUE_96MHZ;
3523 shift = INCVALUE_SHIFT_96MHZ;
3524 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3525 } else {
3526 /* Stable 25MHz frequency */
3527 incperiod = INCPERIOD_25MHZ;
3528 incvalue = INCVALUE_25MHZ;
3529 shift = INCVALUE_SHIFT_25MHZ;
3530 adapter->cc.shift = shift;
3531 }
3532 break;
3533 case e1000_pch_spt:
3534 /* Stable 24MHz frequency */
3535 incperiod = INCPERIOD_24MHZ;
3536 incvalue = INCVALUE_24MHZ;
3537 shift = INCVALUE_SHIFT_24MHZ;
3538 adapter->cc.shift = shift;
3539 break;
3540 case e1000_pch_cnp:
3541 case e1000_pch_tgp:
3542 case e1000_pch_adp:
3543 case e1000_pch_mtp:
3544 case e1000_pch_lnp:
3545 case e1000_pch_ptp:
3546 case e1000_pch_nvp:
3547 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3548 /* Stable 24MHz frequency */
3549 incperiod = INCPERIOD_24MHZ;
3550 incvalue = INCVALUE_24MHZ;
3551 shift = INCVALUE_SHIFT_24MHZ;
3552 adapter->cc.shift = shift;
3553 } else {
3554 /* Stable 38400KHz frequency */
3555 incperiod = INCPERIOD_38400KHZ;
3556 incvalue = INCVALUE_38400KHZ;
3557 shift = INCVALUE_SHIFT_38400KHZ;
3558 adapter->cc.shift = shift;
3559 }
3560 break;
3561 case e1000_82574:
3562 case e1000_82583:
3563 /* Stable 25MHz frequency */
3564 incperiod = INCPERIOD_25MHZ;
3565 incvalue = INCVALUE_25MHZ;
3566 shift = INCVALUE_SHIFT_25MHZ;
3567 adapter->cc.shift = shift;
3568 break;
3569 default:
3570 return -EINVAL;
3571 }
3572
3573 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3574 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3575
3576 return 0;
3577}
3578
3579/**
3580 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3581 * @adapter: board private structure
3582 * @config: timestamp configuration
3583 *
3584 * Outgoing time stamping can be enabled and disabled. Play nice and
3585 * disable it when requested, although it shouldn't cause any overhead
3586 * when no packet needs it. At most one packet in the queue may be
3587 * marked for time stamping, otherwise it would be impossible to tell
3588 * for sure to which packet the hardware time stamp belongs.
3589 *
3590 * Incoming time stamping has to be configured via the hardware filters.
3591 * Not all combinations are supported, in particular event type has to be
3592 * specified. Matching the kind of event packet is not supported, with the
3593 * exception of "all V2 events regardless of level 2 or 4".
3594 **/
3595static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3596 struct hwtstamp_config *config)
3597{
3598 struct e1000_hw *hw = &adapter->hw;
3599 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3600 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3601 u32 rxmtrl = 0;
3602 u16 rxudp = 0;
3603 bool is_l4 = false;
3604 bool is_l2 = false;
3605 u32 regval;
3606
3607 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3608 return -EINVAL;
3609
3610 switch (config->tx_type) {
3611 case HWTSTAMP_TX_OFF:
3612 tsync_tx_ctl = 0;
3613 break;
3614 case HWTSTAMP_TX_ON:
3615 break;
3616 default:
3617 return -ERANGE;
3618 }
3619
3620 switch (config->rx_filter) {
3621 case HWTSTAMP_FILTER_NONE:
3622 tsync_rx_ctl = 0;
3623 break;
3624 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3625 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3626 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3627 is_l4 = true;
3628 break;
3629 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3630 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3631 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3632 is_l4 = true;
3633 break;
3634 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3635 /* Also time stamps V2 L2 Path Delay Request/Response */
3636 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3637 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3638 is_l2 = true;
3639 break;
3640 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3641 /* Also time stamps V2 L2 Path Delay Request/Response. */
3642 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3643 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3644 is_l2 = true;
3645 break;
3646 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3647 /* Hardware cannot filter just V2 L4 Sync messages */
3648 fallthrough;
3649 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3650 /* Also time stamps V2 Path Delay Request/Response. */
3651 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3652 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3653 is_l2 = true;
3654 is_l4 = true;
3655 break;
3656 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3657 /* Hardware cannot filter just V2 L4 Delay Request messages */
3658 fallthrough;
3659 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3660 /* Also time stamps V2 Path Delay Request/Response. */
3661 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3662 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3663 is_l2 = true;
3664 is_l4 = true;
3665 break;
3666 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3667 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3668 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3669 fallthrough;
3670 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3671 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3672 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3673 is_l2 = true;
3674 is_l4 = true;
3675 break;
3676 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3677 /* For V1, the hardware can only filter Sync messages or
3678 * Delay Request messages but not both so fall-through to
3679 * time stamp all packets.
3680 */
3681 fallthrough;
3682 case HWTSTAMP_FILTER_NTP_ALL:
3683 case HWTSTAMP_FILTER_ALL:
3684 is_l2 = true;
3685 is_l4 = true;
3686 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3687 config->rx_filter = HWTSTAMP_FILTER_ALL;
3688 break;
3689 default:
3690 return -ERANGE;
3691 }
3692
3693 adapter->hwtstamp_config = *config;
3694
3695 /* enable/disable Tx h/w time stamping */
3696 regval = er32(TSYNCTXCTL);
3697 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3698 regval |= tsync_tx_ctl;
3699 ew32(TSYNCTXCTL, regval);
3700 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3701 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3702 e_err("Timesync Tx Control register not set as expected\n");
3703 return -EAGAIN;
3704 }
3705
3706 /* enable/disable Rx h/w time stamping */
3707 regval = er32(TSYNCRXCTL);
3708 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3709 regval |= tsync_rx_ctl;
3710 ew32(TSYNCRXCTL, regval);
3711 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3712 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3713 (regval & (E1000_TSYNCRXCTL_ENABLED |
3714 E1000_TSYNCRXCTL_TYPE_MASK))) {
3715 e_err("Timesync Rx Control register not set as expected\n");
3716 return -EAGAIN;
3717 }
3718
3719 /* L2: define ethertype filter for time stamped packets */
3720 if (is_l2)
3721 rxmtrl |= ETH_P_1588;
3722
3723 /* define which PTP packets get time stamped */
3724 ew32(RXMTRL, rxmtrl);
3725
3726 /* Filter by destination port */
3727 if (is_l4) {
3728 rxudp = PTP_EV_PORT;
3729 cpu_to_be16s(&rxudp);
3730 }
3731 ew32(RXUDP, rxudp);
3732
3733 e1e_flush();
3734
3735 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3736 er32(RXSTMPH);
3737 er32(TXSTMPH);
3738
3739 return 0;
3740}
3741
3742/**
3743 * e1000_configure - configure the hardware for Rx and Tx
3744 * @adapter: private board structure
3745 **/
3746static void e1000_configure(struct e1000_adapter *adapter)
3747{
3748 struct e1000_ring *rx_ring = adapter->rx_ring;
3749
3750 e1000e_set_rx_mode(adapter->netdev);
3751
3752 e1000_restore_vlan(adapter);
3753 e1000_init_manageability_pt(adapter);
3754
3755 e1000_configure_tx(adapter);
3756
3757 if (adapter->netdev->features & NETIF_F_RXHASH)
3758 e1000e_setup_rss_hash(adapter);
3759 e1000_setup_rctl(adapter);
3760 e1000_configure_rx(adapter);
3761 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3762}
3763
3764/**
3765 * e1000e_power_up_phy - restore link in case the phy was powered down
3766 * @adapter: address of board private structure
3767 *
3768 * The phy may be powered down to save power and turn off link when the
3769 * driver is unloaded and wake on lan is not enabled (among others)
3770 * *** this routine MUST be followed by a call to e1000e_reset ***
3771 **/
3772void e1000e_power_up_phy(struct e1000_adapter *adapter)
3773{
3774 if (adapter->hw.phy.ops.power_up)
3775 adapter->hw.phy.ops.power_up(&adapter->hw);
3776
3777 adapter->hw.mac.ops.setup_link(&adapter->hw);
3778}
3779
3780/**
3781 * e1000_power_down_phy - Power down the PHY
3782 * @adapter: board private structure
3783 *
3784 * Power down the PHY so no link is implied when interface is down.
3785 * The PHY cannot be powered down if management or WoL is active.
3786 */
3787static void e1000_power_down_phy(struct e1000_adapter *adapter)
3788{
3789 if (adapter->hw.phy.ops.power_down)
3790 adapter->hw.phy.ops.power_down(&adapter->hw);
3791}
3792
3793/**
3794 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3795 * @adapter: board private structure
3796 *
3797 * We want to clear all pending descriptors from the TX ring.
3798 * zeroing happens when the HW reads the regs. We assign the ring itself as
3799 * the data of the next descriptor. We don't care about the data we are about
3800 * to reset the HW.
3801 */
3802static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3803{
3804 struct e1000_hw *hw = &adapter->hw;
3805 struct e1000_ring *tx_ring = adapter->tx_ring;
3806 struct e1000_tx_desc *tx_desc = NULL;
3807 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3808 u16 size = 512;
3809
3810 tctl = er32(TCTL);
3811 ew32(TCTL, tctl | E1000_TCTL_EN);
3812 tdt = er32(TDT(0));
3813 BUG_ON(tdt != tx_ring->next_to_use);
3814 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3815 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
3816
3817 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3818 tx_desc->upper.data = 0;
3819 /* flush descriptors to memory before notifying the HW */
3820 wmb();
3821 tx_ring->next_to_use++;
3822 if (tx_ring->next_to_use == tx_ring->count)
3823 tx_ring->next_to_use = 0;
3824 ew32(TDT(0), tx_ring->next_to_use);
3825 usleep_range(200, 250);
3826}
3827
3828/**
3829 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3830 * @adapter: board private structure
3831 *
3832 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3833 */
3834static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3835{
3836 u32 rctl, rxdctl;
3837 struct e1000_hw *hw = &adapter->hw;
3838
3839 rctl = er32(RCTL);
3840 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3841 e1e_flush();
3842 usleep_range(100, 150);
3843
3844 rxdctl = er32(RXDCTL(0));
3845 /* zero the lower 14 bits (prefetch and host thresholds) */
3846 rxdctl &= 0xffffc000;
3847
3848 /* update thresholds: prefetch threshold to 31, host threshold to 1
3849 * and make sure the granularity is "descriptors" and not "cache lines"
3850 */
3851 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3852
3853 ew32(RXDCTL(0), rxdctl);
3854 /* momentarily enable the RX ring for the changes to take effect */
3855 ew32(RCTL, rctl | E1000_RCTL_EN);
3856 e1e_flush();
3857 usleep_range(100, 150);
3858 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3859}
3860
3861/**
3862 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3863 * @adapter: board private structure
3864 *
3865 * In i219, the descriptor rings must be emptied before resetting the HW
3866 * or before changing the device state to D3 during runtime (runtime PM).
3867 *
3868 * Failure to do this will cause the HW to enter a unit hang state which can
3869 * only be released by PCI reset on the device
3870 *
3871 */
3872
3873static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3874{
3875 u16 hang_state;
3876 u32 fext_nvm11, tdlen;
3877 struct e1000_hw *hw = &adapter->hw;
3878
3879 /* First, disable MULR fix in FEXTNVM11 */
3880 fext_nvm11 = er32(FEXTNVM11);
3881 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3882 ew32(FEXTNVM11, fext_nvm11);
3883 /* do nothing if we're not in faulty state, or if the queue is empty */
3884 tdlen = er32(TDLEN(0));
3885 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3886 &hang_state);
3887 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3888 return;
3889 e1000_flush_tx_ring(adapter);
3890 /* recheck, maybe the fault is caused by the rx ring */
3891 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3892 &hang_state);
3893 if (hang_state & FLUSH_DESC_REQUIRED)
3894 e1000_flush_rx_ring(adapter);
3895}
3896
3897/**
3898 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3899 * @adapter: board private structure
3900 *
3901 * When the MAC is reset, all hardware bits for timesync will be reset to the
3902 * default values. This function will restore the settings last in place.
3903 * Since the clock SYSTIME registers are reset, we will simply restore the
3904 * cyclecounter to the kernel real clock time.
3905 **/
3906static void e1000e_systim_reset(struct e1000_adapter *adapter)
3907{
3908 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3909 struct e1000_hw *hw = &adapter->hw;
3910 unsigned long flags;
3911 u32 timinca;
3912 s32 ret_val;
3913
3914 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3915 return;
3916
3917 if (info->adjfine) {
3918 /* restore the previous ptp frequency delta */
3919 ret_val = info->adjfine(info, adapter->ptp_delta);
3920 } else {
3921 /* set the default base frequency if no adjustment possible */
3922 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3923 if (!ret_val)
3924 ew32(TIMINCA, timinca);
3925 }
3926
3927 if (ret_val) {
3928 dev_warn(&adapter->pdev->dev,
3929 "Failed to restore TIMINCA clock rate delta: %d\n",
3930 ret_val);
3931 return;
3932 }
3933
3934 /* reset the systim ns time counter */
3935 spin_lock_irqsave(&adapter->systim_lock, flags);
3936 timecounter_init(&adapter->tc, &adapter->cc,
3937 ktime_to_ns(ktime_get_real()));
3938 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3939
3940 /* restore the previous hwtstamp configuration settings */
3941 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3942}
3943
3944/**
3945 * e1000e_reset - bring the hardware into a known good state
3946 * @adapter: board private structure
3947 *
3948 * This function boots the hardware and enables some settings that
3949 * require a configuration cycle of the hardware - those cannot be
3950 * set/changed during runtime. After reset the device needs to be
3951 * properly configured for Rx, Tx etc.
3952 */
3953void e1000e_reset(struct e1000_adapter *adapter)
3954{
3955 struct e1000_mac_info *mac = &adapter->hw.mac;
3956 struct e1000_fc_info *fc = &adapter->hw.fc;
3957 struct e1000_hw *hw = &adapter->hw;
3958 u32 tx_space, min_tx_space, min_rx_space;
3959 u32 pba = adapter->pba;
3960 u16 hwm;
3961
3962 /* reset Packet Buffer Allocation to default */
3963 ew32(PBA, pba);
3964
3965 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3966 /* To maintain wire speed transmits, the Tx FIFO should be
3967 * large enough to accommodate two full transmit packets,
3968 * rounded up to the next 1KB and expressed in KB. Likewise,
3969 * the Rx FIFO should be large enough to accommodate at least
3970 * one full receive packet and is similarly rounded up and
3971 * expressed in KB.
3972 */
3973 pba = er32(PBA);
3974 /* upper 16 bits has Tx packet buffer allocation size in KB */
3975 tx_space = pba >> 16;
3976 /* lower 16 bits has Rx packet buffer allocation size in KB */
3977 pba &= 0xffff;
3978 /* the Tx fifo also stores 16 bytes of information about the Tx
3979 * but don't include ethernet FCS because hardware appends it
3980 */
3981 min_tx_space = (adapter->max_frame_size +
3982 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3983 min_tx_space = ALIGN(min_tx_space, 1024);
3984 min_tx_space >>= 10;
3985 /* software strips receive CRC, so leave room for it */
3986 min_rx_space = adapter->max_frame_size;
3987 min_rx_space = ALIGN(min_rx_space, 1024);
3988 min_rx_space >>= 10;
3989
3990 /* If current Tx allocation is less than the min Tx FIFO size,
3991 * and the min Tx FIFO size is less than the current Rx FIFO
3992 * allocation, take space away from current Rx allocation
3993 */
3994 if ((tx_space < min_tx_space) &&
3995 ((min_tx_space - tx_space) < pba)) {
3996 pba -= min_tx_space - tx_space;
3997
3998 /* if short on Rx space, Rx wins and must trump Tx
3999 * adjustment
4000 */
4001 if (pba < min_rx_space)
4002 pba = min_rx_space;
4003 }
4004
4005 ew32(PBA, pba);
4006 }
4007
4008 /* flow control settings
4009 *
4010 * The high water mark must be low enough to fit one full frame
4011 * (or the size used for early receive) above it in the Rx FIFO.
4012 * Set it to the lower of:
4013 * - 90% of the Rx FIFO size, and
4014 * - the full Rx FIFO size minus one full frame
4015 */
4016 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4017 fc->pause_time = 0xFFFF;
4018 else
4019 fc->pause_time = E1000_FC_PAUSE_TIME;
4020 fc->send_xon = true;
4021 fc->current_mode = fc->requested_mode;
4022
4023 switch (hw->mac.type) {
4024 case e1000_ich9lan:
4025 case e1000_ich10lan:
4026 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4027 pba = 14;
4028 ew32(PBA, pba);
4029 fc->high_water = 0x2800;
4030 fc->low_water = fc->high_water - 8;
4031 break;
4032 }
4033 fallthrough;
4034 default:
4035 hwm = min(((pba << 10) * 9 / 10),
4036 ((pba << 10) - adapter->max_frame_size));
4037
4038 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4039 fc->low_water = fc->high_water - 8;
4040 break;
4041 case e1000_pchlan:
4042 /* Workaround PCH LOM adapter hangs with certain network
4043 * loads. If hangs persist, try disabling Tx flow control.
4044 */
4045 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4046 fc->high_water = 0x3500;
4047 fc->low_water = 0x1500;
4048 } else {
4049 fc->high_water = 0x5000;
4050 fc->low_water = 0x3000;
4051 }
4052 fc->refresh_time = 0x1000;
4053 break;
4054 case e1000_pch2lan:
4055 case e1000_pch_lpt:
4056 case e1000_pch_spt:
4057 case e1000_pch_cnp:
4058 case e1000_pch_tgp:
4059 case e1000_pch_adp:
4060 case e1000_pch_mtp:
4061 case e1000_pch_lnp:
4062 case e1000_pch_ptp:
4063 case e1000_pch_nvp:
4064 fc->refresh_time = 0xFFFF;
4065 fc->pause_time = 0xFFFF;
4066
4067 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4068 fc->high_water = 0x05C20;
4069 fc->low_water = 0x05048;
4070 break;
4071 }
4072
4073 pba = 14;
4074 ew32(PBA, pba);
4075 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4076 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4077 break;
4078 }
4079
4080 /* Alignment of Tx data is on an arbitrary byte boundary with the
4081 * maximum size per Tx descriptor limited only to the transmit
4082 * allocation of the packet buffer minus 96 bytes with an upper
4083 * limit of 24KB due to receive synchronization limitations.
4084 */
4085 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4086 24 << 10);
4087
4088 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4089 * fit in receive buffer.
4090 */
4091 if (adapter->itr_setting & 0x3) {
4092 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4093 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4094 dev_info(&adapter->pdev->dev,
4095 "Interrupt Throttle Rate off\n");
4096 adapter->flags2 |= FLAG2_DISABLE_AIM;
4097 e1000e_write_itr(adapter, 0);
4098 }
4099 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4100 dev_info(&adapter->pdev->dev,
4101 "Interrupt Throttle Rate on\n");
4102 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4103 adapter->itr = 20000;
4104 e1000e_write_itr(adapter, adapter->itr);
4105 }
4106 }
4107
4108 if (hw->mac.type >= e1000_pch_spt)
4109 e1000_flush_desc_rings(adapter);
4110 /* Allow time for pending master requests to run */
4111 mac->ops.reset_hw(hw);
4112
4113 /* For parts with AMT enabled, let the firmware know
4114 * that the network interface is in control
4115 */
4116 if (adapter->flags & FLAG_HAS_AMT)
4117 e1000e_get_hw_control(adapter);
4118
4119 ew32(WUC, 0);
4120
4121 if (mac->ops.init_hw(hw))
4122 e_err("Hardware Error\n");
4123
4124 e1000_update_mng_vlan(adapter);
4125
4126 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4127 ew32(VET, ETH_P_8021Q);
4128
4129 e1000e_reset_adaptive(hw);
4130
4131 /* restore systim and hwtstamp settings */
4132 e1000e_systim_reset(adapter);
4133
4134 /* Set EEE advertisement as appropriate */
4135 if (adapter->flags2 & FLAG2_HAS_EEE) {
4136 s32 ret_val;
4137 u16 adv_addr;
4138
4139 switch (hw->phy.type) {
4140 case e1000_phy_82579:
4141 adv_addr = I82579_EEE_ADVERTISEMENT;
4142 break;
4143 case e1000_phy_i217:
4144 adv_addr = I217_EEE_ADVERTISEMENT;
4145 break;
4146 default:
4147 dev_err(&adapter->pdev->dev,
4148 "Invalid PHY type setting EEE advertisement\n");
4149 return;
4150 }
4151
4152 ret_val = hw->phy.ops.acquire(hw);
4153 if (ret_val) {
4154 dev_err(&adapter->pdev->dev,
4155 "EEE advertisement - unable to acquire PHY\n");
4156 return;
4157 }
4158
4159 e1000_write_emi_reg_locked(hw, adv_addr,
4160 hw->dev_spec.ich8lan.eee_disable ?
4161 0 : adapter->eee_advert);
4162
4163 hw->phy.ops.release(hw);
4164 }
4165
4166 if (!netif_running(adapter->netdev) &&
4167 !test_bit(__E1000_TESTING, &adapter->state))
4168 e1000_power_down_phy(adapter);
4169
4170 e1000_get_phy_info(hw);
4171
4172 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4173 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4174 u16 phy_data = 0;
4175 /* speed up time to link by disabling smart power down, ignore
4176 * the return value of this function because there is nothing
4177 * different we would do if it failed
4178 */
4179 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4180 phy_data &= ~IGP02E1000_PM_SPD;
4181 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4182 }
4183 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4184 u32 reg;
4185
4186 /* Fextnvm7 @ 0xe4[2] = 1 */
4187 reg = er32(FEXTNVM7);
4188 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4189 ew32(FEXTNVM7, reg);
4190 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4191 reg = er32(FEXTNVM9);
4192 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4193 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4194 ew32(FEXTNVM9, reg);
4195 }
4196
4197}
4198
4199/**
4200 * e1000e_trigger_lsc - trigger an LSC interrupt
4201 * @adapter: board private structure
4202 *
4203 * Fire a link status change interrupt to start the watchdog.
4204 **/
4205static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4206{
4207 struct e1000_hw *hw = &adapter->hw;
4208
4209 if (adapter->msix_entries)
4210 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4211 else
4212 ew32(ICS, E1000_ICS_LSC);
4213}
4214
4215void e1000e_up(struct e1000_adapter *adapter)
4216{
4217 /* hardware has been reset, we need to reload some things */
4218 e1000_configure(adapter);
4219
4220 clear_bit(__E1000_DOWN, &adapter->state);
4221
4222 if (adapter->msix_entries)
4223 e1000_configure_msix(adapter);
4224 e1000_irq_enable(adapter);
4225
4226 /* Tx queue started by watchdog timer when link is up */
4227
4228 e1000e_trigger_lsc(adapter);
4229}
4230
4231static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4232{
4233 struct e1000_hw *hw = &adapter->hw;
4234
4235 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4236 return;
4237
4238 /* flush pending descriptor writebacks to memory */
4239 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4240 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4241
4242 /* execute the writes immediately */
4243 e1e_flush();
4244
4245 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4246 * write is successful
4247 */
4248 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4249 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4250
4251 /* execute the writes immediately */
4252 e1e_flush();
4253}
4254
4255static void e1000e_update_stats(struct e1000_adapter *adapter);
4256
4257/**
4258 * e1000e_down - quiesce the device and optionally reset the hardware
4259 * @adapter: board private structure
4260 * @reset: boolean flag to reset the hardware or not
4261 */
4262void e1000e_down(struct e1000_adapter *adapter, bool reset)
4263{
4264 struct net_device *netdev = adapter->netdev;
4265 struct e1000_hw *hw = &adapter->hw;
4266 u32 tctl, rctl;
4267
4268 /* signal that we're down so the interrupt handler does not
4269 * reschedule our watchdog timer
4270 */
4271 set_bit(__E1000_DOWN, &adapter->state);
4272
4273 netif_carrier_off(netdev);
4274
4275 /* disable receives in the hardware */
4276 rctl = er32(RCTL);
4277 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4278 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4279 /* flush and sleep below */
4280
4281 netif_stop_queue(netdev);
4282
4283 /* disable transmits in the hardware */
4284 tctl = er32(TCTL);
4285 tctl &= ~E1000_TCTL_EN;
4286 ew32(TCTL, tctl);
4287
4288 /* flush both disables and wait for them to finish */
4289 e1e_flush();
4290 usleep_range(10000, 11000);
4291
4292 e1000_irq_disable(adapter);
4293
4294 napi_synchronize(&adapter->napi);
4295
4296 del_timer_sync(&adapter->watchdog_timer);
4297 del_timer_sync(&adapter->phy_info_timer);
4298
4299 spin_lock(&adapter->stats64_lock);
4300 e1000e_update_stats(adapter);
4301 spin_unlock(&adapter->stats64_lock);
4302
4303 e1000e_flush_descriptors(adapter);
4304
4305 adapter->link_speed = 0;
4306 adapter->link_duplex = 0;
4307
4308 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4309 if ((hw->mac.type >= e1000_pch2lan) &&
4310 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4311 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4312 e_dbg("failed to disable jumbo frame workaround mode\n");
4313
4314 if (!pci_channel_offline(adapter->pdev)) {
4315 if (reset)
4316 e1000e_reset(adapter);
4317 else if (hw->mac.type >= e1000_pch_spt)
4318 e1000_flush_desc_rings(adapter);
4319 }
4320 e1000_clean_tx_ring(adapter->tx_ring);
4321 e1000_clean_rx_ring(adapter->rx_ring);
4322}
4323
4324void e1000e_reinit_locked(struct e1000_adapter *adapter)
4325{
4326 might_sleep();
4327 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4328 usleep_range(1000, 1100);
4329 e1000e_down(adapter, true);
4330 e1000e_up(adapter);
4331 clear_bit(__E1000_RESETTING, &adapter->state);
4332}
4333
4334/**
4335 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4336 * @hw: pointer to the HW structure
4337 * @systim: PHC time value read, sanitized and returned
4338 * @sts: structure to hold system time before and after reading SYSTIML,
4339 * may be NULL
4340 *
4341 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4342 * check to see that the time is incrementing at a reasonable
4343 * rate and is a multiple of incvalue.
4344 **/
4345static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4346 struct ptp_system_timestamp *sts)
4347{
4348 u64 time_delta, rem, temp;
4349 u64 systim_next;
4350 u32 incvalue;
4351 int i;
4352
4353 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4354 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4355 /* latch SYSTIMH on read of SYSTIML */
4356 ptp_read_system_prets(sts);
4357 systim_next = (u64)er32(SYSTIML);
4358 ptp_read_system_postts(sts);
4359 systim_next |= (u64)er32(SYSTIMH) << 32;
4360
4361 time_delta = systim_next - systim;
4362 temp = time_delta;
4363 /* VMWare users have seen incvalue of zero, don't div / 0 */
4364 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4365
4366 systim = systim_next;
4367
4368 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4369 break;
4370 }
4371
4372 return systim;
4373}
4374
4375/**
4376 * e1000e_read_systim - read SYSTIM register
4377 * @adapter: board private structure
4378 * @sts: structure which will contain system time before and after reading
4379 * SYSTIML, may be NULL
4380 **/
4381u64 e1000e_read_systim(struct e1000_adapter *adapter,
4382 struct ptp_system_timestamp *sts)
4383{
4384 struct e1000_hw *hw = &adapter->hw;
4385 u32 systimel, systimel_2, systimeh;
4386 u64 systim;
4387 /* SYSTIMH latching upon SYSTIML read does not work well.
4388 * This means that if SYSTIML overflows after we read it but before
4389 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4390 * will experience a huge non linear increment in the systime value
4391 * to fix that we test for overflow and if true, we re-read systime.
4392 */
4393 ptp_read_system_prets(sts);
4394 systimel = er32(SYSTIML);
4395 ptp_read_system_postts(sts);
4396 systimeh = er32(SYSTIMH);
4397 /* Is systimel is so large that overflow is possible? */
4398 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4399 ptp_read_system_prets(sts);
4400 systimel_2 = er32(SYSTIML);
4401 ptp_read_system_postts(sts);
4402 if (systimel > systimel_2) {
4403 /* There was an overflow, read again SYSTIMH, and use
4404 * systimel_2
4405 */
4406 systimeh = er32(SYSTIMH);
4407 systimel = systimel_2;
4408 }
4409 }
4410 systim = (u64)systimel;
4411 systim |= (u64)systimeh << 32;
4412
4413 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4414 systim = e1000e_sanitize_systim(hw, systim, sts);
4415
4416 return systim;
4417}
4418
4419/**
4420 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4421 * @cc: cyclecounter structure
4422 **/
4423static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4424{
4425 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4426 cc);
4427
4428 return e1000e_read_systim(adapter, NULL);
4429}
4430
4431/**
4432 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4433 * @adapter: board private structure to initialize
4434 *
4435 * e1000_sw_init initializes the Adapter private data structure.
4436 * Fields are initialized based on PCI device information and
4437 * OS network device settings (MTU size).
4438 **/
4439static int e1000_sw_init(struct e1000_adapter *adapter)
4440{
4441 struct net_device *netdev = adapter->netdev;
4442
4443 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4444 adapter->rx_ps_bsize0 = 128;
4445 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4446 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4447 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4448 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4449
4450 spin_lock_init(&adapter->stats64_lock);
4451
4452 e1000e_set_interrupt_capability(adapter);
4453
4454 if (e1000_alloc_queues(adapter))
4455 return -ENOMEM;
4456
4457 /* Setup hardware time stamping cyclecounter */
4458 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4459 adapter->cc.read = e1000e_cyclecounter_read;
4460 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4461 adapter->cc.mult = 1;
4462 /* cc.shift set in e1000e_get_base_tininca() */
4463
4464 spin_lock_init(&adapter->systim_lock);
4465 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4466 }
4467
4468 /* Explicitly disable IRQ since the NIC can be in any state. */
4469 e1000_irq_disable(adapter);
4470
4471 set_bit(__E1000_DOWN, &adapter->state);
4472 return 0;
4473}
4474
4475/**
4476 * e1000_intr_msi_test - Interrupt Handler
4477 * @irq: interrupt number
4478 * @data: pointer to a network interface device structure
4479 **/
4480static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4481{
4482 struct net_device *netdev = data;
4483 struct e1000_adapter *adapter = netdev_priv(netdev);
4484 struct e1000_hw *hw = &adapter->hw;
4485 u32 icr = er32(ICR);
4486
4487 e_dbg("icr is %08X\n", icr);
4488 if (icr & E1000_ICR_RXSEQ) {
4489 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4490 /* Force memory writes to complete before acknowledging the
4491 * interrupt is handled.
4492 */
4493 wmb();
4494 }
4495
4496 return IRQ_HANDLED;
4497}
4498
4499/**
4500 * e1000_test_msi_interrupt - Returns 0 for successful test
4501 * @adapter: board private struct
4502 *
4503 * code flow taken from tg3.c
4504 **/
4505static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4506{
4507 struct net_device *netdev = adapter->netdev;
4508 struct e1000_hw *hw = &adapter->hw;
4509 int err;
4510
4511 /* poll_enable hasn't been called yet, so don't need disable */
4512 /* clear any pending events */
4513 er32(ICR);
4514
4515 /* free the real vector and request a test handler */
4516 e1000_free_irq(adapter);
4517 e1000e_reset_interrupt_capability(adapter);
4518
4519 /* Assume that the test fails, if it succeeds then the test
4520 * MSI irq handler will unset this flag
4521 */
4522 adapter->flags |= FLAG_MSI_TEST_FAILED;
4523
4524 err = pci_enable_msi(adapter->pdev);
4525 if (err)
4526 goto msi_test_failed;
4527
4528 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4529 netdev->name, netdev);
4530 if (err) {
4531 pci_disable_msi(adapter->pdev);
4532 goto msi_test_failed;
4533 }
4534
4535 /* Force memory writes to complete before enabling and firing an
4536 * interrupt.
4537 */
4538 wmb();
4539
4540 e1000_irq_enable(adapter);
4541
4542 /* fire an unusual interrupt on the test handler */
4543 ew32(ICS, E1000_ICS_RXSEQ);
4544 e1e_flush();
4545 msleep(100);
4546
4547 e1000_irq_disable(adapter);
4548
4549 rmb(); /* read flags after interrupt has been fired */
4550
4551 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4552 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4553 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4554 } else {
4555 e_dbg("MSI interrupt test succeeded!\n");
4556 }
4557
4558 free_irq(adapter->pdev->irq, netdev);
4559 pci_disable_msi(adapter->pdev);
4560
4561msi_test_failed:
4562 e1000e_set_interrupt_capability(adapter);
4563 return e1000_request_irq(adapter);
4564}
4565
4566/**
4567 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4568 * @adapter: board private struct
4569 *
4570 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4571 **/
4572static int e1000_test_msi(struct e1000_adapter *adapter)
4573{
4574 int err;
4575 u16 pci_cmd;
4576
4577 if (!(adapter->flags & FLAG_MSI_ENABLED))
4578 return 0;
4579
4580 /* disable SERR in case the MSI write causes a master abort */
4581 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4582 if (pci_cmd & PCI_COMMAND_SERR)
4583 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4584 pci_cmd & ~PCI_COMMAND_SERR);
4585
4586 err = e1000_test_msi_interrupt(adapter);
4587
4588 /* re-enable SERR */
4589 if (pci_cmd & PCI_COMMAND_SERR) {
4590 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4591 pci_cmd |= PCI_COMMAND_SERR;
4592 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4593 }
4594
4595 return err;
4596}
4597
4598/**
4599 * e1000e_open - Called when a network interface is made active
4600 * @netdev: network interface device structure
4601 *
4602 * Returns 0 on success, negative value on failure
4603 *
4604 * The open entry point is called when a network interface is made
4605 * active by the system (IFF_UP). At this point all resources needed
4606 * for transmit and receive operations are allocated, the interrupt
4607 * handler is registered with the OS, the watchdog timer is started,
4608 * and the stack is notified that the interface is ready.
4609 **/
4610int e1000e_open(struct net_device *netdev)
4611{
4612 struct e1000_adapter *adapter = netdev_priv(netdev);
4613 struct e1000_hw *hw = &adapter->hw;
4614 struct pci_dev *pdev = adapter->pdev;
4615 int err;
4616
4617 /* disallow open during test */
4618 if (test_bit(__E1000_TESTING, &adapter->state))
4619 return -EBUSY;
4620
4621 pm_runtime_get_sync(&pdev->dev);
4622
4623 netif_carrier_off(netdev);
4624 netif_stop_queue(netdev);
4625
4626 /* allocate transmit descriptors */
4627 err = e1000e_setup_tx_resources(adapter->tx_ring);
4628 if (err)
4629 goto err_setup_tx;
4630
4631 /* allocate receive descriptors */
4632 err = e1000e_setup_rx_resources(adapter->rx_ring);
4633 if (err)
4634 goto err_setup_rx;
4635
4636 /* If AMT is enabled, let the firmware know that the network
4637 * interface is now open and reset the part to a known state.
4638 */
4639 if (adapter->flags & FLAG_HAS_AMT) {
4640 e1000e_get_hw_control(adapter);
4641 e1000e_reset(adapter);
4642 }
4643
4644 e1000e_power_up_phy(adapter);
4645
4646 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4647 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4648 e1000_update_mng_vlan(adapter);
4649
4650 /* DMA latency requirement to workaround jumbo issue */
4651 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
4652
4653 /* before we allocate an interrupt, we must be ready to handle it.
4654 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4655 * as soon as we call pci_request_irq, so we have to setup our
4656 * clean_rx handler before we do so.
4657 */
4658 e1000_configure(adapter);
4659
4660 err = e1000_request_irq(adapter);
4661 if (err)
4662 goto err_req_irq;
4663
4664 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4665 * ignore e1000e MSI messages, which means we need to test our MSI
4666 * interrupt now
4667 */
4668 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4669 err = e1000_test_msi(adapter);
4670 if (err) {
4671 e_err("Interrupt allocation failed\n");
4672 goto err_req_irq;
4673 }
4674 }
4675
4676 /* From here on the code is the same as e1000e_up() */
4677 clear_bit(__E1000_DOWN, &adapter->state);
4678
4679 napi_enable(&adapter->napi);
4680
4681 e1000_irq_enable(adapter);
4682
4683 adapter->tx_hang_recheck = false;
4684
4685 hw->mac.get_link_status = true;
4686 pm_runtime_put(&pdev->dev);
4687
4688 e1000e_trigger_lsc(adapter);
4689
4690 return 0;
4691
4692err_req_irq:
4693 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4694 e1000e_release_hw_control(adapter);
4695 e1000_power_down_phy(adapter);
4696 e1000e_free_rx_resources(adapter->rx_ring);
4697err_setup_rx:
4698 e1000e_free_tx_resources(adapter->tx_ring);
4699err_setup_tx:
4700 e1000e_reset(adapter);
4701 pm_runtime_put_sync(&pdev->dev);
4702
4703 return err;
4704}
4705
4706/**
4707 * e1000e_close - Disables a network interface
4708 * @netdev: network interface device structure
4709 *
4710 * Returns 0, this is not allowed to fail
4711 *
4712 * The close entry point is called when an interface is de-activated
4713 * by the OS. The hardware is still under the drivers control, but
4714 * needs to be disabled. A global MAC reset is issued to stop the
4715 * hardware, and all transmit and receive resources are freed.
4716 **/
4717int e1000e_close(struct net_device *netdev)
4718{
4719 struct e1000_adapter *adapter = netdev_priv(netdev);
4720 struct pci_dev *pdev = adapter->pdev;
4721 int count = E1000_CHECK_RESET_COUNT;
4722
4723 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4724 usleep_range(10000, 11000);
4725
4726 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4727
4728 pm_runtime_get_sync(&pdev->dev);
4729
4730 if (netif_device_present(netdev)) {
4731 e1000e_down(adapter, true);
4732 e1000_free_irq(adapter);
4733
4734 /* Link status message must follow this format */
4735 netdev_info(netdev, "NIC Link is Down\n");
4736 }
4737
4738 napi_disable(&adapter->napi);
4739
4740 e1000e_free_tx_resources(adapter->tx_ring);
4741 e1000e_free_rx_resources(adapter->rx_ring);
4742
4743 /* kill manageability vlan ID if supported, but not if a vlan with
4744 * the same ID is registered on the host OS (let 8021q kill it)
4745 */
4746 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4747 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4748 adapter->mng_vlan_id);
4749
4750 /* If AMT is enabled, let the firmware know that the network
4751 * interface is now closed
4752 */
4753 if ((adapter->flags & FLAG_HAS_AMT) &&
4754 !test_bit(__E1000_TESTING, &adapter->state))
4755 e1000e_release_hw_control(adapter);
4756
4757 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4758
4759 pm_runtime_put_sync(&pdev->dev);
4760
4761 return 0;
4762}
4763
4764/**
4765 * e1000_set_mac - Change the Ethernet Address of the NIC
4766 * @netdev: network interface device structure
4767 * @p: pointer to an address structure
4768 *
4769 * Returns 0 on success, negative on failure
4770 **/
4771static int e1000_set_mac(struct net_device *netdev, void *p)
4772{
4773 struct e1000_adapter *adapter = netdev_priv(netdev);
4774 struct e1000_hw *hw = &adapter->hw;
4775 struct sockaddr *addr = p;
4776
4777 if (!is_valid_ether_addr(addr->sa_data))
4778 return -EADDRNOTAVAIL;
4779
4780 eth_hw_addr_set(netdev, addr->sa_data);
4781 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4782
4783 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4784
4785 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4786 /* activate the work around */
4787 e1000e_set_laa_state_82571(&adapter->hw, 1);
4788
4789 /* Hold a copy of the LAA in RAR[14] This is done so that
4790 * between the time RAR[0] gets clobbered and the time it
4791 * gets fixed (in e1000_watchdog), the actual LAA is in one
4792 * of the RARs and no incoming packets directed to this port
4793 * are dropped. Eventually the LAA will be in RAR[0] and
4794 * RAR[14]
4795 */
4796 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4797 adapter->hw.mac.rar_entry_count - 1);
4798 }
4799
4800 return 0;
4801}
4802
4803/**
4804 * e1000e_update_phy_task - work thread to update phy
4805 * @work: pointer to our work struct
4806 *
4807 * this worker thread exists because we must acquire a
4808 * semaphore to read the phy, which we could msleep while
4809 * waiting for it, and we can't msleep in a timer.
4810 **/
4811static void e1000e_update_phy_task(struct work_struct *work)
4812{
4813 struct e1000_adapter *adapter = container_of(work,
4814 struct e1000_adapter,
4815 update_phy_task);
4816 struct e1000_hw *hw = &adapter->hw;
4817
4818 if (test_bit(__E1000_DOWN, &adapter->state))
4819 return;
4820
4821 e1000_get_phy_info(hw);
4822
4823 /* Enable EEE on 82579 after link up */
4824 if (hw->phy.type >= e1000_phy_82579)
4825 e1000_set_eee_pchlan(hw);
4826}
4827
4828/**
4829 * e1000_update_phy_info - timre call-back to update PHY info
4830 * @t: pointer to timer_list containing private info adapter
4831 *
4832 * Need to wait a few seconds after link up to get diagnostic information from
4833 * the phy
4834 **/
4835static void e1000_update_phy_info(struct timer_list *t)
4836{
4837 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4838
4839 if (test_bit(__E1000_DOWN, &adapter->state))
4840 return;
4841
4842 schedule_work(&adapter->update_phy_task);
4843}
4844
4845/**
4846 * e1000e_update_phy_stats - Update the PHY statistics counters
4847 * @adapter: board private structure
4848 *
4849 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4850 **/
4851static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4852{
4853 struct e1000_hw *hw = &adapter->hw;
4854 s32 ret_val;
4855 u16 phy_data;
4856
4857 ret_val = hw->phy.ops.acquire(hw);
4858 if (ret_val)
4859 return;
4860
4861 /* A page set is expensive so check if already on desired page.
4862 * If not, set to the page with the PHY status registers.
4863 */
4864 hw->phy.addr = 1;
4865 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4866 &phy_data);
4867 if (ret_val)
4868 goto release;
4869 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4870 ret_val = hw->phy.ops.set_page(hw,
4871 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4872 if (ret_val)
4873 goto release;
4874 }
4875
4876 /* Single Collision Count */
4877 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4878 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4879 if (!ret_val)
4880 adapter->stats.scc += phy_data;
4881
4882 /* Excessive Collision Count */
4883 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4884 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4885 if (!ret_val)
4886 adapter->stats.ecol += phy_data;
4887
4888 /* Multiple Collision Count */
4889 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4890 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4891 if (!ret_val)
4892 adapter->stats.mcc += phy_data;
4893
4894 /* Late Collision Count */
4895 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4896 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4897 if (!ret_val)
4898 adapter->stats.latecol += phy_data;
4899
4900 /* Collision Count - also used for adaptive IFS */
4901 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4902 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4903 if (!ret_val)
4904 hw->mac.collision_delta = phy_data;
4905
4906 /* Defer Count */
4907 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4908 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4909 if (!ret_val)
4910 adapter->stats.dc += phy_data;
4911
4912 /* Transmit with no CRS */
4913 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4914 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4915 if (!ret_val)
4916 adapter->stats.tncrs += phy_data;
4917
4918release:
4919 hw->phy.ops.release(hw);
4920}
4921
4922/**
4923 * e1000e_update_stats - Update the board statistics counters
4924 * @adapter: board private structure
4925 **/
4926static void e1000e_update_stats(struct e1000_adapter *adapter)
4927{
4928 struct net_device *netdev = adapter->netdev;
4929 struct e1000_hw *hw = &adapter->hw;
4930 struct pci_dev *pdev = adapter->pdev;
4931
4932 /* Prevent stats update while adapter is being reset, or if the pci
4933 * connection is down.
4934 */
4935 if (adapter->link_speed == 0)
4936 return;
4937 if (pci_channel_offline(pdev))
4938 return;
4939
4940 adapter->stats.crcerrs += er32(CRCERRS);
4941 adapter->stats.gprc += er32(GPRC);
4942 adapter->stats.gorc += er32(GORCL);
4943 er32(GORCH); /* Clear gorc */
4944 adapter->stats.bprc += er32(BPRC);
4945 adapter->stats.mprc += er32(MPRC);
4946 adapter->stats.roc += er32(ROC);
4947
4948 adapter->stats.mpc += er32(MPC);
4949
4950 /* Half-duplex statistics */
4951 if (adapter->link_duplex == HALF_DUPLEX) {
4952 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4953 e1000e_update_phy_stats(adapter);
4954 } else {
4955 adapter->stats.scc += er32(SCC);
4956 adapter->stats.ecol += er32(ECOL);
4957 adapter->stats.mcc += er32(MCC);
4958 adapter->stats.latecol += er32(LATECOL);
4959 adapter->stats.dc += er32(DC);
4960
4961 hw->mac.collision_delta = er32(COLC);
4962
4963 if ((hw->mac.type != e1000_82574) &&
4964 (hw->mac.type != e1000_82583))
4965 adapter->stats.tncrs += er32(TNCRS);
4966 }
4967 adapter->stats.colc += hw->mac.collision_delta;
4968 }
4969
4970 adapter->stats.xonrxc += er32(XONRXC);
4971 adapter->stats.xontxc += er32(XONTXC);
4972 adapter->stats.xoffrxc += er32(XOFFRXC);
4973 adapter->stats.xofftxc += er32(XOFFTXC);
4974 adapter->stats.gptc += er32(GPTC);
4975 adapter->stats.gotc += er32(GOTCL);
4976 er32(GOTCH); /* Clear gotc */
4977 adapter->stats.rnbc += er32(RNBC);
4978 adapter->stats.ruc += er32(RUC);
4979
4980 adapter->stats.mptc += er32(MPTC);
4981 adapter->stats.bptc += er32(BPTC);
4982
4983 /* used for adaptive IFS */
4984
4985 hw->mac.tx_packet_delta = er32(TPT);
4986 adapter->stats.tpt += hw->mac.tx_packet_delta;
4987
4988 adapter->stats.algnerrc += er32(ALGNERRC);
4989 adapter->stats.rxerrc += er32(RXERRC);
4990 adapter->stats.cexterr += er32(CEXTERR);
4991 adapter->stats.tsctc += er32(TSCTC);
4992 adapter->stats.tsctfc += er32(TSCTFC);
4993
4994 /* Fill out the OS statistics structure */
4995 netdev->stats.multicast = adapter->stats.mprc;
4996 netdev->stats.collisions = adapter->stats.colc;
4997
4998 /* Rx Errors */
4999
5000 /* RLEC on some newer hardware can be incorrect so build
5001 * our own version based on RUC and ROC
5002 */
5003 netdev->stats.rx_errors = adapter->stats.rxerrc +
5004 adapter->stats.crcerrs + adapter->stats.algnerrc +
5005 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5006 netdev->stats.rx_length_errors = adapter->stats.ruc +
5007 adapter->stats.roc;
5008 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5009 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5010 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5011
5012 /* Tx Errors */
5013 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5014 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5015 netdev->stats.tx_window_errors = adapter->stats.latecol;
5016 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5017
5018 /* Tx Dropped needs to be maintained elsewhere */
5019
5020 /* Management Stats */
5021 adapter->stats.mgptc += er32(MGTPTC);
5022 adapter->stats.mgprc += er32(MGTPRC);
5023 adapter->stats.mgpdc += er32(MGTPDC);
5024
5025 /* Correctable ECC Errors */
5026 if (hw->mac.type >= e1000_pch_lpt) {
5027 u32 pbeccsts = er32(PBECCSTS);
5028
5029 adapter->corr_errors +=
5030 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5031 adapter->uncorr_errors +=
5032 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
5033 }
5034}
5035
5036/**
5037 * e1000_phy_read_status - Update the PHY register status snapshot
5038 * @adapter: board private structure
5039 **/
5040static void e1000_phy_read_status(struct e1000_adapter *adapter)
5041{
5042 struct e1000_hw *hw = &adapter->hw;
5043 struct e1000_phy_regs *phy = &adapter->phy_regs;
5044
5045 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5046 (er32(STATUS) & E1000_STATUS_LU) &&
5047 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5048 int ret_val;
5049
5050 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5051 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5052 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5053 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5054 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5055 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5056 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5057 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5058 if (ret_val)
5059 e_warn("Error reading PHY register\n");
5060 } else {
5061 /* Do not read PHY registers if link is not up
5062 * Set values to typical power-on defaults
5063 */
5064 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5065 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5066 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5067 BMSR_ERCAP);
5068 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5069 ADVERTISE_ALL | ADVERTISE_CSMA);
5070 phy->lpa = 0;
5071 phy->expansion = EXPANSION_ENABLENPAGE;
5072 phy->ctrl1000 = ADVERTISE_1000FULL;
5073 phy->stat1000 = 0;
5074 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5075 }
5076}
5077
5078static void e1000_print_link_info(struct e1000_adapter *adapter)
5079{
5080 struct e1000_hw *hw = &adapter->hw;
5081 u32 ctrl = er32(CTRL);
5082
5083 /* Link status message must follow this format for user tools */
5084 netdev_info(adapter->netdev,
5085 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5086 adapter->link_speed,
5087 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5088 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5089 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5090 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5091}
5092
5093static bool e1000e_has_link(struct e1000_adapter *adapter)
5094{
5095 struct e1000_hw *hw = &adapter->hw;
5096 bool link_active = false;
5097 s32 ret_val = 0;
5098
5099 /* get_link_status is set on LSC (link status) interrupt or
5100 * Rx sequence error interrupt. get_link_status will stay
5101 * true until the check_for_link establishes link
5102 * for copper adapters ONLY
5103 */
5104 switch (hw->phy.media_type) {
5105 case e1000_media_type_copper:
5106 if (hw->mac.get_link_status) {
5107 ret_val = hw->mac.ops.check_for_link(hw);
5108 link_active = !hw->mac.get_link_status;
5109 } else {
5110 link_active = true;
5111 }
5112 break;
5113 case e1000_media_type_fiber:
5114 ret_val = hw->mac.ops.check_for_link(hw);
5115 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5116 break;
5117 case e1000_media_type_internal_serdes:
5118 ret_val = hw->mac.ops.check_for_link(hw);
5119 link_active = hw->mac.serdes_has_link;
5120 break;
5121 default:
5122 case e1000_media_type_unknown:
5123 break;
5124 }
5125
5126 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5127 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5128 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5129 e_info("Gigabit has been disabled, downgrading speed\n");
5130 }
5131
5132 return link_active;
5133}
5134
5135static void e1000e_enable_receives(struct e1000_adapter *adapter)
5136{
5137 /* make sure the receive unit is started */
5138 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5139 (adapter->flags & FLAG_RESTART_NOW)) {
5140 struct e1000_hw *hw = &adapter->hw;
5141 u32 rctl = er32(RCTL);
5142
5143 ew32(RCTL, rctl | E1000_RCTL_EN);
5144 adapter->flags &= ~FLAG_RESTART_NOW;
5145 }
5146}
5147
5148static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5149{
5150 struct e1000_hw *hw = &adapter->hw;
5151
5152 /* With 82574 controllers, PHY needs to be checked periodically
5153 * for hung state and reset, if two calls return true
5154 */
5155 if (e1000_check_phy_82574(hw))
5156 adapter->phy_hang_count++;
5157 else
5158 adapter->phy_hang_count = 0;
5159
5160 if (adapter->phy_hang_count > 1) {
5161 adapter->phy_hang_count = 0;
5162 e_dbg("PHY appears hung - resetting\n");
5163 schedule_work(&adapter->reset_task);
5164 }
5165}
5166
5167/**
5168 * e1000_watchdog - Timer Call-back
5169 * @t: pointer to timer_list containing private info adapter
5170 **/
5171static void e1000_watchdog(struct timer_list *t)
5172{
5173 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5174
5175 /* Do the rest outside of interrupt context */
5176 schedule_work(&adapter->watchdog_task);
5177
5178 /* TODO: make this use queue_delayed_work() */
5179}
5180
5181static void e1000_watchdog_task(struct work_struct *work)
5182{
5183 struct e1000_adapter *adapter = container_of(work,
5184 struct e1000_adapter,
5185 watchdog_task);
5186 struct net_device *netdev = adapter->netdev;
5187 struct e1000_mac_info *mac = &adapter->hw.mac;
5188 struct e1000_phy_info *phy = &adapter->hw.phy;
5189 struct e1000_ring *tx_ring = adapter->tx_ring;
5190 u32 dmoff_exit_timeout = 100, tries = 0;
5191 struct e1000_hw *hw = &adapter->hw;
5192 u32 link, tctl, pcim_state;
5193
5194 if (test_bit(__E1000_DOWN, &adapter->state))
5195 return;
5196
5197 link = e1000e_has_link(adapter);
5198 if ((netif_carrier_ok(netdev)) && link) {
5199 /* Cancel scheduled suspend requests. */
5200 pm_runtime_resume(netdev->dev.parent);
5201
5202 e1000e_enable_receives(adapter);
5203 goto link_up;
5204 }
5205
5206 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5207 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5208 e1000_update_mng_vlan(adapter);
5209
5210 if (link) {
5211 if (!netif_carrier_ok(netdev)) {
5212 bool txb2b = true;
5213
5214 /* Cancel scheduled suspend requests. */
5215 pm_runtime_resume(netdev->dev.parent);
5216
5217 /* Checking if MAC is in DMoff state*/
5218 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
5219 pcim_state = er32(STATUS);
5220 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5221 if (tries++ == dmoff_exit_timeout) {
5222 e_dbg("Error in exiting dmoff\n");
5223 break;
5224 }
5225 usleep_range(10000, 20000);
5226 pcim_state = er32(STATUS);
5227
5228 /* Checking if MAC exited DMoff state */
5229 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5230 e1000_phy_hw_reset(&adapter->hw);
5231 }
5232 }
5233
5234 /* update snapshot of PHY registers on LSC */
5235 e1000_phy_read_status(adapter);
5236 mac->ops.get_link_up_info(&adapter->hw,
5237 &adapter->link_speed,
5238 &adapter->link_duplex);
5239 e1000_print_link_info(adapter);
5240
5241 /* check if SmartSpeed worked */
5242 e1000e_check_downshift(hw);
5243 if (phy->speed_downgraded)
5244 netdev_warn(netdev,
5245 "Link Speed was downgraded by SmartSpeed\n");
5246
5247 /* On supported PHYs, check for duplex mismatch only
5248 * if link has autonegotiated at 10/100 half
5249 */
5250 if ((hw->phy.type == e1000_phy_igp_3 ||
5251 hw->phy.type == e1000_phy_bm) &&
5252 hw->mac.autoneg &&
5253 (adapter->link_speed == SPEED_10 ||
5254 adapter->link_speed == SPEED_100) &&
5255 (adapter->link_duplex == HALF_DUPLEX)) {
5256 u16 autoneg_exp;
5257
5258 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5259
5260 if (!(autoneg_exp & EXPANSION_NWAY))
5261 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5262 }
5263
5264 /* adjust timeout factor according to speed/duplex */
5265 adapter->tx_timeout_factor = 1;
5266 switch (adapter->link_speed) {
5267 case SPEED_10:
5268 txb2b = false;
5269 adapter->tx_timeout_factor = 16;
5270 break;
5271 case SPEED_100:
5272 txb2b = false;
5273 adapter->tx_timeout_factor = 10;
5274 break;
5275 }
5276
5277 /* workaround: re-program speed mode bit after
5278 * link-up event
5279 */
5280 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5281 !txb2b) {
5282 u32 tarc0;
5283
5284 tarc0 = er32(TARC(0));
5285 tarc0 &= ~SPEED_MODE_BIT;
5286 ew32(TARC(0), tarc0);
5287 }
5288
5289 /* enable transmits in the hardware, need to do this
5290 * after setting TARC(0)
5291 */
5292 tctl = er32(TCTL);
5293 tctl |= E1000_TCTL_EN;
5294 ew32(TCTL, tctl);
5295
5296 /* Perform any post-link-up configuration before
5297 * reporting link up.
5298 */
5299 if (phy->ops.cfg_on_link_up)
5300 phy->ops.cfg_on_link_up(hw);
5301
5302 netif_wake_queue(netdev);
5303 netif_carrier_on(netdev);
5304
5305 if (!test_bit(__E1000_DOWN, &adapter->state))
5306 mod_timer(&adapter->phy_info_timer,
5307 round_jiffies(jiffies + 2 * HZ));
5308 }
5309 } else {
5310 if (netif_carrier_ok(netdev)) {
5311 adapter->link_speed = 0;
5312 adapter->link_duplex = 0;
5313 /* Link status message must follow this format */
5314 netdev_info(netdev, "NIC Link is Down\n");
5315 netif_carrier_off(netdev);
5316 netif_stop_queue(netdev);
5317 if (!test_bit(__E1000_DOWN, &adapter->state))
5318 mod_timer(&adapter->phy_info_timer,
5319 round_jiffies(jiffies + 2 * HZ));
5320
5321 /* 8000ES2LAN requires a Rx packet buffer work-around
5322 * on link down event; reset the controller to flush
5323 * the Rx packet buffer.
5324 */
5325 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5326 adapter->flags |= FLAG_RESTART_NOW;
5327 else
5328 pm_schedule_suspend(netdev->dev.parent,
5329 LINK_TIMEOUT);
5330 }
5331 }
5332
5333link_up:
5334 spin_lock(&adapter->stats64_lock);
5335 e1000e_update_stats(adapter);
5336
5337 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5338 adapter->tpt_old = adapter->stats.tpt;
5339 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5340 adapter->colc_old = adapter->stats.colc;
5341
5342 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5343 adapter->gorc_old = adapter->stats.gorc;
5344 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5345 adapter->gotc_old = adapter->stats.gotc;
5346 spin_unlock(&adapter->stats64_lock);
5347
5348 /* If the link is lost the controller stops DMA, but
5349 * if there is queued Tx work it cannot be done. So
5350 * reset the controller to flush the Tx packet buffers.
5351 */
5352 if (!netif_carrier_ok(netdev) &&
5353 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5354 adapter->flags |= FLAG_RESTART_NOW;
5355
5356 /* If reset is necessary, do it outside of interrupt context. */
5357 if (adapter->flags & FLAG_RESTART_NOW) {
5358 schedule_work(&adapter->reset_task);
5359 /* return immediately since reset is imminent */
5360 return;
5361 }
5362
5363 e1000e_update_adaptive(&adapter->hw);
5364
5365 /* Simple mode for Interrupt Throttle Rate (ITR) */
5366 if (adapter->itr_setting == 4) {
5367 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5368 * Total asymmetrical Tx or Rx gets ITR=8000;
5369 * everyone else is between 2000-8000.
5370 */
5371 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5372 u32 dif = (adapter->gotc > adapter->gorc ?
5373 adapter->gotc - adapter->gorc :
5374 adapter->gorc - adapter->gotc) / 10000;
5375 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5376
5377 e1000e_write_itr(adapter, itr);
5378 }
5379
5380 /* Cause software interrupt to ensure Rx ring is cleaned */
5381 if (adapter->msix_entries)
5382 ew32(ICS, adapter->rx_ring->ims_val);
5383 else
5384 ew32(ICS, E1000_ICS_RXDMT0);
5385
5386 /* flush pending descriptors to memory before detecting Tx hang */
5387 e1000e_flush_descriptors(adapter);
5388
5389 /* Force detection of hung controller every watchdog period */
5390 adapter->detect_tx_hung = true;
5391
5392 /* With 82571 controllers, LAA may be overwritten due to controller
5393 * reset from the other port. Set the appropriate LAA in RAR[0]
5394 */
5395 if (e1000e_get_laa_state_82571(hw))
5396 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5397
5398 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5399 e1000e_check_82574_phy_workaround(adapter);
5400
5401 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5402 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5403 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5404 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5405 er32(RXSTMPH);
5406 adapter->rx_hwtstamp_cleared++;
5407 } else {
5408 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5409 }
5410 }
5411
5412 /* Reset the timer */
5413 if (!test_bit(__E1000_DOWN, &adapter->state))
5414 mod_timer(&adapter->watchdog_timer,
5415 round_jiffies(jiffies + 2 * HZ));
5416}
5417
5418#define E1000_TX_FLAGS_CSUM 0x00000001
5419#define E1000_TX_FLAGS_VLAN 0x00000002
5420#define E1000_TX_FLAGS_TSO 0x00000004
5421#define E1000_TX_FLAGS_IPV4 0x00000008
5422#define E1000_TX_FLAGS_NO_FCS 0x00000010
5423#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5424#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5425#define E1000_TX_FLAGS_VLAN_SHIFT 16
5426
5427static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5428 __be16 protocol)
5429{
5430 struct e1000_context_desc *context_desc;
5431 struct e1000_buffer *buffer_info;
5432 unsigned int i;
5433 u32 cmd_length = 0;
5434 u16 ipcse = 0, mss;
5435 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5436 int err;
5437
5438 if (!skb_is_gso(skb))
5439 return 0;
5440
5441 err = skb_cow_head(skb, 0);
5442 if (err < 0)
5443 return err;
5444
5445 hdr_len = skb_tcp_all_headers(skb);
5446 mss = skb_shinfo(skb)->gso_size;
5447 if (protocol == htons(ETH_P_IP)) {
5448 struct iphdr *iph = ip_hdr(skb);
5449 iph->tot_len = 0;
5450 iph->check = 0;
5451 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5452 0, IPPROTO_TCP, 0);
5453 cmd_length = E1000_TXD_CMD_IP;
5454 ipcse = skb_transport_offset(skb) - 1;
5455 } else if (skb_is_gso_v6(skb)) {
5456 tcp_v6_gso_csum_prep(skb);
5457 ipcse = 0;
5458 }
5459 ipcss = skb_network_offset(skb);
5460 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5461 tucss = skb_transport_offset(skb);
5462 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5463
5464 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5465 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5466
5467 i = tx_ring->next_to_use;
5468 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5469 buffer_info = &tx_ring->buffer_info[i];
5470
5471 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5472 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5473 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5474 context_desc->upper_setup.tcp_fields.tucss = tucss;
5475 context_desc->upper_setup.tcp_fields.tucso = tucso;
5476 context_desc->upper_setup.tcp_fields.tucse = 0;
5477 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5478 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5479 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5480
5481 buffer_info->time_stamp = jiffies;
5482 buffer_info->next_to_watch = i;
5483
5484 i++;
5485 if (i == tx_ring->count)
5486 i = 0;
5487 tx_ring->next_to_use = i;
5488
5489 return 1;
5490}
5491
5492static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5493 __be16 protocol)
5494{
5495 struct e1000_adapter *adapter = tx_ring->adapter;
5496 struct e1000_context_desc *context_desc;
5497 struct e1000_buffer *buffer_info;
5498 unsigned int i;
5499 u8 css;
5500 u32 cmd_len = E1000_TXD_CMD_DEXT;
5501
5502 if (skb->ip_summed != CHECKSUM_PARTIAL)
5503 return false;
5504
5505 switch (protocol) {
5506 case cpu_to_be16(ETH_P_IP):
5507 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5508 cmd_len |= E1000_TXD_CMD_TCP;
5509 break;
5510 case cpu_to_be16(ETH_P_IPV6):
5511 /* XXX not handling all IPV6 headers */
5512 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5513 cmd_len |= E1000_TXD_CMD_TCP;
5514 break;
5515 default:
5516 if (unlikely(net_ratelimit()))
5517 e_warn("checksum_partial proto=%x!\n",
5518 be16_to_cpu(protocol));
5519 break;
5520 }
5521
5522 css = skb_checksum_start_offset(skb);
5523
5524 i = tx_ring->next_to_use;
5525 buffer_info = &tx_ring->buffer_info[i];
5526 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5527
5528 context_desc->lower_setup.ip_config = 0;
5529 context_desc->upper_setup.tcp_fields.tucss = css;
5530 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5531 context_desc->upper_setup.tcp_fields.tucse = 0;
5532 context_desc->tcp_seg_setup.data = 0;
5533 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5534
5535 buffer_info->time_stamp = jiffies;
5536 buffer_info->next_to_watch = i;
5537
5538 i++;
5539 if (i == tx_ring->count)
5540 i = 0;
5541 tx_ring->next_to_use = i;
5542
5543 return true;
5544}
5545
5546static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5547 unsigned int first, unsigned int max_per_txd,
5548 unsigned int nr_frags)
5549{
5550 struct e1000_adapter *adapter = tx_ring->adapter;
5551 struct pci_dev *pdev = adapter->pdev;
5552 struct e1000_buffer *buffer_info;
5553 unsigned int len = skb_headlen(skb);
5554 unsigned int offset = 0, size, count = 0, i;
5555 unsigned int f, bytecount, segs;
5556
5557 i = tx_ring->next_to_use;
5558
5559 while (len) {
5560 buffer_info = &tx_ring->buffer_info[i];
5561 size = min(len, max_per_txd);
5562
5563 buffer_info->length = size;
5564 buffer_info->time_stamp = jiffies;
5565 buffer_info->next_to_watch = i;
5566 buffer_info->dma = dma_map_single(&pdev->dev,
5567 skb->data + offset,
5568 size, DMA_TO_DEVICE);
5569 buffer_info->mapped_as_page = false;
5570 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5571 goto dma_error;
5572
5573 len -= size;
5574 offset += size;
5575 count++;
5576
5577 if (len) {
5578 i++;
5579 if (i == tx_ring->count)
5580 i = 0;
5581 }
5582 }
5583
5584 for (f = 0; f < nr_frags; f++) {
5585 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5586
5587 len = skb_frag_size(frag);
5588 offset = 0;
5589
5590 while (len) {
5591 i++;
5592 if (i == tx_ring->count)
5593 i = 0;
5594
5595 buffer_info = &tx_ring->buffer_info[i];
5596 size = min(len, max_per_txd);
5597
5598 buffer_info->length = size;
5599 buffer_info->time_stamp = jiffies;
5600 buffer_info->next_to_watch = i;
5601 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5602 offset, size,
5603 DMA_TO_DEVICE);
5604 buffer_info->mapped_as_page = true;
5605 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5606 goto dma_error;
5607
5608 len -= size;
5609 offset += size;
5610 count++;
5611 }
5612 }
5613
5614 segs = skb_shinfo(skb)->gso_segs ? : 1;
5615 /* multiply data chunks by size of headers */
5616 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5617
5618 tx_ring->buffer_info[i].skb = skb;
5619 tx_ring->buffer_info[i].segs = segs;
5620 tx_ring->buffer_info[i].bytecount = bytecount;
5621 tx_ring->buffer_info[first].next_to_watch = i;
5622
5623 return count;
5624
5625dma_error:
5626 dev_err(&pdev->dev, "Tx DMA map failed\n");
5627 buffer_info->dma = 0;
5628 if (count)
5629 count--;
5630
5631 while (count--) {
5632 if (i == 0)
5633 i += tx_ring->count;
5634 i--;
5635 buffer_info = &tx_ring->buffer_info[i];
5636 e1000_put_txbuf(tx_ring, buffer_info, true);
5637 }
5638
5639 return 0;
5640}
5641
5642static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5643{
5644 struct e1000_adapter *adapter = tx_ring->adapter;
5645 struct e1000_tx_desc *tx_desc = NULL;
5646 struct e1000_buffer *buffer_info;
5647 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5648 unsigned int i;
5649
5650 if (tx_flags & E1000_TX_FLAGS_TSO) {
5651 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5652 E1000_TXD_CMD_TSE;
5653 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5654
5655 if (tx_flags & E1000_TX_FLAGS_IPV4)
5656 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5657 }
5658
5659 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5660 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5661 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5662 }
5663
5664 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5665 txd_lower |= E1000_TXD_CMD_VLE;
5666 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5667 }
5668
5669 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5670 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5671
5672 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5673 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5674 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5675 }
5676
5677 i = tx_ring->next_to_use;
5678
5679 do {
5680 buffer_info = &tx_ring->buffer_info[i];
5681 tx_desc = E1000_TX_DESC(*tx_ring, i);
5682 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5683 tx_desc->lower.data = cpu_to_le32(txd_lower |
5684 buffer_info->length);
5685 tx_desc->upper.data = cpu_to_le32(txd_upper);
5686
5687 i++;
5688 if (i == tx_ring->count)
5689 i = 0;
5690 } while (--count > 0);
5691
5692 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5693
5694 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5695 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5696 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5697
5698 /* Force memory writes to complete before letting h/w
5699 * know there are new descriptors to fetch. (Only
5700 * applicable for weak-ordered memory model archs,
5701 * such as IA-64).
5702 */
5703 wmb();
5704
5705 tx_ring->next_to_use = i;
5706}
5707
5708#define MINIMUM_DHCP_PACKET_SIZE 282
5709static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5710 struct sk_buff *skb)
5711{
5712 struct e1000_hw *hw = &adapter->hw;
5713 u16 length, offset;
5714
5715 if (skb_vlan_tag_present(skb) &&
5716 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5717 (adapter->hw.mng_cookie.status &
5718 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5719 return 0;
5720
5721 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5722 return 0;
5723
5724 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5725 return 0;
5726
5727 {
5728 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5729 struct udphdr *udp;
5730
5731 if (ip->protocol != IPPROTO_UDP)
5732 return 0;
5733
5734 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5735 if (ntohs(udp->dest) != 67)
5736 return 0;
5737
5738 offset = (u8 *)udp + 8 - skb->data;
5739 length = skb->len - offset;
5740 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5741 }
5742
5743 return 0;
5744}
5745
5746static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5747{
5748 struct e1000_adapter *adapter = tx_ring->adapter;
5749
5750 netif_stop_queue(adapter->netdev);
5751 /* Herbert's original patch had:
5752 * smp_mb__after_netif_stop_queue();
5753 * but since that doesn't exist yet, just open code it.
5754 */
5755 smp_mb();
5756
5757 /* We need to check again in a case another CPU has just
5758 * made room available.
5759 */
5760 if (e1000_desc_unused(tx_ring) < size)
5761 return -EBUSY;
5762
5763 /* A reprieve! */
5764 netif_start_queue(adapter->netdev);
5765 ++adapter->restart_queue;
5766 return 0;
5767}
5768
5769static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5770{
5771 BUG_ON(size > tx_ring->count);
5772
5773 if (e1000_desc_unused(tx_ring) >= size)
5774 return 0;
5775 return __e1000_maybe_stop_tx(tx_ring, size);
5776}
5777
5778static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5779 struct net_device *netdev)
5780{
5781 struct e1000_adapter *adapter = netdev_priv(netdev);
5782 struct e1000_ring *tx_ring = adapter->tx_ring;
5783 unsigned int first;
5784 unsigned int tx_flags = 0;
5785 unsigned int len = skb_headlen(skb);
5786 unsigned int nr_frags;
5787 unsigned int mss;
5788 int count = 0;
5789 int tso;
5790 unsigned int f;
5791 __be16 protocol = vlan_get_protocol(skb);
5792
5793 if (test_bit(__E1000_DOWN, &adapter->state)) {
5794 dev_kfree_skb_any(skb);
5795 return NETDEV_TX_OK;
5796 }
5797
5798 if (skb->len <= 0) {
5799 dev_kfree_skb_any(skb);
5800 return NETDEV_TX_OK;
5801 }
5802
5803 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5804 * pad skb in order to meet this minimum size requirement
5805 */
5806 if (skb_put_padto(skb, 17))
5807 return NETDEV_TX_OK;
5808
5809 mss = skb_shinfo(skb)->gso_size;
5810 if (mss) {
5811 u8 hdr_len;
5812
5813 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5814 * points to just header, pull a few bytes of payload from
5815 * frags into skb->data
5816 */
5817 hdr_len = skb_tcp_all_headers(skb);
5818 /* we do this workaround for ES2LAN, but it is un-necessary,
5819 * avoiding it could save a lot of cycles
5820 */
5821 if (skb->data_len && (hdr_len == len)) {
5822 unsigned int pull_size;
5823
5824 pull_size = min_t(unsigned int, 4, skb->data_len);
5825 if (!__pskb_pull_tail(skb, pull_size)) {
5826 e_err("__pskb_pull_tail failed.\n");
5827 dev_kfree_skb_any(skb);
5828 return NETDEV_TX_OK;
5829 }
5830 len = skb_headlen(skb);
5831 }
5832 }
5833
5834 /* reserve a descriptor for the offload context */
5835 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5836 count++;
5837 count++;
5838
5839 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5840
5841 nr_frags = skb_shinfo(skb)->nr_frags;
5842 for (f = 0; f < nr_frags; f++)
5843 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5844 adapter->tx_fifo_limit);
5845
5846 if (adapter->hw.mac.tx_pkt_filtering)
5847 e1000_transfer_dhcp_info(adapter, skb);
5848
5849 /* need: count + 2 desc gap to keep tail from touching
5850 * head, otherwise try next time
5851 */
5852 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5853 return NETDEV_TX_BUSY;
5854
5855 if (skb_vlan_tag_present(skb)) {
5856 tx_flags |= E1000_TX_FLAGS_VLAN;
5857 tx_flags |= (skb_vlan_tag_get(skb) <<
5858 E1000_TX_FLAGS_VLAN_SHIFT);
5859 }
5860
5861 first = tx_ring->next_to_use;
5862
5863 tso = e1000_tso(tx_ring, skb, protocol);
5864 if (tso < 0) {
5865 dev_kfree_skb_any(skb);
5866 return NETDEV_TX_OK;
5867 }
5868
5869 if (tso)
5870 tx_flags |= E1000_TX_FLAGS_TSO;
5871 else if (e1000_tx_csum(tx_ring, skb, protocol))
5872 tx_flags |= E1000_TX_FLAGS_CSUM;
5873
5874 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5875 * 82571 hardware supports TSO capabilities for IPv6 as well...
5876 * no longer assume, we must.
5877 */
5878 if (protocol == htons(ETH_P_IP))
5879 tx_flags |= E1000_TX_FLAGS_IPV4;
5880
5881 if (unlikely(skb->no_fcs))
5882 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5883
5884 /* if count is 0 then mapping error has occurred */
5885 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5886 nr_frags);
5887 if (count) {
5888 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5889 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5890 if (!adapter->tx_hwtstamp_skb) {
5891 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5892 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5893 adapter->tx_hwtstamp_skb = skb_get(skb);
5894 adapter->tx_hwtstamp_start = jiffies;
5895 schedule_work(&adapter->tx_hwtstamp_work);
5896 } else {
5897 adapter->tx_hwtstamp_skipped++;
5898 }
5899 }
5900
5901 skb_tx_timestamp(skb);
5902
5903 netdev_sent_queue(netdev, skb->len);
5904 e1000_tx_queue(tx_ring, tx_flags, count);
5905 /* Make sure there is space in the ring for the next send. */
5906 e1000_maybe_stop_tx(tx_ring,
5907 ((MAX_SKB_FRAGS + 1) *
5908 DIV_ROUND_UP(PAGE_SIZE,
5909 adapter->tx_fifo_limit) + 4));
5910
5911 if (!netdev_xmit_more() ||
5912 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5913 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5914 e1000e_update_tdt_wa(tx_ring,
5915 tx_ring->next_to_use);
5916 else
5917 writel(tx_ring->next_to_use, tx_ring->tail);
5918 }
5919 } else {
5920 dev_kfree_skb_any(skb);
5921 tx_ring->buffer_info[first].time_stamp = 0;
5922 tx_ring->next_to_use = first;
5923 }
5924
5925 return NETDEV_TX_OK;
5926}
5927
5928/**
5929 * e1000_tx_timeout - Respond to a Tx Hang
5930 * @netdev: network interface device structure
5931 * @txqueue: index of the hung queue (unused)
5932 **/
5933static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
5934{
5935 struct e1000_adapter *adapter = netdev_priv(netdev);
5936
5937 /* Do the reset outside of interrupt context */
5938 adapter->tx_timeout_count++;
5939 schedule_work(&adapter->reset_task);
5940}
5941
5942static void e1000_reset_task(struct work_struct *work)
5943{
5944 struct e1000_adapter *adapter;
5945 adapter = container_of(work, struct e1000_adapter, reset_task);
5946
5947 rtnl_lock();
5948 /* don't run the task if already down */
5949 if (test_bit(__E1000_DOWN, &adapter->state)) {
5950 rtnl_unlock();
5951 return;
5952 }
5953
5954 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5955 e1000e_dump(adapter);
5956 e_err("Reset adapter unexpectedly\n");
5957 }
5958 e1000e_reinit_locked(adapter);
5959 rtnl_unlock();
5960}
5961
5962/**
5963 * e1000e_get_stats64 - Get System Network Statistics
5964 * @netdev: network interface device structure
5965 * @stats: rtnl_link_stats64 pointer
5966 *
5967 * Returns the address of the device statistics structure.
5968 **/
5969void e1000e_get_stats64(struct net_device *netdev,
5970 struct rtnl_link_stats64 *stats)
5971{
5972 struct e1000_adapter *adapter = netdev_priv(netdev);
5973
5974 spin_lock(&adapter->stats64_lock);
5975 e1000e_update_stats(adapter);
5976 /* Fill out the OS statistics structure */
5977 stats->rx_bytes = adapter->stats.gorc;
5978 stats->rx_packets = adapter->stats.gprc;
5979 stats->tx_bytes = adapter->stats.gotc;
5980 stats->tx_packets = adapter->stats.gptc;
5981 stats->multicast = adapter->stats.mprc;
5982 stats->collisions = adapter->stats.colc;
5983
5984 /* Rx Errors */
5985
5986 /* RLEC on some newer hardware can be incorrect so build
5987 * our own version based on RUC and ROC
5988 */
5989 stats->rx_errors = adapter->stats.rxerrc +
5990 adapter->stats.crcerrs + adapter->stats.algnerrc +
5991 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5992 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
5993 stats->rx_crc_errors = adapter->stats.crcerrs;
5994 stats->rx_frame_errors = adapter->stats.algnerrc;
5995 stats->rx_missed_errors = adapter->stats.mpc;
5996
5997 /* Tx Errors */
5998 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5999 stats->tx_aborted_errors = adapter->stats.ecol;
6000 stats->tx_window_errors = adapter->stats.latecol;
6001 stats->tx_carrier_errors = adapter->stats.tncrs;
6002
6003 /* Tx Dropped needs to be maintained elsewhere */
6004
6005 spin_unlock(&adapter->stats64_lock);
6006}
6007
6008/**
6009 * e1000_change_mtu - Change the Maximum Transfer Unit
6010 * @netdev: network interface device structure
6011 * @new_mtu: new value for maximum frame size
6012 *
6013 * Returns 0 on success, negative on failure
6014 **/
6015static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6016{
6017 struct e1000_adapter *adapter = netdev_priv(netdev);
6018 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6019
6020 /* Jumbo frame support */
6021 if ((new_mtu > ETH_DATA_LEN) &&
6022 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6023 e_err("Jumbo Frames not supported.\n");
6024 return -EINVAL;
6025 }
6026
6027 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6028 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6029 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6030 (new_mtu > ETH_DATA_LEN)) {
6031 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6032 return -EINVAL;
6033 }
6034
6035 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6036 usleep_range(1000, 1100);
6037 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6038 adapter->max_frame_size = max_frame;
6039 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6040 netdev->mtu, new_mtu);
6041 netdev->mtu = new_mtu;
6042
6043 pm_runtime_get_sync(netdev->dev.parent);
6044
6045 if (netif_running(netdev))
6046 e1000e_down(adapter, true);
6047
6048 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6049 * means we reserve 2 more, this pushes us to allocate from the next
6050 * larger slab size.
6051 * i.e. RXBUFFER_2048 --> size-4096 slab
6052 * However with the new *_jumbo_rx* routines, jumbo receives will use
6053 * fragmented skbs
6054 */
6055
6056 if (max_frame <= 2048)
6057 adapter->rx_buffer_len = 2048;
6058 else
6059 adapter->rx_buffer_len = 4096;
6060
6061 /* adjust allocation if LPE protects us, and we aren't using SBP */
6062 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6063 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6064
6065 if (netif_running(netdev))
6066 e1000e_up(adapter);
6067 else
6068 e1000e_reset(adapter);
6069
6070 pm_runtime_put_sync(netdev->dev.parent);
6071
6072 clear_bit(__E1000_RESETTING, &adapter->state);
6073
6074 return 0;
6075}
6076
6077static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6078 int cmd)
6079{
6080 struct e1000_adapter *adapter = netdev_priv(netdev);
6081 struct mii_ioctl_data *data = if_mii(ifr);
6082
6083 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6084 return -EOPNOTSUPP;
6085
6086 switch (cmd) {
6087 case SIOCGMIIPHY:
6088 data->phy_id = adapter->hw.phy.addr;
6089 break;
6090 case SIOCGMIIREG:
6091 e1000_phy_read_status(adapter);
6092
6093 switch (data->reg_num & 0x1F) {
6094 case MII_BMCR:
6095 data->val_out = adapter->phy_regs.bmcr;
6096 break;
6097 case MII_BMSR:
6098 data->val_out = adapter->phy_regs.bmsr;
6099 break;
6100 case MII_PHYSID1:
6101 data->val_out = (adapter->hw.phy.id >> 16);
6102 break;
6103 case MII_PHYSID2:
6104 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6105 break;
6106 case MII_ADVERTISE:
6107 data->val_out = adapter->phy_regs.advertise;
6108 break;
6109 case MII_LPA:
6110 data->val_out = adapter->phy_regs.lpa;
6111 break;
6112 case MII_EXPANSION:
6113 data->val_out = adapter->phy_regs.expansion;
6114 break;
6115 case MII_CTRL1000:
6116 data->val_out = adapter->phy_regs.ctrl1000;
6117 break;
6118 case MII_STAT1000:
6119 data->val_out = adapter->phy_regs.stat1000;
6120 break;
6121 case MII_ESTATUS:
6122 data->val_out = adapter->phy_regs.estatus;
6123 break;
6124 default:
6125 return -EIO;
6126 }
6127 break;
6128 case SIOCSMIIREG:
6129 default:
6130 return -EOPNOTSUPP;
6131 }
6132 return 0;
6133}
6134
6135/**
6136 * e1000e_hwtstamp_set - control hardware time stamping
6137 * @netdev: network interface device structure
6138 * @ifr: interface request
6139 *
6140 * Outgoing time stamping can be enabled and disabled. Play nice and
6141 * disable it when requested, although it shouldn't cause any overhead
6142 * when no packet needs it. At most one packet in the queue may be
6143 * marked for time stamping, otherwise it would be impossible to tell
6144 * for sure to which packet the hardware time stamp belongs.
6145 *
6146 * Incoming time stamping has to be configured via the hardware filters.
6147 * Not all combinations are supported, in particular event type has to be
6148 * specified. Matching the kind of event packet is not supported, with the
6149 * exception of "all V2 events regardless of level 2 or 4".
6150 **/
6151static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6152{
6153 struct e1000_adapter *adapter = netdev_priv(netdev);
6154 struct hwtstamp_config config;
6155 int ret_val;
6156
6157 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6158 return -EFAULT;
6159
6160 ret_val = e1000e_config_hwtstamp(adapter, &config);
6161 if (ret_val)
6162 return ret_val;
6163
6164 switch (config.rx_filter) {
6165 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6166 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6167 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6168 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6169 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6170 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6171 /* With V2 type filters which specify a Sync or Delay Request,
6172 * Path Delay Request/Response messages are also time stamped
6173 * by hardware so notify the caller the requested packets plus
6174 * some others are time stamped.
6175 */
6176 config.rx_filter = HWTSTAMP_FILTER_SOME;
6177 break;
6178 default:
6179 break;
6180 }
6181
6182 return copy_to_user(ifr->ifr_data, &config,
6183 sizeof(config)) ? -EFAULT : 0;
6184}
6185
6186static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6187{
6188 struct e1000_adapter *adapter = netdev_priv(netdev);
6189
6190 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6191 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6192}
6193
6194static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6195{
6196 switch (cmd) {
6197 case SIOCGMIIPHY:
6198 case SIOCGMIIREG:
6199 case SIOCSMIIREG:
6200 return e1000_mii_ioctl(netdev, ifr, cmd);
6201 case SIOCSHWTSTAMP:
6202 return e1000e_hwtstamp_set(netdev, ifr);
6203 case SIOCGHWTSTAMP:
6204 return e1000e_hwtstamp_get(netdev, ifr);
6205 default:
6206 return -EOPNOTSUPP;
6207 }
6208}
6209
6210static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6211{
6212 struct e1000_hw *hw = &adapter->hw;
6213 u32 i, mac_reg, wuc;
6214 u16 phy_reg, wuc_enable;
6215 int retval;
6216
6217 /* copy MAC RARs to PHY RARs */
6218 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6219
6220 retval = hw->phy.ops.acquire(hw);
6221 if (retval) {
6222 e_err("Could not acquire PHY\n");
6223 return retval;
6224 }
6225
6226 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6227 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6228 if (retval)
6229 goto release;
6230
6231 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6232 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6233 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6234 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6235 (u16)(mac_reg & 0xFFFF));
6236 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6237 (u16)((mac_reg >> 16) & 0xFFFF));
6238 }
6239
6240 /* configure PHY Rx Control register */
6241 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6242 mac_reg = er32(RCTL);
6243 if (mac_reg & E1000_RCTL_UPE)
6244 phy_reg |= BM_RCTL_UPE;
6245 if (mac_reg & E1000_RCTL_MPE)
6246 phy_reg |= BM_RCTL_MPE;
6247 phy_reg &= ~(BM_RCTL_MO_MASK);
6248 if (mac_reg & E1000_RCTL_MO_3)
6249 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg)
6250 << BM_RCTL_MO_SHIFT);
6251 if (mac_reg & E1000_RCTL_BAM)
6252 phy_reg |= BM_RCTL_BAM;
6253 if (mac_reg & E1000_RCTL_PMCF)
6254 phy_reg |= BM_RCTL_PMCF;
6255 mac_reg = er32(CTRL);
6256 if (mac_reg & E1000_CTRL_RFCE)
6257 phy_reg |= BM_RCTL_RFCE;
6258 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6259
6260 wuc = E1000_WUC_PME_EN;
6261 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6262 wuc |= E1000_WUC_APME;
6263
6264 /* enable PHY wakeup in MAC register */
6265 ew32(WUFC, wufc);
6266 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6267 E1000_WUC_PME_STATUS | wuc));
6268
6269 /* configure and enable PHY wakeup in PHY registers */
6270 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6271 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6272
6273 /* activate PHY wakeup */
6274 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6275 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6276 if (retval)
6277 e_err("Could not set PHY Host Wakeup bit\n");
6278release:
6279 hw->phy.ops.release(hw);
6280
6281 return retval;
6282}
6283
6284static void e1000e_flush_lpic(struct pci_dev *pdev)
6285{
6286 struct net_device *netdev = pci_get_drvdata(pdev);
6287 struct e1000_adapter *adapter = netdev_priv(netdev);
6288 struct e1000_hw *hw = &adapter->hw;
6289 u32 ret_val;
6290
6291 pm_runtime_get_sync(netdev->dev.parent);
6292
6293 ret_val = hw->phy.ops.acquire(hw);
6294 if (ret_val)
6295 goto fl_out;
6296
6297 pr_info("EEE TX LPI TIMER: %08X\n",
6298 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6299
6300 hw->phy.ops.release(hw);
6301
6302fl_out:
6303 pm_runtime_put_sync(netdev->dev.parent);
6304}
6305
6306/* S0ix implementation */
6307static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6308{
6309 struct e1000_hw *hw = &adapter->hw;
6310 u32 mac_data;
6311 u16 phy_data;
6312
6313 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6314 hw->mac.type >= e1000_pch_adp) {
6315 /* Request ME configure the device for S0ix */
6316 mac_data = er32(H2ME);
6317 mac_data |= E1000_H2ME_START_DPG;
6318 mac_data &= ~E1000_H2ME_EXIT_DPG;
6319 trace_e1000e_trace_mac_register(mac_data);
6320 ew32(H2ME, mac_data);
6321 } else {
6322 /* Request driver configure the device to S0ix */
6323 /* Disable the periodic inband message,
6324 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6325 */
6326 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6327 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6328 phy_data |= BIT(10);
6329 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6330
6331 /* Make sure we don't exit K1 every time a new packet arrives
6332 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6333 */
6334 e1e_rphy(hw, I217_CGFREG, &phy_data);
6335 phy_data |= BIT(5);
6336 e1e_wphy(hw, I217_CGFREG, phy_data);
6337
6338 /* Change the MAC/PHY interface to SMBus
6339 * Force the SMBus in PHY page769_23[0] = 1
6340 * Force the SMBus in MAC CTRL_EXT[11] = 1
6341 */
6342 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6343 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6344 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6345 mac_data = er32(CTRL_EXT);
6346 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6347 ew32(CTRL_EXT, mac_data);
6348
6349 /* DFT control: PHY bit: page769_20[0] = 1
6350 * page769_20[7] - PHY PLL stop
6351 * page769_20[8] - PHY go to the electrical idle
6352 * page769_20[9] - PHY serdes disable
6353 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6354 */
6355 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6356 phy_data |= BIT(0);
6357 phy_data |= BIT(7);
6358 phy_data |= BIT(8);
6359 phy_data |= BIT(9);
6360 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6361
6362 mac_data = er32(EXTCNF_CTRL);
6363 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6364 ew32(EXTCNF_CTRL, mac_data);
6365
6366 /* Enable the Dynamic Power Gating in the MAC */
6367 mac_data = er32(FEXTNVM7);
6368 mac_data |= BIT(22);
6369 ew32(FEXTNVM7, mac_data);
6370
6371 /* Disable disconnected cable conditioning for Power Gating */
6372 mac_data = er32(DPGFR);
6373 mac_data |= BIT(2);
6374 ew32(DPGFR, mac_data);
6375
6376 /* Don't wake from dynamic Power Gating with clock request */
6377 mac_data = er32(FEXTNVM12);
6378 mac_data |= BIT(12);
6379 ew32(FEXTNVM12, mac_data);
6380
6381 /* Ungate PGCB clock */
6382 mac_data = er32(FEXTNVM9);
6383 mac_data &= ~BIT(28);
6384 ew32(FEXTNVM9, mac_data);
6385
6386 /* Enable K1 off to enable mPHY Power Gating */
6387 mac_data = er32(FEXTNVM6);
6388 mac_data |= BIT(31);
6389 ew32(FEXTNVM6, mac_data);
6390
6391 /* Enable mPHY power gating for any link and speed */
6392 mac_data = er32(FEXTNVM8);
6393 mac_data |= BIT(9);
6394 ew32(FEXTNVM8, mac_data);
6395
6396 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6397 mac_data = er32(CTRL_EXT);
6398 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6399 ew32(CTRL_EXT, mac_data);
6400
6401 /* No MAC DPG gating SLP_S0 in modern standby
6402 * Switch the logic of the lanphypc to use PMC counter
6403 */
6404 mac_data = er32(FEXTNVM5);
6405 mac_data |= BIT(7);
6406 ew32(FEXTNVM5, mac_data);
6407 }
6408
6409 /* Disable the time synchronization clock */
6410 mac_data = er32(FEXTNVM7);
6411 mac_data |= BIT(31);
6412 mac_data &= ~BIT(0);
6413 ew32(FEXTNVM7, mac_data);
6414
6415 /* Dynamic Power Gating Enable */
6416 mac_data = er32(CTRL_EXT);
6417 mac_data |= BIT(3);
6418 ew32(CTRL_EXT, mac_data);
6419
6420 /* Check MAC Tx/Rx packet buffer pointers.
6421 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6422 * pending traffic indication that would prevent power gating.
6423 */
6424 mac_data = er32(TDFH);
6425 if (mac_data)
6426 ew32(TDFH, 0);
6427 mac_data = er32(TDFT);
6428 if (mac_data)
6429 ew32(TDFT, 0);
6430 mac_data = er32(TDFHS);
6431 if (mac_data)
6432 ew32(TDFHS, 0);
6433 mac_data = er32(TDFTS);
6434 if (mac_data)
6435 ew32(TDFTS, 0);
6436 mac_data = er32(TDFPC);
6437 if (mac_data)
6438 ew32(TDFPC, 0);
6439 mac_data = er32(RDFH);
6440 if (mac_data)
6441 ew32(RDFH, 0);
6442 mac_data = er32(RDFT);
6443 if (mac_data)
6444 ew32(RDFT, 0);
6445 mac_data = er32(RDFHS);
6446 if (mac_data)
6447 ew32(RDFHS, 0);
6448 mac_data = er32(RDFTS);
6449 if (mac_data)
6450 ew32(RDFTS, 0);
6451 mac_data = er32(RDFPC);
6452 if (mac_data)
6453 ew32(RDFPC, 0);
6454}
6455
6456static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6457{
6458 struct e1000_hw *hw = &adapter->hw;
6459 bool firmware_bug = false;
6460 u32 mac_data;
6461 u16 phy_data;
6462 u32 i = 0;
6463
6464 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6465 hw->mac.type >= e1000_pch_adp) {
6466 /* Keep the GPT clock enabled for CSME */
6467 mac_data = er32(FEXTNVM);
6468 mac_data |= BIT(3);
6469 ew32(FEXTNVM, mac_data);
6470 /* Request ME unconfigure the device from S0ix */
6471 mac_data = er32(H2ME);
6472 mac_data &= ~E1000_H2ME_START_DPG;
6473 mac_data |= E1000_H2ME_EXIT_DPG;
6474 trace_e1000e_trace_mac_register(mac_data);
6475 ew32(H2ME, mac_data);
6476
6477 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6478 * If this takes more than 1 second, show a warning indicating a
6479 * firmware bug
6480 */
6481 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) {
6482 if (i > 100 && !firmware_bug)
6483 firmware_bug = true;
6484
6485 if (i++ == 250) {
6486 e_dbg("Timeout (firmware bug): %d msec\n",
6487 i * 10);
6488 break;
6489 }
6490
6491 usleep_range(10000, 11000);
6492 }
6493 if (firmware_bug)
6494 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
6495 i * 10);
6496 else
6497 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
6498 } else {
6499 /* Request driver unconfigure the device from S0ix */
6500
6501 /* Disable the Dynamic Power Gating in the MAC */
6502 mac_data = er32(FEXTNVM7);
6503 mac_data &= 0xFFBFFFFF;
6504 ew32(FEXTNVM7, mac_data);
6505
6506 /* Disable mPHY power gating for any link and speed */
6507 mac_data = er32(FEXTNVM8);
6508 mac_data &= ~BIT(9);
6509 ew32(FEXTNVM8, mac_data);
6510
6511 /* Disable K1 off */
6512 mac_data = er32(FEXTNVM6);
6513 mac_data &= ~BIT(31);
6514 ew32(FEXTNVM6, mac_data);
6515
6516 /* Disable Ungate PGCB clock */
6517 mac_data = er32(FEXTNVM9);
6518 mac_data |= BIT(28);
6519 ew32(FEXTNVM9, mac_data);
6520
6521 /* Cancel not waking from dynamic
6522 * Power Gating with clock request
6523 */
6524 mac_data = er32(FEXTNVM12);
6525 mac_data &= ~BIT(12);
6526 ew32(FEXTNVM12, mac_data);
6527
6528 /* Cancel disable disconnected cable conditioning
6529 * for Power Gating
6530 */
6531 mac_data = er32(DPGFR);
6532 mac_data &= ~BIT(2);
6533 ew32(DPGFR, mac_data);
6534
6535 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6536 mac_data = er32(CTRL_EXT);
6537 mac_data &= 0xFFF7FFFF;
6538 ew32(CTRL_EXT, mac_data);
6539
6540 /* Revert the lanphypc logic to use the internal Gbe counter
6541 * and not the PMC counter
6542 */
6543 mac_data = er32(FEXTNVM5);
6544 mac_data &= 0xFFFFFF7F;
6545 ew32(FEXTNVM5, mac_data);
6546
6547 /* Enable the periodic inband message,
6548 * Request PCIe clock in K1 page770_17[10:9] =01b
6549 */
6550 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6551 phy_data &= 0xFBFF;
6552 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6553 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6554
6555 /* Return back configuration
6556 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6557 */
6558 e1e_rphy(hw, I217_CGFREG, &phy_data);
6559 phy_data &= 0xFFDF;
6560 e1e_wphy(hw, I217_CGFREG, phy_data);
6561
6562 /* Change the MAC/PHY interface to Kumeran
6563 * Unforce the SMBus in PHY page769_23[0] = 0
6564 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6565 */
6566 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6567 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6568 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6569 mac_data = er32(CTRL_EXT);
6570 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6571 ew32(CTRL_EXT, mac_data);
6572 }
6573
6574 /* Disable Dynamic Power Gating */
6575 mac_data = er32(CTRL_EXT);
6576 mac_data &= 0xFFFFFFF7;
6577 ew32(CTRL_EXT, mac_data);
6578
6579 /* Enable the time synchronization clock */
6580 mac_data = er32(FEXTNVM7);
6581 mac_data &= ~BIT(31);
6582 mac_data |= BIT(0);
6583 ew32(FEXTNVM7, mac_data);
6584}
6585
6586static int e1000e_pm_freeze(struct device *dev)
6587{
6588 struct net_device *netdev = dev_get_drvdata(dev);
6589 struct e1000_adapter *adapter = netdev_priv(netdev);
6590 bool present;
6591
6592 rtnl_lock();
6593
6594 present = netif_device_present(netdev);
6595 netif_device_detach(netdev);
6596
6597 if (present && netif_running(netdev)) {
6598 int count = E1000_CHECK_RESET_COUNT;
6599
6600 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6601 usleep_range(10000, 11000);
6602
6603 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6604
6605 /* Quiesce the device without resetting the hardware */
6606 e1000e_down(adapter, false);
6607 e1000_free_irq(adapter);
6608 }
6609 rtnl_unlock();
6610
6611 e1000e_reset_interrupt_capability(adapter);
6612
6613 /* Allow time for pending master requests to run */
6614 e1000e_disable_pcie_master(&adapter->hw);
6615
6616 return 0;
6617}
6618
6619static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6620{
6621 struct net_device *netdev = pci_get_drvdata(pdev);
6622 struct e1000_adapter *adapter = netdev_priv(netdev);
6623 struct e1000_hw *hw = &adapter->hw;
6624 u32 ctrl, ctrl_ext, rctl, status, wufc;
6625 int retval = 0;
6626
6627 /* Runtime suspend should only enable wakeup for link changes */
6628 if (runtime)
6629 wufc = E1000_WUFC_LNKC;
6630 else if (device_may_wakeup(&pdev->dev))
6631 wufc = adapter->wol;
6632 else
6633 wufc = 0;
6634
6635 status = er32(STATUS);
6636 if (status & E1000_STATUS_LU)
6637 wufc &= ~E1000_WUFC_LNKC;
6638
6639 if (wufc) {
6640 e1000_setup_rctl(adapter);
6641 e1000e_set_rx_mode(netdev);
6642
6643 /* turn on all-multi mode if wake on multicast is enabled */
6644 if (wufc & E1000_WUFC_MC) {
6645 rctl = er32(RCTL);
6646 rctl |= E1000_RCTL_MPE;
6647 ew32(RCTL, rctl);
6648 }
6649
6650 ctrl = er32(CTRL);
6651 ctrl |= E1000_CTRL_ADVD3WUC;
6652 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6653 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6654 ew32(CTRL, ctrl);
6655
6656 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6657 adapter->hw.phy.media_type ==
6658 e1000_media_type_internal_serdes) {
6659 /* keep the laser running in D3 */
6660 ctrl_ext = er32(CTRL_EXT);
6661 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6662 ew32(CTRL_EXT, ctrl_ext);
6663 }
6664
6665 if (!runtime)
6666 e1000e_power_up_phy(adapter);
6667
6668 if (adapter->flags & FLAG_IS_ICH)
6669 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6670
6671 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6672 /* enable wakeup by the PHY */
6673 retval = e1000_init_phy_wakeup(adapter, wufc);
6674 if (retval)
6675 return retval;
6676 } else {
6677 /* enable wakeup by the MAC */
6678 ew32(WUFC, wufc);
6679 ew32(WUC, E1000_WUC_PME_EN);
6680 }
6681 } else {
6682 ew32(WUC, 0);
6683 ew32(WUFC, 0);
6684
6685 e1000_power_down_phy(adapter);
6686 }
6687
6688 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6689 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6690 } else if (hw->mac.type >= e1000_pch_lpt) {
6691 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6692 /* ULP does not support wake from unicast, multicast
6693 * or broadcast.
6694 */
6695 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6696
6697 if (retval)
6698 return retval;
6699 }
6700
6701 /* Ensure that the appropriate bits are set in LPI_CTRL
6702 * for EEE in Sx
6703 */
6704 if ((hw->phy.type >= e1000_phy_i217) &&
6705 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6706 u16 lpi_ctrl = 0;
6707
6708 retval = hw->phy.ops.acquire(hw);
6709 if (!retval) {
6710 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6711 &lpi_ctrl);
6712 if (!retval) {
6713 if (adapter->eee_advert &
6714 hw->dev_spec.ich8lan.eee_lp_ability &
6715 I82579_EEE_100_SUPPORTED)
6716 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6717 if (adapter->eee_advert &
6718 hw->dev_spec.ich8lan.eee_lp_ability &
6719 I82579_EEE_1000_SUPPORTED)
6720 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6721
6722 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6723 lpi_ctrl);
6724 }
6725 }
6726 hw->phy.ops.release(hw);
6727 }
6728
6729 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6730 * would have already happened in close and is redundant.
6731 */
6732 e1000e_release_hw_control(adapter);
6733
6734 pci_clear_master(pdev);
6735
6736 /* The pci-e switch on some quad port adapters will report a
6737 * correctable error when the MAC transitions from D0 to D3. To
6738 * prevent this we need to mask off the correctable errors on the
6739 * downstream port of the pci-e switch.
6740 *
6741 * We don't have the associated upstream bridge while assigning
6742 * the PCI device into guest. For example, the KVM on power is
6743 * one of the cases.
6744 */
6745 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6746 struct pci_dev *us_dev = pdev->bus->self;
6747 u16 devctl;
6748
6749 if (!us_dev)
6750 return 0;
6751
6752 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6753 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6754 (devctl & ~PCI_EXP_DEVCTL_CERE));
6755
6756 pci_save_state(pdev);
6757 pci_prepare_to_sleep(pdev);
6758
6759 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6760 }
6761
6762 return 0;
6763}
6764
6765/**
6766 * __e1000e_disable_aspm - Disable ASPM states
6767 * @pdev: pointer to PCI device struct
6768 * @state: bit-mask of ASPM states to disable
6769 * @locked: indication if this context holds pci_bus_sem locked.
6770 *
6771 * Some devices *must* have certain ASPM states disabled per hardware errata.
6772 **/
6773static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6774{
6775 struct pci_dev *parent = pdev->bus->self;
6776 u16 aspm_dis_mask = 0;
6777 u16 pdev_aspmc, parent_aspmc;
6778
6779 switch (state) {
6780 case PCIE_LINK_STATE_L0S:
6781 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6782 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6783 fallthrough; /* can't have L1 without L0s */
6784 case PCIE_LINK_STATE_L1:
6785 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6786 break;
6787 default:
6788 return;
6789 }
6790
6791 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6792 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6793
6794 if (parent) {
6795 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6796 &parent_aspmc);
6797 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6798 }
6799
6800 /* Nothing to do if the ASPM states to be disabled already are */
6801 if (!(pdev_aspmc & aspm_dis_mask) &&
6802 (!parent || !(parent_aspmc & aspm_dis_mask)))
6803 return;
6804
6805 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6806 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6807 "L0s" : "",
6808 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6809 "L1" : "");
6810
6811#ifdef CONFIG_PCIEASPM
6812 if (locked)
6813 pci_disable_link_state_locked(pdev, state);
6814 else
6815 pci_disable_link_state(pdev, state);
6816
6817 /* Double-check ASPM control. If not disabled by the above, the
6818 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6819 * not enabled); override by writing PCI config space directly.
6820 */
6821 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6822 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6823
6824 if (!(aspm_dis_mask & pdev_aspmc))
6825 return;
6826#endif
6827
6828 /* Both device and parent should have the same ASPM setting.
6829 * Disable ASPM in downstream component first and then upstream.
6830 */
6831 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6832
6833 if (parent)
6834 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6835 aspm_dis_mask);
6836}
6837
6838/**
6839 * e1000e_disable_aspm - Disable ASPM states.
6840 * @pdev: pointer to PCI device struct
6841 * @state: bit-mask of ASPM states to disable
6842 *
6843 * This function acquires the pci_bus_sem!
6844 * Some devices *must* have certain ASPM states disabled per hardware errata.
6845 **/
6846static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6847{
6848 __e1000e_disable_aspm(pdev, state, 0);
6849}
6850
6851/**
6852 * e1000e_disable_aspm_locked - Disable ASPM states.
6853 * @pdev: pointer to PCI device struct
6854 * @state: bit-mask of ASPM states to disable
6855 *
6856 * This function must be called with pci_bus_sem acquired!
6857 * Some devices *must* have certain ASPM states disabled per hardware errata.
6858 **/
6859static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6860{
6861 __e1000e_disable_aspm(pdev, state, 1);
6862}
6863
6864static int e1000e_pm_thaw(struct device *dev)
6865{
6866 struct net_device *netdev = dev_get_drvdata(dev);
6867 struct e1000_adapter *adapter = netdev_priv(netdev);
6868 int rc = 0;
6869
6870 e1000e_set_interrupt_capability(adapter);
6871
6872 rtnl_lock();
6873 if (netif_running(netdev)) {
6874 rc = e1000_request_irq(adapter);
6875 if (rc)
6876 goto err_irq;
6877
6878 e1000e_up(adapter);
6879 }
6880
6881 netif_device_attach(netdev);
6882err_irq:
6883 rtnl_unlock();
6884
6885 return rc;
6886}
6887
6888static int __e1000_resume(struct pci_dev *pdev)
6889{
6890 struct net_device *netdev = pci_get_drvdata(pdev);
6891 struct e1000_adapter *adapter = netdev_priv(netdev);
6892 struct e1000_hw *hw = &adapter->hw;
6893 u16 aspm_disable_flag = 0;
6894
6895 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6896 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6897 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6898 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6899 if (aspm_disable_flag)
6900 e1000e_disable_aspm(pdev, aspm_disable_flag);
6901
6902 pci_set_master(pdev);
6903
6904 if (hw->mac.type >= e1000_pch2lan)
6905 e1000_resume_workarounds_pchlan(&adapter->hw);
6906
6907 e1000e_power_up_phy(adapter);
6908
6909 /* report the system wakeup cause from S3/S4 */
6910 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6911 u16 phy_data;
6912
6913 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6914 if (phy_data) {
6915 e_info("PHY Wakeup cause - %s\n",
6916 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6917 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6918 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6919 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6920 phy_data & E1000_WUS_LNKC ?
6921 "Link Status Change" : "other");
6922 }
6923 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6924 } else {
6925 u32 wus = er32(WUS);
6926
6927 if (wus) {
6928 e_info("MAC Wakeup cause - %s\n",
6929 wus & E1000_WUS_EX ? "Unicast Packet" :
6930 wus & E1000_WUS_MC ? "Multicast Packet" :
6931 wus & E1000_WUS_BC ? "Broadcast Packet" :
6932 wus & E1000_WUS_MAG ? "Magic Packet" :
6933 wus & E1000_WUS_LNKC ? "Link Status Change" :
6934 "other");
6935 }
6936 ew32(WUS, ~0);
6937 }
6938
6939 e1000e_reset(adapter);
6940
6941 e1000_init_manageability_pt(adapter);
6942
6943 /* If the controller has AMT, do not set DRV_LOAD until the interface
6944 * is up. For all other cases, let the f/w know that the h/w is now
6945 * under the control of the driver.
6946 */
6947 if (!(adapter->flags & FLAG_HAS_AMT))
6948 e1000e_get_hw_control(adapter);
6949
6950 return 0;
6951}
6952
6953static __maybe_unused int e1000e_pm_prepare(struct device *dev)
6954{
6955 return pm_runtime_suspended(dev) &&
6956 pm_suspend_via_firmware();
6957}
6958
6959static __maybe_unused int e1000e_pm_suspend(struct device *dev)
6960{
6961 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6962 struct e1000_adapter *adapter = netdev_priv(netdev);
6963 struct pci_dev *pdev = to_pci_dev(dev);
6964 int rc;
6965
6966 e1000e_flush_lpic(pdev);
6967
6968 e1000e_pm_freeze(dev);
6969
6970 rc = __e1000_shutdown(pdev, false);
6971 if (rc) {
6972 e1000e_pm_thaw(dev);
6973 } else {
6974 /* Introduce S0ix implementation */
6975 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6976 e1000e_s0ix_entry_flow(adapter);
6977 }
6978
6979 return rc;
6980}
6981
6982static __maybe_unused int e1000e_pm_resume(struct device *dev)
6983{
6984 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6985 struct e1000_adapter *adapter = netdev_priv(netdev);
6986 struct pci_dev *pdev = to_pci_dev(dev);
6987 int rc;
6988
6989 /* Introduce S0ix implementation */
6990 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6991 e1000e_s0ix_exit_flow(adapter);
6992
6993 rc = __e1000_resume(pdev);
6994 if (rc)
6995 return rc;
6996
6997 return e1000e_pm_thaw(dev);
6998}
6999
7000static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
7001{
7002 struct net_device *netdev = dev_get_drvdata(dev);
7003 struct e1000_adapter *adapter = netdev_priv(netdev);
7004 u16 eee_lp;
7005
7006 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
7007
7008 if (!e1000e_has_link(adapter)) {
7009 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
7010 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
7011 }
7012
7013 return -EBUSY;
7014}
7015
7016static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev)
7017{
7018 struct pci_dev *pdev = to_pci_dev(dev);
7019 struct net_device *netdev = pci_get_drvdata(pdev);
7020 struct e1000_adapter *adapter = netdev_priv(netdev);
7021 int rc;
7022
7023 pdev->pme_poll = true;
7024
7025 rc = __e1000_resume(pdev);
7026 if (rc)
7027 return rc;
7028
7029 if (netdev->flags & IFF_UP)
7030 e1000e_up(adapter);
7031
7032 return rc;
7033}
7034
7035static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev)
7036{
7037 struct pci_dev *pdev = to_pci_dev(dev);
7038 struct net_device *netdev = pci_get_drvdata(pdev);
7039 struct e1000_adapter *adapter = netdev_priv(netdev);
7040
7041 if (netdev->flags & IFF_UP) {
7042 int count = E1000_CHECK_RESET_COUNT;
7043
7044 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
7045 usleep_range(10000, 11000);
7046
7047 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7048
7049 /* Down the device without resetting the hardware */
7050 e1000e_down(adapter, false);
7051 }
7052
7053 if (__e1000_shutdown(pdev, true)) {
7054 e1000e_pm_runtime_resume(dev);
7055 return -EBUSY;
7056 }
7057
7058 return 0;
7059}
7060
7061static void e1000_shutdown(struct pci_dev *pdev)
7062{
7063 e1000e_flush_lpic(pdev);
7064
7065 e1000e_pm_freeze(&pdev->dev);
7066
7067 __e1000_shutdown(pdev, false);
7068}
7069
7070#ifdef CONFIG_NET_POLL_CONTROLLER
7071
7072static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
7073{
7074 struct net_device *netdev = data;
7075 struct e1000_adapter *adapter = netdev_priv(netdev);
7076
7077 if (adapter->msix_entries) {
7078 int vector, msix_irq;
7079
7080 vector = 0;
7081 msix_irq = adapter->msix_entries[vector].vector;
7082 if (disable_hardirq(msix_irq))
7083 e1000_intr_msix_rx(msix_irq, netdev);
7084 enable_irq(msix_irq);
7085
7086 vector++;
7087 msix_irq = adapter->msix_entries[vector].vector;
7088 if (disable_hardirq(msix_irq))
7089 e1000_intr_msix_tx(msix_irq, netdev);
7090 enable_irq(msix_irq);
7091
7092 vector++;
7093 msix_irq = adapter->msix_entries[vector].vector;
7094 if (disable_hardirq(msix_irq))
7095 e1000_msix_other(msix_irq, netdev);
7096 enable_irq(msix_irq);
7097 }
7098
7099 return IRQ_HANDLED;
7100}
7101
7102/**
7103 * e1000_netpoll
7104 * @netdev: network interface device structure
7105 *
7106 * Polling 'interrupt' - used by things like netconsole to send skbs
7107 * without having to re-enable interrupts. It's not called while
7108 * the interrupt routine is executing.
7109 */
7110static void e1000_netpoll(struct net_device *netdev)
7111{
7112 struct e1000_adapter *adapter = netdev_priv(netdev);
7113
7114 switch (adapter->int_mode) {
7115 case E1000E_INT_MODE_MSIX:
7116 e1000_intr_msix(adapter->pdev->irq, netdev);
7117 break;
7118 case E1000E_INT_MODE_MSI:
7119 if (disable_hardirq(adapter->pdev->irq))
7120 e1000_intr_msi(adapter->pdev->irq, netdev);
7121 enable_irq(adapter->pdev->irq);
7122 break;
7123 default: /* E1000E_INT_MODE_LEGACY */
7124 if (disable_hardirq(adapter->pdev->irq))
7125 e1000_intr(adapter->pdev->irq, netdev);
7126 enable_irq(adapter->pdev->irq);
7127 break;
7128 }
7129}
7130#endif
7131
7132/**
7133 * e1000_io_error_detected - called when PCI error is detected
7134 * @pdev: Pointer to PCI device
7135 * @state: The current pci connection state
7136 *
7137 * This function is called after a PCI bus error affecting
7138 * this device has been detected.
7139 */
7140static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7141 pci_channel_state_t state)
7142{
7143 e1000e_pm_freeze(&pdev->dev);
7144
7145 if (state == pci_channel_io_perm_failure)
7146 return PCI_ERS_RESULT_DISCONNECT;
7147
7148 pci_disable_device(pdev);
7149
7150 /* Request a slot reset. */
7151 return PCI_ERS_RESULT_NEED_RESET;
7152}
7153
7154/**
7155 * e1000_io_slot_reset - called after the pci bus has been reset.
7156 * @pdev: Pointer to PCI device
7157 *
7158 * Restart the card from scratch, as if from a cold-boot. Implementation
7159 * resembles the first-half of the e1000e_pm_resume routine.
7160 */
7161static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7162{
7163 struct net_device *netdev = pci_get_drvdata(pdev);
7164 struct e1000_adapter *adapter = netdev_priv(netdev);
7165 struct e1000_hw *hw = &adapter->hw;
7166 u16 aspm_disable_flag = 0;
7167 int err;
7168 pci_ers_result_t result;
7169
7170 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7171 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7172 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7173 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7174 if (aspm_disable_flag)
7175 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
7176
7177 err = pci_enable_device_mem(pdev);
7178 if (err) {
7179 dev_err(&pdev->dev,
7180 "Cannot re-enable PCI device after reset.\n");
7181 result = PCI_ERS_RESULT_DISCONNECT;
7182 } else {
7183 pdev->state_saved = true;
7184 pci_restore_state(pdev);
7185 pci_set_master(pdev);
7186
7187 pci_enable_wake(pdev, PCI_D3hot, 0);
7188 pci_enable_wake(pdev, PCI_D3cold, 0);
7189
7190 e1000e_reset(adapter);
7191 ew32(WUS, ~0);
7192 result = PCI_ERS_RESULT_RECOVERED;
7193 }
7194
7195 return result;
7196}
7197
7198/**
7199 * e1000_io_resume - called when traffic can start flowing again.
7200 * @pdev: Pointer to PCI device
7201 *
7202 * This callback is called when the error recovery driver tells us that
7203 * its OK to resume normal operation. Implementation resembles the
7204 * second-half of the e1000e_pm_resume routine.
7205 */
7206static void e1000_io_resume(struct pci_dev *pdev)
7207{
7208 struct net_device *netdev = pci_get_drvdata(pdev);
7209 struct e1000_adapter *adapter = netdev_priv(netdev);
7210
7211 e1000_init_manageability_pt(adapter);
7212
7213 e1000e_pm_thaw(&pdev->dev);
7214
7215 /* If the controller has AMT, do not set DRV_LOAD until the interface
7216 * is up. For all other cases, let the f/w know that the h/w is now
7217 * under the control of the driver.
7218 */
7219 if (!(adapter->flags & FLAG_HAS_AMT))
7220 e1000e_get_hw_control(adapter);
7221}
7222
7223static void e1000_print_device_info(struct e1000_adapter *adapter)
7224{
7225 struct e1000_hw *hw = &adapter->hw;
7226 struct net_device *netdev = adapter->netdev;
7227 u32 ret_val;
7228 u8 pba_str[E1000_PBANUM_LENGTH];
7229
7230 /* print bus type/speed/width info */
7231 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7232 /* bus width */
7233 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7234 "Width x1"),
7235 /* MAC address */
7236 netdev->dev_addr);
7237 e_info("Intel(R) PRO/%s Network Connection\n",
7238 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7239 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7240 E1000_PBANUM_LENGTH);
7241 if (ret_val)
7242 strscpy((char *)pba_str, "Unknown", sizeof(pba_str));
7243 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7244 hw->mac.type, hw->phy.type, pba_str);
7245}
7246
7247static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7248{
7249 struct e1000_hw *hw = &adapter->hw;
7250 int ret_val;
7251 u16 buf = 0;
7252
7253 if (hw->mac.type != e1000_82573)
7254 return;
7255
7256 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
7257 le16_to_cpus(&buf);
7258 if (!ret_val && (!(buf & BIT(0)))) {
7259 /* Deep Smart Power Down (DSPD) */
7260 dev_warn(&adapter->pdev->dev,
7261 "Warning: detected DSPD enabled in EEPROM\n");
7262 }
7263}
7264
7265static netdev_features_t e1000_fix_features(struct net_device *netdev,
7266 netdev_features_t features)
7267{
7268 struct e1000_adapter *adapter = netdev_priv(netdev);
7269 struct e1000_hw *hw = &adapter->hw;
7270
7271 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7272 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7273 features &= ~NETIF_F_RXFCS;
7274
7275 /* Since there is no support for separate Rx/Tx vlan accel
7276 * enable/disable make sure Tx flag is always in same state as Rx.
7277 */
7278 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7279 features |= NETIF_F_HW_VLAN_CTAG_TX;
7280 else
7281 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7282
7283 return features;
7284}
7285
7286static int e1000_set_features(struct net_device *netdev,
7287 netdev_features_t features)
7288{
7289 struct e1000_adapter *adapter = netdev_priv(netdev);
7290 netdev_features_t changed = features ^ netdev->features;
7291
7292 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7293 adapter->flags |= FLAG_TSO_FORCE;
7294
7295 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7296 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7297 NETIF_F_RXALL)))
7298 return 0;
7299
7300 if (changed & NETIF_F_RXFCS) {
7301 if (features & NETIF_F_RXFCS) {
7302 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7303 } else {
7304 /* We need to take it back to defaults, which might mean
7305 * stripping is still disabled at the adapter level.
7306 */
7307 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7308 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7309 else
7310 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7311 }
7312 }
7313
7314 netdev->features = features;
7315
7316 if (netif_running(netdev))
7317 e1000e_reinit_locked(adapter);
7318 else
7319 e1000e_reset(adapter);
7320
7321 return 1;
7322}
7323
7324static const struct net_device_ops e1000e_netdev_ops = {
7325 .ndo_open = e1000e_open,
7326 .ndo_stop = e1000e_close,
7327 .ndo_start_xmit = e1000_xmit_frame,
7328 .ndo_get_stats64 = e1000e_get_stats64,
7329 .ndo_set_rx_mode = e1000e_set_rx_mode,
7330 .ndo_set_mac_address = e1000_set_mac,
7331 .ndo_change_mtu = e1000_change_mtu,
7332 .ndo_eth_ioctl = e1000_ioctl,
7333 .ndo_tx_timeout = e1000_tx_timeout,
7334 .ndo_validate_addr = eth_validate_addr,
7335
7336 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7337 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7338#ifdef CONFIG_NET_POLL_CONTROLLER
7339 .ndo_poll_controller = e1000_netpoll,
7340#endif
7341 .ndo_set_features = e1000_set_features,
7342 .ndo_fix_features = e1000_fix_features,
7343 .ndo_features_check = passthru_features_check,
7344};
7345
7346/**
7347 * e1000_probe - Device Initialization Routine
7348 * @pdev: PCI device information struct
7349 * @ent: entry in e1000_pci_tbl
7350 *
7351 * Returns 0 on success, negative on failure
7352 *
7353 * e1000_probe initializes an adapter identified by a pci_dev structure.
7354 * The OS initialization, configuring of the adapter private structure,
7355 * and a hardware reset occur.
7356 **/
7357static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7358{
7359 struct net_device *netdev;
7360 struct e1000_adapter *adapter;
7361 struct e1000_hw *hw;
7362 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7363 resource_size_t mmio_start, mmio_len;
7364 resource_size_t flash_start, flash_len;
7365 static int cards_found;
7366 u16 aspm_disable_flag = 0;
7367 u16 eeprom_data = 0;
7368 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7369 int bars, i, err;
7370 s32 ret_val = 0;
7371
7372 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7373 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7374 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7375 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7376 if (aspm_disable_flag)
7377 e1000e_disable_aspm(pdev, aspm_disable_flag);
7378
7379 err = pci_enable_device_mem(pdev);
7380 if (err)
7381 return err;
7382
7383 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7384 if (err) {
7385 dev_err(&pdev->dev,
7386 "No usable DMA configuration, aborting\n");
7387 goto err_dma;
7388 }
7389
7390 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7391 err = pci_request_selected_regions_exclusive(pdev, bars,
7392 e1000e_driver_name);
7393 if (err)
7394 goto err_pci_reg;
7395
7396 pci_set_master(pdev);
7397 /* PCI config space info */
7398 err = pci_save_state(pdev);
7399 if (err)
7400 goto err_alloc_etherdev;
7401
7402 err = -ENOMEM;
7403 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7404 if (!netdev)
7405 goto err_alloc_etherdev;
7406
7407 SET_NETDEV_DEV(netdev, &pdev->dev);
7408
7409 netdev->irq = pdev->irq;
7410
7411 pci_set_drvdata(pdev, netdev);
7412 adapter = netdev_priv(netdev);
7413 hw = &adapter->hw;
7414 adapter->netdev = netdev;
7415 adapter->pdev = pdev;
7416 adapter->ei = ei;
7417 adapter->pba = ei->pba;
7418 adapter->flags = ei->flags;
7419 adapter->flags2 = ei->flags2;
7420 adapter->hw.adapter = adapter;
7421 adapter->hw.mac.type = ei->mac;
7422 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7423 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7424
7425 mmio_start = pci_resource_start(pdev, 0);
7426 mmio_len = pci_resource_len(pdev, 0);
7427
7428 err = -EIO;
7429 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7430 if (!adapter->hw.hw_addr)
7431 goto err_ioremap;
7432
7433 if ((adapter->flags & FLAG_HAS_FLASH) &&
7434 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7435 (hw->mac.type < e1000_pch_spt)) {
7436 flash_start = pci_resource_start(pdev, 1);
7437 flash_len = pci_resource_len(pdev, 1);
7438 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7439 if (!adapter->hw.flash_address)
7440 goto err_flashmap;
7441 }
7442
7443 /* Set default EEE advertisement */
7444 if (adapter->flags2 & FLAG2_HAS_EEE)
7445 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7446
7447 /* construct the net_device struct */
7448 netdev->netdev_ops = &e1000e_netdev_ops;
7449 e1000e_set_ethtool_ops(netdev);
7450 netdev->watchdog_timeo = 5 * HZ;
7451 netif_napi_add(netdev, &adapter->napi, e1000e_poll);
7452 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7453
7454 netdev->mem_start = mmio_start;
7455 netdev->mem_end = mmio_start + mmio_len;
7456
7457 adapter->bd_number = cards_found++;
7458
7459 e1000e_check_options(adapter);
7460
7461 /* setup adapter struct */
7462 err = e1000_sw_init(adapter);
7463 if (err)
7464 goto err_sw_init;
7465
7466 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7467 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7468 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7469
7470 err = ei->get_variants(adapter);
7471 if (err)
7472 goto err_hw_init;
7473
7474 if ((adapter->flags & FLAG_IS_ICH) &&
7475 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7476 (hw->mac.type < e1000_pch_spt))
7477 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7478
7479 hw->mac.ops.get_bus_info(&adapter->hw);
7480
7481 adapter->hw.phy.autoneg_wait_to_complete = 0;
7482
7483 /* Copper options */
7484 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7485 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7486 adapter->hw.phy.disable_polarity_correction = 0;
7487 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7488 }
7489
7490 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7491 dev_info(&pdev->dev,
7492 "PHY reset is blocked due to SOL/IDER session.\n");
7493
7494 /* Set initial default active device features */
7495 netdev->features = (NETIF_F_SG |
7496 NETIF_F_HW_VLAN_CTAG_RX |
7497 NETIF_F_HW_VLAN_CTAG_TX |
7498 NETIF_F_TSO |
7499 NETIF_F_TSO6 |
7500 NETIF_F_RXHASH |
7501 NETIF_F_RXCSUM |
7502 NETIF_F_HW_CSUM);
7503
7504 /* disable TSO for pcie and 10/100 speeds to avoid
7505 * some hardware issues and for i219 to fix transfer
7506 * speed being capped at 60%
7507 */
7508 if (!(adapter->flags & FLAG_TSO_FORCE)) {
7509 switch (adapter->link_speed) {
7510 case SPEED_10:
7511 case SPEED_100:
7512 e_info("10/100 speed: disabling TSO\n");
7513 netdev->features &= ~NETIF_F_TSO;
7514 netdev->features &= ~NETIF_F_TSO6;
7515 break;
7516 case SPEED_1000:
7517 netdev->features |= NETIF_F_TSO;
7518 netdev->features |= NETIF_F_TSO6;
7519 break;
7520 default:
7521 /* oops */
7522 break;
7523 }
7524 if (hw->mac.type == e1000_pch_spt) {
7525 netdev->features &= ~NETIF_F_TSO;
7526 netdev->features &= ~NETIF_F_TSO6;
7527 }
7528 }
7529
7530 /* Set user-changeable features (subset of all device features) */
7531 netdev->hw_features = netdev->features;
7532 netdev->hw_features |= NETIF_F_RXFCS;
7533 netdev->priv_flags |= IFF_SUPP_NOFCS;
7534 netdev->hw_features |= NETIF_F_RXALL;
7535
7536 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7537 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7538
7539 netdev->vlan_features |= (NETIF_F_SG |
7540 NETIF_F_TSO |
7541 NETIF_F_TSO6 |
7542 NETIF_F_HW_CSUM);
7543
7544 netdev->priv_flags |= IFF_UNICAST_FLT;
7545
7546 netdev->features |= NETIF_F_HIGHDMA;
7547 netdev->vlan_features |= NETIF_F_HIGHDMA;
7548
7549 /* MTU range: 68 - max_hw_frame_size */
7550 netdev->min_mtu = ETH_MIN_MTU;
7551 netdev->max_mtu = adapter->max_hw_frame_size -
7552 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7553
7554 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7555 adapter->flags |= FLAG_MNG_PT_ENABLED;
7556
7557 /* before reading the NVM, reset the controller to
7558 * put the device in a known good starting state
7559 */
7560 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7561
7562 /* systems with ASPM and others may see the checksum fail on the first
7563 * attempt. Let's give it a few tries
7564 */
7565 for (i = 0;; i++) {
7566 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7567 break;
7568 if (i == 2) {
7569 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7570 err = -EIO;
7571 goto err_eeprom;
7572 }
7573 }
7574
7575 e1000_eeprom_checks(adapter);
7576
7577 /* copy the MAC address */
7578 if (e1000e_read_mac_addr(&adapter->hw))
7579 dev_err(&pdev->dev,
7580 "NVM Read Error while reading MAC address\n");
7581
7582 eth_hw_addr_set(netdev, adapter->hw.mac.addr);
7583
7584 if (!is_valid_ether_addr(netdev->dev_addr)) {
7585 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7586 netdev->dev_addr);
7587 err = -EIO;
7588 goto err_eeprom;
7589 }
7590
7591 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7592 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7593
7594 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7595 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7596 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7597 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7598 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7599
7600 /* Initialize link parameters. User can change them with ethtool */
7601 adapter->hw.mac.autoneg = 1;
7602 adapter->fc_autoneg = true;
7603 adapter->hw.fc.requested_mode = e1000_fc_default;
7604 adapter->hw.fc.current_mode = e1000_fc_default;
7605 adapter->hw.phy.autoneg_advertised = 0x2f;
7606
7607 /* Initial Wake on LAN setting - If APM wake is enabled in
7608 * the EEPROM, enable the ACPI Magic Packet filter
7609 */
7610 if (adapter->flags & FLAG_APME_IN_WUC) {
7611 /* APME bit in EEPROM is mapped to WUC.APME */
7612 eeprom_data = er32(WUC);
7613 eeprom_apme_mask = E1000_WUC_APME;
7614 if ((hw->mac.type > e1000_ich10lan) &&
7615 (eeprom_data & E1000_WUC_PHY_WAKE))
7616 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7617 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7618 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7619 (adapter->hw.bus.func == 1))
7620 ret_val = e1000_read_nvm(&adapter->hw,
7621 NVM_INIT_CONTROL3_PORT_B,
7622 1, &eeprom_data);
7623 else
7624 ret_val = e1000_read_nvm(&adapter->hw,
7625 NVM_INIT_CONTROL3_PORT_A,
7626 1, &eeprom_data);
7627 }
7628
7629 /* fetch WoL from EEPROM */
7630 if (ret_val)
7631 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7632 else if (eeprom_data & eeprom_apme_mask)
7633 adapter->eeprom_wol |= E1000_WUFC_MAG;
7634
7635 /* now that we have the eeprom settings, apply the special cases
7636 * where the eeprom may be wrong or the board simply won't support
7637 * wake on lan on a particular port
7638 */
7639 if (!(adapter->flags & FLAG_HAS_WOL))
7640 adapter->eeprom_wol = 0;
7641
7642 /* initialize the wol settings based on the eeprom settings */
7643 adapter->wol = adapter->eeprom_wol;
7644
7645 /* make sure adapter isn't asleep if manageability is enabled */
7646 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7647 (hw->mac.ops.check_mng_mode(hw)))
7648 device_wakeup_enable(&pdev->dev);
7649
7650 /* save off EEPROM version number */
7651 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7652
7653 if (ret_val) {
7654 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7655 adapter->eeprom_vers = 0;
7656 }
7657
7658 /* init PTP hardware clock */
7659 e1000e_ptp_init(adapter);
7660
7661 /* reset the hardware with the new settings */
7662 e1000e_reset(adapter);
7663
7664 /* If the controller has AMT, do not set DRV_LOAD until the interface
7665 * is up. For all other cases, let the f/w know that the h/w is now
7666 * under the control of the driver.
7667 */
7668 if (!(adapter->flags & FLAG_HAS_AMT))
7669 e1000e_get_hw_control(adapter);
7670
7671 if (hw->mac.type >= e1000_pch_cnp)
7672 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7673
7674 strscpy(netdev->name, "eth%d", sizeof(netdev->name));
7675 err = register_netdev(netdev);
7676 if (err)
7677 goto err_register;
7678
7679 /* carrier off reporting is important to ethtool even BEFORE open */
7680 netif_carrier_off(netdev);
7681
7682 e1000_print_device_info(adapter);
7683
7684 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE);
7685
7686 if (pci_dev_run_wake(pdev))
7687 pm_runtime_put_noidle(&pdev->dev);
7688
7689 return 0;
7690
7691err_register:
7692 if (!(adapter->flags & FLAG_HAS_AMT))
7693 e1000e_release_hw_control(adapter);
7694err_eeprom:
7695 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7696 e1000_phy_hw_reset(&adapter->hw);
7697err_hw_init:
7698 kfree(adapter->tx_ring);
7699 kfree(adapter->rx_ring);
7700err_sw_init:
7701 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7702 iounmap(adapter->hw.flash_address);
7703 e1000e_reset_interrupt_capability(adapter);
7704err_flashmap:
7705 iounmap(adapter->hw.hw_addr);
7706err_ioremap:
7707 free_netdev(netdev);
7708err_alloc_etherdev:
7709 pci_release_mem_regions(pdev);
7710err_pci_reg:
7711err_dma:
7712 pci_disable_device(pdev);
7713 return err;
7714}
7715
7716/**
7717 * e1000_remove - Device Removal Routine
7718 * @pdev: PCI device information struct
7719 *
7720 * e1000_remove is called by the PCI subsystem to alert the driver
7721 * that it should release a PCI device. This could be caused by a
7722 * Hot-Plug event, or because the driver is going to be removed from
7723 * memory.
7724 **/
7725static void e1000_remove(struct pci_dev *pdev)
7726{
7727 struct net_device *netdev = pci_get_drvdata(pdev);
7728 struct e1000_adapter *adapter = netdev_priv(netdev);
7729
7730 e1000e_ptp_remove(adapter);
7731
7732 /* The timers may be rescheduled, so explicitly disable them
7733 * from being rescheduled.
7734 */
7735 set_bit(__E1000_DOWN, &adapter->state);
7736 del_timer_sync(&adapter->watchdog_timer);
7737 del_timer_sync(&adapter->phy_info_timer);
7738
7739 cancel_work_sync(&adapter->reset_task);
7740 cancel_work_sync(&adapter->watchdog_task);
7741 cancel_work_sync(&adapter->downshift_task);
7742 cancel_work_sync(&adapter->update_phy_task);
7743 cancel_work_sync(&adapter->print_hang_task);
7744
7745 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7746 cancel_work_sync(&adapter->tx_hwtstamp_work);
7747 if (adapter->tx_hwtstamp_skb) {
7748 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7749 adapter->tx_hwtstamp_skb = NULL;
7750 }
7751 }
7752
7753 unregister_netdev(netdev);
7754
7755 if (pci_dev_run_wake(pdev))
7756 pm_runtime_get_noresume(&pdev->dev);
7757
7758 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7759 * would have already happened in close and is redundant.
7760 */
7761 e1000e_release_hw_control(adapter);
7762
7763 e1000e_reset_interrupt_capability(adapter);
7764 kfree(adapter->tx_ring);
7765 kfree(adapter->rx_ring);
7766
7767 iounmap(adapter->hw.hw_addr);
7768 if ((adapter->hw.flash_address) &&
7769 (adapter->hw.mac.type < e1000_pch_spt))
7770 iounmap(adapter->hw.flash_address);
7771 pci_release_mem_regions(pdev);
7772
7773 free_netdev(netdev);
7774
7775 pci_disable_device(pdev);
7776}
7777
7778/* PCI Error Recovery (ERS) */
7779static const struct pci_error_handlers e1000_err_handler = {
7780 .error_detected = e1000_io_error_detected,
7781 .slot_reset = e1000_io_slot_reset,
7782 .resume = e1000_io_resume,
7783};
7784
7785static const struct pci_device_id e1000_pci_tbl[] = {
7786 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7787 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7788 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7789 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7790 board_82571 },
7791 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7792 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7793 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7796
7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7798 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7800 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7801
7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7805
7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7809
7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7811 board_80003es2lan },
7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7813 board_80003es2lan },
7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7815 board_80003es2lan },
7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7817 board_80003es2lan },
7818
7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7827
7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7837
7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7841
7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7845
7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7850
7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7853
7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7862 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7867 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7868 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7870 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp },
7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp },
7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp },
7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp },
7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp },
7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp },
7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp },
7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp },
7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp },
7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp },
7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp },
7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp },
7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp },
7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp },
7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp },
7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp },
7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp },
7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp },
7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp },
7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_mtp },
7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_mtp },
7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp },
7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp },
7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp },
7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp },
7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp },
7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp },
7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp },
7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp },
7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp },
7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp },
7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp },
7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp },
7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), board_pch_mtp },
7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), board_pch_mtp },
7917
7918 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7919};
7920MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7921
7922static const struct dev_pm_ops e1000_pm_ops = {
7923#ifdef CONFIG_PM_SLEEP
7924 .prepare = e1000e_pm_prepare,
7925 .suspend = e1000e_pm_suspend,
7926 .resume = e1000e_pm_resume,
7927 .freeze = e1000e_pm_freeze,
7928 .thaw = e1000e_pm_thaw,
7929 .poweroff = e1000e_pm_suspend,
7930 .restore = e1000e_pm_resume,
7931#endif
7932 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7933 e1000e_pm_runtime_idle)
7934};
7935
7936/* PCI Device API Driver */
7937static struct pci_driver e1000_driver = {
7938 .name = e1000e_driver_name,
7939 .id_table = e1000_pci_tbl,
7940 .probe = e1000_probe,
7941 .remove = e1000_remove,
7942 .driver = {
7943 .pm = &e1000_pm_ops,
7944 },
7945 .shutdown = e1000_shutdown,
7946 .err_handler = &e1000_err_handler
7947};
7948
7949/**
7950 * e1000_init_module - Driver Registration Routine
7951 *
7952 * e1000_init_module is the first routine called when the driver is
7953 * loaded. All it does is register with the PCI subsystem.
7954 **/
7955static int __init e1000_init_module(void)
7956{
7957 pr_info("Intel(R) PRO/1000 Network Driver\n");
7958 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7959
7960 return pci_register_driver(&e1000_driver);
7961}
7962module_init(e1000_init_module);
7963
7964/**
7965 * e1000_exit_module - Driver Exit Cleanup Routine
7966 *
7967 * e1000_exit_module is called just before the driver is removed
7968 * from memory.
7969 **/
7970static void __exit e1000_exit_module(void)
7971{
7972 pci_unregister_driver(&e1000_driver);
7973}
7974module_exit(e1000_exit_module);
7975
7976MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7977MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7978MODULE_LICENSE("GPL v2");
7979
7980/* netdev.c */
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
14#include <linux/interrupt.h>
15#include <linux/tcp.h>
16#include <linux/ipv6.h>
17#include <linux/slab.h>
18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
24#include <linux/pm_qos.h>
25#include <linux/pm_runtime.h>
26#include <linux/aer.h>
27#include <linux/prefetch.h>
28#include <linux/suspend.h>
29
30#include "e1000.h"
31
32char e1000e_driver_name[] = "e1000e";
33
34#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
35static int debug = -1;
36module_param(debug, int, 0);
37MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
38
39static const struct e1000_info *e1000_info_tbl[] = {
40 [board_82571] = &e1000_82571_info,
41 [board_82572] = &e1000_82572_info,
42 [board_82573] = &e1000_82573_info,
43 [board_82574] = &e1000_82574_info,
44 [board_82583] = &e1000_82583_info,
45 [board_80003es2lan] = &e1000_es2_info,
46 [board_ich8lan] = &e1000_ich8_info,
47 [board_ich9lan] = &e1000_ich9_info,
48 [board_ich10lan] = &e1000_ich10_info,
49 [board_pchlan] = &e1000_pch_info,
50 [board_pch2lan] = &e1000_pch2_info,
51 [board_pch_lpt] = &e1000_pch_lpt_info,
52 [board_pch_spt] = &e1000_pch_spt_info,
53 [board_pch_cnp] = &e1000_pch_cnp_info,
54 [board_pch_tgp] = &e1000_pch_tgp_info,
55};
56
57struct e1000_reg_info {
58 u32 ofs;
59 char *name;
60};
61
62static const struct e1000_reg_info e1000_reg_info_tbl[] = {
63 /* General Registers */
64 {E1000_CTRL, "CTRL"},
65 {E1000_STATUS, "STATUS"},
66 {E1000_CTRL_EXT, "CTRL_EXT"},
67
68 /* Interrupt Registers */
69 {E1000_ICR, "ICR"},
70
71 /* Rx Registers */
72 {E1000_RCTL, "RCTL"},
73 {E1000_RDLEN(0), "RDLEN"},
74 {E1000_RDH(0), "RDH"},
75 {E1000_RDT(0), "RDT"},
76 {E1000_RDTR, "RDTR"},
77 {E1000_RXDCTL(0), "RXDCTL"},
78 {E1000_ERT, "ERT"},
79 {E1000_RDBAL(0), "RDBAL"},
80 {E1000_RDBAH(0), "RDBAH"},
81 {E1000_RDFH, "RDFH"},
82 {E1000_RDFT, "RDFT"},
83 {E1000_RDFHS, "RDFHS"},
84 {E1000_RDFTS, "RDFTS"},
85 {E1000_RDFPC, "RDFPC"},
86
87 /* Tx Registers */
88 {E1000_TCTL, "TCTL"},
89 {E1000_TDBAL(0), "TDBAL"},
90 {E1000_TDBAH(0), "TDBAH"},
91 {E1000_TDLEN(0), "TDLEN"},
92 {E1000_TDH(0), "TDH"},
93 {E1000_TDT(0), "TDT"},
94 {E1000_TIDV, "TIDV"},
95 {E1000_TXDCTL(0), "TXDCTL"},
96 {E1000_TADV, "TADV"},
97 {E1000_TARC(0), "TARC"},
98 {E1000_TDFH, "TDFH"},
99 {E1000_TDFT, "TDFT"},
100 {E1000_TDFHS, "TDFHS"},
101 {E1000_TDFTS, "TDFTS"},
102 {E1000_TDFPC, "TDFPC"},
103
104 /* List Terminator */
105 {0, NULL}
106};
107
108/**
109 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
110 * @hw: pointer to the HW structure
111 *
112 * When updating the MAC CSR registers, the Manageability Engine (ME) could
113 * be accessing the registers at the same time. Normally, this is handled in
114 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
115 * accesses later than it should which could result in the register to have
116 * an incorrect value. Workaround this by checking the FWSM register which
117 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
118 * and try again a number of times.
119 **/
120static void __ew32_prepare(struct e1000_hw *hw)
121{
122 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
123
124 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
125 udelay(50);
126}
127
128void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
129{
130 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
131 __ew32_prepare(hw);
132
133 writel(val, hw->hw_addr + reg);
134}
135
136/**
137 * e1000_regdump - register printout routine
138 * @hw: pointer to the HW structure
139 * @reginfo: pointer to the register info table
140 **/
141static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
142{
143 int n = 0;
144 char rname[16];
145 u32 regs[8];
146
147 switch (reginfo->ofs) {
148 case E1000_RXDCTL(0):
149 for (n = 0; n < 2; n++)
150 regs[n] = __er32(hw, E1000_RXDCTL(n));
151 break;
152 case E1000_TXDCTL(0):
153 for (n = 0; n < 2; n++)
154 regs[n] = __er32(hw, E1000_TXDCTL(n));
155 break;
156 case E1000_TARC(0):
157 for (n = 0; n < 2; n++)
158 regs[n] = __er32(hw, E1000_TARC(n));
159 break;
160 default:
161 pr_info("%-15s %08x\n",
162 reginfo->name, __er32(hw, reginfo->ofs));
163 return;
164 }
165
166 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
167 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
168}
169
170static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
171 struct e1000_buffer *bi)
172{
173 int i;
174 struct e1000_ps_page *ps_page;
175
176 for (i = 0; i < adapter->rx_ps_pages; i++) {
177 ps_page = &bi->ps_pages[i];
178
179 if (ps_page->page) {
180 pr_info("packet dump for ps_page %d:\n", i);
181 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
182 16, 1, page_address(ps_page->page),
183 PAGE_SIZE, true);
184 }
185 }
186}
187
188/**
189 * e1000e_dump - Print registers, Tx-ring and Rx-ring
190 * @adapter: board private structure
191 **/
192static void e1000e_dump(struct e1000_adapter *adapter)
193{
194 struct net_device *netdev = adapter->netdev;
195 struct e1000_hw *hw = &adapter->hw;
196 struct e1000_reg_info *reginfo;
197 struct e1000_ring *tx_ring = adapter->tx_ring;
198 struct e1000_tx_desc *tx_desc;
199 struct my_u0 {
200 __le64 a;
201 __le64 b;
202 } *u0;
203 struct e1000_buffer *buffer_info;
204 struct e1000_ring *rx_ring = adapter->rx_ring;
205 union e1000_rx_desc_packet_split *rx_desc_ps;
206 union e1000_rx_desc_extended *rx_desc;
207 struct my_u1 {
208 __le64 a;
209 __le64 b;
210 __le64 c;
211 __le64 d;
212 } *u1;
213 u32 staterr;
214 int i = 0;
215
216 if (!netif_msg_hw(adapter))
217 return;
218
219 /* Print netdevice Info */
220 if (netdev) {
221 dev_info(&adapter->pdev->dev, "Net device Info\n");
222 pr_info("Device Name state trans_start\n");
223 pr_info("%-15s %016lX %016lX\n", netdev->name,
224 netdev->state, dev_trans_start(netdev));
225 }
226
227 /* Print Registers */
228 dev_info(&adapter->pdev->dev, "Register Dump\n");
229 pr_info(" Register Name Value\n");
230 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
231 reginfo->name; reginfo++) {
232 e1000_regdump(hw, reginfo);
233 }
234
235 /* Print Tx Ring Summary */
236 if (!netdev || !netif_running(netdev))
237 return;
238
239 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
240 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
241 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
242 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
243 0, tx_ring->next_to_use, tx_ring->next_to_clean,
244 (unsigned long long)buffer_info->dma,
245 buffer_info->length,
246 buffer_info->next_to_watch,
247 (unsigned long long)buffer_info->time_stamp);
248
249 /* Print Tx Ring */
250 if (!netif_msg_tx_done(adapter))
251 goto rx_ring_summary;
252
253 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
254
255 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
256 *
257 * Legacy Transmit Descriptor
258 * +--------------------------------------------------------------+
259 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
260 * +--------------------------------------------------------------+
261 * 8 | Special | CSS | Status | CMD | CSO | Length |
262 * +--------------------------------------------------------------+
263 * 63 48 47 36 35 32 31 24 23 16 15 0
264 *
265 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
266 * 63 48 47 40 39 32 31 16 15 8 7 0
267 * +----------------------------------------------------------------+
268 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
269 * +----------------------------------------------------------------+
270 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
271 * +----------------------------------------------------------------+
272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
273 *
274 * Extended Data Descriptor (DTYP=0x1)
275 * +----------------------------------------------------------------+
276 * 0 | Buffer Address [63:0] |
277 * +----------------------------------------------------------------+
278 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
279 * +----------------------------------------------------------------+
280 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
281 */
282 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
283 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
284 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
285 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
286 const char *next_desc;
287 tx_desc = E1000_TX_DESC(*tx_ring, i);
288 buffer_info = &tx_ring->buffer_info[i];
289 u0 = (struct my_u0 *)tx_desc;
290 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
291 next_desc = " NTC/U";
292 else if (i == tx_ring->next_to_use)
293 next_desc = " NTU";
294 else if (i == tx_ring->next_to_clean)
295 next_desc = " NTC";
296 else
297 next_desc = "";
298 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
299 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
300 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
301 i,
302 (unsigned long long)le64_to_cpu(u0->a),
303 (unsigned long long)le64_to_cpu(u0->b),
304 (unsigned long long)buffer_info->dma,
305 buffer_info->length, buffer_info->next_to_watch,
306 (unsigned long long)buffer_info->time_stamp,
307 buffer_info->skb, next_desc);
308
309 if (netif_msg_pktdata(adapter) && buffer_info->skb)
310 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
311 16, 1, buffer_info->skb->data,
312 buffer_info->skb->len, true);
313 }
314
315 /* Print Rx Ring Summary */
316rx_ring_summary:
317 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
318 pr_info("Queue [NTU] [NTC]\n");
319 pr_info(" %5d %5X %5X\n",
320 0, rx_ring->next_to_use, rx_ring->next_to_clean);
321
322 /* Print Rx Ring */
323 if (!netif_msg_rx_status(adapter))
324 return;
325
326 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
327 switch (adapter->rx_ps_pages) {
328 case 1:
329 case 2:
330 case 3:
331 /* [Extended] Packet Split Receive Descriptor Format
332 *
333 * +-----------------------------------------------------+
334 * 0 | Buffer Address 0 [63:0] |
335 * +-----------------------------------------------------+
336 * 8 | Buffer Address 1 [63:0] |
337 * +-----------------------------------------------------+
338 * 16 | Buffer Address 2 [63:0] |
339 * +-----------------------------------------------------+
340 * 24 | Buffer Address 3 [63:0] |
341 * +-----------------------------------------------------+
342 */
343 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
344 /* [Extended] Receive Descriptor (Write-Back) Format
345 *
346 * 63 48 47 32 31 13 12 8 7 4 3 0
347 * +------------------------------------------------------+
348 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
349 * | Checksum | Ident | | Queue | | Type |
350 * +------------------------------------------------------+
351 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
352 * +------------------------------------------------------+
353 * 63 48 47 32 31 20 19 0
354 */
355 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
356 for (i = 0; i < rx_ring->count; i++) {
357 const char *next_desc;
358 buffer_info = &rx_ring->buffer_info[i];
359 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
360 u1 = (struct my_u1 *)rx_desc_ps;
361 staterr =
362 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
363
364 if (i == rx_ring->next_to_use)
365 next_desc = " NTU";
366 else if (i == rx_ring->next_to_clean)
367 next_desc = " NTC";
368 else
369 next_desc = "";
370
371 if (staterr & E1000_RXD_STAT_DD) {
372 /* Descriptor Done */
373 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
374 "RWB", i,
375 (unsigned long long)le64_to_cpu(u1->a),
376 (unsigned long long)le64_to_cpu(u1->b),
377 (unsigned long long)le64_to_cpu(u1->c),
378 (unsigned long long)le64_to_cpu(u1->d),
379 buffer_info->skb, next_desc);
380 } else {
381 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
382 "R ", i,
383 (unsigned long long)le64_to_cpu(u1->a),
384 (unsigned long long)le64_to_cpu(u1->b),
385 (unsigned long long)le64_to_cpu(u1->c),
386 (unsigned long long)le64_to_cpu(u1->d),
387 (unsigned long long)buffer_info->dma,
388 buffer_info->skb, next_desc);
389
390 if (netif_msg_pktdata(adapter))
391 e1000e_dump_ps_pages(adapter,
392 buffer_info);
393 }
394 }
395 break;
396 default:
397 case 0:
398 /* Extended Receive Descriptor (Read) Format
399 *
400 * +-----------------------------------------------------+
401 * 0 | Buffer Address [63:0] |
402 * +-----------------------------------------------------+
403 * 8 | Reserved |
404 * +-----------------------------------------------------+
405 */
406 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
407 /* Extended Receive Descriptor (Write-Back) Format
408 *
409 * 63 48 47 32 31 24 23 4 3 0
410 * +------------------------------------------------------+
411 * | RSS Hash | | | |
412 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
413 * | Packet | IP | | | Type |
414 * | Checksum | Ident | | | |
415 * +------------------------------------------------------+
416 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
417 * +------------------------------------------------------+
418 * 63 48 47 32 31 20 19 0
419 */
420 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
421
422 for (i = 0; i < rx_ring->count; i++) {
423 const char *next_desc;
424
425 buffer_info = &rx_ring->buffer_info[i];
426 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
427 u1 = (struct my_u1 *)rx_desc;
428 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
429
430 if (i == rx_ring->next_to_use)
431 next_desc = " NTU";
432 else if (i == rx_ring->next_to_clean)
433 next_desc = " NTC";
434 else
435 next_desc = "";
436
437 if (staterr & E1000_RXD_STAT_DD) {
438 /* Descriptor Done */
439 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
440 "RWB", i,
441 (unsigned long long)le64_to_cpu(u1->a),
442 (unsigned long long)le64_to_cpu(u1->b),
443 buffer_info->skb, next_desc);
444 } else {
445 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
446 "R ", i,
447 (unsigned long long)le64_to_cpu(u1->a),
448 (unsigned long long)le64_to_cpu(u1->b),
449 (unsigned long long)buffer_info->dma,
450 buffer_info->skb, next_desc);
451
452 if (netif_msg_pktdata(adapter) &&
453 buffer_info->skb)
454 print_hex_dump(KERN_INFO, "",
455 DUMP_PREFIX_ADDRESS, 16,
456 1,
457 buffer_info->skb->data,
458 adapter->rx_buffer_len,
459 true);
460 }
461 }
462 }
463}
464
465/**
466 * e1000_desc_unused - calculate if we have unused descriptors
467 * @ring: pointer to ring struct to perform calculation on
468 **/
469static int e1000_desc_unused(struct e1000_ring *ring)
470{
471 if (ring->next_to_clean > ring->next_to_use)
472 return ring->next_to_clean - ring->next_to_use - 1;
473
474 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
475}
476
477/**
478 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
479 * @adapter: board private structure
480 * @hwtstamps: time stamp structure to update
481 * @systim: unsigned 64bit system time value.
482 *
483 * Convert the system time value stored in the RX/TXSTMP registers into a
484 * hwtstamp which can be used by the upper level time stamping functions.
485 *
486 * The 'systim_lock' spinlock is used to protect the consistency of the
487 * system time value. This is needed because reading the 64 bit time
488 * value involves reading two 32 bit registers. The first read latches the
489 * value.
490 **/
491static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
492 struct skb_shared_hwtstamps *hwtstamps,
493 u64 systim)
494{
495 u64 ns;
496 unsigned long flags;
497
498 spin_lock_irqsave(&adapter->systim_lock, flags);
499 ns = timecounter_cyc2time(&adapter->tc, systim);
500 spin_unlock_irqrestore(&adapter->systim_lock, flags);
501
502 memset(hwtstamps, 0, sizeof(*hwtstamps));
503 hwtstamps->hwtstamp = ns_to_ktime(ns);
504}
505
506/**
507 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
508 * @adapter: board private structure
509 * @status: descriptor extended error and status field
510 * @skb: particular skb to include time stamp
511 *
512 * If the time stamp is valid, convert it into the timecounter ns value
513 * and store that result into the shhwtstamps structure which is passed
514 * up the network stack.
515 **/
516static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
517 struct sk_buff *skb)
518{
519 struct e1000_hw *hw = &adapter->hw;
520 u64 rxstmp;
521
522 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
523 !(status & E1000_RXDEXT_STATERR_TST) ||
524 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
525 return;
526
527 /* The Rx time stamp registers contain the time stamp. No other
528 * received packet will be time stamped until the Rx time stamp
529 * registers are read. Because only one packet can be time stamped
530 * at a time, the register values must belong to this packet and
531 * therefore none of the other additional attributes need to be
532 * compared.
533 */
534 rxstmp = (u64)er32(RXSTMPL);
535 rxstmp |= (u64)er32(RXSTMPH) << 32;
536 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
537
538 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
539}
540
541/**
542 * e1000_receive_skb - helper function to handle Rx indications
543 * @adapter: board private structure
544 * @netdev: pointer to netdev struct
545 * @staterr: descriptor extended error and status field as written by hardware
546 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
547 * @skb: pointer to sk_buff to be indicated to stack
548 **/
549static void e1000_receive_skb(struct e1000_adapter *adapter,
550 struct net_device *netdev, struct sk_buff *skb,
551 u32 staterr, __le16 vlan)
552{
553 u16 tag = le16_to_cpu(vlan);
554
555 e1000e_rx_hwtstamp(adapter, staterr, skb);
556
557 skb->protocol = eth_type_trans(skb, netdev);
558
559 if (staterr & E1000_RXD_STAT_VP)
560 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
561
562 napi_gro_receive(&adapter->napi, skb);
563}
564
565/**
566 * e1000_rx_checksum - Receive Checksum Offload
567 * @adapter: board private structure
568 * @status_err: receive descriptor status and error fields
569 * @skb: socket buffer with received data
570 **/
571static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
572 struct sk_buff *skb)
573{
574 u16 status = (u16)status_err;
575 u8 errors = (u8)(status_err >> 24);
576
577 skb_checksum_none_assert(skb);
578
579 /* Rx checksum disabled */
580 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
581 return;
582
583 /* Ignore Checksum bit is set */
584 if (status & E1000_RXD_STAT_IXSM)
585 return;
586
587 /* TCP/UDP checksum error bit or IP checksum error bit is set */
588 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
589 /* let the stack verify checksum errors */
590 adapter->hw_csum_err++;
591 return;
592 }
593
594 /* TCP/UDP Checksum has not been calculated */
595 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
596 return;
597
598 /* It must be a TCP or UDP packet with a valid checksum */
599 skb->ip_summed = CHECKSUM_UNNECESSARY;
600 adapter->hw_csum_good++;
601}
602
603static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
604{
605 struct e1000_adapter *adapter = rx_ring->adapter;
606 struct e1000_hw *hw = &adapter->hw;
607
608 __ew32_prepare(hw);
609 writel(i, rx_ring->tail);
610
611 if (unlikely(i != readl(rx_ring->tail))) {
612 u32 rctl = er32(RCTL);
613
614 ew32(RCTL, rctl & ~E1000_RCTL_EN);
615 e_err("ME firmware caused invalid RDT - resetting\n");
616 schedule_work(&adapter->reset_task);
617 }
618}
619
620static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
621{
622 struct e1000_adapter *adapter = tx_ring->adapter;
623 struct e1000_hw *hw = &adapter->hw;
624
625 __ew32_prepare(hw);
626 writel(i, tx_ring->tail);
627
628 if (unlikely(i != readl(tx_ring->tail))) {
629 u32 tctl = er32(TCTL);
630
631 ew32(TCTL, tctl & ~E1000_TCTL_EN);
632 e_err("ME firmware caused invalid TDT - resetting\n");
633 schedule_work(&adapter->reset_task);
634 }
635}
636
637/**
638 * e1000_alloc_rx_buffers - Replace used receive buffers
639 * @rx_ring: Rx descriptor ring
640 * @cleaned_count: number to reallocate
641 * @gfp: flags for allocation
642 **/
643static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
644 int cleaned_count, gfp_t gfp)
645{
646 struct e1000_adapter *adapter = rx_ring->adapter;
647 struct net_device *netdev = adapter->netdev;
648 struct pci_dev *pdev = adapter->pdev;
649 union e1000_rx_desc_extended *rx_desc;
650 struct e1000_buffer *buffer_info;
651 struct sk_buff *skb;
652 unsigned int i;
653 unsigned int bufsz = adapter->rx_buffer_len;
654
655 i = rx_ring->next_to_use;
656 buffer_info = &rx_ring->buffer_info[i];
657
658 while (cleaned_count--) {
659 skb = buffer_info->skb;
660 if (skb) {
661 skb_trim(skb, 0);
662 goto map_skb;
663 }
664
665 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
666 if (!skb) {
667 /* Better luck next round */
668 adapter->alloc_rx_buff_failed++;
669 break;
670 }
671
672 buffer_info->skb = skb;
673map_skb:
674 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
675 adapter->rx_buffer_len,
676 DMA_FROM_DEVICE);
677 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
678 dev_err(&pdev->dev, "Rx DMA map failed\n");
679 adapter->rx_dma_failed++;
680 break;
681 }
682
683 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
684 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
685
686 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
687 /* Force memory writes to complete before letting h/w
688 * know there are new descriptors to fetch. (Only
689 * applicable for weak-ordered memory model archs,
690 * such as IA-64).
691 */
692 wmb();
693 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
694 e1000e_update_rdt_wa(rx_ring, i);
695 else
696 writel(i, rx_ring->tail);
697 }
698 i++;
699 if (i == rx_ring->count)
700 i = 0;
701 buffer_info = &rx_ring->buffer_info[i];
702 }
703
704 rx_ring->next_to_use = i;
705}
706
707/**
708 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
709 * @rx_ring: Rx descriptor ring
710 * @cleaned_count: number to reallocate
711 * @gfp: flags for allocation
712 **/
713static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
714 int cleaned_count, gfp_t gfp)
715{
716 struct e1000_adapter *adapter = rx_ring->adapter;
717 struct net_device *netdev = adapter->netdev;
718 struct pci_dev *pdev = adapter->pdev;
719 union e1000_rx_desc_packet_split *rx_desc;
720 struct e1000_buffer *buffer_info;
721 struct e1000_ps_page *ps_page;
722 struct sk_buff *skb;
723 unsigned int i, j;
724
725 i = rx_ring->next_to_use;
726 buffer_info = &rx_ring->buffer_info[i];
727
728 while (cleaned_count--) {
729 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
730
731 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
732 ps_page = &buffer_info->ps_pages[j];
733 if (j >= adapter->rx_ps_pages) {
734 /* all unused desc entries get hw null ptr */
735 rx_desc->read.buffer_addr[j + 1] =
736 ~cpu_to_le64(0);
737 continue;
738 }
739 if (!ps_page->page) {
740 ps_page->page = alloc_page(gfp);
741 if (!ps_page->page) {
742 adapter->alloc_rx_buff_failed++;
743 goto no_buffers;
744 }
745 ps_page->dma = dma_map_page(&pdev->dev,
746 ps_page->page,
747 0, PAGE_SIZE,
748 DMA_FROM_DEVICE);
749 if (dma_mapping_error(&pdev->dev,
750 ps_page->dma)) {
751 dev_err(&adapter->pdev->dev,
752 "Rx DMA page map failed\n");
753 adapter->rx_dma_failed++;
754 goto no_buffers;
755 }
756 }
757 /* Refresh the desc even if buffer_addrs
758 * didn't change because each write-back
759 * erases this info.
760 */
761 rx_desc->read.buffer_addr[j + 1] =
762 cpu_to_le64(ps_page->dma);
763 }
764
765 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
766 gfp);
767
768 if (!skb) {
769 adapter->alloc_rx_buff_failed++;
770 break;
771 }
772
773 buffer_info->skb = skb;
774 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
775 adapter->rx_ps_bsize0,
776 DMA_FROM_DEVICE);
777 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
778 dev_err(&pdev->dev, "Rx DMA map failed\n");
779 adapter->rx_dma_failed++;
780 /* cleanup skb */
781 dev_kfree_skb_any(skb);
782 buffer_info->skb = NULL;
783 break;
784 }
785
786 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
787
788 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
789 /* Force memory writes to complete before letting h/w
790 * know there are new descriptors to fetch. (Only
791 * applicable for weak-ordered memory model archs,
792 * such as IA-64).
793 */
794 wmb();
795 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
796 e1000e_update_rdt_wa(rx_ring, i << 1);
797 else
798 writel(i << 1, rx_ring->tail);
799 }
800
801 i++;
802 if (i == rx_ring->count)
803 i = 0;
804 buffer_info = &rx_ring->buffer_info[i];
805 }
806
807no_buffers:
808 rx_ring->next_to_use = i;
809}
810
811/**
812 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
813 * @rx_ring: Rx descriptor ring
814 * @cleaned_count: number of buffers to allocate this pass
815 * @gfp: flags for allocation
816 **/
817
818static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
819 int cleaned_count, gfp_t gfp)
820{
821 struct e1000_adapter *adapter = rx_ring->adapter;
822 struct net_device *netdev = adapter->netdev;
823 struct pci_dev *pdev = adapter->pdev;
824 union e1000_rx_desc_extended *rx_desc;
825 struct e1000_buffer *buffer_info;
826 struct sk_buff *skb;
827 unsigned int i;
828 unsigned int bufsz = 256 - 16; /* for skb_reserve */
829
830 i = rx_ring->next_to_use;
831 buffer_info = &rx_ring->buffer_info[i];
832
833 while (cleaned_count--) {
834 skb = buffer_info->skb;
835 if (skb) {
836 skb_trim(skb, 0);
837 goto check_page;
838 }
839
840 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
841 if (unlikely(!skb)) {
842 /* Better luck next round */
843 adapter->alloc_rx_buff_failed++;
844 break;
845 }
846
847 buffer_info->skb = skb;
848check_page:
849 /* allocate a new page if necessary */
850 if (!buffer_info->page) {
851 buffer_info->page = alloc_page(gfp);
852 if (unlikely(!buffer_info->page)) {
853 adapter->alloc_rx_buff_failed++;
854 break;
855 }
856 }
857
858 if (!buffer_info->dma) {
859 buffer_info->dma = dma_map_page(&pdev->dev,
860 buffer_info->page, 0,
861 PAGE_SIZE,
862 DMA_FROM_DEVICE);
863 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
864 adapter->alloc_rx_buff_failed++;
865 break;
866 }
867 }
868
869 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
870 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
871
872 if (unlikely(++i == rx_ring->count))
873 i = 0;
874 buffer_info = &rx_ring->buffer_info[i];
875 }
876
877 if (likely(rx_ring->next_to_use != i)) {
878 rx_ring->next_to_use = i;
879 if (unlikely(i-- == 0))
880 i = (rx_ring->count - 1);
881
882 /* Force memory writes to complete before letting h/w
883 * know there are new descriptors to fetch. (Only
884 * applicable for weak-ordered memory model archs,
885 * such as IA-64).
886 */
887 wmb();
888 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
889 e1000e_update_rdt_wa(rx_ring, i);
890 else
891 writel(i, rx_ring->tail);
892 }
893}
894
895static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
896 struct sk_buff *skb)
897{
898 if (netdev->features & NETIF_F_RXHASH)
899 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
900}
901
902/**
903 * e1000_clean_rx_irq - Send received data up the network stack
904 * @rx_ring: Rx descriptor ring
905 * @work_done: output parameter for indicating completed work
906 * @work_to_do: how many packets we can clean
907 *
908 * the return value indicates whether actual cleaning was done, there
909 * is no guarantee that everything was cleaned
910 **/
911static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
912 int work_to_do)
913{
914 struct e1000_adapter *adapter = rx_ring->adapter;
915 struct net_device *netdev = adapter->netdev;
916 struct pci_dev *pdev = adapter->pdev;
917 struct e1000_hw *hw = &adapter->hw;
918 union e1000_rx_desc_extended *rx_desc, *next_rxd;
919 struct e1000_buffer *buffer_info, *next_buffer;
920 u32 length, staterr;
921 unsigned int i;
922 int cleaned_count = 0;
923 bool cleaned = false;
924 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
925
926 i = rx_ring->next_to_clean;
927 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
928 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
929 buffer_info = &rx_ring->buffer_info[i];
930
931 while (staterr & E1000_RXD_STAT_DD) {
932 struct sk_buff *skb;
933
934 if (*work_done >= work_to_do)
935 break;
936 (*work_done)++;
937 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
938
939 skb = buffer_info->skb;
940 buffer_info->skb = NULL;
941
942 prefetch(skb->data - NET_IP_ALIGN);
943
944 i++;
945 if (i == rx_ring->count)
946 i = 0;
947 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
948 prefetch(next_rxd);
949
950 next_buffer = &rx_ring->buffer_info[i];
951
952 cleaned = true;
953 cleaned_count++;
954 dma_unmap_single(&pdev->dev, buffer_info->dma,
955 adapter->rx_buffer_len, DMA_FROM_DEVICE);
956 buffer_info->dma = 0;
957
958 length = le16_to_cpu(rx_desc->wb.upper.length);
959
960 /* !EOP means multiple descriptors were used to store a single
961 * packet, if that's the case we need to toss it. In fact, we
962 * need to toss every packet with the EOP bit clear and the
963 * next frame that _does_ have the EOP bit set, as it is by
964 * definition only a frame fragment
965 */
966 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
967 adapter->flags2 |= FLAG2_IS_DISCARDING;
968
969 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
970 /* All receives must fit into a single buffer */
971 e_dbg("Receive packet consumed multiple buffers\n");
972 /* recycle */
973 buffer_info->skb = skb;
974 if (staterr & E1000_RXD_STAT_EOP)
975 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
976 goto next_desc;
977 }
978
979 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
980 !(netdev->features & NETIF_F_RXALL))) {
981 /* recycle */
982 buffer_info->skb = skb;
983 goto next_desc;
984 }
985
986 /* adjust length to remove Ethernet CRC */
987 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
988 /* If configured to store CRC, don't subtract FCS,
989 * but keep the FCS bytes out of the total_rx_bytes
990 * counter
991 */
992 if (netdev->features & NETIF_F_RXFCS)
993 total_rx_bytes -= 4;
994 else
995 length -= 4;
996 }
997
998 total_rx_bytes += length;
999 total_rx_packets++;
1000
1001 /* code added for copybreak, this should improve
1002 * performance for small packets with large amounts
1003 * of reassembly being done in the stack
1004 */
1005 if (length < copybreak) {
1006 struct sk_buff *new_skb =
1007 napi_alloc_skb(&adapter->napi, length);
1008 if (new_skb) {
1009 skb_copy_to_linear_data_offset(new_skb,
1010 -NET_IP_ALIGN,
1011 (skb->data -
1012 NET_IP_ALIGN),
1013 (length +
1014 NET_IP_ALIGN));
1015 /* save the skb in buffer_info as good */
1016 buffer_info->skb = skb;
1017 skb = new_skb;
1018 }
1019 /* else just continue with the old one */
1020 }
1021 /* end copybreak code */
1022 skb_put(skb, length);
1023
1024 /* Receive Checksum Offload */
1025 e1000_rx_checksum(adapter, staterr, skb);
1026
1027 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1028
1029 e1000_receive_skb(adapter, netdev, skb, staterr,
1030 rx_desc->wb.upper.vlan);
1031
1032next_desc:
1033 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1034
1035 /* return some buffers to hardware, one at a time is too slow */
1036 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1037 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1038 GFP_ATOMIC);
1039 cleaned_count = 0;
1040 }
1041
1042 /* use prefetched values */
1043 rx_desc = next_rxd;
1044 buffer_info = next_buffer;
1045
1046 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1047 }
1048 rx_ring->next_to_clean = i;
1049
1050 cleaned_count = e1000_desc_unused(rx_ring);
1051 if (cleaned_count)
1052 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1053
1054 adapter->total_rx_bytes += total_rx_bytes;
1055 adapter->total_rx_packets += total_rx_packets;
1056 return cleaned;
1057}
1058
1059static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1060 struct e1000_buffer *buffer_info,
1061 bool drop)
1062{
1063 struct e1000_adapter *adapter = tx_ring->adapter;
1064
1065 if (buffer_info->dma) {
1066 if (buffer_info->mapped_as_page)
1067 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1068 buffer_info->length, DMA_TO_DEVICE);
1069 else
1070 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1071 buffer_info->length, DMA_TO_DEVICE);
1072 buffer_info->dma = 0;
1073 }
1074 if (buffer_info->skb) {
1075 if (drop)
1076 dev_kfree_skb_any(buffer_info->skb);
1077 else
1078 dev_consume_skb_any(buffer_info->skb);
1079 buffer_info->skb = NULL;
1080 }
1081 buffer_info->time_stamp = 0;
1082}
1083
1084static void e1000_print_hw_hang(struct work_struct *work)
1085{
1086 struct e1000_adapter *adapter = container_of(work,
1087 struct e1000_adapter,
1088 print_hang_task);
1089 struct net_device *netdev = adapter->netdev;
1090 struct e1000_ring *tx_ring = adapter->tx_ring;
1091 unsigned int i = tx_ring->next_to_clean;
1092 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1093 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
1094 struct e1000_hw *hw = &adapter->hw;
1095 u16 phy_status, phy_1000t_status, phy_ext_status;
1096 u16 pci_status;
1097
1098 if (test_bit(__E1000_DOWN, &adapter->state))
1099 return;
1100
1101 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
1102 /* May be block on write-back, flush and detect again
1103 * flush pending descriptor writebacks to memory
1104 */
1105 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1106 /* execute the writes immediately */
1107 e1e_flush();
1108 /* Due to rare timing issues, write to TIDV again to ensure
1109 * the write is successful
1110 */
1111 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1112 /* execute the writes immediately */
1113 e1e_flush();
1114 adapter->tx_hang_recheck = true;
1115 return;
1116 }
1117 adapter->tx_hang_recheck = false;
1118
1119 if (er32(TDH(0)) == er32(TDT(0))) {
1120 e_dbg("false hang detected, ignoring\n");
1121 return;
1122 }
1123
1124 /* Real hang detected */
1125 netif_stop_queue(netdev);
1126
1127 e1e_rphy(hw, MII_BMSR, &phy_status);
1128 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1129 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
1130
1131 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1132
1133 /* detected Hardware unit hang */
1134 e_err("Detected Hardware Unit Hang:\n"
1135 " TDH <%x>\n"
1136 " TDT <%x>\n"
1137 " next_to_use <%x>\n"
1138 " next_to_clean <%x>\n"
1139 "buffer_info[next_to_clean]:\n"
1140 " time_stamp <%lx>\n"
1141 " next_to_watch <%x>\n"
1142 " jiffies <%lx>\n"
1143 " next_to_watch.status <%x>\n"
1144 "MAC Status <%x>\n"
1145 "PHY Status <%x>\n"
1146 "PHY 1000BASE-T Status <%x>\n"
1147 "PHY Extended Status <%x>\n"
1148 "PCI Status <%x>\n",
1149 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1150 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1151 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1152 phy_status, phy_1000t_status, phy_ext_status, pci_status);
1153
1154 e1000e_dump(adapter);
1155
1156 /* Suggest workaround for known h/w issue */
1157 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1158 e_err("Try turning off Tx pause (flow control) via ethtool\n");
1159}
1160
1161/**
1162 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1163 * @work: pointer to work struct
1164 *
1165 * This work function polls the TSYNCTXCTL valid bit to determine when a
1166 * timestamp has been taken for the current stored skb. The timestamp must
1167 * be for this skb because only one such packet is allowed in the queue.
1168 */
1169static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1170{
1171 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1172 tx_hwtstamp_work);
1173 struct e1000_hw *hw = &adapter->hw;
1174
1175 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1176 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
1177 struct skb_shared_hwtstamps shhwtstamps;
1178 u64 txstmp;
1179
1180 txstmp = er32(TXSTMPL);
1181 txstmp |= (u64)er32(TXSTMPH) << 32;
1182
1183 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1184
1185 /* Clear the global tx_hwtstamp_skb pointer and force writes
1186 * prior to notifying the stack of a Tx timestamp.
1187 */
1188 adapter->tx_hwtstamp_skb = NULL;
1189 wmb(); /* force write prior to skb_tstamp_tx */
1190
1191 skb_tstamp_tx(skb, &shhwtstamps);
1192 dev_consume_skb_any(skb);
1193 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1194 + adapter->tx_timeout_factor * HZ)) {
1195 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1196 adapter->tx_hwtstamp_skb = NULL;
1197 adapter->tx_hwtstamp_timeouts++;
1198 e_warn("clearing Tx timestamp hang\n");
1199 } else {
1200 /* reschedule to check later */
1201 schedule_work(&adapter->tx_hwtstamp_work);
1202 }
1203}
1204
1205/**
1206 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1207 * @tx_ring: Tx descriptor ring
1208 *
1209 * the return value indicates whether actual cleaning was done, there
1210 * is no guarantee that everything was cleaned
1211 **/
1212static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
1213{
1214 struct e1000_adapter *adapter = tx_ring->adapter;
1215 struct net_device *netdev = adapter->netdev;
1216 struct e1000_hw *hw = &adapter->hw;
1217 struct e1000_tx_desc *tx_desc, *eop_desc;
1218 struct e1000_buffer *buffer_info;
1219 unsigned int i, eop;
1220 unsigned int count = 0;
1221 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
1222 unsigned int bytes_compl = 0, pkts_compl = 0;
1223
1224 i = tx_ring->next_to_clean;
1225 eop = tx_ring->buffer_info[i].next_to_watch;
1226 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1227
1228 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1229 (count < tx_ring->count)) {
1230 bool cleaned = false;
1231
1232 dma_rmb(); /* read buffer_info after eop_desc */
1233 for (; !cleaned; count++) {
1234 tx_desc = E1000_TX_DESC(*tx_ring, i);
1235 buffer_info = &tx_ring->buffer_info[i];
1236 cleaned = (i == eop);
1237
1238 if (cleaned) {
1239 total_tx_packets += buffer_info->segs;
1240 total_tx_bytes += buffer_info->bytecount;
1241 if (buffer_info->skb) {
1242 bytes_compl += buffer_info->skb->len;
1243 pkts_compl++;
1244 }
1245 }
1246
1247 e1000_put_txbuf(tx_ring, buffer_info, false);
1248 tx_desc->upper.data = 0;
1249
1250 i++;
1251 if (i == tx_ring->count)
1252 i = 0;
1253 }
1254
1255 if (i == tx_ring->next_to_use)
1256 break;
1257 eop = tx_ring->buffer_info[i].next_to_watch;
1258 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1259 }
1260
1261 tx_ring->next_to_clean = i;
1262
1263 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1264
1265#define TX_WAKE_THRESHOLD 32
1266 if (count && netif_carrier_ok(netdev) &&
1267 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
1268 /* Make sure that anybody stopping the queue after this
1269 * sees the new next_to_clean.
1270 */
1271 smp_mb();
1272
1273 if (netif_queue_stopped(netdev) &&
1274 !(test_bit(__E1000_DOWN, &adapter->state))) {
1275 netif_wake_queue(netdev);
1276 ++adapter->restart_queue;
1277 }
1278 }
1279
1280 if (adapter->detect_tx_hung) {
1281 /* Detect a transmit hang in hardware, this serializes the
1282 * check with the clearing of time_stamp and movement of i
1283 */
1284 adapter->detect_tx_hung = false;
1285 if (tx_ring->buffer_info[i].time_stamp &&
1286 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
1287 + (adapter->tx_timeout_factor * HZ)) &&
1288 !(er32(STATUS) & E1000_STATUS_TXOFF))
1289 schedule_work(&adapter->print_hang_task);
1290 else
1291 adapter->tx_hang_recheck = false;
1292 }
1293 adapter->total_tx_bytes += total_tx_bytes;
1294 adapter->total_tx_packets += total_tx_packets;
1295 return count < tx_ring->count;
1296}
1297
1298/**
1299 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1300 * @rx_ring: Rx descriptor ring
1301 * @work_done: output parameter for indicating completed work
1302 * @work_to_do: how many packets we can clean
1303 *
1304 * the return value indicates whether actual cleaning was done, there
1305 * is no guarantee that everything was cleaned
1306 **/
1307static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1308 int work_to_do)
1309{
1310 struct e1000_adapter *adapter = rx_ring->adapter;
1311 struct e1000_hw *hw = &adapter->hw;
1312 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1313 struct net_device *netdev = adapter->netdev;
1314 struct pci_dev *pdev = adapter->pdev;
1315 struct e1000_buffer *buffer_info, *next_buffer;
1316 struct e1000_ps_page *ps_page;
1317 struct sk_buff *skb;
1318 unsigned int i, j;
1319 u32 length, staterr;
1320 int cleaned_count = 0;
1321 bool cleaned = false;
1322 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1323
1324 i = rx_ring->next_to_clean;
1325 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1326 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1327 buffer_info = &rx_ring->buffer_info[i];
1328
1329 while (staterr & E1000_RXD_STAT_DD) {
1330 if (*work_done >= work_to_do)
1331 break;
1332 (*work_done)++;
1333 skb = buffer_info->skb;
1334 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1335
1336 /* in the packet split case this is header only */
1337 prefetch(skb->data - NET_IP_ALIGN);
1338
1339 i++;
1340 if (i == rx_ring->count)
1341 i = 0;
1342 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1343 prefetch(next_rxd);
1344
1345 next_buffer = &rx_ring->buffer_info[i];
1346
1347 cleaned = true;
1348 cleaned_count++;
1349 dma_unmap_single(&pdev->dev, buffer_info->dma,
1350 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
1351 buffer_info->dma = 0;
1352
1353 /* see !EOP comment in other Rx routine */
1354 if (!(staterr & E1000_RXD_STAT_EOP))
1355 adapter->flags2 |= FLAG2_IS_DISCARDING;
1356
1357 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
1358 e_dbg("Packet Split buffers didn't pick up the full packet\n");
1359 dev_kfree_skb_irq(skb);
1360 if (staterr & E1000_RXD_STAT_EOP)
1361 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1362 goto next_desc;
1363 }
1364
1365 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1366 !(netdev->features & NETIF_F_RXALL))) {
1367 dev_kfree_skb_irq(skb);
1368 goto next_desc;
1369 }
1370
1371 length = le16_to_cpu(rx_desc->wb.middle.length0);
1372
1373 if (!length) {
1374 e_dbg("Last part of the packet spanning multiple descriptors\n");
1375 dev_kfree_skb_irq(skb);
1376 goto next_desc;
1377 }
1378
1379 /* Good Receive */
1380 skb_put(skb, length);
1381
1382 {
1383 /* this looks ugly, but it seems compiler issues make
1384 * it more efficient than reusing j
1385 */
1386 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1387
1388 /* page alloc/put takes too long and effects small
1389 * packet throughput, so unsplit small packets and
1390 * save the alloc/put only valid in softirq (napi)
1391 * context to call kmap_*
1392 */
1393 if (l1 && (l1 <= copybreak) &&
1394 ((length + l1) <= adapter->rx_ps_bsize0)) {
1395 u8 *vaddr;
1396
1397 ps_page = &buffer_info->ps_pages[0];
1398
1399 /* there is no documentation about how to call
1400 * kmap_atomic, so we can't hold the mapping
1401 * very long
1402 */
1403 dma_sync_single_for_cpu(&pdev->dev,
1404 ps_page->dma,
1405 PAGE_SIZE,
1406 DMA_FROM_DEVICE);
1407 vaddr = kmap_atomic(ps_page->page);
1408 memcpy(skb_tail_pointer(skb), vaddr, l1);
1409 kunmap_atomic(vaddr);
1410 dma_sync_single_for_device(&pdev->dev,
1411 ps_page->dma,
1412 PAGE_SIZE,
1413 DMA_FROM_DEVICE);
1414
1415 /* remove the CRC */
1416 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1417 if (!(netdev->features & NETIF_F_RXFCS))
1418 l1 -= 4;
1419 }
1420
1421 skb_put(skb, l1);
1422 goto copydone;
1423 } /* if */
1424 }
1425
1426 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1427 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1428 if (!length)
1429 break;
1430
1431 ps_page = &buffer_info->ps_pages[j];
1432 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1433 DMA_FROM_DEVICE);
1434 ps_page->dma = 0;
1435 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1436 ps_page->page = NULL;
1437 skb->len += length;
1438 skb->data_len += length;
1439 skb->truesize += PAGE_SIZE;
1440 }
1441
1442 /* strip the ethernet crc, problem is we're using pages now so
1443 * this whole operation can get a little cpu intensive
1444 */
1445 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1446 if (!(netdev->features & NETIF_F_RXFCS))
1447 pskb_trim(skb, skb->len - 4);
1448 }
1449
1450copydone:
1451 total_rx_bytes += skb->len;
1452 total_rx_packets++;
1453
1454 e1000_rx_checksum(adapter, staterr, skb);
1455
1456 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1457
1458 if (rx_desc->wb.upper.header_status &
1459 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1460 adapter->rx_hdr_split++;
1461
1462 e1000_receive_skb(adapter, netdev, skb, staterr,
1463 rx_desc->wb.middle.vlan);
1464
1465next_desc:
1466 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1467 buffer_info->skb = NULL;
1468
1469 /* return some buffers to hardware, one at a time is too slow */
1470 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
1471 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1472 GFP_ATOMIC);
1473 cleaned_count = 0;
1474 }
1475
1476 /* use prefetched values */
1477 rx_desc = next_rxd;
1478 buffer_info = next_buffer;
1479
1480 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1481 }
1482 rx_ring->next_to_clean = i;
1483
1484 cleaned_count = e1000_desc_unused(rx_ring);
1485 if (cleaned_count)
1486 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1487
1488 adapter->total_rx_bytes += total_rx_bytes;
1489 adapter->total_rx_packets += total_rx_packets;
1490 return cleaned;
1491}
1492
1493static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1494 u16 length)
1495{
1496 bi->page = NULL;
1497 skb->len += length;
1498 skb->data_len += length;
1499 skb->truesize += PAGE_SIZE;
1500}
1501
1502/**
1503 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1504 * @rx_ring: Rx descriptor ring
1505 * @work_done: output parameter for indicating completed work
1506 * @work_to_do: how many packets we can clean
1507 *
1508 * the return value indicates whether actual cleaning was done, there
1509 * is no guarantee that everything was cleaned
1510 **/
1511static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1512 int work_to_do)
1513{
1514 struct e1000_adapter *adapter = rx_ring->adapter;
1515 struct net_device *netdev = adapter->netdev;
1516 struct pci_dev *pdev = adapter->pdev;
1517 union e1000_rx_desc_extended *rx_desc, *next_rxd;
1518 struct e1000_buffer *buffer_info, *next_buffer;
1519 u32 length, staterr;
1520 unsigned int i;
1521 int cleaned_count = 0;
1522 bool cleaned = false;
1523 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1524 struct skb_shared_info *shinfo;
1525
1526 i = rx_ring->next_to_clean;
1527 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1528 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1529 buffer_info = &rx_ring->buffer_info[i];
1530
1531 while (staterr & E1000_RXD_STAT_DD) {
1532 struct sk_buff *skb;
1533
1534 if (*work_done >= work_to_do)
1535 break;
1536 (*work_done)++;
1537 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
1538
1539 skb = buffer_info->skb;
1540 buffer_info->skb = NULL;
1541
1542 ++i;
1543 if (i == rx_ring->count)
1544 i = 0;
1545 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
1546 prefetch(next_rxd);
1547
1548 next_buffer = &rx_ring->buffer_info[i];
1549
1550 cleaned = true;
1551 cleaned_count++;
1552 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1553 DMA_FROM_DEVICE);
1554 buffer_info->dma = 0;
1555
1556 length = le16_to_cpu(rx_desc->wb.upper.length);
1557
1558 /* errors is only valid for DD + EOP descriptors */
1559 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1560 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1561 !(netdev->features & NETIF_F_RXALL)))) {
1562 /* recycle both page and skb */
1563 buffer_info->skb = skb;
1564 /* an error means any chain goes out the window too */
1565 if (rx_ring->rx_skb_top)
1566 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1567 rx_ring->rx_skb_top = NULL;
1568 goto next_desc;
1569 }
1570#define rxtop (rx_ring->rx_skb_top)
1571 if (!(staterr & E1000_RXD_STAT_EOP)) {
1572 /* this descriptor is only the beginning (or middle) */
1573 if (!rxtop) {
1574 /* this is the beginning of a chain */
1575 rxtop = skb;
1576 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1577 0, length);
1578 } else {
1579 /* this is the middle of a chain */
1580 shinfo = skb_shinfo(rxtop);
1581 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1582 buffer_info->page, 0,
1583 length);
1584 /* re-use the skb, only consumed the page */
1585 buffer_info->skb = skb;
1586 }
1587 e1000_consume_page(buffer_info, rxtop, length);
1588 goto next_desc;
1589 } else {
1590 if (rxtop) {
1591 /* end of the chain */
1592 shinfo = skb_shinfo(rxtop);
1593 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1594 buffer_info->page, 0,
1595 length);
1596 /* re-use the current skb, we only consumed the
1597 * page
1598 */
1599 buffer_info->skb = skb;
1600 skb = rxtop;
1601 rxtop = NULL;
1602 e1000_consume_page(buffer_info, skb, length);
1603 } else {
1604 /* no chain, got EOP, this buf is the packet
1605 * copybreak to save the put_page/alloc_page
1606 */
1607 if (length <= copybreak &&
1608 skb_tailroom(skb) >= length) {
1609 u8 *vaddr;
1610 vaddr = kmap_atomic(buffer_info->page);
1611 memcpy(skb_tail_pointer(skb), vaddr,
1612 length);
1613 kunmap_atomic(vaddr);
1614 /* re-use the page, so don't erase
1615 * buffer_info->page
1616 */
1617 skb_put(skb, length);
1618 } else {
1619 skb_fill_page_desc(skb, 0,
1620 buffer_info->page, 0,
1621 length);
1622 e1000_consume_page(buffer_info, skb,
1623 length);
1624 }
1625 }
1626 }
1627
1628 /* Receive Checksum Offload */
1629 e1000_rx_checksum(adapter, staterr, skb);
1630
1631 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1632
1633 /* probably a little skewed due to removing CRC */
1634 total_rx_bytes += skb->len;
1635 total_rx_packets++;
1636
1637 /* eth type trans needs skb->data to point to something */
1638 if (!pskb_may_pull(skb, ETH_HLEN)) {
1639 e_err("pskb_may_pull failed.\n");
1640 dev_kfree_skb_irq(skb);
1641 goto next_desc;
1642 }
1643
1644 e1000_receive_skb(adapter, netdev, skb, staterr,
1645 rx_desc->wb.upper.vlan);
1646
1647next_desc:
1648 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
1649
1650 /* return some buffers to hardware, one at a time is too slow */
1651 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
1652 adapter->alloc_rx_buf(rx_ring, cleaned_count,
1653 GFP_ATOMIC);
1654 cleaned_count = 0;
1655 }
1656
1657 /* use prefetched values */
1658 rx_desc = next_rxd;
1659 buffer_info = next_buffer;
1660
1661 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1662 }
1663 rx_ring->next_to_clean = i;
1664
1665 cleaned_count = e1000_desc_unused(rx_ring);
1666 if (cleaned_count)
1667 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
1668
1669 adapter->total_rx_bytes += total_rx_bytes;
1670 adapter->total_rx_packets += total_rx_packets;
1671 return cleaned;
1672}
1673
1674/**
1675 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1676 * @rx_ring: Rx descriptor ring
1677 **/
1678static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
1679{
1680 struct e1000_adapter *adapter = rx_ring->adapter;
1681 struct e1000_buffer *buffer_info;
1682 struct e1000_ps_page *ps_page;
1683 struct pci_dev *pdev = adapter->pdev;
1684 unsigned int i, j;
1685
1686 /* Free all the Rx ring sk_buffs */
1687 for (i = 0; i < rx_ring->count; i++) {
1688 buffer_info = &rx_ring->buffer_info[i];
1689 if (buffer_info->dma) {
1690 if (adapter->clean_rx == e1000_clean_rx_irq)
1691 dma_unmap_single(&pdev->dev, buffer_info->dma,
1692 adapter->rx_buffer_len,
1693 DMA_FROM_DEVICE);
1694 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
1695 dma_unmap_page(&pdev->dev, buffer_info->dma,
1696 PAGE_SIZE, DMA_FROM_DEVICE);
1697 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
1698 dma_unmap_single(&pdev->dev, buffer_info->dma,
1699 adapter->rx_ps_bsize0,
1700 DMA_FROM_DEVICE);
1701 buffer_info->dma = 0;
1702 }
1703
1704 if (buffer_info->page) {
1705 put_page(buffer_info->page);
1706 buffer_info->page = NULL;
1707 }
1708
1709 if (buffer_info->skb) {
1710 dev_kfree_skb(buffer_info->skb);
1711 buffer_info->skb = NULL;
1712 }
1713
1714 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1715 ps_page = &buffer_info->ps_pages[j];
1716 if (!ps_page->page)
1717 break;
1718 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1719 DMA_FROM_DEVICE);
1720 ps_page->dma = 0;
1721 put_page(ps_page->page);
1722 ps_page->page = NULL;
1723 }
1724 }
1725
1726 /* there also may be some cached data from a chained receive */
1727 if (rx_ring->rx_skb_top) {
1728 dev_kfree_skb(rx_ring->rx_skb_top);
1729 rx_ring->rx_skb_top = NULL;
1730 }
1731
1732 /* Zero out the descriptor ring */
1733 memset(rx_ring->desc, 0, rx_ring->size);
1734
1735 rx_ring->next_to_clean = 0;
1736 rx_ring->next_to_use = 0;
1737 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
1738}
1739
1740static void e1000e_downshift_workaround(struct work_struct *work)
1741{
1742 struct e1000_adapter *adapter = container_of(work,
1743 struct e1000_adapter,
1744 downshift_task);
1745
1746 if (test_bit(__E1000_DOWN, &adapter->state))
1747 return;
1748
1749 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1750}
1751
1752/**
1753 * e1000_intr_msi - Interrupt Handler
1754 * @irq: interrupt number
1755 * @data: pointer to a network interface device structure
1756 **/
1757static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
1758{
1759 struct net_device *netdev = data;
1760 struct e1000_adapter *adapter = netdev_priv(netdev);
1761 struct e1000_hw *hw = &adapter->hw;
1762 u32 icr = er32(ICR);
1763
1764 /* read ICR disables interrupts using IAM */
1765 if (icr & E1000_ICR_LSC) {
1766 hw->mac.get_link_status = true;
1767 /* ICH8 workaround-- Call gig speed drop workaround on cable
1768 * disconnect (LSC) before accessing any PHY registers
1769 */
1770 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1771 (!(er32(STATUS) & E1000_STATUS_LU)))
1772 schedule_work(&adapter->downshift_task);
1773
1774 /* 80003ES2LAN workaround-- For packet buffer work-around on
1775 * link down event; disable receives here in the ISR and reset
1776 * adapter in watchdog
1777 */
1778 if (netif_carrier_ok(netdev) &&
1779 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1780 /* disable receives */
1781 u32 rctl = er32(RCTL);
1782
1783 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1784 adapter->flags |= FLAG_RESTART_NOW;
1785 }
1786 /* guard against interrupt when we're going down */
1787 if (!test_bit(__E1000_DOWN, &adapter->state))
1788 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1789 }
1790
1791 /* Reset on uncorrectable ECC error */
1792 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1793 u32 pbeccsts = er32(PBECCSTS);
1794
1795 adapter->corr_errors +=
1796 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1797 adapter->uncorr_errors +=
1798 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1799 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1800
1801 /* Do the reset outside of interrupt context */
1802 schedule_work(&adapter->reset_task);
1803
1804 /* return immediately since reset is imminent */
1805 return IRQ_HANDLED;
1806 }
1807
1808 if (napi_schedule_prep(&adapter->napi)) {
1809 adapter->total_tx_bytes = 0;
1810 adapter->total_tx_packets = 0;
1811 adapter->total_rx_bytes = 0;
1812 adapter->total_rx_packets = 0;
1813 __napi_schedule(&adapter->napi);
1814 }
1815
1816 return IRQ_HANDLED;
1817}
1818
1819/**
1820 * e1000_intr - Interrupt Handler
1821 * @irq: interrupt number
1822 * @data: pointer to a network interface device structure
1823 **/
1824static irqreturn_t e1000_intr(int __always_unused irq, void *data)
1825{
1826 struct net_device *netdev = data;
1827 struct e1000_adapter *adapter = netdev_priv(netdev);
1828 struct e1000_hw *hw = &adapter->hw;
1829 u32 rctl, icr = er32(ICR);
1830
1831 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
1832 return IRQ_NONE; /* Not our interrupt */
1833
1834 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1835 * not set, then the adapter didn't send an interrupt
1836 */
1837 if (!(icr & E1000_ICR_INT_ASSERTED))
1838 return IRQ_NONE;
1839
1840 /* Interrupt Auto-Mask...upon reading ICR,
1841 * interrupts are masked. No need for the
1842 * IMC write
1843 */
1844
1845 if (icr & E1000_ICR_LSC) {
1846 hw->mac.get_link_status = true;
1847 /* ICH8 workaround-- Call gig speed drop workaround on cable
1848 * disconnect (LSC) before accessing any PHY registers
1849 */
1850 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1851 (!(er32(STATUS) & E1000_STATUS_LU)))
1852 schedule_work(&adapter->downshift_task);
1853
1854 /* 80003ES2LAN workaround--
1855 * For packet buffer work-around on link down event;
1856 * disable receives here in the ISR and
1857 * reset adapter in watchdog
1858 */
1859 if (netif_carrier_ok(netdev) &&
1860 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1861 /* disable receives */
1862 rctl = er32(RCTL);
1863 ew32(RCTL, rctl & ~E1000_RCTL_EN);
1864 adapter->flags |= FLAG_RESTART_NOW;
1865 }
1866 /* guard against interrupt when we're going down */
1867 if (!test_bit(__E1000_DOWN, &adapter->state))
1868 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1869 }
1870
1871 /* Reset on uncorrectable ECC error */
1872 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
1873 u32 pbeccsts = er32(PBECCSTS);
1874
1875 adapter->corr_errors +=
1876 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1877 adapter->uncorr_errors +=
1878 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1879 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1880
1881 /* Do the reset outside of interrupt context */
1882 schedule_work(&adapter->reset_task);
1883
1884 /* return immediately since reset is imminent */
1885 return IRQ_HANDLED;
1886 }
1887
1888 if (napi_schedule_prep(&adapter->napi)) {
1889 adapter->total_tx_bytes = 0;
1890 adapter->total_tx_packets = 0;
1891 adapter->total_rx_bytes = 0;
1892 adapter->total_rx_packets = 0;
1893 __napi_schedule(&adapter->napi);
1894 }
1895
1896 return IRQ_HANDLED;
1897}
1898
1899static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
1900{
1901 struct net_device *netdev = data;
1902 struct e1000_adapter *adapter = netdev_priv(netdev);
1903 struct e1000_hw *hw = &adapter->hw;
1904 u32 icr = er32(ICR);
1905
1906 if (icr & adapter->eiac_mask)
1907 ew32(ICS, (icr & adapter->eiac_mask));
1908
1909 if (icr & E1000_ICR_LSC) {
1910 hw->mac.get_link_status = true;
1911 /* guard against interrupt when we're going down */
1912 if (!test_bit(__E1000_DOWN, &adapter->state))
1913 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1914 }
1915
1916 if (!test_bit(__E1000_DOWN, &adapter->state))
1917 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
1918
1919 return IRQ_HANDLED;
1920}
1921
1922static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
1923{
1924 struct net_device *netdev = data;
1925 struct e1000_adapter *adapter = netdev_priv(netdev);
1926 struct e1000_hw *hw = &adapter->hw;
1927 struct e1000_ring *tx_ring = adapter->tx_ring;
1928
1929 adapter->total_tx_bytes = 0;
1930 adapter->total_tx_packets = 0;
1931
1932 if (!e1000_clean_tx_irq(tx_ring))
1933 /* Ring was not completely cleaned, so fire another interrupt */
1934 ew32(ICS, tx_ring->ims_val);
1935
1936 if (!test_bit(__E1000_DOWN, &adapter->state))
1937 ew32(IMS, adapter->tx_ring->ims_val);
1938
1939 return IRQ_HANDLED;
1940}
1941
1942static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
1943{
1944 struct net_device *netdev = data;
1945 struct e1000_adapter *adapter = netdev_priv(netdev);
1946 struct e1000_ring *rx_ring = adapter->rx_ring;
1947
1948 /* Write the ITR value calculated at the end of the
1949 * previous interrupt.
1950 */
1951 if (rx_ring->set_itr) {
1952 u32 itr = rx_ring->itr_val ?
1953 1000000000 / (rx_ring->itr_val * 256) : 0;
1954
1955 writel(itr, rx_ring->itr_register);
1956 rx_ring->set_itr = 0;
1957 }
1958
1959 if (napi_schedule_prep(&adapter->napi)) {
1960 adapter->total_rx_bytes = 0;
1961 adapter->total_rx_packets = 0;
1962 __napi_schedule(&adapter->napi);
1963 }
1964 return IRQ_HANDLED;
1965}
1966
1967/**
1968 * e1000_configure_msix - Configure MSI-X hardware
1969 * @adapter: board private structure
1970 *
1971 * e1000_configure_msix sets up the hardware to properly
1972 * generate MSI-X interrupts.
1973 **/
1974static void e1000_configure_msix(struct e1000_adapter *adapter)
1975{
1976 struct e1000_hw *hw = &adapter->hw;
1977 struct e1000_ring *rx_ring = adapter->rx_ring;
1978 struct e1000_ring *tx_ring = adapter->tx_ring;
1979 int vector = 0;
1980 u32 ctrl_ext, ivar = 0;
1981
1982 adapter->eiac_mask = 0;
1983
1984 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1985 if (hw->mac.type == e1000_82574) {
1986 u32 rfctl = er32(RFCTL);
1987
1988 rfctl |= E1000_RFCTL_ACK_DIS;
1989 ew32(RFCTL, rfctl);
1990 }
1991
1992 /* Configure Rx vector */
1993 rx_ring->ims_val = E1000_IMS_RXQ0;
1994 adapter->eiac_mask |= rx_ring->ims_val;
1995 if (rx_ring->itr_val)
1996 writel(1000000000 / (rx_ring->itr_val * 256),
1997 rx_ring->itr_register);
1998 else
1999 writel(1, rx_ring->itr_register);
2000 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
2001
2002 /* Configure Tx vector */
2003 tx_ring->ims_val = E1000_IMS_TXQ0;
2004 vector++;
2005 if (tx_ring->itr_val)
2006 writel(1000000000 / (tx_ring->itr_val * 256),
2007 tx_ring->itr_register);
2008 else
2009 writel(1, tx_ring->itr_register);
2010 adapter->eiac_mask |= tx_ring->ims_val;
2011 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2012
2013 /* set vector for Other Causes, e.g. link changes */
2014 vector++;
2015 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2016 if (rx_ring->itr_val)
2017 writel(1000000000 / (rx_ring->itr_val * 256),
2018 hw->hw_addr + E1000_EITR_82574(vector));
2019 else
2020 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2021
2022 /* Cause Tx interrupts on every write back */
2023 ivar |= BIT(31);
2024
2025 ew32(IVAR, ivar);
2026
2027 /* enable MSI-X PBA support */
2028 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2029 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
2030 ew32(CTRL_EXT, ctrl_ext);
2031 e1e_flush();
2032}
2033
2034void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2035{
2036 if (adapter->msix_entries) {
2037 pci_disable_msix(adapter->pdev);
2038 kfree(adapter->msix_entries);
2039 adapter->msix_entries = NULL;
2040 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2041 pci_disable_msi(adapter->pdev);
2042 adapter->flags &= ~FLAG_MSI_ENABLED;
2043 }
2044}
2045
2046/**
2047 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2048 * @adapter: board private structure
2049 *
2050 * Attempt to configure interrupts using the best available
2051 * capabilities of the hardware and kernel.
2052 **/
2053void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2054{
2055 int err;
2056 int i;
2057
2058 switch (adapter->int_mode) {
2059 case E1000E_INT_MODE_MSIX:
2060 if (adapter->flags & FLAG_HAS_MSIX) {
2061 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2062 adapter->msix_entries = kcalloc(adapter->num_vectors,
2063 sizeof(struct
2064 msix_entry),
2065 GFP_KERNEL);
2066 if (adapter->msix_entries) {
2067 struct e1000_adapter *a = adapter;
2068
2069 for (i = 0; i < adapter->num_vectors; i++)
2070 adapter->msix_entries[i].entry = i;
2071
2072 err = pci_enable_msix_range(a->pdev,
2073 a->msix_entries,
2074 a->num_vectors,
2075 a->num_vectors);
2076 if (err > 0)
2077 return;
2078 }
2079 /* MSI-X failed, so fall through and try MSI */
2080 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
2081 e1000e_reset_interrupt_capability(adapter);
2082 }
2083 adapter->int_mode = E1000E_INT_MODE_MSI;
2084 fallthrough;
2085 case E1000E_INT_MODE_MSI:
2086 if (!pci_enable_msi(adapter->pdev)) {
2087 adapter->flags |= FLAG_MSI_ENABLED;
2088 } else {
2089 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2090 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
2091 }
2092 fallthrough;
2093 case E1000E_INT_MODE_LEGACY:
2094 /* Don't do anything; this is the system default */
2095 break;
2096 }
2097
2098 /* store the number of vectors being used */
2099 adapter->num_vectors = 1;
2100}
2101
2102/**
2103 * e1000_request_msix - Initialize MSI-X interrupts
2104 * @adapter: board private structure
2105 *
2106 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2107 * kernel.
2108 **/
2109static int e1000_request_msix(struct e1000_adapter *adapter)
2110{
2111 struct net_device *netdev = adapter->netdev;
2112 int err = 0, vector = 0;
2113
2114 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2115 snprintf(adapter->rx_ring->name,
2116 sizeof(adapter->rx_ring->name) - 1,
2117 "%.14s-rx-0", netdev->name);
2118 else
2119 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2120 err = request_irq(adapter->msix_entries[vector].vector,
2121 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
2122 netdev);
2123 if (err)
2124 return err;
2125 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2126 E1000_EITR_82574(vector);
2127 adapter->rx_ring->itr_val = adapter->itr;
2128 vector++;
2129
2130 if (strlen(netdev->name) < (IFNAMSIZ - 5))
2131 snprintf(adapter->tx_ring->name,
2132 sizeof(adapter->tx_ring->name) - 1,
2133 "%.14s-tx-0", netdev->name);
2134 else
2135 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2136 err = request_irq(adapter->msix_entries[vector].vector,
2137 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
2138 netdev);
2139 if (err)
2140 return err;
2141 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2142 E1000_EITR_82574(vector);
2143 adapter->tx_ring->itr_val = adapter->itr;
2144 vector++;
2145
2146 err = request_irq(adapter->msix_entries[vector].vector,
2147 e1000_msix_other, 0, netdev->name, netdev);
2148 if (err)
2149 return err;
2150
2151 e1000_configure_msix(adapter);
2152
2153 return 0;
2154}
2155
2156/**
2157 * e1000_request_irq - initialize interrupts
2158 * @adapter: board private structure
2159 *
2160 * Attempts to configure interrupts using the best available
2161 * capabilities of the hardware and kernel.
2162 **/
2163static int e1000_request_irq(struct e1000_adapter *adapter)
2164{
2165 struct net_device *netdev = adapter->netdev;
2166 int err;
2167
2168 if (adapter->msix_entries) {
2169 err = e1000_request_msix(adapter);
2170 if (!err)
2171 return err;
2172 /* fall back to MSI */
2173 e1000e_reset_interrupt_capability(adapter);
2174 adapter->int_mode = E1000E_INT_MODE_MSI;
2175 e1000e_set_interrupt_capability(adapter);
2176 }
2177 if (adapter->flags & FLAG_MSI_ENABLED) {
2178 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
2179 netdev->name, netdev);
2180 if (!err)
2181 return err;
2182
2183 /* fall back to legacy interrupt */
2184 e1000e_reset_interrupt_capability(adapter);
2185 adapter->int_mode = E1000E_INT_MODE_LEGACY;
2186 }
2187
2188 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
2189 netdev->name, netdev);
2190 if (err)
2191 e_err("Unable to allocate interrupt, Error: %d\n", err);
2192
2193 return err;
2194}
2195
2196static void e1000_free_irq(struct e1000_adapter *adapter)
2197{
2198 struct net_device *netdev = adapter->netdev;
2199
2200 if (adapter->msix_entries) {
2201 int vector = 0;
2202
2203 free_irq(adapter->msix_entries[vector].vector, netdev);
2204 vector++;
2205
2206 free_irq(adapter->msix_entries[vector].vector, netdev);
2207 vector++;
2208
2209 /* Other Causes interrupt vector */
2210 free_irq(adapter->msix_entries[vector].vector, netdev);
2211 return;
2212 }
2213
2214 free_irq(adapter->pdev->irq, netdev);
2215}
2216
2217/**
2218 * e1000_irq_disable - Mask off interrupt generation on the NIC
2219 * @adapter: board private structure
2220 **/
2221static void e1000_irq_disable(struct e1000_adapter *adapter)
2222{
2223 struct e1000_hw *hw = &adapter->hw;
2224
2225 ew32(IMC, ~0);
2226 if (adapter->msix_entries)
2227 ew32(EIAC_82574, 0);
2228 e1e_flush();
2229
2230 if (adapter->msix_entries) {
2231 int i;
2232
2233 for (i = 0; i < adapter->num_vectors; i++)
2234 synchronize_irq(adapter->msix_entries[i].vector);
2235 } else {
2236 synchronize_irq(adapter->pdev->irq);
2237 }
2238}
2239
2240/**
2241 * e1000_irq_enable - Enable default interrupt generation settings
2242 * @adapter: board private structure
2243 **/
2244static void e1000_irq_enable(struct e1000_adapter *adapter)
2245{
2246 struct e1000_hw *hw = &adapter->hw;
2247
2248 if (adapter->msix_entries) {
2249 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2250 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2251 IMS_OTHER_MASK);
2252 } else if (hw->mac.type >= e1000_pch_lpt) {
2253 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
2254 } else {
2255 ew32(IMS, IMS_ENABLE_MASK);
2256 }
2257 e1e_flush();
2258}
2259
2260/**
2261 * e1000e_get_hw_control - get control of the h/w from f/w
2262 * @adapter: address of board private structure
2263 *
2264 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2265 * For ASF and Pass Through versions of f/w this means that
2266 * the driver is loaded. For AMT version (only with 82573)
2267 * of the f/w this means that the network i/f is open.
2268 **/
2269void e1000e_get_hw_control(struct e1000_adapter *adapter)
2270{
2271 struct e1000_hw *hw = &adapter->hw;
2272 u32 ctrl_ext;
2273 u32 swsm;
2274
2275 /* Let firmware know the driver has taken over */
2276 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2277 swsm = er32(SWSM);
2278 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2279 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2280 ctrl_ext = er32(CTRL_EXT);
2281 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2282 }
2283}
2284
2285/**
2286 * e1000e_release_hw_control - release control of the h/w to f/w
2287 * @adapter: address of board private structure
2288 *
2289 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2290 * For ASF and Pass Through versions of f/w this means that the
2291 * driver is no longer loaded. For AMT version (only with 82573) i
2292 * of the f/w this means that the network i/f is closed.
2293 *
2294 **/
2295void e1000e_release_hw_control(struct e1000_adapter *adapter)
2296{
2297 struct e1000_hw *hw = &adapter->hw;
2298 u32 ctrl_ext;
2299 u32 swsm;
2300
2301 /* Let firmware taken over control of h/w */
2302 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2303 swsm = er32(SWSM);
2304 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2305 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2306 ctrl_ext = er32(CTRL_EXT);
2307 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2308 }
2309}
2310
2311/**
2312 * e1000_alloc_ring_dma - allocate memory for a ring structure
2313 * @adapter: board private structure
2314 * @ring: ring struct for which to allocate dma
2315 **/
2316static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2317 struct e1000_ring *ring)
2318{
2319 struct pci_dev *pdev = adapter->pdev;
2320
2321 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2322 GFP_KERNEL);
2323 if (!ring->desc)
2324 return -ENOMEM;
2325
2326 return 0;
2327}
2328
2329/**
2330 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2331 * @tx_ring: Tx descriptor ring
2332 *
2333 * Return 0 on success, negative on failure
2334 **/
2335int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
2336{
2337 struct e1000_adapter *adapter = tx_ring->adapter;
2338 int err = -ENOMEM, size;
2339
2340 size = sizeof(struct e1000_buffer) * tx_ring->count;
2341 tx_ring->buffer_info = vzalloc(size);
2342 if (!tx_ring->buffer_info)
2343 goto err;
2344
2345 /* round up to nearest 4K */
2346 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2347 tx_ring->size = ALIGN(tx_ring->size, 4096);
2348
2349 err = e1000_alloc_ring_dma(adapter, tx_ring);
2350 if (err)
2351 goto err;
2352
2353 tx_ring->next_to_use = 0;
2354 tx_ring->next_to_clean = 0;
2355
2356 return 0;
2357err:
2358 vfree(tx_ring->buffer_info);
2359 e_err("Unable to allocate memory for the transmit descriptor ring\n");
2360 return err;
2361}
2362
2363/**
2364 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2365 * @rx_ring: Rx descriptor ring
2366 *
2367 * Returns 0 on success, negative on failure
2368 **/
2369int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
2370{
2371 struct e1000_adapter *adapter = rx_ring->adapter;
2372 struct e1000_buffer *buffer_info;
2373 int i, size, desc_len, err = -ENOMEM;
2374
2375 size = sizeof(struct e1000_buffer) * rx_ring->count;
2376 rx_ring->buffer_info = vzalloc(size);
2377 if (!rx_ring->buffer_info)
2378 goto err;
2379
2380 for (i = 0; i < rx_ring->count; i++) {
2381 buffer_info = &rx_ring->buffer_info[i];
2382 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2383 sizeof(struct e1000_ps_page),
2384 GFP_KERNEL);
2385 if (!buffer_info->ps_pages)
2386 goto err_pages;
2387 }
2388
2389 desc_len = sizeof(union e1000_rx_desc_packet_split);
2390
2391 /* Round up to nearest 4K */
2392 rx_ring->size = rx_ring->count * desc_len;
2393 rx_ring->size = ALIGN(rx_ring->size, 4096);
2394
2395 err = e1000_alloc_ring_dma(adapter, rx_ring);
2396 if (err)
2397 goto err_pages;
2398
2399 rx_ring->next_to_clean = 0;
2400 rx_ring->next_to_use = 0;
2401 rx_ring->rx_skb_top = NULL;
2402
2403 return 0;
2404
2405err_pages:
2406 for (i = 0; i < rx_ring->count; i++) {
2407 buffer_info = &rx_ring->buffer_info[i];
2408 kfree(buffer_info->ps_pages);
2409 }
2410err:
2411 vfree(rx_ring->buffer_info);
2412 e_err("Unable to allocate memory for the receive descriptor ring\n");
2413 return err;
2414}
2415
2416/**
2417 * e1000_clean_tx_ring - Free Tx Buffers
2418 * @tx_ring: Tx descriptor ring
2419 **/
2420static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
2421{
2422 struct e1000_adapter *adapter = tx_ring->adapter;
2423 struct e1000_buffer *buffer_info;
2424 unsigned long size;
2425 unsigned int i;
2426
2427 for (i = 0; i < tx_ring->count; i++) {
2428 buffer_info = &tx_ring->buffer_info[i];
2429 e1000_put_txbuf(tx_ring, buffer_info, false);
2430 }
2431
2432 netdev_reset_queue(adapter->netdev);
2433 size = sizeof(struct e1000_buffer) * tx_ring->count;
2434 memset(tx_ring->buffer_info, 0, size);
2435
2436 memset(tx_ring->desc, 0, tx_ring->size);
2437
2438 tx_ring->next_to_use = 0;
2439 tx_ring->next_to_clean = 0;
2440}
2441
2442/**
2443 * e1000e_free_tx_resources - Free Tx Resources per Queue
2444 * @tx_ring: Tx descriptor ring
2445 *
2446 * Free all transmit software resources
2447 **/
2448void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
2449{
2450 struct e1000_adapter *adapter = tx_ring->adapter;
2451 struct pci_dev *pdev = adapter->pdev;
2452
2453 e1000_clean_tx_ring(tx_ring);
2454
2455 vfree(tx_ring->buffer_info);
2456 tx_ring->buffer_info = NULL;
2457
2458 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2459 tx_ring->dma);
2460 tx_ring->desc = NULL;
2461}
2462
2463/**
2464 * e1000e_free_rx_resources - Free Rx Resources
2465 * @rx_ring: Rx descriptor ring
2466 *
2467 * Free all receive software resources
2468 **/
2469void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
2470{
2471 struct e1000_adapter *adapter = rx_ring->adapter;
2472 struct pci_dev *pdev = adapter->pdev;
2473 int i;
2474
2475 e1000_clean_rx_ring(rx_ring);
2476
2477 for (i = 0; i < rx_ring->count; i++)
2478 kfree(rx_ring->buffer_info[i].ps_pages);
2479
2480 vfree(rx_ring->buffer_info);
2481 rx_ring->buffer_info = NULL;
2482
2483 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2484 rx_ring->dma);
2485 rx_ring->desc = NULL;
2486}
2487
2488/**
2489 * e1000_update_itr - update the dynamic ITR value based on statistics
2490 * @itr_setting: current adapter->itr
2491 * @packets: the number of packets during this measurement interval
2492 * @bytes: the number of bytes during this measurement interval
2493 *
2494 * Stores a new ITR value based on packets and byte
2495 * counts during the last interrupt. The advantage of per interrupt
2496 * computation is faster updates and more accurate ITR for the current
2497 * traffic pattern. Constants in this function were computed
2498 * based on theoretical maximum wire speed and thresholds were set based
2499 * on testing data as well as attempting to minimize response time
2500 * while increasing bulk throughput. This functionality is controlled
2501 * by the InterruptThrottleRate module parameter.
2502 **/
2503static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
2504{
2505 unsigned int retval = itr_setting;
2506
2507 if (packets == 0)
2508 return itr_setting;
2509
2510 switch (itr_setting) {
2511 case lowest_latency:
2512 /* handle TSO and jumbo frames */
2513 if (bytes / packets > 8000)
2514 retval = bulk_latency;
2515 else if ((packets < 5) && (bytes > 512))
2516 retval = low_latency;
2517 break;
2518 case low_latency: /* 50 usec aka 20000 ints/s */
2519 if (bytes > 10000) {
2520 /* this if handles the TSO accounting */
2521 if (bytes / packets > 8000)
2522 retval = bulk_latency;
2523 else if ((packets < 10) || ((bytes / packets) > 1200))
2524 retval = bulk_latency;
2525 else if ((packets > 35))
2526 retval = lowest_latency;
2527 } else if (bytes / packets > 2000) {
2528 retval = bulk_latency;
2529 } else if (packets <= 2 && bytes < 512) {
2530 retval = lowest_latency;
2531 }
2532 break;
2533 case bulk_latency: /* 250 usec aka 4000 ints/s */
2534 if (bytes > 25000) {
2535 if (packets > 35)
2536 retval = low_latency;
2537 } else if (bytes < 6000) {
2538 retval = low_latency;
2539 }
2540 break;
2541 }
2542
2543 return retval;
2544}
2545
2546static void e1000_set_itr(struct e1000_adapter *adapter)
2547{
2548 u16 current_itr;
2549 u32 new_itr = adapter->itr;
2550
2551 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2552 if (adapter->link_speed != SPEED_1000) {
2553 current_itr = 0;
2554 new_itr = 4000;
2555 goto set_itr_now;
2556 }
2557
2558 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2559 new_itr = 0;
2560 goto set_itr_now;
2561 }
2562
2563 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2564 adapter->total_tx_packets,
2565 adapter->total_tx_bytes);
2566 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2567 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2568 adapter->tx_itr = low_latency;
2569
2570 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2571 adapter->total_rx_packets,
2572 adapter->total_rx_bytes);
2573 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2574 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2575 adapter->rx_itr = low_latency;
2576
2577 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2578
2579 /* counts and packets in update_itr are dependent on these numbers */
2580 switch (current_itr) {
2581 case lowest_latency:
2582 new_itr = 70000;
2583 break;
2584 case low_latency:
2585 new_itr = 20000; /* aka hwitr = ~200 */
2586 break;
2587 case bulk_latency:
2588 new_itr = 4000;
2589 break;
2590 default:
2591 break;
2592 }
2593
2594set_itr_now:
2595 if (new_itr != adapter->itr) {
2596 /* this attempts to bias the interrupt rate towards Bulk
2597 * by adding intermediate steps when interrupt rate is
2598 * increasing
2599 */
2600 new_itr = new_itr > adapter->itr ?
2601 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
2602 adapter->itr = new_itr;
2603 adapter->rx_ring->itr_val = new_itr;
2604 if (adapter->msix_entries)
2605 adapter->rx_ring->set_itr = 1;
2606 else
2607 e1000e_write_itr(adapter, new_itr);
2608 }
2609}
2610
2611/**
2612 * e1000e_write_itr - write the ITR value to the appropriate registers
2613 * @adapter: address of board private structure
2614 * @itr: new ITR value to program
2615 *
2616 * e1000e_write_itr determines if the adapter is in MSI-X mode
2617 * and, if so, writes the EITR registers with the ITR value.
2618 * Otherwise, it writes the ITR value into the ITR register.
2619 **/
2620void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2621{
2622 struct e1000_hw *hw = &adapter->hw;
2623 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2624
2625 if (adapter->msix_entries) {
2626 int vector;
2627
2628 for (vector = 0; vector < adapter->num_vectors; vector++)
2629 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2630 } else {
2631 ew32(ITR, new_itr);
2632 }
2633}
2634
2635/**
2636 * e1000_alloc_queues - Allocate memory for all rings
2637 * @adapter: board private structure to initialize
2638 **/
2639static int e1000_alloc_queues(struct e1000_adapter *adapter)
2640{
2641 int size = sizeof(struct e1000_ring);
2642
2643 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
2644 if (!adapter->tx_ring)
2645 goto err;
2646 adapter->tx_ring->count = adapter->tx_ring_count;
2647 adapter->tx_ring->adapter = adapter;
2648
2649 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
2650 if (!adapter->rx_ring)
2651 goto err;
2652 adapter->rx_ring->count = adapter->rx_ring_count;
2653 adapter->rx_ring->adapter = adapter;
2654
2655 return 0;
2656err:
2657 e_err("Unable to allocate memory for queues\n");
2658 kfree(adapter->rx_ring);
2659 kfree(adapter->tx_ring);
2660 return -ENOMEM;
2661}
2662
2663/**
2664 * e1000e_poll - NAPI Rx polling callback
2665 * @napi: struct associated with this polling callback
2666 * @budget: number of packets driver is allowed to process this poll
2667 **/
2668static int e1000e_poll(struct napi_struct *napi, int budget)
2669{
2670 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2671 napi);
2672 struct e1000_hw *hw = &adapter->hw;
2673 struct net_device *poll_dev = adapter->netdev;
2674 int tx_cleaned = 1, work_done = 0;
2675
2676 adapter = netdev_priv(poll_dev);
2677
2678 if (!adapter->msix_entries ||
2679 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2680 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
2681
2682 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
2683
2684 if (!tx_cleaned || work_done == budget)
2685 return budget;
2686
2687 /* Exit the polling mode, but don't re-enable interrupts if stack might
2688 * poll us due to busy-polling
2689 */
2690 if (likely(napi_complete_done(napi, work_done))) {
2691 if (adapter->itr_setting & 3)
2692 e1000_set_itr(adapter);
2693 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2694 if (adapter->msix_entries)
2695 ew32(IMS, adapter->rx_ring->ims_val);
2696 else
2697 e1000_irq_enable(adapter);
2698 }
2699 }
2700
2701 return work_done;
2702}
2703
2704static int e1000_vlan_rx_add_vid(struct net_device *netdev,
2705 __always_unused __be16 proto, u16 vid)
2706{
2707 struct e1000_adapter *adapter = netdev_priv(netdev);
2708 struct e1000_hw *hw = &adapter->hw;
2709 u32 vfta, index;
2710
2711 /* don't update vlan cookie if already programmed */
2712 if ((adapter->hw.mng_cookie.status &
2713 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2714 (vid == adapter->mng_vlan_id))
2715 return 0;
2716
2717 /* add VID to filter table */
2718 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2719 index = (vid >> 5) & 0x7F;
2720 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2721 vfta |= BIT((vid & 0x1F));
2722 hw->mac.ops.write_vfta(hw, index, vfta);
2723 }
2724
2725 set_bit(vid, adapter->active_vlans);
2726
2727 return 0;
2728}
2729
2730static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
2731 __always_unused __be16 proto, u16 vid)
2732{
2733 struct e1000_adapter *adapter = netdev_priv(netdev);
2734 struct e1000_hw *hw = &adapter->hw;
2735 u32 vfta, index;
2736
2737 if ((adapter->hw.mng_cookie.status &
2738 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2739 (vid == adapter->mng_vlan_id)) {
2740 /* release control to f/w */
2741 e1000e_release_hw_control(adapter);
2742 return 0;
2743 }
2744
2745 /* remove VID from filter table */
2746 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2747 index = (vid >> 5) & 0x7F;
2748 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2749 vfta &= ~BIT((vid & 0x1F));
2750 hw->mac.ops.write_vfta(hw, index, vfta);
2751 }
2752
2753 clear_bit(vid, adapter->active_vlans);
2754
2755 return 0;
2756}
2757
2758/**
2759 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2760 * @adapter: board private structure to initialize
2761 **/
2762static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
2763{
2764 struct net_device *netdev = adapter->netdev;
2765 struct e1000_hw *hw = &adapter->hw;
2766 u32 rctl;
2767
2768 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2769 /* disable VLAN receive filtering */
2770 rctl = er32(RCTL);
2771 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2772 ew32(RCTL, rctl);
2773
2774 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2775 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2776 adapter->mng_vlan_id);
2777 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
2778 }
2779 }
2780}
2781
2782/**
2783 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2784 * @adapter: board private structure to initialize
2785 **/
2786static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2787{
2788 struct e1000_hw *hw = &adapter->hw;
2789 u32 rctl;
2790
2791 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2792 /* enable VLAN receive filtering */
2793 rctl = er32(RCTL);
2794 rctl |= E1000_RCTL_VFE;
2795 rctl &= ~E1000_RCTL_CFIEN;
2796 ew32(RCTL, rctl);
2797 }
2798}
2799
2800/**
2801 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2802 * @adapter: board private structure to initialize
2803 **/
2804static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
2805{
2806 struct e1000_hw *hw = &adapter->hw;
2807 u32 ctrl;
2808
2809 /* disable VLAN tag insert/strip */
2810 ctrl = er32(CTRL);
2811 ctrl &= ~E1000_CTRL_VME;
2812 ew32(CTRL, ctrl);
2813}
2814
2815/**
2816 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2817 * @adapter: board private structure to initialize
2818 **/
2819static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2820{
2821 struct e1000_hw *hw = &adapter->hw;
2822 u32 ctrl;
2823
2824 /* enable VLAN tag insert/strip */
2825 ctrl = er32(CTRL);
2826 ctrl |= E1000_CTRL_VME;
2827 ew32(CTRL, ctrl);
2828}
2829
2830static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2831{
2832 struct net_device *netdev = adapter->netdev;
2833 u16 vid = adapter->hw.mng_cookie.vlan_id;
2834 u16 old_vid = adapter->mng_vlan_id;
2835
2836 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2837 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
2838 adapter->mng_vlan_id = vid;
2839 }
2840
2841 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2842 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
2843}
2844
2845static void e1000_restore_vlan(struct e1000_adapter *adapter)
2846{
2847 u16 vid;
2848
2849 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
2850
2851 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2852 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
2853}
2854
2855static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
2856{
2857 struct e1000_hw *hw = &adapter->hw;
2858 u32 manc, manc2h, mdef, i, j;
2859
2860 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2861 return;
2862
2863 manc = er32(MANC);
2864
2865 /* enable receiving management packets to the host. this will probably
2866 * generate destination unreachable messages from the host OS, but
2867 * the packets will be handled on SMBUS
2868 */
2869 manc |= E1000_MANC_EN_MNG2HOST;
2870 manc2h = er32(MANC2H);
2871
2872 switch (hw->mac.type) {
2873 default:
2874 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2875 break;
2876 case e1000_82574:
2877 case e1000_82583:
2878 /* Check if IPMI pass-through decision filter already exists;
2879 * if so, enable it.
2880 */
2881 for (i = 0, j = 0; i < 8; i++) {
2882 mdef = er32(MDEF(i));
2883
2884 /* Ignore filters with anything other than IPMI ports */
2885 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2886 continue;
2887
2888 /* Enable this decision filter in MANC2H */
2889 if (mdef)
2890 manc2h |= BIT(i);
2891
2892 j |= mdef;
2893 }
2894
2895 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2896 break;
2897
2898 /* Create new decision filter in an empty filter */
2899 for (i = 0, j = 0; i < 8; i++)
2900 if (er32(MDEF(i)) == 0) {
2901 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2902 E1000_MDEF_PORT_664));
2903 manc2h |= BIT(1);
2904 j++;
2905 break;
2906 }
2907
2908 if (!j)
2909 e_warn("Unable to create IPMI pass-through filter\n");
2910 break;
2911 }
2912
2913 ew32(MANC2H, manc2h);
2914 ew32(MANC, manc);
2915}
2916
2917/**
2918 * e1000_configure_tx - Configure Transmit Unit after Reset
2919 * @adapter: board private structure
2920 *
2921 * Configure the Tx unit of the MAC after a reset.
2922 **/
2923static void e1000_configure_tx(struct e1000_adapter *adapter)
2924{
2925 struct e1000_hw *hw = &adapter->hw;
2926 struct e1000_ring *tx_ring = adapter->tx_ring;
2927 u64 tdba;
2928 u32 tdlen, tctl, tarc;
2929
2930 /* Setup the HW Tx Head and Tail descriptor pointers */
2931 tdba = tx_ring->dma;
2932 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
2933 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2934 ew32(TDBAH(0), (tdba >> 32));
2935 ew32(TDLEN(0), tdlen);
2936 ew32(TDH(0), 0);
2937 ew32(TDT(0), 0);
2938 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2939 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
2940
2941 writel(0, tx_ring->head);
2942 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2943 e1000e_update_tdt_wa(tx_ring, 0);
2944 else
2945 writel(0, tx_ring->tail);
2946
2947 /* Set the Tx Interrupt Delay register */
2948 ew32(TIDV, adapter->tx_int_delay);
2949 /* Tx irq moderation */
2950 ew32(TADV, adapter->tx_abs_int_delay);
2951
2952 if (adapter->flags2 & FLAG2_DMA_BURST) {
2953 u32 txdctl = er32(TXDCTL(0));
2954
2955 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2956 E1000_TXDCTL_WTHRESH);
2957 /* set up some performance related parameters to encourage the
2958 * hardware to use the bus more efficiently in bursts, depends
2959 * on the tx_int_delay to be enabled,
2960 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2961 * hthresh = 1 ==> prefetch when one or more available
2962 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2963 * BEWARE: this seems to work but should be considered first if
2964 * there are Tx hangs or other Tx related bugs
2965 */
2966 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2967 ew32(TXDCTL(0), txdctl);
2968 }
2969 /* erratum work around: set txdctl the same for both queues */
2970 ew32(TXDCTL(1), er32(TXDCTL(0)));
2971
2972 /* Program the Transmit Control Register */
2973 tctl = er32(TCTL);
2974 tctl &= ~E1000_TCTL_CT;
2975 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2976 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2977
2978 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
2979 tarc = er32(TARC(0));
2980 /* set the speed mode bit, we'll clear it if we're not at
2981 * gigabit link later
2982 */
2983#define SPEED_MODE_BIT BIT(21)
2984 tarc |= SPEED_MODE_BIT;
2985 ew32(TARC(0), tarc);
2986 }
2987
2988 /* errata: program both queues to unweighted RR */
2989 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
2990 tarc = er32(TARC(0));
2991 tarc |= 1;
2992 ew32(TARC(0), tarc);
2993 tarc = er32(TARC(1));
2994 tarc |= 1;
2995 ew32(TARC(1), tarc);
2996 }
2997
2998 /* Setup Transmit Descriptor Settings for eop descriptor */
2999 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
3000
3001 /* only set IDE if we are delaying interrupts using the timers */
3002 if (adapter->tx_int_delay)
3003 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3004
3005 /* enable Report Status bit */
3006 adapter->txd_cmd |= E1000_TXD_CMD_RS;
3007
3008 ew32(TCTL, tctl);
3009
3010 hw->mac.ops.config_collision_dist(hw);
3011
3012 /* SPT and KBL Si errata workaround to avoid data corruption */
3013 if (hw->mac.type == e1000_pch_spt) {
3014 u32 reg_val;
3015
3016 reg_val = er32(IOSFPC);
3017 reg_val |= E1000_RCTL_RDMTS_HEX;
3018 ew32(IOSFPC, reg_val);
3019
3020 reg_val = er32(TARC(0));
3021 /* SPT and KBL Si errata workaround to avoid Tx hang.
3022 * Dropping the number of outstanding requests from
3023 * 3 to 2 in order to avoid a buffer overrun.
3024 */
3025 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3026 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
3027 ew32(TARC(0), reg_val);
3028 }
3029}
3030
3031#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3032 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3033
3034/**
3035 * e1000_setup_rctl - configure the receive control registers
3036 * @adapter: Board private structure
3037 **/
3038static void e1000_setup_rctl(struct e1000_adapter *adapter)
3039{
3040 struct e1000_hw *hw = &adapter->hw;
3041 u32 rctl, rfctl;
3042 u32 pages = 0;
3043
3044 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3045 * If jumbo frames not set, program related MAC/PHY registers
3046 * to h/w defaults
3047 */
3048 if (hw->mac.type >= e1000_pch2lan) {
3049 s32 ret_val;
3050
3051 if (adapter->netdev->mtu > ETH_DATA_LEN)
3052 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3053 else
3054 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3055
3056 if (ret_val)
3057 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3058 }
3059
3060 /* Program MC offset vector base */
3061 rctl = er32(RCTL);
3062 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3063 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
3064 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3065 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3066
3067 /* Do not Store bad packets */
3068 rctl &= ~E1000_RCTL_SBP;
3069
3070 /* Enable Long Packet receive */
3071 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3072 rctl &= ~E1000_RCTL_LPE;
3073 else
3074 rctl |= E1000_RCTL_LPE;
3075
3076 /* Some systems expect that the CRC is included in SMBUS traffic. The
3077 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3078 * host memory when this is enabled
3079 */
3080 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3081 rctl |= E1000_RCTL_SECRC;
3082
3083 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3084 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3085 u16 phy_data;
3086
3087 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3088 phy_data &= 0xfff8;
3089 phy_data |= BIT(2);
3090 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3091
3092 e1e_rphy(hw, 22, &phy_data);
3093 phy_data &= 0x0fff;
3094 phy_data |= BIT(14);
3095 e1e_wphy(hw, 0x10, 0x2823);
3096 e1e_wphy(hw, 0x11, 0x0003);
3097 e1e_wphy(hw, 22, phy_data);
3098 }
3099
3100 /* Setup buffer sizes */
3101 rctl &= ~E1000_RCTL_SZ_4096;
3102 rctl |= E1000_RCTL_BSEX;
3103 switch (adapter->rx_buffer_len) {
3104 case 2048:
3105 default:
3106 rctl |= E1000_RCTL_SZ_2048;
3107 rctl &= ~E1000_RCTL_BSEX;
3108 break;
3109 case 4096:
3110 rctl |= E1000_RCTL_SZ_4096;
3111 break;
3112 case 8192:
3113 rctl |= E1000_RCTL_SZ_8192;
3114 break;
3115 case 16384:
3116 rctl |= E1000_RCTL_SZ_16384;
3117 break;
3118 }
3119
3120 /* Enable Extended Status in all Receive Descriptors */
3121 rfctl = er32(RFCTL);
3122 rfctl |= E1000_RFCTL_EXTEN;
3123 ew32(RFCTL, rfctl);
3124
3125 /* 82571 and greater support packet-split where the protocol
3126 * header is placed in skb->data and the packet data is
3127 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3128 * In the case of a non-split, skb->data is linearly filled,
3129 * followed by the page buffers. Therefore, skb->data is
3130 * sized to hold the largest protocol header.
3131 *
3132 * allocations using alloc_page take too long for regular MTU
3133 * so only enable packet split for jumbo frames
3134 *
3135 * Using pages when the page size is greater than 16k wastes
3136 * a lot of memory, since we allocate 3 pages at all times
3137 * per packet.
3138 */
3139 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
3140 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
3141 adapter->rx_ps_pages = pages;
3142 else
3143 adapter->rx_ps_pages = 0;
3144
3145 if (adapter->rx_ps_pages) {
3146 u32 psrctl = 0;
3147
3148 /* Enable Packet split descriptors */
3149 rctl |= E1000_RCTL_DTYP_PS;
3150
3151 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
3152
3153 switch (adapter->rx_ps_pages) {
3154 case 3:
3155 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3156 fallthrough;
3157 case 2:
3158 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3159 fallthrough;
3160 case 1:
3161 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
3162 break;
3163 }
3164
3165 ew32(PSRCTL, psrctl);
3166 }
3167
3168 /* This is useful for sniffing bad packets. */
3169 if (adapter->netdev->features & NETIF_F_RXALL) {
3170 /* UPE and MPE will be handled by normal PROMISC logic
3171 * in e1000e_set_rx_mode
3172 */
3173 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3174 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3175 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3176
3177 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3178 E1000_RCTL_DPF | /* Allow filtered pause */
3179 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3180 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3181 * and that breaks VLANs.
3182 */
3183 }
3184
3185 ew32(RCTL, rctl);
3186 /* just started the receive unit, no need to restart */
3187 adapter->flags &= ~FLAG_RESTART_NOW;
3188}
3189
3190/**
3191 * e1000_configure_rx - Configure Receive Unit after Reset
3192 * @adapter: board private structure
3193 *
3194 * Configure the Rx unit of the MAC after a reset.
3195 **/
3196static void e1000_configure_rx(struct e1000_adapter *adapter)
3197{
3198 struct e1000_hw *hw = &adapter->hw;
3199 struct e1000_ring *rx_ring = adapter->rx_ring;
3200 u64 rdba;
3201 u32 rdlen, rctl, rxcsum, ctrl_ext;
3202
3203 if (adapter->rx_ps_pages) {
3204 /* this is a 32 byte descriptor */
3205 rdlen = rx_ring->count *
3206 sizeof(union e1000_rx_desc_packet_split);
3207 adapter->clean_rx = e1000_clean_rx_irq_ps;
3208 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
3209 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
3210 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3211 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3212 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
3213 } else {
3214 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
3215 adapter->clean_rx = e1000_clean_rx_irq;
3216 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3217 }
3218
3219 /* disable receives while setting up the descriptors */
3220 rctl = er32(RCTL);
3221 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3222 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3223 e1e_flush();
3224 usleep_range(10000, 11000);
3225
3226 if (adapter->flags2 & FLAG2_DMA_BURST) {
3227 /* set the writeback threshold (only takes effect if the RDTR
3228 * is set). set GRAN=1 and write back up to 0x4 worth, and
3229 * enable prefetching of 0x20 Rx descriptors
3230 * granularity = 01
3231 * wthresh = 04,
3232 * hthresh = 04,
3233 * pthresh = 0x20
3234 */
3235 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3236 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3237 }
3238
3239 /* set the Receive Delay Timer Register */
3240 ew32(RDTR, adapter->rx_int_delay);
3241
3242 /* irq moderation */
3243 ew32(RADV, adapter->rx_abs_int_delay);
3244 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
3245 e1000e_write_itr(adapter, adapter->itr);
3246
3247 ctrl_ext = er32(CTRL_EXT);
3248 /* Auto-Mask interrupts upon ICR access */
3249 ctrl_ext |= E1000_CTRL_EXT_IAME;
3250 ew32(IAM, 0xffffffff);
3251 ew32(CTRL_EXT, ctrl_ext);
3252 e1e_flush();
3253
3254 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3255 * the Base and Length of the Rx Descriptor Ring
3256 */
3257 rdba = rx_ring->dma;
3258 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3259 ew32(RDBAH(0), (rdba >> 32));
3260 ew32(RDLEN(0), rdlen);
3261 ew32(RDH(0), 0);
3262 ew32(RDT(0), 0);
3263 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3264 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
3265
3266 writel(0, rx_ring->head);
3267 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3268 e1000e_update_rdt_wa(rx_ring, 0);
3269 else
3270 writel(0, rx_ring->tail);
3271
3272 /* Enable Receive Checksum Offload for TCP and UDP */
3273 rxcsum = er32(RXCSUM);
3274 if (adapter->netdev->features & NETIF_F_RXCSUM)
3275 rxcsum |= E1000_RXCSUM_TUOFL;
3276 else
3277 rxcsum &= ~E1000_RXCSUM_TUOFL;
3278 ew32(RXCSUM, rxcsum);
3279
3280 /* With jumbo frames, excessive C-state transition latencies result
3281 * in dropped transactions.
3282 */
3283 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3284 u32 lat =
3285 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3286 adapter->max_frame_size) * 8 / 1000;
3287
3288 if (adapter->flags & FLAG_IS_ICH) {
3289 u32 rxdctl = er32(RXDCTL(0));
3290
3291 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
3292 }
3293
3294 dev_info(&adapter->pdev->dev,
3295 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
3296 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
3297 } else {
3298 cpu_latency_qos_update_request(&adapter->pm_qos_req,
3299 PM_QOS_DEFAULT_VALUE);
3300 }
3301
3302 /* Enable Receives */
3303 ew32(RCTL, rctl);
3304}
3305
3306/**
3307 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3308 * @netdev: network interface device structure
3309 *
3310 * Writes multicast address list to the MTA hash table.
3311 * Returns: -ENOMEM on failure
3312 * 0 on no addresses written
3313 * X on writing X addresses to MTA
3314 */
3315static int e1000e_write_mc_addr_list(struct net_device *netdev)
3316{
3317 struct e1000_adapter *adapter = netdev_priv(netdev);
3318 struct e1000_hw *hw = &adapter->hw;
3319 struct netdev_hw_addr *ha;
3320 u8 *mta_list;
3321 int i;
3322
3323 if (netdev_mc_empty(netdev)) {
3324 /* nothing to program, so clear mc list */
3325 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3326 return 0;
3327 }
3328
3329 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
3330 if (!mta_list)
3331 return -ENOMEM;
3332
3333 /* update_mc_addr_list expects a packed array of only addresses. */
3334 i = 0;
3335 netdev_for_each_mc_addr(ha, netdev)
3336 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3337
3338 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3339 kfree(mta_list);
3340
3341 return netdev_mc_count(netdev);
3342}
3343
3344/**
3345 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3346 * @netdev: network interface device structure
3347 *
3348 * Writes unicast address list to the RAR table.
3349 * Returns: -ENOMEM on failure/insufficient address space
3350 * 0 on no addresses written
3351 * X on writing X addresses to the RAR table
3352 **/
3353static int e1000e_write_uc_addr_list(struct net_device *netdev)
3354{
3355 struct e1000_adapter *adapter = netdev_priv(netdev);
3356 struct e1000_hw *hw = &adapter->hw;
3357 unsigned int rar_entries;
3358 int count = 0;
3359
3360 rar_entries = hw->mac.ops.rar_get_count(hw);
3361
3362 /* save a rar entry for our hardware address */
3363 rar_entries--;
3364
3365 /* save a rar entry for the LAA workaround */
3366 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3367 rar_entries--;
3368
3369 /* return ENOMEM indicating insufficient memory for addresses */
3370 if (netdev_uc_count(netdev) > rar_entries)
3371 return -ENOMEM;
3372
3373 if (!netdev_uc_empty(netdev) && rar_entries) {
3374 struct netdev_hw_addr *ha;
3375
3376 /* write the addresses in reverse order to avoid write
3377 * combining
3378 */
3379 netdev_for_each_uc_addr(ha, netdev) {
3380 int ret_val;
3381
3382 if (!rar_entries)
3383 break;
3384 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3385 if (ret_val < 0)
3386 return -ENOMEM;
3387 count++;
3388 }
3389 }
3390
3391 /* zero out the remaining RAR entries not used above */
3392 for (; rar_entries > 0; rar_entries--) {
3393 ew32(RAH(rar_entries), 0);
3394 ew32(RAL(rar_entries), 0);
3395 }
3396 e1e_flush();
3397
3398 return count;
3399}
3400
3401/**
3402 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3403 * @netdev: network interface device structure
3404 *
3405 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3406 * address list or the network interface flags are updated. This routine is
3407 * responsible for configuring the hardware for proper unicast, multicast,
3408 * promiscuous mode, and all-multi behavior.
3409 **/
3410static void e1000e_set_rx_mode(struct net_device *netdev)
3411{
3412 struct e1000_adapter *adapter = netdev_priv(netdev);
3413 struct e1000_hw *hw = &adapter->hw;
3414 u32 rctl;
3415
3416 if (pm_runtime_suspended(netdev->dev.parent))
3417 return;
3418
3419 /* Check for Promiscuous and All Multicast modes */
3420 rctl = er32(RCTL);
3421
3422 /* clear the affected bits */
3423 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3424
3425 if (netdev->flags & IFF_PROMISC) {
3426 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
3427 /* Do not hardware filter VLANs in promisc mode */
3428 e1000e_vlan_filter_disable(adapter);
3429 } else {
3430 int count;
3431
3432 if (netdev->flags & IFF_ALLMULTI) {
3433 rctl |= E1000_RCTL_MPE;
3434 } else {
3435 /* Write addresses to the MTA, if the attempt fails
3436 * then we should just turn on promiscuous mode so
3437 * that we can at least receive multicast traffic
3438 */
3439 count = e1000e_write_mc_addr_list(netdev);
3440 if (count < 0)
3441 rctl |= E1000_RCTL_MPE;
3442 }
3443 e1000e_vlan_filter_enable(adapter);
3444 /* Write addresses to available RAR registers, if there is not
3445 * sufficient space to store all the addresses then enable
3446 * unicast promiscuous mode
3447 */
3448 count = e1000e_write_uc_addr_list(netdev);
3449 if (count < 0)
3450 rctl |= E1000_RCTL_UPE;
3451 }
3452
3453 ew32(RCTL, rctl);
3454
3455 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3456 e1000e_vlan_strip_enable(adapter);
3457 else
3458 e1000e_vlan_strip_disable(adapter);
3459}
3460
3461static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3462{
3463 struct e1000_hw *hw = &adapter->hw;
3464 u32 mrqc, rxcsum;
3465 u32 rss_key[10];
3466 int i;
3467
3468 netdev_rss_key_fill(rss_key, sizeof(rss_key));
3469 for (i = 0; i < 10; i++)
3470 ew32(RSSRK(i), rss_key[i]);
3471
3472 /* Direct all traffic to queue 0 */
3473 for (i = 0; i < 32; i++)
3474 ew32(RETA(i), 0);
3475
3476 /* Disable raw packet checksumming so that RSS hash is placed in
3477 * descriptor on writeback.
3478 */
3479 rxcsum = er32(RXCSUM);
3480 rxcsum |= E1000_RXCSUM_PCSD;
3481
3482 ew32(RXCSUM, rxcsum);
3483
3484 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3485 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3486 E1000_MRQC_RSS_FIELD_IPV6 |
3487 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3488 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3489
3490 ew32(MRQC, mrqc);
3491}
3492
3493/**
3494 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3495 * @adapter: board private structure
3496 * @timinca: pointer to returned time increment attributes
3497 *
3498 * Get attributes for incrementing the System Time Register SYSTIML/H at
3499 * the default base frequency, and set the cyclecounter shift value.
3500 **/
3501s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
3502{
3503 struct e1000_hw *hw = &adapter->hw;
3504 u32 incvalue, incperiod, shift;
3505
3506 /* Make sure clock is enabled on I217/I218/I219 before checking
3507 * the frequency
3508 */
3509 if ((hw->mac.type >= e1000_pch_lpt) &&
3510 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3511 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3512 u32 fextnvm7 = er32(FEXTNVM7);
3513
3514 if (!(fextnvm7 & BIT(0))) {
3515 ew32(FEXTNVM7, fextnvm7 | BIT(0));
3516 e1e_flush();
3517 }
3518 }
3519
3520 switch (hw->mac.type) {
3521 case e1000_pch2lan:
3522 /* Stable 96MHz frequency */
3523 incperiod = INCPERIOD_96MHZ;
3524 incvalue = INCVALUE_96MHZ;
3525 shift = INCVALUE_SHIFT_96MHZ;
3526 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3527 break;
3528 case e1000_pch_lpt:
3529 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3530 /* Stable 96MHz frequency */
3531 incperiod = INCPERIOD_96MHZ;
3532 incvalue = INCVALUE_96MHZ;
3533 shift = INCVALUE_SHIFT_96MHZ;
3534 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
3535 } else {
3536 /* Stable 25MHz frequency */
3537 incperiod = INCPERIOD_25MHZ;
3538 incvalue = INCVALUE_25MHZ;
3539 shift = INCVALUE_SHIFT_25MHZ;
3540 adapter->cc.shift = shift;
3541 }
3542 break;
3543 case e1000_pch_spt:
3544 /* Stable 24MHz frequency */
3545 incperiod = INCPERIOD_24MHZ;
3546 incvalue = INCVALUE_24MHZ;
3547 shift = INCVALUE_SHIFT_24MHZ;
3548 adapter->cc.shift = shift;
3549 break;
3550 case e1000_pch_cnp:
3551 case e1000_pch_tgp:
3552 case e1000_pch_adp:
3553 case e1000_pch_mtp:
3554 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3555 /* Stable 24MHz frequency */
3556 incperiod = INCPERIOD_24MHZ;
3557 incvalue = INCVALUE_24MHZ;
3558 shift = INCVALUE_SHIFT_24MHZ;
3559 adapter->cc.shift = shift;
3560 } else {
3561 /* Stable 38400KHz frequency */
3562 incperiod = INCPERIOD_38400KHZ;
3563 incvalue = INCVALUE_38400KHZ;
3564 shift = INCVALUE_SHIFT_38400KHZ;
3565 adapter->cc.shift = shift;
3566 }
3567 break;
3568 case e1000_82574:
3569 case e1000_82583:
3570 /* Stable 25MHz frequency */
3571 incperiod = INCPERIOD_25MHZ;
3572 incvalue = INCVALUE_25MHZ;
3573 shift = INCVALUE_SHIFT_25MHZ;
3574 adapter->cc.shift = shift;
3575 break;
3576 default:
3577 return -EINVAL;
3578 }
3579
3580 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3581 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3582
3583 return 0;
3584}
3585
3586/**
3587 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3588 * @adapter: board private structure
3589 * @config: timestamp configuration
3590 *
3591 * Outgoing time stamping can be enabled and disabled. Play nice and
3592 * disable it when requested, although it shouldn't cause any overhead
3593 * when no packet needs it. At most one packet in the queue may be
3594 * marked for time stamping, otherwise it would be impossible to tell
3595 * for sure to which packet the hardware time stamp belongs.
3596 *
3597 * Incoming time stamping has to be configured via the hardware filters.
3598 * Not all combinations are supported, in particular event type has to be
3599 * specified. Matching the kind of event packet is not supported, with the
3600 * exception of "all V2 events regardless of level 2 or 4".
3601 **/
3602static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3603 struct hwtstamp_config *config)
3604{
3605 struct e1000_hw *hw = &adapter->hw;
3606 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3607 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
3608 u32 rxmtrl = 0;
3609 u16 rxudp = 0;
3610 bool is_l4 = false;
3611 bool is_l2 = false;
3612 u32 regval;
3613
3614 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3615 return -EINVAL;
3616
3617 /* flags reserved for future extensions - must be zero */
3618 if (config->flags)
3619 return -EINVAL;
3620
3621 switch (config->tx_type) {
3622 case HWTSTAMP_TX_OFF:
3623 tsync_tx_ctl = 0;
3624 break;
3625 case HWTSTAMP_TX_ON:
3626 break;
3627 default:
3628 return -ERANGE;
3629 }
3630
3631 switch (config->rx_filter) {
3632 case HWTSTAMP_FILTER_NONE:
3633 tsync_rx_ctl = 0;
3634 break;
3635 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3636 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3637 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3638 is_l4 = true;
3639 break;
3640 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3641 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3642 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3643 is_l4 = true;
3644 break;
3645 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3646 /* Also time stamps V2 L2 Path Delay Request/Response */
3647 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3648 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3649 is_l2 = true;
3650 break;
3651 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3652 /* Also time stamps V2 L2 Path Delay Request/Response. */
3653 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3654 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3655 is_l2 = true;
3656 break;
3657 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3658 /* Hardware cannot filter just V2 L4 Sync messages */
3659 fallthrough;
3660 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3661 /* Also time stamps V2 Path Delay Request/Response. */
3662 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3663 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3664 is_l2 = true;
3665 is_l4 = true;
3666 break;
3667 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3668 /* Hardware cannot filter just V2 L4 Delay Request messages */
3669 fallthrough;
3670 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3671 /* Also time stamps V2 Path Delay Request/Response. */
3672 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3673 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3674 is_l2 = true;
3675 is_l4 = true;
3676 break;
3677 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3678 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3679 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3680 fallthrough;
3681 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3682 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3683 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3684 is_l2 = true;
3685 is_l4 = true;
3686 break;
3687 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3688 /* For V1, the hardware can only filter Sync messages or
3689 * Delay Request messages but not both so fall-through to
3690 * time stamp all packets.
3691 */
3692 fallthrough;
3693 case HWTSTAMP_FILTER_NTP_ALL:
3694 case HWTSTAMP_FILTER_ALL:
3695 is_l2 = true;
3696 is_l4 = true;
3697 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3698 config->rx_filter = HWTSTAMP_FILTER_ALL;
3699 break;
3700 default:
3701 return -ERANGE;
3702 }
3703
3704 adapter->hwtstamp_config = *config;
3705
3706 /* enable/disable Tx h/w time stamping */
3707 regval = er32(TSYNCTXCTL);
3708 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3709 regval |= tsync_tx_ctl;
3710 ew32(TSYNCTXCTL, regval);
3711 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3712 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3713 e_err("Timesync Tx Control register not set as expected\n");
3714 return -EAGAIN;
3715 }
3716
3717 /* enable/disable Rx h/w time stamping */
3718 regval = er32(TSYNCRXCTL);
3719 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3720 regval |= tsync_rx_ctl;
3721 ew32(TSYNCRXCTL, regval);
3722 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3723 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3724 (regval & (E1000_TSYNCRXCTL_ENABLED |
3725 E1000_TSYNCRXCTL_TYPE_MASK))) {
3726 e_err("Timesync Rx Control register not set as expected\n");
3727 return -EAGAIN;
3728 }
3729
3730 /* L2: define ethertype filter for time stamped packets */
3731 if (is_l2)
3732 rxmtrl |= ETH_P_1588;
3733
3734 /* define which PTP packets get time stamped */
3735 ew32(RXMTRL, rxmtrl);
3736
3737 /* Filter by destination port */
3738 if (is_l4) {
3739 rxudp = PTP_EV_PORT;
3740 cpu_to_be16s(&rxudp);
3741 }
3742 ew32(RXUDP, rxudp);
3743
3744 e1e_flush();
3745
3746 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3747 er32(RXSTMPH);
3748 er32(TXSTMPH);
3749
3750 return 0;
3751}
3752
3753/**
3754 * e1000_configure - configure the hardware for Rx and Tx
3755 * @adapter: private board structure
3756 **/
3757static void e1000_configure(struct e1000_adapter *adapter)
3758{
3759 struct e1000_ring *rx_ring = adapter->rx_ring;
3760
3761 e1000e_set_rx_mode(adapter->netdev);
3762
3763 e1000_restore_vlan(adapter);
3764 e1000_init_manageability_pt(adapter);
3765
3766 e1000_configure_tx(adapter);
3767
3768 if (adapter->netdev->features & NETIF_F_RXHASH)
3769 e1000e_setup_rss_hash(adapter);
3770 e1000_setup_rctl(adapter);
3771 e1000_configure_rx(adapter);
3772 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
3773}
3774
3775/**
3776 * e1000e_power_up_phy - restore link in case the phy was powered down
3777 * @adapter: address of board private structure
3778 *
3779 * The phy may be powered down to save power and turn off link when the
3780 * driver is unloaded and wake on lan is not enabled (among others)
3781 * *** this routine MUST be followed by a call to e1000e_reset ***
3782 **/
3783void e1000e_power_up_phy(struct e1000_adapter *adapter)
3784{
3785 if (adapter->hw.phy.ops.power_up)
3786 adapter->hw.phy.ops.power_up(&adapter->hw);
3787
3788 adapter->hw.mac.ops.setup_link(&adapter->hw);
3789}
3790
3791/**
3792 * e1000_power_down_phy - Power down the PHY
3793 * @adapter: board private structure
3794 *
3795 * Power down the PHY so no link is implied when interface is down.
3796 * The PHY cannot be powered down if management or WoL is active.
3797 */
3798static void e1000_power_down_phy(struct e1000_adapter *adapter)
3799{
3800 if (adapter->hw.phy.ops.power_down)
3801 adapter->hw.phy.ops.power_down(&adapter->hw);
3802}
3803
3804/**
3805 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3806 * @adapter: board private structure
3807 *
3808 * We want to clear all pending descriptors from the TX ring.
3809 * zeroing happens when the HW reads the regs. We assign the ring itself as
3810 * the data of the next descriptor. We don't care about the data we are about
3811 * to reset the HW.
3812 */
3813static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3814{
3815 struct e1000_hw *hw = &adapter->hw;
3816 struct e1000_ring *tx_ring = adapter->tx_ring;
3817 struct e1000_tx_desc *tx_desc = NULL;
3818 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3819 u16 size = 512;
3820
3821 tctl = er32(TCTL);
3822 ew32(TCTL, tctl | E1000_TCTL_EN);
3823 tdt = er32(TDT(0));
3824 BUG_ON(tdt != tx_ring->next_to_use);
3825 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3826 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
3827
3828 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3829 tx_desc->upper.data = 0;
3830 /* flush descriptors to memory before notifying the HW */
3831 wmb();
3832 tx_ring->next_to_use++;
3833 if (tx_ring->next_to_use == tx_ring->count)
3834 tx_ring->next_to_use = 0;
3835 ew32(TDT(0), tx_ring->next_to_use);
3836 usleep_range(200, 250);
3837}
3838
3839/**
3840 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3841 * @adapter: board private structure
3842 *
3843 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3844 */
3845static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3846{
3847 u32 rctl, rxdctl;
3848 struct e1000_hw *hw = &adapter->hw;
3849
3850 rctl = er32(RCTL);
3851 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3852 e1e_flush();
3853 usleep_range(100, 150);
3854
3855 rxdctl = er32(RXDCTL(0));
3856 /* zero the lower 14 bits (prefetch and host thresholds) */
3857 rxdctl &= 0xffffc000;
3858
3859 /* update thresholds: prefetch threshold to 31, host threshold to 1
3860 * and make sure the granularity is "descriptors" and not "cache lines"
3861 */
3862 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3863
3864 ew32(RXDCTL(0), rxdctl);
3865 /* momentarily enable the RX ring for the changes to take effect */
3866 ew32(RCTL, rctl | E1000_RCTL_EN);
3867 e1e_flush();
3868 usleep_range(100, 150);
3869 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3870}
3871
3872/**
3873 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3874 * @adapter: board private structure
3875 *
3876 * In i219, the descriptor rings must be emptied before resetting the HW
3877 * or before changing the device state to D3 during runtime (runtime PM).
3878 *
3879 * Failure to do this will cause the HW to enter a unit hang state which can
3880 * only be released by PCI reset on the device
3881 *
3882 */
3883
3884static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3885{
3886 u16 hang_state;
3887 u32 fext_nvm11, tdlen;
3888 struct e1000_hw *hw = &adapter->hw;
3889
3890 /* First, disable MULR fix in FEXTNVM11 */
3891 fext_nvm11 = er32(FEXTNVM11);
3892 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3893 ew32(FEXTNVM11, fext_nvm11);
3894 /* do nothing if we're not in faulty state, or if the queue is empty */
3895 tdlen = er32(TDLEN(0));
3896 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3897 &hang_state);
3898 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
3899 return;
3900 e1000_flush_tx_ring(adapter);
3901 /* recheck, maybe the fault is caused by the rx ring */
3902 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3903 &hang_state);
3904 if (hang_state & FLUSH_DESC_REQUIRED)
3905 e1000_flush_rx_ring(adapter);
3906}
3907
3908/**
3909 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3910 * @adapter: board private structure
3911 *
3912 * When the MAC is reset, all hardware bits for timesync will be reset to the
3913 * default values. This function will restore the settings last in place.
3914 * Since the clock SYSTIME registers are reset, we will simply restore the
3915 * cyclecounter to the kernel real clock time.
3916 **/
3917static void e1000e_systim_reset(struct e1000_adapter *adapter)
3918{
3919 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3920 struct e1000_hw *hw = &adapter->hw;
3921 unsigned long flags;
3922 u32 timinca;
3923 s32 ret_val;
3924
3925 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3926 return;
3927
3928 if (info->adjfreq) {
3929 /* restore the previous ptp frequency delta */
3930 ret_val = info->adjfreq(info, adapter->ptp_delta);
3931 } else {
3932 /* set the default base frequency if no adjustment possible */
3933 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3934 if (!ret_val)
3935 ew32(TIMINCA, timinca);
3936 }
3937
3938 if (ret_val) {
3939 dev_warn(&adapter->pdev->dev,
3940 "Failed to restore TIMINCA clock rate delta: %d\n",
3941 ret_val);
3942 return;
3943 }
3944
3945 /* reset the systim ns time counter */
3946 spin_lock_irqsave(&adapter->systim_lock, flags);
3947 timecounter_init(&adapter->tc, &adapter->cc,
3948 ktime_to_ns(ktime_get_real()));
3949 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3950
3951 /* restore the previous hwtstamp configuration settings */
3952 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3953}
3954
3955/**
3956 * e1000e_reset - bring the hardware into a known good state
3957 * @adapter: board private structure
3958 *
3959 * This function boots the hardware and enables some settings that
3960 * require a configuration cycle of the hardware - those cannot be
3961 * set/changed during runtime. After reset the device needs to be
3962 * properly configured for Rx, Tx etc.
3963 */
3964void e1000e_reset(struct e1000_adapter *adapter)
3965{
3966 struct e1000_mac_info *mac = &adapter->hw.mac;
3967 struct e1000_fc_info *fc = &adapter->hw.fc;
3968 struct e1000_hw *hw = &adapter->hw;
3969 u32 tx_space, min_tx_space, min_rx_space;
3970 u32 pba = adapter->pba;
3971 u16 hwm;
3972
3973 /* reset Packet Buffer Allocation to default */
3974 ew32(PBA, pba);
3975
3976 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
3977 /* To maintain wire speed transmits, the Tx FIFO should be
3978 * large enough to accommodate two full transmit packets,
3979 * rounded up to the next 1KB and expressed in KB. Likewise,
3980 * the Rx FIFO should be large enough to accommodate at least
3981 * one full receive packet and is similarly rounded up and
3982 * expressed in KB.
3983 */
3984 pba = er32(PBA);
3985 /* upper 16 bits has Tx packet buffer allocation size in KB */
3986 tx_space = pba >> 16;
3987 /* lower 16 bits has Rx packet buffer allocation size in KB */
3988 pba &= 0xffff;
3989 /* the Tx fifo also stores 16 bytes of information about the Tx
3990 * but don't include ethernet FCS because hardware appends it
3991 */
3992 min_tx_space = (adapter->max_frame_size +
3993 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
3994 min_tx_space = ALIGN(min_tx_space, 1024);
3995 min_tx_space >>= 10;
3996 /* software strips receive CRC, so leave room for it */
3997 min_rx_space = adapter->max_frame_size;
3998 min_rx_space = ALIGN(min_rx_space, 1024);
3999 min_rx_space >>= 10;
4000
4001 /* If current Tx allocation is less than the min Tx FIFO size,
4002 * and the min Tx FIFO size is less than the current Rx FIFO
4003 * allocation, take space away from current Rx allocation
4004 */
4005 if ((tx_space < min_tx_space) &&
4006 ((min_tx_space - tx_space) < pba)) {
4007 pba -= min_tx_space - tx_space;
4008
4009 /* if short on Rx space, Rx wins and must trump Tx
4010 * adjustment
4011 */
4012 if (pba < min_rx_space)
4013 pba = min_rx_space;
4014 }
4015
4016 ew32(PBA, pba);
4017 }
4018
4019 /* flow control settings
4020 *
4021 * The high water mark must be low enough to fit one full frame
4022 * (or the size used for early receive) above it in the Rx FIFO.
4023 * Set it to the lower of:
4024 * - 90% of the Rx FIFO size, and
4025 * - the full Rx FIFO size minus one full frame
4026 */
4027 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4028 fc->pause_time = 0xFFFF;
4029 else
4030 fc->pause_time = E1000_FC_PAUSE_TIME;
4031 fc->send_xon = true;
4032 fc->current_mode = fc->requested_mode;
4033
4034 switch (hw->mac.type) {
4035 case e1000_ich9lan:
4036 case e1000_ich10lan:
4037 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4038 pba = 14;
4039 ew32(PBA, pba);
4040 fc->high_water = 0x2800;
4041 fc->low_water = fc->high_water - 8;
4042 break;
4043 }
4044 fallthrough;
4045 default:
4046 hwm = min(((pba << 10) * 9 / 10),
4047 ((pba << 10) - adapter->max_frame_size));
4048
4049 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
4050 fc->low_water = fc->high_water - 8;
4051 break;
4052 case e1000_pchlan:
4053 /* Workaround PCH LOM adapter hangs with certain network
4054 * loads. If hangs persist, try disabling Tx flow control.
4055 */
4056 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4057 fc->high_water = 0x3500;
4058 fc->low_water = 0x1500;
4059 } else {
4060 fc->high_water = 0x5000;
4061 fc->low_water = 0x3000;
4062 }
4063 fc->refresh_time = 0x1000;
4064 break;
4065 case e1000_pch2lan:
4066 case e1000_pch_lpt:
4067 case e1000_pch_spt:
4068 case e1000_pch_cnp:
4069 case e1000_pch_tgp:
4070 case e1000_pch_adp:
4071 case e1000_pch_mtp:
4072 fc->refresh_time = 0xFFFF;
4073 fc->pause_time = 0xFFFF;
4074
4075 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4076 fc->high_water = 0x05C20;
4077 fc->low_water = 0x05048;
4078 break;
4079 }
4080
4081 pba = 14;
4082 ew32(PBA, pba);
4083 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4084 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
4085 break;
4086 }
4087
4088 /* Alignment of Tx data is on an arbitrary byte boundary with the
4089 * maximum size per Tx descriptor limited only to the transmit
4090 * allocation of the packet buffer minus 96 bytes with an upper
4091 * limit of 24KB due to receive synchronization limitations.
4092 */
4093 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4094 24 << 10);
4095
4096 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4097 * fit in receive buffer.
4098 */
4099 if (adapter->itr_setting & 0x3) {
4100 if ((adapter->max_frame_size * 2) > (pba << 10)) {
4101 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4102 dev_info(&adapter->pdev->dev,
4103 "Interrupt Throttle Rate off\n");
4104 adapter->flags2 |= FLAG2_DISABLE_AIM;
4105 e1000e_write_itr(adapter, 0);
4106 }
4107 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4108 dev_info(&adapter->pdev->dev,
4109 "Interrupt Throttle Rate on\n");
4110 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4111 adapter->itr = 20000;
4112 e1000e_write_itr(adapter, adapter->itr);
4113 }
4114 }
4115
4116 if (hw->mac.type >= e1000_pch_spt)
4117 e1000_flush_desc_rings(adapter);
4118 /* Allow time for pending master requests to run */
4119 mac->ops.reset_hw(hw);
4120
4121 /* For parts with AMT enabled, let the firmware know
4122 * that the network interface is in control
4123 */
4124 if (adapter->flags & FLAG_HAS_AMT)
4125 e1000e_get_hw_control(adapter);
4126
4127 ew32(WUC, 0);
4128
4129 if (mac->ops.init_hw(hw))
4130 e_err("Hardware Error\n");
4131
4132 e1000_update_mng_vlan(adapter);
4133
4134 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4135 ew32(VET, ETH_P_8021Q);
4136
4137 e1000e_reset_adaptive(hw);
4138
4139 /* restore systim and hwtstamp settings */
4140 e1000e_systim_reset(adapter);
4141
4142 /* Set EEE advertisement as appropriate */
4143 if (adapter->flags2 & FLAG2_HAS_EEE) {
4144 s32 ret_val;
4145 u16 adv_addr;
4146
4147 switch (hw->phy.type) {
4148 case e1000_phy_82579:
4149 adv_addr = I82579_EEE_ADVERTISEMENT;
4150 break;
4151 case e1000_phy_i217:
4152 adv_addr = I217_EEE_ADVERTISEMENT;
4153 break;
4154 default:
4155 dev_err(&adapter->pdev->dev,
4156 "Invalid PHY type setting EEE advertisement\n");
4157 return;
4158 }
4159
4160 ret_val = hw->phy.ops.acquire(hw);
4161 if (ret_val) {
4162 dev_err(&adapter->pdev->dev,
4163 "EEE advertisement - unable to acquire PHY\n");
4164 return;
4165 }
4166
4167 e1000_write_emi_reg_locked(hw, adv_addr,
4168 hw->dev_spec.ich8lan.eee_disable ?
4169 0 : adapter->eee_advert);
4170
4171 hw->phy.ops.release(hw);
4172 }
4173
4174 if (!netif_running(adapter->netdev) &&
4175 !test_bit(__E1000_TESTING, &adapter->state))
4176 e1000_power_down_phy(adapter);
4177
4178 e1000_get_phy_info(hw);
4179
4180 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4181 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
4182 u16 phy_data = 0;
4183 /* speed up time to link by disabling smart power down, ignore
4184 * the return value of this function because there is nothing
4185 * different we would do if it failed
4186 */
4187 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4188 phy_data &= ~IGP02E1000_PM_SPD;
4189 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4190 }
4191 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
4192 u32 reg;
4193
4194 /* Fextnvm7 @ 0xe4[2] = 1 */
4195 reg = er32(FEXTNVM7);
4196 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4197 ew32(FEXTNVM7, reg);
4198 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4199 reg = er32(FEXTNVM9);
4200 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4201 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4202 ew32(FEXTNVM9, reg);
4203 }
4204
4205}
4206
4207/**
4208 * e1000e_trigger_lsc - trigger an LSC interrupt
4209 * @adapter:
4210 *
4211 * Fire a link status change interrupt to start the watchdog.
4212 **/
4213static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
4214{
4215 struct e1000_hw *hw = &adapter->hw;
4216
4217 if (adapter->msix_entries)
4218 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
4219 else
4220 ew32(ICS, E1000_ICS_LSC);
4221}
4222
4223void e1000e_up(struct e1000_adapter *adapter)
4224{
4225 /* hardware has been reset, we need to reload some things */
4226 e1000_configure(adapter);
4227
4228 clear_bit(__E1000_DOWN, &adapter->state);
4229
4230 if (adapter->msix_entries)
4231 e1000_configure_msix(adapter);
4232 e1000_irq_enable(adapter);
4233
4234 /* Tx queue started by watchdog timer when link is up */
4235
4236 e1000e_trigger_lsc(adapter);
4237}
4238
4239static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4240{
4241 struct e1000_hw *hw = &adapter->hw;
4242
4243 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4244 return;
4245
4246 /* flush pending descriptor writebacks to memory */
4247 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4248 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4249
4250 /* execute the writes immediately */
4251 e1e_flush();
4252
4253 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4254 * write is successful
4255 */
4256 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4257 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4258
4259 /* execute the writes immediately */
4260 e1e_flush();
4261}
4262
4263static void e1000e_update_stats(struct e1000_adapter *adapter);
4264
4265/**
4266 * e1000e_down - quiesce the device and optionally reset the hardware
4267 * @adapter: board private structure
4268 * @reset: boolean flag to reset the hardware or not
4269 */
4270void e1000e_down(struct e1000_adapter *adapter, bool reset)
4271{
4272 struct net_device *netdev = adapter->netdev;
4273 struct e1000_hw *hw = &adapter->hw;
4274 u32 tctl, rctl;
4275
4276 /* signal that we're down so the interrupt handler does not
4277 * reschedule our watchdog timer
4278 */
4279 set_bit(__E1000_DOWN, &adapter->state);
4280
4281 netif_carrier_off(netdev);
4282
4283 /* disable receives in the hardware */
4284 rctl = er32(RCTL);
4285 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4286 ew32(RCTL, rctl & ~E1000_RCTL_EN);
4287 /* flush and sleep below */
4288
4289 netif_stop_queue(netdev);
4290
4291 /* disable transmits in the hardware */
4292 tctl = er32(TCTL);
4293 tctl &= ~E1000_TCTL_EN;
4294 ew32(TCTL, tctl);
4295
4296 /* flush both disables and wait for them to finish */
4297 e1e_flush();
4298 usleep_range(10000, 11000);
4299
4300 e1000_irq_disable(adapter);
4301
4302 napi_synchronize(&adapter->napi);
4303
4304 del_timer_sync(&adapter->watchdog_timer);
4305 del_timer_sync(&adapter->phy_info_timer);
4306
4307 spin_lock(&adapter->stats64_lock);
4308 e1000e_update_stats(adapter);
4309 spin_unlock(&adapter->stats64_lock);
4310
4311 e1000e_flush_descriptors(adapter);
4312
4313 adapter->link_speed = 0;
4314 adapter->link_duplex = 0;
4315
4316 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4317 if ((hw->mac.type >= e1000_pch2lan) &&
4318 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4319 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4320 e_dbg("failed to disable jumbo frame workaround mode\n");
4321
4322 if (!pci_channel_offline(adapter->pdev)) {
4323 if (reset)
4324 e1000e_reset(adapter);
4325 else if (hw->mac.type >= e1000_pch_spt)
4326 e1000_flush_desc_rings(adapter);
4327 }
4328 e1000_clean_tx_ring(adapter->tx_ring);
4329 e1000_clean_rx_ring(adapter->rx_ring);
4330}
4331
4332void e1000e_reinit_locked(struct e1000_adapter *adapter)
4333{
4334 might_sleep();
4335 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
4336 usleep_range(1000, 1100);
4337 e1000e_down(adapter, true);
4338 e1000e_up(adapter);
4339 clear_bit(__E1000_RESETTING, &adapter->state);
4340}
4341
4342/**
4343 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4344 * @hw: pointer to the HW structure
4345 * @systim: PHC time value read, sanitized and returned
4346 * @sts: structure to hold system time before and after reading SYSTIML,
4347 * may be NULL
4348 *
4349 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4350 * check to see that the time is incrementing at a reasonable
4351 * rate and is a multiple of incvalue.
4352 **/
4353static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4354 struct ptp_system_timestamp *sts)
4355{
4356 u64 time_delta, rem, temp;
4357 u64 systim_next;
4358 u32 incvalue;
4359 int i;
4360
4361 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4362 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4363 /* latch SYSTIMH on read of SYSTIML */
4364 ptp_read_system_prets(sts);
4365 systim_next = (u64)er32(SYSTIML);
4366 ptp_read_system_postts(sts);
4367 systim_next |= (u64)er32(SYSTIMH) << 32;
4368
4369 time_delta = systim_next - systim;
4370 temp = time_delta;
4371 /* VMWare users have seen incvalue of zero, don't div / 0 */
4372 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4373
4374 systim = systim_next;
4375
4376 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4377 break;
4378 }
4379
4380 return systim;
4381}
4382
4383/**
4384 * e1000e_read_systim - read SYSTIM register
4385 * @adapter: board private structure
4386 * @sts: structure which will contain system time before and after reading
4387 * SYSTIML, may be NULL
4388 **/
4389u64 e1000e_read_systim(struct e1000_adapter *adapter,
4390 struct ptp_system_timestamp *sts)
4391{
4392 struct e1000_hw *hw = &adapter->hw;
4393 u32 systimel, systimel_2, systimeh;
4394 u64 systim;
4395 /* SYSTIMH latching upon SYSTIML read does not work well.
4396 * This means that if SYSTIML overflows after we read it but before
4397 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4398 * will experience a huge non linear increment in the systime value
4399 * to fix that we test for overflow and if true, we re-read systime.
4400 */
4401 ptp_read_system_prets(sts);
4402 systimel = er32(SYSTIML);
4403 ptp_read_system_postts(sts);
4404 systimeh = er32(SYSTIMH);
4405 /* Is systimel is so large that overflow is possible? */
4406 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4407 ptp_read_system_prets(sts);
4408 systimel_2 = er32(SYSTIML);
4409 ptp_read_system_postts(sts);
4410 if (systimel > systimel_2) {
4411 /* There was an overflow, read again SYSTIMH, and use
4412 * systimel_2
4413 */
4414 systimeh = er32(SYSTIMH);
4415 systimel = systimel_2;
4416 }
4417 }
4418 systim = (u64)systimel;
4419 systim |= (u64)systimeh << 32;
4420
4421 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
4422 systim = e1000e_sanitize_systim(hw, systim, sts);
4423
4424 return systim;
4425}
4426
4427/**
4428 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4429 * @cc: cyclecounter structure
4430 **/
4431static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4432{
4433 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4434 cc);
4435
4436 return e1000e_read_systim(adapter, NULL);
4437}
4438
4439/**
4440 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4441 * @adapter: board private structure to initialize
4442 *
4443 * e1000_sw_init initializes the Adapter private data structure.
4444 * Fields are initialized based on PCI device information and
4445 * OS network device settings (MTU size).
4446 **/
4447static int e1000_sw_init(struct e1000_adapter *adapter)
4448{
4449 struct net_device *netdev = adapter->netdev;
4450
4451 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
4452 adapter->rx_ps_bsize0 = 128;
4453 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4454 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
4455 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4456 adapter->rx_ring_count = E1000_DEFAULT_RXD;
4457
4458 spin_lock_init(&adapter->stats64_lock);
4459
4460 e1000e_set_interrupt_capability(adapter);
4461
4462 if (e1000_alloc_queues(adapter))
4463 return -ENOMEM;
4464
4465 /* Setup hardware time stamping cyclecounter */
4466 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4467 adapter->cc.read = e1000e_cyclecounter_read;
4468 adapter->cc.mask = CYCLECOUNTER_MASK(64);
4469 adapter->cc.mult = 1;
4470 /* cc.shift set in e1000e_get_base_tininca() */
4471
4472 spin_lock_init(&adapter->systim_lock);
4473 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4474 }
4475
4476 /* Explicitly disable IRQ since the NIC can be in any state. */
4477 e1000_irq_disable(adapter);
4478
4479 set_bit(__E1000_DOWN, &adapter->state);
4480 return 0;
4481}
4482
4483/**
4484 * e1000_intr_msi_test - Interrupt Handler
4485 * @irq: interrupt number
4486 * @data: pointer to a network interface device structure
4487 **/
4488static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
4489{
4490 struct net_device *netdev = data;
4491 struct e1000_adapter *adapter = netdev_priv(netdev);
4492 struct e1000_hw *hw = &adapter->hw;
4493 u32 icr = er32(ICR);
4494
4495 e_dbg("icr is %08X\n", icr);
4496 if (icr & E1000_ICR_RXSEQ) {
4497 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
4498 /* Force memory writes to complete before acknowledging the
4499 * interrupt is handled.
4500 */
4501 wmb();
4502 }
4503
4504 return IRQ_HANDLED;
4505}
4506
4507/**
4508 * e1000_test_msi_interrupt - Returns 0 for successful test
4509 * @adapter: board private struct
4510 *
4511 * code flow taken from tg3.c
4512 **/
4513static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4514{
4515 struct net_device *netdev = adapter->netdev;
4516 struct e1000_hw *hw = &adapter->hw;
4517 int err;
4518
4519 /* poll_enable hasn't been called yet, so don't need disable */
4520 /* clear any pending events */
4521 er32(ICR);
4522
4523 /* free the real vector and request a test handler */
4524 e1000_free_irq(adapter);
4525 e1000e_reset_interrupt_capability(adapter);
4526
4527 /* Assume that the test fails, if it succeeds then the test
4528 * MSI irq handler will unset this flag
4529 */
4530 adapter->flags |= FLAG_MSI_TEST_FAILED;
4531
4532 err = pci_enable_msi(adapter->pdev);
4533 if (err)
4534 goto msi_test_failed;
4535
4536 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
4537 netdev->name, netdev);
4538 if (err) {
4539 pci_disable_msi(adapter->pdev);
4540 goto msi_test_failed;
4541 }
4542
4543 /* Force memory writes to complete before enabling and firing an
4544 * interrupt.
4545 */
4546 wmb();
4547
4548 e1000_irq_enable(adapter);
4549
4550 /* fire an unusual interrupt on the test handler */
4551 ew32(ICS, E1000_ICS_RXSEQ);
4552 e1e_flush();
4553 msleep(100);
4554
4555 e1000_irq_disable(adapter);
4556
4557 rmb(); /* read flags after interrupt has been fired */
4558
4559 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4560 adapter->int_mode = E1000E_INT_MODE_LEGACY;
4561 e_info("MSI interrupt test failed, using legacy interrupt.\n");
4562 } else {
4563 e_dbg("MSI interrupt test succeeded!\n");
4564 }
4565
4566 free_irq(adapter->pdev->irq, netdev);
4567 pci_disable_msi(adapter->pdev);
4568
4569msi_test_failed:
4570 e1000e_set_interrupt_capability(adapter);
4571 return e1000_request_irq(adapter);
4572}
4573
4574/**
4575 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4576 * @adapter: board private struct
4577 *
4578 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4579 **/
4580static int e1000_test_msi(struct e1000_adapter *adapter)
4581{
4582 int err;
4583 u16 pci_cmd;
4584
4585 if (!(adapter->flags & FLAG_MSI_ENABLED))
4586 return 0;
4587
4588 /* disable SERR in case the MSI write causes a master abort */
4589 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4590 if (pci_cmd & PCI_COMMAND_SERR)
4591 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4592 pci_cmd & ~PCI_COMMAND_SERR);
4593
4594 err = e1000_test_msi_interrupt(adapter);
4595
4596 /* re-enable SERR */
4597 if (pci_cmd & PCI_COMMAND_SERR) {
4598 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4599 pci_cmd |= PCI_COMMAND_SERR;
4600 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4601 }
4602
4603 return err;
4604}
4605
4606/**
4607 * e1000e_open - Called when a network interface is made active
4608 * @netdev: network interface device structure
4609 *
4610 * Returns 0 on success, negative value on failure
4611 *
4612 * The open entry point is called when a network interface is made
4613 * active by the system (IFF_UP). At this point all resources needed
4614 * for transmit and receive operations are allocated, the interrupt
4615 * handler is registered with the OS, the watchdog timer is started,
4616 * and the stack is notified that the interface is ready.
4617 **/
4618int e1000e_open(struct net_device *netdev)
4619{
4620 struct e1000_adapter *adapter = netdev_priv(netdev);
4621 struct e1000_hw *hw = &adapter->hw;
4622 struct pci_dev *pdev = adapter->pdev;
4623 int err;
4624
4625 /* disallow open during test */
4626 if (test_bit(__E1000_TESTING, &adapter->state))
4627 return -EBUSY;
4628
4629 pm_runtime_get_sync(&pdev->dev);
4630
4631 netif_carrier_off(netdev);
4632 netif_stop_queue(netdev);
4633
4634 /* allocate transmit descriptors */
4635 err = e1000e_setup_tx_resources(adapter->tx_ring);
4636 if (err)
4637 goto err_setup_tx;
4638
4639 /* allocate receive descriptors */
4640 err = e1000e_setup_rx_resources(adapter->rx_ring);
4641 if (err)
4642 goto err_setup_rx;
4643
4644 /* If AMT is enabled, let the firmware know that the network
4645 * interface is now open and reset the part to a known state.
4646 */
4647 if (adapter->flags & FLAG_HAS_AMT) {
4648 e1000e_get_hw_control(adapter);
4649 e1000e_reset(adapter);
4650 }
4651
4652 e1000e_power_up_phy(adapter);
4653
4654 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
4655 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
4656 e1000_update_mng_vlan(adapter);
4657
4658 /* DMA latency requirement to workaround jumbo issue */
4659 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
4660
4661 /* before we allocate an interrupt, we must be ready to handle it.
4662 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4663 * as soon as we call pci_request_irq, so we have to setup our
4664 * clean_rx handler before we do so.
4665 */
4666 e1000_configure(adapter);
4667
4668 err = e1000_request_irq(adapter);
4669 if (err)
4670 goto err_req_irq;
4671
4672 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4673 * ignore e1000e MSI messages, which means we need to test our MSI
4674 * interrupt now
4675 */
4676 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
4677 err = e1000_test_msi(adapter);
4678 if (err) {
4679 e_err("Interrupt allocation failed\n");
4680 goto err_req_irq;
4681 }
4682 }
4683
4684 /* From here on the code is the same as e1000e_up() */
4685 clear_bit(__E1000_DOWN, &adapter->state);
4686
4687 napi_enable(&adapter->napi);
4688
4689 e1000_irq_enable(adapter);
4690
4691 adapter->tx_hang_recheck = false;
4692
4693 hw->mac.get_link_status = true;
4694 pm_runtime_put(&pdev->dev);
4695
4696 e1000e_trigger_lsc(adapter);
4697
4698 return 0;
4699
4700err_req_irq:
4701 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4702 e1000e_release_hw_control(adapter);
4703 e1000_power_down_phy(adapter);
4704 e1000e_free_rx_resources(adapter->rx_ring);
4705err_setup_rx:
4706 e1000e_free_tx_resources(adapter->tx_ring);
4707err_setup_tx:
4708 e1000e_reset(adapter);
4709 pm_runtime_put_sync(&pdev->dev);
4710
4711 return err;
4712}
4713
4714/**
4715 * e1000e_close - Disables a network interface
4716 * @netdev: network interface device structure
4717 *
4718 * Returns 0, this is not allowed to fail
4719 *
4720 * The close entry point is called when an interface is de-activated
4721 * by the OS. The hardware is still under the drivers control, but
4722 * needs to be disabled. A global MAC reset is issued to stop the
4723 * hardware, and all transmit and receive resources are freed.
4724 **/
4725int e1000e_close(struct net_device *netdev)
4726{
4727 struct e1000_adapter *adapter = netdev_priv(netdev);
4728 struct pci_dev *pdev = adapter->pdev;
4729 int count = E1000_CHECK_RESET_COUNT;
4730
4731 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4732 usleep_range(10000, 11000);
4733
4734 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
4735
4736 pm_runtime_get_sync(&pdev->dev);
4737
4738 if (netif_device_present(netdev)) {
4739 e1000e_down(adapter, true);
4740 e1000_free_irq(adapter);
4741
4742 /* Link status message must follow this format */
4743 netdev_info(netdev, "NIC Link is Down\n");
4744 }
4745
4746 napi_disable(&adapter->napi);
4747
4748 e1000e_free_tx_resources(adapter->tx_ring);
4749 e1000e_free_rx_resources(adapter->rx_ring);
4750
4751 /* kill manageability vlan ID if supported, but not if a vlan with
4752 * the same ID is registered on the host OS (let 8021q kill it)
4753 */
4754 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
4755 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4756 adapter->mng_vlan_id);
4757
4758 /* If AMT is enabled, let the firmware know that the network
4759 * interface is now closed
4760 */
4761 if ((adapter->flags & FLAG_HAS_AMT) &&
4762 !test_bit(__E1000_TESTING, &adapter->state))
4763 e1000e_release_hw_control(adapter);
4764
4765 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
4766
4767 pm_runtime_put_sync(&pdev->dev);
4768
4769 return 0;
4770}
4771
4772/**
4773 * e1000_set_mac - Change the Ethernet Address of the NIC
4774 * @netdev: network interface device structure
4775 * @p: pointer to an address structure
4776 *
4777 * Returns 0 on success, negative on failure
4778 **/
4779static int e1000_set_mac(struct net_device *netdev, void *p)
4780{
4781 struct e1000_adapter *adapter = netdev_priv(netdev);
4782 struct e1000_hw *hw = &adapter->hw;
4783 struct sockaddr *addr = p;
4784
4785 if (!is_valid_ether_addr(addr->sa_data))
4786 return -EADDRNOTAVAIL;
4787
4788 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4789 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4790
4791 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4792
4793 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4794 /* activate the work around */
4795 e1000e_set_laa_state_82571(&adapter->hw, 1);
4796
4797 /* Hold a copy of the LAA in RAR[14] This is done so that
4798 * between the time RAR[0] gets clobbered and the time it
4799 * gets fixed (in e1000_watchdog), the actual LAA is in one
4800 * of the RARs and no incoming packets directed to this port
4801 * are dropped. Eventually the LAA will be in RAR[0] and
4802 * RAR[14]
4803 */
4804 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4805 adapter->hw.mac.rar_entry_count - 1);
4806 }
4807
4808 return 0;
4809}
4810
4811/**
4812 * e1000e_update_phy_task - work thread to update phy
4813 * @work: pointer to our work struct
4814 *
4815 * this worker thread exists because we must acquire a
4816 * semaphore to read the phy, which we could msleep while
4817 * waiting for it, and we can't msleep in a timer.
4818 **/
4819static void e1000e_update_phy_task(struct work_struct *work)
4820{
4821 struct e1000_adapter *adapter = container_of(work,
4822 struct e1000_adapter,
4823 update_phy_task);
4824 struct e1000_hw *hw = &adapter->hw;
4825
4826 if (test_bit(__E1000_DOWN, &adapter->state))
4827 return;
4828
4829 e1000_get_phy_info(hw);
4830
4831 /* Enable EEE on 82579 after link up */
4832 if (hw->phy.type >= e1000_phy_82579)
4833 e1000_set_eee_pchlan(hw);
4834}
4835
4836/**
4837 * e1000_update_phy_info - timre call-back to update PHY info
4838 * @t: pointer to timer_list containing private info adapter
4839 *
4840 * Need to wait a few seconds after link up to get diagnostic information from
4841 * the phy
4842 **/
4843static void e1000_update_phy_info(struct timer_list *t)
4844{
4845 struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer);
4846
4847 if (test_bit(__E1000_DOWN, &adapter->state))
4848 return;
4849
4850 schedule_work(&adapter->update_phy_task);
4851}
4852
4853/**
4854 * e1000e_update_phy_stats - Update the PHY statistics counters
4855 * @adapter: board private structure
4856 *
4857 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4858 **/
4859static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4860{
4861 struct e1000_hw *hw = &adapter->hw;
4862 s32 ret_val;
4863 u16 phy_data;
4864
4865 ret_val = hw->phy.ops.acquire(hw);
4866 if (ret_val)
4867 return;
4868
4869 /* A page set is expensive so check if already on desired page.
4870 * If not, set to the page with the PHY status registers.
4871 */
4872 hw->phy.addr = 1;
4873 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4874 &phy_data);
4875 if (ret_val)
4876 goto release;
4877 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4878 ret_val = hw->phy.ops.set_page(hw,
4879 HV_STATS_PAGE << IGP_PAGE_SHIFT);
4880 if (ret_val)
4881 goto release;
4882 }
4883
4884 /* Single Collision Count */
4885 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4886 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
4887 if (!ret_val)
4888 adapter->stats.scc += phy_data;
4889
4890 /* Excessive Collision Count */
4891 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4892 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
4893 if (!ret_val)
4894 adapter->stats.ecol += phy_data;
4895
4896 /* Multiple Collision Count */
4897 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4898 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
4899 if (!ret_val)
4900 adapter->stats.mcc += phy_data;
4901
4902 /* Late Collision Count */
4903 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4904 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
4905 if (!ret_val)
4906 adapter->stats.latecol += phy_data;
4907
4908 /* Collision Count - also used for adaptive IFS */
4909 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4910 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
4911 if (!ret_val)
4912 hw->mac.collision_delta = phy_data;
4913
4914 /* Defer Count */
4915 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4916 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
4917 if (!ret_val)
4918 adapter->stats.dc += phy_data;
4919
4920 /* Transmit with no CRS */
4921 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4922 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
4923 if (!ret_val)
4924 adapter->stats.tncrs += phy_data;
4925
4926release:
4927 hw->phy.ops.release(hw);
4928}
4929
4930/**
4931 * e1000e_update_stats - Update the board statistics counters
4932 * @adapter: board private structure
4933 **/
4934static void e1000e_update_stats(struct e1000_adapter *adapter)
4935{
4936 struct net_device *netdev = adapter->netdev;
4937 struct e1000_hw *hw = &adapter->hw;
4938 struct pci_dev *pdev = adapter->pdev;
4939
4940 /* Prevent stats update while adapter is being reset, or if the pci
4941 * connection is down.
4942 */
4943 if (adapter->link_speed == 0)
4944 return;
4945 if (pci_channel_offline(pdev))
4946 return;
4947
4948 adapter->stats.crcerrs += er32(CRCERRS);
4949 adapter->stats.gprc += er32(GPRC);
4950 adapter->stats.gorc += er32(GORCL);
4951 er32(GORCH); /* Clear gorc */
4952 adapter->stats.bprc += er32(BPRC);
4953 adapter->stats.mprc += er32(MPRC);
4954 adapter->stats.roc += er32(ROC);
4955
4956 adapter->stats.mpc += er32(MPC);
4957
4958 /* Half-duplex statistics */
4959 if (adapter->link_duplex == HALF_DUPLEX) {
4960 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4961 e1000e_update_phy_stats(adapter);
4962 } else {
4963 adapter->stats.scc += er32(SCC);
4964 adapter->stats.ecol += er32(ECOL);
4965 adapter->stats.mcc += er32(MCC);
4966 adapter->stats.latecol += er32(LATECOL);
4967 adapter->stats.dc += er32(DC);
4968
4969 hw->mac.collision_delta = er32(COLC);
4970
4971 if ((hw->mac.type != e1000_82574) &&
4972 (hw->mac.type != e1000_82583))
4973 adapter->stats.tncrs += er32(TNCRS);
4974 }
4975 adapter->stats.colc += hw->mac.collision_delta;
4976 }
4977
4978 adapter->stats.xonrxc += er32(XONRXC);
4979 adapter->stats.xontxc += er32(XONTXC);
4980 adapter->stats.xoffrxc += er32(XOFFRXC);
4981 adapter->stats.xofftxc += er32(XOFFTXC);
4982 adapter->stats.gptc += er32(GPTC);
4983 adapter->stats.gotc += er32(GOTCL);
4984 er32(GOTCH); /* Clear gotc */
4985 adapter->stats.rnbc += er32(RNBC);
4986 adapter->stats.ruc += er32(RUC);
4987
4988 adapter->stats.mptc += er32(MPTC);
4989 adapter->stats.bptc += er32(BPTC);
4990
4991 /* used for adaptive IFS */
4992
4993 hw->mac.tx_packet_delta = er32(TPT);
4994 adapter->stats.tpt += hw->mac.tx_packet_delta;
4995
4996 adapter->stats.algnerrc += er32(ALGNERRC);
4997 adapter->stats.rxerrc += er32(RXERRC);
4998 adapter->stats.cexterr += er32(CEXTERR);
4999 adapter->stats.tsctc += er32(TSCTC);
5000 adapter->stats.tsctfc += er32(TSCTFC);
5001
5002 /* Fill out the OS statistics structure */
5003 netdev->stats.multicast = adapter->stats.mprc;
5004 netdev->stats.collisions = adapter->stats.colc;
5005
5006 /* Rx Errors */
5007
5008 /* RLEC on some newer hardware can be incorrect so build
5009 * our own version based on RUC and ROC
5010 */
5011 netdev->stats.rx_errors = adapter->stats.rxerrc +
5012 adapter->stats.crcerrs + adapter->stats.algnerrc +
5013 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5014 netdev->stats.rx_length_errors = adapter->stats.ruc +
5015 adapter->stats.roc;
5016 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5017 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5018 netdev->stats.rx_missed_errors = adapter->stats.mpc;
5019
5020 /* Tx Errors */
5021 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
5022 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5023 netdev->stats.tx_window_errors = adapter->stats.latecol;
5024 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
5025
5026 /* Tx Dropped needs to be maintained elsewhere */
5027
5028 /* Management Stats */
5029 adapter->stats.mgptc += er32(MGTPTC);
5030 adapter->stats.mgprc += er32(MGTPRC);
5031 adapter->stats.mgpdc += er32(MGTPDC);
5032
5033 /* Correctable ECC Errors */
5034 if (hw->mac.type >= e1000_pch_lpt) {
5035 u32 pbeccsts = er32(PBECCSTS);
5036
5037 adapter->corr_errors +=
5038 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5039 adapter->uncorr_errors +=
5040 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
5041 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
5042 }
5043}
5044
5045/**
5046 * e1000_phy_read_status - Update the PHY register status snapshot
5047 * @adapter: board private structure
5048 **/
5049static void e1000_phy_read_status(struct e1000_adapter *adapter)
5050{
5051 struct e1000_hw *hw = &adapter->hw;
5052 struct e1000_phy_regs *phy = &adapter->phy_regs;
5053
5054 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5055 (er32(STATUS) & E1000_STATUS_LU) &&
5056 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
5057 int ret_val;
5058
5059 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5060 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5061 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5062 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5063 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5064 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5065 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5066 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
5067 if (ret_val)
5068 e_warn("Error reading PHY register\n");
5069 } else {
5070 /* Do not read PHY registers if link is not up
5071 * Set values to typical power-on defaults
5072 */
5073 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5074 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5075 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5076 BMSR_ERCAP);
5077 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5078 ADVERTISE_ALL | ADVERTISE_CSMA);
5079 phy->lpa = 0;
5080 phy->expansion = EXPANSION_ENABLENPAGE;
5081 phy->ctrl1000 = ADVERTISE_1000FULL;
5082 phy->stat1000 = 0;
5083 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5084 }
5085}
5086
5087static void e1000_print_link_info(struct e1000_adapter *adapter)
5088{
5089 struct e1000_hw *hw = &adapter->hw;
5090 u32 ctrl = er32(CTRL);
5091
5092 /* Link status message must follow this format for user tools */
5093 netdev_info(adapter->netdev,
5094 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5095 adapter->link_speed,
5096 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5097 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5098 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5099 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
5100}
5101
5102static bool e1000e_has_link(struct e1000_adapter *adapter)
5103{
5104 struct e1000_hw *hw = &adapter->hw;
5105 bool link_active = false;
5106 s32 ret_val = 0;
5107
5108 /* get_link_status is set on LSC (link status) interrupt or
5109 * Rx sequence error interrupt. get_link_status will stay
5110 * true until the check_for_link establishes link
5111 * for copper adapters ONLY
5112 */
5113 switch (hw->phy.media_type) {
5114 case e1000_media_type_copper:
5115 if (hw->mac.get_link_status) {
5116 ret_val = hw->mac.ops.check_for_link(hw);
5117 link_active = !hw->mac.get_link_status;
5118 } else {
5119 link_active = true;
5120 }
5121 break;
5122 case e1000_media_type_fiber:
5123 ret_val = hw->mac.ops.check_for_link(hw);
5124 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5125 break;
5126 case e1000_media_type_internal_serdes:
5127 ret_val = hw->mac.ops.check_for_link(hw);
5128 link_active = hw->mac.serdes_has_link;
5129 break;
5130 default:
5131 case e1000_media_type_unknown:
5132 break;
5133 }
5134
5135 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5136 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5137 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5138 e_info("Gigabit has been disabled, downgrading speed\n");
5139 }
5140
5141 return link_active;
5142}
5143
5144static void e1000e_enable_receives(struct e1000_adapter *adapter)
5145{
5146 /* make sure the receive unit is started */
5147 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5148 (adapter->flags & FLAG_RESTART_NOW)) {
5149 struct e1000_hw *hw = &adapter->hw;
5150 u32 rctl = er32(RCTL);
5151
5152 ew32(RCTL, rctl | E1000_RCTL_EN);
5153 adapter->flags &= ~FLAG_RESTART_NOW;
5154 }
5155}
5156
5157static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5158{
5159 struct e1000_hw *hw = &adapter->hw;
5160
5161 /* With 82574 controllers, PHY needs to be checked periodically
5162 * for hung state and reset, if two calls return true
5163 */
5164 if (e1000_check_phy_82574(hw))
5165 adapter->phy_hang_count++;
5166 else
5167 adapter->phy_hang_count = 0;
5168
5169 if (adapter->phy_hang_count > 1) {
5170 adapter->phy_hang_count = 0;
5171 e_dbg("PHY appears hung - resetting\n");
5172 schedule_work(&adapter->reset_task);
5173 }
5174}
5175
5176/**
5177 * e1000_watchdog - Timer Call-back
5178 * @t: pointer to timer_list containing private info adapter
5179 **/
5180static void e1000_watchdog(struct timer_list *t)
5181{
5182 struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer);
5183
5184 /* Do the rest outside of interrupt context */
5185 schedule_work(&adapter->watchdog_task);
5186
5187 /* TODO: make this use queue_delayed_work() */
5188}
5189
5190static void e1000_watchdog_task(struct work_struct *work)
5191{
5192 struct e1000_adapter *adapter = container_of(work,
5193 struct e1000_adapter,
5194 watchdog_task);
5195 struct net_device *netdev = adapter->netdev;
5196 struct e1000_mac_info *mac = &adapter->hw.mac;
5197 struct e1000_phy_info *phy = &adapter->hw.phy;
5198 struct e1000_ring *tx_ring = adapter->tx_ring;
5199 u32 dmoff_exit_timeout = 100, tries = 0;
5200 struct e1000_hw *hw = &adapter->hw;
5201 u32 link, tctl, pcim_state;
5202
5203 if (test_bit(__E1000_DOWN, &adapter->state))
5204 return;
5205
5206 link = e1000e_has_link(adapter);
5207 if ((netif_carrier_ok(netdev)) && link) {
5208 /* Cancel scheduled suspend requests. */
5209 pm_runtime_resume(netdev->dev.parent);
5210
5211 e1000e_enable_receives(adapter);
5212 goto link_up;
5213 }
5214
5215 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5216 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5217 e1000_update_mng_vlan(adapter);
5218
5219 if (link) {
5220 if (!netif_carrier_ok(netdev)) {
5221 bool txb2b = true;
5222
5223 /* Cancel scheduled suspend requests. */
5224 pm_runtime_resume(netdev->dev.parent);
5225
5226 /* Checking if MAC is in DMoff state*/
5227 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
5228 pcim_state = er32(STATUS);
5229 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5230 if (tries++ == dmoff_exit_timeout) {
5231 e_dbg("Error in exiting dmoff\n");
5232 break;
5233 }
5234 usleep_range(10000, 20000);
5235 pcim_state = er32(STATUS);
5236
5237 /* Checking if MAC exited DMoff state */
5238 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5239 e1000_phy_hw_reset(&adapter->hw);
5240 }
5241 }
5242
5243 /* update snapshot of PHY registers on LSC */
5244 e1000_phy_read_status(adapter);
5245 mac->ops.get_link_up_info(&adapter->hw,
5246 &adapter->link_speed,
5247 &adapter->link_duplex);
5248 e1000_print_link_info(adapter);
5249
5250 /* check if SmartSpeed worked */
5251 e1000e_check_downshift(hw);
5252 if (phy->speed_downgraded)
5253 netdev_warn(netdev,
5254 "Link Speed was downgraded by SmartSpeed\n");
5255
5256 /* On supported PHYs, check for duplex mismatch only
5257 * if link has autonegotiated at 10/100 half
5258 */
5259 if ((hw->phy.type == e1000_phy_igp_3 ||
5260 hw->phy.type == e1000_phy_bm) &&
5261 hw->mac.autoneg &&
5262 (adapter->link_speed == SPEED_10 ||
5263 adapter->link_speed == SPEED_100) &&
5264 (adapter->link_duplex == HALF_DUPLEX)) {
5265 u16 autoneg_exp;
5266
5267 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
5268
5269 if (!(autoneg_exp & EXPANSION_NWAY))
5270 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5271 }
5272
5273 /* adjust timeout factor according to speed/duplex */
5274 adapter->tx_timeout_factor = 1;
5275 switch (adapter->link_speed) {
5276 case SPEED_10:
5277 txb2b = false;
5278 adapter->tx_timeout_factor = 16;
5279 break;
5280 case SPEED_100:
5281 txb2b = false;
5282 adapter->tx_timeout_factor = 10;
5283 break;
5284 }
5285
5286 /* workaround: re-program speed mode bit after
5287 * link-up event
5288 */
5289 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5290 !txb2b) {
5291 u32 tarc0;
5292
5293 tarc0 = er32(TARC(0));
5294 tarc0 &= ~SPEED_MODE_BIT;
5295 ew32(TARC(0), tarc0);
5296 }
5297
5298 /* disable TSO for pcie and 10/100 speeds, to avoid
5299 * some hardware issues
5300 */
5301 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5302 switch (adapter->link_speed) {
5303 case SPEED_10:
5304 case SPEED_100:
5305 e_info("10/100 speed: disabling TSO\n");
5306 netdev->features &= ~NETIF_F_TSO;
5307 netdev->features &= ~NETIF_F_TSO6;
5308 break;
5309 case SPEED_1000:
5310 netdev->features |= NETIF_F_TSO;
5311 netdev->features |= NETIF_F_TSO6;
5312 break;
5313 default:
5314 /* oops */
5315 break;
5316 }
5317 if (hw->mac.type == e1000_pch_spt) {
5318 netdev->features &= ~NETIF_F_TSO;
5319 netdev->features &= ~NETIF_F_TSO6;
5320 }
5321 }
5322
5323 /* enable transmits in the hardware, need to do this
5324 * after setting TARC(0)
5325 */
5326 tctl = er32(TCTL);
5327 tctl |= E1000_TCTL_EN;
5328 ew32(TCTL, tctl);
5329
5330 /* Perform any post-link-up configuration before
5331 * reporting link up.
5332 */
5333 if (phy->ops.cfg_on_link_up)
5334 phy->ops.cfg_on_link_up(hw);
5335
5336 netif_wake_queue(netdev);
5337 netif_carrier_on(netdev);
5338
5339 if (!test_bit(__E1000_DOWN, &adapter->state))
5340 mod_timer(&adapter->phy_info_timer,
5341 round_jiffies(jiffies + 2 * HZ));
5342 }
5343 } else {
5344 if (netif_carrier_ok(netdev)) {
5345 adapter->link_speed = 0;
5346 adapter->link_duplex = 0;
5347 /* Link status message must follow this format */
5348 netdev_info(netdev, "NIC Link is Down\n");
5349 netif_carrier_off(netdev);
5350 netif_stop_queue(netdev);
5351 if (!test_bit(__E1000_DOWN, &adapter->state))
5352 mod_timer(&adapter->phy_info_timer,
5353 round_jiffies(jiffies + 2 * HZ));
5354
5355 /* 8000ES2LAN requires a Rx packet buffer work-around
5356 * on link down event; reset the controller to flush
5357 * the Rx packet buffer.
5358 */
5359 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
5360 adapter->flags |= FLAG_RESTART_NOW;
5361 else
5362 pm_schedule_suspend(netdev->dev.parent,
5363 LINK_TIMEOUT);
5364 }
5365 }
5366
5367link_up:
5368 spin_lock(&adapter->stats64_lock);
5369 e1000e_update_stats(adapter);
5370
5371 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5372 adapter->tpt_old = adapter->stats.tpt;
5373 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5374 adapter->colc_old = adapter->stats.colc;
5375
5376 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5377 adapter->gorc_old = adapter->stats.gorc;
5378 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5379 adapter->gotc_old = adapter->stats.gotc;
5380 spin_unlock(&adapter->stats64_lock);
5381
5382 /* If the link is lost the controller stops DMA, but
5383 * if there is queued Tx work it cannot be done. So
5384 * reset the controller to flush the Tx packet buffers.
5385 */
5386 if (!netif_carrier_ok(netdev) &&
5387 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5388 adapter->flags |= FLAG_RESTART_NOW;
5389
5390 /* If reset is necessary, do it outside of interrupt context. */
5391 if (adapter->flags & FLAG_RESTART_NOW) {
5392 schedule_work(&adapter->reset_task);
5393 /* return immediately since reset is imminent */
5394 return;
5395 }
5396
5397 e1000e_update_adaptive(&adapter->hw);
5398
5399 /* Simple mode for Interrupt Throttle Rate (ITR) */
5400 if (adapter->itr_setting == 4) {
5401 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5402 * Total asymmetrical Tx or Rx gets ITR=8000;
5403 * everyone else is between 2000-8000.
5404 */
5405 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5406 u32 dif = (adapter->gotc > adapter->gorc ?
5407 adapter->gotc - adapter->gorc :
5408 adapter->gorc - adapter->gotc) / 10000;
5409 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5410
5411 e1000e_write_itr(adapter, itr);
5412 }
5413
5414 /* Cause software interrupt to ensure Rx ring is cleaned */
5415 if (adapter->msix_entries)
5416 ew32(ICS, adapter->rx_ring->ims_val);
5417 else
5418 ew32(ICS, E1000_ICS_RXDMT0);
5419
5420 /* flush pending descriptors to memory before detecting Tx hang */
5421 e1000e_flush_descriptors(adapter);
5422
5423 /* Force detection of hung controller every watchdog period */
5424 adapter->detect_tx_hung = true;
5425
5426 /* With 82571 controllers, LAA may be overwritten due to controller
5427 * reset from the other port. Set the appropriate LAA in RAR[0]
5428 */
5429 if (e1000e_get_laa_state_82571(hw))
5430 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
5431
5432 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5433 e1000e_check_82574_phy_workaround(adapter);
5434
5435 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5436 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5437 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5438 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5439 er32(RXSTMPH);
5440 adapter->rx_hwtstamp_cleared++;
5441 } else {
5442 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5443 }
5444 }
5445
5446 /* Reset the timer */
5447 if (!test_bit(__E1000_DOWN, &adapter->state))
5448 mod_timer(&adapter->watchdog_timer,
5449 round_jiffies(jiffies + 2 * HZ));
5450}
5451
5452#define E1000_TX_FLAGS_CSUM 0x00000001
5453#define E1000_TX_FLAGS_VLAN 0x00000002
5454#define E1000_TX_FLAGS_TSO 0x00000004
5455#define E1000_TX_FLAGS_IPV4 0x00000008
5456#define E1000_TX_FLAGS_NO_FCS 0x00000010
5457#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5458#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5459#define E1000_TX_FLAGS_VLAN_SHIFT 16
5460
5461static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5462 __be16 protocol)
5463{
5464 struct e1000_context_desc *context_desc;
5465 struct e1000_buffer *buffer_info;
5466 unsigned int i;
5467 u32 cmd_length = 0;
5468 u16 ipcse = 0, mss;
5469 u8 ipcss, ipcso, tucss, tucso, hdr_len;
5470 int err;
5471
5472 if (!skb_is_gso(skb))
5473 return 0;
5474
5475 err = skb_cow_head(skb, 0);
5476 if (err < 0)
5477 return err;
5478
5479 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5480 mss = skb_shinfo(skb)->gso_size;
5481 if (protocol == htons(ETH_P_IP)) {
5482 struct iphdr *iph = ip_hdr(skb);
5483 iph->tot_len = 0;
5484 iph->check = 0;
5485 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
5486 0, IPPROTO_TCP, 0);
5487 cmd_length = E1000_TXD_CMD_IP;
5488 ipcse = skb_transport_offset(skb) - 1;
5489 } else if (skb_is_gso_v6(skb)) {
5490 tcp_v6_gso_csum_prep(skb);
5491 ipcse = 0;
5492 }
5493 ipcss = skb_network_offset(skb);
5494 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5495 tucss = skb_transport_offset(skb);
5496 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
5497
5498 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
5499 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
5500
5501 i = tx_ring->next_to_use;
5502 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5503 buffer_info = &tx_ring->buffer_info[i];
5504
5505 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5506 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5507 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
5508 context_desc->upper_setup.tcp_fields.tucss = tucss;
5509 context_desc->upper_setup.tcp_fields.tucso = tucso;
5510 context_desc->upper_setup.tcp_fields.tucse = 0;
5511 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
5512 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5513 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5514
5515 buffer_info->time_stamp = jiffies;
5516 buffer_info->next_to_watch = i;
5517
5518 i++;
5519 if (i == tx_ring->count)
5520 i = 0;
5521 tx_ring->next_to_use = i;
5522
5523 return 1;
5524}
5525
5526static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5527 __be16 protocol)
5528{
5529 struct e1000_adapter *adapter = tx_ring->adapter;
5530 struct e1000_context_desc *context_desc;
5531 struct e1000_buffer *buffer_info;
5532 unsigned int i;
5533 u8 css;
5534 u32 cmd_len = E1000_TXD_CMD_DEXT;
5535
5536 if (skb->ip_summed != CHECKSUM_PARTIAL)
5537 return false;
5538
5539 switch (protocol) {
5540 case cpu_to_be16(ETH_P_IP):
5541 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5542 cmd_len |= E1000_TXD_CMD_TCP;
5543 break;
5544 case cpu_to_be16(ETH_P_IPV6):
5545 /* XXX not handling all IPV6 headers */
5546 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5547 cmd_len |= E1000_TXD_CMD_TCP;
5548 break;
5549 default:
5550 if (unlikely(net_ratelimit()))
5551 e_warn("checksum_partial proto=%x!\n",
5552 be16_to_cpu(protocol));
5553 break;
5554 }
5555
5556 css = skb_checksum_start_offset(skb);
5557
5558 i = tx_ring->next_to_use;
5559 buffer_info = &tx_ring->buffer_info[i];
5560 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5561
5562 context_desc->lower_setup.ip_config = 0;
5563 context_desc->upper_setup.tcp_fields.tucss = css;
5564 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
5565 context_desc->upper_setup.tcp_fields.tucse = 0;
5566 context_desc->tcp_seg_setup.data = 0;
5567 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5568
5569 buffer_info->time_stamp = jiffies;
5570 buffer_info->next_to_watch = i;
5571
5572 i++;
5573 if (i == tx_ring->count)
5574 i = 0;
5575 tx_ring->next_to_use = i;
5576
5577 return true;
5578}
5579
5580static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5581 unsigned int first, unsigned int max_per_txd,
5582 unsigned int nr_frags)
5583{
5584 struct e1000_adapter *adapter = tx_ring->adapter;
5585 struct pci_dev *pdev = adapter->pdev;
5586 struct e1000_buffer *buffer_info;
5587 unsigned int len = skb_headlen(skb);
5588 unsigned int offset = 0, size, count = 0, i;
5589 unsigned int f, bytecount, segs;
5590
5591 i = tx_ring->next_to_use;
5592
5593 while (len) {
5594 buffer_info = &tx_ring->buffer_info[i];
5595 size = min(len, max_per_txd);
5596
5597 buffer_info->length = size;
5598 buffer_info->time_stamp = jiffies;
5599 buffer_info->next_to_watch = i;
5600 buffer_info->dma = dma_map_single(&pdev->dev,
5601 skb->data + offset,
5602 size, DMA_TO_DEVICE);
5603 buffer_info->mapped_as_page = false;
5604 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5605 goto dma_error;
5606
5607 len -= size;
5608 offset += size;
5609 count++;
5610
5611 if (len) {
5612 i++;
5613 if (i == tx_ring->count)
5614 i = 0;
5615 }
5616 }
5617
5618 for (f = 0; f < nr_frags; f++) {
5619 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
5620
5621 len = skb_frag_size(frag);
5622 offset = 0;
5623
5624 while (len) {
5625 i++;
5626 if (i == tx_ring->count)
5627 i = 0;
5628
5629 buffer_info = &tx_ring->buffer_info[i];
5630 size = min(len, max_per_txd);
5631
5632 buffer_info->length = size;
5633 buffer_info->time_stamp = jiffies;
5634 buffer_info->next_to_watch = i;
5635 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
5636 offset, size,
5637 DMA_TO_DEVICE);
5638 buffer_info->mapped_as_page = true;
5639 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
5640 goto dma_error;
5641
5642 len -= size;
5643 offset += size;
5644 count++;
5645 }
5646 }
5647
5648 segs = skb_shinfo(skb)->gso_segs ? : 1;
5649 /* multiply data chunks by size of headers */
5650 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5651
5652 tx_ring->buffer_info[i].skb = skb;
5653 tx_ring->buffer_info[i].segs = segs;
5654 tx_ring->buffer_info[i].bytecount = bytecount;
5655 tx_ring->buffer_info[first].next_to_watch = i;
5656
5657 return count;
5658
5659dma_error:
5660 dev_err(&pdev->dev, "Tx DMA map failed\n");
5661 buffer_info->dma = 0;
5662 if (count)
5663 count--;
5664
5665 while (count--) {
5666 if (i == 0)
5667 i += tx_ring->count;
5668 i--;
5669 buffer_info = &tx_ring->buffer_info[i];
5670 e1000_put_txbuf(tx_ring, buffer_info, true);
5671 }
5672
5673 return 0;
5674}
5675
5676static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
5677{
5678 struct e1000_adapter *adapter = tx_ring->adapter;
5679 struct e1000_tx_desc *tx_desc = NULL;
5680 struct e1000_buffer *buffer_info;
5681 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5682 unsigned int i;
5683
5684 if (tx_flags & E1000_TX_FLAGS_TSO) {
5685 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
5686 E1000_TXD_CMD_TSE;
5687 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5688
5689 if (tx_flags & E1000_TX_FLAGS_IPV4)
5690 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5691 }
5692
5693 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5694 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5695 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5696 }
5697
5698 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5699 txd_lower |= E1000_TXD_CMD_VLE;
5700 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5701 }
5702
5703 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5704 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5705
5706 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5707 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5708 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5709 }
5710
5711 i = tx_ring->next_to_use;
5712
5713 do {
5714 buffer_info = &tx_ring->buffer_info[i];
5715 tx_desc = E1000_TX_DESC(*tx_ring, i);
5716 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
5717 tx_desc->lower.data = cpu_to_le32(txd_lower |
5718 buffer_info->length);
5719 tx_desc->upper.data = cpu_to_le32(txd_upper);
5720
5721 i++;
5722 if (i == tx_ring->count)
5723 i = 0;
5724 } while (--count > 0);
5725
5726 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5727
5728 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5729 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5730 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5731
5732 /* Force memory writes to complete before letting h/w
5733 * know there are new descriptors to fetch. (Only
5734 * applicable for weak-ordered memory model archs,
5735 * such as IA-64).
5736 */
5737 wmb();
5738
5739 tx_ring->next_to_use = i;
5740}
5741
5742#define MINIMUM_DHCP_PACKET_SIZE 282
5743static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5744 struct sk_buff *skb)
5745{
5746 struct e1000_hw *hw = &adapter->hw;
5747 u16 length, offset;
5748
5749 if (skb_vlan_tag_present(skb) &&
5750 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5751 (adapter->hw.mng_cookie.status &
5752 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5753 return 0;
5754
5755 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5756 return 0;
5757
5758 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
5759 return 0;
5760
5761 {
5762 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
5763 struct udphdr *udp;
5764
5765 if (ip->protocol != IPPROTO_UDP)
5766 return 0;
5767
5768 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5769 if (ntohs(udp->dest) != 67)
5770 return 0;
5771
5772 offset = (u8 *)udp + 8 - skb->data;
5773 length = skb->len - offset;
5774 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5775 }
5776
5777 return 0;
5778}
5779
5780static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5781{
5782 struct e1000_adapter *adapter = tx_ring->adapter;
5783
5784 netif_stop_queue(adapter->netdev);
5785 /* Herbert's original patch had:
5786 * smp_mb__after_netif_stop_queue();
5787 * but since that doesn't exist yet, just open code it.
5788 */
5789 smp_mb();
5790
5791 /* We need to check again in a case another CPU has just
5792 * made room available.
5793 */
5794 if (e1000_desc_unused(tx_ring) < size)
5795 return -EBUSY;
5796
5797 /* A reprieve! */
5798 netif_start_queue(adapter->netdev);
5799 ++adapter->restart_queue;
5800 return 0;
5801}
5802
5803static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
5804{
5805 BUG_ON(size > tx_ring->count);
5806
5807 if (e1000_desc_unused(tx_ring) >= size)
5808 return 0;
5809 return __e1000_maybe_stop_tx(tx_ring, size);
5810}
5811
5812static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5813 struct net_device *netdev)
5814{
5815 struct e1000_adapter *adapter = netdev_priv(netdev);
5816 struct e1000_ring *tx_ring = adapter->tx_ring;
5817 unsigned int first;
5818 unsigned int tx_flags = 0;
5819 unsigned int len = skb_headlen(skb);
5820 unsigned int nr_frags;
5821 unsigned int mss;
5822 int count = 0;
5823 int tso;
5824 unsigned int f;
5825 __be16 protocol = vlan_get_protocol(skb);
5826
5827 if (test_bit(__E1000_DOWN, &adapter->state)) {
5828 dev_kfree_skb_any(skb);
5829 return NETDEV_TX_OK;
5830 }
5831
5832 if (skb->len <= 0) {
5833 dev_kfree_skb_any(skb);
5834 return NETDEV_TX_OK;
5835 }
5836
5837 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5838 * pad skb in order to meet this minimum size requirement
5839 */
5840 if (skb_put_padto(skb, 17))
5841 return NETDEV_TX_OK;
5842
5843 mss = skb_shinfo(skb)->gso_size;
5844 if (mss) {
5845 u8 hdr_len;
5846
5847 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5848 * points to just header, pull a few bytes of payload from
5849 * frags into skb->data
5850 */
5851 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5852 /* we do this workaround for ES2LAN, but it is un-necessary,
5853 * avoiding it could save a lot of cycles
5854 */
5855 if (skb->data_len && (hdr_len == len)) {
5856 unsigned int pull_size;
5857
5858 pull_size = min_t(unsigned int, 4, skb->data_len);
5859 if (!__pskb_pull_tail(skb, pull_size)) {
5860 e_err("__pskb_pull_tail failed.\n");
5861 dev_kfree_skb_any(skb);
5862 return NETDEV_TX_OK;
5863 }
5864 len = skb_headlen(skb);
5865 }
5866 }
5867
5868 /* reserve a descriptor for the offload context */
5869 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5870 count++;
5871 count++;
5872
5873 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
5874
5875 nr_frags = skb_shinfo(skb)->nr_frags;
5876 for (f = 0; f < nr_frags; f++)
5877 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5878 adapter->tx_fifo_limit);
5879
5880 if (adapter->hw.mac.tx_pkt_filtering)
5881 e1000_transfer_dhcp_info(adapter, skb);
5882
5883 /* need: count + 2 desc gap to keep tail from touching
5884 * head, otherwise try next time
5885 */
5886 if (e1000_maybe_stop_tx(tx_ring, count + 2))
5887 return NETDEV_TX_BUSY;
5888
5889 if (skb_vlan_tag_present(skb)) {
5890 tx_flags |= E1000_TX_FLAGS_VLAN;
5891 tx_flags |= (skb_vlan_tag_get(skb) <<
5892 E1000_TX_FLAGS_VLAN_SHIFT);
5893 }
5894
5895 first = tx_ring->next_to_use;
5896
5897 tso = e1000_tso(tx_ring, skb, protocol);
5898 if (tso < 0) {
5899 dev_kfree_skb_any(skb);
5900 return NETDEV_TX_OK;
5901 }
5902
5903 if (tso)
5904 tx_flags |= E1000_TX_FLAGS_TSO;
5905 else if (e1000_tx_csum(tx_ring, skb, protocol))
5906 tx_flags |= E1000_TX_FLAGS_CSUM;
5907
5908 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5909 * 82571 hardware supports TSO capabilities for IPv6 as well...
5910 * no longer assume, we must.
5911 */
5912 if (protocol == htons(ETH_P_IP))
5913 tx_flags |= E1000_TX_FLAGS_IPV4;
5914
5915 if (unlikely(skb->no_fcs))
5916 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5917
5918 /* if count is 0 then mapping error has occurred */
5919 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5920 nr_frags);
5921 if (count) {
5922 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5923 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5924 if (!adapter->tx_hwtstamp_skb) {
5925 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5926 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5927 adapter->tx_hwtstamp_skb = skb_get(skb);
5928 adapter->tx_hwtstamp_start = jiffies;
5929 schedule_work(&adapter->tx_hwtstamp_work);
5930 } else {
5931 adapter->tx_hwtstamp_skipped++;
5932 }
5933 }
5934
5935 skb_tx_timestamp(skb);
5936
5937 netdev_sent_queue(netdev, skb->len);
5938 e1000_tx_queue(tx_ring, tx_flags, count);
5939 /* Make sure there is space in the ring for the next send. */
5940 e1000_maybe_stop_tx(tx_ring,
5941 (MAX_SKB_FRAGS *
5942 DIV_ROUND_UP(PAGE_SIZE,
5943 adapter->tx_fifo_limit) + 2));
5944
5945 if (!netdev_xmit_more() ||
5946 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5947 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5948 e1000e_update_tdt_wa(tx_ring,
5949 tx_ring->next_to_use);
5950 else
5951 writel(tx_ring->next_to_use, tx_ring->tail);
5952 }
5953 } else {
5954 dev_kfree_skb_any(skb);
5955 tx_ring->buffer_info[first].time_stamp = 0;
5956 tx_ring->next_to_use = first;
5957 }
5958
5959 return NETDEV_TX_OK;
5960}
5961
5962/**
5963 * e1000_tx_timeout - Respond to a Tx Hang
5964 * @netdev: network interface device structure
5965 * @txqueue: index of the hung queue (unused)
5966 **/
5967static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
5968{
5969 struct e1000_adapter *adapter = netdev_priv(netdev);
5970
5971 /* Do the reset outside of interrupt context */
5972 adapter->tx_timeout_count++;
5973 schedule_work(&adapter->reset_task);
5974}
5975
5976static void e1000_reset_task(struct work_struct *work)
5977{
5978 struct e1000_adapter *adapter;
5979 adapter = container_of(work, struct e1000_adapter, reset_task);
5980
5981 rtnl_lock();
5982 /* don't run the task if already down */
5983 if (test_bit(__E1000_DOWN, &adapter->state)) {
5984 rtnl_unlock();
5985 return;
5986 }
5987
5988 if (!(adapter->flags & FLAG_RESTART_NOW)) {
5989 e1000e_dump(adapter);
5990 e_err("Reset adapter unexpectedly\n");
5991 }
5992 e1000e_reinit_locked(adapter);
5993 rtnl_unlock();
5994}
5995
5996/**
5997 * e1000e_get_stats64 - Get System Network Statistics
5998 * @netdev: network interface device structure
5999 * @stats: rtnl_link_stats64 pointer
6000 *
6001 * Returns the address of the device statistics structure.
6002 **/
6003void e1000e_get_stats64(struct net_device *netdev,
6004 struct rtnl_link_stats64 *stats)
6005{
6006 struct e1000_adapter *adapter = netdev_priv(netdev);
6007
6008 spin_lock(&adapter->stats64_lock);
6009 e1000e_update_stats(adapter);
6010 /* Fill out the OS statistics structure */
6011 stats->rx_bytes = adapter->stats.gorc;
6012 stats->rx_packets = adapter->stats.gprc;
6013 stats->tx_bytes = adapter->stats.gotc;
6014 stats->tx_packets = adapter->stats.gptc;
6015 stats->multicast = adapter->stats.mprc;
6016 stats->collisions = adapter->stats.colc;
6017
6018 /* Rx Errors */
6019
6020 /* RLEC on some newer hardware can be incorrect so build
6021 * our own version based on RUC and ROC
6022 */
6023 stats->rx_errors = adapter->stats.rxerrc +
6024 adapter->stats.crcerrs + adapter->stats.algnerrc +
6025 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
6026 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
6027 stats->rx_crc_errors = adapter->stats.crcerrs;
6028 stats->rx_frame_errors = adapter->stats.algnerrc;
6029 stats->rx_missed_errors = adapter->stats.mpc;
6030
6031 /* Tx Errors */
6032 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
6033 stats->tx_aborted_errors = adapter->stats.ecol;
6034 stats->tx_window_errors = adapter->stats.latecol;
6035 stats->tx_carrier_errors = adapter->stats.tncrs;
6036
6037 /* Tx Dropped needs to be maintained elsewhere */
6038
6039 spin_unlock(&adapter->stats64_lock);
6040}
6041
6042/**
6043 * e1000_change_mtu - Change the Maximum Transfer Unit
6044 * @netdev: network interface device structure
6045 * @new_mtu: new value for maximum frame size
6046 *
6047 * Returns 0 on success, negative on failure
6048 **/
6049static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6050{
6051 struct e1000_adapter *adapter = netdev_priv(netdev);
6052 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
6053
6054 /* Jumbo frame support */
6055 if ((new_mtu > ETH_DATA_LEN) &&
6056 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6057 e_err("Jumbo Frames not supported.\n");
6058 return -EINVAL;
6059 }
6060
6061 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6062 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
6063 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6064 (new_mtu > ETH_DATA_LEN)) {
6065 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
6066 return -EINVAL;
6067 }
6068
6069 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
6070 usleep_range(1000, 1100);
6071 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6072 adapter->max_frame_size = max_frame;
6073 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6074 netdev->mtu, new_mtu);
6075 netdev->mtu = new_mtu;
6076
6077 pm_runtime_get_sync(netdev->dev.parent);
6078
6079 if (netif_running(netdev))
6080 e1000e_down(adapter, true);
6081
6082 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6083 * means we reserve 2 more, this pushes us to allocate from the next
6084 * larger slab size.
6085 * i.e. RXBUFFER_2048 --> size-4096 slab
6086 * However with the new *_jumbo_rx* routines, jumbo receives will use
6087 * fragmented skbs
6088 */
6089
6090 if (max_frame <= 2048)
6091 adapter->rx_buffer_len = 2048;
6092 else
6093 adapter->rx_buffer_len = 4096;
6094
6095 /* adjust allocation if LPE protects us, and we aren't using SBP */
6096 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6097 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
6098
6099 if (netif_running(netdev))
6100 e1000e_up(adapter);
6101 else
6102 e1000e_reset(adapter);
6103
6104 pm_runtime_put_sync(netdev->dev.parent);
6105
6106 clear_bit(__E1000_RESETTING, &adapter->state);
6107
6108 return 0;
6109}
6110
6111static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6112 int cmd)
6113{
6114 struct e1000_adapter *adapter = netdev_priv(netdev);
6115 struct mii_ioctl_data *data = if_mii(ifr);
6116
6117 if (adapter->hw.phy.media_type != e1000_media_type_copper)
6118 return -EOPNOTSUPP;
6119
6120 switch (cmd) {
6121 case SIOCGMIIPHY:
6122 data->phy_id = adapter->hw.phy.addr;
6123 break;
6124 case SIOCGMIIREG:
6125 e1000_phy_read_status(adapter);
6126
6127 switch (data->reg_num & 0x1F) {
6128 case MII_BMCR:
6129 data->val_out = adapter->phy_regs.bmcr;
6130 break;
6131 case MII_BMSR:
6132 data->val_out = adapter->phy_regs.bmsr;
6133 break;
6134 case MII_PHYSID1:
6135 data->val_out = (adapter->hw.phy.id >> 16);
6136 break;
6137 case MII_PHYSID2:
6138 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6139 break;
6140 case MII_ADVERTISE:
6141 data->val_out = adapter->phy_regs.advertise;
6142 break;
6143 case MII_LPA:
6144 data->val_out = adapter->phy_regs.lpa;
6145 break;
6146 case MII_EXPANSION:
6147 data->val_out = adapter->phy_regs.expansion;
6148 break;
6149 case MII_CTRL1000:
6150 data->val_out = adapter->phy_regs.ctrl1000;
6151 break;
6152 case MII_STAT1000:
6153 data->val_out = adapter->phy_regs.stat1000;
6154 break;
6155 case MII_ESTATUS:
6156 data->val_out = adapter->phy_regs.estatus;
6157 break;
6158 default:
6159 return -EIO;
6160 }
6161 break;
6162 case SIOCSMIIREG:
6163 default:
6164 return -EOPNOTSUPP;
6165 }
6166 return 0;
6167}
6168
6169/**
6170 * e1000e_hwtstamp_set - control hardware time stamping
6171 * @netdev: network interface device structure
6172 * @ifr: interface request
6173 *
6174 * Outgoing time stamping can be enabled and disabled. Play nice and
6175 * disable it when requested, although it shouldn't cause any overhead
6176 * when no packet needs it. At most one packet in the queue may be
6177 * marked for time stamping, otherwise it would be impossible to tell
6178 * for sure to which packet the hardware time stamp belongs.
6179 *
6180 * Incoming time stamping has to be configured via the hardware filters.
6181 * Not all combinations are supported, in particular event type has to be
6182 * specified. Matching the kind of event packet is not supported, with the
6183 * exception of "all V2 events regardless of level 2 or 4".
6184 **/
6185static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
6186{
6187 struct e1000_adapter *adapter = netdev_priv(netdev);
6188 struct hwtstamp_config config;
6189 int ret_val;
6190
6191 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6192 return -EFAULT;
6193
6194 ret_val = e1000e_config_hwtstamp(adapter, &config);
6195 if (ret_val)
6196 return ret_val;
6197
6198 switch (config.rx_filter) {
6199 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6200 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6201 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6202 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6203 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6204 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6205 /* With V2 type filters which specify a Sync or Delay Request,
6206 * Path Delay Request/Response messages are also time stamped
6207 * by hardware so notify the caller the requested packets plus
6208 * some others are time stamped.
6209 */
6210 config.rx_filter = HWTSTAMP_FILTER_SOME;
6211 break;
6212 default:
6213 break;
6214 }
6215
6216 return copy_to_user(ifr->ifr_data, &config,
6217 sizeof(config)) ? -EFAULT : 0;
6218}
6219
6220static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6221{
6222 struct e1000_adapter *adapter = netdev_priv(netdev);
6223
6224 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6225 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6226}
6227
6228static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6229{
6230 switch (cmd) {
6231 case SIOCGMIIPHY:
6232 case SIOCGMIIREG:
6233 case SIOCSMIIREG:
6234 return e1000_mii_ioctl(netdev, ifr, cmd);
6235 case SIOCSHWTSTAMP:
6236 return e1000e_hwtstamp_set(netdev, ifr);
6237 case SIOCGHWTSTAMP:
6238 return e1000e_hwtstamp_get(netdev, ifr);
6239 default:
6240 return -EOPNOTSUPP;
6241 }
6242}
6243
6244static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6245{
6246 struct e1000_hw *hw = &adapter->hw;
6247 u32 i, mac_reg, wuc;
6248 u16 phy_reg, wuc_enable;
6249 int retval;
6250
6251 /* copy MAC RARs to PHY RARs */
6252 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
6253
6254 retval = hw->phy.ops.acquire(hw);
6255 if (retval) {
6256 e_err("Could not acquire PHY\n");
6257 return retval;
6258 }
6259
6260 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6261 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6262 if (retval)
6263 goto release;
6264
6265 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6266 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6267 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
6268 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6269 (u16)(mac_reg & 0xFFFF));
6270 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6271 (u16)((mac_reg >> 16) & 0xFFFF));
6272 }
6273
6274 /* configure PHY Rx Control register */
6275 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
6276 mac_reg = er32(RCTL);
6277 if (mac_reg & E1000_RCTL_UPE)
6278 phy_reg |= BM_RCTL_UPE;
6279 if (mac_reg & E1000_RCTL_MPE)
6280 phy_reg |= BM_RCTL_MPE;
6281 phy_reg &= ~(BM_RCTL_MO_MASK);
6282 if (mac_reg & E1000_RCTL_MO_3)
6283 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
6284 << BM_RCTL_MO_SHIFT);
6285 if (mac_reg & E1000_RCTL_BAM)
6286 phy_reg |= BM_RCTL_BAM;
6287 if (mac_reg & E1000_RCTL_PMCF)
6288 phy_reg |= BM_RCTL_PMCF;
6289 mac_reg = er32(CTRL);
6290 if (mac_reg & E1000_CTRL_RFCE)
6291 phy_reg |= BM_RCTL_RFCE;
6292 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
6293
6294 wuc = E1000_WUC_PME_EN;
6295 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6296 wuc |= E1000_WUC_APME;
6297
6298 /* enable PHY wakeup in MAC register */
6299 ew32(WUFC, wufc);
6300 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6301 E1000_WUC_PME_STATUS | wuc));
6302
6303 /* configure and enable PHY wakeup in PHY registers */
6304 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
6305 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
6306
6307 /* activate PHY wakeup */
6308 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6309 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6310 if (retval)
6311 e_err("Could not set PHY Host Wakeup bit\n");
6312release:
6313 hw->phy.ops.release(hw);
6314
6315 return retval;
6316}
6317
6318static void e1000e_flush_lpic(struct pci_dev *pdev)
6319{
6320 struct net_device *netdev = pci_get_drvdata(pdev);
6321 struct e1000_adapter *adapter = netdev_priv(netdev);
6322 struct e1000_hw *hw = &adapter->hw;
6323 u32 ret_val;
6324
6325 pm_runtime_get_sync(netdev->dev.parent);
6326
6327 ret_val = hw->phy.ops.acquire(hw);
6328 if (ret_val)
6329 goto fl_out;
6330
6331 pr_info("EEE TX LPI TIMER: %08X\n",
6332 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6333
6334 hw->phy.ops.release(hw);
6335
6336fl_out:
6337 pm_runtime_put_sync(netdev->dev.parent);
6338}
6339
6340/* S0ix implementation */
6341static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6342{
6343 struct e1000_hw *hw = &adapter->hw;
6344 u32 mac_data;
6345 u16 phy_data;
6346
6347 /* Disable the periodic inband message,
6348 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6349 */
6350 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6351 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6352 phy_data |= BIT(10);
6353 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6354
6355 /* Make sure we don't exit K1 every time a new packet arrives
6356 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6357 */
6358 e1e_rphy(hw, I217_CGFREG, &phy_data);
6359 phy_data |= BIT(5);
6360 e1e_wphy(hw, I217_CGFREG, phy_data);
6361
6362 /* Change the MAC/PHY interface to SMBus
6363 * Force the SMBus in PHY page769_23[0] = 1
6364 * Force the SMBus in MAC CTRL_EXT[11] = 1
6365 */
6366 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6367 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6368 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6369 mac_data = er32(CTRL_EXT);
6370 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6371 ew32(CTRL_EXT, mac_data);
6372
6373 /* DFT control: PHY bit: page769_20[0] = 1
6374 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6375 */
6376 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6377 phy_data |= BIT(0);
6378 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6379
6380 mac_data = er32(EXTCNF_CTRL);
6381 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6382 ew32(EXTCNF_CTRL, mac_data);
6383
6384 /* Check MAC Tx/Rx packet buffer pointers.
6385 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6386 * pending traffic indication that would prevent power gating.
6387 */
6388 mac_data = er32(TDFH);
6389 if (mac_data)
6390 ew32(TDFH, 0);
6391 mac_data = er32(TDFT);
6392 if (mac_data)
6393 ew32(TDFT, 0);
6394 mac_data = er32(TDFHS);
6395 if (mac_data)
6396 ew32(TDFHS, 0);
6397 mac_data = er32(TDFTS);
6398 if (mac_data)
6399 ew32(TDFTS, 0);
6400 mac_data = er32(TDFPC);
6401 if (mac_data)
6402 ew32(TDFPC, 0);
6403 mac_data = er32(RDFH);
6404 if (mac_data)
6405 ew32(RDFH, 0);
6406 mac_data = er32(RDFT);
6407 if (mac_data)
6408 ew32(RDFT, 0);
6409 mac_data = er32(RDFHS);
6410 if (mac_data)
6411 ew32(RDFHS, 0);
6412 mac_data = er32(RDFTS);
6413 if (mac_data)
6414 ew32(RDFTS, 0);
6415 mac_data = er32(RDFPC);
6416 if (mac_data)
6417 ew32(RDFPC, 0);
6418
6419 /* Enable the Dynamic Power Gating in the MAC */
6420 mac_data = er32(FEXTNVM7);
6421 mac_data |= BIT(22);
6422 ew32(FEXTNVM7, mac_data);
6423
6424 /* Disable the time synchronization clock */
6425 mac_data = er32(FEXTNVM7);
6426 mac_data |= BIT(31);
6427 mac_data &= ~BIT(0);
6428 ew32(FEXTNVM7, mac_data);
6429
6430 /* Dynamic Power Gating Enable */
6431 mac_data = er32(CTRL_EXT);
6432 mac_data |= BIT(3);
6433 ew32(CTRL_EXT, mac_data);
6434
6435 /* Disable disconnected cable conditioning for Power Gating */
6436 mac_data = er32(DPGFR);
6437 mac_data |= BIT(2);
6438 ew32(DPGFR, mac_data);
6439
6440 /* Don't wake from dynamic Power Gating with clock request */
6441 mac_data = er32(FEXTNVM12);
6442 mac_data |= BIT(12);
6443 ew32(FEXTNVM12, mac_data);
6444
6445 /* Ungate PGCB clock */
6446 mac_data = er32(FEXTNVM9);
6447 mac_data &= ~BIT(28);
6448 ew32(FEXTNVM9, mac_data);
6449
6450 /* Enable K1 off to enable mPHY Power Gating */
6451 mac_data = er32(FEXTNVM6);
6452 mac_data |= BIT(31);
6453 ew32(FEXTNVM6, mac_data);
6454
6455 /* Enable mPHY power gating for any link and speed */
6456 mac_data = er32(FEXTNVM8);
6457 mac_data |= BIT(9);
6458 ew32(FEXTNVM8, mac_data);
6459
6460 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6461 mac_data = er32(CTRL_EXT);
6462 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6463 ew32(CTRL_EXT, mac_data);
6464
6465 /* No MAC DPG gating SLP_S0 in modern standby
6466 * Switch the logic of the lanphypc to use PMC counter
6467 */
6468 mac_data = er32(FEXTNVM5);
6469 mac_data |= BIT(7);
6470 ew32(FEXTNVM5, mac_data);
6471}
6472
6473static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6474{
6475 struct e1000_hw *hw = &adapter->hw;
6476 u32 mac_data;
6477 u16 phy_data;
6478
6479 /* Disable the Dynamic Power Gating in the MAC */
6480 mac_data = er32(FEXTNVM7);
6481 mac_data &= 0xFFBFFFFF;
6482 ew32(FEXTNVM7, mac_data);
6483
6484 /* Enable the time synchronization clock */
6485 mac_data = er32(FEXTNVM7);
6486 mac_data |= BIT(0);
6487 ew32(FEXTNVM7, mac_data);
6488
6489 /* Disable mPHY power gating for any link and speed */
6490 mac_data = er32(FEXTNVM8);
6491 mac_data &= ~BIT(9);
6492 ew32(FEXTNVM8, mac_data);
6493
6494 /* Disable K1 off */
6495 mac_data = er32(FEXTNVM6);
6496 mac_data &= ~BIT(31);
6497 ew32(FEXTNVM6, mac_data);
6498
6499 /* Disable Ungate PGCB clock */
6500 mac_data = er32(FEXTNVM9);
6501 mac_data |= BIT(28);
6502 ew32(FEXTNVM9, mac_data);
6503
6504 /* Cancel not waking from dynamic
6505 * Power Gating with clock request
6506 */
6507 mac_data = er32(FEXTNVM12);
6508 mac_data &= ~BIT(12);
6509 ew32(FEXTNVM12, mac_data);
6510
6511 /* Cancel disable disconnected cable conditioning
6512 * for Power Gating
6513 */
6514 mac_data = er32(DPGFR);
6515 mac_data &= ~BIT(2);
6516 ew32(DPGFR, mac_data);
6517
6518 /* Disable Dynamic Power Gating */
6519 mac_data = er32(CTRL_EXT);
6520 mac_data &= 0xFFFFFFF7;
6521 ew32(CTRL_EXT, mac_data);
6522
6523 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6524 mac_data = er32(CTRL_EXT);
6525 mac_data &= 0xFFF7FFFF;
6526 ew32(CTRL_EXT, mac_data);
6527
6528 /* Revert the lanphypc logic to use the internal Gbe counter
6529 * and not the PMC counter
6530 */
6531 mac_data = er32(FEXTNVM5);
6532 mac_data &= 0xFFFFFF7F;
6533 ew32(FEXTNVM5, mac_data);
6534
6535 /* Enable the periodic inband message,
6536 * Request PCIe clock in K1 page770_17[10:9] =01b
6537 */
6538 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6539 phy_data &= 0xFBFF;
6540 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6541 e1e_wphy(hw, HV_PM_CTRL, phy_data);
6542
6543 /* Return back configuration
6544 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6545 */
6546 e1e_rphy(hw, I217_CGFREG, &phy_data);
6547 phy_data &= 0xFFDF;
6548 e1e_wphy(hw, I217_CGFREG, phy_data);
6549
6550 /* Change the MAC/PHY interface to Kumeran
6551 * Unforce the SMBus in PHY page769_23[0] = 0
6552 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6553 */
6554 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6555 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6556 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6557 mac_data = er32(CTRL_EXT);
6558 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6559 ew32(CTRL_EXT, mac_data);
6560}
6561
6562static int e1000e_pm_freeze(struct device *dev)
6563{
6564 struct net_device *netdev = dev_get_drvdata(dev);
6565 struct e1000_adapter *adapter = netdev_priv(netdev);
6566 bool present;
6567
6568 rtnl_lock();
6569
6570 present = netif_device_present(netdev);
6571 netif_device_detach(netdev);
6572
6573 if (present && netif_running(netdev)) {
6574 int count = E1000_CHECK_RESET_COUNT;
6575
6576 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6577 usleep_range(10000, 11000);
6578
6579 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6580
6581 /* Quiesce the device without resetting the hardware */
6582 e1000e_down(adapter, false);
6583 e1000_free_irq(adapter);
6584 }
6585 rtnl_unlock();
6586
6587 e1000e_reset_interrupt_capability(adapter);
6588
6589 /* Allow time for pending master requests to run */
6590 e1000e_disable_pcie_master(&adapter->hw);
6591
6592 return 0;
6593}
6594
6595static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6596{
6597 struct net_device *netdev = pci_get_drvdata(pdev);
6598 struct e1000_adapter *adapter = netdev_priv(netdev);
6599 struct e1000_hw *hw = &adapter->hw;
6600 u32 ctrl, ctrl_ext, rctl, status, wufc;
6601 int retval = 0;
6602
6603 /* Runtime suspend should only enable wakeup for link changes */
6604 if (runtime)
6605 wufc = E1000_WUFC_LNKC;
6606 else if (device_may_wakeup(&pdev->dev))
6607 wufc = adapter->wol;
6608 else
6609 wufc = 0;
6610
6611 status = er32(STATUS);
6612 if (status & E1000_STATUS_LU)
6613 wufc &= ~E1000_WUFC_LNKC;
6614
6615 if (wufc) {
6616 e1000_setup_rctl(adapter);
6617 e1000e_set_rx_mode(netdev);
6618
6619 /* turn on all-multi mode if wake on multicast is enabled */
6620 if (wufc & E1000_WUFC_MC) {
6621 rctl = er32(RCTL);
6622 rctl |= E1000_RCTL_MPE;
6623 ew32(RCTL, rctl);
6624 }
6625
6626 ctrl = er32(CTRL);
6627 ctrl |= E1000_CTRL_ADVD3WUC;
6628 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6629 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
6630 ew32(CTRL, ctrl);
6631
6632 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6633 adapter->hw.phy.media_type ==
6634 e1000_media_type_internal_serdes) {
6635 /* keep the laser running in D3 */
6636 ctrl_ext = er32(CTRL_EXT);
6637 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
6638 ew32(CTRL_EXT, ctrl_ext);
6639 }
6640
6641 if (!runtime)
6642 e1000e_power_up_phy(adapter);
6643
6644 if (adapter->flags & FLAG_IS_ICH)
6645 e1000_suspend_workarounds_ich8lan(&adapter->hw);
6646
6647 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6648 /* enable wakeup by the PHY */
6649 retval = e1000_init_phy_wakeup(adapter, wufc);
6650 if (retval)
6651 return retval;
6652 } else {
6653 /* enable wakeup by the MAC */
6654 ew32(WUFC, wufc);
6655 ew32(WUC, E1000_WUC_PME_EN);
6656 }
6657 } else {
6658 ew32(WUC, 0);
6659 ew32(WUFC, 0);
6660
6661 e1000_power_down_phy(adapter);
6662 }
6663
6664 if (adapter->hw.phy.type == e1000_phy_igp_3) {
6665 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
6666 } else if (hw->mac.type >= e1000_pch_lpt) {
6667 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6668 /* ULP does not support wake from unicast, multicast
6669 * or broadcast.
6670 */
6671 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6672
6673 if (retval)
6674 return retval;
6675 }
6676
6677 /* Ensure that the appropriate bits are set in LPI_CTRL
6678 * for EEE in Sx
6679 */
6680 if ((hw->phy.type >= e1000_phy_i217) &&
6681 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6682 u16 lpi_ctrl = 0;
6683
6684 retval = hw->phy.ops.acquire(hw);
6685 if (!retval) {
6686 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6687 &lpi_ctrl);
6688 if (!retval) {
6689 if (adapter->eee_advert &
6690 hw->dev_spec.ich8lan.eee_lp_ability &
6691 I82579_EEE_100_SUPPORTED)
6692 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6693 if (adapter->eee_advert &
6694 hw->dev_spec.ich8lan.eee_lp_ability &
6695 I82579_EEE_1000_SUPPORTED)
6696 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6697
6698 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6699 lpi_ctrl);
6700 }
6701 }
6702 hw->phy.ops.release(hw);
6703 }
6704
6705 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6706 * would have already happened in close and is redundant.
6707 */
6708 e1000e_release_hw_control(adapter);
6709
6710 pci_clear_master(pdev);
6711
6712 /* The pci-e switch on some quad port adapters will report a
6713 * correctable error when the MAC transitions from D0 to D3. To
6714 * prevent this we need to mask off the correctable errors on the
6715 * downstream port of the pci-e switch.
6716 *
6717 * We don't have the associated upstream bridge while assigning
6718 * the PCI device into guest. For example, the KVM on power is
6719 * one of the cases.
6720 */
6721 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6722 struct pci_dev *us_dev = pdev->bus->self;
6723 u16 devctl;
6724
6725 if (!us_dev)
6726 return 0;
6727
6728 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6729 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6730 (devctl & ~PCI_EXP_DEVCTL_CERE));
6731
6732 pci_save_state(pdev);
6733 pci_prepare_to_sleep(pdev);
6734
6735 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
6736 }
6737
6738 return 0;
6739}
6740
6741/**
6742 * __e1000e_disable_aspm - Disable ASPM states
6743 * @pdev: pointer to PCI device struct
6744 * @state: bit-mask of ASPM states to disable
6745 * @locked: indication if this context holds pci_bus_sem locked.
6746 *
6747 * Some devices *must* have certain ASPM states disabled per hardware errata.
6748 **/
6749static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6750{
6751 struct pci_dev *parent = pdev->bus->self;
6752 u16 aspm_dis_mask = 0;
6753 u16 pdev_aspmc, parent_aspmc;
6754
6755 switch (state) {
6756 case PCIE_LINK_STATE_L0S:
6757 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6758 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6759 fallthrough; /* can't have L1 without L0s */
6760 case PCIE_LINK_STATE_L1:
6761 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6762 break;
6763 default:
6764 return;
6765 }
6766
6767 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6768 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6769
6770 if (parent) {
6771 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6772 &parent_aspmc);
6773 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6774 }
6775
6776 /* Nothing to do if the ASPM states to be disabled already are */
6777 if (!(pdev_aspmc & aspm_dis_mask) &&
6778 (!parent || !(parent_aspmc & aspm_dis_mask)))
6779 return;
6780
6781 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6782 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6783 "L0s" : "",
6784 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6785 "L1" : "");
6786
6787#ifdef CONFIG_PCIEASPM
6788 if (locked)
6789 pci_disable_link_state_locked(pdev, state);
6790 else
6791 pci_disable_link_state(pdev, state);
6792
6793 /* Double-check ASPM control. If not disabled by the above, the
6794 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6795 * not enabled); override by writing PCI config space directly.
6796 */
6797 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6798 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6799
6800 if (!(aspm_dis_mask & pdev_aspmc))
6801 return;
6802#endif
6803
6804 /* Both device and parent should have the same ASPM setting.
6805 * Disable ASPM in downstream component first and then upstream.
6806 */
6807 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6808
6809 if (parent)
6810 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6811 aspm_dis_mask);
6812}
6813
6814/**
6815 * e1000e_disable_aspm - Disable ASPM states.
6816 * @pdev: pointer to PCI device struct
6817 * @state: bit-mask of ASPM states to disable
6818 *
6819 * This function acquires the pci_bus_sem!
6820 * Some devices *must* have certain ASPM states disabled per hardware errata.
6821 **/
6822static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6823{
6824 __e1000e_disable_aspm(pdev, state, 0);
6825}
6826
6827/**
6828 * e1000e_disable_aspm_locked - Disable ASPM states.
6829 * @pdev: pointer to PCI device struct
6830 * @state: bit-mask of ASPM states to disable
6831 *
6832 * This function must be called with pci_bus_sem acquired!
6833 * Some devices *must* have certain ASPM states disabled per hardware errata.
6834 **/
6835static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6836{
6837 __e1000e_disable_aspm(pdev, state, 1);
6838}
6839
6840static int e1000e_pm_thaw(struct device *dev)
6841{
6842 struct net_device *netdev = dev_get_drvdata(dev);
6843 struct e1000_adapter *adapter = netdev_priv(netdev);
6844 int rc = 0;
6845
6846 e1000e_set_interrupt_capability(adapter);
6847
6848 rtnl_lock();
6849 if (netif_running(netdev)) {
6850 rc = e1000_request_irq(adapter);
6851 if (rc)
6852 goto err_irq;
6853
6854 e1000e_up(adapter);
6855 }
6856
6857 netif_device_attach(netdev);
6858err_irq:
6859 rtnl_unlock();
6860
6861 return rc;
6862}
6863
6864static int __e1000_resume(struct pci_dev *pdev)
6865{
6866 struct net_device *netdev = pci_get_drvdata(pdev);
6867 struct e1000_adapter *adapter = netdev_priv(netdev);
6868 struct e1000_hw *hw = &adapter->hw;
6869 u16 aspm_disable_flag = 0;
6870
6871 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6872 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6873 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6874 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6875 if (aspm_disable_flag)
6876 e1000e_disable_aspm(pdev, aspm_disable_flag);
6877
6878 pci_set_master(pdev);
6879
6880 if (hw->mac.type >= e1000_pch2lan)
6881 e1000_resume_workarounds_pchlan(&adapter->hw);
6882
6883 e1000e_power_up_phy(adapter);
6884
6885 /* report the system wakeup cause from S3/S4 */
6886 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6887 u16 phy_data;
6888
6889 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6890 if (phy_data) {
6891 e_info("PHY Wakeup cause - %s\n",
6892 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6893 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6894 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6895 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6896 phy_data & E1000_WUS_LNKC ?
6897 "Link Status Change" : "other");
6898 }
6899 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6900 } else {
6901 u32 wus = er32(WUS);
6902
6903 if (wus) {
6904 e_info("MAC Wakeup cause - %s\n",
6905 wus & E1000_WUS_EX ? "Unicast Packet" :
6906 wus & E1000_WUS_MC ? "Multicast Packet" :
6907 wus & E1000_WUS_BC ? "Broadcast Packet" :
6908 wus & E1000_WUS_MAG ? "Magic Packet" :
6909 wus & E1000_WUS_LNKC ? "Link Status Change" :
6910 "other");
6911 }
6912 ew32(WUS, ~0);
6913 }
6914
6915 e1000e_reset(adapter);
6916
6917 e1000_init_manageability_pt(adapter);
6918
6919 /* If the controller has AMT, do not set DRV_LOAD until the interface
6920 * is up. For all other cases, let the f/w know that the h/w is now
6921 * under the control of the driver.
6922 */
6923 if (!(adapter->flags & FLAG_HAS_AMT))
6924 e1000e_get_hw_control(adapter);
6925
6926 return 0;
6927}
6928
6929static __maybe_unused int e1000e_pm_prepare(struct device *dev)
6930{
6931 return pm_runtime_suspended(dev) &&
6932 pm_suspend_via_firmware();
6933}
6934
6935static __maybe_unused int e1000e_pm_suspend(struct device *dev)
6936{
6937 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6938 struct e1000_adapter *adapter = netdev_priv(netdev);
6939 struct pci_dev *pdev = to_pci_dev(dev);
6940 int rc;
6941
6942 e1000e_flush_lpic(pdev);
6943
6944 e1000e_pm_freeze(dev);
6945
6946 rc = __e1000_shutdown(pdev, false);
6947 if (rc) {
6948 e1000e_pm_thaw(dev);
6949 } else {
6950 /* Introduce S0ix implementation */
6951 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6952 e1000e_s0ix_entry_flow(adapter);
6953 }
6954
6955 return rc;
6956}
6957
6958static __maybe_unused int e1000e_pm_resume(struct device *dev)
6959{
6960 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6961 struct e1000_adapter *adapter = netdev_priv(netdev);
6962 struct pci_dev *pdev = to_pci_dev(dev);
6963 int rc;
6964
6965 /* Introduce S0ix implementation */
6966 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
6967 e1000e_s0ix_exit_flow(adapter);
6968
6969 rc = __e1000_resume(pdev);
6970 if (rc)
6971 return rc;
6972
6973 return e1000e_pm_thaw(dev);
6974}
6975
6976static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
6977{
6978 struct net_device *netdev = dev_get_drvdata(dev);
6979 struct e1000_adapter *adapter = netdev_priv(netdev);
6980 u16 eee_lp;
6981
6982 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6983
6984 if (!e1000e_has_link(adapter)) {
6985 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
6986 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
6987 }
6988
6989 return -EBUSY;
6990}
6991
6992static __maybe_unused int e1000e_pm_runtime_resume(struct device *dev)
6993{
6994 struct pci_dev *pdev = to_pci_dev(dev);
6995 struct net_device *netdev = pci_get_drvdata(pdev);
6996 struct e1000_adapter *adapter = netdev_priv(netdev);
6997 int rc;
6998
6999 rc = __e1000_resume(pdev);
7000 if (rc)
7001 return rc;
7002
7003 if (netdev->flags & IFF_UP)
7004 e1000e_up(adapter);
7005
7006 return rc;
7007}
7008
7009static __maybe_unused int e1000e_pm_runtime_suspend(struct device *dev)
7010{
7011 struct pci_dev *pdev = to_pci_dev(dev);
7012 struct net_device *netdev = pci_get_drvdata(pdev);
7013 struct e1000_adapter *adapter = netdev_priv(netdev);
7014
7015 if (netdev->flags & IFF_UP) {
7016 int count = E1000_CHECK_RESET_COUNT;
7017
7018 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
7019 usleep_range(10000, 11000);
7020
7021 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7022
7023 /* Down the device without resetting the hardware */
7024 e1000e_down(adapter, false);
7025 }
7026
7027 if (__e1000_shutdown(pdev, true)) {
7028 e1000e_pm_runtime_resume(dev);
7029 return -EBUSY;
7030 }
7031
7032 return 0;
7033}
7034
7035static void e1000_shutdown(struct pci_dev *pdev)
7036{
7037 e1000e_flush_lpic(pdev);
7038
7039 e1000e_pm_freeze(&pdev->dev);
7040
7041 __e1000_shutdown(pdev, false);
7042}
7043
7044#ifdef CONFIG_NET_POLL_CONTROLLER
7045
7046static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
7047{
7048 struct net_device *netdev = data;
7049 struct e1000_adapter *adapter = netdev_priv(netdev);
7050
7051 if (adapter->msix_entries) {
7052 int vector, msix_irq;
7053
7054 vector = 0;
7055 msix_irq = adapter->msix_entries[vector].vector;
7056 if (disable_hardirq(msix_irq))
7057 e1000_intr_msix_rx(msix_irq, netdev);
7058 enable_irq(msix_irq);
7059
7060 vector++;
7061 msix_irq = adapter->msix_entries[vector].vector;
7062 if (disable_hardirq(msix_irq))
7063 e1000_intr_msix_tx(msix_irq, netdev);
7064 enable_irq(msix_irq);
7065
7066 vector++;
7067 msix_irq = adapter->msix_entries[vector].vector;
7068 if (disable_hardirq(msix_irq))
7069 e1000_msix_other(msix_irq, netdev);
7070 enable_irq(msix_irq);
7071 }
7072
7073 return IRQ_HANDLED;
7074}
7075
7076/**
7077 * e1000_netpoll
7078 * @netdev: network interface device structure
7079 *
7080 * Polling 'interrupt' - used by things like netconsole to send skbs
7081 * without having to re-enable interrupts. It's not called while
7082 * the interrupt routine is executing.
7083 */
7084static void e1000_netpoll(struct net_device *netdev)
7085{
7086 struct e1000_adapter *adapter = netdev_priv(netdev);
7087
7088 switch (adapter->int_mode) {
7089 case E1000E_INT_MODE_MSIX:
7090 e1000_intr_msix(adapter->pdev->irq, netdev);
7091 break;
7092 case E1000E_INT_MODE_MSI:
7093 if (disable_hardirq(adapter->pdev->irq))
7094 e1000_intr_msi(adapter->pdev->irq, netdev);
7095 enable_irq(adapter->pdev->irq);
7096 break;
7097 default: /* E1000E_INT_MODE_LEGACY */
7098 if (disable_hardirq(adapter->pdev->irq))
7099 e1000_intr(adapter->pdev->irq, netdev);
7100 enable_irq(adapter->pdev->irq);
7101 break;
7102 }
7103}
7104#endif
7105
7106/**
7107 * e1000_io_error_detected - called when PCI error is detected
7108 * @pdev: Pointer to PCI device
7109 * @state: The current pci connection state
7110 *
7111 * This function is called after a PCI bus error affecting
7112 * this device has been detected.
7113 */
7114static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7115 pci_channel_state_t state)
7116{
7117 e1000e_pm_freeze(&pdev->dev);
7118
7119 if (state == pci_channel_io_perm_failure)
7120 return PCI_ERS_RESULT_DISCONNECT;
7121
7122 pci_disable_device(pdev);
7123
7124 /* Request a slot reset. */
7125 return PCI_ERS_RESULT_NEED_RESET;
7126}
7127
7128/**
7129 * e1000_io_slot_reset - called after the pci bus has been reset.
7130 * @pdev: Pointer to PCI device
7131 *
7132 * Restart the card from scratch, as if from a cold-boot. Implementation
7133 * resembles the first-half of the e1000e_pm_resume routine.
7134 */
7135static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7136{
7137 struct net_device *netdev = pci_get_drvdata(pdev);
7138 struct e1000_adapter *adapter = netdev_priv(netdev);
7139 struct e1000_hw *hw = &adapter->hw;
7140 u16 aspm_disable_flag = 0;
7141 int err;
7142 pci_ers_result_t result;
7143
7144 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7145 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7146 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
7147 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7148 if (aspm_disable_flag)
7149 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
7150
7151 err = pci_enable_device_mem(pdev);
7152 if (err) {
7153 dev_err(&pdev->dev,
7154 "Cannot re-enable PCI device after reset.\n");
7155 result = PCI_ERS_RESULT_DISCONNECT;
7156 } else {
7157 pdev->state_saved = true;
7158 pci_restore_state(pdev);
7159 pci_set_master(pdev);
7160
7161 pci_enable_wake(pdev, PCI_D3hot, 0);
7162 pci_enable_wake(pdev, PCI_D3cold, 0);
7163
7164 e1000e_reset(adapter);
7165 ew32(WUS, ~0);
7166 result = PCI_ERS_RESULT_RECOVERED;
7167 }
7168
7169 return result;
7170}
7171
7172/**
7173 * e1000_io_resume - called when traffic can start flowing again.
7174 * @pdev: Pointer to PCI device
7175 *
7176 * This callback is called when the error recovery driver tells us that
7177 * its OK to resume normal operation. Implementation resembles the
7178 * second-half of the e1000e_pm_resume routine.
7179 */
7180static void e1000_io_resume(struct pci_dev *pdev)
7181{
7182 struct net_device *netdev = pci_get_drvdata(pdev);
7183 struct e1000_adapter *adapter = netdev_priv(netdev);
7184
7185 e1000_init_manageability_pt(adapter);
7186
7187 e1000e_pm_thaw(&pdev->dev);
7188
7189 /* If the controller has AMT, do not set DRV_LOAD until the interface
7190 * is up. For all other cases, let the f/w know that the h/w is now
7191 * under the control of the driver.
7192 */
7193 if (!(adapter->flags & FLAG_HAS_AMT))
7194 e1000e_get_hw_control(adapter);
7195}
7196
7197static void e1000_print_device_info(struct e1000_adapter *adapter)
7198{
7199 struct e1000_hw *hw = &adapter->hw;
7200 struct net_device *netdev = adapter->netdev;
7201 u32 ret_val;
7202 u8 pba_str[E1000_PBANUM_LENGTH];
7203
7204 /* print bus type/speed/width info */
7205 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
7206 /* bus width */
7207 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
7208 "Width x1"),
7209 /* MAC address */
7210 netdev->dev_addr);
7211 e_info("Intel(R) PRO/%s Network Connection\n",
7212 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
7213 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7214 E1000_PBANUM_LENGTH);
7215 if (ret_val)
7216 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
7217 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7218 hw->mac.type, hw->phy.type, pba_str);
7219}
7220
7221static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7222{
7223 struct e1000_hw *hw = &adapter->hw;
7224 int ret_val;
7225 u16 buf = 0;
7226
7227 if (hw->mac.type != e1000_82573)
7228 return;
7229
7230 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
7231 le16_to_cpus(&buf);
7232 if (!ret_val && (!(buf & BIT(0)))) {
7233 /* Deep Smart Power Down (DSPD) */
7234 dev_warn(&adapter->pdev->dev,
7235 "Warning: detected DSPD enabled in EEPROM\n");
7236 }
7237}
7238
7239static netdev_features_t e1000_fix_features(struct net_device *netdev,
7240 netdev_features_t features)
7241{
7242 struct e1000_adapter *adapter = netdev_priv(netdev);
7243 struct e1000_hw *hw = &adapter->hw;
7244
7245 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7246 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7247 features &= ~NETIF_F_RXFCS;
7248
7249 /* Since there is no support for separate Rx/Tx vlan accel
7250 * enable/disable make sure Tx flag is always in same state as Rx.
7251 */
7252 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7253 features |= NETIF_F_HW_VLAN_CTAG_TX;
7254 else
7255 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7256
7257 return features;
7258}
7259
7260static int e1000_set_features(struct net_device *netdev,
7261 netdev_features_t features)
7262{
7263 struct e1000_adapter *adapter = netdev_priv(netdev);
7264 netdev_features_t changed = features ^ netdev->features;
7265
7266 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7267 adapter->flags |= FLAG_TSO_FORCE;
7268
7269 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
7270 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7271 NETIF_F_RXALL)))
7272 return 0;
7273
7274 if (changed & NETIF_F_RXFCS) {
7275 if (features & NETIF_F_RXFCS) {
7276 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7277 } else {
7278 /* We need to take it back to defaults, which might mean
7279 * stripping is still disabled at the adapter level.
7280 */
7281 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7282 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7283 else
7284 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7285 }
7286 }
7287
7288 netdev->features = features;
7289
7290 if (netif_running(netdev))
7291 e1000e_reinit_locked(adapter);
7292 else
7293 e1000e_reset(adapter);
7294
7295 return 1;
7296}
7297
7298static const struct net_device_ops e1000e_netdev_ops = {
7299 .ndo_open = e1000e_open,
7300 .ndo_stop = e1000e_close,
7301 .ndo_start_xmit = e1000_xmit_frame,
7302 .ndo_get_stats64 = e1000e_get_stats64,
7303 .ndo_set_rx_mode = e1000e_set_rx_mode,
7304 .ndo_set_mac_address = e1000_set_mac,
7305 .ndo_change_mtu = e1000_change_mtu,
7306 .ndo_do_ioctl = e1000_ioctl,
7307 .ndo_tx_timeout = e1000_tx_timeout,
7308 .ndo_validate_addr = eth_validate_addr,
7309
7310 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7311 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7312#ifdef CONFIG_NET_POLL_CONTROLLER
7313 .ndo_poll_controller = e1000_netpoll,
7314#endif
7315 .ndo_set_features = e1000_set_features,
7316 .ndo_fix_features = e1000_fix_features,
7317 .ndo_features_check = passthru_features_check,
7318};
7319
7320/**
7321 * e1000_probe - Device Initialization Routine
7322 * @pdev: PCI device information struct
7323 * @ent: entry in e1000_pci_tbl
7324 *
7325 * Returns 0 on success, negative on failure
7326 *
7327 * e1000_probe initializes an adapter identified by a pci_dev structure.
7328 * The OS initialization, configuring of the adapter private structure,
7329 * and a hardware reset occur.
7330 **/
7331static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
7332{
7333 struct net_device *netdev;
7334 struct e1000_adapter *adapter;
7335 struct e1000_hw *hw;
7336 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
7337 resource_size_t mmio_start, mmio_len;
7338 resource_size_t flash_start, flash_len;
7339 static int cards_found;
7340 u16 aspm_disable_flag = 0;
7341 int bars, i, err, pci_using_dac;
7342 u16 eeprom_data = 0;
7343 u16 eeprom_apme_mask = E1000_EEPROM_APME;
7344 s32 ret_val = 0;
7345
7346 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7347 aspm_disable_flag = PCIE_LINK_STATE_L0S;
7348 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
7349 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7350 if (aspm_disable_flag)
7351 e1000e_disable_aspm(pdev, aspm_disable_flag);
7352
7353 err = pci_enable_device_mem(pdev);
7354 if (err)
7355 return err;
7356
7357 pci_using_dac = 0;
7358 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7359 if (!err) {
7360 pci_using_dac = 1;
7361 } else {
7362 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7363 if (err) {
7364 dev_err(&pdev->dev,
7365 "No usable DMA configuration, aborting\n");
7366 goto err_dma;
7367 }
7368 }
7369
7370 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7371 err = pci_request_selected_regions_exclusive(pdev, bars,
7372 e1000e_driver_name);
7373 if (err)
7374 goto err_pci_reg;
7375
7376 /* AER (Advanced Error Reporting) hooks */
7377 pci_enable_pcie_error_reporting(pdev);
7378
7379 pci_set_master(pdev);
7380 /* PCI config space info */
7381 err = pci_save_state(pdev);
7382 if (err)
7383 goto err_alloc_etherdev;
7384
7385 err = -ENOMEM;
7386 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7387 if (!netdev)
7388 goto err_alloc_etherdev;
7389
7390 SET_NETDEV_DEV(netdev, &pdev->dev);
7391
7392 netdev->irq = pdev->irq;
7393
7394 pci_set_drvdata(pdev, netdev);
7395 adapter = netdev_priv(netdev);
7396 hw = &adapter->hw;
7397 adapter->netdev = netdev;
7398 adapter->pdev = pdev;
7399 adapter->ei = ei;
7400 adapter->pba = ei->pba;
7401 adapter->flags = ei->flags;
7402 adapter->flags2 = ei->flags2;
7403 adapter->hw.adapter = adapter;
7404 adapter->hw.mac.type = ei->mac;
7405 adapter->max_hw_frame_size = ei->max_hw_frame_size;
7406 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
7407
7408 mmio_start = pci_resource_start(pdev, 0);
7409 mmio_len = pci_resource_len(pdev, 0);
7410
7411 err = -EIO;
7412 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7413 if (!adapter->hw.hw_addr)
7414 goto err_ioremap;
7415
7416 if ((adapter->flags & FLAG_HAS_FLASH) &&
7417 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7418 (hw->mac.type < e1000_pch_spt)) {
7419 flash_start = pci_resource_start(pdev, 1);
7420 flash_len = pci_resource_len(pdev, 1);
7421 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7422 if (!adapter->hw.flash_address)
7423 goto err_flashmap;
7424 }
7425
7426 /* Set default EEE advertisement */
7427 if (adapter->flags2 & FLAG2_HAS_EEE)
7428 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7429
7430 /* construct the net_device struct */
7431 netdev->netdev_ops = &e1000e_netdev_ops;
7432 e1000e_set_ethtool_ops(netdev);
7433 netdev->watchdog_timeo = 5 * HZ;
7434 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
7435 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
7436
7437 netdev->mem_start = mmio_start;
7438 netdev->mem_end = mmio_start + mmio_len;
7439
7440 adapter->bd_number = cards_found++;
7441
7442 e1000e_check_options(adapter);
7443
7444 /* setup adapter struct */
7445 err = e1000_sw_init(adapter);
7446 if (err)
7447 goto err_sw_init;
7448
7449 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7450 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7451 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7452
7453 err = ei->get_variants(adapter);
7454 if (err)
7455 goto err_hw_init;
7456
7457 if ((adapter->flags & FLAG_IS_ICH) &&
7458 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7459 (hw->mac.type < e1000_pch_spt))
7460 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7461
7462 hw->mac.ops.get_bus_info(&adapter->hw);
7463
7464 adapter->hw.phy.autoneg_wait_to_complete = 0;
7465
7466 /* Copper options */
7467 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
7468 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7469 adapter->hw.phy.disable_polarity_correction = 0;
7470 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7471 }
7472
7473 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
7474 dev_info(&pdev->dev,
7475 "PHY reset is blocked due to SOL/IDER session.\n");
7476
7477 /* Set initial default active device features */
7478 netdev->features = (NETIF_F_SG |
7479 NETIF_F_HW_VLAN_CTAG_RX |
7480 NETIF_F_HW_VLAN_CTAG_TX |
7481 NETIF_F_TSO |
7482 NETIF_F_TSO6 |
7483 NETIF_F_RXHASH |
7484 NETIF_F_RXCSUM |
7485 NETIF_F_HW_CSUM);
7486
7487 /* Set user-changeable features (subset of all device features) */
7488 netdev->hw_features = netdev->features;
7489 netdev->hw_features |= NETIF_F_RXFCS;
7490 netdev->priv_flags |= IFF_SUPP_NOFCS;
7491 netdev->hw_features |= NETIF_F_RXALL;
7492
7493 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
7494 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
7495
7496 netdev->vlan_features |= (NETIF_F_SG |
7497 NETIF_F_TSO |
7498 NETIF_F_TSO6 |
7499 NETIF_F_HW_CSUM);
7500
7501 netdev->priv_flags |= IFF_UNICAST_FLT;
7502
7503 if (pci_using_dac) {
7504 netdev->features |= NETIF_F_HIGHDMA;
7505 netdev->vlan_features |= NETIF_F_HIGHDMA;
7506 }
7507
7508 /* MTU range: 68 - max_hw_frame_size */
7509 netdev->min_mtu = ETH_MIN_MTU;
7510 netdev->max_mtu = adapter->max_hw_frame_size -
7511 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7512
7513 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7514 adapter->flags |= FLAG_MNG_PT_ENABLED;
7515
7516 /* before reading the NVM, reset the controller to
7517 * put the device in a known good starting state
7518 */
7519 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7520
7521 /* systems with ASPM and others may see the checksum fail on the first
7522 * attempt. Let's give it a few tries
7523 */
7524 for (i = 0;; i++) {
7525 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7526 break;
7527 if (i == 2) {
7528 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
7529 err = -EIO;
7530 goto err_eeprom;
7531 }
7532 }
7533
7534 e1000_eeprom_checks(adapter);
7535
7536 /* copy the MAC address */
7537 if (e1000e_read_mac_addr(&adapter->hw))
7538 dev_err(&pdev->dev,
7539 "NVM Read Error while reading MAC address\n");
7540
7541 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
7542
7543 if (!is_valid_ether_addr(netdev->dev_addr)) {
7544 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
7545 netdev->dev_addr);
7546 err = -EIO;
7547 goto err_eeprom;
7548 }
7549
7550 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
7551 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
7552
7553 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7554 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
7555 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7556 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
7557 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
7558
7559 /* Initialize link parameters. User can change them with ethtool */
7560 adapter->hw.mac.autoneg = 1;
7561 adapter->fc_autoneg = true;
7562 adapter->hw.fc.requested_mode = e1000_fc_default;
7563 adapter->hw.fc.current_mode = e1000_fc_default;
7564 adapter->hw.phy.autoneg_advertised = 0x2f;
7565
7566 /* Initial Wake on LAN setting - If APM wake is enabled in
7567 * the EEPROM, enable the ACPI Magic Packet filter
7568 */
7569 if (adapter->flags & FLAG_APME_IN_WUC) {
7570 /* APME bit in EEPROM is mapped to WUC.APME */
7571 eeprom_data = er32(WUC);
7572 eeprom_apme_mask = E1000_WUC_APME;
7573 if ((hw->mac.type > e1000_ich10lan) &&
7574 (eeprom_data & E1000_WUC_PHY_WAKE))
7575 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
7576 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7577 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7578 (adapter->hw.bus.func == 1))
7579 ret_val = e1000_read_nvm(&adapter->hw,
7580 NVM_INIT_CONTROL3_PORT_B,
7581 1, &eeprom_data);
7582 else
7583 ret_val = e1000_read_nvm(&adapter->hw,
7584 NVM_INIT_CONTROL3_PORT_A,
7585 1, &eeprom_data);
7586 }
7587
7588 /* fetch WoL from EEPROM */
7589 if (ret_val)
7590 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
7591 else if (eeprom_data & eeprom_apme_mask)
7592 adapter->eeprom_wol |= E1000_WUFC_MAG;
7593
7594 /* now that we have the eeprom settings, apply the special cases
7595 * where the eeprom may be wrong or the board simply won't support
7596 * wake on lan on a particular port
7597 */
7598 if (!(adapter->flags & FLAG_HAS_WOL))
7599 adapter->eeprom_wol = 0;
7600
7601 /* initialize the wol settings based on the eeprom settings */
7602 adapter->wol = adapter->eeprom_wol;
7603
7604 /* make sure adapter isn't asleep if manageability is enabled */
7605 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7606 (hw->mac.ops.check_mng_mode(hw)))
7607 device_wakeup_enable(&pdev->dev);
7608
7609 /* save off EEPROM version number */
7610 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7611
7612 if (ret_val) {
7613 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
7614 adapter->eeprom_vers = 0;
7615 }
7616
7617 /* init PTP hardware clock */
7618 e1000e_ptp_init(adapter);
7619
7620 /* reset the hardware with the new settings */
7621 e1000e_reset(adapter);
7622
7623 /* If the controller has AMT, do not set DRV_LOAD until the interface
7624 * is up. For all other cases, let the f/w know that the h/w is now
7625 * under the control of the driver.
7626 */
7627 if (!(adapter->flags & FLAG_HAS_AMT))
7628 e1000e_get_hw_control(adapter);
7629
7630 if (hw->mac.type >= e1000_pch_cnp)
7631 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7632
7633 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
7634 err = register_netdev(netdev);
7635 if (err)
7636 goto err_register;
7637
7638 /* carrier off reporting is important to ethtool even BEFORE open */
7639 netif_carrier_off(netdev);
7640
7641 e1000_print_device_info(adapter);
7642
7643 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE);
7644
7645 if (pci_dev_run_wake(pdev) && hw->mac.type != e1000_pch_cnp)
7646 pm_runtime_put_noidle(&pdev->dev);
7647
7648 return 0;
7649
7650err_register:
7651 if (!(adapter->flags & FLAG_HAS_AMT))
7652 e1000e_release_hw_control(adapter);
7653err_eeprom:
7654 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
7655 e1000_phy_hw_reset(&adapter->hw);
7656err_hw_init:
7657 kfree(adapter->tx_ring);
7658 kfree(adapter->rx_ring);
7659err_sw_init:
7660 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
7661 iounmap(adapter->hw.flash_address);
7662 e1000e_reset_interrupt_capability(adapter);
7663err_flashmap:
7664 iounmap(adapter->hw.hw_addr);
7665err_ioremap:
7666 free_netdev(netdev);
7667err_alloc_etherdev:
7668 pci_disable_pcie_error_reporting(pdev);
7669 pci_release_mem_regions(pdev);
7670err_pci_reg:
7671err_dma:
7672 pci_disable_device(pdev);
7673 return err;
7674}
7675
7676/**
7677 * e1000_remove - Device Removal Routine
7678 * @pdev: PCI device information struct
7679 *
7680 * e1000_remove is called by the PCI subsystem to alert the driver
7681 * that it should release a PCI device. The could be caused by a
7682 * Hot-Plug event, or because the driver is going to be removed from
7683 * memory.
7684 **/
7685static void e1000_remove(struct pci_dev *pdev)
7686{
7687 struct net_device *netdev = pci_get_drvdata(pdev);
7688 struct e1000_adapter *adapter = netdev_priv(netdev);
7689
7690 e1000e_ptp_remove(adapter);
7691
7692 /* The timers may be rescheduled, so explicitly disable them
7693 * from being rescheduled.
7694 */
7695 set_bit(__E1000_DOWN, &adapter->state);
7696 del_timer_sync(&adapter->watchdog_timer);
7697 del_timer_sync(&adapter->phy_info_timer);
7698
7699 cancel_work_sync(&adapter->reset_task);
7700 cancel_work_sync(&adapter->watchdog_task);
7701 cancel_work_sync(&adapter->downshift_task);
7702 cancel_work_sync(&adapter->update_phy_task);
7703 cancel_work_sync(&adapter->print_hang_task);
7704
7705 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7706 cancel_work_sync(&adapter->tx_hwtstamp_work);
7707 if (adapter->tx_hwtstamp_skb) {
7708 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
7709 adapter->tx_hwtstamp_skb = NULL;
7710 }
7711 }
7712
7713 unregister_netdev(netdev);
7714
7715 if (pci_dev_run_wake(pdev))
7716 pm_runtime_get_noresume(&pdev->dev);
7717
7718 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7719 * would have already happened in close and is redundant.
7720 */
7721 e1000e_release_hw_control(adapter);
7722
7723 e1000e_reset_interrupt_capability(adapter);
7724 kfree(adapter->tx_ring);
7725 kfree(adapter->rx_ring);
7726
7727 iounmap(adapter->hw.hw_addr);
7728 if ((adapter->hw.flash_address) &&
7729 (adapter->hw.mac.type < e1000_pch_spt))
7730 iounmap(adapter->hw.flash_address);
7731 pci_release_mem_regions(pdev);
7732
7733 free_netdev(netdev);
7734
7735 /* AER disable */
7736 pci_disable_pcie_error_reporting(pdev);
7737
7738 pci_disable_device(pdev);
7739}
7740
7741/* PCI Error Recovery (ERS) */
7742static const struct pci_error_handlers e1000_err_handler = {
7743 .error_detected = e1000_io_error_detected,
7744 .slot_reset = e1000_io_slot_reset,
7745 .resume = e1000_io_resume,
7746};
7747
7748static const struct pci_device_id e1000_pci_tbl[] = {
7749 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7750 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7751 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
7752 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7753 board_82571 },
7754 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7755 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
7756 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7757 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7758 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
7759
7760 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7761 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7762 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7763 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
7764
7765 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7766 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7767 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
7768
7769 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
7770 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
7771 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
7772
7773 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7774 board_80003es2lan },
7775 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7776 board_80003es2lan },
7777 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7778 board_80003es2lan },
7779 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7780 board_80003es2lan },
7781
7782 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7783 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7784 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7785 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7786 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7787 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7788 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
7789 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
7790
7791 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7792 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7793 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7794 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7795 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
7796 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
7797 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7798 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7799 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7800
7801 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7802 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
7804
7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
7807 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
7808
7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7813
7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7816
7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7818 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7822 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7826 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7828 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
7830 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7832 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
7834 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7835 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp },
7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp },
7844 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp },
7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp },
7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp },
7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp },
7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp },
7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp },
7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp },
7854 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_tgp },
7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_tgp },
7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_tgp },
7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_tgp },
7858 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_tgp },
7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_tgp },
7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM19), board_pch_tgp },
7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V19), board_pch_tgp },
7862
7863 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
7864};
7865MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7866
7867static const struct dev_pm_ops e1000_pm_ops = {
7868#ifdef CONFIG_PM_SLEEP
7869 .prepare = e1000e_pm_prepare,
7870 .suspend = e1000e_pm_suspend,
7871 .resume = e1000e_pm_resume,
7872 .freeze = e1000e_pm_freeze,
7873 .thaw = e1000e_pm_thaw,
7874 .poweroff = e1000e_pm_suspend,
7875 .restore = e1000e_pm_resume,
7876#endif
7877 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7878 e1000e_pm_runtime_idle)
7879};
7880
7881/* PCI Device API Driver */
7882static struct pci_driver e1000_driver = {
7883 .name = e1000e_driver_name,
7884 .id_table = e1000_pci_tbl,
7885 .probe = e1000_probe,
7886 .remove = e1000_remove,
7887 .driver = {
7888 .pm = &e1000_pm_ops,
7889 },
7890 .shutdown = e1000_shutdown,
7891 .err_handler = &e1000_err_handler
7892};
7893
7894/**
7895 * e1000_init_module - Driver Registration Routine
7896 *
7897 * e1000_init_module is the first routine called when the driver is
7898 * loaded. All it does is register with the PCI subsystem.
7899 **/
7900static int __init e1000_init_module(void)
7901{
7902 pr_info("Intel(R) PRO/1000 Network Driver\n");
7903 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
7904
7905 return pci_register_driver(&e1000_driver);
7906}
7907module_init(e1000_init_module);
7908
7909/**
7910 * e1000_exit_module - Driver Exit Cleanup Routine
7911 *
7912 * e1000_exit_module is called just before the driver is removed
7913 * from memory.
7914 **/
7915static void __exit e1000_exit_module(void)
7916{
7917 pci_unregister_driver(&e1000_driver);
7918}
7919module_exit(e1000_exit_module);
7920
7921MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7922MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7923MODULE_LICENSE("GPL v2");
7924
7925/* netdev.c */