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1# SPDX-License-Identifier: GPL-2.0-only
2menu "IRQ chip support"
3
4config IRQCHIP
5 def_bool y
6 depends on (OF_IRQ || ACPI_GENERIC_GSI)
7
8config ARM_GIC
9 bool
10 depends on OF
11 select IRQ_DOMAIN_HIERARCHY
12 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
13
14config ARM_GIC_PM
15 bool
16 depends on PM
17 select ARM_GIC
18
19config ARM_GIC_MAX_NR
20 int
21 depends on ARM_GIC
22 default 2 if ARCH_REALVIEW
23 default 1
24
25config ARM_GIC_V2M
26 bool
27 depends on PCI
28 select ARM_GIC
29 select PCI_MSI
30
31config GIC_NON_BANKED
32 bool
33
34config ARM_GIC_V3
35 bool
36 select IRQ_DOMAIN_HIERARCHY
37 select PARTITION_PERCPU
38 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
39 select HAVE_ARM_SMCCC_DISCOVERY
40
41config ARM_GIC_V3_ITS
42 bool
43 select GENERIC_MSI_IRQ
44 default ARM_GIC_V3
45
46config ARM_GIC_V3_ITS_PCI
47 bool
48 depends on ARM_GIC_V3_ITS
49 depends on PCI
50 depends on PCI_MSI
51 default ARM_GIC_V3_ITS
52
53config ARM_GIC_V3_ITS_FSL_MC
54 bool
55 depends on ARM_GIC_V3_ITS
56 depends on FSL_MC_BUS
57 default ARM_GIC_V3_ITS
58
59config ARM_NVIC
60 bool
61 select IRQ_DOMAIN_HIERARCHY
62 select GENERIC_IRQ_CHIP
63
64config ARM_VIC
65 bool
66 select IRQ_DOMAIN
67
68config ARM_VIC_NR
69 int
70 default 4 if ARCH_S5PV210
71 default 2
72 depends on ARM_VIC
73 help
74 The maximum number of VICs available in the system, for
75 power management.
76
77config ARMADA_370_XP_IRQ
78 bool
79 select GENERIC_IRQ_CHIP
80 select PCI_MSI if PCI
81 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
82
83config ALPINE_MSI
84 bool
85 depends on PCI
86 select PCI_MSI
87 select GENERIC_IRQ_CHIP
88
89config AL_FIC
90 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
91 depends on OF
92 depends on HAS_IOMEM
93 select GENERIC_IRQ_CHIP
94 select IRQ_DOMAIN
95 help
96 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
97
98config ATMEL_AIC_IRQ
99 bool
100 select GENERIC_IRQ_CHIP
101 select IRQ_DOMAIN
102 select SPARSE_IRQ
103
104config ATMEL_AIC5_IRQ
105 bool
106 select GENERIC_IRQ_CHIP
107 select IRQ_DOMAIN
108 select SPARSE_IRQ
109
110config I8259
111 bool
112 select IRQ_DOMAIN
113
114config BCM6345_L1_IRQ
115 bool
116 select GENERIC_IRQ_CHIP
117 select IRQ_DOMAIN
118 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
119
120config BCM7038_L1_IRQ
121 tristate "Broadcom STB 7038-style L1/L2 interrupt controller driver"
122 depends on ARCH_BRCMSTB || BMIPS_GENERIC
123 default ARCH_BRCMSTB || BMIPS_GENERIC
124 select GENERIC_IRQ_CHIP
125 select IRQ_DOMAIN
126 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
127
128config BCM7120_L2_IRQ
129 tristate "Broadcom STB 7120-style L2 interrupt controller driver"
130 depends on ARCH_BRCMSTB || BMIPS_GENERIC
131 default ARCH_BRCMSTB || BMIPS_GENERIC
132 select GENERIC_IRQ_CHIP
133 select IRQ_DOMAIN
134
135config BRCMSTB_L2_IRQ
136 tristate "Broadcom STB generic L2 interrupt controller driver"
137 depends on ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
138 default ARCH_BCM2835 || ARCH_BRCMSTB || BMIPS_GENERIC
139 select GENERIC_IRQ_CHIP
140 select IRQ_DOMAIN
141
142config DAVINCI_CP_INTC
143 bool
144 select GENERIC_IRQ_CHIP
145 select IRQ_DOMAIN
146
147config DW_APB_ICTL
148 bool
149 select GENERIC_IRQ_CHIP
150 select IRQ_DOMAIN_HIERARCHY
151
152config FARADAY_FTINTC010
153 bool
154 select IRQ_DOMAIN
155 select SPARSE_IRQ
156
157config HISILICON_IRQ_MBIGEN
158 bool
159 select ARM_GIC_V3
160 select ARM_GIC_V3_ITS
161
162config IMGPDC_IRQ
163 bool
164 select GENERIC_IRQ_CHIP
165 select IRQ_DOMAIN
166
167config IXP4XX_IRQ
168 bool
169 select IRQ_DOMAIN
170 select SPARSE_IRQ
171
172config MADERA_IRQ
173 tristate
174
175config IRQ_MIPS_CPU
176 bool
177 select GENERIC_IRQ_CHIP
178 select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
179 select IRQ_DOMAIN
180 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
181
182config CLPS711X_IRQCHIP
183 bool
184 depends on ARCH_CLPS711X
185 select IRQ_DOMAIN
186 select SPARSE_IRQ
187 default y
188
189config OMPIC
190 bool
191
192config OR1K_PIC
193 bool
194 select IRQ_DOMAIN
195
196config OMAP_IRQCHIP
197 bool
198 select GENERIC_IRQ_CHIP
199 select IRQ_DOMAIN
200
201config ORION_IRQCHIP
202 bool
203 select IRQ_DOMAIN
204
205config PIC32_EVIC
206 bool
207 select GENERIC_IRQ_CHIP
208 select IRQ_DOMAIN
209
210config JCORE_AIC
211 bool "J-Core integrated AIC" if COMPILE_TEST
212 depends on OF
213 select IRQ_DOMAIN
214 help
215 Support for the J-Core integrated AIC.
216
217config RDA_INTC
218 bool
219 select IRQ_DOMAIN
220
221config RENESAS_INTC_IRQPIN
222 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
223 select IRQ_DOMAIN
224 help
225 Enable support for the Renesas Interrupt Controller for external
226 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
227
228config RENESAS_IRQC
229 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
230 select GENERIC_IRQ_CHIP
231 select IRQ_DOMAIN
232 help
233 Enable support for the Renesas Interrupt Controller for external
234 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
235
236config RENESAS_RZA1_IRQC
237 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
238 select IRQ_DOMAIN_HIERARCHY
239 help
240 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
241 to 8 external interrupts with configurable sense select.
242
243config RENESAS_RZG2L_IRQC
244 bool "Renesas RZ/G2L (and alike SoC) IRQC support" if COMPILE_TEST
245 select GENERIC_IRQ_CHIP
246 select IRQ_DOMAIN_HIERARCHY
247 help
248 Enable support for the Renesas RZ/G2L (and alike SoC) Interrupt Controller
249 for external devices.
250
251config SL28CPLD_INTC
252 bool "Kontron sl28cpld IRQ controller"
253 depends on MFD_SL28CPLD=y || COMPILE_TEST
254 select REGMAP_IRQ
255 help
256 Interrupt controller driver for the board management controller
257 found on the Kontron sl28 CPLD.
258
259config ST_IRQCHIP
260 bool
261 select REGMAP
262 select MFD_SYSCON
263 help
264 Enables SysCfg Controlled IRQs on STi based platforms.
265
266config SUN4I_INTC
267 bool
268
269config SUN6I_R_INTC
270 bool
271 select IRQ_DOMAIN_HIERARCHY
272 select IRQ_FASTEOI_HIERARCHY_HANDLERS
273
274config SUNXI_NMI_INTC
275 bool
276 select GENERIC_IRQ_CHIP
277
278config TB10X_IRQC
279 bool
280 select IRQ_DOMAIN
281 select GENERIC_IRQ_CHIP
282
283config TS4800_IRQ
284 tristate "TS-4800 IRQ controller"
285 select IRQ_DOMAIN
286 depends on HAS_IOMEM
287 depends on SOC_IMX51 || COMPILE_TEST
288 help
289 Support for the TS-4800 FPGA IRQ controller
290
291config VERSATILE_FPGA_IRQ
292 bool
293 select IRQ_DOMAIN
294
295config VERSATILE_FPGA_IRQ_NR
296 int
297 default 4
298 depends on VERSATILE_FPGA_IRQ
299
300config XTENSA_MX
301 bool
302 select IRQ_DOMAIN
303 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
304
305config XILINX_INTC
306 bool "Xilinx Interrupt Controller IP"
307 depends on OF_ADDRESS
308 select IRQ_DOMAIN
309 help
310 Support for the Xilinx Interrupt Controller IP core.
311 This is used as a primary controller with MicroBlaze and can also
312 be used as a secondary chained controller on other platforms.
313
314config IRQ_CROSSBAR
315 bool
316 help
317 Support for a CROSSBAR ip that precedes the main interrupt controller.
318 The primary irqchip invokes the crossbar's callback which inturn allocates
319 a free irq and configures the IP. Thus the peripheral interrupts are
320 routed to one of the free irqchip interrupt lines.
321
322config KEYSTONE_IRQ
323 tristate "Keystone 2 IRQ controller IP"
324 depends on ARCH_KEYSTONE
325 help
326 Support for Texas Instruments Keystone 2 IRQ controller IP which
327 is part of the Keystone 2 IPC mechanism
328
329config MIPS_GIC
330 bool
331 select GENERIC_IRQ_IPI if SMP
332 select IRQ_DOMAIN_HIERARCHY
333 select MIPS_CM
334
335config INGENIC_IRQ
336 bool
337 depends on MACH_INGENIC
338 default y
339
340config INGENIC_TCU_IRQ
341 bool "Ingenic JZ47xx TCU interrupt controller"
342 default MACH_INGENIC
343 depends on MIPS || COMPILE_TEST
344 select MFD_SYSCON
345 select GENERIC_IRQ_CHIP
346 help
347 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
348 JZ47xx SoCs.
349
350 If unsure, say N.
351
352config IMX_GPCV2
353 bool
354 select IRQ_DOMAIN
355 help
356 Enables the wakeup IRQs for IMX platforms with GPCv2 block
357
358config IRQ_MXS
359 def_bool y if MACH_ASM9260 || ARCH_MXS
360 select IRQ_DOMAIN
361 select STMP_DEVICE
362
363config MSCC_OCELOT_IRQ
364 bool
365 select IRQ_DOMAIN
366 select GENERIC_IRQ_CHIP
367
368config MVEBU_GICP
369 bool
370
371config MVEBU_ICU
372 bool
373
374config MVEBU_ODMI
375 bool
376 select GENERIC_MSI_IRQ
377
378config MVEBU_PIC
379 bool
380
381config MVEBU_SEI
382 bool
383
384config LS_EXTIRQ
385 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
386 select MFD_SYSCON
387
388config LS_SCFG_MSI
389 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
390 depends on PCI_MSI
391
392config PARTITION_PERCPU
393 bool
394
395config STM32_EXTI
396 bool
397 select IRQ_DOMAIN
398 select GENERIC_IRQ_CHIP
399
400config QCOM_IRQ_COMBINER
401 bool "QCOM IRQ combiner support"
402 depends on ARCH_QCOM && ACPI
403 select IRQ_DOMAIN_HIERARCHY
404 help
405 Say yes here to add support for the IRQ combiner devices embedded
406 in Qualcomm Technologies chips.
407
408config IRQ_UNIPHIER_AIDET
409 bool "UniPhier AIDET support" if COMPILE_TEST
410 depends on ARCH_UNIPHIER || COMPILE_TEST
411 default ARCH_UNIPHIER
412 select IRQ_DOMAIN_HIERARCHY
413 help
414 Support for the UniPhier AIDET (ARM Interrupt Detector).
415
416config MESON_IRQ_GPIO
417 tristate "Meson GPIO Interrupt Multiplexer"
418 depends on ARCH_MESON || COMPILE_TEST
419 default ARCH_MESON
420 select IRQ_DOMAIN_HIERARCHY
421 help
422 Support Meson SoC Family GPIO Interrupt Multiplexer
423
424config GOLDFISH_PIC
425 bool "Goldfish programmable interrupt controller"
426 depends on MIPS && (GOLDFISH || COMPILE_TEST)
427 select GENERIC_IRQ_CHIP
428 select IRQ_DOMAIN
429 help
430 Say yes here to enable Goldfish interrupt controller driver used
431 for Goldfish based virtual platforms.
432
433config QCOM_PDC
434 tristate "QCOM PDC"
435 depends on ARCH_QCOM
436 select IRQ_DOMAIN_HIERARCHY
437 help
438 Power Domain Controller driver to manage and configure wakeup
439 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
440
441config QCOM_MPM
442 tristate "QCOM MPM"
443 depends on ARCH_QCOM
444 depends on MAILBOX
445 select IRQ_DOMAIN_HIERARCHY
446 help
447 MSM Power Manager driver to manage and configure wakeup
448 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
449
450config CSKY_MPINTC
451 bool
452 depends on CSKY
453 help
454 Say yes here to enable C-SKY SMP interrupt controller driver used
455 for C-SKY SMP system.
456 In fact it's not mmio map in hardware and it uses ld/st to visit the
457 controller's register inside CPU.
458
459config CSKY_APB_INTC
460 bool "C-SKY APB Interrupt Controller"
461 depends on CSKY
462 help
463 Say yes here to enable C-SKY APB interrupt controller driver used
464 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
465 the controller's register.
466
467config IMX_IRQSTEER
468 bool "i.MX IRQSTEER support"
469 depends on ARCH_MXC || COMPILE_TEST
470 default ARCH_MXC
471 select IRQ_DOMAIN
472 help
473 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
474
475config IMX_INTMUX
476 bool "i.MX INTMUX support" if COMPILE_TEST
477 default y if ARCH_MXC
478 select IRQ_DOMAIN
479 help
480 Support for the i.MX INTMUX interrupt multiplexer.
481
482config IMX_MU_MSI
483 tristate "i.MX MU used as MSI controller"
484 depends on OF && HAS_IOMEM
485 depends on ARCH_MXC || COMPILE_TEST
486 default m if ARCH_MXC
487 select IRQ_DOMAIN
488 select IRQ_DOMAIN_HIERARCHY
489 select GENERIC_MSI_IRQ
490 help
491 Provide a driver for the i.MX Messaging Unit block used as a
492 CPU-to-CPU MSI controller. This requires a specially crafted DT
493 to make use of this driver.
494
495 If unsure, say N
496
497config LS1X_IRQ
498 bool "Loongson-1 Interrupt Controller"
499 depends on MACH_LOONGSON32
500 default y
501 select IRQ_DOMAIN
502 select GENERIC_IRQ_CHIP
503 help
504 Support for the Loongson-1 platform Interrupt Controller.
505
506config TI_SCI_INTR_IRQCHIP
507 bool
508 depends on TI_SCI_PROTOCOL
509 select IRQ_DOMAIN_HIERARCHY
510 help
511 This enables the irqchip driver support for K3 Interrupt router
512 over TI System Control Interface available on some new TI's SoCs.
513 If you wish to use interrupt router irq resources managed by the
514 TI System Controller, say Y here. Otherwise, say N.
515
516config TI_SCI_INTA_IRQCHIP
517 bool
518 depends on TI_SCI_PROTOCOL
519 select IRQ_DOMAIN_HIERARCHY
520 select TI_SCI_INTA_MSI_DOMAIN
521 help
522 This enables the irqchip driver support for K3 Interrupt aggregator
523 over TI System Control Interface available on some new TI's SoCs.
524 If you wish to use interrupt aggregator irq resources managed by the
525 TI System Controller, say Y here. Otherwise, say N.
526
527config TI_PRUSS_INTC
528 tristate
529 depends on TI_PRUSS
530 default TI_PRUSS
531 select IRQ_DOMAIN
532 help
533 This enables support for the PRU-ICSS Local Interrupt Controller
534 present within a PRU-ICSS subsystem present on various TI SoCs.
535 The PRUSS INTC enables various interrupts to be routed to multiple
536 different processors within the SoC.
537
538config RISCV_INTC
539 bool
540 depends on RISCV
541 select IRQ_DOMAIN_HIERARCHY
542
543config SIFIVE_PLIC
544 bool
545 depends on RISCV
546 select IRQ_DOMAIN_HIERARCHY
547 select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP
548
549config EXYNOS_IRQ_COMBINER
550 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
551 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
552 help
553 Say yes here to add support for the IRQ combiner devices embedded
554 in Samsung Exynos chips.
555
556config IRQ_LOONGARCH_CPU
557 bool
558 select GENERIC_IRQ_CHIP
559 select IRQ_DOMAIN
560 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
561 select LOONGSON_HTVEC
562 select LOONGSON_LIOINTC
563 select LOONGSON_EIOINTC
564 select LOONGSON_PCH_PIC
565 select LOONGSON_PCH_MSI
566 select LOONGSON_PCH_LPC
567 help
568 Support for the LoongArch CPU Interrupt Controller. For details of
569 irq chip hierarchy on LoongArch platforms please read the document
570 Documentation/arch/loongarch/irq-chip-model.rst.
571
572config LOONGSON_LIOINTC
573 bool "Loongson Local I/O Interrupt Controller"
574 depends on MACH_LOONGSON64
575 default y
576 select IRQ_DOMAIN
577 select GENERIC_IRQ_CHIP
578 help
579 Support for the Loongson Local I/O Interrupt Controller.
580
581config LOONGSON_EIOINTC
582 bool "Loongson Extend I/O Interrupt Controller"
583 depends on LOONGARCH
584 depends on MACH_LOONGSON64
585 default MACH_LOONGSON64
586 select IRQ_DOMAIN_HIERARCHY
587 select GENERIC_IRQ_CHIP
588 help
589 Support for the Loongson3 Extend I/O Interrupt Vector Controller.
590
591config LOONGSON_HTPIC
592 bool "Loongson3 HyperTransport PIC Controller"
593 depends on MACH_LOONGSON64 && MIPS
594 default y
595 select IRQ_DOMAIN
596 select GENERIC_IRQ_CHIP
597 help
598 Support for the Loongson-3 HyperTransport PIC Controller.
599
600config LOONGSON_HTVEC
601 bool "Loongson HyperTransport Interrupt Vector Controller"
602 depends on MACH_LOONGSON64
603 default MACH_LOONGSON64
604 select IRQ_DOMAIN_HIERARCHY
605 help
606 Support for the Loongson HyperTransport Interrupt Vector Controller.
607
608config LOONGSON_PCH_PIC
609 bool "Loongson PCH PIC Controller"
610 depends on MACH_LOONGSON64
611 default MACH_LOONGSON64
612 select IRQ_DOMAIN_HIERARCHY
613 select IRQ_FASTEOI_HIERARCHY_HANDLERS
614 help
615 Support for the Loongson PCH PIC Controller.
616
617config LOONGSON_PCH_MSI
618 bool "Loongson PCH MSI Controller"
619 depends on MACH_LOONGSON64
620 depends on PCI
621 default MACH_LOONGSON64
622 select IRQ_DOMAIN_HIERARCHY
623 select PCI_MSI
624 help
625 Support for the Loongson PCH MSI Controller.
626
627config LOONGSON_PCH_LPC
628 bool "Loongson PCH LPC Controller"
629 depends on LOONGARCH
630 depends on MACH_LOONGSON64
631 default MACH_LOONGSON64
632 select IRQ_DOMAIN_HIERARCHY
633 help
634 Support for the Loongson PCH LPC Controller.
635
636config MST_IRQ
637 bool "MStar Interrupt Controller"
638 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
639 default ARCH_MEDIATEK
640 select IRQ_DOMAIN
641 select IRQ_DOMAIN_HIERARCHY
642 help
643 Support MStar Interrupt Controller.
644
645config WPCM450_AIC
646 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
647 depends on ARCH_WPCM450
648 help
649 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
650
651config IRQ_IDT3243X
652 bool
653 select GENERIC_IRQ_CHIP
654 select IRQ_DOMAIN
655
656config APPLE_AIC
657 bool "Apple Interrupt Controller (AIC)"
658 depends on ARM64
659 depends on ARCH_APPLE || COMPILE_TEST
660 select GENERIC_IRQ_IPI_MUX
661 help
662 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
663 such as the M1.
664
665config MCHP_EIC
666 bool "Microchip External Interrupt Controller"
667 depends on ARCH_AT91 || COMPILE_TEST
668 select IRQ_DOMAIN
669 select IRQ_DOMAIN_HIERARCHY
670 help
671 Support for Microchip External Interrupt Controller.
672
673config SUNPLUS_SP7021_INTC
674 bool "Sunplus SP7021 interrupt controller" if COMPILE_TEST
675 default SOC_SP7021
676 help
677 Support for the Sunplus SP7021 Interrupt Controller IP core.
678 SP7021 SoC has 2 Chips: C-Chip & P-Chip. This is used as a
679 chained controller, routing all interrupt source in P-Chip to
680 the primary controller on C-Chip.
681
682endmenu
1# SPDX-License-Identifier: GPL-2.0-only
2menu "IRQ chip support"
3
4config IRQCHIP
5 def_bool y
6 depends on OF_IRQ
7
8config ARM_GIC
9 bool
10 select IRQ_DOMAIN_HIERARCHY
11 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
12
13config ARM_GIC_PM
14 bool
15 depends on PM
16 select ARM_GIC
17
18config ARM_GIC_MAX_NR
19 int
20 depends on ARM_GIC
21 default 2 if ARCH_REALVIEW
22 default 1
23
24config ARM_GIC_V2M
25 bool
26 depends on PCI
27 select ARM_GIC
28 select PCI_MSI
29
30config GIC_NON_BANKED
31 bool
32
33config ARM_GIC_V3
34 bool
35 select IRQ_DOMAIN_HIERARCHY
36 select PARTITION_PERCPU
37 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
38
39config ARM_GIC_V3_ITS
40 bool
41 select GENERIC_MSI_IRQ_DOMAIN
42 default ARM_GIC_V3
43
44config ARM_GIC_V3_ITS_PCI
45 bool
46 depends on ARM_GIC_V3_ITS
47 depends on PCI
48 depends on PCI_MSI
49 default ARM_GIC_V3_ITS
50
51config ARM_GIC_V3_ITS_FSL_MC
52 bool
53 depends on ARM_GIC_V3_ITS
54 depends on FSL_MC_BUS
55 default ARM_GIC_V3_ITS
56
57config ARM_NVIC
58 bool
59 select IRQ_DOMAIN_HIERARCHY
60 select GENERIC_IRQ_CHIP
61
62config ARM_VIC
63 bool
64 select IRQ_DOMAIN
65
66config ARM_VIC_NR
67 int
68 default 4 if ARCH_S5PV210
69 default 2
70 depends on ARM_VIC
71 help
72 The maximum number of VICs available in the system, for
73 power management.
74
75config ARMADA_370_XP_IRQ
76 bool
77 select GENERIC_IRQ_CHIP
78 select PCI_MSI if PCI
79 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
80
81config ALPINE_MSI
82 bool
83 depends on PCI
84 select PCI_MSI
85 select GENERIC_IRQ_CHIP
86
87config AL_FIC
88 bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
89 depends on OF || COMPILE_TEST
90 select GENERIC_IRQ_CHIP
91 select IRQ_DOMAIN
92 help
93 Support Amazon's Annapurna Labs Fabric Interrupt Controller.
94
95config ATMEL_AIC_IRQ
96 bool
97 select GENERIC_IRQ_CHIP
98 select IRQ_DOMAIN
99 select SPARSE_IRQ
100
101config ATMEL_AIC5_IRQ
102 bool
103 select GENERIC_IRQ_CHIP
104 select IRQ_DOMAIN
105 select SPARSE_IRQ
106
107config I8259
108 bool
109 select IRQ_DOMAIN
110
111config BCM6345_L1_IRQ
112 bool
113 select GENERIC_IRQ_CHIP
114 select IRQ_DOMAIN
115 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
116
117config BCM7038_L1_IRQ
118 bool
119 select GENERIC_IRQ_CHIP
120 select IRQ_DOMAIN
121 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
122
123config BCM7120_L2_IRQ
124 bool
125 select GENERIC_IRQ_CHIP
126 select IRQ_DOMAIN
127
128config BRCMSTB_L2_IRQ
129 bool
130 select GENERIC_IRQ_CHIP
131 select IRQ_DOMAIN
132
133config DAVINCI_AINTC
134 bool
135 select GENERIC_IRQ_CHIP
136 select IRQ_DOMAIN
137
138config DAVINCI_CP_INTC
139 bool
140 select GENERIC_IRQ_CHIP
141 select IRQ_DOMAIN
142
143config DW_APB_ICTL
144 bool
145 select GENERIC_IRQ_CHIP
146 select IRQ_DOMAIN_HIERARCHY
147
148config FARADAY_FTINTC010
149 bool
150 select IRQ_DOMAIN
151 select SPARSE_IRQ
152
153config HISILICON_IRQ_MBIGEN
154 bool
155 select ARM_GIC_V3
156 select ARM_GIC_V3_ITS
157
158config IMGPDC_IRQ
159 bool
160 select GENERIC_IRQ_CHIP
161 select IRQ_DOMAIN
162
163config IXP4XX_IRQ
164 bool
165 select IRQ_DOMAIN
166 select SPARSE_IRQ
167
168config MADERA_IRQ
169 tristate
170
171config IRQ_MIPS_CPU
172 bool
173 select GENERIC_IRQ_CHIP
174 select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
175 select IRQ_DOMAIN
176 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
177
178config CLPS711X_IRQCHIP
179 bool
180 depends on ARCH_CLPS711X
181 select IRQ_DOMAIN
182 select SPARSE_IRQ
183 default y
184
185config OMPIC
186 bool
187
188config OR1K_PIC
189 bool
190 select IRQ_DOMAIN
191
192config OMAP_IRQCHIP
193 bool
194 select GENERIC_IRQ_CHIP
195 select IRQ_DOMAIN
196
197config ORION_IRQCHIP
198 bool
199 select IRQ_DOMAIN
200
201config PIC32_EVIC
202 bool
203 select GENERIC_IRQ_CHIP
204 select IRQ_DOMAIN
205
206config JCORE_AIC
207 bool "J-Core integrated AIC" if COMPILE_TEST
208 depends on OF
209 select IRQ_DOMAIN
210 help
211 Support for the J-Core integrated AIC.
212
213config RDA_INTC
214 bool
215 select IRQ_DOMAIN
216
217config RENESAS_INTC_IRQPIN
218 bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
219 select IRQ_DOMAIN
220 help
221 Enable support for the Renesas Interrupt Controller for external
222 interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
223
224config RENESAS_IRQC
225 bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
226 select GENERIC_IRQ_CHIP
227 select IRQ_DOMAIN
228 help
229 Enable support for the Renesas Interrupt Controller for external
230 devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
231
232config RENESAS_RZA1_IRQC
233 bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
234 select IRQ_DOMAIN_HIERARCHY
235 help
236 Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
237 to 8 external interrupts with configurable sense select.
238
239config SL28CPLD_INTC
240 bool "Kontron sl28cpld IRQ controller"
241 depends on MFD_SL28CPLD=y || COMPILE_TEST
242 select REGMAP_IRQ
243 help
244 Interrupt controller driver for the board management controller
245 found on the Kontron sl28 CPLD.
246
247config ST_IRQCHIP
248 bool
249 select REGMAP
250 select MFD_SYSCON
251 help
252 Enables SysCfg Controlled IRQs on STi based platforms.
253
254config TB10X_IRQC
255 bool
256 select IRQ_DOMAIN
257 select GENERIC_IRQ_CHIP
258
259config TS4800_IRQ
260 tristate "TS-4800 IRQ controller"
261 select IRQ_DOMAIN
262 depends on HAS_IOMEM
263 depends on SOC_IMX51 || COMPILE_TEST
264 help
265 Support for the TS-4800 FPGA IRQ controller
266
267config VERSATILE_FPGA_IRQ
268 bool
269 select IRQ_DOMAIN
270
271config VERSATILE_FPGA_IRQ_NR
272 int
273 default 4
274 depends on VERSATILE_FPGA_IRQ
275
276config XTENSA_MX
277 bool
278 select IRQ_DOMAIN
279 select GENERIC_IRQ_EFFECTIVE_AFF_MASK
280
281config XILINX_INTC
282 bool "Xilinx Interrupt Controller IP"
283 depends on MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP
284 select IRQ_DOMAIN
285 help
286 Support for the Xilinx Interrupt Controller IP core.
287 This is used as a primary controller with MicroBlaze and can also
288 be used as a secondary chained controller on other platforms.
289
290config IRQ_CROSSBAR
291 bool
292 help
293 Support for a CROSSBAR ip that precedes the main interrupt controller.
294 The primary irqchip invokes the crossbar's callback which inturn allocates
295 a free irq and configures the IP. Thus the peripheral interrupts are
296 routed to one of the free irqchip interrupt lines.
297
298config KEYSTONE_IRQ
299 tristate "Keystone 2 IRQ controller IP"
300 depends on ARCH_KEYSTONE
301 help
302 Support for Texas Instruments Keystone 2 IRQ controller IP which
303 is part of the Keystone 2 IPC mechanism
304
305config MIPS_GIC
306 bool
307 select GENERIC_IRQ_IPI
308 select MIPS_CM
309
310config INGENIC_IRQ
311 bool
312 depends on MACH_INGENIC
313 default y
314
315config INGENIC_TCU_IRQ
316 bool "Ingenic JZ47xx TCU interrupt controller"
317 default MACH_INGENIC
318 depends on MIPS || COMPILE_TEST
319 select MFD_SYSCON
320 select GENERIC_IRQ_CHIP
321 help
322 Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
323 JZ47xx SoCs.
324
325 If unsure, say N.
326
327config RENESAS_H8300H_INTC
328 bool
329 select IRQ_DOMAIN
330
331config RENESAS_H8S_INTC
332 bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
333 select IRQ_DOMAIN
334 help
335 Enable support for the Renesas H8/300 Interrupt Controller, as found
336 on Renesas H8S SoCs.
337
338config IMX_GPCV2
339 bool
340 select IRQ_DOMAIN
341 help
342 Enables the wakeup IRQs for IMX platforms with GPCv2 block
343
344config IRQ_MXS
345 def_bool y if MACH_ASM9260 || ARCH_MXS
346 select IRQ_DOMAIN
347 select STMP_DEVICE
348
349config MSCC_OCELOT_IRQ
350 bool
351 select IRQ_DOMAIN
352 select GENERIC_IRQ_CHIP
353
354config MVEBU_GICP
355 bool
356
357config MVEBU_ICU
358 bool
359
360config MVEBU_ODMI
361 bool
362 select GENERIC_MSI_IRQ_DOMAIN
363
364config MVEBU_PIC
365 bool
366
367config MVEBU_SEI
368 bool
369
370config LS_EXTIRQ
371 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
372 select MFD_SYSCON
373
374config LS_SCFG_MSI
375 def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
376 depends on PCI && PCI_MSI
377
378config PARTITION_PERCPU
379 bool
380
381config STM32_EXTI
382 bool
383 select IRQ_DOMAIN
384 select GENERIC_IRQ_CHIP
385
386config QCOM_IRQ_COMBINER
387 bool "QCOM IRQ combiner support"
388 depends on ARCH_QCOM && ACPI
389 select IRQ_DOMAIN_HIERARCHY
390 help
391 Say yes here to add support for the IRQ combiner devices embedded
392 in Qualcomm Technologies chips.
393
394config IRQ_UNIPHIER_AIDET
395 bool "UniPhier AIDET support" if COMPILE_TEST
396 depends on ARCH_UNIPHIER || COMPILE_TEST
397 default ARCH_UNIPHIER
398 select IRQ_DOMAIN_HIERARCHY
399 help
400 Support for the UniPhier AIDET (ARM Interrupt Detector).
401
402config MESON_IRQ_GPIO
403 bool "Meson GPIO Interrupt Multiplexer"
404 depends on ARCH_MESON
405 select IRQ_DOMAIN_HIERARCHY
406 help
407 Support Meson SoC Family GPIO Interrupt Multiplexer
408
409config GOLDFISH_PIC
410 bool "Goldfish programmable interrupt controller"
411 depends on MIPS && (GOLDFISH || COMPILE_TEST)
412 select GENERIC_IRQ_CHIP
413 select IRQ_DOMAIN
414 help
415 Say yes here to enable Goldfish interrupt controller driver used
416 for Goldfish based virtual platforms.
417
418config QCOM_PDC
419 tristate "QCOM PDC"
420 depends on ARCH_QCOM
421 select IRQ_DOMAIN_HIERARCHY
422 help
423 Power Domain Controller driver to manage and configure wakeup
424 IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
425
426config CSKY_MPINTC
427 bool
428 depends on CSKY
429 help
430 Say yes here to enable C-SKY SMP interrupt controller driver used
431 for C-SKY SMP system.
432 In fact it's not mmio map in hardware and it uses ld/st to visit the
433 controller's register inside CPU.
434
435config CSKY_APB_INTC
436 bool "C-SKY APB Interrupt Controller"
437 depends on CSKY
438 help
439 Say yes here to enable C-SKY APB interrupt controller driver used
440 by C-SKY single core SOC system. It uses mmio map apb-bus to visit
441 the controller's register.
442
443config IMX_IRQSTEER
444 bool "i.MX IRQSTEER support"
445 depends on ARCH_MXC || COMPILE_TEST
446 default ARCH_MXC
447 select IRQ_DOMAIN
448 help
449 Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
450
451config IMX_INTMUX
452 bool "i.MX INTMUX support" if COMPILE_TEST
453 default y if ARCH_MXC
454 select IRQ_DOMAIN
455 help
456 Support for the i.MX INTMUX interrupt multiplexer.
457
458config LS1X_IRQ
459 bool "Loongson-1 Interrupt Controller"
460 depends on MACH_LOONGSON32
461 default y
462 select IRQ_DOMAIN
463 select GENERIC_IRQ_CHIP
464 help
465 Support for the Loongson-1 platform Interrupt Controller.
466
467config TI_SCI_INTR_IRQCHIP
468 bool
469 depends on TI_SCI_PROTOCOL
470 select IRQ_DOMAIN_HIERARCHY
471 help
472 This enables the irqchip driver support for K3 Interrupt router
473 over TI System Control Interface available on some new TI's SoCs.
474 If you wish to use interrupt router irq resources managed by the
475 TI System Controller, say Y here. Otherwise, say N.
476
477config TI_SCI_INTA_IRQCHIP
478 bool
479 depends on TI_SCI_PROTOCOL
480 select IRQ_DOMAIN_HIERARCHY
481 select TI_SCI_INTA_MSI_DOMAIN
482 help
483 This enables the irqchip driver support for K3 Interrupt aggregator
484 over TI System Control Interface available on some new TI's SoCs.
485 If you wish to use interrupt aggregator irq resources managed by the
486 TI System Controller, say Y here. Otherwise, say N.
487
488config TI_PRUSS_INTC
489 tristate
490 depends on TI_PRUSS
491 default TI_PRUSS
492 select IRQ_DOMAIN
493 help
494 This enables support for the PRU-ICSS Local Interrupt Controller
495 present within a PRU-ICSS subsystem present on various TI SoCs.
496 The PRUSS INTC enables various interrupts to be routed to multiple
497 different processors within the SoC.
498
499config RISCV_INTC
500 bool "RISC-V Local Interrupt Controller"
501 depends on RISCV
502 default y
503 help
504 This enables support for the per-HART local interrupt controller
505 found in standard RISC-V systems. The per-HART local interrupt
506 controller handles timer interrupts, software interrupts, and
507 hardware interrupts. Without a per-HART local interrupt controller,
508 a RISC-V system will be unable to handle any interrupts.
509
510 If you don't know what to do here, say Y.
511
512config SIFIVE_PLIC
513 bool "SiFive Platform-Level Interrupt Controller"
514 depends on RISCV
515 select IRQ_DOMAIN_HIERARCHY
516 help
517 This enables support for the PLIC chip found in SiFive (and
518 potentially other) RISC-V systems. The PLIC controls devices
519 interrupts and connects them to each core's local interrupt
520 controller. Aside from timer and software interrupts, all other
521 interrupt sources are subordinate to the PLIC.
522
523 If you don't know what to do here, say Y.
524
525config EXYNOS_IRQ_COMBINER
526 bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
527 depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
528 help
529 Say yes here to add support for the IRQ combiner devices embedded
530 in Samsung Exynos chips.
531
532config LOONGSON_LIOINTC
533 bool "Loongson Local I/O Interrupt Controller"
534 depends on MACH_LOONGSON64
535 default y
536 select IRQ_DOMAIN
537 select GENERIC_IRQ_CHIP
538 help
539 Support for the Loongson Local I/O Interrupt Controller.
540
541config LOONGSON_HTPIC
542 bool "Loongson3 HyperTransport PIC Controller"
543 depends on MACH_LOONGSON64
544 default y
545 select IRQ_DOMAIN
546 select GENERIC_IRQ_CHIP
547 help
548 Support for the Loongson-3 HyperTransport PIC Controller.
549
550config LOONGSON_HTVEC
551 bool "Loongson3 HyperTransport Interrupt Vector Controller"
552 depends on MACH_LOONGSON64
553 default MACH_LOONGSON64
554 select IRQ_DOMAIN_HIERARCHY
555 help
556 Support for the Loongson3 HyperTransport Interrupt Vector Controller.
557
558config LOONGSON_PCH_PIC
559 bool "Loongson PCH PIC Controller"
560 depends on MACH_LOONGSON64 || COMPILE_TEST
561 default MACH_LOONGSON64
562 select IRQ_DOMAIN_HIERARCHY
563 select IRQ_FASTEOI_HIERARCHY_HANDLERS
564 help
565 Support for the Loongson PCH PIC Controller.
566
567config LOONGSON_PCH_MSI
568 bool "Loongson PCH MSI Controller"
569 depends on MACH_LOONGSON64 || COMPILE_TEST
570 depends on PCI
571 default MACH_LOONGSON64
572 select IRQ_DOMAIN_HIERARCHY
573 select PCI_MSI
574 help
575 Support for the Loongson PCH MSI Controller.
576
577config MST_IRQ
578 bool "MStar Interrupt Controller"
579 depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
580 default ARCH_MEDIATEK
581 select IRQ_DOMAIN
582 select IRQ_DOMAIN_HIERARCHY
583 help
584 Support MStar Interrupt Controller.
585
586config WPCM450_AIC
587 bool "Nuvoton WPCM450 Advanced Interrupt Controller"
588 depends on ARCH_WPCM450
589 help
590 Support for the interrupt controller in the Nuvoton WPCM450 BMC SoC.
591
592config IRQ_IDT3243X
593 bool
594 select GENERIC_IRQ_CHIP
595 select IRQ_DOMAIN
596
597config APPLE_AIC
598 bool "Apple Interrupt Controller (AIC)"
599 depends on ARM64
600 depends on ARCH_APPLE || COMPILE_TEST
601 help
602 Support for the Apple Interrupt Controller found on Apple Silicon SoCs,
603 such as the M1.
604
605endmenu