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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
24
25#ifndef AMDGPU_AMDKFD_H_INCLUDED
26#define AMDGPU_AMDKFD_H_INCLUDED
27
28#include <linux/list.h>
29#include <linux/types.h>
30#include <linux/mm.h>
31#include <linux/kthread.h>
32#include <linux/workqueue.h>
33#include <linux/mmu_notifier.h>
34#include <linux/memremap.h>
35#include <kgd_kfd_interface.h>
36#include <drm/drm_client.h>
37#include "amdgpu_sync.h"
38#include "amdgpu_vm.h"
39#include "amdgpu_xcp.h"
40
41extern uint64_t amdgpu_amdkfd_total_mem_size;
42
43enum TLB_FLUSH_TYPE {
44 TLB_FLUSH_LEGACY = 0,
45 TLB_FLUSH_LIGHTWEIGHT,
46 TLB_FLUSH_HEAVYWEIGHT
47};
48
49struct amdgpu_device;
50
51enum kfd_mem_attachment_type {
52 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
53 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */
54 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */
55 KFD_MEM_ATT_SG /* Tag to DMA map SG BOs */
56};
57
58struct kfd_mem_attachment {
59 struct list_head list;
60 enum kfd_mem_attachment_type type;
61 bool is_mapped;
62 struct amdgpu_bo_va *bo_va;
63 struct amdgpu_device *adev;
64 uint64_t va;
65 uint64_t pte_flags;
66};
67
68struct kgd_mem {
69 struct mutex lock;
70 struct amdgpu_bo *bo;
71 struct dma_buf *dmabuf;
72 struct hmm_range *range;
73 struct list_head attachments;
74 /* protected by amdkfd_process_info.lock */
75 struct list_head validate_list;
76 uint32_t domain;
77 unsigned int mapped_to_gpu_memory;
78 uint64_t va;
79
80 uint32_t alloc_flags;
81
82 uint32_t invalid;
83 struct amdkfd_process_info *process_info;
84
85 struct amdgpu_sync sync;
86
87 uint32_t gem_handle;
88 bool aql_queue;
89 bool is_imported;
90};
91
92/* KFD Memory Eviction */
93struct amdgpu_amdkfd_fence {
94 struct dma_fence base;
95 struct mm_struct *mm;
96 spinlock_t lock;
97 char timeline_name[TASK_COMM_LEN];
98 struct svm_range_bo *svm_bo;
99};
100
101struct amdgpu_kfd_dev {
102 struct kfd_dev *dev;
103 int64_t vram_used[MAX_XCP];
104 uint64_t vram_used_aligned[MAX_XCP];
105 bool init_complete;
106 struct work_struct reset_work;
107
108 /* HMM page migration MEMORY_DEVICE_PRIVATE mapping */
109 struct dev_pagemap pgmap;
110
111 /* Client for KFD BO GEM handle allocations */
112 struct drm_client_dev client;
113};
114
115enum kgd_engine_type {
116 KGD_ENGINE_PFP = 1,
117 KGD_ENGINE_ME,
118 KGD_ENGINE_CE,
119 KGD_ENGINE_MEC1,
120 KGD_ENGINE_MEC2,
121 KGD_ENGINE_RLC,
122 KGD_ENGINE_SDMA1,
123 KGD_ENGINE_SDMA2,
124 KGD_ENGINE_MAX
125};
126
127
128struct amdkfd_process_info {
129 /* List head of all VMs that belong to a KFD process */
130 struct list_head vm_list_head;
131 /* List head for all KFD BOs that belong to a KFD process. */
132 struct list_head kfd_bo_list;
133 /* List of userptr BOs that are valid or invalid */
134 struct list_head userptr_valid_list;
135 struct list_head userptr_inval_list;
136 /* Lock to protect kfd_bo_list */
137 struct mutex lock;
138
139 /* Number of VMs */
140 unsigned int n_vms;
141 /* Eviction Fence */
142 struct amdgpu_amdkfd_fence *eviction_fence;
143
144 /* MMU-notifier related fields */
145 struct mutex notifier_lock;
146 uint32_t evicted_bos;
147 struct delayed_work restore_userptr_work;
148 struct pid *pid;
149 bool block_mmu_notifications;
150};
151
152int amdgpu_amdkfd_init(void);
153void amdgpu_amdkfd_fini(void);
154
155void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
156int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
157void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
158 const void *ih_ring_entry);
159void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
160void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
161void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
162int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev);
163void amdgpu_amdkfd_unlock_kfd(struct amdgpu_device *adev);
164int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev,
165 enum kgd_engine_type engine,
166 uint32_t vmid, uint64_t gpu_addr,
167 uint32_t *ib_cmd, uint32_t ib_len);
168void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle);
169bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev);
170
171bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
172
173int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
174
175int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
176
177void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev);
178
179int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
180 int queue_bit);
181
182struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
183 struct mm_struct *mm,
184 struct svm_range_bo *svm_bo);
185
186int amdgpu_amdkfd_drm_client_create(struct amdgpu_device *adev);
187#if defined(CONFIG_DEBUG_FS)
188int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data);
189#endif
190#if IS_ENABLED(CONFIG_HSA_AMD)
191bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
192struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
193int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
194int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
195 unsigned long cur_seq, struct kgd_mem *mem);
196#else
197static inline
198bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
199{
200 return false;
201}
202
203static inline
204struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
205{
206 return NULL;
207}
208
209static inline
210int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
211{
212 return 0;
213}
214
215static inline
216int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni,
217 unsigned long cur_seq, struct kgd_mem *mem)
218{
219 return 0;
220}
221#endif
222/* Shared API */
223int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size,
224 void **mem_obj, uint64_t *gpu_addr,
225 void **cpu_ptr, bool mqd_gfx9);
226void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void *mem_obj);
227int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size,
228 void **mem_obj);
229void amdgpu_amdkfd_free_gws(struct amdgpu_device *adev, void *mem_obj);
230int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
231int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
232uint32_t amdgpu_amdkfd_get_fw_version(struct amdgpu_device *adev,
233 enum kgd_engine_type type);
234void amdgpu_amdkfd_get_local_mem_info(struct amdgpu_device *adev,
235 struct kfd_local_mem_info *mem_info,
236 struct amdgpu_xcp *xcp);
237uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct amdgpu_device *adev);
238
239uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct amdgpu_device *adev);
240int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd,
241 struct amdgpu_device **dmabuf_adev,
242 uint64_t *bo_size, void *metadata_buffer,
243 size_t buffer_size, uint32_t *metadata_size,
244 uint32_t *flags, int8_t *xcp_id);
245uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst,
246 struct amdgpu_device *src);
247int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst,
248 struct amdgpu_device *src,
249 bool is_min);
250int amdgpu_amdkfd_get_pcie_bandwidth_mbytes(struct amdgpu_device *adev, bool is_min);
251int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev,
252 uint32_t *payload);
253int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off,
254 u32 inst);
255
256/* Read user wptr from a specified user address space with page fault
257 * disabled. The memory must be pinned and mapped to the hardware when
258 * this is called in hqd_load functions, so it should never fault in
259 * the first place. This resolves a circular lock dependency involving
260 * four locks, including the DQM lock and mmap_lock.
261 */
262#define read_user_wptr(mmptr, wptr, dst) \
263 ({ \
264 bool valid = false; \
265 if ((mmptr) && (wptr)) { \
266 pagefault_disable(); \
267 if ((mmptr) == current->mm) { \
268 valid = !get_user((dst), (wptr)); \
269 } else if (current->flags & PF_KTHREAD) { \
270 kthread_use_mm(mmptr); \
271 valid = !get_user((dst), (wptr)); \
272 kthread_unuse_mm(mmptr); \
273 } \
274 pagefault_enable(); \
275 } \
276 valid; \
277 })
278
279/* GPUVM API */
280#define drm_priv_to_vm(drm_priv) \
281 (&((struct amdgpu_fpriv *) \
282 ((struct drm_file *)(drm_priv))->driver_priv)->vm)
283
284int amdgpu_amdkfd_gpuvm_set_vm_pasid(struct amdgpu_device *adev,
285 struct amdgpu_vm *avm, u32 pasid);
286int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct amdgpu_device *adev,
287 struct amdgpu_vm *avm,
288 void **process_info,
289 struct dma_fence **ef);
290void amdgpu_amdkfd_gpuvm_release_process_vm(struct amdgpu_device *adev,
291 void *drm_priv);
292uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
293size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev,
294 uint8_t xcp_id);
295int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
296 struct amdgpu_device *adev, uint64_t va, uint64_t size,
297 void *drm_priv, struct kgd_mem **mem,
298 uint64_t *offset, uint32_t flags, bool criu_resume);
299int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
300 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv,
301 uint64_t *size);
302int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(struct amdgpu_device *adev,
303 struct kgd_mem *mem, void *drm_priv);
304int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
305 struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv);
306int amdgpu_amdkfd_gpuvm_dmaunmap_mem(struct kgd_mem *mem, void *drm_priv);
307int amdgpu_amdkfd_gpuvm_sync_memory(
308 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
309int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_mem *mem,
310 void **kptr, uint64_t *size);
311void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem);
312
313int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_device *adev, struct amdgpu_bo *bo);
314
315int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
316 struct dma_fence __rcu **ef);
317int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev,
318 struct kfd_vm_fault_info *info);
319int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd,
320 uint64_t va, void *drm_priv,
321 struct kgd_mem **mem, uint64_t *size,
322 uint64_t *mmap_offset);
323int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem,
324 struct dma_buf **dmabuf);
325void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev);
326int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev,
327 struct tile_config *config);
328void amdgpu_amdkfd_ras_poison_consumption_handler(struct amdgpu_device *adev,
329 bool reset);
330bool amdgpu_amdkfd_bo_mapped_to_dev(struct amdgpu_device *adev, struct kgd_mem *mem);
331void amdgpu_amdkfd_block_mmu_notifications(void *p);
332int amdgpu_amdkfd_criu_resume(void *p);
333bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev);
334int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
335 uint64_t size, u32 alloc_flag, int8_t xcp_id);
336void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev,
337 uint64_t size, u32 alloc_flag, int8_t xcp_id);
338
339u64 amdgpu_amdkfd_xcp_memory_size(struct amdgpu_device *adev, int xcp_id);
340
341#define KFD_XCP_MEM_ID(adev, xcp_id) \
342 ((adev)->xcp_mgr && (xcp_id) >= 0 ?\
343 (adev)->xcp_mgr->xcp[(xcp_id)].mem_id : -1)
344
345#define KFD_XCP_MEMORY_SIZE(adev, xcp_id) amdgpu_amdkfd_xcp_memory_size((adev), (xcp_id))
346
347
348#if IS_ENABLED(CONFIG_HSA_AMD)
349void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
350void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
351 struct amdgpu_vm *vm);
352
353/**
354 * @amdgpu_amdkfd_release_notify() - Notify KFD when GEM object is released
355 *
356 * Allows KFD to release its resources associated with the GEM object.
357 */
358void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo);
359void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
360#else
361static inline
362void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
363{
364}
365
366static inline
367void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
368 struct amdgpu_vm *vm)
369{
370}
371
372static inline
373void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo)
374{
375}
376#endif
377
378#if IS_ENABLED(CONFIG_HSA_AMD_SVM)
379int kgd2kfd_init_zone_device(struct amdgpu_device *adev);
380#else
381static inline
382int kgd2kfd_init_zone_device(struct amdgpu_device *adev)
383{
384 return 0;
385}
386#endif
387
388/* KGD2KFD callbacks */
389int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger);
390int kgd2kfd_resume_mm(struct mm_struct *mm);
391int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
392 struct dma_fence *fence);
393#if IS_ENABLED(CONFIG_HSA_AMD)
394int kgd2kfd_init(void);
395void kgd2kfd_exit(void);
396struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf);
397bool kgd2kfd_device_init(struct kfd_dev *kfd,
398 const struct kgd2kfd_shared_resources *gpu_resources);
399void kgd2kfd_device_exit(struct kfd_dev *kfd);
400void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
401int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
402int kgd2kfd_pre_reset(struct kfd_dev *kfd);
403int kgd2kfd_post_reset(struct kfd_dev *kfd);
404void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
405void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
406void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask);
407int kgd2kfd_check_and_lock_kfd(void);
408void kgd2kfd_unlock_kfd(void);
409#else
410static inline int kgd2kfd_init(void)
411{
412 return -ENOENT;
413}
414
415static inline void kgd2kfd_exit(void)
416{
417}
418
419static inline
420struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf)
421{
422 return NULL;
423}
424
425static inline
426bool kgd2kfd_device_init(struct kfd_dev *kfd,
427 const struct kgd2kfd_shared_resources *gpu_resources)
428{
429 return false;
430}
431
432static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
433{
434}
435
436static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
437{
438}
439
440static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
441{
442 return 0;
443}
444
445static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
446{
447 return 0;
448}
449
450static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
451{
452 return 0;
453}
454
455static inline
456void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
457{
458}
459
460static inline
461void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
462{
463}
464
465static inline
466void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask)
467{
468}
469
470static inline int kgd2kfd_check_and_lock_kfd(void)
471{
472 return 0;
473}
474
475static inline void kgd2kfd_unlock_kfd(void)
476{
477}
478#endif
479#endif /* AMDGPU_AMDKFD_H_INCLUDED */
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23/* amdgpu_amdkfd.h defines the private interface between amdgpu and amdkfd. */
24
25#ifndef AMDGPU_AMDKFD_H_INCLUDED
26#define AMDGPU_AMDKFD_H_INCLUDED
27
28#include <linux/types.h>
29#include <linux/mm.h>
30#include <linux/kthread.h>
31#include <linux/workqueue.h>
32#include <kgd_kfd_interface.h>
33#include <drm/ttm/ttm_execbuf_util.h>
34#include "amdgpu_sync.h"
35#include "amdgpu_vm.h"
36
37extern uint64_t amdgpu_amdkfd_total_mem_size;
38
39enum TLB_FLUSH_TYPE {
40 TLB_FLUSH_LEGACY = 0,
41 TLB_FLUSH_LIGHTWEIGHT,
42 TLB_FLUSH_HEAVYWEIGHT
43};
44
45struct amdgpu_device;
46
47enum kfd_mem_attachment_type {
48 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
49 KFD_MEM_ATT_USERPTR, /* SG bo to DMA map pages from a userptr bo */
50 KFD_MEM_ATT_DMABUF, /* DMAbuf to DMA map TTM BOs */
51};
52
53struct kfd_mem_attachment {
54 struct list_head list;
55 enum kfd_mem_attachment_type type;
56 bool is_mapped;
57 struct amdgpu_bo_va *bo_va;
58 struct amdgpu_device *adev;
59 uint64_t va;
60 uint64_t pte_flags;
61};
62
63struct kgd_mem {
64 struct mutex lock;
65 struct amdgpu_bo *bo;
66 struct dma_buf *dmabuf;
67 struct list_head attachments;
68 /* protected by amdkfd_process_info.lock */
69 struct ttm_validate_buffer validate_list;
70 struct ttm_validate_buffer resv_list;
71 uint32_t domain;
72 unsigned int mapped_to_gpu_memory;
73 uint64_t va;
74
75 uint32_t alloc_flags;
76
77 atomic_t invalid;
78 struct amdkfd_process_info *process_info;
79
80 struct amdgpu_sync sync;
81
82 bool aql_queue;
83 bool is_imported;
84};
85
86/* KFD Memory Eviction */
87struct amdgpu_amdkfd_fence {
88 struct dma_fence base;
89 struct mm_struct *mm;
90 spinlock_t lock;
91 char timeline_name[TASK_COMM_LEN];
92 struct svm_range_bo *svm_bo;
93};
94
95struct amdgpu_kfd_dev {
96 struct kfd_dev *dev;
97 uint64_t vram_used;
98 bool init_complete;
99};
100
101enum kgd_engine_type {
102 KGD_ENGINE_PFP = 1,
103 KGD_ENGINE_ME,
104 KGD_ENGINE_CE,
105 KGD_ENGINE_MEC1,
106 KGD_ENGINE_MEC2,
107 KGD_ENGINE_RLC,
108 KGD_ENGINE_SDMA1,
109 KGD_ENGINE_SDMA2,
110 KGD_ENGINE_MAX
111};
112
113
114struct amdkfd_process_info {
115 /* List head of all VMs that belong to a KFD process */
116 struct list_head vm_list_head;
117 /* List head for all KFD BOs that belong to a KFD process. */
118 struct list_head kfd_bo_list;
119 /* List of userptr BOs that are valid or invalid */
120 struct list_head userptr_valid_list;
121 struct list_head userptr_inval_list;
122 /* Lock to protect kfd_bo_list */
123 struct mutex lock;
124
125 /* Number of VMs */
126 unsigned int n_vms;
127 /* Eviction Fence */
128 struct amdgpu_amdkfd_fence *eviction_fence;
129
130 /* MMU-notifier related fields */
131 atomic_t evicted_bos;
132 struct delayed_work restore_userptr_work;
133 struct pid *pid;
134};
135
136int amdgpu_amdkfd_init(void);
137void amdgpu_amdkfd_fini(void);
138
139void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm);
140int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev);
141int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm);
142void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
143 const void *ih_ring_entry);
144void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev);
145void amdgpu_amdkfd_device_init(struct amdgpu_device *adev);
146void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev);
147int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
148 uint32_t vmid, uint64_t gpu_addr,
149 uint32_t *ib_cmd, uint32_t ib_len);
150void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle);
151bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd);
152int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid);
153int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid,
154 enum TLB_FLUSH_TYPE flush_type);
155
156bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid);
157
158int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev);
159
160int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev);
161
162void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd);
163
164int amdgpu_queue_mask_bit_to_set_resource_bit(struct amdgpu_device *adev,
165 int queue_bit);
166
167struct amdgpu_amdkfd_fence *amdgpu_amdkfd_fence_create(u64 context,
168 struct mm_struct *mm,
169 struct svm_range_bo *svm_bo);
170#if IS_ENABLED(CONFIG_HSA_AMD)
171bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm);
172struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f);
173int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo);
174int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm);
175#else
176static inline
177bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
178{
179 return false;
180}
181
182static inline
183struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
184{
185 return NULL;
186}
187
188static inline
189int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
190{
191 return 0;
192}
193
194static inline
195int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
196{
197 return 0;
198}
199#endif
200/* Shared API */
201int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
202 void **mem_obj, uint64_t *gpu_addr,
203 void **cpu_ptr, bool mqd_gfx9);
204void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj);
205int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size, void **mem_obj);
206void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj);
207int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem);
208int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem);
209uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
210 enum kgd_engine_type type);
211void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
212 struct kfd_local_mem_info *mem_info);
213uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd);
214
215uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd);
216void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info);
217int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
218 struct kgd_dev **dmabuf_kgd,
219 uint64_t *bo_size, void *metadata_buffer,
220 size_t buffer_size, uint32_t *metadata_size,
221 uint32_t *flags);
222uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd);
223uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd);
224uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd);
225uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd);
226uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd);
227uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd);
228int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd);
229uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src);
230
231/* Read user wptr from a specified user address space with page fault
232 * disabled. The memory must be pinned and mapped to the hardware when
233 * this is called in hqd_load functions, so it should never fault in
234 * the first place. This resolves a circular lock dependency involving
235 * four locks, including the DQM lock and mmap_lock.
236 */
237#define read_user_wptr(mmptr, wptr, dst) \
238 ({ \
239 bool valid = false; \
240 if ((mmptr) && (wptr)) { \
241 pagefault_disable(); \
242 if ((mmptr) == current->mm) { \
243 valid = !get_user((dst), (wptr)); \
244 } else if (current->flags & PF_KTHREAD) { \
245 kthread_use_mm(mmptr); \
246 valid = !get_user((dst), (wptr)); \
247 kthread_unuse_mm(mmptr); \
248 } \
249 pagefault_enable(); \
250 } \
251 valid; \
252 })
253
254/* GPUVM API */
255#define drm_priv_to_vm(drm_priv) \
256 (&((struct amdgpu_fpriv *) \
257 ((struct drm_file *)(drm_priv))->driver_priv)->vm)
258
259int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
260 struct file *filp, u32 pasid,
261 void **process_info,
262 struct dma_fence **ef);
263void amdgpu_amdkfd_gpuvm_release_process_vm(struct kgd_dev *kgd, void *drm_priv);
264uint64_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *drm_priv);
265int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
266 struct kgd_dev *kgd, uint64_t va, uint64_t size,
267 void *drm_priv, struct kgd_mem **mem,
268 uint64_t *offset, uint32_t flags);
269int amdgpu_amdkfd_gpuvm_free_memory_of_gpu(
270 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv,
271 uint64_t *size);
272int amdgpu_amdkfd_gpuvm_map_memory_to_gpu(
273 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
274int amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu(
275 struct kgd_dev *kgd, struct kgd_mem *mem, void *drm_priv);
276int amdgpu_amdkfd_gpuvm_sync_memory(
277 struct kgd_dev *kgd, struct kgd_mem *mem, bool intr);
278int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd,
279 struct kgd_mem *mem, void **kptr, uint64_t *size);
280int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info,
281 struct dma_fence **ef);
282int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct kgd_dev *kgd,
283 struct kfd_vm_fault_info *info);
284int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd,
285 struct dma_buf *dmabuf,
286 uint64_t va, void *drm_priv,
287 struct kgd_mem **mem, uint64_t *size,
288 uint64_t *mmap_offset);
289int amdgpu_amdkfd_get_tile_config(struct kgd_dev *kgd,
290 struct tile_config *config);
291#if IS_ENABLED(CONFIG_HSA_AMD)
292void amdgpu_amdkfd_gpuvm_init_mem_limits(void);
293void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
294 struct amdgpu_vm *vm);
295void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo);
296void amdgpu_amdkfd_reserve_system_mem(uint64_t size);
297#else
298static inline
299void amdgpu_amdkfd_gpuvm_init_mem_limits(void)
300{
301}
302
303static inline
304void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
305 struct amdgpu_vm *vm)
306{
307}
308
309static inline
310void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
311{
312}
313#endif
314/* KGD2KFD callbacks */
315int kgd2kfd_quiesce_mm(struct mm_struct *mm);
316int kgd2kfd_resume_mm(struct mm_struct *mm);
317int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm,
318 struct dma_fence *fence);
319#if IS_ENABLED(CONFIG_HSA_AMD)
320int kgd2kfd_init(void);
321void kgd2kfd_exit(void);
322struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
323 unsigned int asic_type, bool vf);
324bool kgd2kfd_device_init(struct kfd_dev *kfd,
325 struct drm_device *ddev,
326 const struct kgd2kfd_shared_resources *gpu_resources);
327void kgd2kfd_device_exit(struct kfd_dev *kfd);
328void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm);
329int kgd2kfd_resume_iommu(struct kfd_dev *kfd);
330int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm);
331int kgd2kfd_pre_reset(struct kfd_dev *kfd);
332int kgd2kfd_post_reset(struct kfd_dev *kfd);
333void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry);
334void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd);
335void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask);
336#else
337static inline int kgd2kfd_init(void)
338{
339 return -ENOENT;
340}
341
342static inline void kgd2kfd_exit(void)
343{
344}
345
346static inline
347struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
348 unsigned int asic_type, bool vf)
349{
350 return NULL;
351}
352
353static inline
354bool kgd2kfd_device_init(struct kfd_dev *kfd, struct drm_device *ddev,
355 const struct kgd2kfd_shared_resources *gpu_resources)
356{
357 return false;
358}
359
360static inline void kgd2kfd_device_exit(struct kfd_dev *kfd)
361{
362}
363
364static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
365{
366}
367
368static int __maybe_unused kgd2kfd_resume_iommu(struct kfd_dev *kfd)
369{
370 return 0;
371}
372
373static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
374{
375 return 0;
376}
377
378static inline int kgd2kfd_pre_reset(struct kfd_dev *kfd)
379{
380 return 0;
381}
382
383static inline int kgd2kfd_post_reset(struct kfd_dev *kfd)
384{
385 return 0;
386}
387
388static inline
389void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
390{
391}
392
393static inline
394void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
395{
396}
397
398static inline
399void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint32_t throttle_bitmask)
400{
401}
402#endif
403#endif /* AMDGPU_AMDKFD_H_INCLUDED */