1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2/*
   3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
   4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
   5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
   6 */
   7#include <linux/types.h>
   8#include <linux/slab.h>
   9#include <linux/export.h>
  10#include <linux/etherdevice.h>
  11#include <linux/pci.h>
  12#include <linux/firmware.h>
  13
  14#include "iwl-drv.h"
  15#include "iwl-modparams.h"
  16#include "iwl-nvm-parse.h"
  17#include "iwl-prph.h"
  18#include "iwl-io.h"
  19#include "iwl-csr.h"
  20#include "fw/acpi.h"
  21#include "fw/api/nvm-reg.h"
  22#include "fw/api/commands.h"
  23#include "fw/api/cmdhdr.h"
  24#include "fw/img.h"
  25#include "mei/iwl-mei.h"
  26
  27/* NVM offsets (in words) definitions */
  28enum nvm_offsets {
  29	/* NVM HW-Section offset (in words) definitions */
  30	SUBSYSTEM_ID = 0x0A,
  31	HW_ADDR = 0x15,
  32
  33	/* NVM SW-Section offset (in words) definitions */
  34	NVM_SW_SECTION = 0x1C0,
  35	NVM_VERSION = 0,
  36	RADIO_CFG = 1,
  37	SKU = 2,
  38	N_HW_ADDRS = 3,
  39	NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
  40
  41	/* NVM calibration section offset (in words) definitions */
  42	NVM_CALIB_SECTION = 0x2B8,
  43	XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
  44
  45	/* NVM REGULATORY -Section offset (in words) definitions */
  46	NVM_CHANNELS_SDP = 0,
  47};
  48
  49enum ext_nvm_offsets {
  50	/* NVM HW-Section offset (in words) definitions */
  51	MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
  52
  53	/* NVM SW-Section offset (in words) definitions */
  54	NVM_VERSION_EXT_NVM = 0,
  55	N_HW_ADDRS_FAMILY_8000 = 3,
  56
  57	/* NVM PHY_SKU-Section offset (in words) definitions */
  58	RADIO_CFG_FAMILY_EXT_NVM = 0,
  59	SKU_FAMILY_8000 = 2,
  60
  61	/* NVM REGULATORY -Section offset (in words) definitions */
  62	NVM_CHANNELS_EXTENDED = 0,
  63	NVM_LAR_OFFSET_OLD = 0x4C7,
  64	NVM_LAR_OFFSET = 0x507,
  65	NVM_LAR_ENABLED = 0x7,
  66};
  67
  68/* SKU Capabilities (actual values from NVM definition) */
  69enum nvm_sku_bits {
  70	NVM_SKU_CAP_BAND_24GHZ		= BIT(0),
  71	NVM_SKU_CAP_BAND_52GHZ		= BIT(1),
  72	NVM_SKU_CAP_11N_ENABLE		= BIT(2),
  73	NVM_SKU_CAP_11AC_ENABLE		= BIT(3),
  74	NVM_SKU_CAP_MIMO_DISABLE	= BIT(5),
  75};
  76
  77/*
  78 * These are the channel numbers in the order that they are stored in the NVM
  79 */
  80static const u16 iwl_nvm_channels[] = {
  81	/* 2.4 GHz */
  82	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  83	/* 5 GHz */
  84	36, 40, 44, 48, 52, 56, 60, 64,
  85	100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  86	149, 153, 157, 161, 165
  87};
  88
  89static const u16 iwl_ext_nvm_channels[] = {
  90	/* 2.4 GHz */
  91	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
  92	/* 5 GHz */
  93	36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
  94	96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
  95	149, 153, 157, 161, 165, 169, 173, 177, 181
  96};
  97
  98static const u16 iwl_uhb_nvm_channels[] = {
  99	/* 2.4 GHz */
 100	1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
 101	/* 5 GHz */
 102	36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
 103	96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
 104	149, 153, 157, 161, 165, 169, 173, 177, 181,
 105	/* 6-7 GHz */
 106	1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
 107	73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
 108	133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
 109	189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
 110};
 111
 112#define IWL_NVM_NUM_CHANNELS		ARRAY_SIZE(iwl_nvm_channels)
 113#define IWL_NVM_NUM_CHANNELS_EXT	ARRAY_SIZE(iwl_ext_nvm_channels)
 114#define IWL_NVM_NUM_CHANNELS_UHB	ARRAY_SIZE(iwl_uhb_nvm_channels)
 115#define NUM_2GHZ_CHANNELS		14
 116#define NUM_5GHZ_CHANNELS		37
 117#define FIRST_2GHZ_HT_MINUS		5
 118#define LAST_2GHZ_HT_PLUS		9
 119#define N_HW_ADDR_MASK			0xF
 120
 121/* rate data (static) */
 122static struct ieee80211_rate iwl_cfg80211_rates[] = {
 123	{ .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
 124	{ .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
 125	  .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
 126	{ .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
 127	  .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
 128	{ .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
 129	  .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
 130	{ .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
 131	{ .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
 132	{ .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
 133	{ .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
 134	{ .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
 135	{ .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
 136	{ .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
 137	{ .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
 138};
 139#define RATES_24_OFFS	0
 140#define N_RATES_24	ARRAY_SIZE(iwl_cfg80211_rates)
 141#define RATES_52_OFFS	4
 142#define N_RATES_52	(N_RATES_24 - RATES_52_OFFS)
 143
 144/**
 145 * enum iwl_nvm_channel_flags - channel flags in NVM
 146 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
 147 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
 148 * @NVM_CHANNEL_ACTIVE: active scanning allowed
 149 * @NVM_CHANNEL_RADAR: radar detection required
 150 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
 151 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
 152 *	on same channel on 2.4 or same UNII band on 5.2
 153 * @NVM_CHANNEL_UNIFORM: uniform spreading required
 154 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
 155 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
 156 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
 157 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
 158 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
 159 */
 160enum iwl_nvm_channel_flags {
 161	NVM_CHANNEL_VALID		= BIT(0),
 162	NVM_CHANNEL_IBSS		= BIT(1),
 163	NVM_CHANNEL_ACTIVE		= BIT(3),
 164	NVM_CHANNEL_RADAR		= BIT(4),
 165	NVM_CHANNEL_INDOOR_ONLY		= BIT(5),
 166	NVM_CHANNEL_GO_CONCURRENT	= BIT(6),
 167	NVM_CHANNEL_UNIFORM		= BIT(7),
 168	NVM_CHANNEL_20MHZ		= BIT(8),
 169	NVM_CHANNEL_40MHZ		= BIT(9),
 170	NVM_CHANNEL_80MHZ		= BIT(10),
 171	NVM_CHANNEL_160MHZ		= BIT(11),
 172	NVM_CHANNEL_DC_HIGH		= BIT(12),
 173};
 174
 175/**
 176 * enum iwl_reg_capa_flags_v1 - global flags applied for the whole regulatory
 177 * domain.
 178 * @REG_CAPA_V1_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
 179 *	2.4Ghz band is allowed.
 180 * @REG_CAPA_V1_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
 181 *	5Ghz band is allowed.
 182 * @REG_CAPA_V1_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
 183 *	for this regulatory domain (valid only in 5Ghz).
 184 * @REG_CAPA_V1_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
 185 *	for this regulatory domain (valid only in 5Ghz).
 186 * @REG_CAPA_V1_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
 187 * @REG_CAPA_V1_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
 188 * @REG_CAPA_V1_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
 189 *	for this regulatory domain (valid only in 5Ghz).
 190 * @REG_CAPA_V1_DC_HIGH_ENABLED: DC HIGH allowed.
 191 * @REG_CAPA_V1_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
 192 */
 193enum iwl_reg_capa_flags_v1 {
 194	REG_CAPA_V1_BF_CCD_LOW_BAND	= BIT(0),
 195	REG_CAPA_V1_BF_CCD_HIGH_BAND	= BIT(1),
 196	REG_CAPA_V1_160MHZ_ALLOWED	= BIT(2),
 197	REG_CAPA_V1_80MHZ_ALLOWED	= BIT(3),
 198	REG_CAPA_V1_MCS_8_ALLOWED	= BIT(4),
 199	REG_CAPA_V1_MCS_9_ALLOWED	= BIT(5),
 200	REG_CAPA_V1_40MHZ_FORBIDDEN	= BIT(7),
 201	REG_CAPA_V1_DC_HIGH_ENABLED	= BIT(9),
 202	REG_CAPA_V1_11AX_DISABLED	= BIT(10),
 203}; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_1 */
 204
 205/**
 206 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory
 207 * domain (version 2).
 208 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are
 209 *	disabled.
 210 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
 211 *	2.4Ghz band is allowed.
 212 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
 213 *	5Ghz band is allowed.
 214 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
 215 *	for this regulatory domain (valid only in 5Ghz).
 216 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
 217 *	for this regulatory domain (valid only in 5Ghz).
 218 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
 219 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
 220 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118,
 221 *	126, 122) are disabled.
 222 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed
 223 *	for this regulatory domain (uvalid only in 5Ghz).
 224 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
 225 */
 226enum iwl_reg_capa_flags_v2 {
 227	REG_CAPA_V2_STRADDLE_DISABLED	= BIT(0),
 228	REG_CAPA_V2_BF_CCD_LOW_BAND	= BIT(1),
 229	REG_CAPA_V2_BF_CCD_HIGH_BAND	= BIT(2),
 230	REG_CAPA_V2_160MHZ_ALLOWED	= BIT(3),
 231	REG_CAPA_V2_80MHZ_ALLOWED	= BIT(4),
 232	REG_CAPA_V2_MCS_8_ALLOWED	= BIT(5),
 233	REG_CAPA_V2_MCS_9_ALLOWED	= BIT(6),
 234	REG_CAPA_V2_WEATHER_DISABLED	= BIT(7),
 235	REG_CAPA_V2_40MHZ_ALLOWED	= BIT(8),
 236	REG_CAPA_V2_11AX_DISABLED	= BIT(10),
 237}; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_2 */
 238
 239/**
 240 * enum iwl_reg_capa_flags_v4 - global flags applied for the whole regulatory
 241 * domain.
 242 * @REG_CAPA_V4_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
 243 *	for this regulatory domain (valid only in 5Ghz).
 244 * @REG_CAPA_V4_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
 245 *	for this regulatory domain (valid only in 5Ghz).
 246 * @REG_CAPA_V4_MCS_12_ALLOWED: 11ac with MCS 12 is allowed.
 247 * @REG_CAPA_V4_MCS_13_ALLOWED: 11ac with MCS 13 is allowed.
 248 * @REG_CAPA_V4_11BE_DISABLED: 11be is forbidden for this regulatory domain.
 249 * @REG_CAPA_V4_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
 250 * @REG_CAPA_V4_320MHZ_ALLOWED: 11be channel with a width of 320Mhz is allowed
 251 *	for this regulatory domain (valid only in 5GHz).
 252 */
 253enum iwl_reg_capa_flags_v4 {
 254	REG_CAPA_V4_160MHZ_ALLOWED		= BIT(3),
 255	REG_CAPA_V4_80MHZ_ALLOWED		= BIT(4),
 256	REG_CAPA_V4_MCS_12_ALLOWED		= BIT(5),
 257	REG_CAPA_V4_MCS_13_ALLOWED		= BIT(6),
 258	REG_CAPA_V4_11BE_DISABLED		= BIT(8),
 259	REG_CAPA_V4_11AX_DISABLED		= BIT(13),
 260	REG_CAPA_V4_320MHZ_ALLOWED		= BIT(16),
 261}; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_4 */
 262
 263/*
 264* API v2 for reg_capa_flags is relevant from version 6 and onwards of the
 265* MCC update command response.
 266*/
 267#define REG_CAPA_V2_RESP_VER	6
 268
 269/* API v4 for reg_capa_flags is relevant from version 8 and onwards of the
 270 * MCC update command response.
 271 */
 272#define REG_CAPA_V4_RESP_VER	8
 273
 274/**
 275 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for
 276 * handling the different APIs of reg_capa_flags.
 277 *
 278 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed
 279 *	for this regulatory domain.
 280 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed
 281 *	for this regulatory domain (valid only in 5 and 6 Ghz).
 282 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed
 283 *	for this regulatory domain (valid only in 5 and 6 Ghz).
 284 * @allow_320mhz: 11be channel with a width of 320Mhz is allowed
 285 *	for this regulatory domain (valid only in 6 Ghz).
 286 * @disable_11ax: 11ax is forbidden for this regulatory domain.
 287 * @disable_11be: 11be is forbidden for this regulatory domain.
 288 */
 289struct iwl_reg_capa {
 290	bool allow_40mhz;
 291	bool allow_80mhz;
 292	bool allow_160mhz;
 293	bool allow_320mhz;
 294	bool disable_11ax;
 295	bool disable_11be;
 296};
 297
 298static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
 299					       int chan, u32 flags)
 300{
 301#define CHECK_AND_PRINT_I(x)	\
 302	((flags & NVM_CHANNEL_##x) ? " " #x : "")
 303
 304	if (!(flags & NVM_CHANNEL_VALID)) {
 305		IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
 306			      chan, flags);
 307		return;
 308	}
 309
 310	/* Note: already can print up to 101 characters, 110 is the limit! */
 311	IWL_DEBUG_DEV(dev, level,
 312		      "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
 313		      chan, flags,
 314		      CHECK_AND_PRINT_I(VALID),
 315		      CHECK_AND_PRINT_I(IBSS),
 316		      CHECK_AND_PRINT_I(ACTIVE),
 317		      CHECK_AND_PRINT_I(RADAR),
 318		      CHECK_AND_PRINT_I(INDOOR_ONLY),
 319		      CHECK_AND_PRINT_I(GO_CONCURRENT),
 320		      CHECK_AND_PRINT_I(UNIFORM),
 321		      CHECK_AND_PRINT_I(20MHZ),
 322		      CHECK_AND_PRINT_I(40MHZ),
 323		      CHECK_AND_PRINT_I(80MHZ),
 324		      CHECK_AND_PRINT_I(160MHZ),
 325		      CHECK_AND_PRINT_I(DC_HIGH));
 326#undef CHECK_AND_PRINT_I
 327}
 328
 329static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
 330				 u32 nvm_flags, const struct iwl_cfg *cfg)
 331{
 332	u32 flags = IEEE80211_CHAN_NO_HT40;
 333
 334	if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
 335		if (ch_num <= LAST_2GHZ_HT_PLUS)
 336			flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
 337		if (ch_num >= FIRST_2GHZ_HT_MINUS)
 338			flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
 339	} else if (nvm_flags & NVM_CHANNEL_40MHZ) {
 340		if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
 341			flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
 342		else
 343			flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
 344	}
 345	if (!(nvm_flags & NVM_CHANNEL_80MHZ))
 346		flags |= IEEE80211_CHAN_NO_80MHZ;
 347	if (!(nvm_flags & NVM_CHANNEL_160MHZ))
 348		flags |= IEEE80211_CHAN_NO_160MHZ;
 349
 350	if (!(nvm_flags & NVM_CHANNEL_IBSS))
 351		flags |= IEEE80211_CHAN_NO_IR;
 352
 353	if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
 354		flags |= IEEE80211_CHAN_NO_IR;
 355
 356	if (nvm_flags & NVM_CHANNEL_RADAR)
 357		flags |= IEEE80211_CHAN_RADAR;
 358
 359	if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
 360		flags |= IEEE80211_CHAN_INDOOR_ONLY;
 361
 362	/* Set the GO concurrent flag only in case that NO_IR is set.
 363	 * Otherwise it is meaningless
 364	 */
 365	if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
 366	    (flags & IEEE80211_CHAN_NO_IR))
 367		flags |= IEEE80211_CHAN_IR_CONCURRENT;
 368
 369	return flags;
 370}
 371
 372static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
 373{
 374	if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) {
 375		return NL80211_BAND_6GHZ;
 376	}
 377
 378	if (ch_idx >= NUM_2GHZ_CHANNELS)
 379		return NL80211_BAND_5GHZ;
 380	return NL80211_BAND_2GHZ;
 381}
 382
 383static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
 384				struct iwl_nvm_data *data,
 385				const void * const nvm_ch_flags,
 386				u32 sbands_flags, bool v4)
 387{
 388	int ch_idx;
 389	int n_channels = 0;
 390	struct ieee80211_channel *channel;
 391	u32 ch_flags;
 392	int num_of_ch;
 393	const u16 *nvm_chan;
 394
 395	if (cfg->uhb_supported) {
 396		num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
 397		nvm_chan = iwl_uhb_nvm_channels;
 398	} else if (cfg->nvm_type == IWL_NVM_EXT) {
 399		num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
 400		nvm_chan = iwl_ext_nvm_channels;
 401	} else {
 402		num_of_ch = IWL_NVM_NUM_CHANNELS;
 403		nvm_chan = iwl_nvm_channels;
 404	}
 405
 406	for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
 407		enum nl80211_band band =
 408			iwl_nl80211_band_from_channel_idx(ch_idx);
 409
 410		if (v4)
 411			ch_flags =
 412				__le32_to_cpup((const __le32 *)nvm_ch_flags + ch_idx);
 413		else
 414			ch_flags =
 415				__le16_to_cpup((const __le16 *)nvm_ch_flags + ch_idx);
 416
 417		if (band == NL80211_BAND_5GHZ &&
 418		    !data->sku_cap_band_52ghz_enable)
 419			continue;
 420
 421		/* workaround to disable wide channels in 5GHz */
 422		if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
 423		    band == NL80211_BAND_5GHZ) {
 424			ch_flags &= ~(NVM_CHANNEL_40MHZ |
 425				     NVM_CHANNEL_80MHZ |
 426				     NVM_CHANNEL_160MHZ);
 427		}
 428
 429		if (ch_flags & NVM_CHANNEL_160MHZ)
 430			data->vht160_supported = true;
 431
 432		if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
 433		    !(ch_flags & NVM_CHANNEL_VALID)) {
 434			/*
 435			 * Channels might become valid later if lar is
 436			 * supported, hence we still want to add them to
 437			 * the list of supported channels to cfg80211.
 438			 */
 439			iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
 440						    nvm_chan[ch_idx], ch_flags);
 441			continue;
 442		}
 443
 444		channel = &data->channels[n_channels];
 445		n_channels++;
 446
 447		channel->hw_value = nvm_chan[ch_idx];
 448		channel->band = band;
 449		channel->center_freq =
 450			ieee80211_channel_to_frequency(
 451				channel->hw_value, channel->band);
 452
 453		/* Initialize regulatory-based run-time data */
 454
 455		/*
 456		 * Default value - highest tx power value.  max_power
 457		 * is not used in mvm, and is used for backwards compatibility
 458		 */
 459		channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
 460
 461		/* don't put limitations in case we're using LAR */
 462		if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
 463			channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
 464							       ch_idx, band,
 465							       ch_flags, cfg);
 466		else
 467			channel->flags = 0;
 468
 469		/* TODO: Don't put limitations on UHB devices as we still don't
 470		 * have NVM for them
 471		 */
 472		if (cfg->uhb_supported)
 473			channel->flags = 0;
 474		iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
 475					    channel->hw_value, ch_flags);
 476		IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
 477				 channel->hw_value, channel->max_power);
 478	}
 479
 480	return n_channels;
 481}
 482
 483static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
 484				  struct iwl_nvm_data *data,
 485				  struct ieee80211_sta_vht_cap *vht_cap,
 486				  u8 tx_chains, u8 rx_chains)
 487{
 488	const struct iwl_cfg *cfg = trans->cfg;
 489	int num_rx_ants = num_of_ant(rx_chains);
 490	int num_tx_ants = num_of_ant(tx_chains);
 491
 492	vht_cap->vht_supported = true;
 493
 494	vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
 495		       IEEE80211_VHT_CAP_RXSTBC_1 |
 496		       IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
 497		       3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
 498		       IEEE80211_VHT_MAX_AMPDU_1024K <<
 499		       IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
 500
 501	if (!trans->cfg->ht_params->stbc)
 502		vht_cap->cap &= ~IEEE80211_VHT_CAP_RXSTBC_MASK;
 503
 504	if (data->vht160_supported)
 505		vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
 506				IEEE80211_VHT_CAP_SHORT_GI_160;
 507
 508	if (cfg->vht_mu_mimo_supported)
 509		vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
 510
 511	if (cfg->ht_params->ldpc)
 512		vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
 513
 514	if (data->sku_cap_mimo_disabled) {
 515		num_rx_ants = 1;
 516		num_tx_ants = 1;
 517	}
 518
 519	if (trans->cfg->ht_params->stbc && num_tx_ants > 1)
 520		vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
 521	else
 522		vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
 523
 524	switch (iwlwifi_mod_params.amsdu_size) {
 525	case IWL_AMSDU_DEF:
 526		if (trans->trans_cfg->mq_rx_supported)
 527			vht_cap->cap |=
 528				IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
 529		else
 530			vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
 531		break;
 532	case IWL_AMSDU_2K:
 533		if (trans->trans_cfg->mq_rx_supported)
 534			vht_cap->cap |=
 535				IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
 536		else
 537			WARN(1, "RB size of 2K is not supported by this device\n");
 538		break;
 539	case IWL_AMSDU_4K:
 540		vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
 541		break;
 542	case IWL_AMSDU_8K:
 543		vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
 544		break;
 545	case IWL_AMSDU_12K:
 546		vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
 547		break;
 548	default:
 549		break;
 550	}
 551
 552	vht_cap->vht_mcs.rx_mcs_map =
 553		cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
 554			    IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
 555			    IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
 556			    IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
 557			    IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
 558			    IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
 559			    IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
 560			    IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
 561
 562	if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
 563		vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
 564		/* this works because NOT_SUPPORTED == 3 */
 565		vht_cap->vht_mcs.rx_mcs_map |=
 566			cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
 567	}
 568
 569	vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
 570
 571	vht_cap->vht_mcs.tx_highest |=
 572		cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
 573}
 574
 575static const u8 iwl_vendor_caps[] = {
 576	0xdd,			/* vendor element */
 577	0x06,			/* length */
 578	0x00, 0x17, 0x35,	/* Intel OUI */
 579	0x08,			/* type (Intel Capabilities) */
 580	/* followed by 16 bits of capabilities */
 581#define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE	BIT(0)
 582	IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE,
 583	0x00
 584};
 585
 586static const struct ieee80211_sband_iftype_data iwl_he_eht_capa[] = {
 587	{
 588		.types_mask = BIT(NL80211_IFTYPE_STATION),
 589		.he_cap = {
 590			.has_he = true,
 591			.he_cap_elem = {
 592				.mac_cap_info[0] =
 593					IEEE80211_HE_MAC_CAP0_HTC_HE,
 
 594				.mac_cap_info[1] =
 595					IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
 596					IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
 597				.mac_cap_info[2] =
 598					IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
 599				.mac_cap_info[3] =
 600					IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
 601					IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS,
 602				.mac_cap_info[4] =
 603					IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU |
 604					IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
 605				.mac_cap_info[5] =
 606					IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
 607					IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
 608					IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
 609					IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
 610					IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
 
 
 
 
 611				.phy_cap_info[1] =
 612					IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
 613					IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
 614					IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
 615				.phy_cap_info[2] =
 616					IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
 617					IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ,
 618				.phy_cap_info[3] =
 619					IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK |
 620					IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
 621					IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK |
 622					IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
 623				.phy_cap_info[4] =
 624					IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
 625					IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
 626					IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
 627				.phy_cap_info[6] =
 628					IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
 629					IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB |
 630					IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
 631				.phy_cap_info[7] =
 632					IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
 633					IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
 634				.phy_cap_info[8] =
 635					IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
 636					IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
 637					IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
 638					IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
 639					IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
 640				.phy_cap_info[9] =
 641					IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
 642					IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
 643					(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED <<
 644					IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS),
 645				.phy_cap_info[10] =
 646					IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF,
 647			},
 648			/*
 649			 * Set default Tx/Rx HE MCS NSS Support field.
 650			 * Indicate support for up to 2 spatial streams and all
 651			 * MCS, without any special cases
 652			 */
 653			.he_mcs_nss_supp = {
 654				.rx_mcs_80 = cpu_to_le16(0xfffa),
 655				.tx_mcs_80 = cpu_to_le16(0xfffa),
 656				.rx_mcs_160 = cpu_to_le16(0xfffa),
 657				.tx_mcs_160 = cpu_to_le16(0xfffa),
 658				.rx_mcs_80p80 = cpu_to_le16(0xffff),
 659				.tx_mcs_80p80 = cpu_to_le16(0xffff),
 660			},
 661			/*
 662			 * Set default PPE thresholds, with PPET16 set to 0,
 663			 * PPET8 set to 7
 664			 */
 665			.ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
 666		},
 667		.eht_cap = {
 668			.has_eht = true,
 669			.eht_cap_elem = {
 670				.mac_cap_info[0] =
 671					IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
 672					IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
 673					IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2 |
 674					IEEE80211_EHT_MAC_CAP0_SCS_TRAFFIC_DESC,
 675				.phy_cap_info[0] =
 676					IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ |
 677					IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
 678					IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO |
 679					IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE |
 680					IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK,
 681				.phy_cap_info[1] =
 682					IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK  |
 683					IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK,
 684				.phy_cap_info[3] =
 685					IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
 686					IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
 687					IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
 688					IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
 689					IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
 690					IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK |
 691					IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK,
 692
 693				.phy_cap_info[4] =
 694					IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO |
 695					IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
 696					IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI,
 697				.phy_cap_info[5] =
 698					IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK |
 699					IEEE80211_EHT_PHY_CAP5_TX_LESS_242_TONE_RU_SUPP |
 700					IEEE80211_EHT_PHY_CAP5_RX_LESS_242_TONE_RU_SUPP |
 701					IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT,
 702				.phy_cap_info[6] =
 703					IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK |
 704					IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP,
 705				.phy_cap_info[8] =
 706					IEEE80211_EHT_PHY_CAP8_RX_1024QAM_WIDER_BW_DL_OFDMA |
 707					IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA,
 708			},
 709
 710			/* For all MCS and bandwidth, set 2 NSS for both Tx and
 711			 * Rx - note we don't set the only_20mhz, but due to this
 712			 * being a union, it gets set correctly anyway.
 713			 */
 714			.eht_mcs_nss_supp = {
 715				.bw._80 = {
 716					.rx_tx_mcs9_max_nss = 0x22,
 717					.rx_tx_mcs11_max_nss = 0x22,
 718					.rx_tx_mcs13_max_nss = 0x22,
 719				},
 720				.bw._160 = {
 721					.rx_tx_mcs9_max_nss = 0x22,
 722					.rx_tx_mcs11_max_nss = 0x22,
 723					.rx_tx_mcs13_max_nss = 0x22,
 724				},
 725				.bw._320 = {
 726					.rx_tx_mcs9_max_nss = 0x22,
 727					.rx_tx_mcs11_max_nss = 0x22,
 728					.rx_tx_mcs13_max_nss = 0x22,
 729				},
 730			},
 731
 732			/*
 733			 * PPE thresholds for NSS = 2, and RU index bitmap set
 734			 * to 0xc.
 735			 */
 736			.eht_ppe_thres = {0xc1, 0x0e, 0xe0 }
 737		},
 738	},
 739	{
 740		.types_mask = BIT(NL80211_IFTYPE_AP),
 741		.he_cap = {
 742			.has_he = true,
 743			.he_cap_elem = {
 744				.mac_cap_info[0] =
 745					IEEE80211_HE_MAC_CAP0_HTC_HE,
 746				.mac_cap_info[1] =
 747					IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
 748					IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
 749				.mac_cap_info[3] =
 750					IEEE80211_HE_MAC_CAP3_OMI_CONTROL,
 
 
 
 751				.phy_cap_info[1] =
 752					IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
 753				.phy_cap_info[2] =
 754					IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
 755					IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
 756				.phy_cap_info[3] =
 757					IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK |
 758					IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
 759					IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK |
 760					IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
 761				.phy_cap_info[6] =
 762					IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
 763				.phy_cap_info[7] =
 764					IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
 765				.phy_cap_info[8] =
 766					IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
 767					IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
 768				.phy_cap_info[9] =
 769					IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED
 770					<< IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS,
 771			},
 772			/*
 773			 * Set default Tx/Rx HE MCS NSS Support field.
 774			 * Indicate support for up to 2 spatial streams and all
 775			 * MCS, without any special cases
 776			 */
 777			.he_mcs_nss_supp = {
 778				.rx_mcs_80 = cpu_to_le16(0xfffa),
 779				.tx_mcs_80 = cpu_to_le16(0xfffa),
 780				.rx_mcs_160 = cpu_to_le16(0xfffa),
 781				.tx_mcs_160 = cpu_to_le16(0xfffa),
 782				.rx_mcs_80p80 = cpu_to_le16(0xffff),
 783				.tx_mcs_80p80 = cpu_to_le16(0xffff),
 784			},
 785			/*
 786			 * Set default PPE thresholds, with PPET16 set to 0,
 787			 * PPET8 set to 7
 788			 */
 789			.ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
 790		},
 791		.eht_cap = {
 792			.has_eht = true,
 793			.eht_cap_elem = {
 794				.mac_cap_info[0] =
 795					IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
 796					IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
 797					IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2,
 798				.phy_cap_info[0] =
 799					IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ |
 800					IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI,
 801				.phy_cap_info[5] =
 802					IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT,
 803			},
 804
 805			/* For all MCS and bandwidth, set 2 NSS for both Tx and
 806			 * Rx - note we don't set the only_20mhz, but due to this
 807			 * being a union, it gets set correctly anyway.
 808			 */
 809			.eht_mcs_nss_supp = {
 810				.bw._80 = {
 811					.rx_tx_mcs9_max_nss = 0x22,
 812					.rx_tx_mcs11_max_nss = 0x22,
 813					.rx_tx_mcs13_max_nss = 0x22,
 814				},
 815				.bw._160 = {
 816					.rx_tx_mcs9_max_nss = 0x22,
 817					.rx_tx_mcs11_max_nss = 0x22,
 818					.rx_tx_mcs13_max_nss = 0x22,
 819				},
 820				.bw._320 = {
 821					.rx_tx_mcs9_max_nss = 0x22,
 822					.rx_tx_mcs11_max_nss = 0x22,
 823					.rx_tx_mcs13_max_nss = 0x22,
 824				},
 825			},
 826
 827			/*
 828			 * PPE thresholds for NSS = 2, and RU index bitmap set
 829			 * to 0xc.
 830			 */
 831			.eht_ppe_thres = {0xc1, 0x0e, 0xe0 }
 832		},
 833	},
 834};
 835
 836static void iwl_init_he_6ghz_capa(struct iwl_trans *trans,
 837				  struct iwl_nvm_data *data,
 838				  struct ieee80211_supported_band *sband,
 839				  u8 tx_chains, u8 rx_chains)
 840{
 841	struct ieee80211_sta_ht_cap ht_cap;
 842	struct ieee80211_sta_vht_cap vht_cap = {};
 843	struct ieee80211_sband_iftype_data *iftype_data;
 844	u16 he_6ghz_capa = 0;
 845	u32 exp;
 846	int i;
 847
 848	if (sband->band != NL80211_BAND_6GHZ)
 849		return;
 850
 851	/* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */
 852	iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ,
 853			     tx_chains, rx_chains);
 854	WARN_ON(!ht_cap.ht_supported);
 855	iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains);
 856	WARN_ON(!vht_cap.vht_supported);
 857
 858	he_6ghz_capa |=
 859		u16_encode_bits(ht_cap.ampdu_density,
 860				IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START);
 861	exp = u32_get_bits(vht_cap.cap,
 862			   IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
 863	he_6ghz_capa |=
 864		u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP);
 865	exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK);
 866	he_6ghz_capa |=
 867		u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
 868	/* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */
 869	if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN)
 870		he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS;
 871	if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN)
 872		he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
 873
 874	IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa);
 875
 876	/* we know it's writable - we set it before ourselves */
 877	iftype_data = (void *)(uintptr_t)sband->iftype_data;
 878	for (i = 0; i < sband->n_iftype_data; i++)
 879		iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa);
 880}
 881
 882static void
 883iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
 884			 struct iwl_nvm_data *data,
 885			 struct ieee80211_supported_band *sband,
 886			 struct ieee80211_sband_iftype_data *iftype_data,
 887			 u8 tx_chains, u8 rx_chains,
 888			 const struct iwl_fw *fw)
 889{
 890	bool is_ap = iftype_data->types_mask & BIT(NL80211_IFTYPE_AP);
 891	bool no_320;
 892
 893	no_320 = !trans->trans_cfg->integrated &&
 894		 trans->pcie_link_speed < PCI_EXP_LNKSTA_CLS_8_0GB;
 895
 896	if (!data->sku_cap_11be_enable || iwlwifi_mod_params.disable_11be)
 897		iftype_data->eht_cap.has_eht = false;
 898
 899	/* Advertise an A-MPDU exponent extension based on
 900	 * operating band
 901	 */
 902	if (sband->band == NL80211_BAND_6GHZ && iftype_data->eht_cap.has_eht)
 903		iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
 904			IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
 905	else if (sband->band != NL80211_BAND_2GHZ)
 906		iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
 907			IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1;
 908	else
 909		iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
 910			IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
 911
 912	switch (sband->band) {
 913	case NL80211_BAND_2GHZ:
 914		iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
 915			IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
 916		iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] |=
 917			u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
 918				       IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
 919		break;
 920	case NL80211_BAND_6GHZ:
 921		if (!no_320) {
 922			iftype_data->eht_cap.eht_cap_elem.phy_cap_info[0] |=
 923				IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
 924			iftype_data->eht_cap.eht_cap_elem.phy_cap_info[1] |=
 925				IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK;
 926		}
 927		fallthrough;
 928	case NL80211_BAND_5GHZ:
 929		iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
 930			IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
 931			IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
 932		break;
 933	default:
 934		WARN_ON(1);
 935		break;
 936	}
 937
 938	if ((tx_chains & rx_chains) == ANT_AB) {
 939		iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |=
 940			IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ;
 941		iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |=
 942			IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
 943			IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2;
 944		if (!is_ap) {
 945			iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
 946				IEEE80211_HE_PHY_CAP7_MAX_NC_2;
 947
 948			if (iftype_data->eht_cap.has_eht) {
 949				/*
 950				 * Set the number of sounding dimensions for each
 951				 * bandwidth to 1 to indicate the maximal supported
 952				 * value of TXVECTOR parameter NUM_STS of 2
 953				 */
 954				iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] |= 0x49;
 955
 956				/*
 957				 * Set the MAX NC to 1 to indicate sounding feedback of
 958				 * 2 supported by the beamfomee.
 959				 */
 960				iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] |= 0x10;
 961			}
 962		}
 963	} else {
 964		struct ieee80211_he_mcs_nss_supp *he_mcs_nss_supp =
 965			&iftype_data->he_cap.he_mcs_nss_supp;
 966
 967		if (iftype_data->eht_cap.has_eht) {
 968			struct ieee80211_eht_mcs_nss_supp *mcs_nss =
 969				&iftype_data->eht_cap.eht_mcs_nss_supp;
 970
 971			memset(mcs_nss, 0x11, sizeof(*mcs_nss));
 972		}
 973
 974		if (!is_ap) {
 975			/* If not 2x2, we need to indicate 1x1 in the
 976			 * Midamble RX Max NSTS - but not for AP mode
 977			 */
 978			iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &=
 979				~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
 980			iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
 981				~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
 982			iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
 983				IEEE80211_HE_PHY_CAP7_MAX_NC_1;
 984		}
 985
 986		he_mcs_nss_supp->rx_mcs_80 |=
 987			cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
 988		he_mcs_nss_supp->tx_mcs_80 |=
 989			cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
 990		he_mcs_nss_supp->rx_mcs_160 |=
 991			cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
 992		he_mcs_nss_supp->tx_mcs_160 |=
 993			cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
 994		he_mcs_nss_supp->rx_mcs_80p80 |=
 995			cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
 996		he_mcs_nss_supp->tx_mcs_80p80 |=
 997			cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
 998	}
 999
1000	if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210 && !is_ap)
1001		iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |=
1002			IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
1003
1004	switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
1005	case IWL_CFG_RF_TYPE_GF:
1006	case IWL_CFG_RF_TYPE_MR:
1007	case IWL_CFG_RF_TYPE_MS:
1008	case IWL_CFG_RF_TYPE_FM:
1009	case IWL_CFG_RF_TYPE_WH:
1010		iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
1011			IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
1012		if (!is_ap)
1013			iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
1014				IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1015		break;
1016	}
1017
1018	if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL &&
1019	    iftype_data->eht_cap.has_eht) {
1020		iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] &=
1021			~(IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
1022			  IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2);
1023		iftype_data->eht_cap.eht_cap_elem.phy_cap_info[3] &=
1024			~(IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO |
1025			  IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
1026			  IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
1027			  IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
1028			  IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
1029			  IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK |
1030			  IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK);
1031		iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] &=
1032			~(IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO |
1033			  IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP);
1034		iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] &=
1035			~IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK;
1036		iftype_data->eht_cap.eht_cap_elem.phy_cap_info[6] &=
1037			~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK |
1038			  IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP);
1039		iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] |=
1040			IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF;
1041	}
1042
1043	if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT))
1044		iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |=
1045			IEEE80211_HE_MAC_CAP2_BCAST_TWT;
1046
1047	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1048	    !is_ap) {
1049		iftype_data->vendor_elems.data = iwl_vendor_caps;
1050		iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps);
1051	}
1052
1053	if (!trans->cfg->ht_params->stbc) {
1054		iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
1055			~IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1056		iftype_data->he_cap.he_cap_elem.phy_cap_info[7] &=
1057			~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1058	}
1059}
1060
1061static void iwl_init_he_hw_capab(struct iwl_trans *trans,
1062				 struct iwl_nvm_data *data,
1063				 struct ieee80211_supported_band *sband,
1064				 u8 tx_chains, u8 rx_chains,
1065				 const struct iwl_fw *fw)
1066{
1067	struct ieee80211_sband_iftype_data *iftype_data;
1068	int i;
1069
1070	BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_eht_capa));
1071	BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_eht_capa));
1072	BUILD_BUG_ON(sizeof(data->iftd.uhb) != sizeof(iwl_he_eht_capa));
 
 
 
1073
1074	switch (sband->band) {
1075	case NL80211_BAND_2GHZ:
1076		iftype_data = data->iftd.low;
1077		break;
1078	case NL80211_BAND_5GHZ:
1079		iftype_data = data->iftd.high;
1080		break;
1081	case NL80211_BAND_6GHZ:
1082		iftype_data = data->iftd.uhb;
1083		break;
1084	default:
1085		WARN_ON(1);
1086		return;
1087	}
1088
1089	memcpy(iftype_data, iwl_he_eht_capa, sizeof(iwl_he_eht_capa));
1090
1091	_ieee80211_set_sband_iftype_data(sband, iftype_data,
1092					 ARRAY_SIZE(iwl_he_eht_capa));
1093
1094	for (i = 0; i < sband->n_iftype_data; i++)
1095		iwl_nvm_fixup_sband_iftd(trans, data, sband, &iftype_data[i],
1096					 tx_chains, rx_chains, fw);
1097
1098	iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains);
1099}
1100
1101void iwl_reinit_cab(struct iwl_trans *trans, struct iwl_nvm_data *data,
1102		    u8 tx_chains, u8 rx_chains, const struct iwl_fw *fw)
1103{
1104	struct ieee80211_supported_band *sband;
1105
1106	sband = &data->bands[NL80211_BAND_2GHZ];
1107	iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
1108			     tx_chains, rx_chains);
1109
1110	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1111		iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1112				     fw);
1113
1114	sband = &data->bands[NL80211_BAND_5GHZ];
1115	iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
1116			     tx_chains, rx_chains);
1117	if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
1118		iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
1119				      tx_chains, rx_chains);
1120
1121	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1122		iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1123				     fw);
1124
1125	sband = &data->bands[NL80211_BAND_6GHZ];
1126	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1127		iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1128				     fw);
1129}
1130IWL_EXPORT_SYMBOL(iwl_reinit_cab);
1131
1132static void iwl_init_sbands(struct iwl_trans *trans,
1133			    struct iwl_nvm_data *data,
1134			    const void *nvm_ch_flags, u8 tx_chains,
1135			    u8 rx_chains, u32 sbands_flags, bool v4,
1136			    const struct iwl_fw *fw)
1137{
1138	struct device *dev = trans->dev;
1139	const struct iwl_cfg *cfg = trans->cfg;
1140	int n_channels;
1141	int n_used = 0;
1142	struct ieee80211_supported_band *sband;
1143
1144	n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
1145					  sbands_flags, v4);
1146	sband = &data->bands[NL80211_BAND_2GHZ];
1147	sband->band = NL80211_BAND_2GHZ;
1148	sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
1149	sband->n_bitrates = N_RATES_24;
1150	n_used += iwl_init_sband_channels(data, sband, n_channels,
1151					  NL80211_BAND_2GHZ);
1152	iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
1153			     tx_chains, rx_chains);
1154
1155	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1156		iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1157				     fw);
1158
1159	sband = &data->bands[NL80211_BAND_5GHZ];
1160	sband->band = NL80211_BAND_5GHZ;
1161	sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
1162	sband->n_bitrates = N_RATES_52;
1163	n_used += iwl_init_sband_channels(data, sband, n_channels,
1164					  NL80211_BAND_5GHZ);
1165	iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
1166			     tx_chains, rx_chains);
1167	if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
1168		iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
1169				      tx_chains, rx_chains);
1170
1171	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1172		iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1173				     fw);
1174
1175	/* 6GHz band. */
1176	sband = &data->bands[NL80211_BAND_6GHZ];
1177	sband->band = NL80211_BAND_6GHZ;
1178	/* use the same rates as 5GHz band */
1179	sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
1180	sband->n_bitrates = N_RATES_52;
1181	n_used += iwl_init_sband_channels(data, sband, n_channels,
1182					  NL80211_BAND_6GHZ);
1183
1184	if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1185		iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1186				     fw);
1187	else
1188		sband->n_channels = 0;
1189	if (n_channels != n_used)
1190		IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
1191			    n_used, n_channels);
1192}
1193
1194static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
1195		       const __le16 *phy_sku)
1196{
1197	if (cfg->nvm_type != IWL_NVM_EXT)
1198		return le16_to_cpup(nvm_sw + SKU);
1199
1200	return le32_to_cpup((const __le32 *)(phy_sku + SKU_FAMILY_8000));
1201}
1202
1203static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
1204{
1205	if (cfg->nvm_type != IWL_NVM_EXT)
1206		return le16_to_cpup(nvm_sw + NVM_VERSION);
1207	else
1208		return le32_to_cpup((const __le32 *)(nvm_sw +
1209						     NVM_VERSION_EXT_NVM));
1210}
1211
1212static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
1213			     const __le16 *phy_sku)
1214{
1215	if (cfg->nvm_type != IWL_NVM_EXT)
1216		return le16_to_cpup(nvm_sw + RADIO_CFG);
1217
1218	return le32_to_cpup((const __le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
1219
1220}
1221
1222static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
1223{
1224	int n_hw_addr;
1225
1226	if (cfg->nvm_type != IWL_NVM_EXT)
1227		return le16_to_cpup(nvm_sw + N_HW_ADDRS);
1228
1229	n_hw_addr = le32_to_cpup((const __le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
1230
1231	return n_hw_addr & N_HW_ADDR_MASK;
1232}
1233
1234static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
1235			      struct iwl_nvm_data *data,
1236			      u32 radio_cfg)
1237{
1238	if (cfg->nvm_type != IWL_NVM_EXT) {
1239		data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
1240		data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
1241		data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
1242		data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
1243		return;
1244	}
1245
1246	/* set the radio configuration for family 8000 */
1247	data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
1248	data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
1249	data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
1250	data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
1251	data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
1252	data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
1253}
1254
1255static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
1256{
1257	const u8 *hw_addr;
1258
1259	hw_addr = (const u8 *)&mac_addr0;
1260	dest[0] = hw_addr[3];
1261	dest[1] = hw_addr[2];
1262	dest[2] = hw_addr[1];
1263	dest[3] = hw_addr[0];
1264
1265	hw_addr = (const u8 *)&mac_addr1;
1266	dest[4] = hw_addr[1];
1267	dest[5] = hw_addr[0];
1268}
1269
1270static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
1271					struct iwl_nvm_data *data)
1272{
1273	__le32 mac_addr0 = cpu_to_le32(iwl_read32(trans,
1274						  CSR_MAC_ADDR0_STRAP(trans)));
1275	__le32 mac_addr1 = cpu_to_le32(iwl_read32(trans,
1276						  CSR_MAC_ADDR1_STRAP(trans)));
1277
1278	iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1279	/*
1280	 * If the OEM fused a valid address, use it instead of the one in the
1281	 * OTP
1282	 */
1283	if (is_valid_ether_addr(data->hw_addr))
1284		return;
1285
1286	mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans)));
1287	mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans)));
1288
1289	iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1290}
1291
1292static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
1293					   const struct iwl_cfg *cfg,
1294					   struct iwl_nvm_data *data,
1295					   const __le16 *mac_override,
1296					   const __be16 *nvm_hw)
1297{
1298	const u8 *hw_addr;
1299
1300	if (mac_override) {
1301		static const u8 reserved_mac[] = {
1302			0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
1303		};
1304
1305		hw_addr = (const u8 *)(mac_override +
1306				 MAC_ADDRESS_OVERRIDE_EXT_NVM);
1307
1308		/*
1309		 * Store the MAC address from MAO section.
1310		 * No byte swapping is required in MAO section
1311		 */
1312		memcpy(data->hw_addr, hw_addr, ETH_ALEN);
1313
1314		/*
1315		 * Force the use of the OTP MAC address in case of reserved MAC
1316		 * address in the NVM, or if address is given but invalid.
1317		 */
1318		if (is_valid_ether_addr(data->hw_addr) &&
1319		    memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
1320			return;
1321
1322		IWL_ERR(trans,
1323			"mac address from nvm override section is not valid\n");
1324	}
1325
1326	if (nvm_hw) {
1327		/* read the mac address from WFMP registers */
1328		__le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
1329						WFMP_MAC_ADDR_0));
1330		__le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
1331						WFMP_MAC_ADDR_1));
1332
1333		iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1334
1335		return;
1336	}
1337
1338	IWL_ERR(trans, "mac address is not found\n");
1339}
1340
1341static int iwl_set_hw_address(struct iwl_trans *trans,
1342			      const struct iwl_cfg *cfg,
1343			      struct iwl_nvm_data *data, const __be16 *nvm_hw,
1344			      const __le16 *mac_override)
1345{
1346	if (cfg->mac_addr_from_csr) {
1347		iwl_set_hw_address_from_csr(trans, data);
1348	} else if (cfg->nvm_type != IWL_NVM_EXT) {
1349		const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
1350
1351		/* The byte order is little endian 16 bit, meaning 214365 */
1352		data->hw_addr[0] = hw_addr[1];
1353		data->hw_addr[1] = hw_addr[0];
1354		data->hw_addr[2] = hw_addr[3];
1355		data->hw_addr[3] = hw_addr[2];
1356		data->hw_addr[4] = hw_addr[5];
1357		data->hw_addr[5] = hw_addr[4];
1358	} else {
1359		iwl_set_hw_address_family_8000(trans, cfg, data,
1360					       mac_override, nvm_hw);
1361	}
1362
1363	if (!is_valid_ether_addr(data->hw_addr)) {
1364		IWL_ERR(trans, "no valid mac address was found\n");
1365		return -EINVAL;
1366	}
1367
1368	if (!trans->csme_own)
1369		IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n",
1370			 data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR));
1371
1372	return 0;
1373}
1374
1375static bool
1376iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1377			const __be16 *nvm_hw)
1378{
1379	/*
1380	 * Workaround a bug in Indonesia SKUs where the regulatory in
1381	 * some 7000-family OTPs erroneously allow wide channels in
1382	 * 5GHz.  To check for Indonesia, we take the SKU value from
1383	 * bits 1-4 in the subsystem ID and check if it is either 5 or
1384	 * 9.  In those cases, we need to force-disable wide channels
1385	 * in 5GHz otherwise the FW will throw a sysassert when we try
1386	 * to use them.
1387	 */
1388	if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1389		/*
1390		 * Unlike the other sections in the NVM, the hw
1391		 * section uses big-endian.
1392		 */
1393		u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
1394		u8 sku = (subsystem_id & 0x1e) >> 1;
1395
1396		if (sku == 5 || sku == 9) {
1397			IWL_DEBUG_EEPROM(trans->dev,
1398					 "disabling wide channels in 5GHz (0x%0x %d)\n",
1399					 subsystem_id, sku);
1400			return true;
1401		}
1402	}
1403
1404	return false;
1405}
1406
1407struct iwl_nvm_data *
1408iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1409		       const struct iwl_mei_nvm *mei_nvm,
1410		       const struct iwl_fw *fw, u8 tx_ant, u8 rx_ant)
1411{
1412	struct iwl_nvm_data *data;
1413	u32 sbands_flags = 0;
1414	u8 rx_chains = fw->valid_rx_ant;
1415	u8 tx_chains = fw->valid_rx_ant;
1416
1417	if (cfg->uhb_supported)
1418		data = kzalloc(struct_size(data, channels,
1419					   IWL_NVM_NUM_CHANNELS_UHB),
1420					   GFP_KERNEL);
1421	else
1422		data = kzalloc(struct_size(data, channels,
1423					   IWL_NVM_NUM_CHANNELS_EXT),
1424					   GFP_KERNEL);
1425	if (!data)
1426		return NULL;
1427
1428	BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) !=
1429		     IWL_NVM_NUM_CHANNELS_UHB);
1430	data->nvm_version = mei_nvm->nvm_version;
1431
1432	iwl_set_radio_cfg(cfg, data, mei_nvm->radio_cfg);
1433	if (data->valid_tx_ant)
1434		tx_chains &= data->valid_tx_ant;
1435	if (data->valid_rx_ant)
1436		rx_chains &= data->valid_rx_ant;
1437	if (tx_ant)
1438		tx_chains &= tx_ant;
1439	if (rx_ant)
1440		rx_chains &= rx_ant;
1441
1442	data->sku_cap_mimo_disabled = false;
1443	data->sku_cap_band_24ghz_enable = true;
1444	data->sku_cap_band_52ghz_enable = true;
1445	data->sku_cap_11n_enable =
1446		!(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL);
1447	data->sku_cap_11ac_enable = true;
1448	data->sku_cap_11ax_enable =
1449		mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT;
1450
1451	data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT;
1452
1453	data->n_hw_addrs = mei_nvm->n_hw_addrs;
1454	/* If no valid mac address was found - bail out */
1455	if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) {
1456		kfree(data);
1457		return NULL;
1458	}
1459
1460	if (data->lar_enabled &&
1461	    fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1462		sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1463
1464	iwl_init_sbands(trans, data, mei_nvm->channels, tx_chains, rx_chains,
1465			sbands_flags, true, fw);
1466
1467	return data;
1468}
1469IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data);
1470
1471struct iwl_nvm_data *
1472iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1473		   const struct iwl_fw *fw,
1474		   const __be16 *nvm_hw, const __le16 *nvm_sw,
1475		   const __le16 *nvm_calib, const __le16 *regulatory,
1476		   const __le16 *mac_override, const __le16 *phy_sku,
1477		   u8 tx_chains, u8 rx_chains)
1478{
1479	struct iwl_nvm_data *data;
1480	bool lar_enabled;
1481	u32 sku, radio_cfg;
1482	u32 sbands_flags = 0;
1483	u16 lar_config;
1484	const __le16 *ch_section;
1485
1486	if (cfg->uhb_supported)
1487		data = kzalloc(struct_size(data, channels,
1488					   IWL_NVM_NUM_CHANNELS_UHB),
1489					   GFP_KERNEL);
1490	else if (cfg->nvm_type != IWL_NVM_EXT)
1491		data = kzalloc(struct_size(data, channels,
1492					   IWL_NVM_NUM_CHANNELS),
1493					   GFP_KERNEL);
1494	else
1495		data = kzalloc(struct_size(data, channels,
1496					   IWL_NVM_NUM_CHANNELS_EXT),
1497					   GFP_KERNEL);
1498	if (!data)
1499		return NULL;
1500
1501	data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
1502
1503	radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
1504	iwl_set_radio_cfg(cfg, data, radio_cfg);
1505	if (data->valid_tx_ant)
1506		tx_chains &= data->valid_tx_ant;
1507	if (data->valid_rx_ant)
1508		rx_chains &= data->valid_rx_ant;
1509
1510	sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1511	data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1512	data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1513	data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1514	if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1515		data->sku_cap_11n_enable = false;
1516	data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1517				    (sku & NVM_SKU_CAP_11AC_ENABLE);
1518	data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1519
1520	data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1521
1522	if (cfg->nvm_type != IWL_NVM_EXT) {
1523		/* Checking for required sections */
1524		if (!nvm_calib) {
1525			IWL_ERR(trans,
1526				"Can't parse empty Calib NVM sections\n");
1527			kfree(data);
1528			return NULL;
1529		}
1530
1531		ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1532			     &regulatory[NVM_CHANNELS_SDP] :
1533			     &nvm_sw[NVM_CHANNELS];
1534
1535		/* in family 8000 Xtal calibration values moved to OTP */
1536		data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
1537		data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
1538		lar_enabled = true;
1539	} else {
1540		u16 lar_offset = data->nvm_version < 0xE39 ?
1541				 NVM_LAR_OFFSET_OLD :
1542				 NVM_LAR_OFFSET;
1543
1544		lar_config = le16_to_cpup(regulatory + lar_offset);
1545		data->lar_enabled = !!(lar_config &
1546				       NVM_LAR_ENABLED);
1547		lar_enabled = data->lar_enabled;
1548		ch_section = &regulatory[NVM_CHANNELS_EXTENDED];
1549	}
1550
1551	/* If no valid mac address was found - bail out */
1552	if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1553		kfree(data);
1554		return NULL;
1555	}
1556
1557	if (lar_enabled &&
1558	    fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1559		sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1560
1561	if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1562		sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1563
1564	iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1565			sbands_flags, false, fw);
1566	data->calib_version = 255;
1567
1568	return data;
1569}
1570IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1571
1572static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1573				       int ch_idx, u16 nvm_flags,
1574				       struct iwl_reg_capa reg_capa,
1575				       const struct iwl_cfg *cfg)
1576{
1577	u32 flags = NL80211_RRF_NO_HT40;
1578
1579	if (ch_idx < NUM_2GHZ_CHANNELS &&
1580	    (nvm_flags & NVM_CHANNEL_40MHZ)) {
1581		if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1582			flags &= ~NL80211_RRF_NO_HT40PLUS;
1583		if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1584			flags &= ~NL80211_RRF_NO_HT40MINUS;
1585	} else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1586		if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1587			flags &= ~NL80211_RRF_NO_HT40PLUS;
1588		else
1589			flags &= ~NL80211_RRF_NO_HT40MINUS;
1590	}
1591
1592	if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1593		flags |= NL80211_RRF_NO_80MHZ;
1594	if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1595		flags |= NL80211_RRF_NO_160MHZ;
1596
1597	if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1598		flags |= NL80211_RRF_NO_IR;
1599
1600	if (nvm_flags & NVM_CHANNEL_RADAR)
1601		flags |= NL80211_RRF_DFS;
1602
1603	if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1604		flags |= NL80211_RRF_NO_OUTDOOR;
1605
1606	/* Set the GO concurrent flag only in case that NO_IR is set.
1607	 * Otherwise it is meaningless
1608	 */
1609	if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT)) {
1610		if (flags & NL80211_RRF_NO_IR)
1611			flags |= NL80211_RRF_GO_CONCURRENT;
1612		if (flags & NL80211_RRF_DFS) {
1613			flags |= NL80211_RRF_DFS_CONCURRENT;
1614			/* Our device doesn't set active bit for DFS channels
1615			 * however, once marked as DFS no-ir is not needed.
1616			 */
1617			flags &= ~NL80211_RRF_NO_IR;
1618		}
1619	}
1620	/*
1621	 * reg_capa is per regulatory domain so apply it for every channel
1622	 */
1623	if (ch_idx >= NUM_2GHZ_CHANNELS) {
1624		if (!reg_capa.allow_40mhz)
1625			flags |= NL80211_RRF_NO_HT40;
1626
1627		if (!reg_capa.allow_80mhz)
1628			flags |= NL80211_RRF_NO_80MHZ;
1629
1630		if (!reg_capa.allow_160mhz)
1631			flags |= NL80211_RRF_NO_160MHZ;
1632
1633		if (!reg_capa.allow_320mhz)
1634			flags |= NL80211_RRF_NO_320MHZ;
1635	}
1636
1637	if (reg_capa.disable_11ax)
1638		flags |= NL80211_RRF_NO_HE;
1639
1640	if (reg_capa.disable_11be)
1641		flags |= NL80211_RRF_NO_EHT;
1642
1643	return flags;
1644}
1645
1646static struct iwl_reg_capa iwl_get_reg_capa(u32 flags, u8 resp_ver)
1647{
1648	struct iwl_reg_capa reg_capa = {};
1649
1650	if (resp_ver >= REG_CAPA_V4_RESP_VER) {
1651		reg_capa.allow_40mhz = true;
1652		reg_capa.allow_80mhz = flags & REG_CAPA_V4_80MHZ_ALLOWED;
1653		reg_capa.allow_160mhz = flags & REG_CAPA_V4_160MHZ_ALLOWED;
1654		reg_capa.allow_320mhz = flags & REG_CAPA_V4_320MHZ_ALLOWED;
1655		reg_capa.disable_11ax = flags & REG_CAPA_V4_11AX_DISABLED;
1656		reg_capa.disable_11be = flags & REG_CAPA_V4_11BE_DISABLED;
1657	} else if (resp_ver >= REG_CAPA_V2_RESP_VER) {
1658		reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED;
1659		reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED;
1660		reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED;
1661		reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED;
1662	} else {
1663		reg_capa.allow_40mhz = !(flags & REG_CAPA_V1_40MHZ_FORBIDDEN);
1664		reg_capa.allow_80mhz = flags & REG_CAPA_V1_80MHZ_ALLOWED;
1665		reg_capa.allow_160mhz = flags & REG_CAPA_V1_160MHZ_ALLOWED;
1666		reg_capa.disable_11ax = flags & REG_CAPA_V1_11AX_DISABLED;
1667	}
1668	return reg_capa;
1669}
1670
1671struct ieee80211_regdomain *
1672iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1673		       int num_of_ch, __le32 *channels, u16 fw_mcc,
1674		       u16 geo_info, u32 cap, u8 resp_ver)
1675{
1676	int ch_idx;
1677	u16 ch_flags;
1678	u32 reg_rule_flags, prev_reg_rule_flags = 0;
1679	const u16 *nvm_chan;
1680	struct ieee80211_regdomain *regd, *copy_rd;
1681	struct ieee80211_reg_rule *rule;
1682	enum nl80211_band band;
1683	int center_freq, prev_center_freq = 0;
1684	int valid_rules = 0;
1685	bool new_rule;
1686	int max_num_ch;
1687	struct iwl_reg_capa reg_capa;
1688
1689	if (cfg->uhb_supported) {
1690		max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1691		nvm_chan = iwl_uhb_nvm_channels;
1692	} else if (cfg->nvm_type == IWL_NVM_EXT) {
1693		max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1694		nvm_chan = iwl_ext_nvm_channels;
1695	} else {
1696		max_num_ch = IWL_NVM_NUM_CHANNELS;
1697		nvm_chan = iwl_nvm_channels;
1698	}
1699
1700	if (num_of_ch > max_num_ch) {
1701		IWL_DEBUG_DEV(dev, IWL_DL_LAR,
1702			      "Num of channels (%d) is greater than expected. Truncating to %d\n",
1703			      num_of_ch, max_num_ch);
1704		num_of_ch = max_num_ch;
1705	}
1706
1707	if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1708		return ERR_PTR(-EINVAL);
1709
1710	IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1711		      num_of_ch);
1712
1713	/* build a regdomain rule for every valid channel */
1714	regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1715	if (!regd)
1716		return ERR_PTR(-ENOMEM);
1717
1718	/* set alpha2 from FW. */
1719	regd->alpha2[0] = fw_mcc >> 8;
1720	regd->alpha2[1] = fw_mcc & 0xff;
1721
1722	/* parse regulatory capability flags */
1723	reg_capa = iwl_get_reg_capa(cap, resp_ver);
1724
1725	for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1726		ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1727		band = iwl_nl80211_band_from_channel_idx(ch_idx);
1728		center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1729							     band);
1730		new_rule = false;
1731
1732		if (!(ch_flags & NVM_CHANNEL_VALID)) {
1733			iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1734						    nvm_chan[ch_idx], ch_flags);
1735			continue;
1736		}
1737
1738		reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1739							     ch_flags, reg_capa,
1740							     cfg);
1741
1742		/* we can't continue the same rule */
1743		if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1744		    center_freq - prev_center_freq > 20) {
1745			valid_rules++;
1746			new_rule = true;
1747		}
1748
1749		rule = &regd->reg_rules[valid_rules - 1];
1750
1751		if (new_rule)
1752			rule->freq_range.start_freq_khz =
1753						MHZ_TO_KHZ(center_freq - 10);
1754
1755		rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1756
1757		/* this doesn't matter - not used by FW */
1758		rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1759		rule->power_rule.max_eirp =
1760			DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1761
1762		rule->flags = reg_rule_flags;
1763
1764		/* rely on auto-calculation to merge BW of contiguous chans */
1765		rule->flags |= NL80211_RRF_AUTO_BW;
1766		rule->freq_range.max_bandwidth_khz = 0;
1767
1768		prev_center_freq = center_freq;
1769		prev_reg_rule_flags = reg_rule_flags;
1770
1771		iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1772					    nvm_chan[ch_idx], ch_flags);
1773
1774		if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1775		    band == NL80211_BAND_2GHZ)
1776			continue;
1777
1778		reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1779	}
1780
1781	/*
1782	 * Certain firmware versions might report no valid channels
1783	 * if booted in RF-kill, i.e. not all calibrations etc. are
1784	 * running. We'll get out of this situation later when the
1785	 * rfkill is removed and we update the regdomain again, but
1786	 * since cfg80211 doesn't accept an empty regdomain, add a
1787	 * dummy (unusable) rule here in this case so we can init.
1788	 */
1789	if (!valid_rules) {
1790		valid_rules = 1;
1791		rule = &regd->reg_rules[valid_rules - 1];
1792		rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412);
1793		rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413);
1794		rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1);
1795		rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1796		rule->power_rule.max_eirp =
1797			DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1798	}
1799
1800	regd->n_reg_rules = valid_rules;
1801
1802	/*
1803	 * Narrow down regdom for unused regulatory rules to prevent hole
1804	 * between reg rules to wmm rules.
1805	 */
1806	copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1807			  GFP_KERNEL);
1808	if (!copy_rd)
1809		copy_rd = ERR_PTR(-ENOMEM);
1810
1811	kfree(regd);
1812	return copy_rd;
1813}
1814IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1815
1816#define IWL_MAX_NVM_SECTION_SIZE	0x1b58
1817#define IWL_MAX_EXT_NVM_SECTION_SIZE	0x1ffc
1818#define MAX_NVM_FILE_LEN	16384
1819
1820void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1821		    unsigned int len)
1822{
1823#define IWL_4165_DEVICE_ID	0x5501
1824#define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1825
1826	if (section == NVM_SECTION_TYPE_PHY_SKU &&
1827	    hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1828	    (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1829		/* OTP 0x52 bug work around: it's a 1x1 device */
1830		data[3] = ANT_B | (ANT_B << 4);
1831}
1832IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1833
1834/*
1835 * Reads external NVM from a file into mvm->nvm_sections
1836 *
1837 * HOW TO CREATE THE NVM FILE FORMAT:
1838 * ------------------------------
1839 * 1. create hex file, format:
1840 *      3800 -> header
1841 *      0000 -> header
1842 *      5a40 -> data
1843 *
1844 *   rev - 6 bit (word1)
1845 *   len - 10 bit (word1)
1846 *   id - 4 bit (word2)
1847 *   rsv - 12 bit (word2)
1848 *
1849 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1850 *
1851 * 3. create binary file from the hex file
1852 *
1853 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1854 */
1855int iwl_read_external_nvm(struct iwl_trans *trans,
1856			  const char *nvm_file_name,
1857			  struct iwl_nvm_section *nvm_sections)
1858{
1859	int ret, section_size;
1860	u16 section_id;
1861	const struct firmware *fw_entry;
1862	const struct {
1863		__le16 word1;
1864		__le16 word2;
1865		u8 data[];
1866	} *file_sec;
1867	const u8 *eof;
1868	u8 *temp;
1869	int max_section_size;
1870	const __le32 *dword_buff;
1871
1872#define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1873#define NVM_WORD2_ID(x) (x >> 12)
1874#define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1875#define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1876#define NVM_HEADER_0	(0x2A504C54)
1877#define NVM_HEADER_1	(0x4E564D2A)
1878#define NVM_HEADER_SIZE	(4 * sizeof(u32))
1879
1880	IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1881
1882	/* Maximal size depends on NVM version */
1883	if (trans->cfg->nvm_type != IWL_NVM_EXT)
1884		max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1885	else
1886		max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1887
1888	/*
1889	 * Obtain NVM image via request_firmware. Since we already used
1890	 * request_firmware_nowait() for the firmware binary load and only
1891	 * get here after that we assume the NVM request can be satisfied
1892	 * synchronously.
1893	 */
1894	ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1895	if (ret) {
1896		IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1897			nvm_file_name, ret);
1898		return ret;
1899	}
1900
1901	IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1902		 nvm_file_name, fw_entry->size);
1903
1904	if (fw_entry->size > MAX_NVM_FILE_LEN) {
1905		IWL_ERR(trans, "NVM file too large\n");
1906		ret = -EINVAL;
1907		goto out;
1908	}
1909
1910	eof = fw_entry->data + fw_entry->size;
1911	dword_buff = (const __le32 *)fw_entry->data;
1912
1913	/* some NVM file will contain a header.
1914	 * The header is identified by 2 dwords header as follow:
1915	 * dword[0] = 0x2A504C54
1916	 * dword[1] = 0x4E564D2A
1917	 *
1918	 * This header must be skipped when providing the NVM data to the FW.
1919	 */
1920	if (fw_entry->size > NVM_HEADER_SIZE &&
1921	    dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1922	    dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1923		file_sec = (const void *)(fw_entry->data + NVM_HEADER_SIZE);
1924		IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1925		IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1926			 le32_to_cpu(dword_buff[3]));
1927
1928		/* nvm file validation, dword_buff[2] holds the file version */
1929		if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1930		    trans->hw_rev_step == SILICON_C_STEP &&
1931		    le32_to_cpu(dword_buff[2]) < 0xE4A) {
1932			ret = -EFAULT;
1933			goto out;
1934		}
1935	} else {
1936		file_sec = (const void *)fw_entry->data;
1937	}
1938
1939	while (true) {
1940		if (file_sec->data > eof) {
1941			IWL_ERR(trans,
1942				"ERROR - NVM file too short for section header\n");
1943			ret = -EINVAL;
1944			break;
1945		}
1946
1947		/* check for EOF marker */
1948		if (!file_sec->word1 && !file_sec->word2) {
1949			ret = 0;
1950			break;
1951		}
1952
1953		if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1954			section_size =
1955				2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1956			section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1957		} else {
1958			section_size = 2 * EXT_NVM_WORD2_LEN(
1959						le16_to_cpu(file_sec->word2));
1960			section_id = EXT_NVM_WORD1_ID(
1961						le16_to_cpu(file_sec->word1));
1962		}
1963
1964		if (section_size > max_section_size) {
1965			IWL_ERR(trans, "ERROR - section too large (%d)\n",
1966				section_size);
1967			ret = -EINVAL;
1968			break;
1969		}
1970
1971		if (!section_size) {
1972			IWL_ERR(trans, "ERROR - section empty\n");
1973			ret = -EINVAL;
1974			break;
1975		}
1976
1977		if (file_sec->data + section_size > eof) {
1978			IWL_ERR(trans,
1979				"ERROR - NVM file too short for section (%d bytes)\n",
1980				section_size);
1981			ret = -EINVAL;
1982			break;
1983		}
1984
1985		if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1986			 "Invalid NVM section ID %d\n", section_id)) {
1987			ret = -EINVAL;
1988			break;
1989		}
1990
1991		temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1992		if (!temp) {
1993			ret = -ENOMEM;
1994			break;
1995		}
1996
1997		iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1998
1999		kfree(nvm_sections[section_id].data);
2000		nvm_sections[section_id].data = temp;
2001		nvm_sections[section_id].length = section_size;
2002
2003		/* advance to the next section */
2004		file_sec = (const void *)(file_sec->data + section_size);
2005	}
2006out:
2007	release_firmware(fw_entry);
2008	return ret;
2009}
2010IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
2011
2012struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
2013				 const struct iwl_fw *fw,
2014				 u8 set_tx_ant, u8 set_rx_ant)
2015{
2016	struct iwl_nvm_get_info cmd = {};
2017	struct iwl_nvm_data *nvm;
2018	struct iwl_host_cmd hcmd = {
2019		.flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
2020		.data = { &cmd, },
2021		.len = { sizeof(cmd) },
2022		.id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
2023	};
2024	int  ret;
2025	bool empty_otp;
2026	u32 mac_flags;
2027	u32 sbands_flags = 0;
2028	u8 tx_ant;
2029	u8 rx_ant;
2030
2031	/*
2032	 * All the values in iwl_nvm_get_info_rsp v4 are the same as
2033	 * in v3, except for the channel profile part of the
2034	 * regulatory.  So we can just access the new struct, with the
2035	 * exception of the latter.
2036	 */
2037	struct iwl_nvm_get_info_rsp *rsp;
2038	struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
2039	bool v4 = fw_has_api(&fw->ucode_capa,
2040			     IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
2041	size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
2042	void *channel_profile;
2043
2044	ret = iwl_trans_send_cmd(trans, &hcmd);
2045	if (ret)
2046		return ERR_PTR(ret);
2047
2048	if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
2049		 "Invalid payload len in NVM response from FW %d",
2050		 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
2051		ret = -EINVAL;
2052		goto out;
2053	}
2054
2055	rsp = (void *)hcmd.resp_pkt->data;
2056	empty_otp = !!(le32_to_cpu(rsp->general.flags) &
2057		       NVM_GENERAL_FLAGS_EMPTY_OTP);
2058	if (empty_otp)
2059		IWL_INFO(trans, "OTP is empty\n");
2060
2061	nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
2062	if (!nvm) {
2063		ret = -ENOMEM;
2064		goto out;
2065	}
2066
2067	iwl_set_hw_address_from_csr(trans, nvm);
2068	/* TODO: if platform NVM has MAC address - override it here */
2069
2070	if (!is_valid_ether_addr(nvm->hw_addr)) {
2071		IWL_ERR(trans, "no valid mac address was found\n");
2072		ret = -EINVAL;
2073		goto err_free;
2074	}
2075
2076	IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
2077
2078	/* Initialize general data */
2079	nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
2080	nvm->n_hw_addrs = rsp->general.n_hw_addrs;
2081	if (nvm->n_hw_addrs == 0)
2082		IWL_WARN(trans,
2083			 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
2084			 empty_otp);
2085
2086	/* Initialize MAC sku data */
2087	mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
2088	nvm->sku_cap_11ac_enable =
2089		!!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
2090	nvm->sku_cap_11n_enable =
2091		!!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
2092	nvm->sku_cap_11ax_enable =
2093		!!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
2094	nvm->sku_cap_band_24ghz_enable =
2095		!!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
2096	nvm->sku_cap_band_52ghz_enable =
2097		!!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
2098	nvm->sku_cap_mimo_disabled =
2099		!!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
2100	if (CSR_HW_RFID_TYPE(trans->hw_rf_id) == IWL_CFG_RF_TYPE_FM)
2101		nvm->sku_cap_11be_enable = true;
2102
2103	/* Initialize PHY sku data */
2104	nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
2105	nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
2106
2107	if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
2108	    fw_has_capa(&fw->ucode_capa,
2109			IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
2110		nvm->lar_enabled = true;
2111		sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
2112	}
2113
2114	rsp_v3 = (void *)rsp;
2115	channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
2116			  (void *)rsp_v3->regulatory.channel_profile;
2117
2118	tx_ant = nvm->valid_tx_ant & fw->valid_tx_ant;
2119	rx_ant = nvm->valid_rx_ant & fw->valid_rx_ant;
2120
2121	if (set_tx_ant)
2122		tx_ant &= set_tx_ant;
2123	if (set_rx_ant)
2124		rx_ant &= set_rx_ant;
2125
2126	iwl_init_sbands(trans, nvm, channel_profile, tx_ant, rx_ant,
2127			sbands_flags, v4, fw);
2128
2129	iwl_free_resp(&hcmd);
2130	return nvm;
2131
2132err_free:
2133	kfree(nvm);
2134out:
2135	iwl_free_resp(&hcmd);
2136	return ERR_PTR(ret);
2137}
2138IWL_EXPORT_SYMBOL(iwl_get_nvm);