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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include <linux/pci.h>
5#include <linux/delay.h>
6#include <linux/sched.h>
7
8#include "ixgbe.h"
9#include "ixgbe_phy.h"
10#include "ixgbe_x540.h"
11
12#define IXGBE_X540_MAX_TX_QUEUES 128
13#define IXGBE_X540_MAX_RX_QUEUES 128
14#define IXGBE_X540_RAR_ENTRIES 128
15#define IXGBE_X540_MC_TBL_SIZE 128
16#define IXGBE_X540_VFT_TBL_SIZE 128
17#define IXGBE_X540_RX_PB_SIZE 384
18
19static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
20static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
21static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
22static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
23
24enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
25{
26 return ixgbe_media_type_copper;
27}
28
29s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
30{
31 struct ixgbe_mac_info *mac = &hw->mac;
32 struct ixgbe_phy_info *phy = &hw->phy;
33
34 /* set_phy_power was set by default to NULL */
35 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
36
37 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
38 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
39 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
40 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
41 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
42 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
43 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
44
45 return 0;
46}
47
48/**
49 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
50 * @hw: pointer to hardware structure
51 * @speed: new link speed
52 * @autoneg_wait_to_complete: true when waiting for completion is needed
53 **/
54s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
55 bool autoneg_wait_to_complete)
56{
57 return hw->phy.ops.setup_link_speed(hw, speed,
58 autoneg_wait_to_complete);
59}
60
61/**
62 * ixgbe_reset_hw_X540 - Perform hardware reset
63 * @hw: pointer to hardware structure
64 *
65 * Resets the hardware by resetting the transmit and receive units, masks
66 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
67 * reset.
68 **/
69s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
70{
71 s32 status;
72 u32 ctrl, i;
73 u32 swfw_mask = hw->phy.phy_semaphore_mask;
74
75 /* Call adapter stop to disable tx/rx and clear interrupts */
76 status = hw->mac.ops.stop_adapter(hw);
77 if (status)
78 return status;
79
80 /* flush pending Tx transactions */
81 ixgbe_clear_tx_pending(hw);
82
83mac_reset_top:
84 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
85 if (status) {
86 hw_dbg(hw, "semaphore failed with %d", status);
87 return -EBUSY;
88 }
89
90 ctrl = IXGBE_CTRL_RST;
91 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
92 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
93 IXGBE_WRITE_FLUSH(hw);
94 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
95 usleep_range(1000, 1200);
96
97 /* Poll for reset bit to self-clear indicating reset is complete */
98 for (i = 0; i < 10; i++) {
99 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
100 if (!(ctrl & IXGBE_CTRL_RST_MASK))
101 break;
102 udelay(1);
103 }
104
105 if (ctrl & IXGBE_CTRL_RST_MASK) {
106 status = -EIO;
107 hw_dbg(hw, "Reset polling failed to complete.\n");
108 }
109 msleep(100);
110
111 /*
112 * Double resets are required for recovery from certain error
113 * conditions. Between resets, it is necessary to stall to allow time
114 * for any pending HW events to complete.
115 */
116 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
117 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
118 goto mac_reset_top;
119 }
120
121 /* Set the Rx packet buffer size. */
122 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
123
124 /* Store the permanent mac address */
125 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
126
127 /*
128 * Store MAC address from RAR0, clear receive address registers, and
129 * clear the multicast table. Also reset num_rar_entries to 128,
130 * since we modify this value when programming the SAN MAC address.
131 */
132 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
133 hw->mac.ops.init_rx_addrs(hw);
134
135 /* Store the permanent SAN mac address */
136 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
137
138 /* Add the SAN MAC address to the RAR only if it's a valid address */
139 if (is_valid_ether_addr(hw->mac.san_addr)) {
140 /* Save the SAN MAC RAR index */
141 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
142
143 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
144 hw->mac.san_addr, 0, IXGBE_RAH_AV);
145
146 /* clear VMDq pool/queue selection for this RAR */
147 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
148 IXGBE_CLEAR_VMDQ_ALL);
149
150 /* Reserve the last RAR for the SAN MAC address */
151 hw->mac.num_rar_entries--;
152 }
153
154 /* Store the alternative WWNN/WWPN prefix */
155 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
156 &hw->mac.wwpn_prefix);
157
158 return status;
159}
160
161/**
162 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
163 * @hw: pointer to hardware structure
164 *
165 * Starts the hardware using the generic start_hw function
166 * and the generation start_hw function.
167 * Then performs revision-specific operations, if any.
168 **/
169s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
170{
171 s32 ret_val;
172
173 ret_val = ixgbe_start_hw_generic(hw);
174 if (ret_val)
175 return ret_val;
176
177 return ixgbe_start_hw_gen2(hw);
178}
179
180/**
181 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
182 * @hw: pointer to hardware structure
183 *
184 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
185 * ixgbe_hw struct in order to set up EEPROM access.
186 **/
187s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
188{
189 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
190
191 if (eeprom->type == ixgbe_eeprom_uninitialized) {
192 u16 eeprom_size;
193 u32 eec;
194
195 eeprom->semaphore_delay = 10;
196 eeprom->type = ixgbe_flash;
197
198 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
199 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);
200 eeprom->word_size = BIT(eeprom_size +
201 IXGBE_EEPROM_WORD_SIZE_SHIFT);
202
203 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
204 eeprom->type, eeprom->word_size);
205 }
206
207 return 0;
208}
209
210/**
211 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
212 * @hw: pointer to hardware structure
213 * @offset: offset of word in the EEPROM to read
214 * @data: word read from the EEPROM
215 *
216 * Reads a 16 bit word from the EEPROM using the EERD register.
217 **/
218static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
219{
220 s32 status;
221
222 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
223 return -EBUSY;
224
225 status = ixgbe_read_eerd_generic(hw, offset, data);
226
227 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
228 return status;
229}
230
231/**
232 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
233 * @hw: pointer to hardware structure
234 * @offset: offset of word in the EEPROM to read
235 * @words: number of words
236 * @data: word(s) read from the EEPROM
237 *
238 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
239 **/
240static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
241 u16 offset, u16 words, u16 *data)
242{
243 s32 status;
244
245 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
246 return -EBUSY;
247
248 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
249
250 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
251 return status;
252}
253
254/**
255 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
256 * @hw: pointer to hardware structure
257 * @offset: offset of word in the EEPROM to write
258 * @data: word write to the EEPROM
259 *
260 * Write a 16 bit word to the EEPROM using the EEWR register.
261 **/
262static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
263{
264 s32 status;
265
266 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
267 return -EBUSY;
268
269 status = ixgbe_write_eewr_generic(hw, offset, data);
270
271 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
272 return status;
273}
274
275/**
276 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
277 * @hw: pointer to hardware structure
278 * @offset: offset of word in the EEPROM to write
279 * @words: number of words
280 * @data: word(s) write to the EEPROM
281 *
282 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
283 **/
284static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
285 u16 offset, u16 words, u16 *data)
286{
287 s32 status;
288
289 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
290 return -EBUSY;
291
292 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
293
294 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
295 return status;
296}
297
298/**
299 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
300 *
301 * This function does not use synchronization for EERD and EEWR. It can
302 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
303 *
304 * @hw: pointer to hardware structure
305 **/
306static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
307{
308 u16 i;
309 u16 j;
310 u16 checksum = 0;
311 u16 length = 0;
312 u16 pointer = 0;
313 u16 word = 0;
314 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
315 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
316
317 /*
318 * Do not use hw->eeprom.ops.read because we do not want to take
319 * the synchronization semaphores here. Instead use
320 * ixgbe_read_eerd_generic
321 */
322
323 /* Include 0x0-0x3F in the checksum */
324 for (i = 0; i < checksum_last_word; i++) {
325 if (ixgbe_read_eerd_generic(hw, i, &word)) {
326 hw_dbg(hw, "EEPROM read failed\n");
327 return -EIO;
328 }
329 checksum += word;
330 }
331
332 /*
333 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
334 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
335 */
336 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
337 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
338 continue;
339
340 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
341 hw_dbg(hw, "EEPROM read failed\n");
342 break;
343 }
344
345 /* Skip pointer section if the pointer is invalid. */
346 if (pointer == 0xFFFF || pointer == 0 ||
347 pointer >= hw->eeprom.word_size)
348 continue;
349
350 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
351 hw_dbg(hw, "EEPROM read failed\n");
352 return -EIO;
353 }
354
355 /* Skip pointer section if length is invalid. */
356 if (length == 0xFFFF || length == 0 ||
357 (pointer + length) >= hw->eeprom.word_size)
358 continue;
359
360 for (j = pointer + 1; j <= pointer + length; j++) {
361 if (ixgbe_read_eerd_generic(hw, j, &word)) {
362 hw_dbg(hw, "EEPROM read failed\n");
363 return -EIO;
364 }
365 checksum += word;
366 }
367 }
368
369 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
370
371 return (s32)checksum;
372}
373
374/**
375 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
376 * @hw: pointer to hardware structure
377 * @checksum_val: calculated checksum
378 *
379 * Performs checksum calculation and validates the EEPROM checksum. If the
380 * caller does not need checksum_val, the value can be NULL.
381 **/
382static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
383 u16 *checksum_val)
384{
385 s32 status;
386 u16 checksum;
387 u16 read_checksum = 0;
388
389 /* Read the first word from the EEPROM. If this times out or fails, do
390 * not continue or we could be in for a very long wait while every
391 * EEPROM read fails
392 */
393 status = hw->eeprom.ops.read(hw, 0, &checksum);
394 if (status) {
395 hw_dbg(hw, "EEPROM read failed\n");
396 return status;
397 }
398
399 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
400 return -EBUSY;
401
402 status = hw->eeprom.ops.calc_checksum(hw);
403 if (status < 0)
404 goto out;
405
406 checksum = (u16)(status & 0xffff);
407
408 /* Do not use hw->eeprom.ops.read because we do not want to take
409 * the synchronization semaphores twice here.
410 */
411 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
412 &read_checksum);
413 if (status)
414 goto out;
415
416 /* Verify read checksum from EEPROM is the same as
417 * calculated checksum
418 */
419 if (read_checksum != checksum) {
420 hw_dbg(hw, "Invalid EEPROM checksum");
421 status = -EIO;
422 }
423
424 /* If the user cares, return the calculated checksum */
425 if (checksum_val)
426 *checksum_val = checksum;
427
428out:
429 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
430
431 return status;
432}
433
434/**
435 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
436 * @hw: pointer to hardware structure
437 *
438 * After writing EEPROM to shadow RAM using EEWR register, software calculates
439 * checksum and updates the EEPROM and instructs the hardware to update
440 * the flash.
441 **/
442static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
443{
444 s32 status;
445 u16 checksum;
446
447 /* Read the first word from the EEPROM. If this times out or fails, do
448 * not continue or we could be in for a very long wait while every
449 * EEPROM read fails
450 */
451 status = hw->eeprom.ops.read(hw, 0, &checksum);
452 if (status) {
453 hw_dbg(hw, "EEPROM read failed\n");
454 return status;
455 }
456
457 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
458 return -EBUSY;
459
460 status = hw->eeprom.ops.calc_checksum(hw);
461 if (status < 0)
462 goto out;
463
464 checksum = (u16)(status & 0xffff);
465
466 /* Do not use hw->eeprom.ops.write because we do not want to
467 * take the synchronization semaphores twice here.
468 */
469 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
470 if (status)
471 goto out;
472
473 status = ixgbe_update_flash_X540(hw);
474
475out:
476 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
477 return status;
478}
479
480/**
481 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
482 * @hw: pointer to hardware structure
483 *
484 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
485 * EEPROM from shadow RAM to the flash device.
486 **/
487static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
488{
489 u32 flup;
490 s32 status;
491
492 status = ixgbe_poll_flash_update_done_X540(hw);
493 if (status == -EIO) {
494 hw_dbg(hw, "Flash update time out\n");
495 return status;
496 }
497
498 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
499 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
500
501 status = ixgbe_poll_flash_update_done_X540(hw);
502 if (status == 0)
503 hw_dbg(hw, "Flash update complete\n");
504 else
505 hw_dbg(hw, "Flash update time out\n");
506
507 if (hw->revision_id == 0) {
508 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
509
510 if (flup & IXGBE_EEC_SEC1VAL) {
511 flup |= IXGBE_EEC_FLUP;
512 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
513 }
514
515 status = ixgbe_poll_flash_update_done_X540(hw);
516 if (status == 0)
517 hw_dbg(hw, "Flash update complete\n");
518 else
519 hw_dbg(hw, "Flash update time out\n");
520 }
521
522 return status;
523}
524
525/**
526 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
527 * @hw: pointer to hardware structure
528 *
529 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
530 * flash update is done.
531 **/
532static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
533{
534 u32 i;
535 u32 reg;
536
537 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
538 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
539 if (reg & IXGBE_EEC_FLUDONE)
540 return 0;
541 udelay(5);
542 }
543 return -EIO;
544}
545
546/**
547 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
548 * @hw: pointer to hardware structure
549 * @mask: Mask to specify which semaphore to acquire
550 *
551 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
552 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
553 **/
554s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
555{
556 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
557 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
558 u32 fwmask = swmask << 5;
559 u32 timeout = 200;
560 u32 hwmask = 0;
561 u32 swfw_sync;
562 u32 i;
563
564 if (swmask & IXGBE_GSSR_EEP_SM)
565 hwmask = IXGBE_GSSR_FLASH_SM;
566
567 /* SW only mask does not have FW bit pair */
568 if (mask & IXGBE_GSSR_SW_MNG_SM)
569 swmask |= IXGBE_GSSR_SW_MNG_SM;
570
571 swmask |= swi2c_mask;
572 fwmask |= swi2c_mask << 2;
573 for (i = 0; i < timeout; i++) {
574 /* SW NVM semaphore bit is used for access to all
575 * SW_FW_SYNC bits (not just NVM)
576 */
577 if (ixgbe_get_swfw_sync_semaphore(hw))
578 return -EBUSY;
579
580 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
581 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
582 swfw_sync |= swmask;
583 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
584 ixgbe_release_swfw_sync_semaphore(hw);
585 usleep_range(5000, 6000);
586 return 0;
587 }
588 /* Firmware currently using resource (fwmask), hardware
589 * currently using resource (hwmask), or other software
590 * thread currently using resource (swmask)
591 */
592 ixgbe_release_swfw_sync_semaphore(hw);
593 usleep_range(5000, 10000);
594 }
595
596 /* If the resource is not released by the FW/HW the SW can assume that
597 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
598 * of the requested resource(s) while ignoring the corresponding FW/HW
599 * bits in the SW_FW_SYNC register.
600 */
601 if (ixgbe_get_swfw_sync_semaphore(hw))
602 return -EBUSY;
603 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
604 if (swfw_sync & (fwmask | hwmask)) {
605 swfw_sync |= swmask;
606 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
607 ixgbe_release_swfw_sync_semaphore(hw);
608 usleep_range(5000, 6000);
609 return 0;
610 }
611 /* If the resource is not released by other SW the SW can assume that
612 * the other SW malfunctions. In that case the SW should clear all SW
613 * flags that it does not own and then repeat the whole process once
614 * again.
615 */
616 if (swfw_sync & swmask) {
617 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
618 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
619 IXGBE_GSSR_SW_MNG_SM;
620
621 if (swi2c_mask)
622 rmask |= IXGBE_GSSR_I2C_MASK;
623 ixgbe_release_swfw_sync_X540(hw, rmask);
624 ixgbe_release_swfw_sync_semaphore(hw);
625 return -EBUSY;
626 }
627 ixgbe_release_swfw_sync_semaphore(hw);
628
629 return -EBUSY;
630}
631
632/**
633 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
634 * @hw: pointer to hardware structure
635 * @mask: Mask to specify which semaphore to release
636 *
637 * Releases the SWFW semaphore through the SW_FW_SYNC register
638 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
639 **/
640void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
641{
642 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
643 u32 swfw_sync;
644
645 if (mask & IXGBE_GSSR_I2C_MASK)
646 swmask |= mask & IXGBE_GSSR_I2C_MASK;
647 ixgbe_get_swfw_sync_semaphore(hw);
648
649 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
650 swfw_sync &= ~swmask;
651 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
652
653 ixgbe_release_swfw_sync_semaphore(hw);
654 usleep_range(5000, 6000);
655}
656
657/**
658 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
659 * @hw: pointer to hardware structure
660 *
661 * Sets the hardware semaphores so SW/FW can gain control of shared resources
662 */
663static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
664{
665 u32 timeout = 2000;
666 u32 i;
667 u32 swsm;
668
669 /* Get SMBI software semaphore between device drivers first */
670 for (i = 0; i < timeout; i++) {
671 /* If the SMBI bit is 0 when we read it, then the bit will be
672 * set and we have the semaphore
673 */
674 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
675 if (!(swsm & IXGBE_SWSM_SMBI))
676 break;
677 usleep_range(50, 100);
678 }
679
680 if (i == timeout) {
681 hw_dbg(hw,
682 "Software semaphore SMBI between device drivers not granted.\n");
683 return -EIO;
684 }
685
686 /* Now get the semaphore between SW/FW through the REGSMP bit */
687 for (i = 0; i < timeout; i++) {
688 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
689 if (!(swsm & IXGBE_SWFW_REGSMP))
690 return 0;
691
692 usleep_range(50, 100);
693 }
694
695 /* Release semaphores and return error if SW NVM semaphore
696 * was not granted because we do not have access to the EEPROM
697 */
698 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
699 ixgbe_release_swfw_sync_semaphore(hw);
700 return -EIO;
701}
702
703/**
704 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
705 * @hw: pointer to hardware structure
706 *
707 * This function clears hardware semaphore bits.
708 **/
709static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
710{
711 u32 swsm;
712
713 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
714
715 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
716 swsm &= ~IXGBE_SWFW_REGSMP;
717 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
718
719 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
720 swsm &= ~IXGBE_SWSM_SMBI;
721 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
722
723 IXGBE_WRITE_FLUSH(hw);
724}
725
726/**
727 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
728 * @hw: pointer to hardware structure
729 *
730 * This function reset hardware semaphore bits for a semaphore that may
731 * have be left locked due to a catastrophic failure.
732 **/
733void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
734{
735 u32 rmask;
736
737 /* First try to grab the semaphore but we don't need to bother
738 * looking to see whether we got the lock or not since we do
739 * the same thing regardless of whether we got the lock or not.
740 * We got the lock - we release it.
741 * We timeout trying to get the lock - we force its release.
742 */
743 ixgbe_get_swfw_sync_semaphore(hw);
744 ixgbe_release_swfw_sync_semaphore(hw);
745
746 /* Acquire and release all software resources. */
747 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
748 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
749 IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_I2C_MASK;
750
751 ixgbe_acquire_swfw_sync_X540(hw, rmask);
752 ixgbe_release_swfw_sync_X540(hw, rmask);
753}
754
755/**
756 * ixgbe_blink_led_start_X540 - Blink LED based on index.
757 * @hw: pointer to hardware structure
758 * @index: led number to blink
759 *
760 * Devices that implement the version 2 interface:
761 * X540
762 **/
763s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
764{
765 u32 macc_reg;
766 u32 ledctl_reg;
767 ixgbe_link_speed speed;
768 bool link_up;
769
770 if (index > 3)
771 return -EINVAL;
772
773 /* Link should be up in order for the blink bit in the LED control
774 * register to work. Force link and speed in the MAC if link is down.
775 * This will be reversed when we stop the blinking.
776 */
777 hw->mac.ops.check_link(hw, &speed, &link_up, false);
778 if (!link_up) {
779 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
780 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
781 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
782 }
783 /* Set the LED to LINK_UP + BLINK. */
784 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
785 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
786 ledctl_reg |= IXGBE_LED_BLINK(index);
787 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
788 IXGBE_WRITE_FLUSH(hw);
789
790 return 0;
791}
792
793/**
794 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
795 * @hw: pointer to hardware structure
796 * @index: led number to stop blinking
797 *
798 * Devices that implement the version 2 interface:
799 * X540
800 **/
801s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
802{
803 u32 macc_reg;
804 u32 ledctl_reg;
805
806 if (index > 3)
807 return -EINVAL;
808
809 /* Restore the LED to its default value. */
810 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
811 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
812 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
813 ledctl_reg &= ~IXGBE_LED_BLINK(index);
814 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
815
816 /* Unforce link and speed in the MAC. */
817 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
818 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
819 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
820 IXGBE_WRITE_FLUSH(hw);
821
822 return 0;
823}
824static const struct ixgbe_mac_operations mac_ops_X540 = {
825 .init_hw = &ixgbe_init_hw_generic,
826 .reset_hw = &ixgbe_reset_hw_X540,
827 .start_hw = &ixgbe_start_hw_X540,
828 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
829 .get_media_type = &ixgbe_get_media_type_X540,
830 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
831 .get_mac_addr = &ixgbe_get_mac_addr_generic,
832 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
833 .get_device_caps = &ixgbe_get_device_caps_generic,
834 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
835 .stop_adapter = &ixgbe_stop_adapter_generic,
836 .get_bus_info = &ixgbe_get_bus_info_generic,
837 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
838 .read_analog_reg8 = NULL,
839 .write_analog_reg8 = NULL,
840 .setup_link = &ixgbe_setup_mac_link_X540,
841 .set_rxpba = &ixgbe_set_rxpba_generic,
842 .check_link = &ixgbe_check_mac_link_generic,
843 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
844 .led_on = &ixgbe_led_on_generic,
845 .led_off = &ixgbe_led_off_generic,
846 .init_led_link_act = ixgbe_init_led_link_act_generic,
847 .blink_led_start = &ixgbe_blink_led_start_X540,
848 .blink_led_stop = &ixgbe_blink_led_stop_X540,
849 .set_rar = &ixgbe_set_rar_generic,
850 .clear_rar = &ixgbe_clear_rar_generic,
851 .set_vmdq = &ixgbe_set_vmdq_generic,
852 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
853 .clear_vmdq = &ixgbe_clear_vmdq_generic,
854 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
855 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
856 .enable_mc = &ixgbe_enable_mc_generic,
857 .disable_mc = &ixgbe_disable_mc_generic,
858 .clear_vfta = &ixgbe_clear_vfta_generic,
859 .set_vfta = &ixgbe_set_vfta_generic,
860 .fc_enable = &ixgbe_fc_enable_generic,
861 .setup_fc = ixgbe_setup_fc_generic,
862 .fc_autoneg = ixgbe_fc_autoneg,
863 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
864 .init_uta_tables = &ixgbe_init_uta_tables_generic,
865 .setup_sfp = NULL,
866 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
867 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
868 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
869 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
870 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
871 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
872 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
873 .get_thermal_sensor_data = NULL,
874 .init_thermal_sensor_thresh = NULL,
875 .prot_autoc_read = &prot_autoc_read_generic,
876 .prot_autoc_write = &prot_autoc_write_generic,
877 .enable_rx = &ixgbe_enable_rx_generic,
878 .disable_rx = &ixgbe_disable_rx_generic,
879};
880
881static const struct ixgbe_eeprom_operations eeprom_ops_X540 = {
882 .init_params = &ixgbe_init_eeprom_params_X540,
883 .read = &ixgbe_read_eerd_X540,
884 .read_buffer = &ixgbe_read_eerd_buffer_X540,
885 .write = &ixgbe_write_eewr_X540,
886 .write_buffer = &ixgbe_write_eewr_buffer_X540,
887 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
888 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
889 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
890};
891
892static const struct ixgbe_phy_operations phy_ops_X540 = {
893 .identify = &ixgbe_identify_phy_generic,
894 .identify_sfp = &ixgbe_identify_sfp_module_generic,
895 .init = NULL,
896 .reset = NULL,
897 .read_reg = &ixgbe_read_phy_reg_generic,
898 .write_reg = &ixgbe_write_phy_reg_generic,
899 .setup_link = &ixgbe_setup_phy_link_generic,
900 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
901 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
902 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
903 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
904 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
905 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
906 .check_overtemp = &ixgbe_tn_check_overtemp,
907 .set_phy_power = &ixgbe_set_copper_phy_power,
908};
909
910static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
911 IXGBE_MVALS_INIT(X540)
912};
913
914const struct ixgbe_info ixgbe_X540_info = {
915 .mac = ixgbe_mac_X540,
916 .get_invariants = &ixgbe_get_invariants_X540,
917 .mac_ops = &mac_ops_X540,
918 .eeprom_ops = &eeprom_ops_X540,
919 .phy_ops = &phy_ops_X540,
920 .mbx_ops = &mbx_ops_generic,
921 .mvals = ixgbe_mvals_X540,
922};
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2014 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe.h"
34#include "ixgbe_phy.h"
35#include "ixgbe_x540.h"
36
37#define IXGBE_X540_MAX_TX_QUEUES 128
38#define IXGBE_X540_MAX_RX_QUEUES 128
39#define IXGBE_X540_RAR_ENTRIES 128
40#define IXGBE_X540_MC_TBL_SIZE 128
41#define IXGBE_X540_VFT_TBL_SIZE 128
42#define IXGBE_X540_RX_PB_SIZE 384
43
44static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
45static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
46static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
48
49enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
50{
51 return ixgbe_media_type_copper;
52}
53
54s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
55{
56 struct ixgbe_mac_info *mac = &hw->mac;
57 struct ixgbe_phy_info *phy = &hw->phy;
58
59 /* set_phy_power was set by default to NULL */
60 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
61
62 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
63 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
64 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
65 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
66 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
67 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
68 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
69
70 return 0;
71}
72
73/**
74 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
75 * @hw: pointer to hardware structure
76 * @speed: new link speed
77 * @autoneg_wait_to_complete: true when waiting for completion is needed
78 **/
79s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
80 bool autoneg_wait_to_complete)
81{
82 return hw->phy.ops.setup_link_speed(hw, speed,
83 autoneg_wait_to_complete);
84}
85
86/**
87 * ixgbe_reset_hw_X540 - Perform hardware reset
88 * @hw: pointer to hardware structure
89 *
90 * Resets the hardware by resetting the transmit and receive units, masks
91 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
92 * reset.
93 **/
94s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
95{
96 s32 status;
97 u32 ctrl, i;
98
99 /* Call adapter stop to disable tx/rx and clear interrupts */
100 status = hw->mac.ops.stop_adapter(hw);
101 if (status)
102 return status;
103
104 /* flush pending Tx transactions */
105 ixgbe_clear_tx_pending(hw);
106
107mac_reset_top:
108 ctrl = IXGBE_CTRL_RST;
109 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
110 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
111 IXGBE_WRITE_FLUSH(hw);
112 usleep_range(1000, 1200);
113
114 /* Poll for reset bit to self-clear indicating reset is complete */
115 for (i = 0; i < 10; i++) {
116 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
117 if (!(ctrl & IXGBE_CTRL_RST_MASK))
118 break;
119 udelay(1);
120 }
121
122 if (ctrl & IXGBE_CTRL_RST_MASK) {
123 status = IXGBE_ERR_RESET_FAILED;
124 hw_dbg(hw, "Reset polling failed to complete.\n");
125 }
126 msleep(100);
127
128 /*
129 * Double resets are required for recovery from certain error
130 * conditions. Between resets, it is necessary to stall to allow time
131 * for any pending HW events to complete.
132 */
133 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
134 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
135 goto mac_reset_top;
136 }
137
138 /* Set the Rx packet buffer size. */
139 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
140
141 /* Store the permanent mac address */
142 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
143
144 /*
145 * Store MAC address from RAR0, clear receive address registers, and
146 * clear the multicast table. Also reset num_rar_entries to 128,
147 * since we modify this value when programming the SAN MAC address.
148 */
149 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
150 hw->mac.ops.init_rx_addrs(hw);
151
152 /* Store the permanent SAN mac address */
153 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
154
155 /* Add the SAN MAC address to the RAR only if it's a valid address */
156 if (is_valid_ether_addr(hw->mac.san_addr)) {
157 /* Save the SAN MAC RAR index */
158 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
159
160 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
161 hw->mac.san_addr, 0, IXGBE_RAH_AV);
162
163 /* clear VMDq pool/queue selection for this RAR */
164 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
165 IXGBE_CLEAR_VMDQ_ALL);
166
167 /* Reserve the last RAR for the SAN MAC address */
168 hw->mac.num_rar_entries--;
169 }
170
171 /* Store the alternative WWNN/WWPN prefix */
172 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
173 &hw->mac.wwpn_prefix);
174
175 return status;
176}
177
178/**
179 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
180 * @hw: pointer to hardware structure
181 *
182 * Starts the hardware using the generic start_hw function
183 * and the generation start_hw function.
184 * Then performs revision-specific operations, if any.
185 **/
186s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
187{
188 s32 ret_val;
189
190 ret_val = ixgbe_start_hw_generic(hw);
191 if (ret_val)
192 return ret_val;
193
194 return ixgbe_start_hw_gen2(hw);
195}
196
197/**
198 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
199 * @hw: pointer to hardware structure
200 *
201 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
202 * ixgbe_hw struct in order to set up EEPROM access.
203 **/
204s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
205{
206 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
207 u32 eec;
208 u16 eeprom_size;
209
210 if (eeprom->type == ixgbe_eeprom_uninitialized) {
211 eeprom->semaphore_delay = 10;
212 eeprom->type = ixgbe_flash;
213
214 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
215 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
216 IXGBE_EEC_SIZE_SHIFT);
217 eeprom->word_size = 1 << (eeprom_size +
218 IXGBE_EEPROM_WORD_SIZE_SHIFT);
219
220 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
221 eeprom->type, eeprom->word_size);
222 }
223
224 return 0;
225}
226
227/**
228 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
229 * @hw: pointer to hardware structure
230 * @offset: offset of word in the EEPROM to read
231 * @data: word read from the EEPROM
232 *
233 * Reads a 16 bit word from the EEPROM using the EERD register.
234 **/
235static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
236{
237 s32 status;
238
239 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
240 return IXGBE_ERR_SWFW_SYNC;
241
242 status = ixgbe_read_eerd_generic(hw, offset, data);
243
244 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
245 return status;
246}
247
248/**
249 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
250 * @hw: pointer to hardware structure
251 * @offset: offset of word in the EEPROM to read
252 * @words: number of words
253 * @data: word(s) read from the EEPROM
254 *
255 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
256 **/
257static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
258 u16 offset, u16 words, u16 *data)
259{
260 s32 status;
261
262 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
263 return IXGBE_ERR_SWFW_SYNC;
264
265 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
266
267 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
268 return status;
269}
270
271/**
272 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
273 * @hw: pointer to hardware structure
274 * @offset: offset of word in the EEPROM to write
275 * @data: word write to the EEPROM
276 *
277 * Write a 16 bit word to the EEPROM using the EEWR register.
278 **/
279static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
280{
281 s32 status;
282
283 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
284 return IXGBE_ERR_SWFW_SYNC;
285
286 status = ixgbe_write_eewr_generic(hw, offset, data);
287
288 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
289 return status;
290}
291
292/**
293 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
294 * @hw: pointer to hardware structure
295 * @offset: offset of word in the EEPROM to write
296 * @words: number of words
297 * @data: word(s) write to the EEPROM
298 *
299 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
300 **/
301static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
302 u16 offset, u16 words, u16 *data)
303{
304 s32 status;
305
306 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
307 return IXGBE_ERR_SWFW_SYNC;
308
309 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
310
311 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
312 return status;
313}
314
315/**
316 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
317 *
318 * This function does not use synchronization for EERD and EEWR. It can
319 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
320 *
321 * @hw: pointer to hardware structure
322 **/
323static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
324{
325 u16 i;
326 u16 j;
327 u16 checksum = 0;
328 u16 length = 0;
329 u16 pointer = 0;
330 u16 word = 0;
331 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
332 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
333
334 /*
335 * Do not use hw->eeprom.ops.read because we do not want to take
336 * the synchronization semaphores here. Instead use
337 * ixgbe_read_eerd_generic
338 */
339
340 /* Include 0x0-0x3F in the checksum */
341 for (i = 0; i < checksum_last_word; i++) {
342 if (ixgbe_read_eerd_generic(hw, i, &word)) {
343 hw_dbg(hw, "EEPROM read failed\n");
344 return IXGBE_ERR_EEPROM;
345 }
346 checksum += word;
347 }
348
349 /*
350 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
351 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
352 */
353 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
354 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
355 continue;
356
357 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
358 hw_dbg(hw, "EEPROM read failed\n");
359 break;
360 }
361
362 /* Skip pointer section if the pointer is invalid. */
363 if (pointer == 0xFFFF || pointer == 0 ||
364 pointer >= hw->eeprom.word_size)
365 continue;
366
367 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
368 hw_dbg(hw, "EEPROM read failed\n");
369 return IXGBE_ERR_EEPROM;
370 break;
371 }
372
373 /* Skip pointer section if length is invalid. */
374 if (length == 0xFFFF || length == 0 ||
375 (pointer + length) >= hw->eeprom.word_size)
376 continue;
377
378 for (j = pointer + 1; j <= pointer + length; j++) {
379 if (ixgbe_read_eerd_generic(hw, j, &word)) {
380 hw_dbg(hw, "EEPROM read failed\n");
381 return IXGBE_ERR_EEPROM;
382 }
383 checksum += word;
384 }
385 }
386
387 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
388
389 return (s32)checksum;
390}
391
392/**
393 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
394 * @hw: pointer to hardware structure
395 * @checksum_val: calculated checksum
396 *
397 * Performs checksum calculation and validates the EEPROM checksum. If the
398 * caller does not need checksum_val, the value can be NULL.
399 **/
400static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
401 u16 *checksum_val)
402{
403 s32 status;
404 u16 checksum;
405 u16 read_checksum = 0;
406
407 /* Read the first word from the EEPROM. If this times out or fails, do
408 * not continue or we could be in for a very long wait while every
409 * EEPROM read fails
410 */
411 status = hw->eeprom.ops.read(hw, 0, &checksum);
412 if (status) {
413 hw_dbg(hw, "EEPROM read failed\n");
414 return status;
415 }
416
417 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
418 return IXGBE_ERR_SWFW_SYNC;
419
420 status = hw->eeprom.ops.calc_checksum(hw);
421 if (status < 0)
422 goto out;
423
424 checksum = (u16)(status & 0xffff);
425
426 /* Do not use hw->eeprom.ops.read because we do not want to take
427 * the synchronization semaphores twice here.
428 */
429 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
430 &read_checksum);
431 if (status)
432 goto out;
433
434 /* Verify read checksum from EEPROM is the same as
435 * calculated checksum
436 */
437 if (read_checksum != checksum) {
438 hw_dbg(hw, "Invalid EEPROM checksum");
439 status = IXGBE_ERR_EEPROM_CHECKSUM;
440 }
441
442 /* If the user cares, return the calculated checksum */
443 if (checksum_val)
444 *checksum_val = checksum;
445
446out:
447 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
448
449 return status;
450}
451
452/**
453 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
454 * @hw: pointer to hardware structure
455 *
456 * After writing EEPROM to shadow RAM using EEWR register, software calculates
457 * checksum and updates the EEPROM and instructs the hardware to update
458 * the flash.
459 **/
460static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
461{
462 s32 status;
463 u16 checksum;
464
465 /* Read the first word from the EEPROM. If this times out or fails, do
466 * not continue or we could be in for a very long wait while every
467 * EEPROM read fails
468 */
469 status = hw->eeprom.ops.read(hw, 0, &checksum);
470 if (status) {
471 hw_dbg(hw, "EEPROM read failed\n");
472 return status;
473 }
474
475 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
476 return IXGBE_ERR_SWFW_SYNC;
477
478 status = hw->eeprom.ops.calc_checksum(hw);
479 if (status < 0)
480 goto out;
481
482 checksum = (u16)(status & 0xffff);
483
484 /* Do not use hw->eeprom.ops.write because we do not want to
485 * take the synchronization semaphores twice here.
486 */
487 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
488 if (status)
489 goto out;
490
491 status = ixgbe_update_flash_X540(hw);
492
493out:
494 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
495 return status;
496}
497
498/**
499 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
500 * @hw: pointer to hardware structure
501 *
502 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
503 * EEPROM from shadow RAM to the flash device.
504 **/
505static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
506{
507 u32 flup;
508 s32 status;
509
510 status = ixgbe_poll_flash_update_done_X540(hw);
511 if (status == IXGBE_ERR_EEPROM) {
512 hw_dbg(hw, "Flash update time out\n");
513 return status;
514 }
515
516 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
517 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
518
519 status = ixgbe_poll_flash_update_done_X540(hw);
520 if (status == 0)
521 hw_dbg(hw, "Flash update complete\n");
522 else
523 hw_dbg(hw, "Flash update time out\n");
524
525 if (hw->revision_id == 0) {
526 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
527
528 if (flup & IXGBE_EEC_SEC1VAL) {
529 flup |= IXGBE_EEC_FLUP;
530 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
531 }
532
533 status = ixgbe_poll_flash_update_done_X540(hw);
534 if (status == 0)
535 hw_dbg(hw, "Flash update complete\n");
536 else
537 hw_dbg(hw, "Flash update time out\n");
538 }
539
540 return status;
541}
542
543/**
544 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
545 * @hw: pointer to hardware structure
546 *
547 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
548 * flash update is done.
549 **/
550static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
551{
552 u32 i;
553 u32 reg;
554
555 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
556 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
557 if (reg & IXGBE_EEC_FLUDONE)
558 return 0;
559 udelay(5);
560 }
561 return IXGBE_ERR_EEPROM;
562}
563
564/**
565 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
566 * @hw: pointer to hardware structure
567 * @mask: Mask to specify which semaphore to acquire
568 *
569 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
570 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
571 **/
572s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
573{
574 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
575 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
576 u32 fwmask = swmask << 5;
577 u32 timeout = 200;
578 u32 hwmask = 0;
579 u32 swfw_sync;
580 u32 i;
581
582 if (swmask & IXGBE_GSSR_EEP_SM)
583 hwmask = IXGBE_GSSR_FLASH_SM;
584
585 /* SW only mask does not have FW bit pair */
586 if (mask & IXGBE_GSSR_SW_MNG_SM)
587 swmask |= IXGBE_GSSR_SW_MNG_SM;
588
589 swmask |= swi2c_mask;
590 fwmask |= swi2c_mask << 2;
591 for (i = 0; i < timeout; i++) {
592 /* SW NVM semaphore bit is used for access to all
593 * SW_FW_SYNC bits (not just NVM)
594 */
595 if (ixgbe_get_swfw_sync_semaphore(hw))
596 return IXGBE_ERR_SWFW_SYNC;
597
598 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
599 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
600 swfw_sync |= swmask;
601 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
602 ixgbe_release_swfw_sync_semaphore(hw);
603 usleep_range(5000, 6000);
604 return 0;
605 }
606 /* Firmware currently using resource (fwmask), hardware
607 * currently using resource (hwmask), or other software
608 * thread currently using resource (swmask)
609 */
610 ixgbe_release_swfw_sync_semaphore(hw);
611 usleep_range(5000, 10000);
612 }
613
614 /* Failed to get SW only semaphore */
615 if (swmask == IXGBE_GSSR_SW_MNG_SM) {
616 hw_dbg(hw, "Failed to get SW only semaphore\n");
617 return IXGBE_ERR_SWFW_SYNC;
618 }
619
620 /* If the resource is not released by the FW/HW the SW can assume that
621 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
622 * of the requested resource(s) while ignoring the corresponding FW/HW
623 * bits in the SW_FW_SYNC register.
624 */
625 if (ixgbe_get_swfw_sync_semaphore(hw))
626 return IXGBE_ERR_SWFW_SYNC;
627 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
628 if (swfw_sync & (fwmask | hwmask)) {
629 swfw_sync |= swmask;
630 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
631 ixgbe_release_swfw_sync_semaphore(hw);
632 usleep_range(5000, 6000);
633 return 0;
634 }
635 /* If the resource is not released by other SW the SW can assume that
636 * the other SW malfunctions. In that case the SW should clear all SW
637 * flags that it does not own and then repeat the whole process once
638 * again.
639 */
640 if (swfw_sync & swmask) {
641 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
642 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM;
643
644 if (swi2c_mask)
645 rmask |= IXGBE_GSSR_I2C_MASK;
646 ixgbe_release_swfw_sync_X540(hw, rmask);
647 ixgbe_release_swfw_sync_semaphore(hw);
648 return IXGBE_ERR_SWFW_SYNC;
649 }
650 ixgbe_release_swfw_sync_semaphore(hw);
651
652 return IXGBE_ERR_SWFW_SYNC;
653}
654
655/**
656 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
657 * @hw: pointer to hardware structure
658 * @mask: Mask to specify which semaphore to release
659 *
660 * Releases the SWFW semaphore through the SW_FW_SYNC register
661 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
662 **/
663void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
664{
665 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
666 u32 swfw_sync;
667
668 if (mask & IXGBE_GSSR_I2C_MASK)
669 swmask |= mask & IXGBE_GSSR_I2C_MASK;
670 ixgbe_get_swfw_sync_semaphore(hw);
671
672 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
673 swfw_sync &= ~swmask;
674 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
675
676 ixgbe_release_swfw_sync_semaphore(hw);
677 usleep_range(5000, 6000);
678}
679
680/**
681 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
682 * @hw: pointer to hardware structure
683 *
684 * Sets the hardware semaphores so SW/FW can gain control of shared resources
685 */
686static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
687{
688 u32 timeout = 2000;
689 u32 i;
690 u32 swsm;
691
692 /* Get SMBI software semaphore between device drivers first */
693 for (i = 0; i < timeout; i++) {
694 /* If the SMBI bit is 0 when we read it, then the bit will be
695 * set and we have the semaphore
696 */
697 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
698 if (!(swsm & IXGBE_SWSM_SMBI))
699 break;
700 usleep_range(50, 100);
701 }
702
703 if (i == timeout) {
704 hw_dbg(hw,
705 "Software semaphore SMBI between device drivers not granted.\n");
706 return IXGBE_ERR_EEPROM;
707 }
708
709 /* Now get the semaphore between SW/FW through the REGSMP bit */
710 for (i = 0; i < timeout; i++) {
711 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
712 if (!(swsm & IXGBE_SWFW_REGSMP))
713 return 0;
714
715 usleep_range(50, 100);
716 }
717
718 /* Release semaphores and return error if SW NVM semaphore
719 * was not granted because we do not have access to the EEPROM
720 */
721 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
722 ixgbe_release_swfw_sync_semaphore(hw);
723 return IXGBE_ERR_EEPROM;
724}
725
726/**
727 * ixgbe_release_nvm_semaphore - Release hardware semaphore
728 * @hw: pointer to hardware structure
729 *
730 * This function clears hardware semaphore bits.
731 **/
732static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
733{
734 u32 swsm;
735
736 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
737
738 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
739 swsm &= ~IXGBE_SWFW_REGSMP;
740 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
741
742 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
743 swsm &= ~IXGBE_SWSM_SMBI;
744 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
745
746 IXGBE_WRITE_FLUSH(hw);
747}
748
749/**
750 * ixgbe_blink_led_start_X540 - Blink LED based on index.
751 * @hw: pointer to hardware structure
752 * @index: led number to blink
753 *
754 * Devices that implement the version 2 interface:
755 * X540
756 **/
757s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
758{
759 u32 macc_reg;
760 u32 ledctl_reg;
761 ixgbe_link_speed speed;
762 bool link_up;
763
764 /*
765 * Link should be up in order for the blink bit in the LED control
766 * register to work. Force link and speed in the MAC if link is down.
767 * This will be reversed when we stop the blinking.
768 */
769 hw->mac.ops.check_link(hw, &speed, &link_up, false);
770 if (!link_up) {
771 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
772 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
773 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
774 }
775 /* Set the LED to LINK_UP + BLINK. */
776 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
777 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
778 ledctl_reg |= IXGBE_LED_BLINK(index);
779 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
780 IXGBE_WRITE_FLUSH(hw);
781
782 return 0;
783}
784
785/**
786 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
787 * @hw: pointer to hardware structure
788 * @index: led number to stop blinking
789 *
790 * Devices that implement the version 2 interface:
791 * X540
792 **/
793s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
794{
795 u32 macc_reg;
796 u32 ledctl_reg;
797
798 /* Restore the LED to its default value. */
799 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
800 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
801 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
802 ledctl_reg &= ~IXGBE_LED_BLINK(index);
803 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
804
805 /* Unforce link and speed in the MAC. */
806 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
807 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
808 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
809 IXGBE_WRITE_FLUSH(hw);
810
811 return 0;
812}
813static struct ixgbe_mac_operations mac_ops_X540 = {
814 .init_hw = &ixgbe_init_hw_generic,
815 .reset_hw = &ixgbe_reset_hw_X540,
816 .start_hw = &ixgbe_start_hw_X540,
817 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
818 .get_media_type = &ixgbe_get_media_type_X540,
819 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
820 .get_mac_addr = &ixgbe_get_mac_addr_generic,
821 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
822 .get_device_caps = &ixgbe_get_device_caps_generic,
823 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
824 .stop_adapter = &ixgbe_stop_adapter_generic,
825 .get_bus_info = &ixgbe_get_bus_info_generic,
826 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
827 .read_analog_reg8 = NULL,
828 .write_analog_reg8 = NULL,
829 .setup_link = &ixgbe_setup_mac_link_X540,
830 .set_rxpba = &ixgbe_set_rxpba_generic,
831 .check_link = &ixgbe_check_mac_link_generic,
832 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
833 .led_on = &ixgbe_led_on_generic,
834 .led_off = &ixgbe_led_off_generic,
835 .blink_led_start = &ixgbe_blink_led_start_X540,
836 .blink_led_stop = &ixgbe_blink_led_stop_X540,
837 .set_rar = &ixgbe_set_rar_generic,
838 .clear_rar = &ixgbe_clear_rar_generic,
839 .set_vmdq = &ixgbe_set_vmdq_generic,
840 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
841 .clear_vmdq = &ixgbe_clear_vmdq_generic,
842 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
843 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
844 .enable_mc = &ixgbe_enable_mc_generic,
845 .disable_mc = &ixgbe_disable_mc_generic,
846 .clear_vfta = &ixgbe_clear_vfta_generic,
847 .set_vfta = &ixgbe_set_vfta_generic,
848 .fc_enable = &ixgbe_fc_enable_generic,
849 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
850 .init_uta_tables = &ixgbe_init_uta_tables_generic,
851 .setup_sfp = NULL,
852 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
853 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
854 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
855 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
856 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
857 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
858 .get_thermal_sensor_data = NULL,
859 .init_thermal_sensor_thresh = NULL,
860 .prot_autoc_read = &prot_autoc_read_generic,
861 .prot_autoc_write = &prot_autoc_write_generic,
862 .enable_rx = &ixgbe_enable_rx_generic,
863 .disable_rx = &ixgbe_disable_rx_generic,
864};
865
866static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
867 .init_params = &ixgbe_init_eeprom_params_X540,
868 .read = &ixgbe_read_eerd_X540,
869 .read_buffer = &ixgbe_read_eerd_buffer_X540,
870 .write = &ixgbe_write_eewr_X540,
871 .write_buffer = &ixgbe_write_eewr_buffer_X540,
872 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
873 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
874 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
875};
876
877static struct ixgbe_phy_operations phy_ops_X540 = {
878 .identify = &ixgbe_identify_phy_generic,
879 .identify_sfp = &ixgbe_identify_sfp_module_generic,
880 .init = NULL,
881 .reset = NULL,
882 .read_reg = &ixgbe_read_phy_reg_generic,
883 .write_reg = &ixgbe_write_phy_reg_generic,
884 .setup_link = &ixgbe_setup_phy_link_generic,
885 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
886 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
887 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
888 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
889 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
890 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
891 .check_overtemp = &ixgbe_tn_check_overtemp,
892 .set_phy_power = &ixgbe_set_copper_phy_power,
893 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
894};
895
896static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
897 IXGBE_MVALS_INIT(X540)
898};
899
900struct ixgbe_info ixgbe_X540_info = {
901 .mac = ixgbe_mac_X540,
902 .get_invariants = &ixgbe_get_invariants_X540,
903 .mac_ops = &mac_ops_X540,
904 .eeprom_ops = &eeprom_ops_X540,
905 .phy_ops = &phy_ops_X540,
906 .mbx_ops = &mbx_ops_generic,
907 .mvals = ixgbe_mvals_X540,
908};