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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include <linux/pci.h>
5#include <linux/delay.h>
6#include <linux/sched.h>
7
8#include "ixgbe.h"
9#include "ixgbe_phy.h"
10#include "ixgbe_x540.h"
11
12#define IXGBE_X540_MAX_TX_QUEUES 128
13#define IXGBE_X540_MAX_RX_QUEUES 128
14#define IXGBE_X540_RAR_ENTRIES 128
15#define IXGBE_X540_MC_TBL_SIZE 128
16#define IXGBE_X540_VFT_TBL_SIZE 128
17#define IXGBE_X540_RX_PB_SIZE 384
18
19static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
20static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
21static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
22static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
23
24enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
25{
26 return ixgbe_media_type_copper;
27}
28
29s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
30{
31 struct ixgbe_mac_info *mac = &hw->mac;
32 struct ixgbe_phy_info *phy = &hw->phy;
33
34 /* set_phy_power was set by default to NULL */
35 phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
36
37 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
38 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
39 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
40 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
41 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
42 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
43 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
44
45 return 0;
46}
47
48/**
49 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
50 * @hw: pointer to hardware structure
51 * @speed: new link speed
52 * @autoneg_wait_to_complete: true when waiting for completion is needed
53 **/
54s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
55 bool autoneg_wait_to_complete)
56{
57 return hw->phy.ops.setup_link_speed(hw, speed,
58 autoneg_wait_to_complete);
59}
60
61/**
62 * ixgbe_reset_hw_X540 - Perform hardware reset
63 * @hw: pointer to hardware structure
64 *
65 * Resets the hardware by resetting the transmit and receive units, masks
66 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
67 * reset.
68 **/
69s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
70{
71 s32 status;
72 u32 ctrl, i;
73 u32 swfw_mask = hw->phy.phy_semaphore_mask;
74
75 /* Call adapter stop to disable tx/rx and clear interrupts */
76 status = hw->mac.ops.stop_adapter(hw);
77 if (status)
78 return status;
79
80 /* flush pending Tx transactions */
81 ixgbe_clear_tx_pending(hw);
82
83mac_reset_top:
84 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
85 if (status) {
86 hw_dbg(hw, "semaphore failed with %d", status);
87 return -EBUSY;
88 }
89
90 ctrl = IXGBE_CTRL_RST;
91 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
92 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
93 IXGBE_WRITE_FLUSH(hw);
94 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
95 usleep_range(1000, 1200);
96
97 /* Poll for reset bit to self-clear indicating reset is complete */
98 for (i = 0; i < 10; i++) {
99 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
100 if (!(ctrl & IXGBE_CTRL_RST_MASK))
101 break;
102 udelay(1);
103 }
104
105 if (ctrl & IXGBE_CTRL_RST_MASK) {
106 status = -EIO;
107 hw_dbg(hw, "Reset polling failed to complete.\n");
108 }
109 msleep(100);
110
111 /*
112 * Double resets are required for recovery from certain error
113 * conditions. Between resets, it is necessary to stall to allow time
114 * for any pending HW events to complete.
115 */
116 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
117 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
118 goto mac_reset_top;
119 }
120
121 /* Set the Rx packet buffer size. */
122 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
123
124 /* Store the permanent mac address */
125 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
126
127 /*
128 * Store MAC address from RAR0, clear receive address registers, and
129 * clear the multicast table. Also reset num_rar_entries to 128,
130 * since we modify this value when programming the SAN MAC address.
131 */
132 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
133 hw->mac.ops.init_rx_addrs(hw);
134
135 /* Store the permanent SAN mac address */
136 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
137
138 /* Add the SAN MAC address to the RAR only if it's a valid address */
139 if (is_valid_ether_addr(hw->mac.san_addr)) {
140 /* Save the SAN MAC RAR index */
141 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
142
143 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
144 hw->mac.san_addr, 0, IXGBE_RAH_AV);
145
146 /* clear VMDq pool/queue selection for this RAR */
147 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
148 IXGBE_CLEAR_VMDQ_ALL);
149
150 /* Reserve the last RAR for the SAN MAC address */
151 hw->mac.num_rar_entries--;
152 }
153
154 /* Store the alternative WWNN/WWPN prefix */
155 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
156 &hw->mac.wwpn_prefix);
157
158 return status;
159}
160
161/**
162 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
163 * @hw: pointer to hardware structure
164 *
165 * Starts the hardware using the generic start_hw function
166 * and the generation start_hw function.
167 * Then performs revision-specific operations, if any.
168 **/
169s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
170{
171 s32 ret_val;
172
173 ret_val = ixgbe_start_hw_generic(hw);
174 if (ret_val)
175 return ret_val;
176
177 return ixgbe_start_hw_gen2(hw);
178}
179
180/**
181 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
182 * @hw: pointer to hardware structure
183 *
184 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
185 * ixgbe_hw struct in order to set up EEPROM access.
186 **/
187s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
188{
189 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
190
191 if (eeprom->type == ixgbe_eeprom_uninitialized) {
192 u16 eeprom_size;
193 u32 eec;
194
195 eeprom->semaphore_delay = 10;
196 eeprom->type = ixgbe_flash;
197
198 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
199 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);
200 eeprom->word_size = BIT(eeprom_size +
201 IXGBE_EEPROM_WORD_SIZE_SHIFT);
202
203 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
204 eeprom->type, eeprom->word_size);
205 }
206
207 return 0;
208}
209
210/**
211 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
212 * @hw: pointer to hardware structure
213 * @offset: offset of word in the EEPROM to read
214 * @data: word read from the EEPROM
215 *
216 * Reads a 16 bit word from the EEPROM using the EERD register.
217 **/
218static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
219{
220 s32 status;
221
222 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
223 return -EBUSY;
224
225 status = ixgbe_read_eerd_generic(hw, offset, data);
226
227 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
228 return status;
229}
230
231/**
232 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
233 * @hw: pointer to hardware structure
234 * @offset: offset of word in the EEPROM to read
235 * @words: number of words
236 * @data: word(s) read from the EEPROM
237 *
238 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
239 **/
240static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
241 u16 offset, u16 words, u16 *data)
242{
243 s32 status;
244
245 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
246 return -EBUSY;
247
248 status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
249
250 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
251 return status;
252}
253
254/**
255 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
256 * @hw: pointer to hardware structure
257 * @offset: offset of word in the EEPROM to write
258 * @data: word write to the EEPROM
259 *
260 * Write a 16 bit word to the EEPROM using the EEWR register.
261 **/
262static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
263{
264 s32 status;
265
266 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
267 return -EBUSY;
268
269 status = ixgbe_write_eewr_generic(hw, offset, data);
270
271 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
272 return status;
273}
274
275/**
276 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
277 * @hw: pointer to hardware structure
278 * @offset: offset of word in the EEPROM to write
279 * @words: number of words
280 * @data: word(s) write to the EEPROM
281 *
282 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
283 **/
284static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
285 u16 offset, u16 words, u16 *data)
286{
287 s32 status;
288
289 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
290 return -EBUSY;
291
292 status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
293
294 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
295 return status;
296}
297
298/**
299 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
300 *
301 * This function does not use synchronization for EERD and EEWR. It can
302 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
303 *
304 * @hw: pointer to hardware structure
305 **/
306static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
307{
308 u16 i;
309 u16 j;
310 u16 checksum = 0;
311 u16 length = 0;
312 u16 pointer = 0;
313 u16 word = 0;
314 u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
315 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
316
317 /*
318 * Do not use hw->eeprom.ops.read because we do not want to take
319 * the synchronization semaphores here. Instead use
320 * ixgbe_read_eerd_generic
321 */
322
323 /* Include 0x0-0x3F in the checksum */
324 for (i = 0; i < checksum_last_word; i++) {
325 if (ixgbe_read_eerd_generic(hw, i, &word)) {
326 hw_dbg(hw, "EEPROM read failed\n");
327 return -EIO;
328 }
329 checksum += word;
330 }
331
332 /*
333 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
334 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
335 */
336 for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
337 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
338 continue;
339
340 if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
341 hw_dbg(hw, "EEPROM read failed\n");
342 break;
343 }
344
345 /* Skip pointer section if the pointer is invalid. */
346 if (pointer == 0xFFFF || pointer == 0 ||
347 pointer >= hw->eeprom.word_size)
348 continue;
349
350 if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
351 hw_dbg(hw, "EEPROM read failed\n");
352 return -EIO;
353 }
354
355 /* Skip pointer section if length is invalid. */
356 if (length == 0xFFFF || length == 0 ||
357 (pointer + length) >= hw->eeprom.word_size)
358 continue;
359
360 for (j = pointer + 1; j <= pointer + length; j++) {
361 if (ixgbe_read_eerd_generic(hw, j, &word)) {
362 hw_dbg(hw, "EEPROM read failed\n");
363 return -EIO;
364 }
365 checksum += word;
366 }
367 }
368
369 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
370
371 return (s32)checksum;
372}
373
374/**
375 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
376 * @hw: pointer to hardware structure
377 * @checksum_val: calculated checksum
378 *
379 * Performs checksum calculation and validates the EEPROM checksum. If the
380 * caller does not need checksum_val, the value can be NULL.
381 **/
382static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
383 u16 *checksum_val)
384{
385 s32 status;
386 u16 checksum;
387 u16 read_checksum = 0;
388
389 /* Read the first word from the EEPROM. If this times out or fails, do
390 * not continue or we could be in for a very long wait while every
391 * EEPROM read fails
392 */
393 status = hw->eeprom.ops.read(hw, 0, &checksum);
394 if (status) {
395 hw_dbg(hw, "EEPROM read failed\n");
396 return status;
397 }
398
399 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
400 return -EBUSY;
401
402 status = hw->eeprom.ops.calc_checksum(hw);
403 if (status < 0)
404 goto out;
405
406 checksum = (u16)(status & 0xffff);
407
408 /* Do not use hw->eeprom.ops.read because we do not want to take
409 * the synchronization semaphores twice here.
410 */
411 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
412 &read_checksum);
413 if (status)
414 goto out;
415
416 /* Verify read checksum from EEPROM is the same as
417 * calculated checksum
418 */
419 if (read_checksum != checksum) {
420 hw_dbg(hw, "Invalid EEPROM checksum");
421 status = -EIO;
422 }
423
424 /* If the user cares, return the calculated checksum */
425 if (checksum_val)
426 *checksum_val = checksum;
427
428out:
429 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
430
431 return status;
432}
433
434/**
435 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
436 * @hw: pointer to hardware structure
437 *
438 * After writing EEPROM to shadow RAM using EEWR register, software calculates
439 * checksum and updates the EEPROM and instructs the hardware to update
440 * the flash.
441 **/
442static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
443{
444 s32 status;
445 u16 checksum;
446
447 /* Read the first word from the EEPROM. If this times out or fails, do
448 * not continue or we could be in for a very long wait while every
449 * EEPROM read fails
450 */
451 status = hw->eeprom.ops.read(hw, 0, &checksum);
452 if (status) {
453 hw_dbg(hw, "EEPROM read failed\n");
454 return status;
455 }
456
457 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
458 return -EBUSY;
459
460 status = hw->eeprom.ops.calc_checksum(hw);
461 if (status < 0)
462 goto out;
463
464 checksum = (u16)(status & 0xffff);
465
466 /* Do not use hw->eeprom.ops.write because we do not want to
467 * take the synchronization semaphores twice here.
468 */
469 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
470 if (status)
471 goto out;
472
473 status = ixgbe_update_flash_X540(hw);
474
475out:
476 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
477 return status;
478}
479
480/**
481 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
482 * @hw: pointer to hardware structure
483 *
484 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
485 * EEPROM from shadow RAM to the flash device.
486 **/
487static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
488{
489 u32 flup;
490 s32 status;
491
492 status = ixgbe_poll_flash_update_done_X540(hw);
493 if (status == -EIO) {
494 hw_dbg(hw, "Flash update time out\n");
495 return status;
496 }
497
498 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
499 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
500
501 status = ixgbe_poll_flash_update_done_X540(hw);
502 if (status == 0)
503 hw_dbg(hw, "Flash update complete\n");
504 else
505 hw_dbg(hw, "Flash update time out\n");
506
507 if (hw->revision_id == 0) {
508 flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
509
510 if (flup & IXGBE_EEC_SEC1VAL) {
511 flup |= IXGBE_EEC_FLUP;
512 IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
513 }
514
515 status = ixgbe_poll_flash_update_done_X540(hw);
516 if (status == 0)
517 hw_dbg(hw, "Flash update complete\n");
518 else
519 hw_dbg(hw, "Flash update time out\n");
520 }
521
522 return status;
523}
524
525/**
526 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
527 * @hw: pointer to hardware structure
528 *
529 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
530 * flash update is done.
531 **/
532static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
533{
534 u32 i;
535 u32 reg;
536
537 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
538 reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
539 if (reg & IXGBE_EEC_FLUDONE)
540 return 0;
541 udelay(5);
542 }
543 return -EIO;
544}
545
546/**
547 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
548 * @hw: pointer to hardware structure
549 * @mask: Mask to specify which semaphore to acquire
550 *
551 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
552 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
553 **/
554s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
555{
556 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
557 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
558 u32 fwmask = swmask << 5;
559 u32 timeout = 200;
560 u32 hwmask = 0;
561 u32 swfw_sync;
562 u32 i;
563
564 if (swmask & IXGBE_GSSR_EEP_SM)
565 hwmask = IXGBE_GSSR_FLASH_SM;
566
567 /* SW only mask does not have FW bit pair */
568 if (mask & IXGBE_GSSR_SW_MNG_SM)
569 swmask |= IXGBE_GSSR_SW_MNG_SM;
570
571 swmask |= swi2c_mask;
572 fwmask |= swi2c_mask << 2;
573 for (i = 0; i < timeout; i++) {
574 /* SW NVM semaphore bit is used for access to all
575 * SW_FW_SYNC bits (not just NVM)
576 */
577 if (ixgbe_get_swfw_sync_semaphore(hw))
578 return -EBUSY;
579
580 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
581 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
582 swfw_sync |= swmask;
583 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
584 ixgbe_release_swfw_sync_semaphore(hw);
585 usleep_range(5000, 6000);
586 return 0;
587 }
588 /* Firmware currently using resource (fwmask), hardware
589 * currently using resource (hwmask), or other software
590 * thread currently using resource (swmask)
591 */
592 ixgbe_release_swfw_sync_semaphore(hw);
593 usleep_range(5000, 10000);
594 }
595
596 /* If the resource is not released by the FW/HW the SW can assume that
597 * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
598 * of the requested resource(s) while ignoring the corresponding FW/HW
599 * bits in the SW_FW_SYNC register.
600 */
601 if (ixgbe_get_swfw_sync_semaphore(hw))
602 return -EBUSY;
603 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
604 if (swfw_sync & (fwmask | hwmask)) {
605 swfw_sync |= swmask;
606 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
607 ixgbe_release_swfw_sync_semaphore(hw);
608 usleep_range(5000, 6000);
609 return 0;
610 }
611 /* If the resource is not released by other SW the SW can assume that
612 * the other SW malfunctions. In that case the SW should clear all SW
613 * flags that it does not own and then repeat the whole process once
614 * again.
615 */
616 if (swfw_sync & swmask) {
617 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
618 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
619 IXGBE_GSSR_SW_MNG_SM;
620
621 if (swi2c_mask)
622 rmask |= IXGBE_GSSR_I2C_MASK;
623 ixgbe_release_swfw_sync_X540(hw, rmask);
624 ixgbe_release_swfw_sync_semaphore(hw);
625 return -EBUSY;
626 }
627 ixgbe_release_swfw_sync_semaphore(hw);
628
629 return -EBUSY;
630}
631
632/**
633 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
634 * @hw: pointer to hardware structure
635 * @mask: Mask to specify which semaphore to release
636 *
637 * Releases the SWFW semaphore through the SW_FW_SYNC register
638 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
639 **/
640void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
641{
642 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
643 u32 swfw_sync;
644
645 if (mask & IXGBE_GSSR_I2C_MASK)
646 swmask |= mask & IXGBE_GSSR_I2C_MASK;
647 ixgbe_get_swfw_sync_semaphore(hw);
648
649 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
650 swfw_sync &= ~swmask;
651 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
652
653 ixgbe_release_swfw_sync_semaphore(hw);
654 usleep_range(5000, 6000);
655}
656
657/**
658 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
659 * @hw: pointer to hardware structure
660 *
661 * Sets the hardware semaphores so SW/FW can gain control of shared resources
662 */
663static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
664{
665 u32 timeout = 2000;
666 u32 i;
667 u32 swsm;
668
669 /* Get SMBI software semaphore between device drivers first */
670 for (i = 0; i < timeout; i++) {
671 /* If the SMBI bit is 0 when we read it, then the bit will be
672 * set and we have the semaphore
673 */
674 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
675 if (!(swsm & IXGBE_SWSM_SMBI))
676 break;
677 usleep_range(50, 100);
678 }
679
680 if (i == timeout) {
681 hw_dbg(hw,
682 "Software semaphore SMBI between device drivers not granted.\n");
683 return -EIO;
684 }
685
686 /* Now get the semaphore between SW/FW through the REGSMP bit */
687 for (i = 0; i < timeout; i++) {
688 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
689 if (!(swsm & IXGBE_SWFW_REGSMP))
690 return 0;
691
692 usleep_range(50, 100);
693 }
694
695 /* Release semaphores and return error if SW NVM semaphore
696 * was not granted because we do not have access to the EEPROM
697 */
698 hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
699 ixgbe_release_swfw_sync_semaphore(hw);
700 return -EIO;
701}
702
703/**
704 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
705 * @hw: pointer to hardware structure
706 *
707 * This function clears hardware semaphore bits.
708 **/
709static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
710{
711 u32 swsm;
712
713 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
714
715 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
716 swsm &= ~IXGBE_SWFW_REGSMP;
717 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
718
719 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
720 swsm &= ~IXGBE_SWSM_SMBI;
721 IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
722
723 IXGBE_WRITE_FLUSH(hw);
724}
725
726/**
727 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore
728 * @hw: pointer to hardware structure
729 *
730 * This function reset hardware semaphore bits for a semaphore that may
731 * have be left locked due to a catastrophic failure.
732 **/
733void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
734{
735 u32 rmask;
736
737 /* First try to grab the semaphore but we don't need to bother
738 * looking to see whether we got the lock or not since we do
739 * the same thing regardless of whether we got the lock or not.
740 * We got the lock - we release it.
741 * We timeout trying to get the lock - we force its release.
742 */
743 ixgbe_get_swfw_sync_semaphore(hw);
744 ixgbe_release_swfw_sync_semaphore(hw);
745
746 /* Acquire and release all software resources. */
747 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
748 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
749 IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_I2C_MASK;
750
751 ixgbe_acquire_swfw_sync_X540(hw, rmask);
752 ixgbe_release_swfw_sync_X540(hw, rmask);
753}
754
755/**
756 * ixgbe_blink_led_start_X540 - Blink LED based on index.
757 * @hw: pointer to hardware structure
758 * @index: led number to blink
759 *
760 * Devices that implement the version 2 interface:
761 * X540
762 **/
763s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
764{
765 u32 macc_reg;
766 u32 ledctl_reg;
767 ixgbe_link_speed speed;
768 bool link_up;
769
770 if (index > 3)
771 return -EINVAL;
772
773 /* Link should be up in order for the blink bit in the LED control
774 * register to work. Force link and speed in the MAC if link is down.
775 * This will be reversed when we stop the blinking.
776 */
777 hw->mac.ops.check_link(hw, &speed, &link_up, false);
778 if (!link_up) {
779 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
780 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
781 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
782 }
783 /* Set the LED to LINK_UP + BLINK. */
784 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
785 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
786 ledctl_reg |= IXGBE_LED_BLINK(index);
787 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
788 IXGBE_WRITE_FLUSH(hw);
789
790 return 0;
791}
792
793/**
794 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
795 * @hw: pointer to hardware structure
796 * @index: led number to stop blinking
797 *
798 * Devices that implement the version 2 interface:
799 * X540
800 **/
801s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
802{
803 u32 macc_reg;
804 u32 ledctl_reg;
805
806 if (index > 3)
807 return -EINVAL;
808
809 /* Restore the LED to its default value. */
810 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
811 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
812 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
813 ledctl_reg &= ~IXGBE_LED_BLINK(index);
814 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
815
816 /* Unforce link and speed in the MAC. */
817 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
818 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
819 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
820 IXGBE_WRITE_FLUSH(hw);
821
822 return 0;
823}
824static const struct ixgbe_mac_operations mac_ops_X540 = {
825 .init_hw = &ixgbe_init_hw_generic,
826 .reset_hw = &ixgbe_reset_hw_X540,
827 .start_hw = &ixgbe_start_hw_X540,
828 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
829 .get_media_type = &ixgbe_get_media_type_X540,
830 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
831 .get_mac_addr = &ixgbe_get_mac_addr_generic,
832 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
833 .get_device_caps = &ixgbe_get_device_caps_generic,
834 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
835 .stop_adapter = &ixgbe_stop_adapter_generic,
836 .get_bus_info = &ixgbe_get_bus_info_generic,
837 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
838 .read_analog_reg8 = NULL,
839 .write_analog_reg8 = NULL,
840 .setup_link = &ixgbe_setup_mac_link_X540,
841 .set_rxpba = &ixgbe_set_rxpba_generic,
842 .check_link = &ixgbe_check_mac_link_generic,
843 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
844 .led_on = &ixgbe_led_on_generic,
845 .led_off = &ixgbe_led_off_generic,
846 .init_led_link_act = ixgbe_init_led_link_act_generic,
847 .blink_led_start = &ixgbe_blink_led_start_X540,
848 .blink_led_stop = &ixgbe_blink_led_stop_X540,
849 .set_rar = &ixgbe_set_rar_generic,
850 .clear_rar = &ixgbe_clear_rar_generic,
851 .set_vmdq = &ixgbe_set_vmdq_generic,
852 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic,
853 .clear_vmdq = &ixgbe_clear_vmdq_generic,
854 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
855 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
856 .enable_mc = &ixgbe_enable_mc_generic,
857 .disable_mc = &ixgbe_disable_mc_generic,
858 .clear_vfta = &ixgbe_clear_vfta_generic,
859 .set_vfta = &ixgbe_set_vfta_generic,
860 .fc_enable = &ixgbe_fc_enable_generic,
861 .setup_fc = ixgbe_setup_fc_generic,
862 .fc_autoneg = ixgbe_fc_autoneg,
863 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
864 .init_uta_tables = &ixgbe_init_uta_tables_generic,
865 .setup_sfp = NULL,
866 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
867 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
868 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
869 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
870 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
871 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
872 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
873 .get_thermal_sensor_data = NULL,
874 .init_thermal_sensor_thresh = NULL,
875 .prot_autoc_read = &prot_autoc_read_generic,
876 .prot_autoc_write = &prot_autoc_write_generic,
877 .enable_rx = &ixgbe_enable_rx_generic,
878 .disable_rx = &ixgbe_disable_rx_generic,
879};
880
881static const struct ixgbe_eeprom_operations eeprom_ops_X540 = {
882 .init_params = &ixgbe_init_eeprom_params_X540,
883 .read = &ixgbe_read_eerd_X540,
884 .read_buffer = &ixgbe_read_eerd_buffer_X540,
885 .write = &ixgbe_write_eewr_X540,
886 .write_buffer = &ixgbe_write_eewr_buffer_X540,
887 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
888 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
889 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
890};
891
892static const struct ixgbe_phy_operations phy_ops_X540 = {
893 .identify = &ixgbe_identify_phy_generic,
894 .identify_sfp = &ixgbe_identify_sfp_module_generic,
895 .init = NULL,
896 .reset = NULL,
897 .read_reg = &ixgbe_read_phy_reg_generic,
898 .write_reg = &ixgbe_write_phy_reg_generic,
899 .setup_link = &ixgbe_setup_phy_link_generic,
900 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
901 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
902 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
903 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic,
904 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
905 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
906 .check_overtemp = &ixgbe_tn_check_overtemp,
907 .set_phy_power = &ixgbe_set_copper_phy_power,
908};
909
910static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
911 IXGBE_MVALS_INIT(X540)
912};
913
914const struct ixgbe_info ixgbe_X540_info = {
915 .mac = ixgbe_mac_X540,
916 .get_invariants = &ixgbe_get_invariants_X540,
917 .mac_ops = &mac_ops_X540,
918 .eeprom_ops = &eeprom_ops_X540,
919 .phy_ops = &phy_ops_X540,
920 .mbx_ops = &mbx_ops_generic,
921 .mvals = ixgbe_mvals_X540,
922};
1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
34
35#define IXGBE_X540_MAX_TX_QUEUES 128
36#define IXGBE_X540_MAX_RX_QUEUES 128
37#define IXGBE_X540_RAR_ENTRIES 128
38#define IXGBE_X540_MC_TBL_SIZE 128
39#define IXGBE_X540_VFT_TBL_SIZE 128
40#define IXGBE_X540_RX_PB_SIZE 384
41
42static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
43static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
44static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
45static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
46static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
48
49static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
50{
51 return ixgbe_media_type_copper;
52}
53
54static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
55{
56 struct ixgbe_mac_info *mac = &hw->mac;
57
58 /* Call PHY identify routine to get the phy type */
59 ixgbe_identify_phy_generic(hw);
60
61 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
62 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
63 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
64 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
65 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
66 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
67
68 return 0;
69}
70
71/**
72 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
73 * @hw: pointer to hardware structure
74 * @speed: new link speed
75 * @autoneg: true if autonegotiation enabled
76 * @autoneg_wait_to_complete: true when waiting for completion is needed
77 **/
78static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
79 ixgbe_link_speed speed, bool autoneg,
80 bool autoneg_wait_to_complete)
81{
82 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
83 autoneg_wait_to_complete);
84}
85
86/**
87 * ixgbe_reset_hw_X540 - Perform hardware reset
88 * @hw: pointer to hardware structure
89 *
90 * Resets the hardware by resetting the transmit and receive units, masks
91 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
92 * reset.
93 **/
94static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
95{
96 s32 status;
97 u32 ctrl, i;
98
99 /* Call adapter stop to disable tx/rx and clear interrupts */
100 status = hw->mac.ops.stop_adapter(hw);
101 if (status != 0)
102 goto reset_hw_out;
103
104 /* flush pending Tx transactions */
105 ixgbe_clear_tx_pending(hw);
106
107mac_reset_top:
108 ctrl = IXGBE_CTRL_RST;
109 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
110 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
111 IXGBE_WRITE_FLUSH(hw);
112
113 /* Poll for reset bit to self-clear indicating reset is complete */
114 for (i = 0; i < 10; i++) {
115 udelay(1);
116 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
117 if (!(ctrl & IXGBE_CTRL_RST_MASK))
118 break;
119 }
120
121 if (ctrl & IXGBE_CTRL_RST_MASK) {
122 status = IXGBE_ERR_RESET_FAILED;
123 hw_dbg(hw, "Reset polling failed to complete.\n");
124 }
125 msleep(100);
126
127 /*
128 * Double resets are required for recovery from certain error
129 * conditions. Between resets, it is necessary to stall to allow time
130 * for any pending HW events to complete.
131 */
132 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
133 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
134 goto mac_reset_top;
135 }
136
137 /* Set the Rx packet buffer size. */
138 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
139
140 /* Store the permanent mac address */
141 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
142
143 /*
144 * Store MAC address from RAR0, clear receive address registers, and
145 * clear the multicast table. Also reset num_rar_entries to 128,
146 * since we modify this value when programming the SAN MAC address.
147 */
148 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
149 hw->mac.ops.init_rx_addrs(hw);
150
151 /* Store the permanent SAN mac address */
152 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
153
154 /* Add the SAN MAC address to the RAR only if it's a valid address */
155 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
156 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
157 hw->mac.san_addr, 0, IXGBE_RAH_AV);
158
159 /* Reserve the last RAR for the SAN MAC address */
160 hw->mac.num_rar_entries--;
161 }
162
163 /* Store the alternative WWNN/WWPN prefix */
164 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
165 &hw->mac.wwpn_prefix);
166
167reset_hw_out:
168 return status;
169}
170
171/**
172 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
173 * @hw: pointer to hardware structure
174 *
175 * Starts the hardware using the generic start_hw function
176 * and the generation start_hw function.
177 * Then performs revision-specific operations, if any.
178 **/
179static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
180{
181 s32 ret_val = 0;
182
183 ret_val = ixgbe_start_hw_generic(hw);
184 if (ret_val != 0)
185 goto out;
186
187 ret_val = ixgbe_start_hw_gen2(hw);
188 hw->mac.rx_pb_size = IXGBE_X540_RX_PB_SIZE;
189out:
190 return ret_val;
191}
192
193/**
194 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
195 * @hw: pointer to hardware structure
196 *
197 * Determines physical layer capabilities of the current configuration.
198 **/
199static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
200{
201 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
202 u16 ext_ability = 0;
203
204 hw->phy.ops.identify(hw);
205
206 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
207 &ext_ability);
208 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
209 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
210 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
211 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
212 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
213 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
214
215 return physical_layer;
216}
217
218/**
219 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
220 * @hw: pointer to hardware structure
221 *
222 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
223 * ixgbe_hw struct in order to set up EEPROM access.
224 **/
225static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
226{
227 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
228 u32 eec;
229 u16 eeprom_size;
230
231 if (eeprom->type == ixgbe_eeprom_uninitialized) {
232 eeprom->semaphore_delay = 10;
233 eeprom->type = ixgbe_flash;
234
235 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
236 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
237 IXGBE_EEC_SIZE_SHIFT);
238 eeprom->word_size = 1 << (eeprom_size +
239 IXGBE_EEPROM_WORD_SIZE_SHIFT);
240
241 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
242 eeprom->type, eeprom->word_size);
243 }
244
245 return 0;
246}
247
248/**
249 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
250 * @hw: pointer to hardware structure
251 * @offset: offset of word in the EEPROM to read
252 * @data: word read from the EEPROM
253 *
254 * Reads a 16 bit word from the EEPROM using the EERD register.
255 **/
256static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
257{
258 s32 status = 0;
259
260 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
261 0)
262 status = ixgbe_read_eerd_generic(hw, offset, data);
263 else
264 status = IXGBE_ERR_SWFW_SYNC;
265
266 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
267 return status;
268}
269
270/**
271 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
272 * @hw: pointer to hardware structure
273 * @offset: offset of word in the EEPROM to read
274 * @words: number of words
275 * @data: word(s) read from the EEPROM
276 *
277 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
278 **/
279static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
280 u16 offset, u16 words, u16 *data)
281{
282 s32 status = 0;
283
284 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
285 0)
286 status = ixgbe_read_eerd_buffer_generic(hw, offset,
287 words, data);
288 else
289 status = IXGBE_ERR_SWFW_SYNC;
290
291 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
292 return status;
293}
294
295/**
296 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
297 * @hw: pointer to hardware structure
298 * @offset: offset of word in the EEPROM to write
299 * @data: word write to the EEPROM
300 *
301 * Write a 16 bit word to the EEPROM using the EEWR register.
302 **/
303static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
304{
305 s32 status = 0;
306
307 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0)
308 status = ixgbe_write_eewr_generic(hw, offset, data);
309 else
310 status = IXGBE_ERR_SWFW_SYNC;
311
312 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
313 return status;
314}
315
316/**
317 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
318 * @hw: pointer to hardware structure
319 * @offset: offset of word in the EEPROM to write
320 * @words: number of words
321 * @data: word(s) write to the EEPROM
322 *
323 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
324 **/
325static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
326 u16 offset, u16 words, u16 *data)
327{
328 s32 status = 0;
329
330 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
331 0)
332 status = ixgbe_write_eewr_buffer_generic(hw, offset,
333 words, data);
334 else
335 status = IXGBE_ERR_SWFW_SYNC;
336
337 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
338 return status;
339}
340
341/**
342 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
343 *
344 * This function does not use synchronization for EERD and EEWR. It can
345 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
346 *
347 * @hw: pointer to hardware structure
348 **/
349static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
350{
351 u16 i;
352 u16 j;
353 u16 checksum = 0;
354 u16 length = 0;
355 u16 pointer = 0;
356 u16 word = 0;
357
358 /*
359 * Do not use hw->eeprom.ops.read because we do not want to take
360 * the synchronization semaphores here. Instead use
361 * ixgbe_read_eerd_generic
362 */
363
364 /* Include 0x0-0x3F in the checksum */
365 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
366 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) {
367 hw_dbg(hw, "EEPROM read failed\n");
368 break;
369 }
370 checksum += word;
371 }
372
373 /*
374 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
375 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
376 */
377 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
378 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
379 continue;
380
381 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {
382 hw_dbg(hw, "EEPROM read failed\n");
383 break;
384 }
385
386 /* Skip pointer section if the pointer is invalid. */
387 if (pointer == 0xFFFF || pointer == 0 ||
388 pointer >= hw->eeprom.word_size)
389 continue;
390
391 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) {
392 hw_dbg(hw, "EEPROM read failed\n");
393 break;
394 }
395
396 /* Skip pointer section if length is invalid. */
397 if (length == 0xFFFF || length == 0 ||
398 (pointer + length) >= hw->eeprom.word_size)
399 continue;
400
401 for (j = pointer+1; j <= pointer+length; j++) {
402 if (ixgbe_read_eerd_generic(hw, j, &word) != 0) {
403 hw_dbg(hw, "EEPROM read failed\n");
404 break;
405 }
406 checksum += word;
407 }
408 }
409
410 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
411
412 return checksum;
413}
414
415/**
416 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
417 * @hw: pointer to hardware structure
418 * @checksum_val: calculated checksum
419 *
420 * Performs checksum calculation and validates the EEPROM checksum. If the
421 * caller does not need checksum_val, the value can be NULL.
422 **/
423static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
424 u16 *checksum_val)
425{
426 s32 status;
427 u16 checksum;
428 u16 read_checksum = 0;
429
430 /*
431 * Read the first word from the EEPROM. If this times out or fails, do
432 * not continue or we could be in for a very long wait while every
433 * EEPROM read fails
434 */
435 status = hw->eeprom.ops.read(hw, 0, &checksum);
436
437 if (status != 0) {
438 hw_dbg(hw, "EEPROM read failed\n");
439 goto out;
440 }
441
442 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
443 checksum = hw->eeprom.ops.calc_checksum(hw);
444
445 /*
446 * Do not use hw->eeprom.ops.read because we do not want to take
447 * the synchronization semaphores twice here.
448 */
449 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
450 &read_checksum);
451
452 /*
453 * Verify read checksum from EEPROM is the same as
454 * calculated checksum
455 */
456 if (read_checksum != checksum)
457 status = IXGBE_ERR_EEPROM_CHECKSUM;
458
459 /* If the user cares, return the calculated checksum */
460 if (checksum_val)
461 *checksum_val = checksum;
462 } else {
463 status = IXGBE_ERR_SWFW_SYNC;
464 }
465
466 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
467out:
468 return status;
469}
470
471/**
472 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
473 * @hw: pointer to hardware structure
474 *
475 * After writing EEPROM to shadow RAM using EEWR register, software calculates
476 * checksum and updates the EEPROM and instructs the hardware to update
477 * the flash.
478 **/
479static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
480{
481 s32 status;
482 u16 checksum;
483
484 /*
485 * Read the first word from the EEPROM. If this times out or fails, do
486 * not continue or we could be in for a very long wait while every
487 * EEPROM read fails
488 */
489 status = hw->eeprom.ops.read(hw, 0, &checksum);
490
491 if (status != 0)
492 hw_dbg(hw, "EEPROM read failed\n");
493
494 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
495 checksum = hw->eeprom.ops.calc_checksum(hw);
496
497 /*
498 * Do not use hw->eeprom.ops.write because we do not want to
499 * take the synchronization semaphores twice here.
500 */
501 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
502 checksum);
503
504 if (status == 0)
505 status = ixgbe_update_flash_X540(hw);
506 else
507 status = IXGBE_ERR_SWFW_SYNC;
508 }
509
510 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
511
512 return status;
513}
514
515/**
516 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
517 * @hw: pointer to hardware structure
518 *
519 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
520 * EEPROM from shadow RAM to the flash device.
521 **/
522static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
523{
524 u32 flup;
525 s32 status = IXGBE_ERR_EEPROM;
526
527 status = ixgbe_poll_flash_update_done_X540(hw);
528 if (status == IXGBE_ERR_EEPROM) {
529 hw_dbg(hw, "Flash update time out\n");
530 goto out;
531 }
532
533 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
534 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
535
536 status = ixgbe_poll_flash_update_done_X540(hw);
537 if (status == 0)
538 hw_dbg(hw, "Flash update complete\n");
539 else
540 hw_dbg(hw, "Flash update time out\n");
541
542 if (hw->revision_id == 0) {
543 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
544
545 if (flup & IXGBE_EEC_SEC1VAL) {
546 flup |= IXGBE_EEC_FLUP;
547 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
548 }
549
550 status = ixgbe_poll_flash_update_done_X540(hw);
551 if (status == 0)
552 hw_dbg(hw, "Flash update complete\n");
553 else
554 hw_dbg(hw, "Flash update time out\n");
555 }
556out:
557 return status;
558}
559
560/**
561 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
562 * @hw: pointer to hardware structure
563 *
564 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
565 * flash update is done.
566 **/
567static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
568{
569 u32 i;
570 u32 reg;
571 s32 status = IXGBE_ERR_EEPROM;
572
573 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
574 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
575 if (reg & IXGBE_EEC_FLUDONE) {
576 status = 0;
577 break;
578 }
579 udelay(5);
580 }
581 return status;
582}
583
584/**
585 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
586 * @hw: pointer to hardware structure
587 * @mask: Mask to specify which semaphore to acquire
588 *
589 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
590 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
591 **/
592static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
593{
594 u32 swfw_sync;
595 u32 swmask = mask;
596 u32 fwmask = mask << 5;
597 u32 hwmask = 0;
598 u32 timeout = 200;
599 u32 i;
600
601 if (swmask == IXGBE_GSSR_EEP_SM)
602 hwmask = IXGBE_GSSR_FLASH_SM;
603
604 for (i = 0; i < timeout; i++) {
605 /*
606 * SW NVM semaphore bit is used for access to all
607 * SW_FW_SYNC bits (not just NVM)
608 */
609 if (ixgbe_get_swfw_sync_semaphore(hw))
610 return IXGBE_ERR_SWFW_SYNC;
611
612 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
613 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
614 swfw_sync |= swmask;
615 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
616 ixgbe_release_swfw_sync_semaphore(hw);
617 break;
618 } else {
619 /*
620 * Firmware currently using resource (fwmask),
621 * hardware currently using resource (hwmask),
622 * or other software thread currently using
623 * resource (swmask)
624 */
625 ixgbe_release_swfw_sync_semaphore(hw);
626 usleep_range(5000, 10000);
627 }
628 }
629
630 /*
631 * If the resource is not released by the FW/HW the SW can assume that
632 * the FW/HW malfunctions. In that case the SW should sets the
633 * SW bit(s) of the requested resource(s) while ignoring the
634 * corresponding FW/HW bits in the SW_FW_SYNC register.
635 */
636 if (i >= timeout) {
637 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
638 if (swfw_sync & (fwmask | hwmask)) {
639 if (ixgbe_get_swfw_sync_semaphore(hw))
640 return IXGBE_ERR_SWFW_SYNC;
641
642 swfw_sync |= swmask;
643 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
644 ixgbe_release_swfw_sync_semaphore(hw);
645 }
646 }
647
648 usleep_range(5000, 10000);
649 return 0;
650}
651
652/**
653 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
654 * @hw: pointer to hardware structure
655 * @mask: Mask to specify which semaphore to release
656 *
657 * Releases the SWFW semaphore through the SW_FW_SYNC register
658 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
659 **/
660static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
661{
662 u32 swfw_sync;
663 u32 swmask = mask;
664
665 ixgbe_get_swfw_sync_semaphore(hw);
666
667 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
668 swfw_sync &= ~swmask;
669 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
670
671 ixgbe_release_swfw_sync_semaphore(hw);
672 usleep_range(5000, 10000);
673}
674
675/**
676 * ixgbe_get_nvm_semaphore - Get hardware semaphore
677 * @hw: pointer to hardware structure
678 *
679 * Sets the hardware semaphores so SW/FW can gain control of shared resources
680 **/
681static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
682{
683 s32 status = IXGBE_ERR_EEPROM;
684 u32 timeout = 2000;
685 u32 i;
686 u32 swsm;
687
688 /* Get SMBI software semaphore between device drivers first */
689 for (i = 0; i < timeout; i++) {
690 /*
691 * If the SMBI bit is 0 when we read it, then the bit will be
692 * set and we have the semaphore
693 */
694 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
695 if (!(swsm & IXGBE_SWSM_SMBI)) {
696 status = 0;
697 break;
698 }
699 udelay(50);
700 }
701
702 /* Now get the semaphore between SW/FW through the REGSMP bit */
703 if (status) {
704 for (i = 0; i < timeout; i++) {
705 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
706 if (!(swsm & IXGBE_SWFW_REGSMP))
707 break;
708
709 udelay(50);
710 }
711 } else {
712 hw_dbg(hw, "Software semaphore SMBI between device drivers "
713 "not granted.\n");
714 }
715
716 return status;
717}
718
719/**
720 * ixgbe_release_nvm_semaphore - Release hardware semaphore
721 * @hw: pointer to hardware structure
722 *
723 * This function clears hardware semaphore bits.
724 **/
725static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
726{
727 u32 swsm;
728
729 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
730
731 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
732 swsm &= ~IXGBE_SWSM_SMBI;
733 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
734
735 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
736 swsm &= ~IXGBE_SWFW_REGSMP;
737 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
738
739 IXGBE_WRITE_FLUSH(hw);
740}
741
742/**
743 * ixgbe_blink_led_start_X540 - Blink LED based on index.
744 * @hw: pointer to hardware structure
745 * @index: led number to blink
746 *
747 * Devices that implement the version 2 interface:
748 * X540
749 **/
750static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
751{
752 u32 macc_reg;
753 u32 ledctl_reg;
754 ixgbe_link_speed speed;
755 bool link_up;
756
757 /*
758 * Link should be up in order for the blink bit in the LED control
759 * register to work. Force link and speed in the MAC if link is down.
760 * This will be reversed when we stop the blinking.
761 */
762 hw->mac.ops.check_link(hw, &speed, &link_up, false);
763 if (!link_up) {
764 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
765 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
766 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
767 }
768 /* Set the LED to LINK_UP + BLINK. */
769 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
770 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
771 ledctl_reg |= IXGBE_LED_BLINK(index);
772 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
773 IXGBE_WRITE_FLUSH(hw);
774
775 return 0;
776}
777
778/**
779 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
780 * @hw: pointer to hardware structure
781 * @index: led number to stop blinking
782 *
783 * Devices that implement the version 2 interface:
784 * X540
785 **/
786static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
787{
788 u32 macc_reg;
789 u32 ledctl_reg;
790
791 /* Restore the LED to its default value. */
792 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
793 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
794 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
795 ledctl_reg &= ~IXGBE_LED_BLINK(index);
796 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
797
798 /* Unforce link and speed in the MAC. */
799 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
800 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
801 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
802 IXGBE_WRITE_FLUSH(hw);
803
804 return 0;
805}
806static struct ixgbe_mac_operations mac_ops_X540 = {
807 .init_hw = &ixgbe_init_hw_generic,
808 .reset_hw = &ixgbe_reset_hw_X540,
809 .start_hw = &ixgbe_start_hw_X540,
810 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
811 .get_media_type = &ixgbe_get_media_type_X540,
812 .get_supported_physical_layer =
813 &ixgbe_get_supported_physical_layer_X540,
814 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
815 .get_mac_addr = &ixgbe_get_mac_addr_generic,
816 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
817 .get_device_caps = &ixgbe_get_device_caps_generic,
818 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
819 .stop_adapter = &ixgbe_stop_adapter_generic,
820 .get_bus_info = &ixgbe_get_bus_info_generic,
821 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
822 .read_analog_reg8 = NULL,
823 .write_analog_reg8 = NULL,
824 .setup_link = &ixgbe_setup_mac_link_X540,
825 .set_rxpba = &ixgbe_set_rxpba_generic,
826 .check_link = &ixgbe_check_mac_link_generic,
827 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
828 .led_on = &ixgbe_led_on_generic,
829 .led_off = &ixgbe_led_off_generic,
830 .blink_led_start = &ixgbe_blink_led_start_X540,
831 .blink_led_stop = &ixgbe_blink_led_stop_X540,
832 .set_rar = &ixgbe_set_rar_generic,
833 .clear_rar = &ixgbe_clear_rar_generic,
834 .set_vmdq = &ixgbe_set_vmdq_generic,
835 .clear_vmdq = &ixgbe_clear_vmdq_generic,
836 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
837 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
838 .enable_mc = &ixgbe_enable_mc_generic,
839 .disable_mc = &ixgbe_disable_mc_generic,
840 .clear_vfta = &ixgbe_clear_vfta_generic,
841 .set_vfta = &ixgbe_set_vfta_generic,
842 .fc_enable = &ixgbe_fc_enable_generic,
843 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
844 .init_uta_tables = &ixgbe_init_uta_tables_generic,
845 .setup_sfp = NULL,
846 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
847 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
848 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
849 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
850 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
851 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
852 .get_thermal_sensor_data = NULL,
853 .init_thermal_sensor_thresh = NULL,
854};
855
856static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
857 .init_params = &ixgbe_init_eeprom_params_X540,
858 .read = &ixgbe_read_eerd_X540,
859 .read_buffer = &ixgbe_read_eerd_buffer_X540,
860 .write = &ixgbe_write_eewr_X540,
861 .write_buffer = &ixgbe_write_eewr_buffer_X540,
862 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
863 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
864 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
865};
866
867static struct ixgbe_phy_operations phy_ops_X540 = {
868 .identify = &ixgbe_identify_phy_generic,
869 .identify_sfp = &ixgbe_identify_sfp_module_generic,
870 .init = NULL,
871 .reset = NULL,
872 .read_reg = &ixgbe_read_phy_reg_generic,
873 .write_reg = &ixgbe_write_phy_reg_generic,
874 .setup_link = &ixgbe_setup_phy_link_generic,
875 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
876 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
877 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
878 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
879 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
880 .check_overtemp = &ixgbe_tn_check_overtemp,
881 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
882};
883
884struct ixgbe_info ixgbe_X540_info = {
885 .mac = ixgbe_mac_X540,
886 .get_invariants = &ixgbe_get_invariants_X540,
887 .mac_ops = &mac_ops_X540,
888 .eeprom_ops = &eeprom_ops_X540,
889 .phy_ops = &phy_ops_X540,
890 .mbx_ops = &mbx_ops_generic,
891};