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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12#include <linux/bitops.h>
13#include <linux/errno.h>
14#include <linux/err.h>
15#include <linux/kdebug.h>
16#include <linux/module.h>
17#include <linux/uaccess.h>
18#include <linux/vmalloc.h>
19#include <linux/sched/signal.h>
20#include <linux/fs.h>
21#include <linux/memblock.h>
22#include <linux/pgtable.h>
23
24#include <asm/fpu.h>
25#include <asm/page.h>
26#include <asm/cacheflush.h>
27#include <asm/mmu_context.h>
28#include <asm/pgalloc.h>
29
30#include <linux/kvm_host.h>
31
32#include "interrupt.h"
33
34#define CREATE_TRACE_POINTS
35#include "trace.h"
36
37#ifndef VECTORSPACING
38#define VECTORSPACING 0x100 /* for EI/VI mode */
39#endif
40
41const struct _kvm_stats_desc kvm_vm_stats_desc[] = {
42 KVM_GENERIC_VM_STATS()
43};
44
45const struct kvm_stats_header kvm_vm_stats_header = {
46 .name_size = KVM_STATS_NAME_SIZE,
47 .num_desc = ARRAY_SIZE(kvm_vm_stats_desc),
48 .id_offset = sizeof(struct kvm_stats_header),
49 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
50 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
51 sizeof(kvm_vm_stats_desc),
52};
53
54const struct _kvm_stats_desc kvm_vcpu_stats_desc[] = {
55 KVM_GENERIC_VCPU_STATS(),
56 STATS_DESC_COUNTER(VCPU, wait_exits),
57 STATS_DESC_COUNTER(VCPU, cache_exits),
58 STATS_DESC_COUNTER(VCPU, signal_exits),
59 STATS_DESC_COUNTER(VCPU, int_exits),
60 STATS_DESC_COUNTER(VCPU, cop_unusable_exits),
61 STATS_DESC_COUNTER(VCPU, tlbmod_exits),
62 STATS_DESC_COUNTER(VCPU, tlbmiss_ld_exits),
63 STATS_DESC_COUNTER(VCPU, tlbmiss_st_exits),
64 STATS_DESC_COUNTER(VCPU, addrerr_st_exits),
65 STATS_DESC_COUNTER(VCPU, addrerr_ld_exits),
66 STATS_DESC_COUNTER(VCPU, syscall_exits),
67 STATS_DESC_COUNTER(VCPU, resvd_inst_exits),
68 STATS_DESC_COUNTER(VCPU, break_inst_exits),
69 STATS_DESC_COUNTER(VCPU, trap_inst_exits),
70 STATS_DESC_COUNTER(VCPU, msa_fpe_exits),
71 STATS_DESC_COUNTER(VCPU, fpe_exits),
72 STATS_DESC_COUNTER(VCPU, msa_disabled_exits),
73 STATS_DESC_COUNTER(VCPU, flush_dcache_exits),
74 STATS_DESC_COUNTER(VCPU, vz_gpsi_exits),
75 STATS_DESC_COUNTER(VCPU, vz_gsfc_exits),
76 STATS_DESC_COUNTER(VCPU, vz_hc_exits),
77 STATS_DESC_COUNTER(VCPU, vz_grr_exits),
78 STATS_DESC_COUNTER(VCPU, vz_gva_exits),
79 STATS_DESC_COUNTER(VCPU, vz_ghfc_exits),
80 STATS_DESC_COUNTER(VCPU, vz_gpa_exits),
81 STATS_DESC_COUNTER(VCPU, vz_resvd_exits),
82#ifdef CONFIG_CPU_LOONGSON64
83 STATS_DESC_COUNTER(VCPU, vz_cpucfg_exits),
84#endif
85};
86
87const struct kvm_stats_header kvm_vcpu_stats_header = {
88 .name_size = KVM_STATS_NAME_SIZE,
89 .num_desc = ARRAY_SIZE(kvm_vcpu_stats_desc),
90 .id_offset = sizeof(struct kvm_stats_header),
91 .desc_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE,
92 .data_offset = sizeof(struct kvm_stats_header) + KVM_STATS_NAME_SIZE +
93 sizeof(kvm_vcpu_stats_desc),
94};
95
96bool kvm_trace_guest_mode_change;
97
98int kvm_guest_mode_change_trace_reg(void)
99{
100 kvm_trace_guest_mode_change = true;
101 return 0;
102}
103
104void kvm_guest_mode_change_trace_unreg(void)
105{
106 kvm_trace_guest_mode_change = false;
107}
108
109/*
110 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
111 * Config7, so we are "runnable" if interrupts are pending
112 */
113int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
114{
115 return !!(vcpu->arch.pending_exceptions);
116}
117
118bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
119{
120 return false;
121}
122
123int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
124{
125 return 1;
126}
127
128int kvm_arch_hardware_enable(void)
129{
130 return kvm_mips_callbacks->hardware_enable();
131}
132
133void kvm_arch_hardware_disable(void)
134{
135 kvm_mips_callbacks->hardware_disable();
136}
137
138extern void kvm_init_loongson_ipi(struct kvm *kvm);
139
140int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
141{
142 switch (type) {
143 case KVM_VM_MIPS_AUTO:
144 break;
145 case KVM_VM_MIPS_VZ:
146 break;
147 default:
148 /* Unsupported KVM type */
149 return -EINVAL;
150 }
151
152 /* Allocate page table to map GPA -> RPA */
153 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
154 if (!kvm->arch.gpa_mm.pgd)
155 return -ENOMEM;
156
157#ifdef CONFIG_CPU_LOONGSON64
158 kvm_init_loongson_ipi(kvm);
159#endif
160
161 return 0;
162}
163
164static void kvm_mips_free_gpa_pt(struct kvm *kvm)
165{
166 /* It should always be safe to remove after flushing the whole range */
167 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
168 pgd_free(NULL, kvm->arch.gpa_mm.pgd);
169}
170
171void kvm_arch_destroy_vm(struct kvm *kvm)
172{
173 kvm_destroy_vcpus(kvm);
174 kvm_mips_free_gpa_pt(kvm);
175}
176
177long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
178 unsigned long arg)
179{
180 return -ENOIOCTLCMD;
181}
182
183void kvm_arch_flush_shadow_all(struct kvm *kvm)
184{
185 /* Flush whole GPA */
186 kvm_mips_flush_gpa_pt(kvm, 0, ~0);
187 kvm_flush_remote_tlbs(kvm);
188}
189
190void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
191 struct kvm_memory_slot *slot)
192{
193 /*
194 * The slot has been made invalid (ready for moving or deletion), so we
195 * need to ensure that it can no longer be accessed by any guest VCPUs.
196 */
197
198 spin_lock(&kvm->mmu_lock);
199 /* Flush slot from GPA */
200 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
201 slot->base_gfn + slot->npages - 1);
202 kvm_flush_remote_tlbs_memslot(kvm, slot);
203 spin_unlock(&kvm->mmu_lock);
204}
205
206int kvm_arch_prepare_memory_region(struct kvm *kvm,
207 const struct kvm_memory_slot *old,
208 struct kvm_memory_slot *new,
209 enum kvm_mr_change change)
210{
211 return 0;
212}
213
214void kvm_arch_commit_memory_region(struct kvm *kvm,
215 struct kvm_memory_slot *old,
216 const struct kvm_memory_slot *new,
217 enum kvm_mr_change change)
218{
219 int needs_flush;
220
221 /*
222 * If dirty page logging is enabled, write protect all pages in the slot
223 * ready for dirty logging.
224 *
225 * There is no need to do this in any of the following cases:
226 * CREATE: No dirty mappings will already exist.
227 * MOVE/DELETE: The old mappings will already have been cleaned up by
228 * kvm_arch_flush_shadow_memslot()
229 */
230 if (change == KVM_MR_FLAGS_ONLY &&
231 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
232 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
233 spin_lock(&kvm->mmu_lock);
234 /* Write protect GPA page table entries */
235 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
236 new->base_gfn + new->npages - 1);
237 if (needs_flush)
238 kvm_flush_remote_tlbs_memslot(kvm, new);
239 spin_unlock(&kvm->mmu_lock);
240 }
241}
242
243static inline void dump_handler(const char *symbol, void *start, void *end)
244{
245 u32 *p;
246
247 pr_debug("LEAF(%s)\n", symbol);
248
249 pr_debug("\t.set push\n");
250 pr_debug("\t.set noreorder\n");
251
252 for (p = start; p < (u32 *)end; ++p)
253 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
254
255 pr_debug("\t.set\tpop\n");
256
257 pr_debug("\tEND(%s)\n", symbol);
258}
259
260/* low level hrtimer wake routine */
261static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
262{
263 struct kvm_vcpu *vcpu;
264
265 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
266
267 kvm_mips_callbacks->queue_timer_int(vcpu);
268
269 vcpu->arch.wait = 0;
270 rcuwait_wake_up(&vcpu->wait);
271
272 return kvm_mips_count_timeout(vcpu);
273}
274
275int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
276{
277 return 0;
278}
279
280int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
281{
282 int err, size;
283 void *gebase, *p, *handler, *refill_start, *refill_end;
284 int i;
285
286 kvm_debug("kvm @ %p: create cpu %d at %p\n",
287 vcpu->kvm, vcpu->vcpu_id, vcpu);
288
289 err = kvm_mips_callbacks->vcpu_init(vcpu);
290 if (err)
291 return err;
292
293 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
294 HRTIMER_MODE_REL);
295 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
296
297 /*
298 * Allocate space for host mode exception handlers that handle
299 * guest mode exits
300 */
301 if (cpu_has_veic || cpu_has_vint)
302 size = 0x200 + VECTORSPACING * 64;
303 else
304 size = 0x4000;
305
306 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
307
308 if (!gebase) {
309 err = -ENOMEM;
310 goto out_uninit_vcpu;
311 }
312 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
313 ALIGN(size, PAGE_SIZE), gebase);
314
315 /*
316 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
317 * limits us to the low 512MB of physical address space. If the memory
318 * we allocate is out of range, just give up now.
319 */
320 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
321 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
322 gebase);
323 err = -ENOMEM;
324 goto out_free_gebase;
325 }
326
327 /* Save new ebase */
328 vcpu->arch.guest_ebase = gebase;
329
330 /* Build guest exception vectors dynamically in unmapped memory */
331 handler = gebase + 0x2000;
332
333 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
334 refill_start = gebase;
335 if (IS_ENABLED(CONFIG_64BIT))
336 refill_start += 0x080;
337 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
338
339 /* General Exception Entry point */
340 kvm_mips_build_exception(gebase + 0x180, handler);
341
342 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
343 for (i = 0; i < 8; i++) {
344 kvm_debug("L1 Vectored handler @ %p\n",
345 gebase + 0x200 + (i * VECTORSPACING));
346 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
347 handler);
348 }
349
350 /* General exit handler */
351 p = handler;
352 p = kvm_mips_build_exit(p);
353
354 /* Guest entry routine */
355 vcpu->arch.vcpu_run = p;
356 p = kvm_mips_build_vcpu_run(p);
357
358 /* Dump the generated code */
359 pr_debug("#include <asm/asm.h>\n");
360 pr_debug("#include <asm/regdef.h>\n");
361 pr_debug("\n");
362 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
363 dump_handler("kvm_tlb_refill", refill_start, refill_end);
364 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
365 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
366
367 /* Invalidate the icache for these ranges */
368 flush_icache_range((unsigned long)gebase,
369 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
370
371 /* Init */
372 vcpu->arch.last_sched_cpu = -1;
373 vcpu->arch.last_exec_cpu = -1;
374
375 /* Initial guest state */
376 err = kvm_mips_callbacks->vcpu_setup(vcpu);
377 if (err)
378 goto out_free_gebase;
379
380 return 0;
381
382out_free_gebase:
383 kfree(gebase);
384out_uninit_vcpu:
385 kvm_mips_callbacks->vcpu_uninit(vcpu);
386 return err;
387}
388
389void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
390{
391 hrtimer_cancel(&vcpu->arch.comparecount_timer);
392
393 kvm_mips_dump_stats(vcpu);
394
395 kvm_mmu_free_memory_caches(vcpu);
396 kfree(vcpu->arch.guest_ebase);
397
398 kvm_mips_callbacks->vcpu_uninit(vcpu);
399}
400
401int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
402 struct kvm_guest_debug *dbg)
403{
404 return -ENOIOCTLCMD;
405}
406
407/*
408 * Actually run the vCPU, entering an RCU extended quiescent state (EQS) while
409 * the vCPU is running.
410 *
411 * This must be noinstr as instrumentation may make use of RCU, and this is not
412 * safe during the EQS.
413 */
414static int noinstr kvm_mips_vcpu_enter_exit(struct kvm_vcpu *vcpu)
415{
416 int ret;
417
418 guest_state_enter_irqoff();
419 ret = kvm_mips_callbacks->vcpu_run(vcpu);
420 guest_state_exit_irqoff();
421
422 return ret;
423}
424
425int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
426{
427 int r = -EINTR;
428
429 vcpu_load(vcpu);
430
431 kvm_sigset_activate(vcpu);
432
433 if (vcpu->mmio_needed) {
434 if (!vcpu->mmio_is_write)
435 kvm_mips_complete_mmio_load(vcpu);
436 vcpu->mmio_needed = 0;
437 }
438
439 if (vcpu->run->immediate_exit)
440 goto out;
441
442 lose_fpu(1);
443
444 local_irq_disable();
445 guest_timing_enter_irqoff();
446 trace_kvm_enter(vcpu);
447
448 /*
449 * Make sure the read of VCPU requests in vcpu_run() callback is not
450 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
451 * flush request while the requester sees the VCPU as outside of guest
452 * mode and not needing an IPI.
453 */
454 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
455
456 r = kvm_mips_vcpu_enter_exit(vcpu);
457
458 /*
459 * We must ensure that any pending interrupts are taken before
460 * we exit guest timing so that timer ticks are accounted as
461 * guest time. Transiently unmask interrupts so that any
462 * pending interrupts are taken.
463 *
464 * TODO: is there a barrier which ensures that pending interrupts are
465 * recognised? Currently this just hopes that the CPU takes any pending
466 * interrupts between the enable and disable.
467 */
468 local_irq_enable();
469 local_irq_disable();
470
471 trace_kvm_out(vcpu);
472 guest_timing_exit_irqoff();
473 local_irq_enable();
474
475out:
476 kvm_sigset_deactivate(vcpu);
477
478 vcpu_put(vcpu);
479 return r;
480}
481
482int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
483 struct kvm_mips_interrupt *irq)
484{
485 int intr = (int)irq->irq;
486 struct kvm_vcpu *dvcpu = NULL;
487
488 if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] ||
489 intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] ||
490 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) ||
491 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2]))
492 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
493 (int)intr);
494
495 if (irq->cpu == -1)
496 dvcpu = vcpu;
497 else
498 dvcpu = kvm_get_vcpu(vcpu->kvm, irq->cpu);
499
500 if (intr == 2 || intr == 3 || intr == 4 || intr == 6) {
501 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
502
503 } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) {
504 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
505 } else {
506 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
507 irq->cpu, irq->irq);
508 return -EINVAL;
509 }
510
511 dvcpu->arch.wait = 0;
512
513 rcuwait_wake_up(&dvcpu->wait);
514
515 return 0;
516}
517
518int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
519 struct kvm_mp_state *mp_state)
520{
521 return -ENOIOCTLCMD;
522}
523
524int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
525 struct kvm_mp_state *mp_state)
526{
527 return -ENOIOCTLCMD;
528}
529
530static u64 kvm_mips_get_one_regs[] = {
531 KVM_REG_MIPS_R0,
532 KVM_REG_MIPS_R1,
533 KVM_REG_MIPS_R2,
534 KVM_REG_MIPS_R3,
535 KVM_REG_MIPS_R4,
536 KVM_REG_MIPS_R5,
537 KVM_REG_MIPS_R6,
538 KVM_REG_MIPS_R7,
539 KVM_REG_MIPS_R8,
540 KVM_REG_MIPS_R9,
541 KVM_REG_MIPS_R10,
542 KVM_REG_MIPS_R11,
543 KVM_REG_MIPS_R12,
544 KVM_REG_MIPS_R13,
545 KVM_REG_MIPS_R14,
546 KVM_REG_MIPS_R15,
547 KVM_REG_MIPS_R16,
548 KVM_REG_MIPS_R17,
549 KVM_REG_MIPS_R18,
550 KVM_REG_MIPS_R19,
551 KVM_REG_MIPS_R20,
552 KVM_REG_MIPS_R21,
553 KVM_REG_MIPS_R22,
554 KVM_REG_MIPS_R23,
555 KVM_REG_MIPS_R24,
556 KVM_REG_MIPS_R25,
557 KVM_REG_MIPS_R26,
558 KVM_REG_MIPS_R27,
559 KVM_REG_MIPS_R28,
560 KVM_REG_MIPS_R29,
561 KVM_REG_MIPS_R30,
562 KVM_REG_MIPS_R31,
563
564#ifndef CONFIG_CPU_MIPSR6
565 KVM_REG_MIPS_HI,
566 KVM_REG_MIPS_LO,
567#endif
568 KVM_REG_MIPS_PC,
569};
570
571static u64 kvm_mips_get_one_regs_fpu[] = {
572 KVM_REG_MIPS_FCR_IR,
573 KVM_REG_MIPS_FCR_CSR,
574};
575
576static u64 kvm_mips_get_one_regs_msa[] = {
577 KVM_REG_MIPS_MSA_IR,
578 KVM_REG_MIPS_MSA_CSR,
579};
580
581static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
582{
583 unsigned long ret;
584
585 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
586 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
587 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
588 /* odd doubles */
589 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
590 ret += 16;
591 }
592 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
593 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
594 ret += kvm_mips_callbacks->num_regs(vcpu);
595
596 return ret;
597}
598
599static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
600{
601 u64 index;
602 unsigned int i;
603
604 if (copy_to_user(indices, kvm_mips_get_one_regs,
605 sizeof(kvm_mips_get_one_regs)))
606 return -EFAULT;
607 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
608
609 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
610 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
611 sizeof(kvm_mips_get_one_regs_fpu)))
612 return -EFAULT;
613 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
614
615 for (i = 0; i < 32; ++i) {
616 index = KVM_REG_MIPS_FPR_32(i);
617 if (copy_to_user(indices, &index, sizeof(index)))
618 return -EFAULT;
619 ++indices;
620
621 /* skip odd doubles if no F64 */
622 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
623 continue;
624
625 index = KVM_REG_MIPS_FPR_64(i);
626 if (copy_to_user(indices, &index, sizeof(index)))
627 return -EFAULT;
628 ++indices;
629 }
630 }
631
632 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
633 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
634 sizeof(kvm_mips_get_one_regs_msa)))
635 return -EFAULT;
636 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
637
638 for (i = 0; i < 32; ++i) {
639 index = KVM_REG_MIPS_VEC_128(i);
640 if (copy_to_user(indices, &index, sizeof(index)))
641 return -EFAULT;
642 ++indices;
643 }
644 }
645
646 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
647}
648
649static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
650 const struct kvm_one_reg *reg)
651{
652 struct mips_coproc *cop0 = &vcpu->arch.cop0;
653 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
654 int ret;
655 s64 v;
656 s64 vs[2];
657 unsigned int idx;
658
659 switch (reg->id) {
660 /* General purpose registers */
661 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
662 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
663 break;
664#ifndef CONFIG_CPU_MIPSR6
665 case KVM_REG_MIPS_HI:
666 v = (long)vcpu->arch.hi;
667 break;
668 case KVM_REG_MIPS_LO:
669 v = (long)vcpu->arch.lo;
670 break;
671#endif
672 case KVM_REG_MIPS_PC:
673 v = (long)vcpu->arch.pc;
674 break;
675
676 /* Floating point registers */
677 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
678 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
679 return -EINVAL;
680 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
681 /* Odd singles in top of even double when FR=0 */
682 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
683 v = get_fpr32(&fpu->fpr[idx], 0);
684 else
685 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
686 break;
687 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
688 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
689 return -EINVAL;
690 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
691 /* Can't access odd doubles in FR=0 mode */
692 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
693 return -EINVAL;
694 v = get_fpr64(&fpu->fpr[idx], 0);
695 break;
696 case KVM_REG_MIPS_FCR_IR:
697 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
698 return -EINVAL;
699 v = boot_cpu_data.fpu_id;
700 break;
701 case KVM_REG_MIPS_FCR_CSR:
702 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
703 return -EINVAL;
704 v = fpu->fcr31;
705 break;
706
707 /* MIPS SIMD Architecture (MSA) registers */
708 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
709 if (!kvm_mips_guest_has_msa(&vcpu->arch))
710 return -EINVAL;
711 /* Can't access MSA registers in FR=0 mode */
712 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
713 return -EINVAL;
714 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
715#ifdef CONFIG_CPU_LITTLE_ENDIAN
716 /* least significant byte first */
717 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
718 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
719#else
720 /* most significant byte first */
721 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
722 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
723#endif
724 break;
725 case KVM_REG_MIPS_MSA_IR:
726 if (!kvm_mips_guest_has_msa(&vcpu->arch))
727 return -EINVAL;
728 v = boot_cpu_data.msa_id;
729 break;
730 case KVM_REG_MIPS_MSA_CSR:
731 if (!kvm_mips_guest_has_msa(&vcpu->arch))
732 return -EINVAL;
733 v = fpu->msacsr;
734 break;
735
736 /* registers to be handled specially */
737 default:
738 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
739 if (ret)
740 return ret;
741 break;
742 }
743 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
744 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
745
746 return put_user(v, uaddr64);
747 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
748 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
749 u32 v32 = (u32)v;
750
751 return put_user(v32, uaddr32);
752 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
753 void __user *uaddr = (void __user *)(long)reg->addr;
754
755 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
756 } else {
757 return -EINVAL;
758 }
759}
760
761static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
762 const struct kvm_one_reg *reg)
763{
764 struct mips_coproc *cop0 = &vcpu->arch.cop0;
765 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
766 s64 v;
767 s64 vs[2];
768 unsigned int idx;
769
770 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
771 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
772
773 if (get_user(v, uaddr64) != 0)
774 return -EFAULT;
775 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
776 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
777 s32 v32;
778
779 if (get_user(v32, uaddr32) != 0)
780 return -EFAULT;
781 v = (s64)v32;
782 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
783 void __user *uaddr = (void __user *)(long)reg->addr;
784
785 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
786 } else {
787 return -EINVAL;
788 }
789
790 switch (reg->id) {
791 /* General purpose registers */
792 case KVM_REG_MIPS_R0:
793 /* Silently ignore requests to set $0 */
794 break;
795 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
796 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
797 break;
798#ifndef CONFIG_CPU_MIPSR6
799 case KVM_REG_MIPS_HI:
800 vcpu->arch.hi = v;
801 break;
802 case KVM_REG_MIPS_LO:
803 vcpu->arch.lo = v;
804 break;
805#endif
806 case KVM_REG_MIPS_PC:
807 vcpu->arch.pc = v;
808 break;
809
810 /* Floating point registers */
811 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
812 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
813 return -EINVAL;
814 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
815 /* Odd singles in top of even double when FR=0 */
816 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
817 set_fpr32(&fpu->fpr[idx], 0, v);
818 else
819 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
820 break;
821 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
822 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
823 return -EINVAL;
824 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
825 /* Can't access odd doubles in FR=0 mode */
826 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
827 return -EINVAL;
828 set_fpr64(&fpu->fpr[idx], 0, v);
829 break;
830 case KVM_REG_MIPS_FCR_IR:
831 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
832 return -EINVAL;
833 /* Read-only */
834 break;
835 case KVM_REG_MIPS_FCR_CSR:
836 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
837 return -EINVAL;
838 fpu->fcr31 = v;
839 break;
840
841 /* MIPS SIMD Architecture (MSA) registers */
842 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
843 if (!kvm_mips_guest_has_msa(&vcpu->arch))
844 return -EINVAL;
845 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
846#ifdef CONFIG_CPU_LITTLE_ENDIAN
847 /* least significant byte first */
848 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
849 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
850#else
851 /* most significant byte first */
852 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
853 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
854#endif
855 break;
856 case KVM_REG_MIPS_MSA_IR:
857 if (!kvm_mips_guest_has_msa(&vcpu->arch))
858 return -EINVAL;
859 /* Read-only */
860 break;
861 case KVM_REG_MIPS_MSA_CSR:
862 if (!kvm_mips_guest_has_msa(&vcpu->arch))
863 return -EINVAL;
864 fpu->msacsr = v;
865 break;
866
867 /* registers to be handled specially */
868 default:
869 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
870 }
871 return 0;
872}
873
874static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
875 struct kvm_enable_cap *cap)
876{
877 int r = 0;
878
879 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
880 return -EINVAL;
881 if (cap->flags)
882 return -EINVAL;
883 if (cap->args[0])
884 return -EINVAL;
885
886 switch (cap->cap) {
887 case KVM_CAP_MIPS_FPU:
888 vcpu->arch.fpu_enabled = true;
889 break;
890 case KVM_CAP_MIPS_MSA:
891 vcpu->arch.msa_enabled = true;
892 break;
893 default:
894 r = -EINVAL;
895 break;
896 }
897
898 return r;
899}
900
901long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
902 unsigned long arg)
903{
904 struct kvm_vcpu *vcpu = filp->private_data;
905 void __user *argp = (void __user *)arg;
906
907 if (ioctl == KVM_INTERRUPT) {
908 struct kvm_mips_interrupt irq;
909
910 if (copy_from_user(&irq, argp, sizeof(irq)))
911 return -EFAULT;
912 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
913 irq.irq);
914
915 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
916 }
917
918 return -ENOIOCTLCMD;
919}
920
921long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
922 unsigned long arg)
923{
924 struct kvm_vcpu *vcpu = filp->private_data;
925 void __user *argp = (void __user *)arg;
926 long r;
927
928 vcpu_load(vcpu);
929
930 switch (ioctl) {
931 case KVM_SET_ONE_REG:
932 case KVM_GET_ONE_REG: {
933 struct kvm_one_reg reg;
934
935 r = -EFAULT;
936 if (copy_from_user(®, argp, sizeof(reg)))
937 break;
938 if (ioctl == KVM_SET_ONE_REG)
939 r = kvm_mips_set_reg(vcpu, ®);
940 else
941 r = kvm_mips_get_reg(vcpu, ®);
942 break;
943 }
944 case KVM_GET_REG_LIST: {
945 struct kvm_reg_list __user *user_list = argp;
946 struct kvm_reg_list reg_list;
947 unsigned n;
948
949 r = -EFAULT;
950 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
951 break;
952 n = reg_list.n;
953 reg_list.n = kvm_mips_num_regs(vcpu);
954 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
955 break;
956 r = -E2BIG;
957 if (n < reg_list.n)
958 break;
959 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
960 break;
961 }
962 case KVM_ENABLE_CAP: {
963 struct kvm_enable_cap cap;
964
965 r = -EFAULT;
966 if (copy_from_user(&cap, argp, sizeof(cap)))
967 break;
968 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
969 break;
970 }
971 default:
972 r = -ENOIOCTLCMD;
973 }
974
975 vcpu_put(vcpu);
976 return r;
977}
978
979void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
980{
981
982}
983
984int kvm_arch_flush_remote_tlbs(struct kvm *kvm)
985{
986 kvm_mips_callbacks->prepare_flush_shadow(kvm);
987 return 1;
988}
989
990int kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
991{
992 int r;
993
994 switch (ioctl) {
995 default:
996 r = -ENOIOCTLCMD;
997 }
998
999 return r;
1000}
1001
1002int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1003 struct kvm_sregs *sregs)
1004{
1005 return -ENOIOCTLCMD;
1006}
1007
1008int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1009 struct kvm_sregs *sregs)
1010{
1011 return -ENOIOCTLCMD;
1012}
1013
1014void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1015{
1016}
1017
1018int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1019{
1020 return -ENOIOCTLCMD;
1021}
1022
1023int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1024{
1025 return -ENOIOCTLCMD;
1026}
1027
1028vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1029{
1030 return VM_FAULT_SIGBUS;
1031}
1032
1033int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1034{
1035 int r;
1036
1037 switch (ext) {
1038 case KVM_CAP_ONE_REG:
1039 case KVM_CAP_ENABLE_CAP:
1040 case KVM_CAP_READONLY_MEM:
1041 case KVM_CAP_SYNC_MMU:
1042 case KVM_CAP_IMMEDIATE_EXIT:
1043 r = 1;
1044 break;
1045 case KVM_CAP_NR_VCPUS:
1046 r = min_t(unsigned int, num_online_cpus(), KVM_MAX_VCPUS);
1047 break;
1048 case KVM_CAP_MAX_VCPUS:
1049 r = KVM_MAX_VCPUS;
1050 break;
1051 case KVM_CAP_MAX_VCPU_ID:
1052 r = KVM_MAX_VCPU_IDS;
1053 break;
1054 case KVM_CAP_MIPS_FPU:
1055 /* We don't handle systems with inconsistent cpu_has_fpu */
1056 r = !!raw_cpu_has_fpu;
1057 break;
1058 case KVM_CAP_MIPS_MSA:
1059 /*
1060 * We don't support MSA vector partitioning yet:
1061 * 1) It would require explicit support which can't be tested
1062 * yet due to lack of support in current hardware.
1063 * 2) It extends the state that would need to be saved/restored
1064 * by e.g. QEMU for migration.
1065 *
1066 * When vector partitioning hardware becomes available, support
1067 * could be added by requiring a flag when enabling
1068 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1069 * to save/restore the appropriate extra state.
1070 */
1071 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1072 break;
1073 default:
1074 r = kvm_mips_callbacks->check_extension(kvm, ext);
1075 break;
1076 }
1077 return r;
1078}
1079
1080int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1081{
1082 return kvm_mips_pending_timer(vcpu) ||
1083 kvm_read_c0_guest_cause(&vcpu->arch.cop0) & C_TI;
1084}
1085
1086int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1087{
1088 int i;
1089 struct mips_coproc *cop0;
1090
1091 if (!vcpu)
1092 return -1;
1093
1094 kvm_debug("VCPU Register Dump:\n");
1095 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1096 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1097
1098 for (i = 0; i < 32; i += 4) {
1099 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1100 vcpu->arch.gprs[i],
1101 vcpu->arch.gprs[i + 1],
1102 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1103 }
1104 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1105 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1106
1107 cop0 = &vcpu->arch.cop0;
1108 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1109 kvm_read_c0_guest_status(cop0),
1110 kvm_read_c0_guest_cause(cop0));
1111
1112 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1113
1114 return 0;
1115}
1116
1117int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1118{
1119 int i;
1120
1121 vcpu_load(vcpu);
1122
1123 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1124 vcpu->arch.gprs[i] = regs->gpr[i];
1125 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1126 vcpu->arch.hi = regs->hi;
1127 vcpu->arch.lo = regs->lo;
1128 vcpu->arch.pc = regs->pc;
1129
1130 vcpu_put(vcpu);
1131 return 0;
1132}
1133
1134int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1135{
1136 int i;
1137
1138 vcpu_load(vcpu);
1139
1140 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1141 regs->gpr[i] = vcpu->arch.gprs[i];
1142
1143 regs->hi = vcpu->arch.hi;
1144 regs->lo = vcpu->arch.lo;
1145 regs->pc = vcpu->arch.pc;
1146
1147 vcpu_put(vcpu);
1148 return 0;
1149}
1150
1151int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1152 struct kvm_translation *tr)
1153{
1154 return 0;
1155}
1156
1157static void kvm_mips_set_c0_status(void)
1158{
1159 u32 status = read_c0_status();
1160
1161 if (cpu_has_dsp)
1162 status |= (ST0_MX);
1163
1164 write_c0_status(status);
1165 ehb();
1166}
1167
1168/*
1169 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1170 */
1171static int __kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1172{
1173 struct kvm_run *run = vcpu->run;
1174 u32 cause = vcpu->arch.host_cp0_cause;
1175 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1176 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1177 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1178 enum emulation_result er = EMULATE_DONE;
1179 u32 inst;
1180 int ret = RESUME_GUEST;
1181
1182 vcpu->mode = OUTSIDE_GUEST_MODE;
1183
1184 /* Set a default exit reason */
1185 run->exit_reason = KVM_EXIT_UNKNOWN;
1186 run->ready_for_interrupt_injection = 1;
1187
1188 /*
1189 * Set the appropriate status bits based on host CPU features,
1190 * before we hit the scheduler
1191 */
1192 kvm_mips_set_c0_status();
1193
1194 local_irq_enable();
1195
1196 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1197 cause, opc, run, vcpu);
1198 trace_kvm_exit(vcpu, exccode);
1199
1200 switch (exccode) {
1201 case EXCCODE_INT:
1202 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1203
1204 ++vcpu->stat.int_exits;
1205
1206 if (need_resched())
1207 cond_resched();
1208
1209 ret = RESUME_GUEST;
1210 break;
1211
1212 case EXCCODE_CPU:
1213 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1214
1215 ++vcpu->stat.cop_unusable_exits;
1216 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1217 /* XXXKYMA: Might need to return to user space */
1218 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1219 ret = RESUME_HOST;
1220 break;
1221
1222 case EXCCODE_MOD:
1223 ++vcpu->stat.tlbmod_exits;
1224 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1225 break;
1226
1227 case EXCCODE_TLBS:
1228 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1229 cause, kvm_read_c0_guest_status(&vcpu->arch.cop0), opc,
1230 badvaddr);
1231
1232 ++vcpu->stat.tlbmiss_st_exits;
1233 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1234 break;
1235
1236 case EXCCODE_TLBL:
1237 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1238 cause, opc, badvaddr);
1239
1240 ++vcpu->stat.tlbmiss_ld_exits;
1241 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1242 break;
1243
1244 case EXCCODE_ADES:
1245 ++vcpu->stat.addrerr_st_exits;
1246 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1247 break;
1248
1249 case EXCCODE_ADEL:
1250 ++vcpu->stat.addrerr_ld_exits;
1251 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1252 break;
1253
1254 case EXCCODE_SYS:
1255 ++vcpu->stat.syscall_exits;
1256 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1257 break;
1258
1259 case EXCCODE_RI:
1260 ++vcpu->stat.resvd_inst_exits;
1261 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1262 break;
1263
1264 case EXCCODE_BP:
1265 ++vcpu->stat.break_inst_exits;
1266 ret = kvm_mips_callbacks->handle_break(vcpu);
1267 break;
1268
1269 case EXCCODE_TR:
1270 ++vcpu->stat.trap_inst_exits;
1271 ret = kvm_mips_callbacks->handle_trap(vcpu);
1272 break;
1273
1274 case EXCCODE_MSAFPE:
1275 ++vcpu->stat.msa_fpe_exits;
1276 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1277 break;
1278
1279 case EXCCODE_FPE:
1280 ++vcpu->stat.fpe_exits;
1281 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1282 break;
1283
1284 case EXCCODE_MSADIS:
1285 ++vcpu->stat.msa_disabled_exits;
1286 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1287 break;
1288
1289 case EXCCODE_GE:
1290 /* defer exit accounting to handler */
1291 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1292 break;
1293
1294 default:
1295 if (cause & CAUSEF_BD)
1296 opc += 1;
1297 inst = 0;
1298 kvm_get_badinstr(opc, vcpu, &inst);
1299 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1300 exccode, opc, inst, badvaddr,
1301 kvm_read_c0_guest_status(&vcpu->arch.cop0));
1302 kvm_arch_vcpu_dump_regs(vcpu);
1303 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1304 ret = RESUME_HOST;
1305 break;
1306
1307 }
1308
1309 local_irq_disable();
1310
1311 if (ret == RESUME_GUEST)
1312 kvm_vz_acquire_htimer(vcpu);
1313
1314 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1315 kvm_mips_deliver_interrupts(vcpu, cause);
1316
1317 if (!(ret & RESUME_HOST)) {
1318 /* Only check for signals if not already exiting to userspace */
1319 if (signal_pending(current)) {
1320 run->exit_reason = KVM_EXIT_INTR;
1321 ret = (-EINTR << 2) | RESUME_HOST;
1322 ++vcpu->stat.signal_exits;
1323 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1324 }
1325 }
1326
1327 if (ret == RESUME_GUEST) {
1328 trace_kvm_reenter(vcpu);
1329
1330 /*
1331 * Make sure the read of VCPU requests in vcpu_reenter()
1332 * callback is not reordered ahead of the write to vcpu->mode,
1333 * or we could miss a TLB flush request while the requester sees
1334 * the VCPU as outside of guest mode and not needing an IPI.
1335 */
1336 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1337
1338 kvm_mips_callbacks->vcpu_reenter(vcpu);
1339
1340 /*
1341 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1342 * is live), restore FCR31 / MSACSR.
1343 *
1344 * This should be before returning to the guest exception
1345 * vector, as it may well cause an [MSA] FP exception if there
1346 * are pending exception bits unmasked. (see
1347 * kvm_mips_csr_die_notifier() for how that is handled).
1348 */
1349 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1350 read_c0_status() & ST0_CU1)
1351 __kvm_restore_fcsr(&vcpu->arch);
1352
1353 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1354 read_c0_config5() & MIPS_CONF5_MSAEN)
1355 __kvm_restore_msacsr(&vcpu->arch);
1356 }
1357 return ret;
1358}
1359
1360int noinstr kvm_mips_handle_exit(struct kvm_vcpu *vcpu)
1361{
1362 int ret;
1363
1364 guest_state_exit_irqoff();
1365 ret = __kvm_mips_handle_exit(vcpu);
1366 guest_state_enter_irqoff();
1367
1368 return ret;
1369}
1370
1371/* Enable FPU for guest and restore context */
1372void kvm_own_fpu(struct kvm_vcpu *vcpu)
1373{
1374 struct mips_coproc *cop0 = &vcpu->arch.cop0;
1375 unsigned int sr, cfg5;
1376
1377 preempt_disable();
1378
1379 sr = kvm_read_c0_guest_status(cop0);
1380
1381 /*
1382 * If MSA state is already live, it is undefined how it interacts with
1383 * FR=0 FPU state, and we don't want to hit reserved instruction
1384 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1385 * play it safe and save it first.
1386 */
1387 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1388 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1389 kvm_lose_fpu(vcpu);
1390
1391 /*
1392 * Enable FPU for guest
1393 * We set FR and FRE according to guest context
1394 */
1395 change_c0_status(ST0_CU1 | ST0_FR, sr);
1396 if (cpu_has_fre) {
1397 cfg5 = kvm_read_c0_guest_config5(cop0);
1398 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1399 }
1400 enable_fpu_hazard();
1401
1402 /* If guest FPU state not active, restore it now */
1403 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1404 __kvm_restore_fpu(&vcpu->arch);
1405 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1406 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1407 } else {
1408 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1409 }
1410
1411 preempt_enable();
1412}
1413
1414#ifdef CONFIG_CPU_HAS_MSA
1415/* Enable MSA for guest and restore context */
1416void kvm_own_msa(struct kvm_vcpu *vcpu)
1417{
1418 struct mips_coproc *cop0 = &vcpu->arch.cop0;
1419 unsigned int sr, cfg5;
1420
1421 preempt_disable();
1422
1423 /*
1424 * Enable FPU if enabled in guest, since we're restoring FPU context
1425 * anyway. We set FR and FRE according to guest context.
1426 */
1427 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1428 sr = kvm_read_c0_guest_status(cop0);
1429
1430 /*
1431 * If FR=0 FPU state is already live, it is undefined how it
1432 * interacts with MSA state, so play it safe and save it first.
1433 */
1434 if (!(sr & ST0_FR) &&
1435 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1436 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1437 kvm_lose_fpu(vcpu);
1438
1439 change_c0_status(ST0_CU1 | ST0_FR, sr);
1440 if (sr & ST0_CU1 && cpu_has_fre) {
1441 cfg5 = kvm_read_c0_guest_config5(cop0);
1442 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1443 }
1444 }
1445
1446 /* Enable MSA for guest */
1447 set_c0_config5(MIPS_CONF5_MSAEN);
1448 enable_fpu_hazard();
1449
1450 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1451 case KVM_MIPS_AUX_FPU:
1452 /*
1453 * Guest FPU state already loaded, only restore upper MSA state
1454 */
1455 __kvm_restore_msa_upper(&vcpu->arch);
1456 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1457 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1458 break;
1459 case 0:
1460 /* Neither FPU or MSA already active, restore full MSA state */
1461 __kvm_restore_msa(&vcpu->arch);
1462 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1463 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1464 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1465 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1466 KVM_TRACE_AUX_FPU_MSA);
1467 break;
1468 default:
1469 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1470 break;
1471 }
1472
1473 preempt_enable();
1474}
1475#endif
1476
1477/* Drop FPU & MSA without saving it */
1478void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1479{
1480 preempt_disable();
1481 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1482 disable_msa();
1483 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1484 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1485 }
1486 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1487 clear_c0_status(ST0_CU1 | ST0_FR);
1488 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1489 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1490 }
1491 preempt_enable();
1492}
1493
1494/* Save and disable FPU & MSA */
1495void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1496{
1497 /*
1498 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1499 * is disabled in guest context (software), but the register state in
1500 * the hardware may still be in use.
1501 * This is why we explicitly re-enable the hardware before saving.
1502 */
1503
1504 preempt_disable();
1505 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1506 __kvm_save_msa(&vcpu->arch);
1507 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1508
1509 /* Disable MSA & FPU */
1510 disable_msa();
1511 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1512 clear_c0_status(ST0_CU1 | ST0_FR);
1513 disable_fpu_hazard();
1514 }
1515 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1516 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1517 __kvm_save_fpu(&vcpu->arch);
1518 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1519 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1520
1521 /* Disable FPU */
1522 clear_c0_status(ST0_CU1 | ST0_FR);
1523 disable_fpu_hazard();
1524 }
1525 preempt_enable();
1526}
1527
1528/*
1529 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1530 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1531 * exception if cause bits are set in the value being written.
1532 */
1533static int kvm_mips_csr_die_notify(struct notifier_block *self,
1534 unsigned long cmd, void *ptr)
1535{
1536 struct die_args *args = (struct die_args *)ptr;
1537 struct pt_regs *regs = args->regs;
1538 unsigned long pc;
1539
1540 /* Only interested in FPE and MSAFPE */
1541 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1542 return NOTIFY_DONE;
1543
1544 /* Return immediately if guest context isn't active */
1545 if (!(current->flags & PF_VCPU))
1546 return NOTIFY_DONE;
1547
1548 /* Should never get here from user mode */
1549 BUG_ON(user_mode(regs));
1550
1551 pc = instruction_pointer(regs);
1552 switch (cmd) {
1553 case DIE_FP:
1554 /* match 2nd instruction in __kvm_restore_fcsr */
1555 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1556 return NOTIFY_DONE;
1557 break;
1558 case DIE_MSAFP:
1559 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1560 if (!cpu_has_msa ||
1561 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1562 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1563 return NOTIFY_DONE;
1564 break;
1565 }
1566
1567 /* Move PC forward a little and continue executing */
1568 instruction_pointer(regs) += 4;
1569
1570 return NOTIFY_STOP;
1571}
1572
1573static struct notifier_block kvm_mips_csr_die_notifier = {
1574 .notifier_call = kvm_mips_csr_die_notify,
1575};
1576
1577static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = {
1578 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1579 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1580 [MIPS_EXC_INT_IPI_1] = C_IRQ1,
1581 [MIPS_EXC_INT_IPI_2] = C_IRQ2,
1582};
1583
1584static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = {
1585 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1586 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1587 [MIPS_EXC_INT_IO_2] = C_IRQ1,
1588 [MIPS_EXC_INT_IPI_1] = C_IRQ4,
1589};
1590
1591u32 *kvm_priority_to_irq = kvm_default_priority_to_irq;
1592
1593u32 kvm_irq_to_priority(u32 irq)
1594{
1595 int i;
1596
1597 for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) {
1598 if (kvm_priority_to_irq[i] == (1 << (irq + 8)))
1599 return i;
1600 }
1601
1602 return MIPS_EXC_MAX;
1603}
1604
1605static int __init kvm_mips_init(void)
1606{
1607 int ret;
1608
1609 if (cpu_has_mmid) {
1610 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1611 return -EOPNOTSUPP;
1612 }
1613
1614 ret = kvm_mips_entry_setup();
1615 if (ret)
1616 return ret;
1617
1618 ret = kvm_mips_emulation_init();
1619 if (ret)
1620 return ret;
1621
1622
1623 if (boot_cpu_type() == CPU_LOONGSON64)
1624 kvm_priority_to_irq = kvm_loongson3_priority_to_irq;
1625
1626 register_die_notifier(&kvm_mips_csr_die_notifier);
1627
1628 ret = kvm_init(sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1629 if (ret) {
1630 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1631 return ret;
1632 }
1633 return 0;
1634}
1635
1636static void __exit kvm_mips_exit(void)
1637{
1638 kvm_exit();
1639
1640 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1641}
1642
1643module_init(kvm_mips_init);
1644module_exit(kvm_mips_exit);
1645
1646EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12#include <linux/errno.h>
13#include <linux/err.h>
14#include <linux/kdebug.h>
15#include <linux/module.h>
16#include <linux/vmalloc.h>
17#include <linux/fs.h>
18#include <linux/bootmem.h>
19#include <asm/fpu.h>
20#include <asm/page.h>
21#include <asm/cacheflush.h>
22#include <asm/mmu_context.h>
23#include <asm/pgtable.h>
24
25#include <linux/kvm_host.h>
26
27#include "interrupt.h"
28#include "commpage.h"
29
30#define CREATE_TRACE_POINTS
31#include "trace.h"
32
33#ifndef VECTORSPACING
34#define VECTORSPACING 0x100 /* for EI/VI mode */
35#endif
36
37#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
38struct kvm_stats_debugfs_item debugfs_entries[] = {
39 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
40 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
41 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
42 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
43 { "cop_unsuable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
44 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
45 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
46 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
47 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
48 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
49 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
50 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
51 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
52 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
53 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
54 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
55 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
56 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
57 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
58 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
59 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
60 {NULL}
61};
62
63static int kvm_mips_reset_vcpu(struct kvm_vcpu *vcpu)
64{
65 int i;
66
67 for_each_possible_cpu(i) {
68 vcpu->arch.guest_kernel_asid[i] = 0;
69 vcpu->arch.guest_user_asid[i] = 0;
70 }
71
72 return 0;
73}
74
75/*
76 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
77 * Config7, so we are "runnable" if interrupts are pending
78 */
79int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
80{
81 return !!(vcpu->arch.pending_exceptions);
82}
83
84int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
85{
86 return 1;
87}
88
89int kvm_arch_hardware_enable(void)
90{
91 return 0;
92}
93
94int kvm_arch_hardware_setup(void)
95{
96 return 0;
97}
98
99void kvm_arch_check_processor_compat(void *rtn)
100{
101 *(int *)rtn = 0;
102}
103
104static void kvm_mips_init_tlbs(struct kvm *kvm)
105{
106 unsigned long wired;
107
108 /*
109 * Add a wired entry to the TLB, it is used to map the commpage to
110 * the Guest kernel
111 */
112 wired = read_c0_wired();
113 write_c0_wired(wired + 1);
114 mtc0_tlbw_hazard();
115 kvm->arch.commpage_tlb = wired;
116
117 kvm_debug("[%d] commpage TLB: %d\n", smp_processor_id(),
118 kvm->arch.commpage_tlb);
119}
120
121static void kvm_mips_init_vm_percpu(void *arg)
122{
123 struct kvm *kvm = (struct kvm *)arg;
124
125 kvm_mips_init_tlbs(kvm);
126 kvm_mips_callbacks->vm_init(kvm);
127
128}
129
130int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
131{
132 if (atomic_inc_return(&kvm_mips_instance) == 1) {
133 kvm_debug("%s: 1st KVM instance, setup host TLB parameters\n",
134 __func__);
135 on_each_cpu(kvm_mips_init_vm_percpu, kvm, 1);
136 }
137
138 return 0;
139}
140
141void kvm_mips_free_vcpus(struct kvm *kvm)
142{
143 unsigned int i;
144 struct kvm_vcpu *vcpu;
145
146 /* Put the pages we reserved for the guest pmap */
147 for (i = 0; i < kvm->arch.guest_pmap_npages; i++) {
148 if (kvm->arch.guest_pmap[i] != KVM_INVALID_PAGE)
149 kvm_mips_release_pfn_clean(kvm->arch.guest_pmap[i]);
150 }
151 kfree(kvm->arch.guest_pmap);
152
153 kvm_for_each_vcpu(i, vcpu, kvm) {
154 kvm_arch_vcpu_free(vcpu);
155 }
156
157 mutex_lock(&kvm->lock);
158
159 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
160 kvm->vcpus[i] = NULL;
161
162 atomic_set(&kvm->online_vcpus, 0);
163
164 mutex_unlock(&kvm->lock);
165}
166
167static void kvm_mips_uninit_tlbs(void *arg)
168{
169 /* Restore wired count */
170 write_c0_wired(0);
171 mtc0_tlbw_hazard();
172 /* Clear out all the TLBs */
173 kvm_local_flush_tlb_all();
174}
175
176void kvm_arch_destroy_vm(struct kvm *kvm)
177{
178 kvm_mips_free_vcpus(kvm);
179
180 /* If this is the last instance, restore wired count */
181 if (atomic_dec_return(&kvm_mips_instance) == 0) {
182 kvm_debug("%s: last KVM instance, restoring TLB parameters\n",
183 __func__);
184 on_each_cpu(kvm_mips_uninit_tlbs, NULL, 1);
185 }
186}
187
188long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
189 unsigned long arg)
190{
191 return -ENOIOCTLCMD;
192}
193
194int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
195 unsigned long npages)
196{
197 return 0;
198}
199
200int kvm_arch_prepare_memory_region(struct kvm *kvm,
201 struct kvm_memory_slot *memslot,
202 const struct kvm_userspace_memory_region *mem,
203 enum kvm_mr_change change)
204{
205 return 0;
206}
207
208void kvm_arch_commit_memory_region(struct kvm *kvm,
209 const struct kvm_userspace_memory_region *mem,
210 const struct kvm_memory_slot *old,
211 const struct kvm_memory_slot *new,
212 enum kvm_mr_change change)
213{
214 unsigned long npages = 0;
215 int i;
216
217 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
218 __func__, kvm, mem->slot, mem->guest_phys_addr,
219 mem->memory_size, mem->userspace_addr);
220
221 /* Setup Guest PMAP table */
222 if (!kvm->arch.guest_pmap) {
223 if (mem->slot == 0)
224 npages = mem->memory_size >> PAGE_SHIFT;
225
226 if (npages) {
227 kvm->arch.guest_pmap_npages = npages;
228 kvm->arch.guest_pmap =
229 kzalloc(npages * sizeof(unsigned long), GFP_KERNEL);
230
231 if (!kvm->arch.guest_pmap) {
232 kvm_err("Failed to allocate guest PMAP\n");
233 return;
234 }
235
236 kvm_debug("Allocated space for Guest PMAP Table (%ld pages) @ %p\n",
237 npages, kvm->arch.guest_pmap);
238
239 /* Now setup the page table */
240 for (i = 0; i < npages; i++)
241 kvm->arch.guest_pmap[i] = KVM_INVALID_PAGE;
242 }
243 }
244}
245
246struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
247{
248 int err, size, offset;
249 void *gebase;
250 int i;
251
252 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
253
254 if (!vcpu) {
255 err = -ENOMEM;
256 goto out;
257 }
258
259 err = kvm_vcpu_init(vcpu, kvm, id);
260
261 if (err)
262 goto out_free_cpu;
263
264 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
265
266 /*
267 * Allocate space for host mode exception handlers that handle
268 * guest mode exits
269 */
270 if (cpu_has_veic || cpu_has_vint)
271 size = 0x200 + VECTORSPACING * 64;
272 else
273 size = 0x4000;
274
275 /* Save Linux EBASE */
276 vcpu->arch.host_ebase = (void *)read_c0_ebase();
277
278 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
279
280 if (!gebase) {
281 err = -ENOMEM;
282 goto out_uninit_cpu;
283 }
284 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
285 ALIGN(size, PAGE_SIZE), gebase);
286
287 /* Save new ebase */
288 vcpu->arch.guest_ebase = gebase;
289
290 /* Copy L1 Guest Exception handler to correct offset */
291
292 /* TLB Refill, EXL = 0 */
293 memcpy(gebase, mips32_exception,
294 mips32_exceptionEnd - mips32_exception);
295
296 /* General Exception Entry point */
297 memcpy(gebase + 0x180, mips32_exception,
298 mips32_exceptionEnd - mips32_exception);
299
300 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
301 for (i = 0; i < 8; i++) {
302 kvm_debug("L1 Vectored handler @ %p\n",
303 gebase + 0x200 + (i * VECTORSPACING));
304 memcpy(gebase + 0x200 + (i * VECTORSPACING), mips32_exception,
305 mips32_exceptionEnd - mips32_exception);
306 }
307
308 /* General handler, relocate to unmapped space for sanity's sake */
309 offset = 0x2000;
310 kvm_debug("Installing KVM Exception handlers @ %p, %#x bytes\n",
311 gebase + offset,
312 mips32_GuestExceptionEnd - mips32_GuestException);
313
314 memcpy(gebase + offset, mips32_GuestException,
315 mips32_GuestExceptionEnd - mips32_GuestException);
316
317 /* Invalidate the icache for these ranges */
318 local_flush_icache_range((unsigned long)gebase,
319 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
320
321 /*
322 * Allocate comm page for guest kernel, a TLB will be reserved for
323 * mapping GVA @ 0xFFFF8000 to this page
324 */
325 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
326
327 if (!vcpu->arch.kseg0_commpage) {
328 err = -ENOMEM;
329 goto out_free_gebase;
330 }
331
332 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
333 kvm_mips_commpage_init(vcpu);
334
335 /* Init */
336 vcpu->arch.last_sched_cpu = -1;
337
338 /* Start off the timer */
339 kvm_mips_init_count(vcpu);
340
341 return vcpu;
342
343out_free_gebase:
344 kfree(gebase);
345
346out_uninit_cpu:
347 kvm_vcpu_uninit(vcpu);
348
349out_free_cpu:
350 kfree(vcpu);
351
352out:
353 return ERR_PTR(err);
354}
355
356void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
357{
358 hrtimer_cancel(&vcpu->arch.comparecount_timer);
359
360 kvm_vcpu_uninit(vcpu);
361
362 kvm_mips_dump_stats(vcpu);
363
364 kfree(vcpu->arch.guest_ebase);
365 kfree(vcpu->arch.kseg0_commpage);
366 kfree(vcpu);
367}
368
369void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
370{
371 kvm_arch_vcpu_free(vcpu);
372}
373
374int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
375 struct kvm_guest_debug *dbg)
376{
377 return -ENOIOCTLCMD;
378}
379
380int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
381{
382 int r = 0;
383 sigset_t sigsaved;
384
385 if (vcpu->sigset_active)
386 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
387
388 if (vcpu->mmio_needed) {
389 if (!vcpu->mmio_is_write)
390 kvm_mips_complete_mmio_load(vcpu, run);
391 vcpu->mmio_needed = 0;
392 }
393
394 lose_fpu(1);
395
396 local_irq_disable();
397 /* Check if we have any exceptions/interrupts pending */
398 kvm_mips_deliver_interrupts(vcpu,
399 kvm_read_c0_guest_cause(vcpu->arch.cop0));
400
401 __kvm_guest_enter();
402
403 /* Disable hardware page table walking while in guest */
404 htw_stop();
405
406 r = __kvm_mips_vcpu_run(run, vcpu);
407
408 /* Re-enable HTW before enabling interrupts */
409 htw_start();
410
411 __kvm_guest_exit();
412 local_irq_enable();
413
414 if (vcpu->sigset_active)
415 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
416
417 return r;
418}
419
420int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
421 struct kvm_mips_interrupt *irq)
422{
423 int intr = (int)irq->irq;
424 struct kvm_vcpu *dvcpu = NULL;
425
426 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
427 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
428 (int)intr);
429
430 if (irq->cpu == -1)
431 dvcpu = vcpu;
432 else
433 dvcpu = vcpu->kvm->vcpus[irq->cpu];
434
435 if (intr == 2 || intr == 3 || intr == 4) {
436 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
437
438 } else if (intr == -2 || intr == -3 || intr == -4) {
439 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
440 } else {
441 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
442 irq->cpu, irq->irq);
443 return -EINVAL;
444 }
445
446 dvcpu->arch.wait = 0;
447
448 if (swait_active(&dvcpu->wq))
449 swake_up(&dvcpu->wq);
450
451 return 0;
452}
453
454int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
455 struct kvm_mp_state *mp_state)
456{
457 return -ENOIOCTLCMD;
458}
459
460int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
461 struct kvm_mp_state *mp_state)
462{
463 return -ENOIOCTLCMD;
464}
465
466static u64 kvm_mips_get_one_regs[] = {
467 KVM_REG_MIPS_R0,
468 KVM_REG_MIPS_R1,
469 KVM_REG_MIPS_R2,
470 KVM_REG_MIPS_R3,
471 KVM_REG_MIPS_R4,
472 KVM_REG_MIPS_R5,
473 KVM_REG_MIPS_R6,
474 KVM_REG_MIPS_R7,
475 KVM_REG_MIPS_R8,
476 KVM_REG_MIPS_R9,
477 KVM_REG_MIPS_R10,
478 KVM_REG_MIPS_R11,
479 KVM_REG_MIPS_R12,
480 KVM_REG_MIPS_R13,
481 KVM_REG_MIPS_R14,
482 KVM_REG_MIPS_R15,
483 KVM_REG_MIPS_R16,
484 KVM_REG_MIPS_R17,
485 KVM_REG_MIPS_R18,
486 KVM_REG_MIPS_R19,
487 KVM_REG_MIPS_R20,
488 KVM_REG_MIPS_R21,
489 KVM_REG_MIPS_R22,
490 KVM_REG_MIPS_R23,
491 KVM_REG_MIPS_R24,
492 KVM_REG_MIPS_R25,
493 KVM_REG_MIPS_R26,
494 KVM_REG_MIPS_R27,
495 KVM_REG_MIPS_R28,
496 KVM_REG_MIPS_R29,
497 KVM_REG_MIPS_R30,
498 KVM_REG_MIPS_R31,
499
500 KVM_REG_MIPS_HI,
501 KVM_REG_MIPS_LO,
502 KVM_REG_MIPS_PC,
503
504 KVM_REG_MIPS_CP0_INDEX,
505 KVM_REG_MIPS_CP0_CONTEXT,
506 KVM_REG_MIPS_CP0_USERLOCAL,
507 KVM_REG_MIPS_CP0_PAGEMASK,
508 KVM_REG_MIPS_CP0_WIRED,
509 KVM_REG_MIPS_CP0_HWRENA,
510 KVM_REG_MIPS_CP0_BADVADDR,
511 KVM_REG_MIPS_CP0_COUNT,
512 KVM_REG_MIPS_CP0_ENTRYHI,
513 KVM_REG_MIPS_CP0_COMPARE,
514 KVM_REG_MIPS_CP0_STATUS,
515 KVM_REG_MIPS_CP0_CAUSE,
516 KVM_REG_MIPS_CP0_EPC,
517 KVM_REG_MIPS_CP0_PRID,
518 KVM_REG_MIPS_CP0_CONFIG,
519 KVM_REG_MIPS_CP0_CONFIG1,
520 KVM_REG_MIPS_CP0_CONFIG2,
521 KVM_REG_MIPS_CP0_CONFIG3,
522 KVM_REG_MIPS_CP0_CONFIG4,
523 KVM_REG_MIPS_CP0_CONFIG5,
524 KVM_REG_MIPS_CP0_CONFIG7,
525 KVM_REG_MIPS_CP0_ERROREPC,
526
527 KVM_REG_MIPS_COUNT_CTL,
528 KVM_REG_MIPS_COUNT_RESUME,
529 KVM_REG_MIPS_COUNT_HZ,
530};
531
532static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
533 const struct kvm_one_reg *reg)
534{
535 struct mips_coproc *cop0 = vcpu->arch.cop0;
536 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
537 int ret;
538 s64 v;
539 s64 vs[2];
540 unsigned int idx;
541
542 switch (reg->id) {
543 /* General purpose registers */
544 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
545 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
546 break;
547 case KVM_REG_MIPS_HI:
548 v = (long)vcpu->arch.hi;
549 break;
550 case KVM_REG_MIPS_LO:
551 v = (long)vcpu->arch.lo;
552 break;
553 case KVM_REG_MIPS_PC:
554 v = (long)vcpu->arch.pc;
555 break;
556
557 /* Floating point registers */
558 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
559 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
560 return -EINVAL;
561 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
562 /* Odd singles in top of even double when FR=0 */
563 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
564 v = get_fpr32(&fpu->fpr[idx], 0);
565 else
566 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
567 break;
568 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
569 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
570 return -EINVAL;
571 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
572 /* Can't access odd doubles in FR=0 mode */
573 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
574 return -EINVAL;
575 v = get_fpr64(&fpu->fpr[idx], 0);
576 break;
577 case KVM_REG_MIPS_FCR_IR:
578 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
579 return -EINVAL;
580 v = boot_cpu_data.fpu_id;
581 break;
582 case KVM_REG_MIPS_FCR_CSR:
583 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
584 return -EINVAL;
585 v = fpu->fcr31;
586 break;
587
588 /* MIPS SIMD Architecture (MSA) registers */
589 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
590 if (!kvm_mips_guest_has_msa(&vcpu->arch))
591 return -EINVAL;
592 /* Can't access MSA registers in FR=0 mode */
593 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
594 return -EINVAL;
595 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
596#ifdef CONFIG_CPU_LITTLE_ENDIAN
597 /* least significant byte first */
598 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
599 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
600#else
601 /* most significant byte first */
602 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
603 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
604#endif
605 break;
606 case KVM_REG_MIPS_MSA_IR:
607 if (!kvm_mips_guest_has_msa(&vcpu->arch))
608 return -EINVAL;
609 v = boot_cpu_data.msa_id;
610 break;
611 case KVM_REG_MIPS_MSA_CSR:
612 if (!kvm_mips_guest_has_msa(&vcpu->arch))
613 return -EINVAL;
614 v = fpu->msacsr;
615 break;
616
617 /* Co-processor 0 registers */
618 case KVM_REG_MIPS_CP0_INDEX:
619 v = (long)kvm_read_c0_guest_index(cop0);
620 break;
621 case KVM_REG_MIPS_CP0_CONTEXT:
622 v = (long)kvm_read_c0_guest_context(cop0);
623 break;
624 case KVM_REG_MIPS_CP0_USERLOCAL:
625 v = (long)kvm_read_c0_guest_userlocal(cop0);
626 break;
627 case KVM_REG_MIPS_CP0_PAGEMASK:
628 v = (long)kvm_read_c0_guest_pagemask(cop0);
629 break;
630 case KVM_REG_MIPS_CP0_WIRED:
631 v = (long)kvm_read_c0_guest_wired(cop0);
632 break;
633 case KVM_REG_MIPS_CP0_HWRENA:
634 v = (long)kvm_read_c0_guest_hwrena(cop0);
635 break;
636 case KVM_REG_MIPS_CP0_BADVADDR:
637 v = (long)kvm_read_c0_guest_badvaddr(cop0);
638 break;
639 case KVM_REG_MIPS_CP0_ENTRYHI:
640 v = (long)kvm_read_c0_guest_entryhi(cop0);
641 break;
642 case KVM_REG_MIPS_CP0_COMPARE:
643 v = (long)kvm_read_c0_guest_compare(cop0);
644 break;
645 case KVM_REG_MIPS_CP0_STATUS:
646 v = (long)kvm_read_c0_guest_status(cop0);
647 break;
648 case KVM_REG_MIPS_CP0_CAUSE:
649 v = (long)kvm_read_c0_guest_cause(cop0);
650 break;
651 case KVM_REG_MIPS_CP0_EPC:
652 v = (long)kvm_read_c0_guest_epc(cop0);
653 break;
654 case KVM_REG_MIPS_CP0_PRID:
655 v = (long)kvm_read_c0_guest_prid(cop0);
656 break;
657 case KVM_REG_MIPS_CP0_CONFIG:
658 v = (long)kvm_read_c0_guest_config(cop0);
659 break;
660 case KVM_REG_MIPS_CP0_CONFIG1:
661 v = (long)kvm_read_c0_guest_config1(cop0);
662 break;
663 case KVM_REG_MIPS_CP0_CONFIG2:
664 v = (long)kvm_read_c0_guest_config2(cop0);
665 break;
666 case KVM_REG_MIPS_CP0_CONFIG3:
667 v = (long)kvm_read_c0_guest_config3(cop0);
668 break;
669 case KVM_REG_MIPS_CP0_CONFIG4:
670 v = (long)kvm_read_c0_guest_config4(cop0);
671 break;
672 case KVM_REG_MIPS_CP0_CONFIG5:
673 v = (long)kvm_read_c0_guest_config5(cop0);
674 break;
675 case KVM_REG_MIPS_CP0_CONFIG7:
676 v = (long)kvm_read_c0_guest_config7(cop0);
677 break;
678 case KVM_REG_MIPS_CP0_ERROREPC:
679 v = (long)kvm_read_c0_guest_errorepc(cop0);
680 break;
681 /* registers to be handled specially */
682 case KVM_REG_MIPS_CP0_COUNT:
683 case KVM_REG_MIPS_COUNT_CTL:
684 case KVM_REG_MIPS_COUNT_RESUME:
685 case KVM_REG_MIPS_COUNT_HZ:
686 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
687 if (ret)
688 return ret;
689 break;
690 default:
691 return -EINVAL;
692 }
693 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
694 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
695
696 return put_user(v, uaddr64);
697 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
698 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
699 u32 v32 = (u32)v;
700
701 return put_user(v32, uaddr32);
702 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
703 void __user *uaddr = (void __user *)(long)reg->addr;
704
705 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
706 } else {
707 return -EINVAL;
708 }
709}
710
711static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
712 const struct kvm_one_reg *reg)
713{
714 struct mips_coproc *cop0 = vcpu->arch.cop0;
715 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
716 s64 v;
717 s64 vs[2];
718 unsigned int idx;
719
720 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
721 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
722
723 if (get_user(v, uaddr64) != 0)
724 return -EFAULT;
725 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
726 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
727 s32 v32;
728
729 if (get_user(v32, uaddr32) != 0)
730 return -EFAULT;
731 v = (s64)v32;
732 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
733 void __user *uaddr = (void __user *)(long)reg->addr;
734
735 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
736 } else {
737 return -EINVAL;
738 }
739
740 switch (reg->id) {
741 /* General purpose registers */
742 case KVM_REG_MIPS_R0:
743 /* Silently ignore requests to set $0 */
744 break;
745 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
746 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
747 break;
748 case KVM_REG_MIPS_HI:
749 vcpu->arch.hi = v;
750 break;
751 case KVM_REG_MIPS_LO:
752 vcpu->arch.lo = v;
753 break;
754 case KVM_REG_MIPS_PC:
755 vcpu->arch.pc = v;
756 break;
757
758 /* Floating point registers */
759 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
760 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
761 return -EINVAL;
762 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
763 /* Odd singles in top of even double when FR=0 */
764 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
765 set_fpr32(&fpu->fpr[idx], 0, v);
766 else
767 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
768 break;
769 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
770 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
771 return -EINVAL;
772 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
773 /* Can't access odd doubles in FR=0 mode */
774 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
775 return -EINVAL;
776 set_fpr64(&fpu->fpr[idx], 0, v);
777 break;
778 case KVM_REG_MIPS_FCR_IR:
779 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
780 return -EINVAL;
781 /* Read-only */
782 break;
783 case KVM_REG_MIPS_FCR_CSR:
784 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
785 return -EINVAL;
786 fpu->fcr31 = v;
787 break;
788
789 /* MIPS SIMD Architecture (MSA) registers */
790 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
791 if (!kvm_mips_guest_has_msa(&vcpu->arch))
792 return -EINVAL;
793 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
794#ifdef CONFIG_CPU_LITTLE_ENDIAN
795 /* least significant byte first */
796 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
797 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
798#else
799 /* most significant byte first */
800 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
801 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
802#endif
803 break;
804 case KVM_REG_MIPS_MSA_IR:
805 if (!kvm_mips_guest_has_msa(&vcpu->arch))
806 return -EINVAL;
807 /* Read-only */
808 break;
809 case KVM_REG_MIPS_MSA_CSR:
810 if (!kvm_mips_guest_has_msa(&vcpu->arch))
811 return -EINVAL;
812 fpu->msacsr = v;
813 break;
814
815 /* Co-processor 0 registers */
816 case KVM_REG_MIPS_CP0_INDEX:
817 kvm_write_c0_guest_index(cop0, v);
818 break;
819 case KVM_REG_MIPS_CP0_CONTEXT:
820 kvm_write_c0_guest_context(cop0, v);
821 break;
822 case KVM_REG_MIPS_CP0_USERLOCAL:
823 kvm_write_c0_guest_userlocal(cop0, v);
824 break;
825 case KVM_REG_MIPS_CP0_PAGEMASK:
826 kvm_write_c0_guest_pagemask(cop0, v);
827 break;
828 case KVM_REG_MIPS_CP0_WIRED:
829 kvm_write_c0_guest_wired(cop0, v);
830 break;
831 case KVM_REG_MIPS_CP0_HWRENA:
832 kvm_write_c0_guest_hwrena(cop0, v);
833 break;
834 case KVM_REG_MIPS_CP0_BADVADDR:
835 kvm_write_c0_guest_badvaddr(cop0, v);
836 break;
837 case KVM_REG_MIPS_CP0_ENTRYHI:
838 kvm_write_c0_guest_entryhi(cop0, v);
839 break;
840 case KVM_REG_MIPS_CP0_STATUS:
841 kvm_write_c0_guest_status(cop0, v);
842 break;
843 case KVM_REG_MIPS_CP0_EPC:
844 kvm_write_c0_guest_epc(cop0, v);
845 break;
846 case KVM_REG_MIPS_CP0_PRID:
847 kvm_write_c0_guest_prid(cop0, v);
848 break;
849 case KVM_REG_MIPS_CP0_ERROREPC:
850 kvm_write_c0_guest_errorepc(cop0, v);
851 break;
852 /* registers to be handled specially */
853 case KVM_REG_MIPS_CP0_COUNT:
854 case KVM_REG_MIPS_CP0_COMPARE:
855 case KVM_REG_MIPS_CP0_CAUSE:
856 case KVM_REG_MIPS_CP0_CONFIG:
857 case KVM_REG_MIPS_CP0_CONFIG1:
858 case KVM_REG_MIPS_CP0_CONFIG2:
859 case KVM_REG_MIPS_CP0_CONFIG3:
860 case KVM_REG_MIPS_CP0_CONFIG4:
861 case KVM_REG_MIPS_CP0_CONFIG5:
862 case KVM_REG_MIPS_COUNT_CTL:
863 case KVM_REG_MIPS_COUNT_RESUME:
864 case KVM_REG_MIPS_COUNT_HZ:
865 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
866 default:
867 return -EINVAL;
868 }
869 return 0;
870}
871
872static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
873 struct kvm_enable_cap *cap)
874{
875 int r = 0;
876
877 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
878 return -EINVAL;
879 if (cap->flags)
880 return -EINVAL;
881 if (cap->args[0])
882 return -EINVAL;
883
884 switch (cap->cap) {
885 case KVM_CAP_MIPS_FPU:
886 vcpu->arch.fpu_enabled = true;
887 break;
888 case KVM_CAP_MIPS_MSA:
889 vcpu->arch.msa_enabled = true;
890 break;
891 default:
892 r = -EINVAL;
893 break;
894 }
895
896 return r;
897}
898
899long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
900 unsigned long arg)
901{
902 struct kvm_vcpu *vcpu = filp->private_data;
903 void __user *argp = (void __user *)arg;
904 long r;
905
906 switch (ioctl) {
907 case KVM_SET_ONE_REG:
908 case KVM_GET_ONE_REG: {
909 struct kvm_one_reg reg;
910
911 if (copy_from_user(®, argp, sizeof(reg)))
912 return -EFAULT;
913 if (ioctl == KVM_SET_ONE_REG)
914 return kvm_mips_set_reg(vcpu, ®);
915 else
916 return kvm_mips_get_reg(vcpu, ®);
917 }
918 case KVM_GET_REG_LIST: {
919 struct kvm_reg_list __user *user_list = argp;
920 u64 __user *reg_dest;
921 struct kvm_reg_list reg_list;
922 unsigned n;
923
924 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
925 return -EFAULT;
926 n = reg_list.n;
927 reg_list.n = ARRAY_SIZE(kvm_mips_get_one_regs);
928 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
929 return -EFAULT;
930 if (n < reg_list.n)
931 return -E2BIG;
932 reg_dest = user_list->reg;
933 if (copy_to_user(reg_dest, kvm_mips_get_one_regs,
934 sizeof(kvm_mips_get_one_regs)))
935 return -EFAULT;
936 return 0;
937 }
938 case KVM_NMI:
939 /* Treat the NMI as a CPU reset */
940 r = kvm_mips_reset_vcpu(vcpu);
941 break;
942 case KVM_INTERRUPT:
943 {
944 struct kvm_mips_interrupt irq;
945
946 r = -EFAULT;
947 if (copy_from_user(&irq, argp, sizeof(irq)))
948 goto out;
949
950 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
951 irq.irq);
952
953 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
954 break;
955 }
956 case KVM_ENABLE_CAP: {
957 struct kvm_enable_cap cap;
958
959 r = -EFAULT;
960 if (copy_from_user(&cap, argp, sizeof(cap)))
961 goto out;
962 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
963 break;
964 }
965 default:
966 r = -ENOIOCTLCMD;
967 }
968
969out:
970 return r;
971}
972
973/* Get (and clear) the dirty memory log for a memory slot. */
974int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
975{
976 struct kvm_memslots *slots;
977 struct kvm_memory_slot *memslot;
978 unsigned long ga, ga_end;
979 int is_dirty = 0;
980 int r;
981 unsigned long n;
982
983 mutex_lock(&kvm->slots_lock);
984
985 r = kvm_get_dirty_log(kvm, log, &is_dirty);
986 if (r)
987 goto out;
988
989 /* If nothing is dirty, don't bother messing with page tables. */
990 if (is_dirty) {
991 slots = kvm_memslots(kvm);
992 memslot = id_to_memslot(slots, log->slot);
993
994 ga = memslot->base_gfn << PAGE_SHIFT;
995 ga_end = ga + (memslot->npages << PAGE_SHIFT);
996
997 kvm_info("%s: dirty, ga: %#lx, ga_end %#lx\n", __func__, ga,
998 ga_end);
999
1000 n = kvm_dirty_bitmap_bytes(memslot);
1001 memset(memslot->dirty_bitmap, 0, n);
1002 }
1003
1004 r = 0;
1005out:
1006 mutex_unlock(&kvm->slots_lock);
1007 return r;
1008
1009}
1010
1011long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1012{
1013 long r;
1014
1015 switch (ioctl) {
1016 default:
1017 r = -ENOIOCTLCMD;
1018 }
1019
1020 return r;
1021}
1022
1023int kvm_arch_init(void *opaque)
1024{
1025 if (kvm_mips_callbacks) {
1026 kvm_err("kvm: module already exists\n");
1027 return -EEXIST;
1028 }
1029
1030 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1031}
1032
1033void kvm_arch_exit(void)
1034{
1035 kvm_mips_callbacks = NULL;
1036}
1037
1038int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1039 struct kvm_sregs *sregs)
1040{
1041 return -ENOIOCTLCMD;
1042}
1043
1044int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1045 struct kvm_sregs *sregs)
1046{
1047 return -ENOIOCTLCMD;
1048}
1049
1050void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1051{
1052}
1053
1054int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1055{
1056 return -ENOIOCTLCMD;
1057}
1058
1059int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1060{
1061 return -ENOIOCTLCMD;
1062}
1063
1064int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1065{
1066 return VM_FAULT_SIGBUS;
1067}
1068
1069int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1070{
1071 int r;
1072
1073 switch (ext) {
1074 case KVM_CAP_ONE_REG:
1075 case KVM_CAP_ENABLE_CAP:
1076 r = 1;
1077 break;
1078 case KVM_CAP_COALESCED_MMIO:
1079 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1080 break;
1081 case KVM_CAP_MIPS_FPU:
1082 r = !!cpu_has_fpu;
1083 break;
1084 case KVM_CAP_MIPS_MSA:
1085 /*
1086 * We don't support MSA vector partitioning yet:
1087 * 1) It would require explicit support which can't be tested
1088 * yet due to lack of support in current hardware.
1089 * 2) It extends the state that would need to be saved/restored
1090 * by e.g. QEMU for migration.
1091 *
1092 * When vector partitioning hardware becomes available, support
1093 * could be added by requiring a flag when enabling
1094 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1095 * to save/restore the appropriate extra state.
1096 */
1097 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1098 break;
1099 default:
1100 r = 0;
1101 break;
1102 }
1103 return r;
1104}
1105
1106int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1107{
1108 return kvm_mips_pending_timer(vcpu);
1109}
1110
1111int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1112{
1113 int i;
1114 struct mips_coproc *cop0;
1115
1116 if (!vcpu)
1117 return -1;
1118
1119 kvm_debug("VCPU Register Dump:\n");
1120 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1121 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1122
1123 for (i = 0; i < 32; i += 4) {
1124 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1125 vcpu->arch.gprs[i],
1126 vcpu->arch.gprs[i + 1],
1127 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1128 }
1129 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1130 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1131
1132 cop0 = vcpu->arch.cop0;
1133 kvm_debug("\tStatus: 0x%08lx, Cause: 0x%08lx\n",
1134 kvm_read_c0_guest_status(cop0),
1135 kvm_read_c0_guest_cause(cop0));
1136
1137 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1138
1139 return 0;
1140}
1141
1142int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1143{
1144 int i;
1145
1146 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1147 vcpu->arch.gprs[i] = regs->gpr[i];
1148 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1149 vcpu->arch.hi = regs->hi;
1150 vcpu->arch.lo = regs->lo;
1151 vcpu->arch.pc = regs->pc;
1152
1153 return 0;
1154}
1155
1156int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1157{
1158 int i;
1159
1160 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1161 regs->gpr[i] = vcpu->arch.gprs[i];
1162
1163 regs->hi = vcpu->arch.hi;
1164 regs->lo = vcpu->arch.lo;
1165 regs->pc = vcpu->arch.pc;
1166
1167 return 0;
1168}
1169
1170static void kvm_mips_comparecount_func(unsigned long data)
1171{
1172 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1173
1174 kvm_mips_callbacks->queue_timer_int(vcpu);
1175
1176 vcpu->arch.wait = 0;
1177 if (swait_active(&vcpu->wq))
1178 swake_up(&vcpu->wq);
1179}
1180
1181/* low level hrtimer wake routine */
1182static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1183{
1184 struct kvm_vcpu *vcpu;
1185
1186 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1187 kvm_mips_comparecount_func((unsigned long) vcpu);
1188 return kvm_mips_count_timeout(vcpu);
1189}
1190
1191int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1192{
1193 kvm_mips_callbacks->vcpu_init(vcpu);
1194 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1195 HRTIMER_MODE_REL);
1196 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1197 return 0;
1198}
1199
1200int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1201 struct kvm_translation *tr)
1202{
1203 return 0;
1204}
1205
1206/* Initial guest state */
1207int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1208{
1209 return kvm_mips_callbacks->vcpu_setup(vcpu);
1210}
1211
1212static void kvm_mips_set_c0_status(void)
1213{
1214 uint32_t status = read_c0_status();
1215
1216 if (cpu_has_dsp)
1217 status |= (ST0_MX);
1218
1219 write_c0_status(status);
1220 ehb();
1221}
1222
1223/*
1224 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1225 */
1226int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1227{
1228 uint32_t cause = vcpu->arch.host_cp0_cause;
1229 uint32_t exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1230 uint32_t __user *opc = (uint32_t __user *) vcpu->arch.pc;
1231 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1232 enum emulation_result er = EMULATE_DONE;
1233 int ret = RESUME_GUEST;
1234
1235 /* re-enable HTW before enabling interrupts */
1236 htw_start();
1237
1238 /* Set a default exit reason */
1239 run->exit_reason = KVM_EXIT_UNKNOWN;
1240 run->ready_for_interrupt_injection = 1;
1241
1242 /*
1243 * Set the appropriate status bits based on host CPU features,
1244 * before we hit the scheduler
1245 */
1246 kvm_mips_set_c0_status();
1247
1248 local_irq_enable();
1249
1250 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1251 cause, opc, run, vcpu);
1252
1253 /*
1254 * Do a privilege check, if in UM most of these exit conditions end up
1255 * causing an exception to be delivered to the Guest Kernel
1256 */
1257 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1258 if (er == EMULATE_PRIV_FAIL) {
1259 goto skip_emul;
1260 } else if (er == EMULATE_FAIL) {
1261 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1262 ret = RESUME_HOST;
1263 goto skip_emul;
1264 }
1265
1266 switch (exccode) {
1267 case EXCCODE_INT:
1268 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1269
1270 ++vcpu->stat.int_exits;
1271 trace_kvm_exit(vcpu, INT_EXITS);
1272
1273 if (need_resched())
1274 cond_resched();
1275
1276 ret = RESUME_GUEST;
1277 break;
1278
1279 case EXCCODE_CPU:
1280 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1281
1282 ++vcpu->stat.cop_unusable_exits;
1283 trace_kvm_exit(vcpu, COP_UNUSABLE_EXITS);
1284 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1285 /* XXXKYMA: Might need to return to user space */
1286 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1287 ret = RESUME_HOST;
1288 break;
1289
1290 case EXCCODE_MOD:
1291 ++vcpu->stat.tlbmod_exits;
1292 trace_kvm_exit(vcpu, TLBMOD_EXITS);
1293 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1294 break;
1295
1296 case EXCCODE_TLBS:
1297 kvm_debug("TLB ST fault: cause %#x, status %#lx, PC: %p, BadVaddr: %#lx\n",
1298 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1299 badvaddr);
1300
1301 ++vcpu->stat.tlbmiss_st_exits;
1302 trace_kvm_exit(vcpu, TLBMISS_ST_EXITS);
1303 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1304 break;
1305
1306 case EXCCODE_TLBL:
1307 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1308 cause, opc, badvaddr);
1309
1310 ++vcpu->stat.tlbmiss_ld_exits;
1311 trace_kvm_exit(vcpu, TLBMISS_LD_EXITS);
1312 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1313 break;
1314
1315 case EXCCODE_ADES:
1316 ++vcpu->stat.addrerr_st_exits;
1317 trace_kvm_exit(vcpu, ADDRERR_ST_EXITS);
1318 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1319 break;
1320
1321 case EXCCODE_ADEL:
1322 ++vcpu->stat.addrerr_ld_exits;
1323 trace_kvm_exit(vcpu, ADDRERR_LD_EXITS);
1324 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1325 break;
1326
1327 case EXCCODE_SYS:
1328 ++vcpu->stat.syscall_exits;
1329 trace_kvm_exit(vcpu, SYSCALL_EXITS);
1330 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1331 break;
1332
1333 case EXCCODE_RI:
1334 ++vcpu->stat.resvd_inst_exits;
1335 trace_kvm_exit(vcpu, RESVD_INST_EXITS);
1336 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1337 break;
1338
1339 case EXCCODE_BP:
1340 ++vcpu->stat.break_inst_exits;
1341 trace_kvm_exit(vcpu, BREAK_INST_EXITS);
1342 ret = kvm_mips_callbacks->handle_break(vcpu);
1343 break;
1344
1345 case EXCCODE_TR:
1346 ++vcpu->stat.trap_inst_exits;
1347 trace_kvm_exit(vcpu, TRAP_INST_EXITS);
1348 ret = kvm_mips_callbacks->handle_trap(vcpu);
1349 break;
1350
1351 case EXCCODE_MSAFPE:
1352 ++vcpu->stat.msa_fpe_exits;
1353 trace_kvm_exit(vcpu, MSA_FPE_EXITS);
1354 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1355 break;
1356
1357 case EXCCODE_FPE:
1358 ++vcpu->stat.fpe_exits;
1359 trace_kvm_exit(vcpu, FPE_EXITS);
1360 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1361 break;
1362
1363 case EXCCODE_MSADIS:
1364 ++vcpu->stat.msa_disabled_exits;
1365 trace_kvm_exit(vcpu, MSA_DISABLED_EXITS);
1366 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1367 break;
1368
1369 default:
1370 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#lx\n",
1371 exccode, opc, kvm_get_inst(opc, vcpu), badvaddr,
1372 kvm_read_c0_guest_status(vcpu->arch.cop0));
1373 kvm_arch_vcpu_dump_regs(vcpu);
1374 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1375 ret = RESUME_HOST;
1376 break;
1377
1378 }
1379
1380skip_emul:
1381 local_irq_disable();
1382
1383 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1384 kvm_mips_deliver_interrupts(vcpu, cause);
1385
1386 if (!(ret & RESUME_HOST)) {
1387 /* Only check for signals if not already exiting to userspace */
1388 if (signal_pending(current)) {
1389 run->exit_reason = KVM_EXIT_INTR;
1390 ret = (-EINTR << 2) | RESUME_HOST;
1391 ++vcpu->stat.signal_exits;
1392 trace_kvm_exit(vcpu, SIGNAL_EXITS);
1393 }
1394 }
1395
1396 if (ret == RESUME_GUEST) {
1397 /*
1398 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1399 * is live), restore FCR31 / MSACSR.
1400 *
1401 * This should be before returning to the guest exception
1402 * vector, as it may well cause an [MSA] FP exception if there
1403 * are pending exception bits unmasked. (see
1404 * kvm_mips_csr_die_notifier() for how that is handled).
1405 */
1406 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1407 read_c0_status() & ST0_CU1)
1408 __kvm_restore_fcsr(&vcpu->arch);
1409
1410 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1411 read_c0_config5() & MIPS_CONF5_MSAEN)
1412 __kvm_restore_msacsr(&vcpu->arch);
1413 }
1414
1415 /* Disable HTW before returning to guest or host */
1416 htw_stop();
1417
1418 return ret;
1419}
1420
1421/* Enable FPU for guest and restore context */
1422void kvm_own_fpu(struct kvm_vcpu *vcpu)
1423{
1424 struct mips_coproc *cop0 = vcpu->arch.cop0;
1425 unsigned int sr, cfg5;
1426
1427 preempt_disable();
1428
1429 sr = kvm_read_c0_guest_status(cop0);
1430
1431 /*
1432 * If MSA state is already live, it is undefined how it interacts with
1433 * FR=0 FPU state, and we don't want to hit reserved instruction
1434 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1435 * play it safe and save it first.
1436 *
1437 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1438 * get called when guest CU1 is set, however we can't trust the guest
1439 * not to clobber the status register directly via the commpage.
1440 */
1441 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1442 vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA)
1443 kvm_lose_fpu(vcpu);
1444
1445 /*
1446 * Enable FPU for guest
1447 * We set FR and FRE according to guest context
1448 */
1449 change_c0_status(ST0_CU1 | ST0_FR, sr);
1450 if (cpu_has_fre) {
1451 cfg5 = kvm_read_c0_guest_config5(cop0);
1452 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1453 }
1454 enable_fpu_hazard();
1455
1456 /* If guest FPU state not active, restore it now */
1457 if (!(vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)) {
1458 __kvm_restore_fpu(&vcpu->arch);
1459 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1460 }
1461
1462 preempt_enable();
1463}
1464
1465#ifdef CONFIG_CPU_HAS_MSA
1466/* Enable MSA for guest and restore context */
1467void kvm_own_msa(struct kvm_vcpu *vcpu)
1468{
1469 struct mips_coproc *cop0 = vcpu->arch.cop0;
1470 unsigned int sr, cfg5;
1471
1472 preempt_disable();
1473
1474 /*
1475 * Enable FPU if enabled in guest, since we're restoring FPU context
1476 * anyway. We set FR and FRE according to guest context.
1477 */
1478 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1479 sr = kvm_read_c0_guest_status(cop0);
1480
1481 /*
1482 * If FR=0 FPU state is already live, it is undefined how it
1483 * interacts with MSA state, so play it safe and save it first.
1484 */
1485 if (!(sr & ST0_FR) &&
1486 (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU |
1487 KVM_MIPS_FPU_MSA)) == KVM_MIPS_FPU_FPU)
1488 kvm_lose_fpu(vcpu);
1489
1490 change_c0_status(ST0_CU1 | ST0_FR, sr);
1491 if (sr & ST0_CU1 && cpu_has_fre) {
1492 cfg5 = kvm_read_c0_guest_config5(cop0);
1493 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1494 }
1495 }
1496
1497 /* Enable MSA for guest */
1498 set_c0_config5(MIPS_CONF5_MSAEN);
1499 enable_fpu_hazard();
1500
1501 switch (vcpu->arch.fpu_inuse & (KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA)) {
1502 case KVM_MIPS_FPU_FPU:
1503 /*
1504 * Guest FPU state already loaded, only restore upper MSA state
1505 */
1506 __kvm_restore_msa_upper(&vcpu->arch);
1507 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1508 break;
1509 case 0:
1510 /* Neither FPU or MSA already active, restore full MSA state */
1511 __kvm_restore_msa(&vcpu->arch);
1512 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_MSA;
1513 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1514 vcpu->arch.fpu_inuse |= KVM_MIPS_FPU_FPU;
1515 break;
1516 default:
1517 break;
1518 }
1519
1520 preempt_enable();
1521}
1522#endif
1523
1524/* Drop FPU & MSA without saving it */
1525void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1526{
1527 preempt_disable();
1528 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1529 disable_msa();
1530 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_MSA;
1531 }
1532 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1533 clear_c0_status(ST0_CU1 | ST0_FR);
1534 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1535 }
1536 preempt_enable();
1537}
1538
1539/* Save and disable FPU & MSA */
1540void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1541{
1542 /*
1543 * FPU & MSA get disabled in root context (hardware) when it is disabled
1544 * in guest context (software), but the register state in the hardware
1545 * may still be in use. This is why we explicitly re-enable the hardware
1546 * before saving.
1547 */
1548
1549 preempt_disable();
1550 if (cpu_has_msa && vcpu->arch.fpu_inuse & KVM_MIPS_FPU_MSA) {
1551 set_c0_config5(MIPS_CONF5_MSAEN);
1552 enable_fpu_hazard();
1553
1554 __kvm_save_msa(&vcpu->arch);
1555
1556 /* Disable MSA & FPU */
1557 disable_msa();
1558 if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU)
1559 clear_c0_status(ST0_CU1 | ST0_FR);
1560 vcpu->arch.fpu_inuse &= ~(KVM_MIPS_FPU_FPU | KVM_MIPS_FPU_MSA);
1561 } else if (vcpu->arch.fpu_inuse & KVM_MIPS_FPU_FPU) {
1562 set_c0_status(ST0_CU1);
1563 enable_fpu_hazard();
1564
1565 __kvm_save_fpu(&vcpu->arch);
1566 vcpu->arch.fpu_inuse &= ~KVM_MIPS_FPU_FPU;
1567
1568 /* Disable FPU */
1569 clear_c0_status(ST0_CU1 | ST0_FR);
1570 }
1571 preempt_enable();
1572}
1573
1574/*
1575 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1576 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1577 * exception if cause bits are set in the value being written.
1578 */
1579static int kvm_mips_csr_die_notify(struct notifier_block *self,
1580 unsigned long cmd, void *ptr)
1581{
1582 struct die_args *args = (struct die_args *)ptr;
1583 struct pt_regs *regs = args->regs;
1584 unsigned long pc;
1585
1586 /* Only interested in FPE and MSAFPE */
1587 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1588 return NOTIFY_DONE;
1589
1590 /* Return immediately if guest context isn't active */
1591 if (!(current->flags & PF_VCPU))
1592 return NOTIFY_DONE;
1593
1594 /* Should never get here from user mode */
1595 BUG_ON(user_mode(regs));
1596
1597 pc = instruction_pointer(regs);
1598 switch (cmd) {
1599 case DIE_FP:
1600 /* match 2nd instruction in __kvm_restore_fcsr */
1601 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1602 return NOTIFY_DONE;
1603 break;
1604 case DIE_MSAFP:
1605 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1606 if (!cpu_has_msa ||
1607 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1608 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1609 return NOTIFY_DONE;
1610 break;
1611 }
1612
1613 /* Move PC forward a little and continue executing */
1614 instruction_pointer(regs) += 4;
1615
1616 return NOTIFY_STOP;
1617}
1618
1619static struct notifier_block kvm_mips_csr_die_notifier = {
1620 .notifier_call = kvm_mips_csr_die_notify,
1621};
1622
1623static int __init kvm_mips_init(void)
1624{
1625 int ret;
1626
1627 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1628
1629 if (ret)
1630 return ret;
1631
1632 register_die_notifier(&kvm_mips_csr_die_notifier);
1633
1634 /*
1635 * On MIPS, kernel modules are executed from "mapped space", which
1636 * requires TLBs. The TLB handling code is statically linked with
1637 * the rest of the kernel (tlb.c) to avoid the possibility of
1638 * double faulting. The issue is that the TLB code references
1639 * routines that are part of the the KVM module, which are only
1640 * available once the module is loaded.
1641 */
1642 kvm_mips_gfn_to_pfn = gfn_to_pfn;
1643 kvm_mips_release_pfn_clean = kvm_release_pfn_clean;
1644 kvm_mips_is_error_pfn = is_error_pfn;
1645
1646 return 0;
1647}
1648
1649static void __exit kvm_mips_exit(void)
1650{
1651 kvm_exit();
1652
1653 kvm_mips_gfn_to_pfn = NULL;
1654 kvm_mips_release_pfn_clean = NULL;
1655 kvm_mips_is_error_pfn = NULL;
1656
1657 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1658}
1659
1660module_init(kvm_mips_init);
1661module_exit(kvm_mips_exit);
1662
1663EXPORT_TRACEPOINT_SYMBOL(kvm_exit);