1/*
  2 * Samsung's Exynos5 SoC series common device tree source
  3 *
  4 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
  5 *		http://www.samsung.com
  6 *
  7 * Samsung's Exynos5 SoC series device nodes are listed in this file. Particular
  8 * SoCs from Exynos5 series can include this file and provide values for SoCs
  9 * specfic bindings.
 10 *
 11 * This program is free software; you can redistribute it and/or modify
 12 * it under the terms of the GNU General Public License version 2 as
 13 * published by the Free Software Foundation.
 14 */
 15
 16#include "skeleton.dtsi"
 17#include "exynos-syscon-restart.dtsi"
 18
 19/ {
 20	interrupt-parent = <&gic>;
 21
 22	aliases {
 23		serial0 = &serial_0;
 24		serial1 = &serial_1;
 25		serial2 = &serial_2;
 26		serial3 = &serial_3;
 27	};
 28
 29	chipid@10000000 {
 30		compatible = "samsung,exynos4210-chipid";
 31		reg = <0x10000000 0x100>;
 32	};
 33
 34	sromc@12250000 {
 35		compatible = "samsung,exynos-srom";
 36		reg = <0x12250000 0x14>;
 37	};
 38
 39	combiner: interrupt-controller@10440000 {
 40		compatible = "samsung,exynos4210-combiner";
 41		#interrupt-cells = <2>;
 42		interrupt-controller;
 43		samsung,combiner-nr = <32>;
 44		reg = <0x10440000 0x1000>;
 45		interrupts =	<0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
 46				<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
 47				<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
 48				<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
 49				<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
 50				<0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
 51				<0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
 52				<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
 53	};
 54
 55	gic: interrupt-controller@10481000 {
 56		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
 57		#interrupt-cells = <3>;
 58		interrupt-controller;
 59		reg =	<0x10481000 0x1000>,
 60			<0x10482000 0x1000>,
 61			<0x10484000 0x2000>,
 62			<0x10486000 0x2000>;
 63		interrupts = <1 9 0xf04>;
 64	};
 65
 66	serial_0: serial@12C00000 {
 67		compatible = "samsung,exynos4210-uart";
 68		reg = <0x12C00000 0x100>;
 69		interrupts = <0 51 0>;
 70	};
 71
 72	serial_1: serial@12C10000 {
 73		compatible = "samsung,exynos4210-uart";
 74		reg = <0x12C10000 0x100>;
 75		interrupts = <0 52 0>;
 76	};
 77
 78	serial_2: serial@12C20000 {
 79		compatible = "samsung,exynos4210-uart";
 80		reg = <0x12C20000 0x100>;
 81		interrupts = <0 53 0>;
 82	};
 83
 84	serial_3: serial@12C30000 {
 85		compatible = "samsung,exynos4210-uart";
 86		reg = <0x12C30000 0x100>;
 87		interrupts = <0 54 0>;
 88	};
 89
 90	rtc: rtc@101E0000 {
 91		compatible = "samsung,s3c6410-rtc";
 92		reg = <0x101E0000 0x100>;
 93		interrupts = <0 43 0>, <0 44 0>;
 94		status = "disabled";
 95	};
 96
 97	fimd: fimd@14400000 {
 98		compatible = "samsung,exynos5250-fimd";
 99		interrupt-parent = <&combiner>;
100		reg = <0x14400000 0x40000>;
101		interrupt-names = "fifo", "vsync", "lcd_sys";
102		interrupts = <18 4>, <18 5>, <18 6>;
103		samsung,sysreg = <&sysreg_system_controller>;
104		status = "disabled";
105	};
106
107	dp: dp-controller@145B0000 {
108		compatible = "samsung,exynos5-dp";
109		reg = <0x145B0000 0x1000>;
110		interrupts = <10 3>;
111		interrupt-parent = <&combiner>;
112		#address-cells = <1>;
113		#size-cells = <0>;
114		status = "disabled";
115	};
116};