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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for PowerMac Z85c30 based ESCC cell found in the
4 * "macio" ASICs of various PowerMac models
5 *
6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
7 *
8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
9 * and drivers/serial/sunzilog.c by David S. Miller
10 *
11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
12 * adapted special tweaks needed for us. I don't think it's worth
13 * merging back those though. The DMA code still has to get in
14 * and once done, I expect that driver to remain fairly stable in
15 * the long term, unless we change the driver model again...
16 *
17 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
18 * - Enable BREAK interrupt
19 * - Add support for sysreq
20 *
21 * TODO: - Add DMA support
22 * - Defer port shutdown to a few seconds after close
23 * - maybe put something right into uap->clk_divisor
24 */
25
26#undef DEBUG
27#undef USE_CTRL_O_SYSRQ
28
29#include <linux/module.h>
30#include <linux/tty.h>
31
32#include <linux/tty_flip.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/fcntl.h>
36#include <linux/mm.h>
37#include <linux/kernel.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/adb.h>
42#include <linux/pmu.h>
43#include <linux/bitops.h>
44#include <linux/sysrq.h>
45#include <linux/mutex.h>
46#include <linux/of_address.h>
47#include <linux/of_irq.h>
48#include <asm/sections.h>
49#include <linux/io.h>
50#include <asm/irq.h>
51
52#ifdef CONFIG_PPC_PMAC
53#include <asm/machdep.h>
54#include <asm/pmac_feature.h>
55#include <asm/macio.h>
56#else
57#include <linux/platform_device.h>
58#define of_machine_is_compatible(x) (0)
59#endif
60
61#include <linux/serial.h>
62#include <linux/serial_core.h>
63
64#include "pmac_zilog.h"
65
66MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
67MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
68MODULE_LICENSE("GPL");
69
70#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
71#define PMACZILOG_MAJOR TTY_MAJOR
72#define PMACZILOG_MINOR 64
73#define PMACZILOG_NAME "ttyS"
74#else
75#define PMACZILOG_MAJOR 204
76#define PMACZILOG_MINOR 192
77#define PMACZILOG_NAME "ttyPZ"
78#endif
79
80#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
81#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
82#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
83
84/*
85 * For the sake of early serial console, we can do a pre-probe
86 * (optional) of the ports at rather early boot time.
87 */
88static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
89static int pmz_ports_count;
90
91static struct uart_driver pmz_uart_reg = {
92 .owner = THIS_MODULE,
93 .driver_name = PMACZILOG_NAME,
94 .dev_name = PMACZILOG_NAME,
95 .major = PMACZILOG_MAJOR,
96 .minor = PMACZILOG_MINOR,
97};
98
99
100/*
101 * Load all registers to reprogram the port
102 * This function must only be called when the TX is not busy. The UART
103 * port lock must be held and local interrupts disabled.
104 */
105static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
106{
107 int i;
108
109 /* Let pending transmits finish. */
110 for (i = 0; i < 1000; i++) {
111 unsigned char stat = read_zsreg(uap, R1);
112 if (stat & ALL_SNT)
113 break;
114 udelay(100);
115 }
116
117 ZS_CLEARERR(uap);
118 zssync(uap);
119 ZS_CLEARFIFO(uap);
120 zssync(uap);
121 ZS_CLEARERR(uap);
122
123 /* Disable all interrupts. */
124 write_zsreg(uap, R1,
125 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
126
127 /* Set parity, sync config, stop bits, and clock divisor. */
128 write_zsreg(uap, R4, regs[R4]);
129
130 /* Set misc. TX/RX control bits. */
131 write_zsreg(uap, R10, regs[R10]);
132
133 /* Set TX/RX controls sans the enable bits. */
134 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
136
137 /* now set R7 "prime" on ESCC */
138 write_zsreg(uap, R15, regs[R15] | EN85C30);
139 write_zsreg(uap, R7, regs[R7P]);
140
141 /* make sure we use R7 "non-prime" on ESCC */
142 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
143
144 /* Synchronous mode config. */
145 write_zsreg(uap, R6, regs[R6]);
146 write_zsreg(uap, R7, regs[R7]);
147
148 /* Disable baud generator. */
149 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
150
151 /* Clock mode control. */
152 write_zsreg(uap, R11, regs[R11]);
153
154 /* Lower and upper byte of baud rate generator divisor. */
155 write_zsreg(uap, R12, regs[R12]);
156 write_zsreg(uap, R13, regs[R13]);
157
158 /* Now rewrite R14, with BRENAB (if set). */
159 write_zsreg(uap, R14, regs[R14]);
160
161 /* Reset external status interrupts. */
162 write_zsreg(uap, R0, RES_EXT_INT);
163 write_zsreg(uap, R0, RES_EXT_INT);
164
165 /* Rewrite R3/R5, this time without enables masked. */
166 write_zsreg(uap, R3, regs[R3]);
167 write_zsreg(uap, R5, regs[R5]);
168
169 /* Rewrite R1, this time without IRQ enabled masked. */
170 write_zsreg(uap, R1, regs[R1]);
171
172 /* Enable interrupts */
173 write_zsreg(uap, R9, regs[R9]);
174}
175
176/*
177 * We do like sunzilog to avoid disrupting pending Tx
178 * Reprogram the Zilog channel HW registers with the copies found in the
179 * software state struct. If the transmitter is busy, we defer this update
180 * until the next TX complete interrupt. Else, we do it right now.
181 *
182 * The UART port lock must be held and local interrupts disabled.
183 */
184static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
185{
186 if (!ZS_REGS_HELD(uap)) {
187 if (ZS_TX_ACTIVE(uap)) {
188 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
189 } else {
190 pmz_debug("pmz: maybe_update_regs: updating\n");
191 pmz_load_zsregs(uap, uap->curregs);
192 }
193 }
194}
195
196static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
197{
198 if (enable) {
199 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
200 if (!ZS_IS_EXTCLK(uap))
201 uap->curregs[1] |= EXT_INT_ENAB;
202 } else {
203 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
204 }
205 write_zsreg(uap, R1, uap->curregs[1]);
206}
207
208static bool pmz_receive_chars(struct uart_pmac_port *uap)
209 __must_hold(&uap->port.lock)
210{
211 struct tty_port *port;
212 unsigned char ch, r1, drop, flag;
213 int loops = 0;
214
215 /* Sanity check, make sure the old bug is no longer happening */
216 if (uap->port.state == NULL) {
217 WARN_ON(1);
218 (void)read_zsdata(uap);
219 return false;
220 }
221 port = &uap->port.state->port;
222
223 while (1) {
224 drop = 0;
225
226 r1 = read_zsreg(uap, R1);
227 ch = read_zsdata(uap);
228
229 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
230 write_zsreg(uap, R0, ERR_RES);
231 zssync(uap);
232 }
233
234 ch &= uap->parity_mask;
235 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
236 uap->flags &= ~PMACZILOG_FLAG_BREAK;
237 }
238
239#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
240#ifdef USE_CTRL_O_SYSRQ
241 /* Handle the SysRq ^O Hack */
242 if (ch == '\x0f') {
243 uap->port.sysrq = jiffies + HZ*5;
244 goto next_char;
245 }
246#endif /* USE_CTRL_O_SYSRQ */
247 if (uap->port.sysrq) {
248 int swallow;
249 uart_port_unlock(&uap->port);
250 swallow = uart_handle_sysrq_char(&uap->port, ch);
251 uart_port_lock(&uap->port);
252 if (swallow)
253 goto next_char;
254 }
255#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
256
257 /* A real serial line, record the character and status. */
258 if (drop)
259 goto next_char;
260
261 flag = TTY_NORMAL;
262 uap->port.icount.rx++;
263
264 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
265 if (r1 & BRK_ABRT) {
266 pmz_debug("pmz: got break !\n");
267 r1 &= ~(PAR_ERR | CRC_ERR);
268 uap->port.icount.brk++;
269 if (uart_handle_break(&uap->port))
270 goto next_char;
271 }
272 else if (r1 & PAR_ERR)
273 uap->port.icount.parity++;
274 else if (r1 & CRC_ERR)
275 uap->port.icount.frame++;
276 if (r1 & Rx_OVR)
277 uap->port.icount.overrun++;
278 r1 &= uap->port.read_status_mask;
279 if (r1 & BRK_ABRT)
280 flag = TTY_BREAK;
281 else if (r1 & PAR_ERR)
282 flag = TTY_PARITY;
283 else if (r1 & CRC_ERR)
284 flag = TTY_FRAME;
285 }
286
287 if (uap->port.ignore_status_mask == 0xff ||
288 (r1 & uap->port.ignore_status_mask) == 0) {
289 tty_insert_flip_char(port, ch, flag);
290 }
291 if (r1 & Rx_OVR)
292 tty_insert_flip_char(port, 0, TTY_OVERRUN);
293 next_char:
294 /* We can get stuck in an infinite loop getting char 0 when the
295 * line is in a wrong HW state, we break that here.
296 * When that happens, I disable the receive side of the driver.
297 * Note that what I've been experiencing is a real irq loop where
298 * I'm getting flooded regardless of the actual port speed.
299 * Something strange is going on with the HW
300 */
301 if ((++loops) > 1000)
302 goto flood;
303 ch = read_zsreg(uap, R0);
304 if (!(ch & Rx_CH_AV))
305 break;
306 }
307
308 return true;
309 flood:
310 pmz_interrupt_control(uap, 0);
311 pmz_error("pmz: rx irq flood !\n");
312 return true;
313}
314
315static void pmz_status_handle(struct uart_pmac_port *uap)
316{
317 unsigned char status;
318
319 status = read_zsreg(uap, R0);
320 write_zsreg(uap, R0, RES_EXT_INT);
321 zssync(uap);
322
323 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
324 if (status & SYNC_HUNT)
325 uap->port.icount.dsr++;
326
327 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
328 * But it does not tell us which bit has changed, we have to keep
329 * track of this ourselves.
330 * The CTS input is inverted for some reason. -- paulus
331 */
332 if ((status ^ uap->prev_status) & DCD)
333 uart_handle_dcd_change(&uap->port,
334 (status & DCD));
335 if ((status ^ uap->prev_status) & CTS)
336 uart_handle_cts_change(&uap->port,
337 !(status & CTS));
338
339 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
340 }
341
342 if (status & BRK_ABRT)
343 uap->flags |= PMACZILOG_FLAG_BREAK;
344
345 uap->prev_status = status;
346}
347
348static void pmz_transmit_chars(struct uart_pmac_port *uap)
349{
350 struct circ_buf *xmit;
351
352 if (ZS_IS_CONS(uap)) {
353 unsigned char status = read_zsreg(uap, R0);
354
355 /* TX still busy? Just wait for the next TX done interrupt.
356 *
357 * It can occur because of how we do serial console writes. It would
358 * be nice to transmit console writes just like we normally would for
359 * a TTY line. (ie. buffered and TX interrupt driven). That is not
360 * easy because console writes cannot sleep. One solution might be
361 * to poll on enough port->xmit space becoming free. -DaveM
362 */
363 if (!(status & Tx_BUF_EMP))
364 return;
365 }
366
367 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
368
369 if (ZS_REGS_HELD(uap)) {
370 pmz_load_zsregs(uap, uap->curregs);
371 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
372 }
373
374 if (ZS_TX_STOPPED(uap)) {
375 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
376 goto ack_tx_int;
377 }
378
379 /* Under some circumstances, we see interrupts reported for
380 * a closed channel. The interrupt mask in R1 is clear, but
381 * R3 still signals the interrupts and we see them when taking
382 * an interrupt for the other channel (this could be a qemu
383 * bug but since the ESCC doc doesn't specify precsiely whether
384 * R3 interrup status bits are masked by R1 interrupt enable
385 * bits, better safe than sorry). --BenH.
386 */
387 if (!ZS_IS_OPEN(uap))
388 goto ack_tx_int;
389
390 if (uap->port.x_char) {
391 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
392 write_zsdata(uap, uap->port.x_char);
393 zssync(uap);
394 uap->port.icount.tx++;
395 uap->port.x_char = 0;
396 return;
397 }
398
399 if (uap->port.state == NULL)
400 goto ack_tx_int;
401 xmit = &uap->port.state->xmit;
402 if (uart_circ_empty(xmit)) {
403 uart_write_wakeup(&uap->port);
404 goto ack_tx_int;
405 }
406 if (uart_tx_stopped(&uap->port))
407 goto ack_tx_int;
408
409 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
410 write_zsdata(uap, xmit->buf[xmit->tail]);
411 zssync(uap);
412
413 uart_xmit_advance(&uap->port, 1);
414
415 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
416 uart_write_wakeup(&uap->port);
417
418 return;
419
420ack_tx_int:
421 write_zsreg(uap, R0, RES_Tx_P);
422 zssync(uap);
423}
424
425/* Hrm... we register that twice, fixme later.... */
426static irqreturn_t pmz_interrupt(int irq, void *dev_id)
427{
428 struct uart_pmac_port *uap = dev_id;
429 struct uart_pmac_port *uap_a;
430 struct uart_pmac_port *uap_b;
431 int rc = IRQ_NONE;
432 bool push;
433 u8 r3;
434
435 uap_a = pmz_get_port_A(uap);
436 uap_b = uap_a->mate;
437
438 uart_port_lock(&uap_a->port);
439 r3 = read_zsreg(uap_a, R3);
440
441 /* Channel A */
442 push = false;
443 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
444 if (!ZS_IS_OPEN(uap_a)) {
445 pmz_debug("ChanA interrupt while not open !\n");
446 goto skip_a;
447 }
448 write_zsreg(uap_a, R0, RES_H_IUS);
449 zssync(uap_a);
450 if (r3 & CHAEXT)
451 pmz_status_handle(uap_a);
452 if (r3 & CHARxIP)
453 push = pmz_receive_chars(uap_a);
454 if (r3 & CHATxIP)
455 pmz_transmit_chars(uap_a);
456 rc = IRQ_HANDLED;
457 }
458 skip_a:
459 uart_port_unlock(&uap_a->port);
460 if (push)
461 tty_flip_buffer_push(&uap->port.state->port);
462
463 if (!uap_b)
464 goto out;
465
466 uart_port_lock(&uap_b->port);
467 push = false;
468 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
469 if (!ZS_IS_OPEN(uap_b)) {
470 pmz_debug("ChanB interrupt while not open !\n");
471 goto skip_b;
472 }
473 write_zsreg(uap_b, R0, RES_H_IUS);
474 zssync(uap_b);
475 if (r3 & CHBEXT)
476 pmz_status_handle(uap_b);
477 if (r3 & CHBRxIP)
478 push = pmz_receive_chars(uap_b);
479 if (r3 & CHBTxIP)
480 pmz_transmit_chars(uap_b);
481 rc = IRQ_HANDLED;
482 }
483 skip_b:
484 uart_port_unlock(&uap_b->port);
485 if (push)
486 tty_flip_buffer_push(&uap->port.state->port);
487
488 out:
489 return rc;
490}
491
492/*
493 * Peek the status register, lock not held by caller
494 */
495static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
496{
497 unsigned long flags;
498 u8 status;
499
500 uart_port_lock_irqsave(&uap->port, &flags);
501 status = read_zsreg(uap, R0);
502 uart_port_unlock_irqrestore(&uap->port, flags);
503
504 return status;
505}
506
507/*
508 * Check if transmitter is empty
509 * The port lock is not held.
510 */
511static unsigned int pmz_tx_empty(struct uart_port *port)
512{
513 unsigned char status;
514
515 status = pmz_peek_status(to_pmz(port));
516 if (status & Tx_BUF_EMP)
517 return TIOCSER_TEMT;
518 return 0;
519}
520
521/*
522 * Set Modem Control (RTS & DTR) bits
523 * The port lock is held and interrupts are disabled.
524 * Note: Shall we really filter out RTS on external ports or
525 * should that be dealt at higher level only ?
526 */
527static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
528{
529 struct uart_pmac_port *uap = to_pmz(port);
530 unsigned char set_bits, clear_bits;
531
532 /* Do nothing for irda for now... */
533 if (ZS_IS_IRDA(uap))
534 return;
535 /* We get called during boot with a port not up yet */
536 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
537 return;
538
539 set_bits = clear_bits = 0;
540
541 if (ZS_IS_INTMODEM(uap)) {
542 if (mctrl & TIOCM_RTS)
543 set_bits |= RTS;
544 else
545 clear_bits |= RTS;
546 }
547 if (mctrl & TIOCM_DTR)
548 set_bits |= DTR;
549 else
550 clear_bits |= DTR;
551
552 /* NOTE: Not subject to 'transmitter active' rule. */
553 uap->curregs[R5] |= set_bits;
554 uap->curregs[R5] &= ~clear_bits;
555
556 write_zsreg(uap, R5, uap->curregs[R5]);
557 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
558 set_bits, clear_bits, uap->curregs[R5]);
559 zssync(uap);
560}
561
562/*
563 * Get Modem Control bits (only the input ones, the core will
564 * or that with a cached value of the control ones)
565 * The port lock is held and interrupts are disabled.
566 */
567static unsigned int pmz_get_mctrl(struct uart_port *port)
568{
569 struct uart_pmac_port *uap = to_pmz(port);
570 unsigned char status;
571 unsigned int ret;
572
573 status = read_zsreg(uap, R0);
574
575 ret = 0;
576 if (status & DCD)
577 ret |= TIOCM_CAR;
578 if (status & SYNC_HUNT)
579 ret |= TIOCM_DSR;
580 if (!(status & CTS))
581 ret |= TIOCM_CTS;
582
583 return ret;
584}
585
586/*
587 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
588 * though for DMA, we will have to do a bit more.
589 * The port lock is held and interrupts are disabled.
590 */
591static void pmz_stop_tx(struct uart_port *port)
592{
593 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
594}
595
596/*
597 * Kick the Tx side.
598 * The port lock is held and interrupts are disabled.
599 */
600static void pmz_start_tx(struct uart_port *port)
601{
602 struct uart_pmac_port *uap = to_pmz(port);
603 unsigned char status;
604
605 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
606 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
607
608 status = read_zsreg(uap, R0);
609
610 /* TX busy? Just wait for the TX done interrupt. */
611 if (!(status & Tx_BUF_EMP))
612 return;
613
614 /* Send the first character to jump-start the TX done
615 * IRQ sending engine.
616 */
617 if (port->x_char) {
618 write_zsdata(uap, port->x_char);
619 zssync(uap);
620 port->icount.tx++;
621 port->x_char = 0;
622 } else {
623 struct circ_buf *xmit = &port->state->xmit;
624
625 if (uart_circ_empty(xmit))
626 return;
627 write_zsdata(uap, xmit->buf[xmit->tail]);
628 zssync(uap);
629 uart_xmit_advance(port, 1);
630
631 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
632 uart_write_wakeup(&uap->port);
633 }
634}
635
636/*
637 * Stop Rx side, basically disable emitting of
638 * Rx interrupts on the port. We don't disable the rx
639 * side of the chip proper though
640 * The port lock is held.
641 */
642static void pmz_stop_rx(struct uart_port *port)
643{
644 struct uart_pmac_port *uap = to_pmz(port);
645
646 /* Disable all RX interrupts. */
647 uap->curregs[R1] &= ~RxINT_MASK;
648 pmz_maybe_update_regs(uap);
649}
650
651/*
652 * Enable modem status change interrupts
653 * The port lock is held.
654 */
655static void pmz_enable_ms(struct uart_port *port)
656{
657 struct uart_pmac_port *uap = to_pmz(port);
658 unsigned char new_reg;
659
660 if (ZS_IS_IRDA(uap))
661 return;
662 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
663 if (new_reg != uap->curregs[R15]) {
664 uap->curregs[R15] = new_reg;
665
666 /* NOTE: Not subject to 'transmitter active' rule. */
667 write_zsreg(uap, R15, uap->curregs[R15]);
668 }
669}
670
671/*
672 * Control break state emission
673 * The port lock is not held.
674 */
675static void pmz_break_ctl(struct uart_port *port, int break_state)
676{
677 struct uart_pmac_port *uap = to_pmz(port);
678 unsigned char set_bits, clear_bits, new_reg;
679 unsigned long flags;
680
681 set_bits = clear_bits = 0;
682
683 if (break_state)
684 set_bits |= SND_BRK;
685 else
686 clear_bits |= SND_BRK;
687
688 uart_port_lock_irqsave(port, &flags);
689
690 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
691 if (new_reg != uap->curregs[R5]) {
692 uap->curregs[R5] = new_reg;
693 write_zsreg(uap, R5, uap->curregs[R5]);
694 }
695
696 uart_port_unlock_irqrestore(port, flags);
697}
698
699#ifdef CONFIG_PPC_PMAC
700
701/*
702 * Turn power on or off to the SCC and associated stuff
703 * (port drivers, modem, IR port, etc.)
704 * Returns the number of milliseconds we should wait before
705 * trying to use the port.
706 */
707static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
708{
709 int delay = 0;
710 int rc;
711
712 if (state) {
713 rc = pmac_call_feature(
714 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
715 pmz_debug("port power on result: %d\n", rc);
716 if (ZS_IS_INTMODEM(uap)) {
717 rc = pmac_call_feature(
718 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
719 delay = 2500; /* wait for 2.5s before using */
720 pmz_debug("modem power result: %d\n", rc);
721 }
722 } else {
723 /* TODO: Make that depend on a timer, don't power down
724 * immediately
725 */
726 if (ZS_IS_INTMODEM(uap)) {
727 rc = pmac_call_feature(
728 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
729 pmz_debug("port power off result: %d\n", rc);
730 }
731 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
732 }
733 return delay;
734}
735
736#else
737
738static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
739{
740 return 0;
741}
742
743#endif /* !CONFIG_PPC_PMAC */
744
745/*
746 * FixZeroBug....Works around a bug in the SCC receiving channel.
747 * Inspired from Darwin code, 15 Sept. 2000 -DanM
748 *
749 * The following sequence prevents a problem that is seen with O'Hare ASICs
750 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
751 * at the input to the receiver becomes 'stuck' and locks up the receiver.
752 * This problem can occur as a result of a zero bit at the receiver input
753 * coincident with any of the following events:
754 *
755 * The SCC is initialized (hardware or software).
756 * A framing error is detected.
757 * The clocking option changes from synchronous or X1 asynchronous
758 * clocking to X16, X32, or X64 asynchronous clocking.
759 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
760 *
761 * This workaround attempts to recover from the lockup condition by placing
762 * the SCC in synchronous loopback mode with a fast clock before programming
763 * any of the asynchronous modes.
764 */
765static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
766{
767 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
768 zssync(uap);
769 udelay(10);
770 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
771 zssync(uap);
772
773 write_zsreg(uap, 4, X1CLK | MONSYNC);
774 write_zsreg(uap, 3, Rx8);
775 write_zsreg(uap, 5, Tx8 | RTS);
776 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
777 write_zsreg(uap, 11, RCBR | TCBR);
778 write_zsreg(uap, 12, 0);
779 write_zsreg(uap, 13, 0);
780 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
781 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
782 write_zsreg(uap, 3, Rx8 | RxENABLE);
783 write_zsreg(uap, 0, RES_EXT_INT);
784 write_zsreg(uap, 0, RES_EXT_INT);
785 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
786
787 /* The channel should be OK now, but it is probably receiving
788 * loopback garbage.
789 * Switch to asynchronous mode, disable the receiver,
790 * and discard everything in the receive buffer.
791 */
792 write_zsreg(uap, 9, NV);
793 write_zsreg(uap, 4, X16CLK | SB_MASK);
794 write_zsreg(uap, 3, Rx8);
795
796 while (read_zsreg(uap, 0) & Rx_CH_AV) {
797 (void)read_zsreg(uap, 8);
798 write_zsreg(uap, 0, RES_EXT_INT);
799 write_zsreg(uap, 0, ERR_RES);
800 }
801}
802
803/*
804 * Real startup routine, powers up the hardware and sets up
805 * the SCC. Returns a delay in ms where you need to wait before
806 * actually using the port, this is typically the internal modem
807 * powerup delay. This routine expect the lock to be taken.
808 */
809static int __pmz_startup(struct uart_pmac_port *uap)
810{
811 int pwr_delay = 0;
812
813 memset(&uap->curregs, 0, sizeof(uap->curregs));
814
815 /* Power up the SCC & underlying hardware (modem/irda) */
816 pwr_delay = pmz_set_scc_power(uap, 1);
817
818 /* Nice buggy HW ... */
819 pmz_fix_zero_bug_scc(uap);
820
821 /* Reset the channel */
822 uap->curregs[R9] = 0;
823 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
824 zssync(uap);
825 udelay(10);
826 write_zsreg(uap, 9, 0);
827 zssync(uap);
828
829 /* Clear the interrupt registers */
830 write_zsreg(uap, R1, 0);
831 write_zsreg(uap, R0, ERR_RES);
832 write_zsreg(uap, R0, ERR_RES);
833 write_zsreg(uap, R0, RES_H_IUS);
834 write_zsreg(uap, R0, RES_H_IUS);
835
836 /* Setup some valid baud rate */
837 uap->curregs[R4] = X16CLK | SB1;
838 uap->curregs[R3] = Rx8;
839 uap->curregs[R5] = Tx8 | RTS;
840 if (!ZS_IS_IRDA(uap))
841 uap->curregs[R5] |= DTR;
842 uap->curregs[R12] = 0;
843 uap->curregs[R13] = 0;
844 uap->curregs[R14] = BRENAB;
845
846 /* Clear handshaking, enable BREAK interrupts */
847 uap->curregs[R15] = BRKIE;
848
849 /* Master interrupt enable */
850 uap->curregs[R9] |= NV | MIE;
851
852 pmz_load_zsregs(uap, uap->curregs);
853
854 /* Enable receiver and transmitter. */
855 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
856 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
857
858 /* Remember status for DCD/CTS changes */
859 uap->prev_status = read_zsreg(uap, R0);
860
861 return pwr_delay;
862}
863
864static void pmz_irda_reset(struct uart_pmac_port *uap)
865{
866 unsigned long flags;
867
868 uart_port_lock_irqsave(&uap->port, &flags);
869 uap->curregs[R5] |= DTR;
870 write_zsreg(uap, R5, uap->curregs[R5]);
871 zssync(uap);
872 uart_port_unlock_irqrestore(&uap->port, flags);
873 msleep(110);
874
875 uart_port_lock_irqsave(&uap->port, &flags);
876 uap->curregs[R5] &= ~DTR;
877 write_zsreg(uap, R5, uap->curregs[R5]);
878 zssync(uap);
879 uart_port_unlock_irqrestore(&uap->port, flags);
880 msleep(10);
881}
882
883/*
884 * This is the "normal" startup routine, using the above one
885 * wrapped with the lock and doing a schedule delay
886 */
887static int pmz_startup(struct uart_port *port)
888{
889 struct uart_pmac_port *uap = to_pmz(port);
890 unsigned long flags;
891 int pwr_delay = 0;
892
893 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
894
895 /* A console is never powered down. Else, power up and
896 * initialize the chip
897 */
898 if (!ZS_IS_CONS(uap)) {
899 uart_port_lock_irqsave(port, &flags);
900 pwr_delay = __pmz_startup(uap);
901 uart_port_unlock_irqrestore(port, flags);
902 }
903 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
904 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
905 uap->irq_name, uap)) {
906 pmz_error("Unable to register zs interrupt handler.\n");
907 pmz_set_scc_power(uap, 0);
908 return -ENXIO;
909 }
910
911 /* Right now, we deal with delay by blocking here, I'll be
912 * smarter later on
913 */
914 if (pwr_delay != 0) {
915 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
916 msleep(pwr_delay);
917 }
918
919 /* IrDA reset is done now */
920 if (ZS_IS_IRDA(uap))
921 pmz_irda_reset(uap);
922
923 /* Enable interrupt requests for the channel */
924 uart_port_lock_irqsave(port, &flags);
925 pmz_interrupt_control(uap, 1);
926 uart_port_unlock_irqrestore(port, flags);
927
928 return 0;
929}
930
931static void pmz_shutdown(struct uart_port *port)
932{
933 struct uart_pmac_port *uap = to_pmz(port);
934 unsigned long flags;
935
936 uart_port_lock_irqsave(port, &flags);
937
938 /* Disable interrupt requests for the channel */
939 pmz_interrupt_control(uap, 0);
940
941 if (!ZS_IS_CONS(uap)) {
942 /* Disable receiver and transmitter */
943 uap->curregs[R3] &= ~RxENABLE;
944 uap->curregs[R5] &= ~TxENABLE;
945
946 /* Disable break assertion */
947 uap->curregs[R5] &= ~SND_BRK;
948 pmz_maybe_update_regs(uap);
949 }
950
951 uart_port_unlock_irqrestore(port, flags);
952
953 /* Release interrupt handler */
954 free_irq(uap->port.irq, uap);
955
956 uart_port_lock_irqsave(port, &flags);
957
958 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
959
960 if (!ZS_IS_CONS(uap))
961 pmz_set_scc_power(uap, 0); /* Shut the chip down */
962
963 uart_port_unlock_irqrestore(port, flags);
964}
965
966/* Shared by TTY driver and serial console setup. The port lock is held
967 * and local interrupts are disabled.
968 */
969static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
970 unsigned int iflag, unsigned long baud)
971{
972 int brg;
973
974 /* Switch to external clocking for IrDA high clock rates. That
975 * code could be re-used for Midi interfaces with different
976 * multipliers
977 */
978 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
979 uap->curregs[R4] = X1CLK;
980 uap->curregs[R11] = RCTRxCP | TCTRxCP;
981 uap->curregs[R14] = 0; /* BRG off */
982 uap->curregs[R12] = 0;
983 uap->curregs[R13] = 0;
984 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
985 } else {
986 switch (baud) {
987 case ZS_CLOCK/16: /* 230400 */
988 uap->curregs[R4] = X16CLK;
989 uap->curregs[R11] = 0;
990 uap->curregs[R14] = 0;
991 break;
992 case ZS_CLOCK/32: /* 115200 */
993 uap->curregs[R4] = X32CLK;
994 uap->curregs[R11] = 0;
995 uap->curregs[R14] = 0;
996 break;
997 default:
998 uap->curregs[R4] = X16CLK;
999 uap->curregs[R11] = TCBR | RCBR;
1000 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1001 uap->curregs[R12] = (brg & 255);
1002 uap->curregs[R13] = ((brg >> 8) & 255);
1003 uap->curregs[R14] = BRENAB;
1004 }
1005 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1006 }
1007
1008 /* Character size, stop bits, and parity. */
1009 uap->curregs[3] &= ~RxN_MASK;
1010 uap->curregs[5] &= ~TxN_MASK;
1011
1012 switch (cflag & CSIZE) {
1013 case CS5:
1014 uap->curregs[3] |= Rx5;
1015 uap->curregs[5] |= Tx5;
1016 uap->parity_mask = 0x1f;
1017 break;
1018 case CS6:
1019 uap->curregs[3] |= Rx6;
1020 uap->curregs[5] |= Tx6;
1021 uap->parity_mask = 0x3f;
1022 break;
1023 case CS7:
1024 uap->curregs[3] |= Rx7;
1025 uap->curregs[5] |= Tx7;
1026 uap->parity_mask = 0x7f;
1027 break;
1028 case CS8:
1029 default:
1030 uap->curregs[3] |= Rx8;
1031 uap->curregs[5] |= Tx8;
1032 uap->parity_mask = 0xff;
1033 break;
1034 }
1035 uap->curregs[4] &= ~(SB_MASK);
1036 if (cflag & CSTOPB)
1037 uap->curregs[4] |= SB2;
1038 else
1039 uap->curregs[4] |= SB1;
1040 if (cflag & PARENB)
1041 uap->curregs[4] |= PAR_ENAB;
1042 else
1043 uap->curregs[4] &= ~PAR_ENAB;
1044 if (!(cflag & PARODD))
1045 uap->curregs[4] |= PAR_EVEN;
1046 else
1047 uap->curregs[4] &= ~PAR_EVEN;
1048
1049 uap->port.read_status_mask = Rx_OVR;
1050 if (iflag & INPCK)
1051 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1052 if (iflag & (IGNBRK | BRKINT | PARMRK))
1053 uap->port.read_status_mask |= BRK_ABRT;
1054
1055 uap->port.ignore_status_mask = 0;
1056 if (iflag & IGNPAR)
1057 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1058 if (iflag & IGNBRK) {
1059 uap->port.ignore_status_mask |= BRK_ABRT;
1060 if (iflag & IGNPAR)
1061 uap->port.ignore_status_mask |= Rx_OVR;
1062 }
1063
1064 if ((cflag & CREAD) == 0)
1065 uap->port.ignore_status_mask = 0xff;
1066}
1067
1068
1069/*
1070 * Set the irda codec on the imac to the specified baud rate.
1071 */
1072static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1073{
1074 u8 cmdbyte;
1075 int t, version;
1076
1077 switch (*baud) {
1078 /* SIR modes */
1079 case 2400:
1080 cmdbyte = 0x53;
1081 break;
1082 case 4800:
1083 cmdbyte = 0x52;
1084 break;
1085 case 9600:
1086 cmdbyte = 0x51;
1087 break;
1088 case 19200:
1089 cmdbyte = 0x50;
1090 break;
1091 case 38400:
1092 cmdbyte = 0x4f;
1093 break;
1094 case 57600:
1095 cmdbyte = 0x4e;
1096 break;
1097 case 115200:
1098 cmdbyte = 0x4d;
1099 break;
1100 /* The FIR modes aren't really supported at this point, how
1101 * do we select the speed ? via the FCR on KeyLargo ?
1102 */
1103 case 1152000:
1104 cmdbyte = 0;
1105 break;
1106 case 4000000:
1107 cmdbyte = 0;
1108 break;
1109 default: /* 9600 */
1110 cmdbyte = 0x51;
1111 *baud = 9600;
1112 break;
1113 }
1114
1115 /* Wait for transmitter to drain */
1116 t = 10000;
1117 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1118 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1119 if (--t <= 0) {
1120 pmz_error("transmitter didn't drain\n");
1121 return;
1122 }
1123 udelay(10);
1124 }
1125
1126 /* Drain the receiver too */
1127 t = 100;
1128 (void)read_zsdata(uap);
1129 (void)read_zsdata(uap);
1130 (void)read_zsdata(uap);
1131 mdelay(10);
1132 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1133 read_zsdata(uap);
1134 mdelay(10);
1135 if (--t <= 0) {
1136 pmz_error("receiver didn't drain\n");
1137 return;
1138 }
1139 }
1140
1141 /* Switch to command mode */
1142 uap->curregs[R5] |= DTR;
1143 write_zsreg(uap, R5, uap->curregs[R5]);
1144 zssync(uap);
1145 mdelay(1);
1146
1147 /* Switch SCC to 19200 */
1148 pmz_convert_to_zs(uap, CS8, 0, 19200);
1149 pmz_load_zsregs(uap, uap->curregs);
1150 mdelay(1);
1151
1152 /* Write get_version command byte */
1153 write_zsdata(uap, 1);
1154 t = 5000;
1155 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1156 if (--t <= 0) {
1157 pmz_error("irda_setup timed out on get_version byte\n");
1158 goto out;
1159 }
1160 udelay(10);
1161 }
1162 version = read_zsdata(uap);
1163
1164 if (version < 4) {
1165 pmz_info("IrDA: dongle version %d not supported\n", version);
1166 goto out;
1167 }
1168
1169 /* Send speed mode */
1170 write_zsdata(uap, cmdbyte);
1171 t = 5000;
1172 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1173 if (--t <= 0) {
1174 pmz_error("irda_setup timed out on speed mode byte\n");
1175 goto out;
1176 }
1177 udelay(10);
1178 }
1179 t = read_zsdata(uap);
1180 if (t != cmdbyte)
1181 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1182
1183 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1184 *baud, version);
1185
1186 (void)read_zsdata(uap);
1187 (void)read_zsdata(uap);
1188 (void)read_zsdata(uap);
1189
1190 out:
1191 /* Switch back to data mode */
1192 uap->curregs[R5] &= ~DTR;
1193 write_zsreg(uap, R5, uap->curregs[R5]);
1194 zssync(uap);
1195
1196 (void)read_zsdata(uap);
1197 (void)read_zsdata(uap);
1198 (void)read_zsdata(uap);
1199}
1200
1201
1202static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1203 const struct ktermios *old)
1204{
1205 struct uart_pmac_port *uap = to_pmz(port);
1206 unsigned long baud;
1207
1208 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1209 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1210 * about the FIR mode and high speed modes. So these are unused. For
1211 * implementing proper support for these, we should probably add some
1212 * DMA as well, at least on the Rx side, which isn't a simple thing
1213 * at this point.
1214 */
1215 if (ZS_IS_IRDA(uap)) {
1216 /* Calc baud rate */
1217 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1218 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1219 /* Cet the irda codec to the right rate */
1220 pmz_irda_setup(uap, &baud);
1221 /* Set final baud rate */
1222 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1223 pmz_load_zsregs(uap, uap->curregs);
1224 zssync(uap);
1225 } else {
1226 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1227 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1228 /* Make sure modem status interrupts are correctly configured */
1229 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1230 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1231 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1232 } else {
1233 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1234 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1235 }
1236
1237 /* Load registers to the chip */
1238 pmz_maybe_update_regs(uap);
1239 }
1240 uart_update_timeout(port, termios->c_cflag, baud);
1241}
1242
1243/* The port lock is not held. */
1244static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1245 const struct ktermios *old)
1246{
1247 struct uart_pmac_port *uap = to_pmz(port);
1248 unsigned long flags;
1249
1250 uart_port_lock_irqsave(port, &flags);
1251
1252 /* Disable IRQs on the port */
1253 pmz_interrupt_control(uap, 0);
1254
1255 /* Setup new port configuration */
1256 __pmz_set_termios(port, termios, old);
1257
1258 /* Re-enable IRQs on the port */
1259 if (ZS_IS_OPEN(uap))
1260 pmz_interrupt_control(uap, 1);
1261
1262 uart_port_unlock_irqrestore(port, flags);
1263}
1264
1265static const char *pmz_type(struct uart_port *port)
1266{
1267 struct uart_pmac_port *uap = to_pmz(port);
1268
1269 if (ZS_IS_IRDA(uap))
1270 return "Z85c30 ESCC - Infrared port";
1271 else if (ZS_IS_INTMODEM(uap))
1272 return "Z85c30 ESCC - Internal modem";
1273 return "Z85c30 ESCC - Serial port";
1274}
1275
1276/* We do not request/release mappings of the registers here, this
1277 * happens at early serial probe time.
1278 */
1279static void pmz_release_port(struct uart_port *port)
1280{
1281}
1282
1283static int pmz_request_port(struct uart_port *port)
1284{
1285 return 0;
1286}
1287
1288/* These do not need to do anything interesting either. */
1289static void pmz_config_port(struct uart_port *port, int flags)
1290{
1291}
1292
1293/* We do not support letting the user mess with the divisor, IRQ, etc. */
1294static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1295{
1296 return -EINVAL;
1297}
1298
1299#ifdef CONFIG_CONSOLE_POLL
1300
1301static int pmz_poll_get_char(struct uart_port *port)
1302{
1303 struct uart_pmac_port *uap =
1304 container_of(port, struct uart_pmac_port, port);
1305 int tries = 2;
1306
1307 while (tries) {
1308 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
1309 return read_zsdata(uap);
1310 if (tries--)
1311 udelay(5);
1312 }
1313
1314 return NO_POLL_CHAR;
1315}
1316
1317static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1318{
1319 struct uart_pmac_port *uap =
1320 container_of(port, struct uart_pmac_port, port);
1321
1322 /* Wait for the transmit buffer to empty. */
1323 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1324 udelay(5);
1325 write_zsdata(uap, c);
1326}
1327
1328#endif /* CONFIG_CONSOLE_POLL */
1329
1330static const struct uart_ops pmz_pops = {
1331 .tx_empty = pmz_tx_empty,
1332 .set_mctrl = pmz_set_mctrl,
1333 .get_mctrl = pmz_get_mctrl,
1334 .stop_tx = pmz_stop_tx,
1335 .start_tx = pmz_start_tx,
1336 .stop_rx = pmz_stop_rx,
1337 .enable_ms = pmz_enable_ms,
1338 .break_ctl = pmz_break_ctl,
1339 .startup = pmz_startup,
1340 .shutdown = pmz_shutdown,
1341 .set_termios = pmz_set_termios,
1342 .type = pmz_type,
1343 .release_port = pmz_release_port,
1344 .request_port = pmz_request_port,
1345 .config_port = pmz_config_port,
1346 .verify_port = pmz_verify_port,
1347#ifdef CONFIG_CONSOLE_POLL
1348 .poll_get_char = pmz_poll_get_char,
1349 .poll_put_char = pmz_poll_put_char,
1350#endif
1351};
1352
1353#ifdef CONFIG_PPC_PMAC
1354
1355/*
1356 * Setup one port structure after probing, HW is down at this point,
1357 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1358 * register our console before uart_add_one_port() is called
1359 */
1360static int __init pmz_init_port(struct uart_pmac_port *uap)
1361{
1362 struct device_node *np = uap->node;
1363 const char *conn;
1364 const struct slot_names_prop {
1365 int count;
1366 char name[1];
1367 } *slots;
1368 int len;
1369 struct resource r_ports;
1370
1371 /*
1372 * Request & map chip registers
1373 */
1374 if (of_address_to_resource(np, 0, &r_ports))
1375 return -ENODEV;
1376 uap->port.mapbase = r_ports.start;
1377 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1378
1379 uap->control_reg = uap->port.membase;
1380 uap->data_reg = uap->control_reg + 0x10;
1381
1382 /*
1383 * Detect port type
1384 */
1385 if (of_device_is_compatible(np, "cobalt"))
1386 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1387 conn = of_get_property(np, "AAPL,connector", &len);
1388 if (conn && (strcmp(conn, "infrared") == 0))
1389 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1390 uap->port_type = PMAC_SCC_ASYNC;
1391 /* 1999 Powerbook G3 has slot-names property instead */
1392 slots = of_get_property(np, "slot-names", &len);
1393 if (slots && slots->count > 0) {
1394 if (strcmp(slots->name, "IrDA") == 0)
1395 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1396 else if (strcmp(slots->name, "Modem") == 0)
1397 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1398 }
1399 if (ZS_IS_IRDA(uap))
1400 uap->port_type = PMAC_SCC_IRDA;
1401 if (ZS_IS_INTMODEM(uap)) {
1402 struct device_node* i2c_modem =
1403 of_find_node_by_name(NULL, "i2c-modem");
1404 if (i2c_modem) {
1405 const char* mid =
1406 of_get_property(i2c_modem, "modem-id", NULL);
1407 if (mid) switch(*mid) {
1408 case 0x04 :
1409 case 0x05 :
1410 case 0x07 :
1411 case 0x08 :
1412 case 0x0b :
1413 case 0x0c :
1414 uap->port_type = PMAC_SCC_I2S1;
1415 }
1416 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1417 mid ? (*mid) : 0);
1418 of_node_put(i2c_modem);
1419 } else {
1420 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1421 }
1422 }
1423
1424 /*
1425 * Init remaining bits of "port" structure
1426 */
1427 uap->port.iotype = UPIO_MEM;
1428 uap->port.irq = irq_of_parse_and_map(np, 0);
1429 uap->port.uartclk = ZS_CLOCK;
1430 uap->port.fifosize = 1;
1431 uap->port.ops = &pmz_pops;
1432 uap->port.type = PORT_PMAC_ZILOG;
1433 uap->port.flags = 0;
1434
1435 /*
1436 * Fixup for the port on Gatwick for which the device-tree has
1437 * missing interrupts. Normally, the macio_dev would contain
1438 * fixed up interrupt info, but we use the device-tree directly
1439 * here due to early probing so we need the fixup too.
1440 */
1441 if (uap->port.irq == 0 &&
1442 np->parent && np->parent->parent &&
1443 of_device_is_compatible(np->parent->parent, "gatwick")) {
1444 /* IRQs on gatwick are offset by 64 */
1445 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1446 }
1447
1448 /* Setup some valid baud rate information in the register
1449 * shadows so we don't write crap there before baud rate is
1450 * first initialized.
1451 */
1452 pmz_convert_to_zs(uap, CS8, 0, 9600);
1453
1454 return 0;
1455}
1456
1457/*
1458 * Get rid of a port on module removal
1459 */
1460static void pmz_dispose_port(struct uart_pmac_port *uap)
1461{
1462 struct device_node *np;
1463
1464 np = uap->node;
1465 iounmap(uap->control_reg);
1466 uap->node = NULL;
1467 of_node_put(np);
1468 memset(uap, 0, sizeof(struct uart_pmac_port));
1469}
1470
1471/*
1472 * Called upon match with an escc node in the device-tree.
1473 */
1474static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1475{
1476 struct uart_pmac_port *uap;
1477 int i;
1478
1479 /* Iterate the pmz_ports array to find a matching entry
1480 */
1481 for (i = 0; i < MAX_ZS_PORTS; i++)
1482 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1483 break;
1484 if (i >= MAX_ZS_PORTS)
1485 return -ENODEV;
1486
1487
1488 uap = &pmz_ports[i];
1489 uap->dev = mdev;
1490 uap->port.dev = &mdev->ofdev.dev;
1491 dev_set_drvdata(&mdev->ofdev.dev, uap);
1492
1493 /* We still activate the port even when failing to request resources
1494 * to work around bugs in ancient Apple device-trees
1495 */
1496 if (macio_request_resources(uap->dev, "pmac_zilog"))
1497 printk(KERN_WARNING "%pOFn: Failed to request resource"
1498 ", port still active\n",
1499 uap->node);
1500 else
1501 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1502
1503 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1504}
1505
1506/*
1507 * That one should not be called, macio isn't really a hotswap device,
1508 * we don't expect one of those serial ports to go away...
1509 */
1510static int pmz_detach(struct macio_dev *mdev)
1511{
1512 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1513
1514 if (!uap)
1515 return -ENODEV;
1516
1517 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1518
1519 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1520 macio_release_resources(uap->dev);
1521 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1522 }
1523 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1524 uap->dev = NULL;
1525 uap->port.dev = NULL;
1526
1527 return 0;
1528}
1529
1530
1531static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1532{
1533 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1534
1535 if (uap == NULL) {
1536 printk("HRM... pmz_suspend with NULL uap\n");
1537 return 0;
1538 }
1539
1540 uart_suspend_port(&pmz_uart_reg, &uap->port);
1541
1542 return 0;
1543}
1544
1545
1546static int pmz_resume(struct macio_dev *mdev)
1547{
1548 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1549
1550 if (uap == NULL)
1551 return 0;
1552
1553 uart_resume_port(&pmz_uart_reg, &uap->port);
1554
1555 return 0;
1556}
1557
1558/*
1559 * Probe all ports in the system and build the ports array, we register
1560 * with the serial layer later, so we get a proper struct device which
1561 * allows the tty to attach properly. This is later than it used to be
1562 * but the tty layer really wants it that way.
1563 */
1564static int __init pmz_probe(void)
1565{
1566 struct device_node *node_p, *node_a, *node_b, *np;
1567 int count = 0;
1568 int rc;
1569
1570 /*
1571 * Find all escc chips in the system
1572 */
1573 for_each_node_by_name(node_p, "escc") {
1574 /*
1575 * First get channel A/B node pointers
1576 *
1577 * TODO: Add routines with proper locking to do that...
1578 */
1579 node_a = node_b = NULL;
1580 for_each_child_of_node(node_p, np) {
1581 if (of_node_name_prefix(np, "ch-a"))
1582 node_a = of_node_get(np);
1583 else if (of_node_name_prefix(np, "ch-b"))
1584 node_b = of_node_get(np);
1585 }
1586 if (!node_a && !node_b) {
1587 of_node_put(node_a);
1588 of_node_put(node_b);
1589 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",
1590 (!node_a) ? 'a' : 'b', node_p);
1591 continue;
1592 }
1593
1594 /*
1595 * Fill basic fields in the port structures
1596 */
1597 if (node_b != NULL) {
1598 pmz_ports[count].mate = &pmz_ports[count+1];
1599 pmz_ports[count+1].mate = &pmz_ports[count];
1600 }
1601 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1602 pmz_ports[count].node = node_a;
1603 pmz_ports[count+1].node = node_b;
1604 pmz_ports[count].port.line = count;
1605 pmz_ports[count+1].port.line = count+1;
1606
1607 /*
1608 * Setup the ports for real
1609 */
1610 rc = pmz_init_port(&pmz_ports[count]);
1611 if (rc == 0 && node_b != NULL)
1612 rc = pmz_init_port(&pmz_ports[count+1]);
1613 if (rc != 0) {
1614 of_node_put(node_a);
1615 of_node_put(node_b);
1616 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1617 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1618 continue;
1619 }
1620 count += 2;
1621 }
1622 pmz_ports_count = count;
1623
1624 return 0;
1625}
1626
1627#else
1628
1629/* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware
1630 * tree to obtain the device_nodes needed to start the console before the
1631 * macio driver. On Macs without OpenFirmware, global platform_devices take
1632 * the place of those device_nodes.
1633 */
1634extern struct platform_device scc_a_pdev, scc_b_pdev;
1635
1636static int __init pmz_init_port(struct uart_pmac_port *uap)
1637{
1638 struct resource *r_ports;
1639 int irq;
1640
1641 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1642 if (!r_ports)
1643 return -ENODEV;
1644
1645 irq = platform_get_irq(uap->pdev, 0);
1646 if (irq < 0)
1647 return irq;
1648
1649 uap->port.mapbase = r_ports->start;
1650 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1651 uap->port.iotype = UPIO_MEM;
1652 uap->port.irq = irq;
1653 uap->port.uartclk = ZS_CLOCK;
1654 uap->port.fifosize = 1;
1655 uap->port.ops = &pmz_pops;
1656 uap->port.type = PORT_PMAC_ZILOG;
1657 uap->port.flags = 0;
1658
1659 uap->control_reg = uap->port.membase;
1660 uap->data_reg = uap->control_reg + 4;
1661 uap->port_type = 0;
1662 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE);
1663
1664 pmz_convert_to_zs(uap, CS8, 0, 9600);
1665
1666 return 0;
1667}
1668
1669static int __init pmz_probe(void)
1670{
1671 int err;
1672
1673 pmz_ports_count = 0;
1674
1675 pmz_ports[0].port.line = 0;
1676 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1677 pmz_ports[0].pdev = &scc_a_pdev;
1678 err = pmz_init_port(&pmz_ports[0]);
1679 if (err)
1680 return err;
1681 pmz_ports_count++;
1682
1683 pmz_ports[0].mate = &pmz_ports[1];
1684 pmz_ports[1].mate = &pmz_ports[0];
1685 pmz_ports[1].port.line = 1;
1686 pmz_ports[1].flags = 0;
1687 pmz_ports[1].pdev = &scc_b_pdev;
1688 err = pmz_init_port(&pmz_ports[1]);
1689 if (err)
1690 return err;
1691 pmz_ports_count++;
1692
1693 return 0;
1694}
1695
1696static void pmz_dispose_port(struct uart_pmac_port *uap)
1697{
1698 memset(uap, 0, sizeof(struct uart_pmac_port));
1699}
1700
1701static int __init pmz_attach(struct platform_device *pdev)
1702{
1703 struct uart_pmac_port *uap;
1704 int i;
1705
1706 /* Iterate the pmz_ports array to find a matching entry */
1707 for (i = 0; i < pmz_ports_count; i++)
1708 if (pmz_ports[i].pdev == pdev)
1709 break;
1710 if (i >= pmz_ports_count)
1711 return -ENODEV;
1712
1713 uap = &pmz_ports[i];
1714 uap->port.dev = &pdev->dev;
1715 platform_set_drvdata(pdev, uap);
1716
1717 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1718}
1719
1720static int __exit pmz_detach(struct platform_device *pdev)
1721{
1722 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1723
1724 if (!uap)
1725 return -ENODEV;
1726
1727 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1728
1729 uap->port.dev = NULL;
1730
1731 return 0;
1732}
1733
1734#endif /* !CONFIG_PPC_PMAC */
1735
1736#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1737
1738static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1739static int __init pmz_console_setup(struct console *co, char *options);
1740
1741static struct console pmz_console = {
1742 .name = PMACZILOG_NAME,
1743 .write = pmz_console_write,
1744 .device = uart_console_device,
1745 .setup = pmz_console_setup,
1746 .flags = CON_PRINTBUFFER,
1747 .index = -1,
1748 .data = &pmz_uart_reg,
1749};
1750
1751#define PMACZILOG_CONSOLE &pmz_console
1752#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1753#define PMACZILOG_CONSOLE (NULL)
1754#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1755
1756/*
1757 * Register the driver, console driver and ports with the serial
1758 * core
1759 */
1760static int __init pmz_register(void)
1761{
1762 pmz_uart_reg.nr = pmz_ports_count;
1763 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1764
1765 /*
1766 * Register this driver with the serial core
1767 */
1768 return uart_register_driver(&pmz_uart_reg);
1769}
1770
1771#ifdef CONFIG_PPC_PMAC
1772
1773static const struct of_device_id pmz_match[] =
1774{
1775 {
1776 .name = "ch-a",
1777 },
1778 {
1779 .name = "ch-b",
1780 },
1781 {},
1782};
1783MODULE_DEVICE_TABLE (of, pmz_match);
1784
1785static struct macio_driver pmz_driver = {
1786 .driver = {
1787 .name = "pmac_zilog",
1788 .owner = THIS_MODULE,
1789 .of_match_table = pmz_match,
1790 },
1791 .probe = pmz_attach,
1792 .remove = pmz_detach,
1793 .suspend = pmz_suspend,
1794 .resume = pmz_resume,
1795};
1796
1797#else
1798
1799static struct platform_driver pmz_driver = {
1800 .remove = __exit_p(pmz_detach),
1801 .driver = {
1802 .name = "scc",
1803 },
1804};
1805
1806#endif /* !CONFIG_PPC_PMAC */
1807
1808static int __init init_pmz(void)
1809{
1810 int rc, i;
1811
1812 /*
1813 * First, we need to do a direct OF-based probe pass. We
1814 * do that because we want serial console up before the
1815 * macio stuffs calls us back, and since that makes it
1816 * easier to pass the proper number of channels to
1817 * uart_register_driver()
1818 */
1819 if (pmz_ports_count == 0)
1820 pmz_probe();
1821
1822 /*
1823 * Bail early if no port found
1824 */
1825 if (pmz_ports_count == 0)
1826 return -ENODEV;
1827
1828 /*
1829 * Now we register with the serial layer
1830 */
1831 rc = pmz_register();
1832 if (rc) {
1833 printk(KERN_ERR
1834 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1835 "pmac_zilog: Did another serial driver already claim the minors?\n");
1836 /* effectively "pmz_unprobe()" */
1837 for (i=0; i < pmz_ports_count; i++)
1838 pmz_dispose_port(&pmz_ports[i]);
1839 return rc;
1840 }
1841
1842 /*
1843 * Then we register the macio driver itself
1844 */
1845#ifdef CONFIG_PPC_PMAC
1846 return macio_register_driver(&pmz_driver);
1847#else
1848 return platform_driver_probe(&pmz_driver, pmz_attach);
1849#endif
1850}
1851
1852static void __exit exit_pmz(void)
1853{
1854 int i;
1855
1856#ifdef CONFIG_PPC_PMAC
1857 /* Get rid of macio-driver (detach from macio) */
1858 macio_unregister_driver(&pmz_driver);
1859#else
1860 platform_driver_unregister(&pmz_driver);
1861#endif
1862
1863 for (i = 0; i < pmz_ports_count; i++) {
1864 struct uart_pmac_port *uport = &pmz_ports[i];
1865#ifdef CONFIG_PPC_PMAC
1866 if (uport->node != NULL)
1867 pmz_dispose_port(uport);
1868#else
1869 if (uport->pdev != NULL)
1870 pmz_dispose_port(uport);
1871#endif
1872 }
1873 /* Unregister UART driver */
1874 uart_unregister_driver(&pmz_uart_reg);
1875}
1876
1877#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1878
1879static void pmz_console_putchar(struct uart_port *port, unsigned char ch)
1880{
1881 struct uart_pmac_port *uap =
1882 container_of(port, struct uart_pmac_port, port);
1883
1884 /* Wait for the transmit buffer to empty. */
1885 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1886 udelay(5);
1887 write_zsdata(uap, ch);
1888}
1889
1890/*
1891 * Print a string to the serial port trying not to disturb
1892 * any possible real use of the port...
1893 */
1894static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1895{
1896 struct uart_pmac_port *uap = &pmz_ports[con->index];
1897 unsigned long flags;
1898
1899 uart_port_lock_irqsave(&uap->port, &flags);
1900
1901 /* Turn of interrupts and enable the transmitter. */
1902 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1903 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1904
1905 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1906
1907 /* Restore the values in the registers. */
1908 write_zsreg(uap, R1, uap->curregs[1]);
1909 /* Don't disable the transmitter. */
1910
1911 uart_port_unlock_irqrestore(&uap->port, flags);
1912}
1913
1914/*
1915 * Setup the serial console
1916 */
1917static int __init pmz_console_setup(struct console *co, char *options)
1918{
1919 struct uart_pmac_port *uap;
1920 struct uart_port *port;
1921 int baud = 38400;
1922 int bits = 8;
1923 int parity = 'n';
1924 int flow = 'n';
1925 unsigned long pwr_delay;
1926
1927 /*
1928 * XServe's default to 57600 bps
1929 */
1930 if (of_machine_is_compatible("RackMac1,1")
1931 || of_machine_is_compatible("RackMac1,2")
1932 || of_machine_is_compatible("MacRISC4"))
1933 baud = 57600;
1934
1935 /*
1936 * Check whether an invalid uart number has been specified, and
1937 * if so, search for the first available port that does have
1938 * console support.
1939 */
1940 if (co->index >= pmz_ports_count)
1941 co->index = 0;
1942 uap = &pmz_ports[co->index];
1943#ifdef CONFIG_PPC_PMAC
1944 if (uap->node == NULL)
1945 return -ENODEV;
1946#else
1947 if (uap->pdev == NULL)
1948 return -ENODEV;
1949#endif
1950 port = &uap->port;
1951
1952 /*
1953 * Mark port as beeing a console
1954 */
1955 uap->flags |= PMACZILOG_FLAG_IS_CONS;
1956
1957 /*
1958 * Temporary fix for uart layer who didn't setup the spinlock yet
1959 */
1960 spin_lock_init(&port->lock);
1961
1962 /*
1963 * Enable the hardware
1964 */
1965 pwr_delay = __pmz_startup(uap);
1966 if (pwr_delay)
1967 mdelay(pwr_delay);
1968
1969 if (options)
1970 uart_parse_options(options, &baud, &parity, &bits, &flow);
1971
1972 return uart_set_options(port, co, baud, parity, bits, flow);
1973}
1974
1975static int __init pmz_console_init(void)
1976{
1977 /* Probe ports */
1978 pmz_probe();
1979
1980 if (pmz_ports_count == 0)
1981 return -ENODEV;
1982
1983 /* TODO: Autoprobe console based on OF */
1984 /* pmz_console.index = i; */
1985 register_console(&pmz_console);
1986
1987 return 0;
1988
1989}
1990console_initcall(pmz_console_init);
1991#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1992
1993module_init(init_pmz);
1994module_exit(exit_pmz);
1/*
2 * Driver for PowerMac Z85c30 based ESCC cell found in the
3 * "macio" ASICs of various PowerMac models
4 *
5 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
6 *
7 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
8 * and drivers/serial/sunzilog.c by David S. Miller
9 *
10 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
11 * adapted special tweaks needed for us. I don't think it's worth
12 * merging back those though. The DMA code still has to get in
13 * and once done, I expect that driver to remain fairly stable in
14 * the long term, unless we change the driver model again...
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 *
30 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
31 * - Enable BREAK interrupt
32 * - Add support for sysreq
33 *
34 * TODO: - Add DMA support
35 * - Defer port shutdown to a few seconds after close
36 * - maybe put something right into uap->clk_divisor
37 */
38
39#undef DEBUG
40#undef DEBUG_HARD
41#undef USE_CTRL_O_SYSRQ
42
43#include <linux/module.h>
44#include <linux/tty.h>
45
46#include <linux/tty_flip.h>
47#include <linux/major.h>
48#include <linux/string.h>
49#include <linux/fcntl.h>
50#include <linux/mm.h>
51#include <linux/kernel.h>
52#include <linux/delay.h>
53#include <linux/init.h>
54#include <linux/console.h>
55#include <linux/adb.h>
56#include <linux/pmu.h>
57#include <linux/bitops.h>
58#include <linux/sysrq.h>
59#include <linux/mutex.h>
60#include <linux/of_address.h>
61#include <linux/of_irq.h>
62#include <asm/sections.h>
63#include <asm/io.h>
64#include <asm/irq.h>
65
66#ifdef CONFIG_PPC_PMAC
67#include <asm/prom.h>
68#include <asm/machdep.h>
69#include <asm/pmac_feature.h>
70#include <asm/dbdma.h>
71#include <asm/macio.h>
72#else
73#include <linux/platform_device.h>
74#define of_machine_is_compatible(x) (0)
75#endif
76
77#if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
78#define SUPPORT_SYSRQ
79#endif
80
81#include <linux/serial.h>
82#include <linux/serial_core.h>
83
84#include "pmac_zilog.h"
85
86/* Not yet implemented */
87#undef HAS_DBDMA
88
89static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
90MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
91MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
92MODULE_LICENSE("GPL");
93
94#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
95#define PMACZILOG_MAJOR TTY_MAJOR
96#define PMACZILOG_MINOR 64
97#define PMACZILOG_NAME "ttyS"
98#else
99#define PMACZILOG_MAJOR 204
100#define PMACZILOG_MINOR 192
101#define PMACZILOG_NAME "ttyPZ"
102#endif
103
104#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
105#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
106#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
107
108/*
109 * For the sake of early serial console, we can do a pre-probe
110 * (optional) of the ports at rather early boot time.
111 */
112static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
113static int pmz_ports_count;
114
115static struct uart_driver pmz_uart_reg = {
116 .owner = THIS_MODULE,
117 .driver_name = PMACZILOG_NAME,
118 .dev_name = PMACZILOG_NAME,
119 .major = PMACZILOG_MAJOR,
120 .minor = PMACZILOG_MINOR,
121};
122
123
124/*
125 * Load all registers to reprogram the port
126 * This function must only be called when the TX is not busy. The UART
127 * port lock must be held and local interrupts disabled.
128 */
129static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
130{
131 int i;
132
133 /* Let pending transmits finish. */
134 for (i = 0; i < 1000; i++) {
135 unsigned char stat = read_zsreg(uap, R1);
136 if (stat & ALL_SNT)
137 break;
138 udelay(100);
139 }
140
141 ZS_CLEARERR(uap);
142 zssync(uap);
143 ZS_CLEARFIFO(uap);
144 zssync(uap);
145 ZS_CLEARERR(uap);
146
147 /* Disable all interrupts. */
148 write_zsreg(uap, R1,
149 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
150
151 /* Set parity, sync config, stop bits, and clock divisor. */
152 write_zsreg(uap, R4, regs[R4]);
153
154 /* Set misc. TX/RX control bits. */
155 write_zsreg(uap, R10, regs[R10]);
156
157 /* Set TX/RX controls sans the enable bits. */
158 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
159 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
160
161 /* now set R7 "prime" on ESCC */
162 write_zsreg(uap, R15, regs[R15] | EN85C30);
163 write_zsreg(uap, R7, regs[R7P]);
164
165 /* make sure we use R7 "non-prime" on ESCC */
166 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
167
168 /* Synchronous mode config. */
169 write_zsreg(uap, R6, regs[R6]);
170 write_zsreg(uap, R7, regs[R7]);
171
172 /* Disable baud generator. */
173 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
174
175 /* Clock mode control. */
176 write_zsreg(uap, R11, regs[R11]);
177
178 /* Lower and upper byte of baud rate generator divisor. */
179 write_zsreg(uap, R12, regs[R12]);
180 write_zsreg(uap, R13, regs[R13]);
181
182 /* Now rewrite R14, with BRENAB (if set). */
183 write_zsreg(uap, R14, regs[R14]);
184
185 /* Reset external status interrupts. */
186 write_zsreg(uap, R0, RES_EXT_INT);
187 write_zsreg(uap, R0, RES_EXT_INT);
188
189 /* Rewrite R3/R5, this time without enables masked. */
190 write_zsreg(uap, R3, regs[R3]);
191 write_zsreg(uap, R5, regs[R5]);
192
193 /* Rewrite R1, this time without IRQ enabled masked. */
194 write_zsreg(uap, R1, regs[R1]);
195
196 /* Enable interrupts */
197 write_zsreg(uap, R9, regs[R9]);
198}
199
200/*
201 * We do like sunzilog to avoid disrupting pending Tx
202 * Reprogram the Zilog channel HW registers with the copies found in the
203 * software state struct. If the transmitter is busy, we defer this update
204 * until the next TX complete interrupt. Else, we do it right now.
205 *
206 * The UART port lock must be held and local interrupts disabled.
207 */
208static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
209{
210 if (!ZS_REGS_HELD(uap)) {
211 if (ZS_TX_ACTIVE(uap)) {
212 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
213 } else {
214 pmz_debug("pmz: maybe_update_regs: updating\n");
215 pmz_load_zsregs(uap, uap->curregs);
216 }
217 }
218}
219
220static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
221{
222 if (enable) {
223 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
224 if (!ZS_IS_EXTCLK(uap))
225 uap->curregs[1] |= EXT_INT_ENAB;
226 } else {
227 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
228 }
229 write_zsreg(uap, R1, uap->curregs[1]);
230}
231
232static bool pmz_receive_chars(struct uart_pmac_port *uap)
233{
234 struct tty_port *port;
235 unsigned char ch, r1, drop, error, flag;
236 int loops = 0;
237
238 /* Sanity check, make sure the old bug is no longer happening */
239 if (uap->port.state == NULL) {
240 WARN_ON(1);
241 (void)read_zsdata(uap);
242 return false;
243 }
244 port = &uap->port.state->port;
245
246 while (1) {
247 error = 0;
248 drop = 0;
249
250 r1 = read_zsreg(uap, R1);
251 ch = read_zsdata(uap);
252
253 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
254 write_zsreg(uap, R0, ERR_RES);
255 zssync(uap);
256 }
257
258 ch &= uap->parity_mask;
259 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
260 uap->flags &= ~PMACZILOG_FLAG_BREAK;
261 }
262
263#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
264#ifdef USE_CTRL_O_SYSRQ
265 /* Handle the SysRq ^O Hack */
266 if (ch == '\x0f') {
267 uap->port.sysrq = jiffies + HZ*5;
268 goto next_char;
269 }
270#endif /* USE_CTRL_O_SYSRQ */
271 if (uap->port.sysrq) {
272 int swallow;
273 spin_unlock(&uap->port.lock);
274 swallow = uart_handle_sysrq_char(&uap->port, ch);
275 spin_lock(&uap->port.lock);
276 if (swallow)
277 goto next_char;
278 }
279#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
280
281 /* A real serial line, record the character and status. */
282 if (drop)
283 goto next_char;
284
285 flag = TTY_NORMAL;
286 uap->port.icount.rx++;
287
288 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
289 error = 1;
290 if (r1 & BRK_ABRT) {
291 pmz_debug("pmz: got break !\n");
292 r1 &= ~(PAR_ERR | CRC_ERR);
293 uap->port.icount.brk++;
294 if (uart_handle_break(&uap->port))
295 goto next_char;
296 }
297 else if (r1 & PAR_ERR)
298 uap->port.icount.parity++;
299 else if (r1 & CRC_ERR)
300 uap->port.icount.frame++;
301 if (r1 & Rx_OVR)
302 uap->port.icount.overrun++;
303 r1 &= uap->port.read_status_mask;
304 if (r1 & BRK_ABRT)
305 flag = TTY_BREAK;
306 else if (r1 & PAR_ERR)
307 flag = TTY_PARITY;
308 else if (r1 & CRC_ERR)
309 flag = TTY_FRAME;
310 }
311
312 if (uap->port.ignore_status_mask == 0xff ||
313 (r1 & uap->port.ignore_status_mask) == 0) {
314 tty_insert_flip_char(port, ch, flag);
315 }
316 if (r1 & Rx_OVR)
317 tty_insert_flip_char(port, 0, TTY_OVERRUN);
318 next_char:
319 /* We can get stuck in an infinite loop getting char 0 when the
320 * line is in a wrong HW state, we break that here.
321 * When that happens, I disable the receive side of the driver.
322 * Note that what I've been experiencing is a real irq loop where
323 * I'm getting flooded regardless of the actual port speed.
324 * Something strange is going on with the HW
325 */
326 if ((++loops) > 1000)
327 goto flood;
328 ch = read_zsreg(uap, R0);
329 if (!(ch & Rx_CH_AV))
330 break;
331 }
332
333 return true;
334 flood:
335 pmz_interrupt_control(uap, 0);
336 pmz_error("pmz: rx irq flood !\n");
337 return true;
338}
339
340static void pmz_status_handle(struct uart_pmac_port *uap)
341{
342 unsigned char status;
343
344 status = read_zsreg(uap, R0);
345 write_zsreg(uap, R0, RES_EXT_INT);
346 zssync(uap);
347
348 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
349 if (status & SYNC_HUNT)
350 uap->port.icount.dsr++;
351
352 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
353 * But it does not tell us which bit has changed, we have to keep
354 * track of this ourselves.
355 * The CTS input is inverted for some reason. -- paulus
356 */
357 if ((status ^ uap->prev_status) & DCD)
358 uart_handle_dcd_change(&uap->port,
359 (status & DCD));
360 if ((status ^ uap->prev_status) & CTS)
361 uart_handle_cts_change(&uap->port,
362 !(status & CTS));
363
364 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
365 }
366
367 if (status & BRK_ABRT)
368 uap->flags |= PMACZILOG_FLAG_BREAK;
369
370 uap->prev_status = status;
371}
372
373static void pmz_transmit_chars(struct uart_pmac_port *uap)
374{
375 struct circ_buf *xmit;
376
377 if (ZS_IS_CONS(uap)) {
378 unsigned char status = read_zsreg(uap, R0);
379
380 /* TX still busy? Just wait for the next TX done interrupt.
381 *
382 * It can occur because of how we do serial console writes. It would
383 * be nice to transmit console writes just like we normally would for
384 * a TTY line. (ie. buffered and TX interrupt driven). That is not
385 * easy because console writes cannot sleep. One solution might be
386 * to poll on enough port->xmit space becoming free. -DaveM
387 */
388 if (!(status & Tx_BUF_EMP))
389 return;
390 }
391
392 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
393
394 if (ZS_REGS_HELD(uap)) {
395 pmz_load_zsregs(uap, uap->curregs);
396 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
397 }
398
399 if (ZS_TX_STOPPED(uap)) {
400 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
401 goto ack_tx_int;
402 }
403
404 /* Under some circumstances, we see interrupts reported for
405 * a closed channel. The interrupt mask in R1 is clear, but
406 * R3 still signals the interrupts and we see them when taking
407 * an interrupt for the other channel (this could be a qemu
408 * bug but since the ESCC doc doesn't specify precsiely whether
409 * R3 interrup status bits are masked by R1 interrupt enable
410 * bits, better safe than sorry). --BenH.
411 */
412 if (!ZS_IS_OPEN(uap))
413 goto ack_tx_int;
414
415 if (uap->port.x_char) {
416 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
417 write_zsdata(uap, uap->port.x_char);
418 zssync(uap);
419 uap->port.icount.tx++;
420 uap->port.x_char = 0;
421 return;
422 }
423
424 if (uap->port.state == NULL)
425 goto ack_tx_int;
426 xmit = &uap->port.state->xmit;
427 if (uart_circ_empty(xmit)) {
428 uart_write_wakeup(&uap->port);
429 goto ack_tx_int;
430 }
431 if (uart_tx_stopped(&uap->port))
432 goto ack_tx_int;
433
434 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
435 write_zsdata(uap, xmit->buf[xmit->tail]);
436 zssync(uap);
437
438 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
439 uap->port.icount.tx++;
440
441 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
442 uart_write_wakeup(&uap->port);
443
444 return;
445
446ack_tx_int:
447 write_zsreg(uap, R0, RES_Tx_P);
448 zssync(uap);
449}
450
451/* Hrm... we register that twice, fixme later.... */
452static irqreturn_t pmz_interrupt(int irq, void *dev_id)
453{
454 struct uart_pmac_port *uap = dev_id;
455 struct uart_pmac_port *uap_a;
456 struct uart_pmac_port *uap_b;
457 int rc = IRQ_NONE;
458 bool push;
459 u8 r3;
460
461 uap_a = pmz_get_port_A(uap);
462 uap_b = uap_a->mate;
463
464 spin_lock(&uap_a->port.lock);
465 r3 = read_zsreg(uap_a, R3);
466
467#ifdef DEBUG_HARD
468 pmz_debug("irq, r3: %x\n", r3);
469#endif
470 /* Channel A */
471 push = false;
472 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
473 if (!ZS_IS_OPEN(uap_a)) {
474 pmz_debug("ChanA interrupt while not open !\n");
475 goto skip_a;
476 }
477 write_zsreg(uap_a, R0, RES_H_IUS);
478 zssync(uap_a);
479 if (r3 & CHAEXT)
480 pmz_status_handle(uap_a);
481 if (r3 & CHARxIP)
482 push = pmz_receive_chars(uap_a);
483 if (r3 & CHATxIP)
484 pmz_transmit_chars(uap_a);
485 rc = IRQ_HANDLED;
486 }
487 skip_a:
488 spin_unlock(&uap_a->port.lock);
489 if (push)
490 tty_flip_buffer_push(&uap->port.state->port);
491
492 if (!uap_b)
493 goto out;
494
495 spin_lock(&uap_b->port.lock);
496 push = false;
497 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
498 if (!ZS_IS_OPEN(uap_b)) {
499 pmz_debug("ChanB interrupt while not open !\n");
500 goto skip_b;
501 }
502 write_zsreg(uap_b, R0, RES_H_IUS);
503 zssync(uap_b);
504 if (r3 & CHBEXT)
505 pmz_status_handle(uap_b);
506 if (r3 & CHBRxIP)
507 push = pmz_receive_chars(uap_b);
508 if (r3 & CHBTxIP)
509 pmz_transmit_chars(uap_b);
510 rc = IRQ_HANDLED;
511 }
512 skip_b:
513 spin_unlock(&uap_b->port.lock);
514 if (push)
515 tty_flip_buffer_push(&uap->port.state->port);
516
517 out:
518 return rc;
519}
520
521/*
522 * Peek the status register, lock not held by caller
523 */
524static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
525{
526 unsigned long flags;
527 u8 status;
528
529 spin_lock_irqsave(&uap->port.lock, flags);
530 status = read_zsreg(uap, R0);
531 spin_unlock_irqrestore(&uap->port.lock, flags);
532
533 return status;
534}
535
536/*
537 * Check if transmitter is empty
538 * The port lock is not held.
539 */
540static unsigned int pmz_tx_empty(struct uart_port *port)
541{
542 unsigned char status;
543
544 status = pmz_peek_status(to_pmz(port));
545 if (status & Tx_BUF_EMP)
546 return TIOCSER_TEMT;
547 return 0;
548}
549
550/*
551 * Set Modem Control (RTS & DTR) bits
552 * The port lock is held and interrupts are disabled.
553 * Note: Shall we really filter out RTS on external ports or
554 * should that be dealt at higher level only ?
555 */
556static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
557{
558 struct uart_pmac_port *uap = to_pmz(port);
559 unsigned char set_bits, clear_bits;
560
561 /* Do nothing for irda for now... */
562 if (ZS_IS_IRDA(uap))
563 return;
564 /* We get called during boot with a port not up yet */
565 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
566 return;
567
568 set_bits = clear_bits = 0;
569
570 if (ZS_IS_INTMODEM(uap)) {
571 if (mctrl & TIOCM_RTS)
572 set_bits |= RTS;
573 else
574 clear_bits |= RTS;
575 }
576 if (mctrl & TIOCM_DTR)
577 set_bits |= DTR;
578 else
579 clear_bits |= DTR;
580
581 /* NOTE: Not subject to 'transmitter active' rule. */
582 uap->curregs[R5] |= set_bits;
583 uap->curregs[R5] &= ~clear_bits;
584
585 write_zsreg(uap, R5, uap->curregs[R5]);
586 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
587 set_bits, clear_bits, uap->curregs[R5]);
588 zssync(uap);
589}
590
591/*
592 * Get Modem Control bits (only the input ones, the core will
593 * or that with a cached value of the control ones)
594 * The port lock is held and interrupts are disabled.
595 */
596static unsigned int pmz_get_mctrl(struct uart_port *port)
597{
598 struct uart_pmac_port *uap = to_pmz(port);
599 unsigned char status;
600 unsigned int ret;
601
602 status = read_zsreg(uap, R0);
603
604 ret = 0;
605 if (status & DCD)
606 ret |= TIOCM_CAR;
607 if (status & SYNC_HUNT)
608 ret |= TIOCM_DSR;
609 if (!(status & CTS))
610 ret |= TIOCM_CTS;
611
612 return ret;
613}
614
615/*
616 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
617 * though for DMA, we will have to do a bit more.
618 * The port lock is held and interrupts are disabled.
619 */
620static void pmz_stop_tx(struct uart_port *port)
621{
622 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
623}
624
625/*
626 * Kick the Tx side.
627 * The port lock is held and interrupts are disabled.
628 */
629static void pmz_start_tx(struct uart_port *port)
630{
631 struct uart_pmac_port *uap = to_pmz(port);
632 unsigned char status;
633
634 pmz_debug("pmz: start_tx()\n");
635
636 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
637 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
638
639 status = read_zsreg(uap, R0);
640
641 /* TX busy? Just wait for the TX done interrupt. */
642 if (!(status & Tx_BUF_EMP))
643 return;
644
645 /* Send the first character to jump-start the TX done
646 * IRQ sending engine.
647 */
648 if (port->x_char) {
649 write_zsdata(uap, port->x_char);
650 zssync(uap);
651 port->icount.tx++;
652 port->x_char = 0;
653 } else {
654 struct circ_buf *xmit = &port->state->xmit;
655
656 if (uart_circ_empty(xmit))
657 goto out;
658 write_zsdata(uap, xmit->buf[xmit->tail]);
659 zssync(uap);
660 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
661 port->icount.tx++;
662
663 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
664 uart_write_wakeup(&uap->port);
665 }
666 out:
667 pmz_debug("pmz: start_tx() done.\n");
668}
669
670/*
671 * Stop Rx side, basically disable emitting of
672 * Rx interrupts on the port. We don't disable the rx
673 * side of the chip proper though
674 * The port lock is held.
675 */
676static void pmz_stop_rx(struct uart_port *port)
677{
678 struct uart_pmac_port *uap = to_pmz(port);
679
680 pmz_debug("pmz: stop_rx()()\n");
681
682 /* Disable all RX interrupts. */
683 uap->curregs[R1] &= ~RxINT_MASK;
684 pmz_maybe_update_regs(uap);
685
686 pmz_debug("pmz: stop_rx() done.\n");
687}
688
689/*
690 * Enable modem status change interrupts
691 * The port lock is held.
692 */
693static void pmz_enable_ms(struct uart_port *port)
694{
695 struct uart_pmac_port *uap = to_pmz(port);
696 unsigned char new_reg;
697
698 if (ZS_IS_IRDA(uap))
699 return;
700 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
701 if (new_reg != uap->curregs[R15]) {
702 uap->curregs[R15] = new_reg;
703
704 /* NOTE: Not subject to 'transmitter active' rule. */
705 write_zsreg(uap, R15, uap->curregs[R15]);
706 }
707}
708
709/*
710 * Control break state emission
711 * The port lock is not held.
712 */
713static void pmz_break_ctl(struct uart_port *port, int break_state)
714{
715 struct uart_pmac_port *uap = to_pmz(port);
716 unsigned char set_bits, clear_bits, new_reg;
717 unsigned long flags;
718
719 set_bits = clear_bits = 0;
720
721 if (break_state)
722 set_bits |= SND_BRK;
723 else
724 clear_bits |= SND_BRK;
725
726 spin_lock_irqsave(&port->lock, flags);
727
728 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
729 if (new_reg != uap->curregs[R5]) {
730 uap->curregs[R5] = new_reg;
731 write_zsreg(uap, R5, uap->curregs[R5]);
732 }
733
734 spin_unlock_irqrestore(&port->lock, flags);
735}
736
737#ifdef CONFIG_PPC_PMAC
738
739/*
740 * Turn power on or off to the SCC and associated stuff
741 * (port drivers, modem, IR port, etc.)
742 * Returns the number of milliseconds we should wait before
743 * trying to use the port.
744 */
745static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
746{
747 int delay = 0;
748 int rc;
749
750 if (state) {
751 rc = pmac_call_feature(
752 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
753 pmz_debug("port power on result: %d\n", rc);
754 if (ZS_IS_INTMODEM(uap)) {
755 rc = pmac_call_feature(
756 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
757 delay = 2500; /* wait for 2.5s before using */
758 pmz_debug("modem power result: %d\n", rc);
759 }
760 } else {
761 /* TODO: Make that depend on a timer, don't power down
762 * immediately
763 */
764 if (ZS_IS_INTMODEM(uap)) {
765 rc = pmac_call_feature(
766 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
767 pmz_debug("port power off result: %d\n", rc);
768 }
769 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
770 }
771 return delay;
772}
773
774#else
775
776static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
777{
778 return 0;
779}
780
781#endif /* !CONFIG_PPC_PMAC */
782
783/*
784 * FixZeroBug....Works around a bug in the SCC receiving channel.
785 * Inspired from Darwin code, 15 Sept. 2000 -DanM
786 *
787 * The following sequence prevents a problem that is seen with O'Hare ASICs
788 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
789 * at the input to the receiver becomes 'stuck' and locks up the receiver.
790 * This problem can occur as a result of a zero bit at the receiver input
791 * coincident with any of the following events:
792 *
793 * The SCC is initialized (hardware or software).
794 * A framing error is detected.
795 * The clocking option changes from synchronous or X1 asynchronous
796 * clocking to X16, X32, or X64 asynchronous clocking.
797 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
798 *
799 * This workaround attempts to recover from the lockup condition by placing
800 * the SCC in synchronous loopback mode with a fast clock before programming
801 * any of the asynchronous modes.
802 */
803static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
804{
805 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
806 zssync(uap);
807 udelay(10);
808 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
809 zssync(uap);
810
811 write_zsreg(uap, 4, X1CLK | MONSYNC);
812 write_zsreg(uap, 3, Rx8);
813 write_zsreg(uap, 5, Tx8 | RTS);
814 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
815 write_zsreg(uap, 11, RCBR | TCBR);
816 write_zsreg(uap, 12, 0);
817 write_zsreg(uap, 13, 0);
818 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
819 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
820 write_zsreg(uap, 3, Rx8 | RxENABLE);
821 write_zsreg(uap, 0, RES_EXT_INT);
822 write_zsreg(uap, 0, RES_EXT_INT);
823 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
824
825 /* The channel should be OK now, but it is probably receiving
826 * loopback garbage.
827 * Switch to asynchronous mode, disable the receiver,
828 * and discard everything in the receive buffer.
829 */
830 write_zsreg(uap, 9, NV);
831 write_zsreg(uap, 4, X16CLK | SB_MASK);
832 write_zsreg(uap, 3, Rx8);
833
834 while (read_zsreg(uap, 0) & Rx_CH_AV) {
835 (void)read_zsreg(uap, 8);
836 write_zsreg(uap, 0, RES_EXT_INT);
837 write_zsreg(uap, 0, ERR_RES);
838 }
839}
840
841/*
842 * Real startup routine, powers up the hardware and sets up
843 * the SCC. Returns a delay in ms where you need to wait before
844 * actually using the port, this is typically the internal modem
845 * powerup delay. This routine expect the lock to be taken.
846 */
847static int __pmz_startup(struct uart_pmac_port *uap)
848{
849 int pwr_delay = 0;
850
851 memset(&uap->curregs, 0, sizeof(uap->curregs));
852
853 /* Power up the SCC & underlying hardware (modem/irda) */
854 pwr_delay = pmz_set_scc_power(uap, 1);
855
856 /* Nice buggy HW ... */
857 pmz_fix_zero_bug_scc(uap);
858
859 /* Reset the channel */
860 uap->curregs[R9] = 0;
861 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
862 zssync(uap);
863 udelay(10);
864 write_zsreg(uap, 9, 0);
865 zssync(uap);
866
867 /* Clear the interrupt registers */
868 write_zsreg(uap, R1, 0);
869 write_zsreg(uap, R0, ERR_RES);
870 write_zsreg(uap, R0, ERR_RES);
871 write_zsreg(uap, R0, RES_H_IUS);
872 write_zsreg(uap, R0, RES_H_IUS);
873
874 /* Setup some valid baud rate */
875 uap->curregs[R4] = X16CLK | SB1;
876 uap->curregs[R3] = Rx8;
877 uap->curregs[R5] = Tx8 | RTS;
878 if (!ZS_IS_IRDA(uap))
879 uap->curregs[R5] |= DTR;
880 uap->curregs[R12] = 0;
881 uap->curregs[R13] = 0;
882 uap->curregs[R14] = BRENAB;
883
884 /* Clear handshaking, enable BREAK interrupts */
885 uap->curregs[R15] = BRKIE;
886
887 /* Master interrupt enable */
888 uap->curregs[R9] |= NV | MIE;
889
890 pmz_load_zsregs(uap, uap->curregs);
891
892 /* Enable receiver and transmitter. */
893 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
894 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
895
896 /* Remember status for DCD/CTS changes */
897 uap->prev_status = read_zsreg(uap, R0);
898
899 return pwr_delay;
900}
901
902static void pmz_irda_reset(struct uart_pmac_port *uap)
903{
904 unsigned long flags;
905
906 spin_lock_irqsave(&uap->port.lock, flags);
907 uap->curregs[R5] |= DTR;
908 write_zsreg(uap, R5, uap->curregs[R5]);
909 zssync(uap);
910 spin_unlock_irqrestore(&uap->port.lock, flags);
911 msleep(110);
912
913 spin_lock_irqsave(&uap->port.lock, flags);
914 uap->curregs[R5] &= ~DTR;
915 write_zsreg(uap, R5, uap->curregs[R5]);
916 zssync(uap);
917 spin_unlock_irqrestore(&uap->port.lock, flags);
918 msleep(10);
919}
920
921/*
922 * This is the "normal" startup routine, using the above one
923 * wrapped with the lock and doing a schedule delay
924 */
925static int pmz_startup(struct uart_port *port)
926{
927 struct uart_pmac_port *uap = to_pmz(port);
928 unsigned long flags;
929 int pwr_delay = 0;
930
931 pmz_debug("pmz: startup()\n");
932
933 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
934
935 /* A console is never powered down. Else, power up and
936 * initialize the chip
937 */
938 if (!ZS_IS_CONS(uap)) {
939 spin_lock_irqsave(&port->lock, flags);
940 pwr_delay = __pmz_startup(uap);
941 spin_unlock_irqrestore(&port->lock, flags);
942 }
943 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
944 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
945 uap->irq_name, uap)) {
946 pmz_error("Unable to register zs interrupt handler.\n");
947 pmz_set_scc_power(uap, 0);
948 return -ENXIO;
949 }
950
951 /* Right now, we deal with delay by blocking here, I'll be
952 * smarter later on
953 */
954 if (pwr_delay != 0) {
955 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
956 msleep(pwr_delay);
957 }
958
959 /* IrDA reset is done now */
960 if (ZS_IS_IRDA(uap))
961 pmz_irda_reset(uap);
962
963 /* Enable interrupt requests for the channel */
964 spin_lock_irqsave(&port->lock, flags);
965 pmz_interrupt_control(uap, 1);
966 spin_unlock_irqrestore(&port->lock, flags);
967
968 pmz_debug("pmz: startup() done.\n");
969
970 return 0;
971}
972
973static void pmz_shutdown(struct uart_port *port)
974{
975 struct uart_pmac_port *uap = to_pmz(port);
976 unsigned long flags;
977
978 pmz_debug("pmz: shutdown()\n");
979
980 spin_lock_irqsave(&port->lock, flags);
981
982 /* Disable interrupt requests for the channel */
983 pmz_interrupt_control(uap, 0);
984
985 if (!ZS_IS_CONS(uap)) {
986 /* Disable receiver and transmitter */
987 uap->curregs[R3] &= ~RxENABLE;
988 uap->curregs[R5] &= ~TxENABLE;
989
990 /* Disable break assertion */
991 uap->curregs[R5] &= ~SND_BRK;
992 pmz_maybe_update_regs(uap);
993 }
994
995 spin_unlock_irqrestore(&port->lock, flags);
996
997 /* Release interrupt handler */
998 free_irq(uap->port.irq, uap);
999
1000 spin_lock_irqsave(&port->lock, flags);
1001
1002 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
1003
1004 if (!ZS_IS_CONS(uap))
1005 pmz_set_scc_power(uap, 0); /* Shut the chip down */
1006
1007 spin_unlock_irqrestore(&port->lock, flags);
1008
1009 pmz_debug("pmz: shutdown() done.\n");
1010}
1011
1012/* Shared by TTY driver and serial console setup. The port lock is held
1013 * and local interrupts are disabled.
1014 */
1015static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1016 unsigned int iflag, unsigned long baud)
1017{
1018 int brg;
1019
1020 /* Switch to external clocking for IrDA high clock rates. That
1021 * code could be re-used for Midi interfaces with different
1022 * multipliers
1023 */
1024 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1025 uap->curregs[R4] = X1CLK;
1026 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1027 uap->curregs[R14] = 0; /* BRG off */
1028 uap->curregs[R12] = 0;
1029 uap->curregs[R13] = 0;
1030 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1031 } else {
1032 switch (baud) {
1033 case ZS_CLOCK/16: /* 230400 */
1034 uap->curregs[R4] = X16CLK;
1035 uap->curregs[R11] = 0;
1036 uap->curregs[R14] = 0;
1037 break;
1038 case ZS_CLOCK/32: /* 115200 */
1039 uap->curregs[R4] = X32CLK;
1040 uap->curregs[R11] = 0;
1041 uap->curregs[R14] = 0;
1042 break;
1043 default:
1044 uap->curregs[R4] = X16CLK;
1045 uap->curregs[R11] = TCBR | RCBR;
1046 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1047 uap->curregs[R12] = (brg & 255);
1048 uap->curregs[R13] = ((brg >> 8) & 255);
1049 uap->curregs[R14] = BRENAB;
1050 }
1051 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1052 }
1053
1054 /* Character size, stop bits, and parity. */
1055 uap->curregs[3] &= ~RxN_MASK;
1056 uap->curregs[5] &= ~TxN_MASK;
1057
1058 switch (cflag & CSIZE) {
1059 case CS5:
1060 uap->curregs[3] |= Rx5;
1061 uap->curregs[5] |= Tx5;
1062 uap->parity_mask = 0x1f;
1063 break;
1064 case CS6:
1065 uap->curregs[3] |= Rx6;
1066 uap->curregs[5] |= Tx6;
1067 uap->parity_mask = 0x3f;
1068 break;
1069 case CS7:
1070 uap->curregs[3] |= Rx7;
1071 uap->curregs[5] |= Tx7;
1072 uap->parity_mask = 0x7f;
1073 break;
1074 case CS8:
1075 default:
1076 uap->curregs[3] |= Rx8;
1077 uap->curregs[5] |= Tx8;
1078 uap->parity_mask = 0xff;
1079 break;
1080 }
1081 uap->curregs[4] &= ~(SB_MASK);
1082 if (cflag & CSTOPB)
1083 uap->curregs[4] |= SB2;
1084 else
1085 uap->curregs[4] |= SB1;
1086 if (cflag & PARENB)
1087 uap->curregs[4] |= PAR_ENAB;
1088 else
1089 uap->curregs[4] &= ~PAR_ENAB;
1090 if (!(cflag & PARODD))
1091 uap->curregs[4] |= PAR_EVEN;
1092 else
1093 uap->curregs[4] &= ~PAR_EVEN;
1094
1095 uap->port.read_status_mask = Rx_OVR;
1096 if (iflag & INPCK)
1097 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1098 if (iflag & (IGNBRK | BRKINT | PARMRK))
1099 uap->port.read_status_mask |= BRK_ABRT;
1100
1101 uap->port.ignore_status_mask = 0;
1102 if (iflag & IGNPAR)
1103 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1104 if (iflag & IGNBRK) {
1105 uap->port.ignore_status_mask |= BRK_ABRT;
1106 if (iflag & IGNPAR)
1107 uap->port.ignore_status_mask |= Rx_OVR;
1108 }
1109
1110 if ((cflag & CREAD) == 0)
1111 uap->port.ignore_status_mask = 0xff;
1112}
1113
1114
1115/*
1116 * Set the irda codec on the imac to the specified baud rate.
1117 */
1118static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1119{
1120 u8 cmdbyte;
1121 int t, version;
1122
1123 switch (*baud) {
1124 /* SIR modes */
1125 case 2400:
1126 cmdbyte = 0x53;
1127 break;
1128 case 4800:
1129 cmdbyte = 0x52;
1130 break;
1131 case 9600:
1132 cmdbyte = 0x51;
1133 break;
1134 case 19200:
1135 cmdbyte = 0x50;
1136 break;
1137 case 38400:
1138 cmdbyte = 0x4f;
1139 break;
1140 case 57600:
1141 cmdbyte = 0x4e;
1142 break;
1143 case 115200:
1144 cmdbyte = 0x4d;
1145 break;
1146 /* The FIR modes aren't really supported at this point, how
1147 * do we select the speed ? via the FCR on KeyLargo ?
1148 */
1149 case 1152000:
1150 cmdbyte = 0;
1151 break;
1152 case 4000000:
1153 cmdbyte = 0;
1154 break;
1155 default: /* 9600 */
1156 cmdbyte = 0x51;
1157 *baud = 9600;
1158 break;
1159 }
1160
1161 /* Wait for transmitter to drain */
1162 t = 10000;
1163 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1164 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1165 if (--t <= 0) {
1166 pmz_error("transmitter didn't drain\n");
1167 return;
1168 }
1169 udelay(10);
1170 }
1171
1172 /* Drain the receiver too */
1173 t = 100;
1174 (void)read_zsdata(uap);
1175 (void)read_zsdata(uap);
1176 (void)read_zsdata(uap);
1177 mdelay(10);
1178 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1179 read_zsdata(uap);
1180 mdelay(10);
1181 if (--t <= 0) {
1182 pmz_error("receiver didn't drain\n");
1183 return;
1184 }
1185 }
1186
1187 /* Switch to command mode */
1188 uap->curregs[R5] |= DTR;
1189 write_zsreg(uap, R5, uap->curregs[R5]);
1190 zssync(uap);
1191 mdelay(1);
1192
1193 /* Switch SCC to 19200 */
1194 pmz_convert_to_zs(uap, CS8, 0, 19200);
1195 pmz_load_zsregs(uap, uap->curregs);
1196 mdelay(1);
1197
1198 /* Write get_version command byte */
1199 write_zsdata(uap, 1);
1200 t = 5000;
1201 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1202 if (--t <= 0) {
1203 pmz_error("irda_setup timed out on get_version byte\n");
1204 goto out;
1205 }
1206 udelay(10);
1207 }
1208 version = read_zsdata(uap);
1209
1210 if (version < 4) {
1211 pmz_info("IrDA: dongle version %d not supported\n", version);
1212 goto out;
1213 }
1214
1215 /* Send speed mode */
1216 write_zsdata(uap, cmdbyte);
1217 t = 5000;
1218 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1219 if (--t <= 0) {
1220 pmz_error("irda_setup timed out on speed mode byte\n");
1221 goto out;
1222 }
1223 udelay(10);
1224 }
1225 t = read_zsdata(uap);
1226 if (t != cmdbyte)
1227 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1228
1229 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1230 *baud, version);
1231
1232 (void)read_zsdata(uap);
1233 (void)read_zsdata(uap);
1234 (void)read_zsdata(uap);
1235
1236 out:
1237 /* Switch back to data mode */
1238 uap->curregs[R5] &= ~DTR;
1239 write_zsreg(uap, R5, uap->curregs[R5]);
1240 zssync(uap);
1241
1242 (void)read_zsdata(uap);
1243 (void)read_zsdata(uap);
1244 (void)read_zsdata(uap);
1245}
1246
1247
1248static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1249 struct ktermios *old)
1250{
1251 struct uart_pmac_port *uap = to_pmz(port);
1252 unsigned long baud;
1253
1254 pmz_debug("pmz: set_termios()\n");
1255
1256 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1257
1258 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1259 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1260 * about the FIR mode and high speed modes. So these are unused. For
1261 * implementing proper support for these, we should probably add some
1262 * DMA as well, at least on the Rx side, which isn't a simple thing
1263 * at this point.
1264 */
1265 if (ZS_IS_IRDA(uap)) {
1266 /* Calc baud rate */
1267 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1268 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1269 /* Cet the irda codec to the right rate */
1270 pmz_irda_setup(uap, &baud);
1271 /* Set final baud rate */
1272 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1273 pmz_load_zsregs(uap, uap->curregs);
1274 zssync(uap);
1275 } else {
1276 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1277 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1278 /* Make sure modem status interrupts are correctly configured */
1279 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1280 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1281 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1282 } else {
1283 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1284 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1285 }
1286
1287 /* Load registers to the chip */
1288 pmz_maybe_update_regs(uap);
1289 }
1290 uart_update_timeout(port, termios->c_cflag, baud);
1291
1292 pmz_debug("pmz: set_termios() done.\n");
1293}
1294
1295/* The port lock is not held. */
1296static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1297 struct ktermios *old)
1298{
1299 struct uart_pmac_port *uap = to_pmz(port);
1300 unsigned long flags;
1301
1302 spin_lock_irqsave(&port->lock, flags);
1303
1304 /* Disable IRQs on the port */
1305 pmz_interrupt_control(uap, 0);
1306
1307 /* Setup new port configuration */
1308 __pmz_set_termios(port, termios, old);
1309
1310 /* Re-enable IRQs on the port */
1311 if (ZS_IS_OPEN(uap))
1312 pmz_interrupt_control(uap, 1);
1313
1314 spin_unlock_irqrestore(&port->lock, flags);
1315}
1316
1317static const char *pmz_type(struct uart_port *port)
1318{
1319 struct uart_pmac_port *uap = to_pmz(port);
1320
1321 if (ZS_IS_IRDA(uap))
1322 return "Z85c30 ESCC - Infrared port";
1323 else if (ZS_IS_INTMODEM(uap))
1324 return "Z85c30 ESCC - Internal modem";
1325 return "Z85c30 ESCC - Serial port";
1326}
1327
1328/* We do not request/release mappings of the registers here, this
1329 * happens at early serial probe time.
1330 */
1331static void pmz_release_port(struct uart_port *port)
1332{
1333}
1334
1335static int pmz_request_port(struct uart_port *port)
1336{
1337 return 0;
1338}
1339
1340/* These do not need to do anything interesting either. */
1341static void pmz_config_port(struct uart_port *port, int flags)
1342{
1343}
1344
1345/* We do not support letting the user mess with the divisor, IRQ, etc. */
1346static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1347{
1348 return -EINVAL;
1349}
1350
1351#ifdef CONFIG_CONSOLE_POLL
1352
1353static int pmz_poll_get_char(struct uart_port *port)
1354{
1355 struct uart_pmac_port *uap =
1356 container_of(port, struct uart_pmac_port, port);
1357 int tries = 2;
1358
1359 while (tries) {
1360 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
1361 return read_zsdata(uap);
1362 if (tries--)
1363 udelay(5);
1364 }
1365
1366 return NO_POLL_CHAR;
1367}
1368
1369static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1370{
1371 struct uart_pmac_port *uap =
1372 container_of(port, struct uart_pmac_port, port);
1373
1374 /* Wait for the transmit buffer to empty. */
1375 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1376 udelay(5);
1377 write_zsdata(uap, c);
1378}
1379
1380#endif /* CONFIG_CONSOLE_POLL */
1381
1382static struct uart_ops pmz_pops = {
1383 .tx_empty = pmz_tx_empty,
1384 .set_mctrl = pmz_set_mctrl,
1385 .get_mctrl = pmz_get_mctrl,
1386 .stop_tx = pmz_stop_tx,
1387 .start_tx = pmz_start_tx,
1388 .stop_rx = pmz_stop_rx,
1389 .enable_ms = pmz_enable_ms,
1390 .break_ctl = pmz_break_ctl,
1391 .startup = pmz_startup,
1392 .shutdown = pmz_shutdown,
1393 .set_termios = pmz_set_termios,
1394 .type = pmz_type,
1395 .release_port = pmz_release_port,
1396 .request_port = pmz_request_port,
1397 .config_port = pmz_config_port,
1398 .verify_port = pmz_verify_port,
1399#ifdef CONFIG_CONSOLE_POLL
1400 .poll_get_char = pmz_poll_get_char,
1401 .poll_put_char = pmz_poll_put_char,
1402#endif
1403};
1404
1405#ifdef CONFIG_PPC_PMAC
1406
1407/*
1408 * Setup one port structure after probing, HW is down at this point,
1409 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1410 * register our console before uart_add_one_port() is called
1411 */
1412static int __init pmz_init_port(struct uart_pmac_port *uap)
1413{
1414 struct device_node *np = uap->node;
1415 const char *conn;
1416 const struct slot_names_prop {
1417 int count;
1418 char name[1];
1419 } *slots;
1420 int len;
1421 struct resource r_ports, r_rxdma, r_txdma;
1422
1423 /*
1424 * Request & map chip registers
1425 */
1426 if (of_address_to_resource(np, 0, &r_ports))
1427 return -ENODEV;
1428 uap->port.mapbase = r_ports.start;
1429 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1430
1431 uap->control_reg = uap->port.membase;
1432 uap->data_reg = uap->control_reg + 0x10;
1433
1434 /*
1435 * Request & map DBDMA registers
1436 */
1437#ifdef HAS_DBDMA
1438 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1439 of_address_to_resource(np, 2, &r_rxdma) == 0)
1440 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1441#else
1442 memset(&r_txdma, 0, sizeof(struct resource));
1443 memset(&r_rxdma, 0, sizeof(struct resource));
1444#endif
1445 if (ZS_HAS_DMA(uap)) {
1446 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1447 if (uap->tx_dma_regs == NULL) {
1448 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1449 goto no_dma;
1450 }
1451 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1452 if (uap->rx_dma_regs == NULL) {
1453 iounmap(uap->tx_dma_regs);
1454 uap->tx_dma_regs = NULL;
1455 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1456 goto no_dma;
1457 }
1458 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1459 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1460 }
1461no_dma:
1462
1463 /*
1464 * Detect port type
1465 */
1466 if (of_device_is_compatible(np, "cobalt"))
1467 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1468 conn = of_get_property(np, "AAPL,connector", &len);
1469 if (conn && (strcmp(conn, "infrared") == 0))
1470 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1471 uap->port_type = PMAC_SCC_ASYNC;
1472 /* 1999 Powerbook G3 has slot-names property instead */
1473 slots = of_get_property(np, "slot-names", &len);
1474 if (slots && slots->count > 0) {
1475 if (strcmp(slots->name, "IrDA") == 0)
1476 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1477 else if (strcmp(slots->name, "Modem") == 0)
1478 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1479 }
1480 if (ZS_IS_IRDA(uap))
1481 uap->port_type = PMAC_SCC_IRDA;
1482 if (ZS_IS_INTMODEM(uap)) {
1483 struct device_node* i2c_modem =
1484 of_find_node_by_name(NULL, "i2c-modem");
1485 if (i2c_modem) {
1486 const char* mid =
1487 of_get_property(i2c_modem, "modem-id", NULL);
1488 if (mid) switch(*mid) {
1489 case 0x04 :
1490 case 0x05 :
1491 case 0x07 :
1492 case 0x08 :
1493 case 0x0b :
1494 case 0x0c :
1495 uap->port_type = PMAC_SCC_I2S1;
1496 }
1497 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1498 mid ? (*mid) : 0);
1499 of_node_put(i2c_modem);
1500 } else {
1501 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1502 }
1503 }
1504
1505 /*
1506 * Init remaining bits of "port" structure
1507 */
1508 uap->port.iotype = UPIO_MEM;
1509 uap->port.irq = irq_of_parse_and_map(np, 0);
1510 uap->port.uartclk = ZS_CLOCK;
1511 uap->port.fifosize = 1;
1512 uap->port.ops = &pmz_pops;
1513 uap->port.type = PORT_PMAC_ZILOG;
1514 uap->port.flags = 0;
1515
1516 /*
1517 * Fixup for the port on Gatwick for which the device-tree has
1518 * missing interrupts. Normally, the macio_dev would contain
1519 * fixed up interrupt info, but we use the device-tree directly
1520 * here due to early probing so we need the fixup too.
1521 */
1522 if (uap->port.irq == 0 &&
1523 np->parent && np->parent->parent &&
1524 of_device_is_compatible(np->parent->parent, "gatwick")) {
1525 /* IRQs on gatwick are offset by 64 */
1526 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1527 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1528 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1529 }
1530
1531 /* Setup some valid baud rate information in the register
1532 * shadows so we don't write crap there before baud rate is
1533 * first initialized.
1534 */
1535 pmz_convert_to_zs(uap, CS8, 0, 9600);
1536
1537 return 0;
1538}
1539
1540/*
1541 * Get rid of a port on module removal
1542 */
1543static void pmz_dispose_port(struct uart_pmac_port *uap)
1544{
1545 struct device_node *np;
1546
1547 np = uap->node;
1548 iounmap(uap->rx_dma_regs);
1549 iounmap(uap->tx_dma_regs);
1550 iounmap(uap->control_reg);
1551 uap->node = NULL;
1552 of_node_put(np);
1553 memset(uap, 0, sizeof(struct uart_pmac_port));
1554}
1555
1556/*
1557 * Called upon match with an escc node in the device-tree.
1558 */
1559static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1560{
1561 struct uart_pmac_port *uap;
1562 int i;
1563
1564 /* Iterate the pmz_ports array to find a matching entry
1565 */
1566 for (i = 0; i < MAX_ZS_PORTS; i++)
1567 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1568 break;
1569 if (i >= MAX_ZS_PORTS)
1570 return -ENODEV;
1571
1572
1573 uap = &pmz_ports[i];
1574 uap->dev = mdev;
1575 uap->port.dev = &mdev->ofdev.dev;
1576 dev_set_drvdata(&mdev->ofdev.dev, uap);
1577
1578 /* We still activate the port even when failing to request resources
1579 * to work around bugs in ancient Apple device-trees
1580 */
1581 if (macio_request_resources(uap->dev, "pmac_zilog"))
1582 printk(KERN_WARNING "%s: Failed to request resource"
1583 ", port still active\n",
1584 uap->node->name);
1585 else
1586 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1587
1588 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1589}
1590
1591/*
1592 * That one should not be called, macio isn't really a hotswap device,
1593 * we don't expect one of those serial ports to go away...
1594 */
1595static int pmz_detach(struct macio_dev *mdev)
1596{
1597 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1598
1599 if (!uap)
1600 return -ENODEV;
1601
1602 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1603
1604 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1605 macio_release_resources(uap->dev);
1606 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1607 }
1608 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1609 uap->dev = NULL;
1610 uap->port.dev = NULL;
1611
1612 return 0;
1613}
1614
1615
1616static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1617{
1618 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1619
1620 if (uap == NULL) {
1621 printk("HRM... pmz_suspend with NULL uap\n");
1622 return 0;
1623 }
1624
1625 uart_suspend_port(&pmz_uart_reg, &uap->port);
1626
1627 return 0;
1628}
1629
1630
1631static int pmz_resume(struct macio_dev *mdev)
1632{
1633 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1634
1635 if (uap == NULL)
1636 return 0;
1637
1638 uart_resume_port(&pmz_uart_reg, &uap->port);
1639
1640 return 0;
1641}
1642
1643/*
1644 * Probe all ports in the system and build the ports array, we register
1645 * with the serial layer later, so we get a proper struct device which
1646 * allows the tty to attach properly. This is later than it used to be
1647 * but the tty layer really wants it that way.
1648 */
1649static int __init pmz_probe(void)
1650{
1651 struct device_node *node_p, *node_a, *node_b, *np;
1652 int count = 0;
1653 int rc;
1654
1655 /*
1656 * Find all escc chips in the system
1657 */
1658 for_each_node_by_name(node_p, "escc") {
1659 /*
1660 * First get channel A/B node pointers
1661 *
1662 * TODO: Add routines with proper locking to do that...
1663 */
1664 node_a = node_b = NULL;
1665 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1666 if (strncmp(np->name, "ch-a", 4) == 0)
1667 node_a = of_node_get(np);
1668 else if (strncmp(np->name, "ch-b", 4) == 0)
1669 node_b = of_node_get(np);
1670 }
1671 if (!node_a && !node_b) {
1672 of_node_put(node_a);
1673 of_node_put(node_b);
1674 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n",
1675 (!node_a) ? 'a' : 'b', node_p->full_name);
1676 continue;
1677 }
1678
1679 /*
1680 * Fill basic fields in the port structures
1681 */
1682 if (node_b != NULL) {
1683 pmz_ports[count].mate = &pmz_ports[count+1];
1684 pmz_ports[count+1].mate = &pmz_ports[count];
1685 }
1686 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1687 pmz_ports[count].node = node_a;
1688 pmz_ports[count+1].node = node_b;
1689 pmz_ports[count].port.line = count;
1690 pmz_ports[count+1].port.line = count+1;
1691
1692 /*
1693 * Setup the ports for real
1694 */
1695 rc = pmz_init_port(&pmz_ports[count]);
1696 if (rc == 0 && node_b != NULL)
1697 rc = pmz_init_port(&pmz_ports[count+1]);
1698 if (rc != 0) {
1699 of_node_put(node_a);
1700 of_node_put(node_b);
1701 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1702 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1703 continue;
1704 }
1705 count += 2;
1706 }
1707 pmz_ports_count = count;
1708
1709 return 0;
1710}
1711
1712#else
1713
1714extern struct platform_device scc_a_pdev, scc_b_pdev;
1715
1716static int __init pmz_init_port(struct uart_pmac_port *uap)
1717{
1718 struct resource *r_ports;
1719 int irq;
1720
1721 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1722 irq = platform_get_irq(uap->pdev, 0);
1723 if (!r_ports || !irq)
1724 return -ENODEV;
1725
1726 uap->port.mapbase = r_ports->start;
1727 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1728 uap->port.iotype = UPIO_MEM;
1729 uap->port.irq = irq;
1730 uap->port.uartclk = ZS_CLOCK;
1731 uap->port.fifosize = 1;
1732 uap->port.ops = &pmz_pops;
1733 uap->port.type = PORT_PMAC_ZILOG;
1734 uap->port.flags = 0;
1735
1736 uap->control_reg = uap->port.membase;
1737 uap->data_reg = uap->control_reg + 4;
1738 uap->port_type = 0;
1739
1740 pmz_convert_to_zs(uap, CS8, 0, 9600);
1741
1742 return 0;
1743}
1744
1745static int __init pmz_probe(void)
1746{
1747 int err;
1748
1749 pmz_ports_count = 0;
1750
1751 pmz_ports[0].port.line = 0;
1752 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1753 pmz_ports[0].pdev = &scc_a_pdev;
1754 err = pmz_init_port(&pmz_ports[0]);
1755 if (err)
1756 return err;
1757 pmz_ports_count++;
1758
1759 pmz_ports[0].mate = &pmz_ports[1];
1760 pmz_ports[1].mate = &pmz_ports[0];
1761 pmz_ports[1].port.line = 1;
1762 pmz_ports[1].flags = 0;
1763 pmz_ports[1].pdev = &scc_b_pdev;
1764 err = pmz_init_port(&pmz_ports[1]);
1765 if (err)
1766 return err;
1767 pmz_ports_count++;
1768
1769 return 0;
1770}
1771
1772static void pmz_dispose_port(struct uart_pmac_port *uap)
1773{
1774 memset(uap, 0, sizeof(struct uart_pmac_port));
1775}
1776
1777static int __init pmz_attach(struct platform_device *pdev)
1778{
1779 struct uart_pmac_port *uap;
1780 int i;
1781
1782 /* Iterate the pmz_ports array to find a matching entry */
1783 for (i = 0; i < pmz_ports_count; i++)
1784 if (pmz_ports[i].pdev == pdev)
1785 break;
1786 if (i >= pmz_ports_count)
1787 return -ENODEV;
1788
1789 uap = &pmz_ports[i];
1790 uap->port.dev = &pdev->dev;
1791 platform_set_drvdata(pdev, uap);
1792
1793 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1794}
1795
1796static int __exit pmz_detach(struct platform_device *pdev)
1797{
1798 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1799
1800 if (!uap)
1801 return -ENODEV;
1802
1803 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1804
1805 uap->port.dev = NULL;
1806
1807 return 0;
1808}
1809
1810#endif /* !CONFIG_PPC_PMAC */
1811
1812#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1813
1814static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1815static int __init pmz_console_setup(struct console *co, char *options);
1816
1817static struct console pmz_console = {
1818 .name = PMACZILOG_NAME,
1819 .write = pmz_console_write,
1820 .device = uart_console_device,
1821 .setup = pmz_console_setup,
1822 .flags = CON_PRINTBUFFER,
1823 .index = -1,
1824 .data = &pmz_uart_reg,
1825};
1826
1827#define PMACZILOG_CONSOLE &pmz_console
1828#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1829#define PMACZILOG_CONSOLE (NULL)
1830#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1831
1832/*
1833 * Register the driver, console driver and ports with the serial
1834 * core
1835 */
1836static int __init pmz_register(void)
1837{
1838 pmz_uart_reg.nr = pmz_ports_count;
1839 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1840
1841 /*
1842 * Register this driver with the serial core
1843 */
1844 return uart_register_driver(&pmz_uart_reg);
1845}
1846
1847#ifdef CONFIG_PPC_PMAC
1848
1849static const struct of_device_id pmz_match[] =
1850{
1851 {
1852 .name = "ch-a",
1853 },
1854 {
1855 .name = "ch-b",
1856 },
1857 {},
1858};
1859MODULE_DEVICE_TABLE (of, pmz_match);
1860
1861static struct macio_driver pmz_driver = {
1862 .driver = {
1863 .name = "pmac_zilog",
1864 .owner = THIS_MODULE,
1865 .of_match_table = pmz_match,
1866 },
1867 .probe = pmz_attach,
1868 .remove = pmz_detach,
1869 .suspend = pmz_suspend,
1870 .resume = pmz_resume,
1871};
1872
1873#else
1874
1875static struct platform_driver pmz_driver = {
1876 .remove = __exit_p(pmz_detach),
1877 .driver = {
1878 .name = "scc",
1879 },
1880};
1881
1882#endif /* !CONFIG_PPC_PMAC */
1883
1884static int __init init_pmz(void)
1885{
1886 int rc, i;
1887 printk(KERN_INFO "%s\n", version);
1888
1889 /*
1890 * First, we need to do a direct OF-based probe pass. We
1891 * do that because we want serial console up before the
1892 * macio stuffs calls us back, and since that makes it
1893 * easier to pass the proper number of channels to
1894 * uart_register_driver()
1895 */
1896 if (pmz_ports_count == 0)
1897 pmz_probe();
1898
1899 /*
1900 * Bail early if no port found
1901 */
1902 if (pmz_ports_count == 0)
1903 return -ENODEV;
1904
1905 /*
1906 * Now we register with the serial layer
1907 */
1908 rc = pmz_register();
1909 if (rc) {
1910 printk(KERN_ERR
1911 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1912 "pmac_zilog: Did another serial driver already claim the minors?\n");
1913 /* effectively "pmz_unprobe()" */
1914 for (i=0; i < pmz_ports_count; i++)
1915 pmz_dispose_port(&pmz_ports[i]);
1916 return rc;
1917 }
1918
1919 /*
1920 * Then we register the macio driver itself
1921 */
1922#ifdef CONFIG_PPC_PMAC
1923 return macio_register_driver(&pmz_driver);
1924#else
1925 return platform_driver_probe(&pmz_driver, pmz_attach);
1926#endif
1927}
1928
1929static void __exit exit_pmz(void)
1930{
1931 int i;
1932
1933#ifdef CONFIG_PPC_PMAC
1934 /* Get rid of macio-driver (detach from macio) */
1935 macio_unregister_driver(&pmz_driver);
1936#else
1937 platform_driver_unregister(&pmz_driver);
1938#endif
1939
1940 for (i = 0; i < pmz_ports_count; i++) {
1941 struct uart_pmac_port *uport = &pmz_ports[i];
1942#ifdef CONFIG_PPC_PMAC
1943 if (uport->node != NULL)
1944 pmz_dispose_port(uport);
1945#else
1946 if (uport->pdev != NULL)
1947 pmz_dispose_port(uport);
1948#endif
1949 }
1950 /* Unregister UART driver */
1951 uart_unregister_driver(&pmz_uart_reg);
1952}
1953
1954#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1955
1956static void pmz_console_putchar(struct uart_port *port, int ch)
1957{
1958 struct uart_pmac_port *uap =
1959 container_of(port, struct uart_pmac_port, port);
1960
1961 /* Wait for the transmit buffer to empty. */
1962 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1963 udelay(5);
1964 write_zsdata(uap, ch);
1965}
1966
1967/*
1968 * Print a string to the serial port trying not to disturb
1969 * any possible real use of the port...
1970 */
1971static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1972{
1973 struct uart_pmac_port *uap = &pmz_ports[con->index];
1974 unsigned long flags;
1975
1976 spin_lock_irqsave(&uap->port.lock, flags);
1977
1978 /* Turn of interrupts and enable the transmitter. */
1979 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1980 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1981
1982 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1983
1984 /* Restore the values in the registers. */
1985 write_zsreg(uap, R1, uap->curregs[1]);
1986 /* Don't disable the transmitter. */
1987
1988 spin_unlock_irqrestore(&uap->port.lock, flags);
1989}
1990
1991/*
1992 * Setup the serial console
1993 */
1994static int __init pmz_console_setup(struct console *co, char *options)
1995{
1996 struct uart_pmac_port *uap;
1997 struct uart_port *port;
1998 int baud = 38400;
1999 int bits = 8;
2000 int parity = 'n';
2001 int flow = 'n';
2002 unsigned long pwr_delay;
2003
2004 /*
2005 * XServe's default to 57600 bps
2006 */
2007 if (of_machine_is_compatible("RackMac1,1")
2008 || of_machine_is_compatible("RackMac1,2")
2009 || of_machine_is_compatible("MacRISC4"))
2010 baud = 57600;
2011
2012 /*
2013 * Check whether an invalid uart number has been specified, and
2014 * if so, search for the first available port that does have
2015 * console support.
2016 */
2017 if (co->index >= pmz_ports_count)
2018 co->index = 0;
2019 uap = &pmz_ports[co->index];
2020#ifdef CONFIG_PPC_PMAC
2021 if (uap->node == NULL)
2022 return -ENODEV;
2023#else
2024 if (uap->pdev == NULL)
2025 return -ENODEV;
2026#endif
2027 port = &uap->port;
2028
2029 /*
2030 * Mark port as beeing a console
2031 */
2032 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2033
2034 /*
2035 * Temporary fix for uart layer who didn't setup the spinlock yet
2036 */
2037 spin_lock_init(&port->lock);
2038
2039 /*
2040 * Enable the hardware
2041 */
2042 pwr_delay = __pmz_startup(uap);
2043 if (pwr_delay)
2044 mdelay(pwr_delay);
2045
2046 if (options)
2047 uart_parse_options(options, &baud, &parity, &bits, &flow);
2048
2049 return uart_set_options(port, co, baud, parity, bits, flow);
2050}
2051
2052static int __init pmz_console_init(void)
2053{
2054 /* Probe ports */
2055 pmz_probe();
2056
2057 if (pmz_ports_count == 0)
2058 return -ENODEV;
2059
2060 /* TODO: Autoprobe console based on OF */
2061 /* pmz_console.index = i; */
2062 register_console(&pmz_console);
2063
2064 return 0;
2065
2066}
2067console_initcall(pmz_console_init);
2068#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2069
2070module_init(init_pmz);
2071module_exit(exit_pmz);