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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for PowerMac Z85c30 based ESCC cell found in the
4 * "macio" ASICs of various PowerMac models
5 *
6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
7 *
8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
9 * and drivers/serial/sunzilog.c by David S. Miller
10 *
11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
12 * adapted special tweaks needed for us. I don't think it's worth
13 * merging back those though. The DMA code still has to get in
14 * and once done, I expect that driver to remain fairly stable in
15 * the long term, unless we change the driver model again...
16 *
17 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
18 * - Enable BREAK interrupt
19 * - Add support for sysreq
20 *
21 * TODO: - Add DMA support
22 * - Defer port shutdown to a few seconds after close
23 * - maybe put something right into uap->clk_divisor
24 */
25
26#undef DEBUG
27#undef USE_CTRL_O_SYSRQ
28
29#include <linux/module.h>
30#include <linux/tty.h>
31
32#include <linux/tty_flip.h>
33#include <linux/major.h>
34#include <linux/string.h>
35#include <linux/fcntl.h>
36#include <linux/mm.h>
37#include <linux/kernel.h>
38#include <linux/delay.h>
39#include <linux/init.h>
40#include <linux/console.h>
41#include <linux/adb.h>
42#include <linux/pmu.h>
43#include <linux/bitops.h>
44#include <linux/sysrq.h>
45#include <linux/mutex.h>
46#include <linux/of_address.h>
47#include <linux/of_irq.h>
48#include <asm/sections.h>
49#include <linux/io.h>
50#include <asm/irq.h>
51
52#ifdef CONFIG_PPC_PMAC
53#include <asm/machdep.h>
54#include <asm/pmac_feature.h>
55#include <asm/macio.h>
56#else
57#include <linux/platform_device.h>
58#define of_machine_is_compatible(x) (0)
59#endif
60
61#include <linux/serial.h>
62#include <linux/serial_core.h>
63
64#include "pmac_zilog.h"
65
66MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
67MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
68MODULE_LICENSE("GPL");
69
70#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
71#define PMACZILOG_MAJOR TTY_MAJOR
72#define PMACZILOG_MINOR 64
73#define PMACZILOG_NAME "ttyS"
74#else
75#define PMACZILOG_MAJOR 204
76#define PMACZILOG_MINOR 192
77#define PMACZILOG_NAME "ttyPZ"
78#endif
79
80#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
81#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
82#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
83
84/*
85 * For the sake of early serial console, we can do a pre-probe
86 * (optional) of the ports at rather early boot time.
87 */
88static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
89static int pmz_ports_count;
90
91static struct uart_driver pmz_uart_reg = {
92 .owner = THIS_MODULE,
93 .driver_name = PMACZILOG_NAME,
94 .dev_name = PMACZILOG_NAME,
95 .major = PMACZILOG_MAJOR,
96 .minor = PMACZILOG_MINOR,
97};
98
99
100/*
101 * Load all registers to reprogram the port
102 * This function must only be called when the TX is not busy. The UART
103 * port lock must be held and local interrupts disabled.
104 */
105static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
106{
107 int i;
108
109 /* Let pending transmits finish. */
110 for (i = 0; i < 1000; i++) {
111 unsigned char stat = read_zsreg(uap, R1);
112 if (stat & ALL_SNT)
113 break;
114 udelay(100);
115 }
116
117 ZS_CLEARERR(uap);
118 zssync(uap);
119 ZS_CLEARFIFO(uap);
120 zssync(uap);
121 ZS_CLEARERR(uap);
122
123 /* Disable all interrupts. */
124 write_zsreg(uap, R1,
125 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
126
127 /* Set parity, sync config, stop bits, and clock divisor. */
128 write_zsreg(uap, R4, regs[R4]);
129
130 /* Set misc. TX/RX control bits. */
131 write_zsreg(uap, R10, regs[R10]);
132
133 /* Set TX/RX controls sans the enable bits. */
134 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
135 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
136
137 /* now set R7 "prime" on ESCC */
138 write_zsreg(uap, R15, regs[R15] | EN85C30);
139 write_zsreg(uap, R7, regs[R7P]);
140
141 /* make sure we use R7 "non-prime" on ESCC */
142 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
143
144 /* Synchronous mode config. */
145 write_zsreg(uap, R6, regs[R6]);
146 write_zsreg(uap, R7, regs[R7]);
147
148 /* Disable baud generator. */
149 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
150
151 /* Clock mode control. */
152 write_zsreg(uap, R11, regs[R11]);
153
154 /* Lower and upper byte of baud rate generator divisor. */
155 write_zsreg(uap, R12, regs[R12]);
156 write_zsreg(uap, R13, regs[R13]);
157
158 /* Now rewrite R14, with BRENAB (if set). */
159 write_zsreg(uap, R14, regs[R14]);
160
161 /* Reset external status interrupts. */
162 write_zsreg(uap, R0, RES_EXT_INT);
163 write_zsreg(uap, R0, RES_EXT_INT);
164
165 /* Rewrite R3/R5, this time without enables masked. */
166 write_zsreg(uap, R3, regs[R3]);
167 write_zsreg(uap, R5, regs[R5]);
168
169 /* Rewrite R1, this time without IRQ enabled masked. */
170 write_zsreg(uap, R1, regs[R1]);
171
172 /* Enable interrupts */
173 write_zsreg(uap, R9, regs[R9]);
174}
175
176/*
177 * We do like sunzilog to avoid disrupting pending Tx
178 * Reprogram the Zilog channel HW registers with the copies found in the
179 * software state struct. If the transmitter is busy, we defer this update
180 * until the next TX complete interrupt. Else, we do it right now.
181 *
182 * The UART port lock must be held and local interrupts disabled.
183 */
184static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
185{
186 if (!ZS_REGS_HELD(uap)) {
187 if (ZS_TX_ACTIVE(uap)) {
188 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
189 } else {
190 pmz_debug("pmz: maybe_update_regs: updating\n");
191 pmz_load_zsregs(uap, uap->curregs);
192 }
193 }
194}
195
196static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
197{
198 if (enable) {
199 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
200 if (!ZS_IS_EXTCLK(uap))
201 uap->curregs[1] |= EXT_INT_ENAB;
202 } else {
203 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
204 }
205 write_zsreg(uap, R1, uap->curregs[1]);
206}
207
208static bool pmz_receive_chars(struct uart_pmac_port *uap)
209 __must_hold(&uap->port.lock)
210{
211 struct tty_port *port;
212 unsigned char ch, r1, drop, flag;
213 int loops = 0;
214
215 /* Sanity check, make sure the old bug is no longer happening */
216 if (uap->port.state == NULL) {
217 WARN_ON(1);
218 (void)read_zsdata(uap);
219 return false;
220 }
221 port = &uap->port.state->port;
222
223 while (1) {
224 drop = 0;
225
226 r1 = read_zsreg(uap, R1);
227 ch = read_zsdata(uap);
228
229 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
230 write_zsreg(uap, R0, ERR_RES);
231 zssync(uap);
232 }
233
234 ch &= uap->parity_mask;
235 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
236 uap->flags &= ~PMACZILOG_FLAG_BREAK;
237 }
238
239#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
240#ifdef USE_CTRL_O_SYSRQ
241 /* Handle the SysRq ^O Hack */
242 if (ch == '\x0f') {
243 uap->port.sysrq = jiffies + HZ*5;
244 goto next_char;
245 }
246#endif /* USE_CTRL_O_SYSRQ */
247 if (uap->port.sysrq) {
248 int swallow;
249 uart_port_unlock(&uap->port);
250 swallow = uart_handle_sysrq_char(&uap->port, ch);
251 uart_port_lock(&uap->port);
252 if (swallow)
253 goto next_char;
254 }
255#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
256
257 /* A real serial line, record the character and status. */
258 if (drop)
259 goto next_char;
260
261 flag = TTY_NORMAL;
262 uap->port.icount.rx++;
263
264 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
265 if (r1 & BRK_ABRT) {
266 pmz_debug("pmz: got break !\n");
267 r1 &= ~(PAR_ERR | CRC_ERR);
268 uap->port.icount.brk++;
269 if (uart_handle_break(&uap->port))
270 goto next_char;
271 }
272 else if (r1 & PAR_ERR)
273 uap->port.icount.parity++;
274 else if (r1 & CRC_ERR)
275 uap->port.icount.frame++;
276 if (r1 & Rx_OVR)
277 uap->port.icount.overrun++;
278 r1 &= uap->port.read_status_mask;
279 if (r1 & BRK_ABRT)
280 flag = TTY_BREAK;
281 else if (r1 & PAR_ERR)
282 flag = TTY_PARITY;
283 else if (r1 & CRC_ERR)
284 flag = TTY_FRAME;
285 }
286
287 if (uap->port.ignore_status_mask == 0xff ||
288 (r1 & uap->port.ignore_status_mask) == 0) {
289 tty_insert_flip_char(port, ch, flag);
290 }
291 if (r1 & Rx_OVR)
292 tty_insert_flip_char(port, 0, TTY_OVERRUN);
293 next_char:
294 /* We can get stuck in an infinite loop getting char 0 when the
295 * line is in a wrong HW state, we break that here.
296 * When that happens, I disable the receive side of the driver.
297 * Note that what I've been experiencing is a real irq loop where
298 * I'm getting flooded regardless of the actual port speed.
299 * Something strange is going on with the HW
300 */
301 if ((++loops) > 1000)
302 goto flood;
303 ch = read_zsreg(uap, R0);
304 if (!(ch & Rx_CH_AV))
305 break;
306 }
307
308 return true;
309 flood:
310 pmz_interrupt_control(uap, 0);
311 pmz_error("pmz: rx irq flood !\n");
312 return true;
313}
314
315static void pmz_status_handle(struct uart_pmac_port *uap)
316{
317 unsigned char status;
318
319 status = read_zsreg(uap, R0);
320 write_zsreg(uap, R0, RES_EXT_INT);
321 zssync(uap);
322
323 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
324 if (status & SYNC_HUNT)
325 uap->port.icount.dsr++;
326
327 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
328 * But it does not tell us which bit has changed, we have to keep
329 * track of this ourselves.
330 * The CTS input is inverted for some reason. -- paulus
331 */
332 if ((status ^ uap->prev_status) & DCD)
333 uart_handle_dcd_change(&uap->port,
334 (status & DCD));
335 if ((status ^ uap->prev_status) & CTS)
336 uart_handle_cts_change(&uap->port,
337 !(status & CTS));
338
339 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
340 }
341
342 if (status & BRK_ABRT)
343 uap->flags |= PMACZILOG_FLAG_BREAK;
344
345 uap->prev_status = status;
346}
347
348static void pmz_transmit_chars(struct uart_pmac_port *uap)
349{
350 struct circ_buf *xmit;
351
352 if (ZS_IS_CONS(uap)) {
353 unsigned char status = read_zsreg(uap, R0);
354
355 /* TX still busy? Just wait for the next TX done interrupt.
356 *
357 * It can occur because of how we do serial console writes. It would
358 * be nice to transmit console writes just like we normally would for
359 * a TTY line. (ie. buffered and TX interrupt driven). That is not
360 * easy because console writes cannot sleep. One solution might be
361 * to poll on enough port->xmit space becoming free. -DaveM
362 */
363 if (!(status & Tx_BUF_EMP))
364 return;
365 }
366
367 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
368
369 if (ZS_REGS_HELD(uap)) {
370 pmz_load_zsregs(uap, uap->curregs);
371 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
372 }
373
374 if (ZS_TX_STOPPED(uap)) {
375 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
376 goto ack_tx_int;
377 }
378
379 /* Under some circumstances, we see interrupts reported for
380 * a closed channel. The interrupt mask in R1 is clear, but
381 * R3 still signals the interrupts and we see them when taking
382 * an interrupt for the other channel (this could be a qemu
383 * bug but since the ESCC doc doesn't specify precsiely whether
384 * R3 interrup status bits are masked by R1 interrupt enable
385 * bits, better safe than sorry). --BenH.
386 */
387 if (!ZS_IS_OPEN(uap))
388 goto ack_tx_int;
389
390 if (uap->port.x_char) {
391 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
392 write_zsdata(uap, uap->port.x_char);
393 zssync(uap);
394 uap->port.icount.tx++;
395 uap->port.x_char = 0;
396 return;
397 }
398
399 if (uap->port.state == NULL)
400 goto ack_tx_int;
401 xmit = &uap->port.state->xmit;
402 if (uart_circ_empty(xmit)) {
403 uart_write_wakeup(&uap->port);
404 goto ack_tx_int;
405 }
406 if (uart_tx_stopped(&uap->port))
407 goto ack_tx_int;
408
409 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
410 write_zsdata(uap, xmit->buf[xmit->tail]);
411 zssync(uap);
412
413 uart_xmit_advance(&uap->port, 1);
414
415 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
416 uart_write_wakeup(&uap->port);
417
418 return;
419
420ack_tx_int:
421 write_zsreg(uap, R0, RES_Tx_P);
422 zssync(uap);
423}
424
425/* Hrm... we register that twice, fixme later.... */
426static irqreturn_t pmz_interrupt(int irq, void *dev_id)
427{
428 struct uart_pmac_port *uap = dev_id;
429 struct uart_pmac_port *uap_a;
430 struct uart_pmac_port *uap_b;
431 int rc = IRQ_NONE;
432 bool push;
433 u8 r3;
434
435 uap_a = pmz_get_port_A(uap);
436 uap_b = uap_a->mate;
437
438 uart_port_lock(&uap_a->port);
439 r3 = read_zsreg(uap_a, R3);
440
441 /* Channel A */
442 push = false;
443 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
444 if (!ZS_IS_OPEN(uap_a)) {
445 pmz_debug("ChanA interrupt while not open !\n");
446 goto skip_a;
447 }
448 write_zsreg(uap_a, R0, RES_H_IUS);
449 zssync(uap_a);
450 if (r3 & CHAEXT)
451 pmz_status_handle(uap_a);
452 if (r3 & CHARxIP)
453 push = pmz_receive_chars(uap_a);
454 if (r3 & CHATxIP)
455 pmz_transmit_chars(uap_a);
456 rc = IRQ_HANDLED;
457 }
458 skip_a:
459 uart_port_unlock(&uap_a->port);
460 if (push)
461 tty_flip_buffer_push(&uap->port.state->port);
462
463 if (!uap_b)
464 goto out;
465
466 uart_port_lock(&uap_b->port);
467 push = false;
468 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
469 if (!ZS_IS_OPEN(uap_b)) {
470 pmz_debug("ChanB interrupt while not open !\n");
471 goto skip_b;
472 }
473 write_zsreg(uap_b, R0, RES_H_IUS);
474 zssync(uap_b);
475 if (r3 & CHBEXT)
476 pmz_status_handle(uap_b);
477 if (r3 & CHBRxIP)
478 push = pmz_receive_chars(uap_b);
479 if (r3 & CHBTxIP)
480 pmz_transmit_chars(uap_b);
481 rc = IRQ_HANDLED;
482 }
483 skip_b:
484 uart_port_unlock(&uap_b->port);
485 if (push)
486 tty_flip_buffer_push(&uap->port.state->port);
487
488 out:
489 return rc;
490}
491
492/*
493 * Peek the status register, lock not held by caller
494 */
495static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
496{
497 unsigned long flags;
498 u8 status;
499
500 uart_port_lock_irqsave(&uap->port, &flags);
501 status = read_zsreg(uap, R0);
502 uart_port_unlock_irqrestore(&uap->port, flags);
503
504 return status;
505}
506
507/*
508 * Check if transmitter is empty
509 * The port lock is not held.
510 */
511static unsigned int pmz_tx_empty(struct uart_port *port)
512{
513 unsigned char status;
514
515 status = pmz_peek_status(to_pmz(port));
516 if (status & Tx_BUF_EMP)
517 return TIOCSER_TEMT;
518 return 0;
519}
520
521/*
522 * Set Modem Control (RTS & DTR) bits
523 * The port lock is held and interrupts are disabled.
524 * Note: Shall we really filter out RTS on external ports or
525 * should that be dealt at higher level only ?
526 */
527static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
528{
529 struct uart_pmac_port *uap = to_pmz(port);
530 unsigned char set_bits, clear_bits;
531
532 /* Do nothing for irda for now... */
533 if (ZS_IS_IRDA(uap))
534 return;
535 /* We get called during boot with a port not up yet */
536 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
537 return;
538
539 set_bits = clear_bits = 0;
540
541 if (ZS_IS_INTMODEM(uap)) {
542 if (mctrl & TIOCM_RTS)
543 set_bits |= RTS;
544 else
545 clear_bits |= RTS;
546 }
547 if (mctrl & TIOCM_DTR)
548 set_bits |= DTR;
549 else
550 clear_bits |= DTR;
551
552 /* NOTE: Not subject to 'transmitter active' rule. */
553 uap->curregs[R5] |= set_bits;
554 uap->curregs[R5] &= ~clear_bits;
555
556 write_zsreg(uap, R5, uap->curregs[R5]);
557 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
558 set_bits, clear_bits, uap->curregs[R5]);
559 zssync(uap);
560}
561
562/*
563 * Get Modem Control bits (only the input ones, the core will
564 * or that with a cached value of the control ones)
565 * The port lock is held and interrupts are disabled.
566 */
567static unsigned int pmz_get_mctrl(struct uart_port *port)
568{
569 struct uart_pmac_port *uap = to_pmz(port);
570 unsigned char status;
571 unsigned int ret;
572
573 status = read_zsreg(uap, R0);
574
575 ret = 0;
576 if (status & DCD)
577 ret |= TIOCM_CAR;
578 if (status & SYNC_HUNT)
579 ret |= TIOCM_DSR;
580 if (!(status & CTS))
581 ret |= TIOCM_CTS;
582
583 return ret;
584}
585
586/*
587 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
588 * though for DMA, we will have to do a bit more.
589 * The port lock is held and interrupts are disabled.
590 */
591static void pmz_stop_tx(struct uart_port *port)
592{
593 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
594}
595
596/*
597 * Kick the Tx side.
598 * The port lock is held and interrupts are disabled.
599 */
600static void pmz_start_tx(struct uart_port *port)
601{
602 struct uart_pmac_port *uap = to_pmz(port);
603 unsigned char status;
604
605 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
606 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
607
608 status = read_zsreg(uap, R0);
609
610 /* TX busy? Just wait for the TX done interrupt. */
611 if (!(status & Tx_BUF_EMP))
612 return;
613
614 /* Send the first character to jump-start the TX done
615 * IRQ sending engine.
616 */
617 if (port->x_char) {
618 write_zsdata(uap, port->x_char);
619 zssync(uap);
620 port->icount.tx++;
621 port->x_char = 0;
622 } else {
623 struct circ_buf *xmit = &port->state->xmit;
624
625 if (uart_circ_empty(xmit))
626 return;
627 write_zsdata(uap, xmit->buf[xmit->tail]);
628 zssync(uap);
629 uart_xmit_advance(port, 1);
630
631 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
632 uart_write_wakeup(&uap->port);
633 }
634}
635
636/*
637 * Stop Rx side, basically disable emitting of
638 * Rx interrupts on the port. We don't disable the rx
639 * side of the chip proper though
640 * The port lock is held.
641 */
642static void pmz_stop_rx(struct uart_port *port)
643{
644 struct uart_pmac_port *uap = to_pmz(port);
645
646 /* Disable all RX interrupts. */
647 uap->curregs[R1] &= ~RxINT_MASK;
648 pmz_maybe_update_regs(uap);
649}
650
651/*
652 * Enable modem status change interrupts
653 * The port lock is held.
654 */
655static void pmz_enable_ms(struct uart_port *port)
656{
657 struct uart_pmac_port *uap = to_pmz(port);
658 unsigned char new_reg;
659
660 if (ZS_IS_IRDA(uap))
661 return;
662 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
663 if (new_reg != uap->curregs[R15]) {
664 uap->curregs[R15] = new_reg;
665
666 /* NOTE: Not subject to 'transmitter active' rule. */
667 write_zsreg(uap, R15, uap->curregs[R15]);
668 }
669}
670
671/*
672 * Control break state emission
673 * The port lock is not held.
674 */
675static void pmz_break_ctl(struct uart_port *port, int break_state)
676{
677 struct uart_pmac_port *uap = to_pmz(port);
678 unsigned char set_bits, clear_bits, new_reg;
679 unsigned long flags;
680
681 set_bits = clear_bits = 0;
682
683 if (break_state)
684 set_bits |= SND_BRK;
685 else
686 clear_bits |= SND_BRK;
687
688 uart_port_lock_irqsave(port, &flags);
689
690 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
691 if (new_reg != uap->curregs[R5]) {
692 uap->curregs[R5] = new_reg;
693 write_zsreg(uap, R5, uap->curregs[R5]);
694 }
695
696 uart_port_unlock_irqrestore(port, flags);
697}
698
699#ifdef CONFIG_PPC_PMAC
700
701/*
702 * Turn power on or off to the SCC and associated stuff
703 * (port drivers, modem, IR port, etc.)
704 * Returns the number of milliseconds we should wait before
705 * trying to use the port.
706 */
707static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
708{
709 int delay = 0;
710 int rc;
711
712 if (state) {
713 rc = pmac_call_feature(
714 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
715 pmz_debug("port power on result: %d\n", rc);
716 if (ZS_IS_INTMODEM(uap)) {
717 rc = pmac_call_feature(
718 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
719 delay = 2500; /* wait for 2.5s before using */
720 pmz_debug("modem power result: %d\n", rc);
721 }
722 } else {
723 /* TODO: Make that depend on a timer, don't power down
724 * immediately
725 */
726 if (ZS_IS_INTMODEM(uap)) {
727 rc = pmac_call_feature(
728 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
729 pmz_debug("port power off result: %d\n", rc);
730 }
731 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
732 }
733 return delay;
734}
735
736#else
737
738static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
739{
740 return 0;
741}
742
743#endif /* !CONFIG_PPC_PMAC */
744
745/*
746 * FixZeroBug....Works around a bug in the SCC receiving channel.
747 * Inspired from Darwin code, 15 Sept. 2000 -DanM
748 *
749 * The following sequence prevents a problem that is seen with O'Hare ASICs
750 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
751 * at the input to the receiver becomes 'stuck' and locks up the receiver.
752 * This problem can occur as a result of a zero bit at the receiver input
753 * coincident with any of the following events:
754 *
755 * The SCC is initialized (hardware or software).
756 * A framing error is detected.
757 * The clocking option changes from synchronous or X1 asynchronous
758 * clocking to X16, X32, or X64 asynchronous clocking.
759 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
760 *
761 * This workaround attempts to recover from the lockup condition by placing
762 * the SCC in synchronous loopback mode with a fast clock before programming
763 * any of the asynchronous modes.
764 */
765static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
766{
767 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
768 zssync(uap);
769 udelay(10);
770 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
771 zssync(uap);
772
773 write_zsreg(uap, 4, X1CLK | MONSYNC);
774 write_zsreg(uap, 3, Rx8);
775 write_zsreg(uap, 5, Tx8 | RTS);
776 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
777 write_zsreg(uap, 11, RCBR | TCBR);
778 write_zsreg(uap, 12, 0);
779 write_zsreg(uap, 13, 0);
780 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
781 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
782 write_zsreg(uap, 3, Rx8 | RxENABLE);
783 write_zsreg(uap, 0, RES_EXT_INT);
784 write_zsreg(uap, 0, RES_EXT_INT);
785 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
786
787 /* The channel should be OK now, but it is probably receiving
788 * loopback garbage.
789 * Switch to asynchronous mode, disable the receiver,
790 * and discard everything in the receive buffer.
791 */
792 write_zsreg(uap, 9, NV);
793 write_zsreg(uap, 4, X16CLK | SB_MASK);
794 write_zsreg(uap, 3, Rx8);
795
796 while (read_zsreg(uap, 0) & Rx_CH_AV) {
797 (void)read_zsreg(uap, 8);
798 write_zsreg(uap, 0, RES_EXT_INT);
799 write_zsreg(uap, 0, ERR_RES);
800 }
801}
802
803/*
804 * Real startup routine, powers up the hardware and sets up
805 * the SCC. Returns a delay in ms where you need to wait before
806 * actually using the port, this is typically the internal modem
807 * powerup delay. This routine expect the lock to be taken.
808 */
809static int __pmz_startup(struct uart_pmac_port *uap)
810{
811 int pwr_delay = 0;
812
813 memset(&uap->curregs, 0, sizeof(uap->curregs));
814
815 /* Power up the SCC & underlying hardware (modem/irda) */
816 pwr_delay = pmz_set_scc_power(uap, 1);
817
818 /* Nice buggy HW ... */
819 pmz_fix_zero_bug_scc(uap);
820
821 /* Reset the channel */
822 uap->curregs[R9] = 0;
823 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
824 zssync(uap);
825 udelay(10);
826 write_zsreg(uap, 9, 0);
827 zssync(uap);
828
829 /* Clear the interrupt registers */
830 write_zsreg(uap, R1, 0);
831 write_zsreg(uap, R0, ERR_RES);
832 write_zsreg(uap, R0, ERR_RES);
833 write_zsreg(uap, R0, RES_H_IUS);
834 write_zsreg(uap, R0, RES_H_IUS);
835
836 /* Setup some valid baud rate */
837 uap->curregs[R4] = X16CLK | SB1;
838 uap->curregs[R3] = Rx8;
839 uap->curregs[R5] = Tx8 | RTS;
840 if (!ZS_IS_IRDA(uap))
841 uap->curregs[R5] |= DTR;
842 uap->curregs[R12] = 0;
843 uap->curregs[R13] = 0;
844 uap->curregs[R14] = BRENAB;
845
846 /* Clear handshaking, enable BREAK interrupts */
847 uap->curregs[R15] = BRKIE;
848
849 /* Master interrupt enable */
850 uap->curregs[R9] |= NV | MIE;
851
852 pmz_load_zsregs(uap, uap->curregs);
853
854 /* Enable receiver and transmitter. */
855 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
856 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
857
858 /* Remember status for DCD/CTS changes */
859 uap->prev_status = read_zsreg(uap, R0);
860
861 return pwr_delay;
862}
863
864static void pmz_irda_reset(struct uart_pmac_port *uap)
865{
866 unsigned long flags;
867
868 uart_port_lock_irqsave(&uap->port, &flags);
869 uap->curregs[R5] |= DTR;
870 write_zsreg(uap, R5, uap->curregs[R5]);
871 zssync(uap);
872 uart_port_unlock_irqrestore(&uap->port, flags);
873 msleep(110);
874
875 uart_port_lock_irqsave(&uap->port, &flags);
876 uap->curregs[R5] &= ~DTR;
877 write_zsreg(uap, R5, uap->curregs[R5]);
878 zssync(uap);
879 uart_port_unlock_irqrestore(&uap->port, flags);
880 msleep(10);
881}
882
883/*
884 * This is the "normal" startup routine, using the above one
885 * wrapped with the lock and doing a schedule delay
886 */
887static int pmz_startup(struct uart_port *port)
888{
889 struct uart_pmac_port *uap = to_pmz(port);
890 unsigned long flags;
891 int pwr_delay = 0;
892
893 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
894
895 /* A console is never powered down. Else, power up and
896 * initialize the chip
897 */
898 if (!ZS_IS_CONS(uap)) {
899 uart_port_lock_irqsave(port, &flags);
900 pwr_delay = __pmz_startup(uap);
901 uart_port_unlock_irqrestore(port, flags);
902 }
903 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
904 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
905 uap->irq_name, uap)) {
906 pmz_error("Unable to register zs interrupt handler.\n");
907 pmz_set_scc_power(uap, 0);
908 return -ENXIO;
909 }
910
911 /* Right now, we deal with delay by blocking here, I'll be
912 * smarter later on
913 */
914 if (pwr_delay != 0) {
915 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
916 msleep(pwr_delay);
917 }
918
919 /* IrDA reset is done now */
920 if (ZS_IS_IRDA(uap))
921 pmz_irda_reset(uap);
922
923 /* Enable interrupt requests for the channel */
924 uart_port_lock_irqsave(port, &flags);
925 pmz_interrupt_control(uap, 1);
926 uart_port_unlock_irqrestore(port, flags);
927
928 return 0;
929}
930
931static void pmz_shutdown(struct uart_port *port)
932{
933 struct uart_pmac_port *uap = to_pmz(port);
934 unsigned long flags;
935
936 uart_port_lock_irqsave(port, &flags);
937
938 /* Disable interrupt requests for the channel */
939 pmz_interrupt_control(uap, 0);
940
941 if (!ZS_IS_CONS(uap)) {
942 /* Disable receiver and transmitter */
943 uap->curregs[R3] &= ~RxENABLE;
944 uap->curregs[R5] &= ~TxENABLE;
945
946 /* Disable break assertion */
947 uap->curregs[R5] &= ~SND_BRK;
948 pmz_maybe_update_regs(uap);
949 }
950
951 uart_port_unlock_irqrestore(port, flags);
952
953 /* Release interrupt handler */
954 free_irq(uap->port.irq, uap);
955
956 uart_port_lock_irqsave(port, &flags);
957
958 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
959
960 if (!ZS_IS_CONS(uap))
961 pmz_set_scc_power(uap, 0); /* Shut the chip down */
962
963 uart_port_unlock_irqrestore(port, flags);
964}
965
966/* Shared by TTY driver and serial console setup. The port lock is held
967 * and local interrupts are disabled.
968 */
969static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
970 unsigned int iflag, unsigned long baud)
971{
972 int brg;
973
974 /* Switch to external clocking for IrDA high clock rates. That
975 * code could be re-used for Midi interfaces with different
976 * multipliers
977 */
978 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
979 uap->curregs[R4] = X1CLK;
980 uap->curregs[R11] = RCTRxCP | TCTRxCP;
981 uap->curregs[R14] = 0; /* BRG off */
982 uap->curregs[R12] = 0;
983 uap->curregs[R13] = 0;
984 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
985 } else {
986 switch (baud) {
987 case ZS_CLOCK/16: /* 230400 */
988 uap->curregs[R4] = X16CLK;
989 uap->curregs[R11] = 0;
990 uap->curregs[R14] = 0;
991 break;
992 case ZS_CLOCK/32: /* 115200 */
993 uap->curregs[R4] = X32CLK;
994 uap->curregs[R11] = 0;
995 uap->curregs[R14] = 0;
996 break;
997 default:
998 uap->curregs[R4] = X16CLK;
999 uap->curregs[R11] = TCBR | RCBR;
1000 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1001 uap->curregs[R12] = (brg & 255);
1002 uap->curregs[R13] = ((brg >> 8) & 255);
1003 uap->curregs[R14] = BRENAB;
1004 }
1005 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1006 }
1007
1008 /* Character size, stop bits, and parity. */
1009 uap->curregs[3] &= ~RxN_MASK;
1010 uap->curregs[5] &= ~TxN_MASK;
1011
1012 switch (cflag & CSIZE) {
1013 case CS5:
1014 uap->curregs[3] |= Rx5;
1015 uap->curregs[5] |= Tx5;
1016 uap->parity_mask = 0x1f;
1017 break;
1018 case CS6:
1019 uap->curregs[3] |= Rx6;
1020 uap->curregs[5] |= Tx6;
1021 uap->parity_mask = 0x3f;
1022 break;
1023 case CS7:
1024 uap->curregs[3] |= Rx7;
1025 uap->curregs[5] |= Tx7;
1026 uap->parity_mask = 0x7f;
1027 break;
1028 case CS8:
1029 default:
1030 uap->curregs[3] |= Rx8;
1031 uap->curregs[5] |= Tx8;
1032 uap->parity_mask = 0xff;
1033 break;
1034 }
1035 uap->curregs[4] &= ~(SB_MASK);
1036 if (cflag & CSTOPB)
1037 uap->curregs[4] |= SB2;
1038 else
1039 uap->curregs[4] |= SB1;
1040 if (cflag & PARENB)
1041 uap->curregs[4] |= PAR_ENAB;
1042 else
1043 uap->curregs[4] &= ~PAR_ENAB;
1044 if (!(cflag & PARODD))
1045 uap->curregs[4] |= PAR_EVEN;
1046 else
1047 uap->curregs[4] &= ~PAR_EVEN;
1048
1049 uap->port.read_status_mask = Rx_OVR;
1050 if (iflag & INPCK)
1051 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1052 if (iflag & (IGNBRK | BRKINT | PARMRK))
1053 uap->port.read_status_mask |= BRK_ABRT;
1054
1055 uap->port.ignore_status_mask = 0;
1056 if (iflag & IGNPAR)
1057 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1058 if (iflag & IGNBRK) {
1059 uap->port.ignore_status_mask |= BRK_ABRT;
1060 if (iflag & IGNPAR)
1061 uap->port.ignore_status_mask |= Rx_OVR;
1062 }
1063
1064 if ((cflag & CREAD) == 0)
1065 uap->port.ignore_status_mask = 0xff;
1066}
1067
1068
1069/*
1070 * Set the irda codec on the imac to the specified baud rate.
1071 */
1072static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1073{
1074 u8 cmdbyte;
1075 int t, version;
1076
1077 switch (*baud) {
1078 /* SIR modes */
1079 case 2400:
1080 cmdbyte = 0x53;
1081 break;
1082 case 4800:
1083 cmdbyte = 0x52;
1084 break;
1085 case 9600:
1086 cmdbyte = 0x51;
1087 break;
1088 case 19200:
1089 cmdbyte = 0x50;
1090 break;
1091 case 38400:
1092 cmdbyte = 0x4f;
1093 break;
1094 case 57600:
1095 cmdbyte = 0x4e;
1096 break;
1097 case 115200:
1098 cmdbyte = 0x4d;
1099 break;
1100 /* The FIR modes aren't really supported at this point, how
1101 * do we select the speed ? via the FCR on KeyLargo ?
1102 */
1103 case 1152000:
1104 cmdbyte = 0;
1105 break;
1106 case 4000000:
1107 cmdbyte = 0;
1108 break;
1109 default: /* 9600 */
1110 cmdbyte = 0x51;
1111 *baud = 9600;
1112 break;
1113 }
1114
1115 /* Wait for transmitter to drain */
1116 t = 10000;
1117 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1118 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1119 if (--t <= 0) {
1120 pmz_error("transmitter didn't drain\n");
1121 return;
1122 }
1123 udelay(10);
1124 }
1125
1126 /* Drain the receiver too */
1127 t = 100;
1128 (void)read_zsdata(uap);
1129 (void)read_zsdata(uap);
1130 (void)read_zsdata(uap);
1131 mdelay(10);
1132 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1133 read_zsdata(uap);
1134 mdelay(10);
1135 if (--t <= 0) {
1136 pmz_error("receiver didn't drain\n");
1137 return;
1138 }
1139 }
1140
1141 /* Switch to command mode */
1142 uap->curregs[R5] |= DTR;
1143 write_zsreg(uap, R5, uap->curregs[R5]);
1144 zssync(uap);
1145 mdelay(1);
1146
1147 /* Switch SCC to 19200 */
1148 pmz_convert_to_zs(uap, CS8, 0, 19200);
1149 pmz_load_zsregs(uap, uap->curregs);
1150 mdelay(1);
1151
1152 /* Write get_version command byte */
1153 write_zsdata(uap, 1);
1154 t = 5000;
1155 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1156 if (--t <= 0) {
1157 pmz_error("irda_setup timed out on get_version byte\n");
1158 goto out;
1159 }
1160 udelay(10);
1161 }
1162 version = read_zsdata(uap);
1163
1164 if (version < 4) {
1165 pmz_info("IrDA: dongle version %d not supported\n", version);
1166 goto out;
1167 }
1168
1169 /* Send speed mode */
1170 write_zsdata(uap, cmdbyte);
1171 t = 5000;
1172 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1173 if (--t <= 0) {
1174 pmz_error("irda_setup timed out on speed mode byte\n");
1175 goto out;
1176 }
1177 udelay(10);
1178 }
1179 t = read_zsdata(uap);
1180 if (t != cmdbyte)
1181 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1182
1183 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1184 *baud, version);
1185
1186 (void)read_zsdata(uap);
1187 (void)read_zsdata(uap);
1188 (void)read_zsdata(uap);
1189
1190 out:
1191 /* Switch back to data mode */
1192 uap->curregs[R5] &= ~DTR;
1193 write_zsreg(uap, R5, uap->curregs[R5]);
1194 zssync(uap);
1195
1196 (void)read_zsdata(uap);
1197 (void)read_zsdata(uap);
1198 (void)read_zsdata(uap);
1199}
1200
1201
1202static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1203 const struct ktermios *old)
1204{
1205 struct uart_pmac_port *uap = to_pmz(port);
1206 unsigned long baud;
1207
1208 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1209 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1210 * about the FIR mode and high speed modes. So these are unused. For
1211 * implementing proper support for these, we should probably add some
1212 * DMA as well, at least on the Rx side, which isn't a simple thing
1213 * at this point.
1214 */
1215 if (ZS_IS_IRDA(uap)) {
1216 /* Calc baud rate */
1217 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1218 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1219 /* Cet the irda codec to the right rate */
1220 pmz_irda_setup(uap, &baud);
1221 /* Set final baud rate */
1222 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1223 pmz_load_zsregs(uap, uap->curregs);
1224 zssync(uap);
1225 } else {
1226 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1227 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1228 /* Make sure modem status interrupts are correctly configured */
1229 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1230 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1231 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1232 } else {
1233 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1234 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1235 }
1236
1237 /* Load registers to the chip */
1238 pmz_maybe_update_regs(uap);
1239 }
1240 uart_update_timeout(port, termios->c_cflag, baud);
1241}
1242
1243/* The port lock is not held. */
1244static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1245 const struct ktermios *old)
1246{
1247 struct uart_pmac_port *uap = to_pmz(port);
1248 unsigned long flags;
1249
1250 uart_port_lock_irqsave(port, &flags);
1251
1252 /* Disable IRQs on the port */
1253 pmz_interrupt_control(uap, 0);
1254
1255 /* Setup new port configuration */
1256 __pmz_set_termios(port, termios, old);
1257
1258 /* Re-enable IRQs on the port */
1259 if (ZS_IS_OPEN(uap))
1260 pmz_interrupt_control(uap, 1);
1261
1262 uart_port_unlock_irqrestore(port, flags);
1263}
1264
1265static const char *pmz_type(struct uart_port *port)
1266{
1267 struct uart_pmac_port *uap = to_pmz(port);
1268
1269 if (ZS_IS_IRDA(uap))
1270 return "Z85c30 ESCC - Infrared port";
1271 else if (ZS_IS_INTMODEM(uap))
1272 return "Z85c30 ESCC - Internal modem";
1273 return "Z85c30 ESCC - Serial port";
1274}
1275
1276/* We do not request/release mappings of the registers here, this
1277 * happens at early serial probe time.
1278 */
1279static void pmz_release_port(struct uart_port *port)
1280{
1281}
1282
1283static int pmz_request_port(struct uart_port *port)
1284{
1285 return 0;
1286}
1287
1288/* These do not need to do anything interesting either. */
1289static void pmz_config_port(struct uart_port *port, int flags)
1290{
1291}
1292
1293/* We do not support letting the user mess with the divisor, IRQ, etc. */
1294static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1295{
1296 return -EINVAL;
1297}
1298
1299#ifdef CONFIG_CONSOLE_POLL
1300
1301static int pmz_poll_get_char(struct uart_port *port)
1302{
1303 struct uart_pmac_port *uap =
1304 container_of(port, struct uart_pmac_port, port);
1305 int tries = 2;
1306
1307 while (tries) {
1308 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
1309 return read_zsdata(uap);
1310 if (tries--)
1311 udelay(5);
1312 }
1313
1314 return NO_POLL_CHAR;
1315}
1316
1317static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1318{
1319 struct uart_pmac_port *uap =
1320 container_of(port, struct uart_pmac_port, port);
1321
1322 /* Wait for the transmit buffer to empty. */
1323 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1324 udelay(5);
1325 write_zsdata(uap, c);
1326}
1327
1328#endif /* CONFIG_CONSOLE_POLL */
1329
1330static const struct uart_ops pmz_pops = {
1331 .tx_empty = pmz_tx_empty,
1332 .set_mctrl = pmz_set_mctrl,
1333 .get_mctrl = pmz_get_mctrl,
1334 .stop_tx = pmz_stop_tx,
1335 .start_tx = pmz_start_tx,
1336 .stop_rx = pmz_stop_rx,
1337 .enable_ms = pmz_enable_ms,
1338 .break_ctl = pmz_break_ctl,
1339 .startup = pmz_startup,
1340 .shutdown = pmz_shutdown,
1341 .set_termios = pmz_set_termios,
1342 .type = pmz_type,
1343 .release_port = pmz_release_port,
1344 .request_port = pmz_request_port,
1345 .config_port = pmz_config_port,
1346 .verify_port = pmz_verify_port,
1347#ifdef CONFIG_CONSOLE_POLL
1348 .poll_get_char = pmz_poll_get_char,
1349 .poll_put_char = pmz_poll_put_char,
1350#endif
1351};
1352
1353#ifdef CONFIG_PPC_PMAC
1354
1355/*
1356 * Setup one port structure after probing, HW is down at this point,
1357 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1358 * register our console before uart_add_one_port() is called
1359 */
1360static int __init pmz_init_port(struct uart_pmac_port *uap)
1361{
1362 struct device_node *np = uap->node;
1363 const char *conn;
1364 const struct slot_names_prop {
1365 int count;
1366 char name[1];
1367 } *slots;
1368 int len;
1369 struct resource r_ports;
1370
1371 /*
1372 * Request & map chip registers
1373 */
1374 if (of_address_to_resource(np, 0, &r_ports))
1375 return -ENODEV;
1376 uap->port.mapbase = r_ports.start;
1377 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1378
1379 uap->control_reg = uap->port.membase;
1380 uap->data_reg = uap->control_reg + 0x10;
1381
1382 /*
1383 * Detect port type
1384 */
1385 if (of_device_is_compatible(np, "cobalt"))
1386 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1387 conn = of_get_property(np, "AAPL,connector", &len);
1388 if (conn && (strcmp(conn, "infrared") == 0))
1389 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1390 uap->port_type = PMAC_SCC_ASYNC;
1391 /* 1999 Powerbook G3 has slot-names property instead */
1392 slots = of_get_property(np, "slot-names", &len);
1393 if (slots && slots->count > 0) {
1394 if (strcmp(slots->name, "IrDA") == 0)
1395 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1396 else if (strcmp(slots->name, "Modem") == 0)
1397 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1398 }
1399 if (ZS_IS_IRDA(uap))
1400 uap->port_type = PMAC_SCC_IRDA;
1401 if (ZS_IS_INTMODEM(uap)) {
1402 struct device_node* i2c_modem =
1403 of_find_node_by_name(NULL, "i2c-modem");
1404 if (i2c_modem) {
1405 const char* mid =
1406 of_get_property(i2c_modem, "modem-id", NULL);
1407 if (mid) switch(*mid) {
1408 case 0x04 :
1409 case 0x05 :
1410 case 0x07 :
1411 case 0x08 :
1412 case 0x0b :
1413 case 0x0c :
1414 uap->port_type = PMAC_SCC_I2S1;
1415 }
1416 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1417 mid ? (*mid) : 0);
1418 of_node_put(i2c_modem);
1419 } else {
1420 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1421 }
1422 }
1423
1424 /*
1425 * Init remaining bits of "port" structure
1426 */
1427 uap->port.iotype = UPIO_MEM;
1428 uap->port.irq = irq_of_parse_and_map(np, 0);
1429 uap->port.uartclk = ZS_CLOCK;
1430 uap->port.fifosize = 1;
1431 uap->port.ops = &pmz_pops;
1432 uap->port.type = PORT_PMAC_ZILOG;
1433 uap->port.flags = 0;
1434
1435 /*
1436 * Fixup for the port on Gatwick for which the device-tree has
1437 * missing interrupts. Normally, the macio_dev would contain
1438 * fixed up interrupt info, but we use the device-tree directly
1439 * here due to early probing so we need the fixup too.
1440 */
1441 if (uap->port.irq == 0 &&
1442 np->parent && np->parent->parent &&
1443 of_device_is_compatible(np->parent->parent, "gatwick")) {
1444 /* IRQs on gatwick are offset by 64 */
1445 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1446 }
1447
1448 /* Setup some valid baud rate information in the register
1449 * shadows so we don't write crap there before baud rate is
1450 * first initialized.
1451 */
1452 pmz_convert_to_zs(uap, CS8, 0, 9600);
1453
1454 return 0;
1455}
1456
1457/*
1458 * Get rid of a port on module removal
1459 */
1460static void pmz_dispose_port(struct uart_pmac_port *uap)
1461{
1462 struct device_node *np;
1463
1464 np = uap->node;
1465 iounmap(uap->control_reg);
1466 uap->node = NULL;
1467 of_node_put(np);
1468 memset(uap, 0, sizeof(struct uart_pmac_port));
1469}
1470
1471/*
1472 * Called upon match with an escc node in the device-tree.
1473 */
1474static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1475{
1476 struct uart_pmac_port *uap;
1477 int i;
1478
1479 /* Iterate the pmz_ports array to find a matching entry
1480 */
1481 for (i = 0; i < MAX_ZS_PORTS; i++)
1482 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1483 break;
1484 if (i >= MAX_ZS_PORTS)
1485 return -ENODEV;
1486
1487
1488 uap = &pmz_ports[i];
1489 uap->dev = mdev;
1490 uap->port.dev = &mdev->ofdev.dev;
1491 dev_set_drvdata(&mdev->ofdev.dev, uap);
1492
1493 /* We still activate the port even when failing to request resources
1494 * to work around bugs in ancient Apple device-trees
1495 */
1496 if (macio_request_resources(uap->dev, "pmac_zilog"))
1497 printk(KERN_WARNING "%pOFn: Failed to request resource"
1498 ", port still active\n",
1499 uap->node);
1500 else
1501 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1502
1503 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1504}
1505
1506/*
1507 * That one should not be called, macio isn't really a hotswap device,
1508 * we don't expect one of those serial ports to go away...
1509 */
1510static int pmz_detach(struct macio_dev *mdev)
1511{
1512 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1513
1514 if (!uap)
1515 return -ENODEV;
1516
1517 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1518
1519 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1520 macio_release_resources(uap->dev);
1521 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1522 }
1523 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1524 uap->dev = NULL;
1525 uap->port.dev = NULL;
1526
1527 return 0;
1528}
1529
1530
1531static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1532{
1533 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1534
1535 if (uap == NULL) {
1536 printk("HRM... pmz_suspend with NULL uap\n");
1537 return 0;
1538 }
1539
1540 uart_suspend_port(&pmz_uart_reg, &uap->port);
1541
1542 return 0;
1543}
1544
1545
1546static int pmz_resume(struct macio_dev *mdev)
1547{
1548 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1549
1550 if (uap == NULL)
1551 return 0;
1552
1553 uart_resume_port(&pmz_uart_reg, &uap->port);
1554
1555 return 0;
1556}
1557
1558/*
1559 * Probe all ports in the system and build the ports array, we register
1560 * with the serial layer later, so we get a proper struct device which
1561 * allows the tty to attach properly. This is later than it used to be
1562 * but the tty layer really wants it that way.
1563 */
1564static int __init pmz_probe(void)
1565{
1566 struct device_node *node_p, *node_a, *node_b, *np;
1567 int count = 0;
1568 int rc;
1569
1570 /*
1571 * Find all escc chips in the system
1572 */
1573 for_each_node_by_name(node_p, "escc") {
1574 /*
1575 * First get channel A/B node pointers
1576 *
1577 * TODO: Add routines with proper locking to do that...
1578 */
1579 node_a = node_b = NULL;
1580 for_each_child_of_node(node_p, np) {
1581 if (of_node_name_prefix(np, "ch-a"))
1582 node_a = of_node_get(np);
1583 else if (of_node_name_prefix(np, "ch-b"))
1584 node_b = of_node_get(np);
1585 }
1586 if (!node_a && !node_b) {
1587 of_node_put(node_a);
1588 of_node_put(node_b);
1589 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",
1590 (!node_a) ? 'a' : 'b', node_p);
1591 continue;
1592 }
1593
1594 /*
1595 * Fill basic fields in the port structures
1596 */
1597 if (node_b != NULL) {
1598 pmz_ports[count].mate = &pmz_ports[count+1];
1599 pmz_ports[count+1].mate = &pmz_ports[count];
1600 }
1601 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1602 pmz_ports[count].node = node_a;
1603 pmz_ports[count+1].node = node_b;
1604 pmz_ports[count].port.line = count;
1605 pmz_ports[count+1].port.line = count+1;
1606
1607 /*
1608 * Setup the ports for real
1609 */
1610 rc = pmz_init_port(&pmz_ports[count]);
1611 if (rc == 0 && node_b != NULL)
1612 rc = pmz_init_port(&pmz_ports[count+1]);
1613 if (rc != 0) {
1614 of_node_put(node_a);
1615 of_node_put(node_b);
1616 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1617 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1618 continue;
1619 }
1620 count += 2;
1621 }
1622 pmz_ports_count = count;
1623
1624 return 0;
1625}
1626
1627#else
1628
1629/* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware
1630 * tree to obtain the device_nodes needed to start the console before the
1631 * macio driver. On Macs without OpenFirmware, global platform_devices take
1632 * the place of those device_nodes.
1633 */
1634extern struct platform_device scc_a_pdev, scc_b_pdev;
1635
1636static int __init pmz_init_port(struct uart_pmac_port *uap)
1637{
1638 struct resource *r_ports;
1639 int irq;
1640
1641 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1642 if (!r_ports)
1643 return -ENODEV;
1644
1645 irq = platform_get_irq(uap->pdev, 0);
1646 if (irq < 0)
1647 return irq;
1648
1649 uap->port.mapbase = r_ports->start;
1650 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1651 uap->port.iotype = UPIO_MEM;
1652 uap->port.irq = irq;
1653 uap->port.uartclk = ZS_CLOCK;
1654 uap->port.fifosize = 1;
1655 uap->port.ops = &pmz_pops;
1656 uap->port.type = PORT_PMAC_ZILOG;
1657 uap->port.flags = 0;
1658
1659 uap->control_reg = uap->port.membase;
1660 uap->data_reg = uap->control_reg + 4;
1661 uap->port_type = 0;
1662 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE);
1663
1664 pmz_convert_to_zs(uap, CS8, 0, 9600);
1665
1666 return 0;
1667}
1668
1669static int __init pmz_probe(void)
1670{
1671 int err;
1672
1673 pmz_ports_count = 0;
1674
1675 pmz_ports[0].port.line = 0;
1676 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1677 pmz_ports[0].pdev = &scc_a_pdev;
1678 err = pmz_init_port(&pmz_ports[0]);
1679 if (err)
1680 return err;
1681 pmz_ports_count++;
1682
1683 pmz_ports[0].mate = &pmz_ports[1];
1684 pmz_ports[1].mate = &pmz_ports[0];
1685 pmz_ports[1].port.line = 1;
1686 pmz_ports[1].flags = 0;
1687 pmz_ports[1].pdev = &scc_b_pdev;
1688 err = pmz_init_port(&pmz_ports[1]);
1689 if (err)
1690 return err;
1691 pmz_ports_count++;
1692
1693 return 0;
1694}
1695
1696static void pmz_dispose_port(struct uart_pmac_port *uap)
1697{
1698 memset(uap, 0, sizeof(struct uart_pmac_port));
1699}
1700
1701static int __init pmz_attach(struct platform_device *pdev)
1702{
1703 struct uart_pmac_port *uap;
1704 int i;
1705
1706 /* Iterate the pmz_ports array to find a matching entry */
1707 for (i = 0; i < pmz_ports_count; i++)
1708 if (pmz_ports[i].pdev == pdev)
1709 break;
1710 if (i >= pmz_ports_count)
1711 return -ENODEV;
1712
1713 uap = &pmz_ports[i];
1714 uap->port.dev = &pdev->dev;
1715 platform_set_drvdata(pdev, uap);
1716
1717 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1718}
1719
1720static int __exit pmz_detach(struct platform_device *pdev)
1721{
1722 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1723
1724 if (!uap)
1725 return -ENODEV;
1726
1727 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1728
1729 uap->port.dev = NULL;
1730
1731 return 0;
1732}
1733
1734#endif /* !CONFIG_PPC_PMAC */
1735
1736#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1737
1738static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1739static int __init pmz_console_setup(struct console *co, char *options);
1740
1741static struct console pmz_console = {
1742 .name = PMACZILOG_NAME,
1743 .write = pmz_console_write,
1744 .device = uart_console_device,
1745 .setup = pmz_console_setup,
1746 .flags = CON_PRINTBUFFER,
1747 .index = -1,
1748 .data = &pmz_uart_reg,
1749};
1750
1751#define PMACZILOG_CONSOLE &pmz_console
1752#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1753#define PMACZILOG_CONSOLE (NULL)
1754#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1755
1756/*
1757 * Register the driver, console driver and ports with the serial
1758 * core
1759 */
1760static int __init pmz_register(void)
1761{
1762 pmz_uart_reg.nr = pmz_ports_count;
1763 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1764
1765 /*
1766 * Register this driver with the serial core
1767 */
1768 return uart_register_driver(&pmz_uart_reg);
1769}
1770
1771#ifdef CONFIG_PPC_PMAC
1772
1773static const struct of_device_id pmz_match[] =
1774{
1775 {
1776 .name = "ch-a",
1777 },
1778 {
1779 .name = "ch-b",
1780 },
1781 {},
1782};
1783MODULE_DEVICE_TABLE (of, pmz_match);
1784
1785static struct macio_driver pmz_driver = {
1786 .driver = {
1787 .name = "pmac_zilog",
1788 .owner = THIS_MODULE,
1789 .of_match_table = pmz_match,
1790 },
1791 .probe = pmz_attach,
1792 .remove = pmz_detach,
1793 .suspend = pmz_suspend,
1794 .resume = pmz_resume,
1795};
1796
1797#else
1798
1799static struct platform_driver pmz_driver = {
1800 .remove = __exit_p(pmz_detach),
1801 .driver = {
1802 .name = "scc",
1803 },
1804};
1805
1806#endif /* !CONFIG_PPC_PMAC */
1807
1808static int __init init_pmz(void)
1809{
1810 int rc, i;
1811
1812 /*
1813 * First, we need to do a direct OF-based probe pass. We
1814 * do that because we want serial console up before the
1815 * macio stuffs calls us back, and since that makes it
1816 * easier to pass the proper number of channels to
1817 * uart_register_driver()
1818 */
1819 if (pmz_ports_count == 0)
1820 pmz_probe();
1821
1822 /*
1823 * Bail early if no port found
1824 */
1825 if (pmz_ports_count == 0)
1826 return -ENODEV;
1827
1828 /*
1829 * Now we register with the serial layer
1830 */
1831 rc = pmz_register();
1832 if (rc) {
1833 printk(KERN_ERR
1834 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1835 "pmac_zilog: Did another serial driver already claim the minors?\n");
1836 /* effectively "pmz_unprobe()" */
1837 for (i=0; i < pmz_ports_count; i++)
1838 pmz_dispose_port(&pmz_ports[i]);
1839 return rc;
1840 }
1841
1842 /*
1843 * Then we register the macio driver itself
1844 */
1845#ifdef CONFIG_PPC_PMAC
1846 return macio_register_driver(&pmz_driver);
1847#else
1848 return platform_driver_probe(&pmz_driver, pmz_attach);
1849#endif
1850}
1851
1852static void __exit exit_pmz(void)
1853{
1854 int i;
1855
1856#ifdef CONFIG_PPC_PMAC
1857 /* Get rid of macio-driver (detach from macio) */
1858 macio_unregister_driver(&pmz_driver);
1859#else
1860 platform_driver_unregister(&pmz_driver);
1861#endif
1862
1863 for (i = 0; i < pmz_ports_count; i++) {
1864 struct uart_pmac_port *uport = &pmz_ports[i];
1865#ifdef CONFIG_PPC_PMAC
1866 if (uport->node != NULL)
1867 pmz_dispose_port(uport);
1868#else
1869 if (uport->pdev != NULL)
1870 pmz_dispose_port(uport);
1871#endif
1872 }
1873 /* Unregister UART driver */
1874 uart_unregister_driver(&pmz_uart_reg);
1875}
1876
1877#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1878
1879static void pmz_console_putchar(struct uart_port *port, unsigned char ch)
1880{
1881 struct uart_pmac_port *uap =
1882 container_of(port, struct uart_pmac_port, port);
1883
1884 /* Wait for the transmit buffer to empty. */
1885 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1886 udelay(5);
1887 write_zsdata(uap, ch);
1888}
1889
1890/*
1891 * Print a string to the serial port trying not to disturb
1892 * any possible real use of the port...
1893 */
1894static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1895{
1896 struct uart_pmac_port *uap = &pmz_ports[con->index];
1897 unsigned long flags;
1898
1899 uart_port_lock_irqsave(&uap->port, &flags);
1900
1901 /* Turn of interrupts and enable the transmitter. */
1902 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1903 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1904
1905 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1906
1907 /* Restore the values in the registers. */
1908 write_zsreg(uap, R1, uap->curregs[1]);
1909 /* Don't disable the transmitter. */
1910
1911 uart_port_unlock_irqrestore(&uap->port, flags);
1912}
1913
1914/*
1915 * Setup the serial console
1916 */
1917static int __init pmz_console_setup(struct console *co, char *options)
1918{
1919 struct uart_pmac_port *uap;
1920 struct uart_port *port;
1921 int baud = 38400;
1922 int bits = 8;
1923 int parity = 'n';
1924 int flow = 'n';
1925 unsigned long pwr_delay;
1926
1927 /*
1928 * XServe's default to 57600 bps
1929 */
1930 if (of_machine_is_compatible("RackMac1,1")
1931 || of_machine_is_compatible("RackMac1,2")
1932 || of_machine_is_compatible("MacRISC4"))
1933 baud = 57600;
1934
1935 /*
1936 * Check whether an invalid uart number has been specified, and
1937 * if so, search for the first available port that does have
1938 * console support.
1939 */
1940 if (co->index >= pmz_ports_count)
1941 co->index = 0;
1942 uap = &pmz_ports[co->index];
1943#ifdef CONFIG_PPC_PMAC
1944 if (uap->node == NULL)
1945 return -ENODEV;
1946#else
1947 if (uap->pdev == NULL)
1948 return -ENODEV;
1949#endif
1950 port = &uap->port;
1951
1952 /*
1953 * Mark port as beeing a console
1954 */
1955 uap->flags |= PMACZILOG_FLAG_IS_CONS;
1956
1957 /*
1958 * Temporary fix for uart layer who didn't setup the spinlock yet
1959 */
1960 spin_lock_init(&port->lock);
1961
1962 /*
1963 * Enable the hardware
1964 */
1965 pwr_delay = __pmz_startup(uap);
1966 if (pwr_delay)
1967 mdelay(pwr_delay);
1968
1969 if (options)
1970 uart_parse_options(options, &baud, &parity, &bits, &flow);
1971
1972 return uart_set_options(port, co, baud, parity, bits, flow);
1973}
1974
1975static int __init pmz_console_init(void)
1976{
1977 /* Probe ports */
1978 pmz_probe();
1979
1980 if (pmz_ports_count == 0)
1981 return -ENODEV;
1982
1983 /* TODO: Autoprobe console based on OF */
1984 /* pmz_console.index = i; */
1985 register_console(&pmz_console);
1986
1987 return 0;
1988
1989}
1990console_initcall(pmz_console_init);
1991#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1992
1993module_init(init_pmz);
1994module_exit(exit_pmz);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Driver for PowerMac Z85c30 based ESCC cell found in the
4 * "macio" ASICs of various PowerMac models
5 *
6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
7 *
8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras
9 * and drivers/serial/sunzilog.c by David S. Miller
10 *
11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and
12 * adapted special tweaks needed for us. I don't think it's worth
13 * merging back those though. The DMA code still has to get in
14 * and once done, I expect that driver to remain fairly stable in
15 * the long term, unless we change the driver model again...
16 *
17 * 2004-08-06 Harald Welte <laforge@gnumonks.org>
18 * - Enable BREAK interrupt
19 * - Add support for sysreq
20 *
21 * TODO: - Add DMA support
22 * - Defer port shutdown to a few seconds after close
23 * - maybe put something right into uap->clk_divisor
24 */
25
26#undef DEBUG
27#undef DEBUG_HARD
28#undef USE_CTRL_O_SYSRQ
29
30#include <linux/module.h>
31#include <linux/tty.h>
32
33#include <linux/tty_flip.h>
34#include <linux/major.h>
35#include <linux/string.h>
36#include <linux/fcntl.h>
37#include <linux/mm.h>
38#include <linux/kernel.h>
39#include <linux/delay.h>
40#include <linux/init.h>
41#include <linux/console.h>
42#include <linux/adb.h>
43#include <linux/pmu.h>
44#include <linux/bitops.h>
45#include <linux/sysrq.h>
46#include <linux/mutex.h>
47#include <linux/of_address.h>
48#include <linux/of_irq.h>
49#include <asm/sections.h>
50#include <asm/io.h>
51#include <asm/irq.h>
52
53#ifdef CONFIG_PPC_PMAC
54#include <asm/prom.h>
55#include <asm/machdep.h>
56#include <asm/pmac_feature.h>
57#include <asm/dbdma.h>
58#include <asm/macio.h>
59#else
60#include <linux/platform_device.h>
61#define of_machine_is_compatible(x) (0)
62#endif
63
64#if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
65#define SUPPORT_SYSRQ
66#endif
67
68#include <linux/serial.h>
69#include <linux/serial_core.h>
70
71#include "pmac_zilog.h"
72
73/* Not yet implemented */
74#undef HAS_DBDMA
75
76static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)";
77MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
78MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports.");
79MODULE_LICENSE("GPL");
80
81#ifdef CONFIG_SERIAL_PMACZILOG_TTYS
82#define PMACZILOG_MAJOR TTY_MAJOR
83#define PMACZILOG_MINOR 64
84#define PMACZILOG_NAME "ttyS"
85#else
86#define PMACZILOG_MAJOR 204
87#define PMACZILOG_MINOR 192
88#define PMACZILOG_NAME "ttyPZ"
89#endif
90
91#define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg)
92#define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg)
93#define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg)
94
95/*
96 * For the sake of early serial console, we can do a pre-probe
97 * (optional) of the ports at rather early boot time.
98 */
99static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS];
100static int pmz_ports_count;
101
102static struct uart_driver pmz_uart_reg = {
103 .owner = THIS_MODULE,
104 .driver_name = PMACZILOG_NAME,
105 .dev_name = PMACZILOG_NAME,
106 .major = PMACZILOG_MAJOR,
107 .minor = PMACZILOG_MINOR,
108};
109
110
111/*
112 * Load all registers to reprogram the port
113 * This function must only be called when the TX is not busy. The UART
114 * port lock must be held and local interrupts disabled.
115 */
116static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs)
117{
118 int i;
119
120 /* Let pending transmits finish. */
121 for (i = 0; i < 1000; i++) {
122 unsigned char stat = read_zsreg(uap, R1);
123 if (stat & ALL_SNT)
124 break;
125 udelay(100);
126 }
127
128 ZS_CLEARERR(uap);
129 zssync(uap);
130 ZS_CLEARFIFO(uap);
131 zssync(uap);
132 ZS_CLEARERR(uap);
133
134 /* Disable all interrupts. */
135 write_zsreg(uap, R1,
136 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
137
138 /* Set parity, sync config, stop bits, and clock divisor. */
139 write_zsreg(uap, R4, regs[R4]);
140
141 /* Set misc. TX/RX control bits. */
142 write_zsreg(uap, R10, regs[R10]);
143
144 /* Set TX/RX controls sans the enable bits. */
145 write_zsreg(uap, R3, regs[R3] & ~RxENABLE);
146 write_zsreg(uap, R5, regs[R5] & ~TxENABLE);
147
148 /* now set R7 "prime" on ESCC */
149 write_zsreg(uap, R15, regs[R15] | EN85C30);
150 write_zsreg(uap, R7, regs[R7P]);
151
152 /* make sure we use R7 "non-prime" on ESCC */
153 write_zsreg(uap, R15, regs[R15] & ~EN85C30);
154
155 /* Synchronous mode config. */
156 write_zsreg(uap, R6, regs[R6]);
157 write_zsreg(uap, R7, regs[R7]);
158
159 /* Disable baud generator. */
160 write_zsreg(uap, R14, regs[R14] & ~BRENAB);
161
162 /* Clock mode control. */
163 write_zsreg(uap, R11, regs[R11]);
164
165 /* Lower and upper byte of baud rate generator divisor. */
166 write_zsreg(uap, R12, regs[R12]);
167 write_zsreg(uap, R13, regs[R13]);
168
169 /* Now rewrite R14, with BRENAB (if set). */
170 write_zsreg(uap, R14, regs[R14]);
171
172 /* Reset external status interrupts. */
173 write_zsreg(uap, R0, RES_EXT_INT);
174 write_zsreg(uap, R0, RES_EXT_INT);
175
176 /* Rewrite R3/R5, this time without enables masked. */
177 write_zsreg(uap, R3, regs[R3]);
178 write_zsreg(uap, R5, regs[R5]);
179
180 /* Rewrite R1, this time without IRQ enabled masked. */
181 write_zsreg(uap, R1, regs[R1]);
182
183 /* Enable interrupts */
184 write_zsreg(uap, R9, regs[R9]);
185}
186
187/*
188 * We do like sunzilog to avoid disrupting pending Tx
189 * Reprogram the Zilog channel HW registers with the copies found in the
190 * software state struct. If the transmitter is busy, we defer this update
191 * until the next TX complete interrupt. Else, we do it right now.
192 *
193 * The UART port lock must be held and local interrupts disabled.
194 */
195static void pmz_maybe_update_regs(struct uart_pmac_port *uap)
196{
197 if (!ZS_REGS_HELD(uap)) {
198 if (ZS_TX_ACTIVE(uap)) {
199 uap->flags |= PMACZILOG_FLAG_REGS_HELD;
200 } else {
201 pmz_debug("pmz: maybe_update_regs: updating\n");
202 pmz_load_zsregs(uap, uap->curregs);
203 }
204 }
205}
206
207static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable)
208{
209 if (enable) {
210 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB;
211 if (!ZS_IS_EXTCLK(uap))
212 uap->curregs[1] |= EXT_INT_ENAB;
213 } else {
214 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
215 }
216 write_zsreg(uap, R1, uap->curregs[1]);
217}
218
219static bool pmz_receive_chars(struct uart_pmac_port *uap)
220{
221 struct tty_port *port;
222 unsigned char ch, r1, drop, error, flag;
223 int loops = 0;
224
225 /* Sanity check, make sure the old bug is no longer happening */
226 if (uap->port.state == NULL) {
227 WARN_ON(1);
228 (void)read_zsdata(uap);
229 return false;
230 }
231 port = &uap->port.state->port;
232
233 while (1) {
234 error = 0;
235 drop = 0;
236
237 r1 = read_zsreg(uap, R1);
238 ch = read_zsdata(uap);
239
240 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
241 write_zsreg(uap, R0, ERR_RES);
242 zssync(uap);
243 }
244
245 ch &= uap->parity_mask;
246 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) {
247 uap->flags &= ~PMACZILOG_FLAG_BREAK;
248 }
249
250#if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE)
251#ifdef USE_CTRL_O_SYSRQ
252 /* Handle the SysRq ^O Hack */
253 if (ch == '\x0f') {
254 uap->port.sysrq = jiffies + HZ*5;
255 goto next_char;
256 }
257#endif /* USE_CTRL_O_SYSRQ */
258 if (uap->port.sysrq) {
259 int swallow;
260 spin_unlock(&uap->port.lock);
261 swallow = uart_handle_sysrq_char(&uap->port, ch);
262 spin_lock(&uap->port.lock);
263 if (swallow)
264 goto next_char;
265 }
266#endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */
267
268 /* A real serial line, record the character and status. */
269 if (drop)
270 goto next_char;
271
272 flag = TTY_NORMAL;
273 uap->port.icount.rx++;
274
275 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) {
276 error = 1;
277 if (r1 & BRK_ABRT) {
278 pmz_debug("pmz: got break !\n");
279 r1 &= ~(PAR_ERR | CRC_ERR);
280 uap->port.icount.brk++;
281 if (uart_handle_break(&uap->port))
282 goto next_char;
283 }
284 else if (r1 & PAR_ERR)
285 uap->port.icount.parity++;
286 else if (r1 & CRC_ERR)
287 uap->port.icount.frame++;
288 if (r1 & Rx_OVR)
289 uap->port.icount.overrun++;
290 r1 &= uap->port.read_status_mask;
291 if (r1 & BRK_ABRT)
292 flag = TTY_BREAK;
293 else if (r1 & PAR_ERR)
294 flag = TTY_PARITY;
295 else if (r1 & CRC_ERR)
296 flag = TTY_FRAME;
297 }
298
299 if (uap->port.ignore_status_mask == 0xff ||
300 (r1 & uap->port.ignore_status_mask) == 0) {
301 tty_insert_flip_char(port, ch, flag);
302 }
303 if (r1 & Rx_OVR)
304 tty_insert_flip_char(port, 0, TTY_OVERRUN);
305 next_char:
306 /* We can get stuck in an infinite loop getting char 0 when the
307 * line is in a wrong HW state, we break that here.
308 * When that happens, I disable the receive side of the driver.
309 * Note that what I've been experiencing is a real irq loop where
310 * I'm getting flooded regardless of the actual port speed.
311 * Something strange is going on with the HW
312 */
313 if ((++loops) > 1000)
314 goto flood;
315 ch = read_zsreg(uap, R0);
316 if (!(ch & Rx_CH_AV))
317 break;
318 }
319
320 return true;
321 flood:
322 pmz_interrupt_control(uap, 0);
323 pmz_error("pmz: rx irq flood !\n");
324 return true;
325}
326
327static void pmz_status_handle(struct uart_pmac_port *uap)
328{
329 unsigned char status;
330
331 status = read_zsreg(uap, R0);
332 write_zsreg(uap, R0, RES_EXT_INT);
333 zssync(uap);
334
335 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) {
336 if (status & SYNC_HUNT)
337 uap->port.icount.dsr++;
338
339 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
340 * But it does not tell us which bit has changed, we have to keep
341 * track of this ourselves.
342 * The CTS input is inverted for some reason. -- paulus
343 */
344 if ((status ^ uap->prev_status) & DCD)
345 uart_handle_dcd_change(&uap->port,
346 (status & DCD));
347 if ((status ^ uap->prev_status) & CTS)
348 uart_handle_cts_change(&uap->port,
349 !(status & CTS));
350
351 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
352 }
353
354 if (status & BRK_ABRT)
355 uap->flags |= PMACZILOG_FLAG_BREAK;
356
357 uap->prev_status = status;
358}
359
360static void pmz_transmit_chars(struct uart_pmac_port *uap)
361{
362 struct circ_buf *xmit;
363
364 if (ZS_IS_CONS(uap)) {
365 unsigned char status = read_zsreg(uap, R0);
366
367 /* TX still busy? Just wait for the next TX done interrupt.
368 *
369 * It can occur because of how we do serial console writes. It would
370 * be nice to transmit console writes just like we normally would for
371 * a TTY line. (ie. buffered and TX interrupt driven). That is not
372 * easy because console writes cannot sleep. One solution might be
373 * to poll on enough port->xmit space becoming free. -DaveM
374 */
375 if (!(status & Tx_BUF_EMP))
376 return;
377 }
378
379 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE;
380
381 if (ZS_REGS_HELD(uap)) {
382 pmz_load_zsregs(uap, uap->curregs);
383 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD;
384 }
385
386 if (ZS_TX_STOPPED(uap)) {
387 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
388 goto ack_tx_int;
389 }
390
391 /* Under some circumstances, we see interrupts reported for
392 * a closed channel. The interrupt mask in R1 is clear, but
393 * R3 still signals the interrupts and we see them when taking
394 * an interrupt for the other channel (this could be a qemu
395 * bug but since the ESCC doc doesn't specify precsiely whether
396 * R3 interrup status bits are masked by R1 interrupt enable
397 * bits, better safe than sorry). --BenH.
398 */
399 if (!ZS_IS_OPEN(uap))
400 goto ack_tx_int;
401
402 if (uap->port.x_char) {
403 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
404 write_zsdata(uap, uap->port.x_char);
405 zssync(uap);
406 uap->port.icount.tx++;
407 uap->port.x_char = 0;
408 return;
409 }
410
411 if (uap->port.state == NULL)
412 goto ack_tx_int;
413 xmit = &uap->port.state->xmit;
414 if (uart_circ_empty(xmit)) {
415 uart_write_wakeup(&uap->port);
416 goto ack_tx_int;
417 }
418 if (uart_tx_stopped(&uap->port))
419 goto ack_tx_int;
420
421 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
422 write_zsdata(uap, xmit->buf[xmit->tail]);
423 zssync(uap);
424
425 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
426 uap->port.icount.tx++;
427
428 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
429 uart_write_wakeup(&uap->port);
430
431 return;
432
433ack_tx_int:
434 write_zsreg(uap, R0, RES_Tx_P);
435 zssync(uap);
436}
437
438/* Hrm... we register that twice, fixme later.... */
439static irqreturn_t pmz_interrupt(int irq, void *dev_id)
440{
441 struct uart_pmac_port *uap = dev_id;
442 struct uart_pmac_port *uap_a;
443 struct uart_pmac_port *uap_b;
444 int rc = IRQ_NONE;
445 bool push;
446 u8 r3;
447
448 uap_a = pmz_get_port_A(uap);
449 uap_b = uap_a->mate;
450
451 spin_lock(&uap_a->port.lock);
452 r3 = read_zsreg(uap_a, R3);
453
454#ifdef DEBUG_HARD
455 pmz_debug("irq, r3: %x\n", r3);
456#endif
457 /* Channel A */
458 push = false;
459 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
460 if (!ZS_IS_OPEN(uap_a)) {
461 pmz_debug("ChanA interrupt while not open !\n");
462 goto skip_a;
463 }
464 write_zsreg(uap_a, R0, RES_H_IUS);
465 zssync(uap_a);
466 if (r3 & CHAEXT)
467 pmz_status_handle(uap_a);
468 if (r3 & CHARxIP)
469 push = pmz_receive_chars(uap_a);
470 if (r3 & CHATxIP)
471 pmz_transmit_chars(uap_a);
472 rc = IRQ_HANDLED;
473 }
474 skip_a:
475 spin_unlock(&uap_a->port.lock);
476 if (push)
477 tty_flip_buffer_push(&uap->port.state->port);
478
479 if (!uap_b)
480 goto out;
481
482 spin_lock(&uap_b->port.lock);
483 push = false;
484 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
485 if (!ZS_IS_OPEN(uap_b)) {
486 pmz_debug("ChanB interrupt while not open !\n");
487 goto skip_b;
488 }
489 write_zsreg(uap_b, R0, RES_H_IUS);
490 zssync(uap_b);
491 if (r3 & CHBEXT)
492 pmz_status_handle(uap_b);
493 if (r3 & CHBRxIP)
494 push = pmz_receive_chars(uap_b);
495 if (r3 & CHBTxIP)
496 pmz_transmit_chars(uap_b);
497 rc = IRQ_HANDLED;
498 }
499 skip_b:
500 spin_unlock(&uap_b->port.lock);
501 if (push)
502 tty_flip_buffer_push(&uap->port.state->port);
503
504 out:
505 return rc;
506}
507
508/*
509 * Peek the status register, lock not held by caller
510 */
511static inline u8 pmz_peek_status(struct uart_pmac_port *uap)
512{
513 unsigned long flags;
514 u8 status;
515
516 spin_lock_irqsave(&uap->port.lock, flags);
517 status = read_zsreg(uap, R0);
518 spin_unlock_irqrestore(&uap->port.lock, flags);
519
520 return status;
521}
522
523/*
524 * Check if transmitter is empty
525 * The port lock is not held.
526 */
527static unsigned int pmz_tx_empty(struct uart_port *port)
528{
529 unsigned char status;
530
531 status = pmz_peek_status(to_pmz(port));
532 if (status & Tx_BUF_EMP)
533 return TIOCSER_TEMT;
534 return 0;
535}
536
537/*
538 * Set Modem Control (RTS & DTR) bits
539 * The port lock is held and interrupts are disabled.
540 * Note: Shall we really filter out RTS on external ports or
541 * should that be dealt at higher level only ?
542 */
543static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl)
544{
545 struct uart_pmac_port *uap = to_pmz(port);
546 unsigned char set_bits, clear_bits;
547
548 /* Do nothing for irda for now... */
549 if (ZS_IS_IRDA(uap))
550 return;
551 /* We get called during boot with a port not up yet */
552 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)))
553 return;
554
555 set_bits = clear_bits = 0;
556
557 if (ZS_IS_INTMODEM(uap)) {
558 if (mctrl & TIOCM_RTS)
559 set_bits |= RTS;
560 else
561 clear_bits |= RTS;
562 }
563 if (mctrl & TIOCM_DTR)
564 set_bits |= DTR;
565 else
566 clear_bits |= DTR;
567
568 /* NOTE: Not subject to 'transmitter active' rule. */
569 uap->curregs[R5] |= set_bits;
570 uap->curregs[R5] &= ~clear_bits;
571
572 write_zsreg(uap, R5, uap->curregs[R5]);
573 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n",
574 set_bits, clear_bits, uap->curregs[R5]);
575 zssync(uap);
576}
577
578/*
579 * Get Modem Control bits (only the input ones, the core will
580 * or that with a cached value of the control ones)
581 * The port lock is held and interrupts are disabled.
582 */
583static unsigned int pmz_get_mctrl(struct uart_port *port)
584{
585 struct uart_pmac_port *uap = to_pmz(port);
586 unsigned char status;
587 unsigned int ret;
588
589 status = read_zsreg(uap, R0);
590
591 ret = 0;
592 if (status & DCD)
593 ret |= TIOCM_CAR;
594 if (status & SYNC_HUNT)
595 ret |= TIOCM_DSR;
596 if (!(status & CTS))
597 ret |= TIOCM_CTS;
598
599 return ret;
600}
601
602/*
603 * Stop TX side. Dealt like sunzilog at next Tx interrupt,
604 * though for DMA, we will have to do a bit more.
605 * The port lock is held and interrupts are disabled.
606 */
607static void pmz_stop_tx(struct uart_port *port)
608{
609 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED;
610}
611
612/*
613 * Kick the Tx side.
614 * The port lock is held and interrupts are disabled.
615 */
616static void pmz_start_tx(struct uart_port *port)
617{
618 struct uart_pmac_port *uap = to_pmz(port);
619 unsigned char status;
620
621 pmz_debug("pmz: start_tx()\n");
622
623 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE;
624 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED;
625
626 status = read_zsreg(uap, R0);
627
628 /* TX busy? Just wait for the TX done interrupt. */
629 if (!(status & Tx_BUF_EMP))
630 return;
631
632 /* Send the first character to jump-start the TX done
633 * IRQ sending engine.
634 */
635 if (port->x_char) {
636 write_zsdata(uap, port->x_char);
637 zssync(uap);
638 port->icount.tx++;
639 port->x_char = 0;
640 } else {
641 struct circ_buf *xmit = &port->state->xmit;
642
643 if (uart_circ_empty(xmit))
644 goto out;
645 write_zsdata(uap, xmit->buf[xmit->tail]);
646 zssync(uap);
647 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
648 port->icount.tx++;
649
650 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
651 uart_write_wakeup(&uap->port);
652 }
653 out:
654 pmz_debug("pmz: start_tx() done.\n");
655}
656
657/*
658 * Stop Rx side, basically disable emitting of
659 * Rx interrupts on the port. We don't disable the rx
660 * side of the chip proper though
661 * The port lock is held.
662 */
663static void pmz_stop_rx(struct uart_port *port)
664{
665 struct uart_pmac_port *uap = to_pmz(port);
666
667 pmz_debug("pmz: stop_rx()()\n");
668
669 /* Disable all RX interrupts. */
670 uap->curregs[R1] &= ~RxINT_MASK;
671 pmz_maybe_update_regs(uap);
672
673 pmz_debug("pmz: stop_rx() done.\n");
674}
675
676/*
677 * Enable modem status change interrupts
678 * The port lock is held.
679 */
680static void pmz_enable_ms(struct uart_port *port)
681{
682 struct uart_pmac_port *uap = to_pmz(port);
683 unsigned char new_reg;
684
685 if (ZS_IS_IRDA(uap))
686 return;
687 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
688 if (new_reg != uap->curregs[R15]) {
689 uap->curregs[R15] = new_reg;
690
691 /* NOTE: Not subject to 'transmitter active' rule. */
692 write_zsreg(uap, R15, uap->curregs[R15]);
693 }
694}
695
696/*
697 * Control break state emission
698 * The port lock is not held.
699 */
700static void pmz_break_ctl(struct uart_port *port, int break_state)
701{
702 struct uart_pmac_port *uap = to_pmz(port);
703 unsigned char set_bits, clear_bits, new_reg;
704 unsigned long flags;
705
706 set_bits = clear_bits = 0;
707
708 if (break_state)
709 set_bits |= SND_BRK;
710 else
711 clear_bits |= SND_BRK;
712
713 spin_lock_irqsave(&port->lock, flags);
714
715 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits;
716 if (new_reg != uap->curregs[R5]) {
717 uap->curregs[R5] = new_reg;
718 write_zsreg(uap, R5, uap->curregs[R5]);
719 }
720
721 spin_unlock_irqrestore(&port->lock, flags);
722}
723
724#ifdef CONFIG_PPC_PMAC
725
726/*
727 * Turn power on or off to the SCC and associated stuff
728 * (port drivers, modem, IR port, etc.)
729 * Returns the number of milliseconds we should wait before
730 * trying to use the port.
731 */
732static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
733{
734 int delay = 0;
735 int rc;
736
737 if (state) {
738 rc = pmac_call_feature(
739 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1);
740 pmz_debug("port power on result: %d\n", rc);
741 if (ZS_IS_INTMODEM(uap)) {
742 rc = pmac_call_feature(
743 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1);
744 delay = 2500; /* wait for 2.5s before using */
745 pmz_debug("modem power result: %d\n", rc);
746 }
747 } else {
748 /* TODO: Make that depend on a timer, don't power down
749 * immediately
750 */
751 if (ZS_IS_INTMODEM(uap)) {
752 rc = pmac_call_feature(
753 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0);
754 pmz_debug("port power off result: %d\n", rc);
755 }
756 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0);
757 }
758 return delay;
759}
760
761#else
762
763static int pmz_set_scc_power(struct uart_pmac_port *uap, int state)
764{
765 return 0;
766}
767
768#endif /* !CONFIG_PPC_PMAC */
769
770/*
771 * FixZeroBug....Works around a bug in the SCC receiving channel.
772 * Inspired from Darwin code, 15 Sept. 2000 -DanM
773 *
774 * The following sequence prevents a problem that is seen with O'Hare ASICs
775 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero
776 * at the input to the receiver becomes 'stuck' and locks up the receiver.
777 * This problem can occur as a result of a zero bit at the receiver input
778 * coincident with any of the following events:
779 *
780 * The SCC is initialized (hardware or software).
781 * A framing error is detected.
782 * The clocking option changes from synchronous or X1 asynchronous
783 * clocking to X16, X32, or X64 asynchronous clocking.
784 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1.
785 *
786 * This workaround attempts to recover from the lockup condition by placing
787 * the SCC in synchronous loopback mode with a fast clock before programming
788 * any of the asynchronous modes.
789 */
790static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap)
791{
792 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
793 zssync(uap);
794 udelay(10);
795 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV);
796 zssync(uap);
797
798 write_zsreg(uap, 4, X1CLK | MONSYNC);
799 write_zsreg(uap, 3, Rx8);
800 write_zsreg(uap, 5, Tx8 | RTS);
801 write_zsreg(uap, 9, NV); /* Didn't we already do this? */
802 write_zsreg(uap, 11, RCBR | TCBR);
803 write_zsreg(uap, 12, 0);
804 write_zsreg(uap, 13, 0);
805 write_zsreg(uap, 14, (LOOPBAK | BRSRC));
806 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB));
807 write_zsreg(uap, 3, Rx8 | RxENABLE);
808 write_zsreg(uap, 0, RES_EXT_INT);
809 write_zsreg(uap, 0, RES_EXT_INT);
810 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */
811
812 /* The channel should be OK now, but it is probably receiving
813 * loopback garbage.
814 * Switch to asynchronous mode, disable the receiver,
815 * and discard everything in the receive buffer.
816 */
817 write_zsreg(uap, 9, NV);
818 write_zsreg(uap, 4, X16CLK | SB_MASK);
819 write_zsreg(uap, 3, Rx8);
820
821 while (read_zsreg(uap, 0) & Rx_CH_AV) {
822 (void)read_zsreg(uap, 8);
823 write_zsreg(uap, 0, RES_EXT_INT);
824 write_zsreg(uap, 0, ERR_RES);
825 }
826}
827
828/*
829 * Real startup routine, powers up the hardware and sets up
830 * the SCC. Returns a delay in ms where you need to wait before
831 * actually using the port, this is typically the internal modem
832 * powerup delay. This routine expect the lock to be taken.
833 */
834static int __pmz_startup(struct uart_pmac_port *uap)
835{
836 int pwr_delay = 0;
837
838 memset(&uap->curregs, 0, sizeof(uap->curregs));
839
840 /* Power up the SCC & underlying hardware (modem/irda) */
841 pwr_delay = pmz_set_scc_power(uap, 1);
842
843 /* Nice buggy HW ... */
844 pmz_fix_zero_bug_scc(uap);
845
846 /* Reset the channel */
847 uap->curregs[R9] = 0;
848 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB);
849 zssync(uap);
850 udelay(10);
851 write_zsreg(uap, 9, 0);
852 zssync(uap);
853
854 /* Clear the interrupt registers */
855 write_zsreg(uap, R1, 0);
856 write_zsreg(uap, R0, ERR_RES);
857 write_zsreg(uap, R0, ERR_RES);
858 write_zsreg(uap, R0, RES_H_IUS);
859 write_zsreg(uap, R0, RES_H_IUS);
860
861 /* Setup some valid baud rate */
862 uap->curregs[R4] = X16CLK | SB1;
863 uap->curregs[R3] = Rx8;
864 uap->curregs[R5] = Tx8 | RTS;
865 if (!ZS_IS_IRDA(uap))
866 uap->curregs[R5] |= DTR;
867 uap->curregs[R12] = 0;
868 uap->curregs[R13] = 0;
869 uap->curregs[R14] = BRENAB;
870
871 /* Clear handshaking, enable BREAK interrupts */
872 uap->curregs[R15] = BRKIE;
873
874 /* Master interrupt enable */
875 uap->curregs[R9] |= NV | MIE;
876
877 pmz_load_zsregs(uap, uap->curregs);
878
879 /* Enable receiver and transmitter. */
880 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE);
881 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE);
882
883 /* Remember status for DCD/CTS changes */
884 uap->prev_status = read_zsreg(uap, R0);
885
886 return pwr_delay;
887}
888
889static void pmz_irda_reset(struct uart_pmac_port *uap)
890{
891 unsigned long flags;
892
893 spin_lock_irqsave(&uap->port.lock, flags);
894 uap->curregs[R5] |= DTR;
895 write_zsreg(uap, R5, uap->curregs[R5]);
896 zssync(uap);
897 spin_unlock_irqrestore(&uap->port.lock, flags);
898 msleep(110);
899
900 spin_lock_irqsave(&uap->port.lock, flags);
901 uap->curregs[R5] &= ~DTR;
902 write_zsreg(uap, R5, uap->curregs[R5]);
903 zssync(uap);
904 spin_unlock_irqrestore(&uap->port.lock, flags);
905 msleep(10);
906}
907
908/*
909 * This is the "normal" startup routine, using the above one
910 * wrapped with the lock and doing a schedule delay
911 */
912static int pmz_startup(struct uart_port *port)
913{
914 struct uart_pmac_port *uap = to_pmz(port);
915 unsigned long flags;
916 int pwr_delay = 0;
917
918 pmz_debug("pmz: startup()\n");
919
920 uap->flags |= PMACZILOG_FLAG_IS_OPEN;
921
922 /* A console is never powered down. Else, power up and
923 * initialize the chip
924 */
925 if (!ZS_IS_CONS(uap)) {
926 spin_lock_irqsave(&port->lock, flags);
927 pwr_delay = __pmz_startup(uap);
928 spin_unlock_irqrestore(&port->lock, flags);
929 }
930 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line);
931 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED,
932 uap->irq_name, uap)) {
933 pmz_error("Unable to register zs interrupt handler.\n");
934 pmz_set_scc_power(uap, 0);
935 return -ENXIO;
936 }
937
938 /* Right now, we deal with delay by blocking here, I'll be
939 * smarter later on
940 */
941 if (pwr_delay != 0) {
942 pmz_debug("pmz: delaying %d ms\n", pwr_delay);
943 msleep(pwr_delay);
944 }
945
946 /* IrDA reset is done now */
947 if (ZS_IS_IRDA(uap))
948 pmz_irda_reset(uap);
949
950 /* Enable interrupt requests for the channel */
951 spin_lock_irqsave(&port->lock, flags);
952 pmz_interrupt_control(uap, 1);
953 spin_unlock_irqrestore(&port->lock, flags);
954
955 pmz_debug("pmz: startup() done.\n");
956
957 return 0;
958}
959
960static void pmz_shutdown(struct uart_port *port)
961{
962 struct uart_pmac_port *uap = to_pmz(port);
963 unsigned long flags;
964
965 pmz_debug("pmz: shutdown()\n");
966
967 spin_lock_irqsave(&port->lock, flags);
968
969 /* Disable interrupt requests for the channel */
970 pmz_interrupt_control(uap, 0);
971
972 if (!ZS_IS_CONS(uap)) {
973 /* Disable receiver and transmitter */
974 uap->curregs[R3] &= ~RxENABLE;
975 uap->curregs[R5] &= ~TxENABLE;
976
977 /* Disable break assertion */
978 uap->curregs[R5] &= ~SND_BRK;
979 pmz_maybe_update_regs(uap);
980 }
981
982 spin_unlock_irqrestore(&port->lock, flags);
983
984 /* Release interrupt handler */
985 free_irq(uap->port.irq, uap);
986
987 spin_lock_irqsave(&port->lock, flags);
988
989 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN;
990
991 if (!ZS_IS_CONS(uap))
992 pmz_set_scc_power(uap, 0); /* Shut the chip down */
993
994 spin_unlock_irqrestore(&port->lock, flags);
995
996 pmz_debug("pmz: shutdown() done.\n");
997}
998
999/* Shared by TTY driver and serial console setup. The port lock is held
1000 * and local interrupts are disabled.
1001 */
1002static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag,
1003 unsigned int iflag, unsigned long baud)
1004{
1005 int brg;
1006
1007 /* Switch to external clocking for IrDA high clock rates. That
1008 * code could be re-used for Midi interfaces with different
1009 * multipliers
1010 */
1011 if (baud >= 115200 && ZS_IS_IRDA(uap)) {
1012 uap->curregs[R4] = X1CLK;
1013 uap->curregs[R11] = RCTRxCP | TCTRxCP;
1014 uap->curregs[R14] = 0; /* BRG off */
1015 uap->curregs[R12] = 0;
1016 uap->curregs[R13] = 0;
1017 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK;
1018 } else {
1019 switch (baud) {
1020 case ZS_CLOCK/16: /* 230400 */
1021 uap->curregs[R4] = X16CLK;
1022 uap->curregs[R11] = 0;
1023 uap->curregs[R14] = 0;
1024 break;
1025 case ZS_CLOCK/32: /* 115200 */
1026 uap->curregs[R4] = X32CLK;
1027 uap->curregs[R11] = 0;
1028 uap->curregs[R14] = 0;
1029 break;
1030 default:
1031 uap->curregs[R4] = X16CLK;
1032 uap->curregs[R11] = TCBR | RCBR;
1033 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16);
1034 uap->curregs[R12] = (brg & 255);
1035 uap->curregs[R13] = ((brg >> 8) & 255);
1036 uap->curregs[R14] = BRENAB;
1037 }
1038 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK;
1039 }
1040
1041 /* Character size, stop bits, and parity. */
1042 uap->curregs[3] &= ~RxN_MASK;
1043 uap->curregs[5] &= ~TxN_MASK;
1044
1045 switch (cflag & CSIZE) {
1046 case CS5:
1047 uap->curregs[3] |= Rx5;
1048 uap->curregs[5] |= Tx5;
1049 uap->parity_mask = 0x1f;
1050 break;
1051 case CS6:
1052 uap->curregs[3] |= Rx6;
1053 uap->curregs[5] |= Tx6;
1054 uap->parity_mask = 0x3f;
1055 break;
1056 case CS7:
1057 uap->curregs[3] |= Rx7;
1058 uap->curregs[5] |= Tx7;
1059 uap->parity_mask = 0x7f;
1060 break;
1061 case CS8:
1062 default:
1063 uap->curregs[3] |= Rx8;
1064 uap->curregs[5] |= Tx8;
1065 uap->parity_mask = 0xff;
1066 break;
1067 }
1068 uap->curregs[4] &= ~(SB_MASK);
1069 if (cflag & CSTOPB)
1070 uap->curregs[4] |= SB2;
1071 else
1072 uap->curregs[4] |= SB1;
1073 if (cflag & PARENB)
1074 uap->curregs[4] |= PAR_ENAB;
1075 else
1076 uap->curregs[4] &= ~PAR_ENAB;
1077 if (!(cflag & PARODD))
1078 uap->curregs[4] |= PAR_EVEN;
1079 else
1080 uap->curregs[4] &= ~PAR_EVEN;
1081
1082 uap->port.read_status_mask = Rx_OVR;
1083 if (iflag & INPCK)
1084 uap->port.read_status_mask |= CRC_ERR | PAR_ERR;
1085 if (iflag & (IGNBRK | BRKINT | PARMRK))
1086 uap->port.read_status_mask |= BRK_ABRT;
1087
1088 uap->port.ignore_status_mask = 0;
1089 if (iflag & IGNPAR)
1090 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
1091 if (iflag & IGNBRK) {
1092 uap->port.ignore_status_mask |= BRK_ABRT;
1093 if (iflag & IGNPAR)
1094 uap->port.ignore_status_mask |= Rx_OVR;
1095 }
1096
1097 if ((cflag & CREAD) == 0)
1098 uap->port.ignore_status_mask = 0xff;
1099}
1100
1101
1102/*
1103 * Set the irda codec on the imac to the specified baud rate.
1104 */
1105static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud)
1106{
1107 u8 cmdbyte;
1108 int t, version;
1109
1110 switch (*baud) {
1111 /* SIR modes */
1112 case 2400:
1113 cmdbyte = 0x53;
1114 break;
1115 case 4800:
1116 cmdbyte = 0x52;
1117 break;
1118 case 9600:
1119 cmdbyte = 0x51;
1120 break;
1121 case 19200:
1122 cmdbyte = 0x50;
1123 break;
1124 case 38400:
1125 cmdbyte = 0x4f;
1126 break;
1127 case 57600:
1128 cmdbyte = 0x4e;
1129 break;
1130 case 115200:
1131 cmdbyte = 0x4d;
1132 break;
1133 /* The FIR modes aren't really supported at this point, how
1134 * do we select the speed ? via the FCR on KeyLargo ?
1135 */
1136 case 1152000:
1137 cmdbyte = 0;
1138 break;
1139 case 4000000:
1140 cmdbyte = 0;
1141 break;
1142 default: /* 9600 */
1143 cmdbyte = 0x51;
1144 *baud = 9600;
1145 break;
1146 }
1147
1148 /* Wait for transmitter to drain */
1149 t = 10000;
1150 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0
1151 || (read_zsreg(uap, R1) & ALL_SNT) == 0) {
1152 if (--t <= 0) {
1153 pmz_error("transmitter didn't drain\n");
1154 return;
1155 }
1156 udelay(10);
1157 }
1158
1159 /* Drain the receiver too */
1160 t = 100;
1161 (void)read_zsdata(uap);
1162 (void)read_zsdata(uap);
1163 (void)read_zsdata(uap);
1164 mdelay(10);
1165 while (read_zsreg(uap, R0) & Rx_CH_AV) {
1166 read_zsdata(uap);
1167 mdelay(10);
1168 if (--t <= 0) {
1169 pmz_error("receiver didn't drain\n");
1170 return;
1171 }
1172 }
1173
1174 /* Switch to command mode */
1175 uap->curregs[R5] |= DTR;
1176 write_zsreg(uap, R5, uap->curregs[R5]);
1177 zssync(uap);
1178 mdelay(1);
1179
1180 /* Switch SCC to 19200 */
1181 pmz_convert_to_zs(uap, CS8, 0, 19200);
1182 pmz_load_zsregs(uap, uap->curregs);
1183 mdelay(1);
1184
1185 /* Write get_version command byte */
1186 write_zsdata(uap, 1);
1187 t = 5000;
1188 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1189 if (--t <= 0) {
1190 pmz_error("irda_setup timed out on get_version byte\n");
1191 goto out;
1192 }
1193 udelay(10);
1194 }
1195 version = read_zsdata(uap);
1196
1197 if (version < 4) {
1198 pmz_info("IrDA: dongle version %d not supported\n", version);
1199 goto out;
1200 }
1201
1202 /* Send speed mode */
1203 write_zsdata(uap, cmdbyte);
1204 t = 5000;
1205 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) {
1206 if (--t <= 0) {
1207 pmz_error("irda_setup timed out on speed mode byte\n");
1208 goto out;
1209 }
1210 udelay(10);
1211 }
1212 t = read_zsdata(uap);
1213 if (t != cmdbyte)
1214 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte);
1215
1216 pmz_info("IrDA setup for %ld bps, dongle version: %d\n",
1217 *baud, version);
1218
1219 (void)read_zsdata(uap);
1220 (void)read_zsdata(uap);
1221 (void)read_zsdata(uap);
1222
1223 out:
1224 /* Switch back to data mode */
1225 uap->curregs[R5] &= ~DTR;
1226 write_zsreg(uap, R5, uap->curregs[R5]);
1227 zssync(uap);
1228
1229 (void)read_zsdata(uap);
1230 (void)read_zsdata(uap);
1231 (void)read_zsdata(uap);
1232}
1233
1234
1235static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1236 struct ktermios *old)
1237{
1238 struct uart_pmac_port *uap = to_pmz(port);
1239 unsigned long baud;
1240
1241 pmz_debug("pmz: set_termios()\n");
1242
1243 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios));
1244
1245 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds
1246 * on the IR dongle. Note that the IRTTY driver currently doesn't know
1247 * about the FIR mode and high speed modes. So these are unused. For
1248 * implementing proper support for these, we should probably add some
1249 * DMA as well, at least on the Rx side, which isn't a simple thing
1250 * at this point.
1251 */
1252 if (ZS_IS_IRDA(uap)) {
1253 /* Calc baud rate */
1254 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000);
1255 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud);
1256 /* Cet the irda codec to the right rate */
1257 pmz_irda_setup(uap, &baud);
1258 /* Set final baud rate */
1259 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1260 pmz_load_zsregs(uap, uap->curregs);
1261 zssync(uap);
1262 } else {
1263 baud = uart_get_baud_rate(port, termios, old, 1200, 230400);
1264 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud);
1265 /* Make sure modem status interrupts are correctly configured */
1266 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) {
1267 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE;
1268 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS;
1269 } else {
1270 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE);
1271 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS;
1272 }
1273
1274 /* Load registers to the chip */
1275 pmz_maybe_update_regs(uap);
1276 }
1277 uart_update_timeout(port, termios->c_cflag, baud);
1278
1279 pmz_debug("pmz: set_termios() done.\n");
1280}
1281
1282/* The port lock is not held. */
1283static void pmz_set_termios(struct uart_port *port, struct ktermios *termios,
1284 struct ktermios *old)
1285{
1286 struct uart_pmac_port *uap = to_pmz(port);
1287 unsigned long flags;
1288
1289 spin_lock_irqsave(&port->lock, flags);
1290
1291 /* Disable IRQs on the port */
1292 pmz_interrupt_control(uap, 0);
1293
1294 /* Setup new port configuration */
1295 __pmz_set_termios(port, termios, old);
1296
1297 /* Re-enable IRQs on the port */
1298 if (ZS_IS_OPEN(uap))
1299 pmz_interrupt_control(uap, 1);
1300
1301 spin_unlock_irqrestore(&port->lock, flags);
1302}
1303
1304static const char *pmz_type(struct uart_port *port)
1305{
1306 struct uart_pmac_port *uap = to_pmz(port);
1307
1308 if (ZS_IS_IRDA(uap))
1309 return "Z85c30 ESCC - Infrared port";
1310 else if (ZS_IS_INTMODEM(uap))
1311 return "Z85c30 ESCC - Internal modem";
1312 return "Z85c30 ESCC - Serial port";
1313}
1314
1315/* We do not request/release mappings of the registers here, this
1316 * happens at early serial probe time.
1317 */
1318static void pmz_release_port(struct uart_port *port)
1319{
1320}
1321
1322static int pmz_request_port(struct uart_port *port)
1323{
1324 return 0;
1325}
1326
1327/* These do not need to do anything interesting either. */
1328static void pmz_config_port(struct uart_port *port, int flags)
1329{
1330}
1331
1332/* We do not support letting the user mess with the divisor, IRQ, etc. */
1333static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser)
1334{
1335 return -EINVAL;
1336}
1337
1338#ifdef CONFIG_CONSOLE_POLL
1339
1340static int pmz_poll_get_char(struct uart_port *port)
1341{
1342 struct uart_pmac_port *uap =
1343 container_of(port, struct uart_pmac_port, port);
1344 int tries = 2;
1345
1346 while (tries) {
1347 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0)
1348 return read_zsdata(uap);
1349 if (tries--)
1350 udelay(5);
1351 }
1352
1353 return NO_POLL_CHAR;
1354}
1355
1356static void pmz_poll_put_char(struct uart_port *port, unsigned char c)
1357{
1358 struct uart_pmac_port *uap =
1359 container_of(port, struct uart_pmac_port, port);
1360
1361 /* Wait for the transmit buffer to empty. */
1362 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1363 udelay(5);
1364 write_zsdata(uap, c);
1365}
1366
1367#endif /* CONFIG_CONSOLE_POLL */
1368
1369static const struct uart_ops pmz_pops = {
1370 .tx_empty = pmz_tx_empty,
1371 .set_mctrl = pmz_set_mctrl,
1372 .get_mctrl = pmz_get_mctrl,
1373 .stop_tx = pmz_stop_tx,
1374 .start_tx = pmz_start_tx,
1375 .stop_rx = pmz_stop_rx,
1376 .enable_ms = pmz_enable_ms,
1377 .break_ctl = pmz_break_ctl,
1378 .startup = pmz_startup,
1379 .shutdown = pmz_shutdown,
1380 .set_termios = pmz_set_termios,
1381 .type = pmz_type,
1382 .release_port = pmz_release_port,
1383 .request_port = pmz_request_port,
1384 .config_port = pmz_config_port,
1385 .verify_port = pmz_verify_port,
1386#ifdef CONFIG_CONSOLE_POLL
1387 .poll_get_char = pmz_poll_get_char,
1388 .poll_put_char = pmz_poll_put_char,
1389#endif
1390};
1391
1392#ifdef CONFIG_PPC_PMAC
1393
1394/*
1395 * Setup one port structure after probing, HW is down at this point,
1396 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't
1397 * register our console before uart_add_one_port() is called
1398 */
1399static int __init pmz_init_port(struct uart_pmac_port *uap)
1400{
1401 struct device_node *np = uap->node;
1402 const char *conn;
1403 const struct slot_names_prop {
1404 int count;
1405 char name[1];
1406 } *slots;
1407 int len;
1408 struct resource r_ports, r_rxdma, r_txdma;
1409
1410 /*
1411 * Request & map chip registers
1412 */
1413 if (of_address_to_resource(np, 0, &r_ports))
1414 return -ENODEV;
1415 uap->port.mapbase = r_ports.start;
1416 uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
1417
1418 uap->control_reg = uap->port.membase;
1419 uap->data_reg = uap->control_reg + 0x10;
1420
1421 /*
1422 * Request & map DBDMA registers
1423 */
1424#ifdef HAS_DBDMA
1425 if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
1426 of_address_to_resource(np, 2, &r_rxdma) == 0)
1427 uap->flags |= PMACZILOG_FLAG_HAS_DMA;
1428#else
1429 memset(&r_txdma, 0, sizeof(struct resource));
1430 memset(&r_rxdma, 0, sizeof(struct resource));
1431#endif
1432 if (ZS_HAS_DMA(uap)) {
1433 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
1434 if (uap->tx_dma_regs == NULL) {
1435 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1436 goto no_dma;
1437 }
1438 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
1439 if (uap->rx_dma_regs == NULL) {
1440 iounmap(uap->tx_dma_regs);
1441 uap->tx_dma_regs = NULL;
1442 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
1443 goto no_dma;
1444 }
1445 uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
1446 uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
1447 }
1448no_dma:
1449
1450 /*
1451 * Detect port type
1452 */
1453 if (of_device_is_compatible(np, "cobalt"))
1454 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1455 conn = of_get_property(np, "AAPL,connector", &len);
1456 if (conn && (strcmp(conn, "infrared") == 0))
1457 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1458 uap->port_type = PMAC_SCC_ASYNC;
1459 /* 1999 Powerbook G3 has slot-names property instead */
1460 slots = of_get_property(np, "slot-names", &len);
1461 if (slots && slots->count > 0) {
1462 if (strcmp(slots->name, "IrDA") == 0)
1463 uap->flags |= PMACZILOG_FLAG_IS_IRDA;
1464 else if (strcmp(slots->name, "Modem") == 0)
1465 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
1466 }
1467 if (ZS_IS_IRDA(uap))
1468 uap->port_type = PMAC_SCC_IRDA;
1469 if (ZS_IS_INTMODEM(uap)) {
1470 struct device_node* i2c_modem =
1471 of_find_node_by_name(NULL, "i2c-modem");
1472 if (i2c_modem) {
1473 const char* mid =
1474 of_get_property(i2c_modem, "modem-id", NULL);
1475 if (mid) switch(*mid) {
1476 case 0x04 :
1477 case 0x05 :
1478 case 0x07 :
1479 case 0x08 :
1480 case 0x0b :
1481 case 0x0c :
1482 uap->port_type = PMAC_SCC_I2S1;
1483 }
1484 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
1485 mid ? (*mid) : 0);
1486 of_node_put(i2c_modem);
1487 } else {
1488 printk(KERN_INFO "pmac_zilog: serial modem detected\n");
1489 }
1490 }
1491
1492 /*
1493 * Init remaining bits of "port" structure
1494 */
1495 uap->port.iotype = UPIO_MEM;
1496 uap->port.irq = irq_of_parse_and_map(np, 0);
1497 uap->port.uartclk = ZS_CLOCK;
1498 uap->port.fifosize = 1;
1499 uap->port.ops = &pmz_pops;
1500 uap->port.type = PORT_PMAC_ZILOG;
1501 uap->port.flags = 0;
1502
1503 /*
1504 * Fixup for the port on Gatwick for which the device-tree has
1505 * missing interrupts. Normally, the macio_dev would contain
1506 * fixed up interrupt info, but we use the device-tree directly
1507 * here due to early probing so we need the fixup too.
1508 */
1509 if (uap->port.irq == 0 &&
1510 np->parent && np->parent->parent &&
1511 of_device_is_compatible(np->parent->parent, "gatwick")) {
1512 /* IRQs on gatwick are offset by 64 */
1513 uap->port.irq = irq_create_mapping(NULL, 64 + 15);
1514 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4);
1515 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5);
1516 }
1517
1518 /* Setup some valid baud rate information in the register
1519 * shadows so we don't write crap there before baud rate is
1520 * first initialized.
1521 */
1522 pmz_convert_to_zs(uap, CS8, 0, 9600);
1523
1524 return 0;
1525}
1526
1527/*
1528 * Get rid of a port on module removal
1529 */
1530static void pmz_dispose_port(struct uart_pmac_port *uap)
1531{
1532 struct device_node *np;
1533
1534 np = uap->node;
1535 iounmap(uap->rx_dma_regs);
1536 iounmap(uap->tx_dma_regs);
1537 iounmap(uap->control_reg);
1538 uap->node = NULL;
1539 of_node_put(np);
1540 memset(uap, 0, sizeof(struct uart_pmac_port));
1541}
1542
1543/*
1544 * Called upon match with an escc node in the device-tree.
1545 */
1546static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match)
1547{
1548 struct uart_pmac_port *uap;
1549 int i;
1550
1551 /* Iterate the pmz_ports array to find a matching entry
1552 */
1553 for (i = 0; i < MAX_ZS_PORTS; i++)
1554 if (pmz_ports[i].node == mdev->ofdev.dev.of_node)
1555 break;
1556 if (i >= MAX_ZS_PORTS)
1557 return -ENODEV;
1558
1559
1560 uap = &pmz_ports[i];
1561 uap->dev = mdev;
1562 uap->port.dev = &mdev->ofdev.dev;
1563 dev_set_drvdata(&mdev->ofdev.dev, uap);
1564
1565 /* We still activate the port even when failing to request resources
1566 * to work around bugs in ancient Apple device-trees
1567 */
1568 if (macio_request_resources(uap->dev, "pmac_zilog"))
1569 printk(KERN_WARNING "%s: Failed to request resource"
1570 ", port still active\n",
1571 uap->node->name);
1572 else
1573 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED;
1574
1575 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1576}
1577
1578/*
1579 * That one should not be called, macio isn't really a hotswap device,
1580 * we don't expect one of those serial ports to go away...
1581 */
1582static int pmz_detach(struct macio_dev *mdev)
1583{
1584 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1585
1586 if (!uap)
1587 return -ENODEV;
1588
1589 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1590
1591 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) {
1592 macio_release_resources(uap->dev);
1593 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED;
1594 }
1595 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1596 uap->dev = NULL;
1597 uap->port.dev = NULL;
1598
1599 return 0;
1600}
1601
1602
1603static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state)
1604{
1605 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1606
1607 if (uap == NULL) {
1608 printk("HRM... pmz_suspend with NULL uap\n");
1609 return 0;
1610 }
1611
1612 uart_suspend_port(&pmz_uart_reg, &uap->port);
1613
1614 return 0;
1615}
1616
1617
1618static int pmz_resume(struct macio_dev *mdev)
1619{
1620 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev);
1621
1622 if (uap == NULL)
1623 return 0;
1624
1625 uart_resume_port(&pmz_uart_reg, &uap->port);
1626
1627 return 0;
1628}
1629
1630/*
1631 * Probe all ports in the system and build the ports array, we register
1632 * with the serial layer later, so we get a proper struct device which
1633 * allows the tty to attach properly. This is later than it used to be
1634 * but the tty layer really wants it that way.
1635 */
1636static int __init pmz_probe(void)
1637{
1638 struct device_node *node_p, *node_a, *node_b, *np;
1639 int count = 0;
1640 int rc;
1641
1642 /*
1643 * Find all escc chips in the system
1644 */
1645 for_each_node_by_name(node_p, "escc") {
1646 /*
1647 * First get channel A/B node pointers
1648 *
1649 * TODO: Add routines with proper locking to do that...
1650 */
1651 node_a = node_b = NULL;
1652 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) {
1653 if (strncmp(np->name, "ch-a", 4) == 0)
1654 node_a = of_node_get(np);
1655 else if (strncmp(np->name, "ch-b", 4) == 0)
1656 node_b = of_node_get(np);
1657 }
1658 if (!node_a && !node_b) {
1659 of_node_put(node_a);
1660 of_node_put(node_b);
1661 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n",
1662 (!node_a) ? 'a' : 'b', node_p);
1663 continue;
1664 }
1665
1666 /*
1667 * Fill basic fields in the port structures
1668 */
1669 if (node_b != NULL) {
1670 pmz_ports[count].mate = &pmz_ports[count+1];
1671 pmz_ports[count+1].mate = &pmz_ports[count];
1672 }
1673 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1674 pmz_ports[count].node = node_a;
1675 pmz_ports[count+1].node = node_b;
1676 pmz_ports[count].port.line = count;
1677 pmz_ports[count+1].port.line = count+1;
1678
1679 /*
1680 * Setup the ports for real
1681 */
1682 rc = pmz_init_port(&pmz_ports[count]);
1683 if (rc == 0 && node_b != NULL)
1684 rc = pmz_init_port(&pmz_ports[count+1]);
1685 if (rc != 0) {
1686 of_node_put(node_a);
1687 of_node_put(node_b);
1688 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port));
1689 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port));
1690 continue;
1691 }
1692 count += 2;
1693 }
1694 pmz_ports_count = count;
1695
1696 return 0;
1697}
1698
1699#else
1700
1701extern struct platform_device scc_a_pdev, scc_b_pdev;
1702
1703static int __init pmz_init_port(struct uart_pmac_port *uap)
1704{
1705 struct resource *r_ports;
1706 int irq;
1707
1708 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0);
1709 irq = platform_get_irq(uap->pdev, 0);
1710 if (!r_ports || irq <= 0)
1711 return -ENODEV;
1712
1713 uap->port.mapbase = r_ports->start;
1714 uap->port.membase = (unsigned char __iomem *) r_ports->start;
1715 uap->port.iotype = UPIO_MEM;
1716 uap->port.irq = irq;
1717 uap->port.uartclk = ZS_CLOCK;
1718 uap->port.fifosize = 1;
1719 uap->port.ops = &pmz_pops;
1720 uap->port.type = PORT_PMAC_ZILOG;
1721 uap->port.flags = 0;
1722
1723 uap->control_reg = uap->port.membase;
1724 uap->data_reg = uap->control_reg + 4;
1725 uap->port_type = 0;
1726
1727 pmz_convert_to_zs(uap, CS8, 0, 9600);
1728
1729 return 0;
1730}
1731
1732static int __init pmz_probe(void)
1733{
1734 int err;
1735
1736 pmz_ports_count = 0;
1737
1738 pmz_ports[0].port.line = 0;
1739 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A;
1740 pmz_ports[0].pdev = &scc_a_pdev;
1741 err = pmz_init_port(&pmz_ports[0]);
1742 if (err)
1743 return err;
1744 pmz_ports_count++;
1745
1746 pmz_ports[0].mate = &pmz_ports[1];
1747 pmz_ports[1].mate = &pmz_ports[0];
1748 pmz_ports[1].port.line = 1;
1749 pmz_ports[1].flags = 0;
1750 pmz_ports[1].pdev = &scc_b_pdev;
1751 err = pmz_init_port(&pmz_ports[1]);
1752 if (err)
1753 return err;
1754 pmz_ports_count++;
1755
1756 return 0;
1757}
1758
1759static void pmz_dispose_port(struct uart_pmac_port *uap)
1760{
1761 memset(uap, 0, sizeof(struct uart_pmac_port));
1762}
1763
1764static int __init pmz_attach(struct platform_device *pdev)
1765{
1766 struct uart_pmac_port *uap;
1767 int i;
1768
1769 /* Iterate the pmz_ports array to find a matching entry */
1770 for (i = 0; i < pmz_ports_count; i++)
1771 if (pmz_ports[i].pdev == pdev)
1772 break;
1773 if (i >= pmz_ports_count)
1774 return -ENODEV;
1775
1776 uap = &pmz_ports[i];
1777 uap->port.dev = &pdev->dev;
1778 platform_set_drvdata(pdev, uap);
1779
1780 return uart_add_one_port(&pmz_uart_reg, &uap->port);
1781}
1782
1783static int __exit pmz_detach(struct platform_device *pdev)
1784{
1785 struct uart_pmac_port *uap = platform_get_drvdata(pdev);
1786
1787 if (!uap)
1788 return -ENODEV;
1789
1790 uart_remove_one_port(&pmz_uart_reg, &uap->port);
1791
1792 uap->port.dev = NULL;
1793
1794 return 0;
1795}
1796
1797#endif /* !CONFIG_PPC_PMAC */
1798
1799#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1800
1801static void pmz_console_write(struct console *con, const char *s, unsigned int count);
1802static int __init pmz_console_setup(struct console *co, char *options);
1803
1804static struct console pmz_console = {
1805 .name = PMACZILOG_NAME,
1806 .write = pmz_console_write,
1807 .device = uart_console_device,
1808 .setup = pmz_console_setup,
1809 .flags = CON_PRINTBUFFER,
1810 .index = -1,
1811 .data = &pmz_uart_reg,
1812};
1813
1814#define PMACZILOG_CONSOLE &pmz_console
1815#else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1816#define PMACZILOG_CONSOLE (NULL)
1817#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
1818
1819/*
1820 * Register the driver, console driver and ports with the serial
1821 * core
1822 */
1823static int __init pmz_register(void)
1824{
1825 pmz_uart_reg.nr = pmz_ports_count;
1826 pmz_uart_reg.cons = PMACZILOG_CONSOLE;
1827
1828 /*
1829 * Register this driver with the serial core
1830 */
1831 return uart_register_driver(&pmz_uart_reg);
1832}
1833
1834#ifdef CONFIG_PPC_PMAC
1835
1836static const struct of_device_id pmz_match[] =
1837{
1838 {
1839 .name = "ch-a",
1840 },
1841 {
1842 .name = "ch-b",
1843 },
1844 {},
1845};
1846MODULE_DEVICE_TABLE (of, pmz_match);
1847
1848static struct macio_driver pmz_driver = {
1849 .driver = {
1850 .name = "pmac_zilog",
1851 .owner = THIS_MODULE,
1852 .of_match_table = pmz_match,
1853 },
1854 .probe = pmz_attach,
1855 .remove = pmz_detach,
1856 .suspend = pmz_suspend,
1857 .resume = pmz_resume,
1858};
1859
1860#else
1861
1862static struct platform_driver pmz_driver = {
1863 .remove = __exit_p(pmz_detach),
1864 .driver = {
1865 .name = "scc",
1866 },
1867};
1868
1869#endif /* !CONFIG_PPC_PMAC */
1870
1871static int __init init_pmz(void)
1872{
1873 int rc, i;
1874 printk(KERN_INFO "%s\n", version);
1875
1876 /*
1877 * First, we need to do a direct OF-based probe pass. We
1878 * do that because we want serial console up before the
1879 * macio stuffs calls us back, and since that makes it
1880 * easier to pass the proper number of channels to
1881 * uart_register_driver()
1882 */
1883 if (pmz_ports_count == 0)
1884 pmz_probe();
1885
1886 /*
1887 * Bail early if no port found
1888 */
1889 if (pmz_ports_count == 0)
1890 return -ENODEV;
1891
1892 /*
1893 * Now we register with the serial layer
1894 */
1895 rc = pmz_register();
1896 if (rc) {
1897 printk(KERN_ERR
1898 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n"
1899 "pmac_zilog: Did another serial driver already claim the minors?\n");
1900 /* effectively "pmz_unprobe()" */
1901 for (i=0; i < pmz_ports_count; i++)
1902 pmz_dispose_port(&pmz_ports[i]);
1903 return rc;
1904 }
1905
1906 /*
1907 * Then we register the macio driver itself
1908 */
1909#ifdef CONFIG_PPC_PMAC
1910 return macio_register_driver(&pmz_driver);
1911#else
1912 return platform_driver_probe(&pmz_driver, pmz_attach);
1913#endif
1914}
1915
1916static void __exit exit_pmz(void)
1917{
1918 int i;
1919
1920#ifdef CONFIG_PPC_PMAC
1921 /* Get rid of macio-driver (detach from macio) */
1922 macio_unregister_driver(&pmz_driver);
1923#else
1924 platform_driver_unregister(&pmz_driver);
1925#endif
1926
1927 for (i = 0; i < pmz_ports_count; i++) {
1928 struct uart_pmac_port *uport = &pmz_ports[i];
1929#ifdef CONFIG_PPC_PMAC
1930 if (uport->node != NULL)
1931 pmz_dispose_port(uport);
1932#else
1933 if (uport->pdev != NULL)
1934 pmz_dispose_port(uport);
1935#endif
1936 }
1937 /* Unregister UART driver */
1938 uart_unregister_driver(&pmz_uart_reg);
1939}
1940
1941#ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE
1942
1943static void pmz_console_putchar(struct uart_port *port, int ch)
1944{
1945 struct uart_pmac_port *uap =
1946 container_of(port, struct uart_pmac_port, port);
1947
1948 /* Wait for the transmit buffer to empty. */
1949 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0)
1950 udelay(5);
1951 write_zsdata(uap, ch);
1952}
1953
1954/*
1955 * Print a string to the serial port trying not to disturb
1956 * any possible real use of the port...
1957 */
1958static void pmz_console_write(struct console *con, const char *s, unsigned int count)
1959{
1960 struct uart_pmac_port *uap = &pmz_ports[con->index];
1961 unsigned long flags;
1962
1963 spin_lock_irqsave(&uap->port.lock, flags);
1964
1965 /* Turn of interrupts and enable the transmitter. */
1966 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB);
1967 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR);
1968
1969 uart_console_write(&uap->port, s, count, pmz_console_putchar);
1970
1971 /* Restore the values in the registers. */
1972 write_zsreg(uap, R1, uap->curregs[1]);
1973 /* Don't disable the transmitter. */
1974
1975 spin_unlock_irqrestore(&uap->port.lock, flags);
1976}
1977
1978/*
1979 * Setup the serial console
1980 */
1981static int __init pmz_console_setup(struct console *co, char *options)
1982{
1983 struct uart_pmac_port *uap;
1984 struct uart_port *port;
1985 int baud = 38400;
1986 int bits = 8;
1987 int parity = 'n';
1988 int flow = 'n';
1989 unsigned long pwr_delay;
1990
1991 /*
1992 * XServe's default to 57600 bps
1993 */
1994 if (of_machine_is_compatible("RackMac1,1")
1995 || of_machine_is_compatible("RackMac1,2")
1996 || of_machine_is_compatible("MacRISC4"))
1997 baud = 57600;
1998
1999 /*
2000 * Check whether an invalid uart number has been specified, and
2001 * if so, search for the first available port that does have
2002 * console support.
2003 */
2004 if (co->index >= pmz_ports_count)
2005 co->index = 0;
2006 uap = &pmz_ports[co->index];
2007#ifdef CONFIG_PPC_PMAC
2008 if (uap->node == NULL)
2009 return -ENODEV;
2010#else
2011 if (uap->pdev == NULL)
2012 return -ENODEV;
2013#endif
2014 port = &uap->port;
2015
2016 /*
2017 * Mark port as beeing a console
2018 */
2019 uap->flags |= PMACZILOG_FLAG_IS_CONS;
2020
2021 /*
2022 * Temporary fix for uart layer who didn't setup the spinlock yet
2023 */
2024 spin_lock_init(&port->lock);
2025
2026 /*
2027 * Enable the hardware
2028 */
2029 pwr_delay = __pmz_startup(uap);
2030 if (pwr_delay)
2031 mdelay(pwr_delay);
2032
2033 if (options)
2034 uart_parse_options(options, &baud, &parity, &bits, &flow);
2035
2036 return uart_set_options(port, co, baud, parity, bits, flow);
2037}
2038
2039static int __init pmz_console_init(void)
2040{
2041 /* Probe ports */
2042 pmz_probe();
2043
2044 if (pmz_ports_count == 0)
2045 return -ENODEV;
2046
2047 /* TODO: Autoprobe console based on OF */
2048 /* pmz_console.index = i; */
2049 register_console(&pmz_console);
2050
2051 return 0;
2052
2053}
2054console_initcall(pmz_console_init);
2055#endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */
2056
2057module_init(init_pmz);
2058module_exit(exit_pmz);