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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * High Speed Serial Ports on NXP LPC32xx SoC
4 *
5 * Authors: Kevin Wells <kevin.wells@nxp.com>
6 * Roland Stigge <stigge@antcom.de>
7 *
8 * Copyright (C) 2010 NXP Semiconductors
9 * Copyright (C) 2012 Roland Stigge
10 */
11
12#include <linux/module.h>
13#include <linux/ioport.h>
14#include <linux/init.h>
15#include <linux/console.h>
16#include <linux/sysrq.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/nmi.h>
24#include <linux/io.h>
25#include <linux/irq.h>
26#include <linux/of.h>
27#include <linux/sizes.h>
28#include <linux/soc/nxp/lpc32xx-misc.h>
29
30/*
31 * High Speed UART register offsets
32 */
33#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
34#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
35#define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
36#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
37#define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
38
39#define LPC32XX_HSU_BREAK_DATA (1 << 10)
40#define LPC32XX_HSU_ERROR_DATA (1 << 9)
41#define LPC32XX_HSU_RX_EMPTY (1 << 8)
42
43#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
44#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
45
46#define LPC32XX_HSU_TX_INT_SET (1 << 6)
47#define LPC32XX_HSU_RX_OE_INT (1 << 5)
48#define LPC32XX_HSU_BRK_INT (1 << 4)
49#define LPC32XX_HSU_FE_INT (1 << 3)
50#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
51#define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
52#define LPC32XX_HSU_TX_INT (1 << 0)
53
54#define LPC32XX_HSU_HRTS_INV (1 << 21)
55#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
56#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
57#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
58#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
59#define LPC32XX_HSU_HRTS_EN (1 << 18)
60#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
61#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
62#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
63#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
64#define LPC32XX_HSU_HCTS_INV (1 << 15)
65#define LPC32XX_HSU_HCTS_EN (1 << 14)
66#define LPC32XX_HSU_OFFSET(n) ((n) << 9)
67#define LPC32XX_HSU_BREAK (1 << 8)
68#define LPC32XX_HSU_ERR_INT_EN (1 << 7)
69#define LPC32XX_HSU_RX_INT_EN (1 << 6)
70#define LPC32XX_HSU_TX_INT_EN (1 << 5)
71#define LPC32XX_HSU_RX_TL1B (0x0 << 2)
72#define LPC32XX_HSU_RX_TL4B (0x1 << 2)
73#define LPC32XX_HSU_RX_TL8B (0x2 << 2)
74#define LPC32XX_HSU_RX_TL16B (0x3 << 2)
75#define LPC32XX_HSU_RX_TL32B (0x4 << 2)
76#define LPC32XX_HSU_RX_TL48B (0x5 << 2)
77#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
78#define LPC32XX_HSU_TX_TL0B (0x0 << 0)
79#define LPC32XX_HSU_TX_TL4B (0x1 << 0)
80#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
81#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
82
83#define LPC32XX_MAIN_OSC_FREQ 13000000
84
85#define MODNAME "lpc32xx_hsuart"
86
87struct lpc32xx_hsuart_port {
88 struct uart_port port;
89};
90
91#define FIFO_READ_LIMIT 128
92#define MAX_PORTS 3
93#define LPC32XX_TTY_NAME "ttyTX"
94static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
95
96#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
97static void wait_for_xmit_empty(struct uart_port *port)
98{
99 unsigned int timeout = 10000;
100
101 do {
102 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
103 port->membase))) == 0)
104 break;
105 if (--timeout == 0)
106 break;
107 udelay(1);
108 } while (1);
109}
110
111static void wait_for_xmit_ready(struct uart_port *port)
112{
113 unsigned int timeout = 10000;
114
115 while (1) {
116 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
117 port->membase))) < 32)
118 break;
119 if (--timeout == 0)
120 break;
121 udelay(1);
122 }
123}
124
125static void lpc32xx_hsuart_console_putchar(struct uart_port *port, unsigned char ch)
126{
127 wait_for_xmit_ready(port);
128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
129}
130
131static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
132 unsigned int count)
133{
134 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
135 unsigned long flags;
136 int locked = 1;
137
138 touch_nmi_watchdog();
139 local_irq_save(flags);
140 if (up->port.sysrq)
141 locked = 0;
142 else if (oops_in_progress)
143 locked = uart_port_trylock(&up->port);
144 else
145 uart_port_lock(&up->port);
146
147 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
148 wait_for_xmit_empty(&up->port);
149
150 if (locked)
151 uart_port_unlock(&up->port);
152 local_irq_restore(flags);
153}
154
155static int __init lpc32xx_hsuart_console_setup(struct console *co,
156 char *options)
157{
158 struct uart_port *port;
159 int baud = 115200;
160 int bits = 8;
161 int parity = 'n';
162 int flow = 'n';
163
164 if (co->index >= MAX_PORTS)
165 co->index = 0;
166
167 port = &lpc32xx_hs_ports[co->index].port;
168 if (!port->membase)
169 return -ENODEV;
170
171 if (options)
172 uart_parse_options(options, &baud, &parity, &bits, &flow);
173
174 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
175
176 return uart_set_options(port, co, baud, parity, bits, flow);
177}
178
179static struct uart_driver lpc32xx_hsuart_reg;
180static struct console lpc32xx_hsuart_console = {
181 .name = LPC32XX_TTY_NAME,
182 .write = lpc32xx_hsuart_console_write,
183 .device = uart_console_device,
184 .setup = lpc32xx_hsuart_console_setup,
185 .flags = CON_PRINTBUFFER,
186 .index = -1,
187 .data = &lpc32xx_hsuart_reg,
188};
189
190static int __init lpc32xx_hsuart_console_init(void)
191{
192 register_console(&lpc32xx_hsuart_console);
193 return 0;
194}
195console_initcall(lpc32xx_hsuart_console_init);
196
197#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
198#else
199#define LPC32XX_HSUART_CONSOLE NULL
200#endif
201
202static struct uart_driver lpc32xx_hs_reg = {
203 .owner = THIS_MODULE,
204 .driver_name = MODNAME,
205 .dev_name = LPC32XX_TTY_NAME,
206 .nr = MAX_PORTS,
207 .cons = LPC32XX_HSUART_CONSOLE,
208};
209static int uarts_registered;
210
211static unsigned int __serial_get_clock_div(unsigned long uartclk,
212 unsigned long rate)
213{
214 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
215 u32 rate_diff;
216
217 /* Find the closest divider to get the desired clock rate */
218 div = uartclk / rate;
219 goodrate = hsu_rate = (div / 14) - 1;
220 if (hsu_rate != 0)
221 hsu_rate--;
222
223 /* Tweak divider */
224 l_hsu_rate = hsu_rate + 3;
225 rate_diff = 0xFFFFFFFF;
226
227 while (hsu_rate < l_hsu_rate) {
228 comprate = uartclk / ((hsu_rate + 1) * 14);
229 if (abs(comprate - rate) < rate_diff) {
230 goodrate = hsu_rate;
231 rate_diff = abs(comprate - rate);
232 }
233
234 hsu_rate++;
235 }
236 if (hsu_rate > 0xFF)
237 hsu_rate = 0xFF;
238
239 return goodrate;
240}
241
242static void __serial_uart_flush(struct uart_port *port)
243{
244 int cnt = 0;
245
246 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
247 (cnt++ < FIFO_READ_LIMIT))
248 readl(LPC32XX_HSUART_FIFO(port->membase));
249}
250
251static void __serial_lpc32xx_rx(struct uart_port *port)
252{
253 struct tty_port *tport = &port->state->port;
254 unsigned int tmp, flag;
255
256 /* Read data from FIFO and push into terminal */
257 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
258 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
259 flag = TTY_NORMAL;
260 port->icount.rx++;
261
262 if (tmp & LPC32XX_HSU_ERROR_DATA) {
263 /* Framing error */
264 writel(LPC32XX_HSU_FE_INT,
265 LPC32XX_HSUART_IIR(port->membase));
266 port->icount.frame++;
267 flag = TTY_FRAME;
268 tty_insert_flip_char(tport, 0, TTY_FRAME);
269 }
270
271 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
272
273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
274 }
275
276 tty_flip_buffer_push(tport);
277}
278
279static bool serial_lpc32xx_tx_ready(struct uart_port *port)
280{
281 u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase));
282
283 return LPC32XX_HSU_TX_LEV(level) < 64;
284}
285
286static void __serial_lpc32xx_tx(struct uart_port *port)
287{
288 u8 ch;
289
290 uart_port_tx(port, ch,
291 serial_lpc32xx_tx_ready(port),
292 writel(ch, LPC32XX_HSUART_FIFO(port->membase)));
293}
294
295static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
296{
297 struct uart_port *port = dev_id;
298 struct tty_port *tport = &port->state->port;
299 u32 status;
300
301 uart_port_lock(port);
302
303 /* Read UART status and clear latched interrupts */
304 status = readl(LPC32XX_HSUART_IIR(port->membase));
305
306 if (status & LPC32XX_HSU_BRK_INT) {
307 /* Break received */
308 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
309 port->icount.brk++;
310 uart_handle_break(port);
311 }
312
313 /* Framing error */
314 if (status & LPC32XX_HSU_FE_INT)
315 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
316
317 if (status & LPC32XX_HSU_RX_OE_INT) {
318 /* Receive FIFO overrun */
319 writel(LPC32XX_HSU_RX_OE_INT,
320 LPC32XX_HSUART_IIR(port->membase));
321 port->icount.overrun++;
322 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
323 tty_flip_buffer_push(tport);
324 }
325
326 /* Data received? */
327 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
328 __serial_lpc32xx_rx(port);
329
330 /* Transmit data request? */
331 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
332 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
333 __serial_lpc32xx_tx(port);
334 }
335
336 uart_port_unlock(port);
337
338 return IRQ_HANDLED;
339}
340
341/* port->lock is not held. */
342static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
343{
344 unsigned int ret = 0;
345
346 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
347 ret = TIOCSER_TEMT;
348
349 return ret;
350}
351
352/* port->lock held by caller. */
353static void serial_lpc32xx_set_mctrl(struct uart_port *port,
354 unsigned int mctrl)
355{
356 /* No signals are supported on HS UARTs */
357}
358
359/* port->lock is held by caller and interrupts are disabled. */
360static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
361{
362 /* No signals are supported on HS UARTs */
363 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
364}
365
366/* port->lock held by caller. */
367static void serial_lpc32xx_stop_tx(struct uart_port *port)
368{
369 u32 tmp;
370
371 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
372 tmp &= ~LPC32XX_HSU_TX_INT_EN;
373 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
374}
375
376/* port->lock held by caller. */
377static void serial_lpc32xx_start_tx(struct uart_port *port)
378{
379 u32 tmp;
380
381 __serial_lpc32xx_tx(port);
382 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
383 tmp |= LPC32XX_HSU_TX_INT_EN;
384 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
385}
386
387/* port->lock held by caller. */
388static void serial_lpc32xx_stop_rx(struct uart_port *port)
389{
390 u32 tmp;
391
392 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
393 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
394 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
395
396 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
397 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
398}
399
400/* port->lock is not held. */
401static void serial_lpc32xx_break_ctl(struct uart_port *port,
402 int break_state)
403{
404 unsigned long flags;
405 u32 tmp;
406
407 uart_port_lock_irqsave(port, &flags);
408 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
409 if (break_state != 0)
410 tmp |= LPC32XX_HSU_BREAK;
411 else
412 tmp &= ~LPC32XX_HSU_BREAK;
413 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
414 uart_port_unlock_irqrestore(port, flags);
415}
416
417/* port->lock is not held. */
418static int serial_lpc32xx_startup(struct uart_port *port)
419{
420 int retval;
421 unsigned long flags;
422 u32 tmp;
423
424 uart_port_lock_irqsave(port, &flags);
425
426 __serial_uart_flush(port);
427
428 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
429 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
430 LPC32XX_HSUART_IIR(port->membase));
431
432 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
433
434 /*
435 * Set receiver timeout, HSU offset of 20, no break, no interrupts,
436 * and default FIFO trigger levels
437 */
438 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
439 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
440 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
441
442 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
443
444 uart_port_unlock_irqrestore(port, flags);
445
446 retval = request_irq(port->irq, serial_lpc32xx_interrupt,
447 0, MODNAME, port);
448 if (!retval)
449 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
450 LPC32XX_HSUART_CTRL(port->membase));
451
452 return retval;
453}
454
455/* port->lock is not held. */
456static void serial_lpc32xx_shutdown(struct uart_port *port)
457{
458 u32 tmp;
459 unsigned long flags;
460
461 uart_port_lock_irqsave(port, &flags);
462
463 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
464 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
465 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
466
467 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
468
469 uart_port_unlock_irqrestore(port, flags);
470
471 free_irq(port->irq, port);
472}
473
474/* port->lock is not held. */
475static void serial_lpc32xx_set_termios(struct uart_port *port,
476 struct ktermios *termios,
477 const struct ktermios *old)
478{
479 unsigned long flags;
480 unsigned int baud, quot;
481 u32 tmp;
482
483 /* Always 8-bit, no parity, 1 stop bit */
484 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
485 termios->c_cflag |= CS8;
486
487 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
488
489 baud = uart_get_baud_rate(port, termios, old, 0,
490 port->uartclk / 14);
491
492 quot = __serial_get_clock_div(port->uartclk, baud);
493
494 uart_port_lock_irqsave(port, &flags);
495
496 /* Ignore characters? */
497 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
498 if ((termios->c_cflag & CREAD) == 0)
499 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
500 else
501 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
502 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
503
504 writel(quot, LPC32XX_HSUART_RATE(port->membase));
505
506 uart_update_timeout(port, termios->c_cflag, baud);
507
508 uart_port_unlock_irqrestore(port, flags);
509
510 /* Don't rewrite B0 */
511 if (tty_termios_baud_rate(termios))
512 tty_termios_encode_baud_rate(termios, baud, baud);
513}
514
515static const char *serial_lpc32xx_type(struct uart_port *port)
516{
517 return MODNAME;
518}
519
520static void serial_lpc32xx_release_port(struct uart_port *port)
521{
522 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
523 if (port->flags & UPF_IOREMAP) {
524 iounmap(port->membase);
525 port->membase = NULL;
526 }
527
528 release_mem_region(port->mapbase, SZ_4K);
529 }
530}
531
532static int serial_lpc32xx_request_port(struct uart_port *port)
533{
534 int ret = -ENODEV;
535
536 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
537 ret = 0;
538
539 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
540 ret = -EBUSY;
541 else if (port->flags & UPF_IOREMAP) {
542 port->membase = ioremap(port->mapbase, SZ_4K);
543 if (!port->membase) {
544 release_mem_region(port->mapbase, SZ_4K);
545 ret = -ENOMEM;
546 }
547 }
548 }
549
550 return ret;
551}
552
553static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
554{
555 int ret;
556
557 ret = serial_lpc32xx_request_port(port);
558 if (ret < 0)
559 return;
560 port->type = PORT_UART00;
561 port->fifosize = 64;
562
563 __serial_uart_flush(port);
564
565 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
566 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
567 LPC32XX_HSUART_IIR(port->membase));
568
569 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
570
571 /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
572 and default FIFO trigger levels */
573 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
574 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
575 LPC32XX_HSUART_CTRL(port->membase));
576}
577
578static int serial_lpc32xx_verify_port(struct uart_port *port,
579 struct serial_struct *ser)
580{
581 int ret = 0;
582
583 if (ser->type != PORT_UART00)
584 ret = -EINVAL;
585
586 return ret;
587}
588
589static const struct uart_ops serial_lpc32xx_pops = {
590 .tx_empty = serial_lpc32xx_tx_empty,
591 .set_mctrl = serial_lpc32xx_set_mctrl,
592 .get_mctrl = serial_lpc32xx_get_mctrl,
593 .stop_tx = serial_lpc32xx_stop_tx,
594 .start_tx = serial_lpc32xx_start_tx,
595 .stop_rx = serial_lpc32xx_stop_rx,
596 .break_ctl = serial_lpc32xx_break_ctl,
597 .startup = serial_lpc32xx_startup,
598 .shutdown = serial_lpc32xx_shutdown,
599 .set_termios = serial_lpc32xx_set_termios,
600 .type = serial_lpc32xx_type,
601 .release_port = serial_lpc32xx_release_port,
602 .request_port = serial_lpc32xx_request_port,
603 .config_port = serial_lpc32xx_config_port,
604 .verify_port = serial_lpc32xx_verify_port,
605};
606
607/*
608 * Register a set of serial devices attached to a platform device
609 */
610static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
611{
612 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
613 int ret = 0;
614 struct resource *res;
615
616 if (uarts_registered >= MAX_PORTS) {
617 dev_err(&pdev->dev,
618 "Error: Number of possible ports exceeded (%d)!\n",
619 uarts_registered + 1);
620 return -ENXIO;
621 }
622
623 memset(p, 0, sizeof(*p));
624
625 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626 if (!res) {
627 dev_err(&pdev->dev,
628 "Error getting mem resource for HS UART port %d\n",
629 uarts_registered);
630 return -ENXIO;
631 }
632 p->port.mapbase = res->start;
633 p->port.membase = NULL;
634
635 ret = platform_get_irq(pdev, 0);
636 if (ret < 0)
637 return ret;
638 p->port.irq = ret;
639
640 p->port.iotype = UPIO_MEM32;
641 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
642 p->port.regshift = 2;
643 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
644 p->port.dev = &pdev->dev;
645 p->port.ops = &serial_lpc32xx_pops;
646 p->port.line = uarts_registered++;
647 spin_lock_init(&p->port.lock);
648
649 /* send port to loopback mode by default */
650 lpc32xx_loopback_set(p->port.mapbase, 1);
651
652 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
653
654 platform_set_drvdata(pdev, p);
655
656 return ret;
657}
658
659/*
660 * Remove serial ports registered against a platform device.
661 */
662static void serial_hs_lpc32xx_remove(struct platform_device *pdev)
663{
664 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
665
666 uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
667}
668
669
670#ifdef CONFIG_PM
671static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
672 pm_message_t state)
673{
674 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
675
676 uart_suspend_port(&lpc32xx_hs_reg, &p->port);
677
678 return 0;
679}
680
681static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
682{
683 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
684
685 uart_resume_port(&lpc32xx_hs_reg, &p->port);
686
687 return 0;
688}
689#else
690#define serial_hs_lpc32xx_suspend NULL
691#define serial_hs_lpc32xx_resume NULL
692#endif
693
694static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
695 { .compatible = "nxp,lpc3220-hsuart" },
696 { /* sentinel */ }
697};
698
699MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
700
701static struct platform_driver serial_hs_lpc32xx_driver = {
702 .probe = serial_hs_lpc32xx_probe,
703 .remove_new = serial_hs_lpc32xx_remove,
704 .suspend = serial_hs_lpc32xx_suspend,
705 .resume = serial_hs_lpc32xx_resume,
706 .driver = {
707 .name = MODNAME,
708 .of_match_table = serial_hs_lpc32xx_dt_ids,
709 },
710};
711
712static int __init lpc32xx_hsuart_init(void)
713{
714 int ret;
715
716 ret = uart_register_driver(&lpc32xx_hs_reg);
717 if (ret)
718 return ret;
719
720 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
721 if (ret)
722 uart_unregister_driver(&lpc32xx_hs_reg);
723
724 return ret;
725}
726
727static void __exit lpc32xx_hsuart_exit(void)
728{
729 platform_driver_unregister(&serial_hs_lpc32xx_driver);
730 uart_unregister_driver(&lpc32xx_hs_reg);
731}
732
733module_init(lpc32xx_hsuart_init);
734module_exit(lpc32xx_hsuart_exit);
735
736MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
737MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
738MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
739MODULE_LICENSE("GPL");
1/*
2 * High Speed Serial Ports on NXP LPC32xx SoC
3 *
4 * Authors: Kevin Wells <kevin.wells@nxp.com>
5 * Roland Stigge <stigge@antcom.de>
6 *
7 * Copyright (C) 2010 NXP Semiconductors
8 * Copyright (C) 2012 Roland Stigge
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/module.h>
22#include <linux/ioport.h>
23#include <linux/init.h>
24#include <linux/console.h>
25#include <linux/sysrq.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/serial_core.h>
29#include <linux/serial.h>
30#include <linux/platform_device.h>
31#include <linux/delay.h>
32#include <linux/nmi.h>
33#include <linux/io.h>
34#include <linux/irq.h>
35#include <linux/gpio.h>
36#include <linux/of.h>
37#include <mach/platform.h>
38#include <mach/hardware.h>
39
40/*
41 * High Speed UART register offsets
42 */
43#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
44#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
45#define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
46#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
47#define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
48
49#define LPC32XX_HSU_BREAK_DATA (1 << 10)
50#define LPC32XX_HSU_ERROR_DATA (1 << 9)
51#define LPC32XX_HSU_RX_EMPTY (1 << 8)
52
53#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
54#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
55
56#define LPC32XX_HSU_TX_INT_SET (1 << 6)
57#define LPC32XX_HSU_RX_OE_INT (1 << 5)
58#define LPC32XX_HSU_BRK_INT (1 << 4)
59#define LPC32XX_HSU_FE_INT (1 << 3)
60#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
61#define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
62#define LPC32XX_HSU_TX_INT (1 << 0)
63
64#define LPC32XX_HSU_HRTS_INV (1 << 21)
65#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
66#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
67#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
68#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
69#define LPC32XX_HSU_HRTS_EN (1 << 18)
70#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
71#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
72#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
73#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
74#define LPC32XX_HSU_HCTS_INV (1 << 15)
75#define LPC32XX_HSU_HCTS_EN (1 << 14)
76#define LPC32XX_HSU_OFFSET(n) ((n) << 9)
77#define LPC32XX_HSU_BREAK (1 << 8)
78#define LPC32XX_HSU_ERR_INT_EN (1 << 7)
79#define LPC32XX_HSU_RX_INT_EN (1 << 6)
80#define LPC32XX_HSU_TX_INT_EN (1 << 5)
81#define LPC32XX_HSU_RX_TL1B (0x0 << 2)
82#define LPC32XX_HSU_RX_TL4B (0x1 << 2)
83#define LPC32XX_HSU_RX_TL8B (0x2 << 2)
84#define LPC32XX_HSU_RX_TL16B (0x3 << 2)
85#define LPC32XX_HSU_RX_TL32B (0x4 << 2)
86#define LPC32XX_HSU_RX_TL48B (0x5 << 2)
87#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
88#define LPC32XX_HSU_TX_TL0B (0x0 << 0)
89#define LPC32XX_HSU_TX_TL4B (0x1 << 0)
90#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
91#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
92
93#define MODNAME "lpc32xx_hsuart"
94
95struct lpc32xx_hsuart_port {
96 struct uart_port port;
97};
98
99#define FIFO_READ_LIMIT 128
100#define MAX_PORTS 3
101#define LPC32XX_TTY_NAME "ttyTX"
102static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
103
104#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
105static void wait_for_xmit_empty(struct uart_port *port)
106{
107 unsigned int timeout = 10000;
108
109 do {
110 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
111 port->membase))) == 0)
112 break;
113 if (--timeout == 0)
114 break;
115 udelay(1);
116 } while (1);
117}
118
119static void wait_for_xmit_ready(struct uart_port *port)
120{
121 unsigned int timeout = 10000;
122
123 while (1) {
124 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
125 port->membase))) < 32)
126 break;
127 if (--timeout == 0)
128 break;
129 udelay(1);
130 }
131}
132
133static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
134{
135 wait_for_xmit_ready(port);
136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
137}
138
139static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
140 unsigned int count)
141{
142 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
143 unsigned long flags;
144 int locked = 1;
145
146 touch_nmi_watchdog();
147 local_irq_save(flags);
148 if (up->port.sysrq)
149 locked = 0;
150 else if (oops_in_progress)
151 locked = spin_trylock(&up->port.lock);
152 else
153 spin_lock(&up->port.lock);
154
155 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
156 wait_for_xmit_empty(&up->port);
157
158 if (locked)
159 spin_unlock(&up->port.lock);
160 local_irq_restore(flags);
161}
162
163static int __init lpc32xx_hsuart_console_setup(struct console *co,
164 char *options)
165{
166 struct uart_port *port;
167 int baud = 115200;
168 int bits = 8;
169 int parity = 'n';
170 int flow = 'n';
171
172 if (co->index >= MAX_PORTS)
173 co->index = 0;
174
175 port = &lpc32xx_hs_ports[co->index].port;
176 if (!port->membase)
177 return -ENODEV;
178
179 if (options)
180 uart_parse_options(options, &baud, &parity, &bits, &flow);
181
182 return uart_set_options(port, co, baud, parity, bits, flow);
183}
184
185static struct uart_driver lpc32xx_hsuart_reg;
186static struct console lpc32xx_hsuart_console = {
187 .name = LPC32XX_TTY_NAME,
188 .write = lpc32xx_hsuart_console_write,
189 .device = uart_console_device,
190 .setup = lpc32xx_hsuart_console_setup,
191 .flags = CON_PRINTBUFFER,
192 .index = -1,
193 .data = &lpc32xx_hsuart_reg,
194};
195
196static int __init lpc32xx_hsuart_console_init(void)
197{
198 register_console(&lpc32xx_hsuart_console);
199 return 0;
200}
201console_initcall(lpc32xx_hsuart_console_init);
202
203#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
204#else
205#define LPC32XX_HSUART_CONSOLE NULL
206#endif
207
208static struct uart_driver lpc32xx_hs_reg = {
209 .owner = THIS_MODULE,
210 .driver_name = MODNAME,
211 .dev_name = LPC32XX_TTY_NAME,
212 .nr = MAX_PORTS,
213 .cons = LPC32XX_HSUART_CONSOLE,
214};
215static int uarts_registered;
216
217static unsigned int __serial_get_clock_div(unsigned long uartclk,
218 unsigned long rate)
219{
220 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
221 u32 rate_diff;
222
223 /* Find the closest divider to get the desired clock rate */
224 div = uartclk / rate;
225 goodrate = hsu_rate = (div / 14) - 1;
226 if (hsu_rate != 0)
227 hsu_rate--;
228
229 /* Tweak divider */
230 l_hsu_rate = hsu_rate + 3;
231 rate_diff = 0xFFFFFFFF;
232
233 while (hsu_rate < l_hsu_rate) {
234 comprate = uartclk / ((hsu_rate + 1) * 14);
235 if (abs(comprate - rate) < rate_diff) {
236 goodrate = hsu_rate;
237 rate_diff = abs(comprate - rate);
238 }
239
240 hsu_rate++;
241 }
242 if (hsu_rate > 0xFF)
243 hsu_rate = 0xFF;
244
245 return goodrate;
246}
247
248static void __serial_uart_flush(struct uart_port *port)
249{
250 u32 tmp;
251 int cnt = 0;
252
253 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
254 (cnt++ < FIFO_READ_LIMIT))
255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
256}
257
258static void __serial_lpc32xx_rx(struct uart_port *port)
259{
260 struct tty_port *tport = &port->state->port;
261 unsigned int tmp, flag;
262
263 /* Read data from FIFO and push into terminal */
264 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
265 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
266 flag = TTY_NORMAL;
267 port->icount.rx++;
268
269 if (tmp & LPC32XX_HSU_ERROR_DATA) {
270 /* Framing error */
271 writel(LPC32XX_HSU_FE_INT,
272 LPC32XX_HSUART_IIR(port->membase));
273 port->icount.frame++;
274 flag = TTY_FRAME;
275 tty_insert_flip_char(tport, 0, TTY_FRAME);
276 }
277
278 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
279
280 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
281 }
282
283 spin_unlock(&port->lock);
284 tty_flip_buffer_push(tport);
285 spin_lock(&port->lock);
286}
287
288static void __serial_lpc32xx_tx(struct uart_port *port)
289{
290 struct circ_buf *xmit = &port->state->xmit;
291 unsigned int tmp;
292
293 if (port->x_char) {
294 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
295 port->icount.tx++;
296 port->x_char = 0;
297 return;
298 }
299
300 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
301 goto exit_tx;
302
303 /* Transfer data */
304 while (LPC32XX_HSU_TX_LEV(readl(
305 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
306 writel((u32) xmit->buf[xmit->tail],
307 LPC32XX_HSUART_FIFO(port->membase));
308 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
309 port->icount.tx++;
310 if (uart_circ_empty(xmit))
311 break;
312 }
313
314 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
315 uart_write_wakeup(port);
316
317exit_tx:
318 if (uart_circ_empty(xmit)) {
319 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
320 tmp &= ~LPC32XX_HSU_TX_INT_EN;
321 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
322 }
323}
324
325static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
326{
327 struct uart_port *port = dev_id;
328 struct tty_port *tport = &port->state->port;
329 u32 status;
330
331 spin_lock(&port->lock);
332
333 /* Read UART status and clear latched interrupts */
334 status = readl(LPC32XX_HSUART_IIR(port->membase));
335
336 if (status & LPC32XX_HSU_BRK_INT) {
337 /* Break received */
338 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
339 port->icount.brk++;
340 uart_handle_break(port);
341 }
342
343 /* Framing error */
344 if (status & LPC32XX_HSU_FE_INT)
345 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
346
347 if (status & LPC32XX_HSU_RX_OE_INT) {
348 /* Receive FIFO overrun */
349 writel(LPC32XX_HSU_RX_OE_INT,
350 LPC32XX_HSUART_IIR(port->membase));
351 port->icount.overrun++;
352 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
353 tty_schedule_flip(tport);
354 }
355
356 /* Data received? */
357 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
358 __serial_lpc32xx_rx(port);
359
360 /* Transmit data request? */
361 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
362 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
363 __serial_lpc32xx_tx(port);
364 }
365
366 spin_unlock(&port->lock);
367
368 return IRQ_HANDLED;
369}
370
371/* port->lock is not held. */
372static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
373{
374 unsigned int ret = 0;
375
376 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
377 ret = TIOCSER_TEMT;
378
379 return ret;
380}
381
382/* port->lock held by caller. */
383static void serial_lpc32xx_set_mctrl(struct uart_port *port,
384 unsigned int mctrl)
385{
386 /* No signals are supported on HS UARTs */
387}
388
389/* port->lock is held by caller and interrupts are disabled. */
390static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
391{
392 /* No signals are supported on HS UARTs */
393 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
394}
395
396/* port->lock held by caller. */
397static void serial_lpc32xx_stop_tx(struct uart_port *port)
398{
399 u32 tmp;
400
401 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
402 tmp &= ~LPC32XX_HSU_TX_INT_EN;
403 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
404}
405
406/* port->lock held by caller. */
407static void serial_lpc32xx_start_tx(struct uart_port *port)
408{
409 u32 tmp;
410
411 __serial_lpc32xx_tx(port);
412 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
413 tmp |= LPC32XX_HSU_TX_INT_EN;
414 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
415}
416
417/* port->lock held by caller. */
418static void serial_lpc32xx_stop_rx(struct uart_port *port)
419{
420 u32 tmp;
421
422 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
423 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
424 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
425
426 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
427 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
428}
429
430/* port->lock is not held. */
431static void serial_lpc32xx_break_ctl(struct uart_port *port,
432 int break_state)
433{
434 unsigned long flags;
435 u32 tmp;
436
437 spin_lock_irqsave(&port->lock, flags);
438 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
439 if (break_state != 0)
440 tmp |= LPC32XX_HSU_BREAK;
441 else
442 tmp &= ~LPC32XX_HSU_BREAK;
443 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
444 spin_unlock_irqrestore(&port->lock, flags);
445}
446
447/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
448static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
449{
450 int bit;
451 u32 tmp;
452
453 switch (mapbase) {
454 case LPC32XX_HS_UART1_BASE:
455 bit = 0;
456 break;
457 case LPC32XX_HS_UART2_BASE:
458 bit = 1;
459 break;
460 case LPC32XX_HS_UART7_BASE:
461 bit = 6;
462 break;
463 default:
464 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
465 return;
466 }
467
468 tmp = readl(LPC32XX_UARTCTL_CLOOP);
469 if (state)
470 tmp |= (1 << bit);
471 else
472 tmp &= ~(1 << bit);
473 writel(tmp, LPC32XX_UARTCTL_CLOOP);
474}
475
476/* port->lock is not held. */
477static int serial_lpc32xx_startup(struct uart_port *port)
478{
479 int retval;
480 unsigned long flags;
481 u32 tmp;
482
483 spin_lock_irqsave(&port->lock, flags);
484
485 __serial_uart_flush(port);
486
487 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
488 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
489 LPC32XX_HSUART_IIR(port->membase));
490
491 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
492
493 /*
494 * Set receiver timeout, HSU offset of 20, no break, no interrupts,
495 * and default FIFO trigger levels
496 */
497 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
498 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
499 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
500
501 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
502
503 spin_unlock_irqrestore(&port->lock, flags);
504
505 retval = request_irq(port->irq, serial_lpc32xx_interrupt,
506 0, MODNAME, port);
507 if (!retval)
508 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
509 LPC32XX_HSUART_CTRL(port->membase));
510
511 return retval;
512}
513
514/* port->lock is not held. */
515static void serial_lpc32xx_shutdown(struct uart_port *port)
516{
517 u32 tmp;
518 unsigned long flags;
519
520 spin_lock_irqsave(&port->lock, flags);
521
522 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
523 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
524 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
525
526 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
527
528 spin_unlock_irqrestore(&port->lock, flags);
529
530 free_irq(port->irq, port);
531}
532
533/* port->lock is not held. */
534static void serial_lpc32xx_set_termios(struct uart_port *port,
535 struct ktermios *termios,
536 struct ktermios *old)
537{
538 unsigned long flags;
539 unsigned int baud, quot;
540 u32 tmp;
541
542 /* Always 8-bit, no parity, 1 stop bit */
543 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
544 termios->c_cflag |= CS8;
545
546 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
547
548 baud = uart_get_baud_rate(port, termios, old, 0,
549 port->uartclk / 14);
550
551 quot = __serial_get_clock_div(port->uartclk, baud);
552
553 spin_lock_irqsave(&port->lock, flags);
554
555 /* Ignore characters? */
556 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
557 if ((termios->c_cflag & CREAD) == 0)
558 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
559 else
560 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
561 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
562
563 writel(quot, LPC32XX_HSUART_RATE(port->membase));
564
565 uart_update_timeout(port, termios->c_cflag, baud);
566
567 spin_unlock_irqrestore(&port->lock, flags);
568
569 /* Don't rewrite B0 */
570 if (tty_termios_baud_rate(termios))
571 tty_termios_encode_baud_rate(termios, baud, baud);
572}
573
574static const char *serial_lpc32xx_type(struct uart_port *port)
575{
576 return MODNAME;
577}
578
579static void serial_lpc32xx_release_port(struct uart_port *port)
580{
581 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
582 if (port->flags & UPF_IOREMAP) {
583 iounmap(port->membase);
584 port->membase = NULL;
585 }
586
587 release_mem_region(port->mapbase, SZ_4K);
588 }
589}
590
591static int serial_lpc32xx_request_port(struct uart_port *port)
592{
593 int ret = -ENODEV;
594
595 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
596 ret = 0;
597
598 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
599 ret = -EBUSY;
600 else if (port->flags & UPF_IOREMAP) {
601 port->membase = ioremap(port->mapbase, SZ_4K);
602 if (!port->membase) {
603 release_mem_region(port->mapbase, SZ_4K);
604 ret = -ENOMEM;
605 }
606 }
607 }
608
609 return ret;
610}
611
612static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
613{
614 int ret;
615
616 ret = serial_lpc32xx_request_port(port);
617 if (ret < 0)
618 return;
619 port->type = PORT_UART00;
620 port->fifosize = 64;
621
622 __serial_uart_flush(port);
623
624 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
625 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
626 LPC32XX_HSUART_IIR(port->membase));
627
628 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
629
630 /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
631 and default FIFO trigger levels */
632 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
633 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
634 LPC32XX_HSUART_CTRL(port->membase));
635}
636
637static int serial_lpc32xx_verify_port(struct uart_port *port,
638 struct serial_struct *ser)
639{
640 int ret = 0;
641
642 if (ser->type != PORT_UART00)
643 ret = -EINVAL;
644
645 return ret;
646}
647
648static struct uart_ops serial_lpc32xx_pops = {
649 .tx_empty = serial_lpc32xx_tx_empty,
650 .set_mctrl = serial_lpc32xx_set_mctrl,
651 .get_mctrl = serial_lpc32xx_get_mctrl,
652 .stop_tx = serial_lpc32xx_stop_tx,
653 .start_tx = serial_lpc32xx_start_tx,
654 .stop_rx = serial_lpc32xx_stop_rx,
655 .break_ctl = serial_lpc32xx_break_ctl,
656 .startup = serial_lpc32xx_startup,
657 .shutdown = serial_lpc32xx_shutdown,
658 .set_termios = serial_lpc32xx_set_termios,
659 .type = serial_lpc32xx_type,
660 .release_port = serial_lpc32xx_release_port,
661 .request_port = serial_lpc32xx_request_port,
662 .config_port = serial_lpc32xx_config_port,
663 .verify_port = serial_lpc32xx_verify_port,
664};
665
666/*
667 * Register a set of serial devices attached to a platform device
668 */
669static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
670{
671 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
672 int ret = 0;
673 struct resource *res;
674
675 if (uarts_registered >= MAX_PORTS) {
676 dev_err(&pdev->dev,
677 "Error: Number of possible ports exceeded (%d)!\n",
678 uarts_registered + 1);
679 return -ENXIO;
680 }
681
682 memset(p, 0, sizeof(*p));
683
684 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
685 if (!res) {
686 dev_err(&pdev->dev,
687 "Error getting mem resource for HS UART port %d\n",
688 uarts_registered);
689 return -ENXIO;
690 }
691 p->port.mapbase = res->start;
692 p->port.membase = NULL;
693
694 ret = platform_get_irq(pdev, 0);
695 if (ret < 0) {
696 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
697 uarts_registered);
698 return ret;
699 }
700 p->port.irq = ret;
701
702 p->port.iotype = UPIO_MEM32;
703 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
704 p->port.regshift = 2;
705 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
706 p->port.dev = &pdev->dev;
707 p->port.ops = &serial_lpc32xx_pops;
708 p->port.line = uarts_registered++;
709 spin_lock_init(&p->port.lock);
710
711 /* send port to loopback mode by default */
712 lpc32xx_loopback_set(p->port.mapbase, 1);
713
714 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
715
716 platform_set_drvdata(pdev, p);
717
718 return ret;
719}
720
721/*
722 * Remove serial ports registered against a platform device.
723 */
724static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
725{
726 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
727
728 uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
729
730 return 0;
731}
732
733
734#ifdef CONFIG_PM
735static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
736 pm_message_t state)
737{
738 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
739
740 uart_suspend_port(&lpc32xx_hs_reg, &p->port);
741
742 return 0;
743}
744
745static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
746{
747 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
748
749 uart_resume_port(&lpc32xx_hs_reg, &p->port);
750
751 return 0;
752}
753#else
754#define serial_hs_lpc32xx_suspend NULL
755#define serial_hs_lpc32xx_resume NULL
756#endif
757
758static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
759 { .compatible = "nxp,lpc3220-hsuart" },
760 { /* sentinel */ }
761};
762
763MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
764
765static struct platform_driver serial_hs_lpc32xx_driver = {
766 .probe = serial_hs_lpc32xx_probe,
767 .remove = serial_hs_lpc32xx_remove,
768 .suspend = serial_hs_lpc32xx_suspend,
769 .resume = serial_hs_lpc32xx_resume,
770 .driver = {
771 .name = MODNAME,
772 .of_match_table = serial_hs_lpc32xx_dt_ids,
773 },
774};
775
776static int __init lpc32xx_hsuart_init(void)
777{
778 int ret;
779
780 ret = uart_register_driver(&lpc32xx_hs_reg);
781 if (ret)
782 return ret;
783
784 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
785 if (ret)
786 uart_unregister_driver(&lpc32xx_hs_reg);
787
788 return ret;
789}
790
791static void __exit lpc32xx_hsuart_exit(void)
792{
793 platform_driver_unregister(&serial_hs_lpc32xx_driver);
794 uart_unregister_driver(&lpc32xx_hs_reg);
795}
796
797module_init(lpc32xx_hsuart_init);
798module_exit(lpc32xx_hsuart_exit);
799
800MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
801MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
802MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
803MODULE_LICENSE("GPL");