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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * High Speed Serial Ports on NXP LPC32xx SoC
4 *
5 * Authors: Kevin Wells <kevin.wells@nxp.com>
6 * Roland Stigge <stigge@antcom.de>
7 *
8 * Copyright (C) 2010 NXP Semiconductors
9 * Copyright (C) 2012 Roland Stigge
10 */
11
12#include <linux/module.h>
13#include <linux/ioport.h>
14#include <linux/init.h>
15#include <linux/console.h>
16#include <linux/sysrq.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/nmi.h>
24#include <linux/io.h>
25#include <linux/irq.h>
26#include <linux/of.h>
27#include <linux/sizes.h>
28#include <linux/soc/nxp/lpc32xx-misc.h>
29
30/*
31 * High Speed UART register offsets
32 */
33#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
34#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
35#define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
36#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
37#define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
38
39#define LPC32XX_HSU_BREAK_DATA (1 << 10)
40#define LPC32XX_HSU_ERROR_DATA (1 << 9)
41#define LPC32XX_HSU_RX_EMPTY (1 << 8)
42
43#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
44#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
45
46#define LPC32XX_HSU_TX_INT_SET (1 << 6)
47#define LPC32XX_HSU_RX_OE_INT (1 << 5)
48#define LPC32XX_HSU_BRK_INT (1 << 4)
49#define LPC32XX_HSU_FE_INT (1 << 3)
50#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
51#define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
52#define LPC32XX_HSU_TX_INT (1 << 0)
53
54#define LPC32XX_HSU_HRTS_INV (1 << 21)
55#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
56#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
57#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
58#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
59#define LPC32XX_HSU_HRTS_EN (1 << 18)
60#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
61#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
62#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
63#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
64#define LPC32XX_HSU_HCTS_INV (1 << 15)
65#define LPC32XX_HSU_HCTS_EN (1 << 14)
66#define LPC32XX_HSU_OFFSET(n) ((n) << 9)
67#define LPC32XX_HSU_BREAK (1 << 8)
68#define LPC32XX_HSU_ERR_INT_EN (1 << 7)
69#define LPC32XX_HSU_RX_INT_EN (1 << 6)
70#define LPC32XX_HSU_TX_INT_EN (1 << 5)
71#define LPC32XX_HSU_RX_TL1B (0x0 << 2)
72#define LPC32XX_HSU_RX_TL4B (0x1 << 2)
73#define LPC32XX_HSU_RX_TL8B (0x2 << 2)
74#define LPC32XX_HSU_RX_TL16B (0x3 << 2)
75#define LPC32XX_HSU_RX_TL32B (0x4 << 2)
76#define LPC32XX_HSU_RX_TL48B (0x5 << 2)
77#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
78#define LPC32XX_HSU_TX_TL0B (0x0 << 0)
79#define LPC32XX_HSU_TX_TL4B (0x1 << 0)
80#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
81#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
82
83#define LPC32XX_MAIN_OSC_FREQ 13000000
84
85#define MODNAME "lpc32xx_hsuart"
86
87struct lpc32xx_hsuart_port {
88 struct uart_port port;
89};
90
91#define FIFO_READ_LIMIT 128
92#define MAX_PORTS 3
93#define LPC32XX_TTY_NAME "ttyTX"
94static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
95
96#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
97static void wait_for_xmit_empty(struct uart_port *port)
98{
99 unsigned int timeout = 10000;
100
101 do {
102 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
103 port->membase))) == 0)
104 break;
105 if (--timeout == 0)
106 break;
107 udelay(1);
108 } while (1);
109}
110
111static void wait_for_xmit_ready(struct uart_port *port)
112{
113 unsigned int timeout = 10000;
114
115 while (1) {
116 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
117 port->membase))) < 32)
118 break;
119 if (--timeout == 0)
120 break;
121 udelay(1);
122 }
123}
124
125static void lpc32xx_hsuart_console_putchar(struct uart_port *port, unsigned char ch)
126{
127 wait_for_xmit_ready(port);
128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
129}
130
131static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
132 unsigned int count)
133{
134 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
135 unsigned long flags;
136 int locked = 1;
137
138 touch_nmi_watchdog();
139 local_irq_save(flags);
140 if (up->port.sysrq)
141 locked = 0;
142 else if (oops_in_progress)
143 locked = uart_port_trylock(&up->port);
144 else
145 uart_port_lock(&up->port);
146
147 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
148 wait_for_xmit_empty(&up->port);
149
150 if (locked)
151 uart_port_unlock(&up->port);
152 local_irq_restore(flags);
153}
154
155static int __init lpc32xx_hsuart_console_setup(struct console *co,
156 char *options)
157{
158 struct uart_port *port;
159 int baud = 115200;
160 int bits = 8;
161 int parity = 'n';
162 int flow = 'n';
163
164 if (co->index >= MAX_PORTS)
165 co->index = 0;
166
167 port = &lpc32xx_hs_ports[co->index].port;
168 if (!port->membase)
169 return -ENODEV;
170
171 if (options)
172 uart_parse_options(options, &baud, &parity, &bits, &flow);
173
174 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
175
176 return uart_set_options(port, co, baud, parity, bits, flow);
177}
178
179static struct uart_driver lpc32xx_hsuart_reg;
180static struct console lpc32xx_hsuart_console = {
181 .name = LPC32XX_TTY_NAME,
182 .write = lpc32xx_hsuart_console_write,
183 .device = uart_console_device,
184 .setup = lpc32xx_hsuart_console_setup,
185 .flags = CON_PRINTBUFFER,
186 .index = -1,
187 .data = &lpc32xx_hsuart_reg,
188};
189
190static int __init lpc32xx_hsuart_console_init(void)
191{
192 register_console(&lpc32xx_hsuart_console);
193 return 0;
194}
195console_initcall(lpc32xx_hsuart_console_init);
196
197#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
198#else
199#define LPC32XX_HSUART_CONSOLE NULL
200#endif
201
202static struct uart_driver lpc32xx_hs_reg = {
203 .owner = THIS_MODULE,
204 .driver_name = MODNAME,
205 .dev_name = LPC32XX_TTY_NAME,
206 .nr = MAX_PORTS,
207 .cons = LPC32XX_HSUART_CONSOLE,
208};
209static int uarts_registered;
210
211static unsigned int __serial_get_clock_div(unsigned long uartclk,
212 unsigned long rate)
213{
214 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
215 u32 rate_diff;
216
217 /* Find the closest divider to get the desired clock rate */
218 div = uartclk / rate;
219 goodrate = hsu_rate = (div / 14) - 1;
220 if (hsu_rate != 0)
221 hsu_rate--;
222
223 /* Tweak divider */
224 l_hsu_rate = hsu_rate + 3;
225 rate_diff = 0xFFFFFFFF;
226
227 while (hsu_rate < l_hsu_rate) {
228 comprate = uartclk / ((hsu_rate + 1) * 14);
229 if (abs(comprate - rate) < rate_diff) {
230 goodrate = hsu_rate;
231 rate_diff = abs(comprate - rate);
232 }
233
234 hsu_rate++;
235 }
236 if (hsu_rate > 0xFF)
237 hsu_rate = 0xFF;
238
239 return goodrate;
240}
241
242static void __serial_uart_flush(struct uart_port *port)
243{
244 int cnt = 0;
245
246 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
247 (cnt++ < FIFO_READ_LIMIT))
248 readl(LPC32XX_HSUART_FIFO(port->membase));
249}
250
251static void __serial_lpc32xx_rx(struct uart_port *port)
252{
253 struct tty_port *tport = &port->state->port;
254 unsigned int tmp, flag;
255
256 /* Read data from FIFO and push into terminal */
257 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
258 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
259 flag = TTY_NORMAL;
260 port->icount.rx++;
261
262 if (tmp & LPC32XX_HSU_ERROR_DATA) {
263 /* Framing error */
264 writel(LPC32XX_HSU_FE_INT,
265 LPC32XX_HSUART_IIR(port->membase));
266 port->icount.frame++;
267 flag = TTY_FRAME;
268 tty_insert_flip_char(tport, 0, TTY_FRAME);
269 }
270
271 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
272
273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
274 }
275
276 tty_flip_buffer_push(tport);
277}
278
279static bool serial_lpc32xx_tx_ready(struct uart_port *port)
280{
281 u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase));
282
283 return LPC32XX_HSU_TX_LEV(level) < 64;
284}
285
286static void __serial_lpc32xx_tx(struct uart_port *port)
287{
288 u8 ch;
289
290 uart_port_tx(port, ch,
291 serial_lpc32xx_tx_ready(port),
292 writel(ch, LPC32XX_HSUART_FIFO(port->membase)));
293}
294
295static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
296{
297 struct uart_port *port = dev_id;
298 struct tty_port *tport = &port->state->port;
299 u32 status;
300
301 uart_port_lock(port);
302
303 /* Read UART status and clear latched interrupts */
304 status = readl(LPC32XX_HSUART_IIR(port->membase));
305
306 if (status & LPC32XX_HSU_BRK_INT) {
307 /* Break received */
308 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
309 port->icount.brk++;
310 uart_handle_break(port);
311 }
312
313 /* Framing error */
314 if (status & LPC32XX_HSU_FE_INT)
315 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
316
317 if (status & LPC32XX_HSU_RX_OE_INT) {
318 /* Receive FIFO overrun */
319 writel(LPC32XX_HSU_RX_OE_INT,
320 LPC32XX_HSUART_IIR(port->membase));
321 port->icount.overrun++;
322 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
323 tty_flip_buffer_push(tport);
324 }
325
326 /* Data received? */
327 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
328 __serial_lpc32xx_rx(port);
329
330 /* Transmit data request? */
331 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
332 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
333 __serial_lpc32xx_tx(port);
334 }
335
336 uart_port_unlock(port);
337
338 return IRQ_HANDLED;
339}
340
341/* port->lock is not held. */
342static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
343{
344 unsigned int ret = 0;
345
346 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
347 ret = TIOCSER_TEMT;
348
349 return ret;
350}
351
352/* port->lock held by caller. */
353static void serial_lpc32xx_set_mctrl(struct uart_port *port,
354 unsigned int mctrl)
355{
356 /* No signals are supported on HS UARTs */
357}
358
359/* port->lock is held by caller and interrupts are disabled. */
360static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
361{
362 /* No signals are supported on HS UARTs */
363 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
364}
365
366/* port->lock held by caller. */
367static void serial_lpc32xx_stop_tx(struct uart_port *port)
368{
369 u32 tmp;
370
371 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
372 tmp &= ~LPC32XX_HSU_TX_INT_EN;
373 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
374}
375
376/* port->lock held by caller. */
377static void serial_lpc32xx_start_tx(struct uart_port *port)
378{
379 u32 tmp;
380
381 __serial_lpc32xx_tx(port);
382 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
383 tmp |= LPC32XX_HSU_TX_INT_EN;
384 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
385}
386
387/* port->lock held by caller. */
388static void serial_lpc32xx_stop_rx(struct uart_port *port)
389{
390 u32 tmp;
391
392 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
393 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
394 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
395
396 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
397 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
398}
399
400/* port->lock is not held. */
401static void serial_lpc32xx_break_ctl(struct uart_port *port,
402 int break_state)
403{
404 unsigned long flags;
405 u32 tmp;
406
407 uart_port_lock_irqsave(port, &flags);
408 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
409 if (break_state != 0)
410 tmp |= LPC32XX_HSU_BREAK;
411 else
412 tmp &= ~LPC32XX_HSU_BREAK;
413 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
414 uart_port_unlock_irqrestore(port, flags);
415}
416
417/* port->lock is not held. */
418static int serial_lpc32xx_startup(struct uart_port *port)
419{
420 int retval;
421 unsigned long flags;
422 u32 tmp;
423
424 uart_port_lock_irqsave(port, &flags);
425
426 __serial_uart_flush(port);
427
428 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
429 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
430 LPC32XX_HSUART_IIR(port->membase));
431
432 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
433
434 /*
435 * Set receiver timeout, HSU offset of 20, no break, no interrupts,
436 * and default FIFO trigger levels
437 */
438 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
439 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
440 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
441
442 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
443
444 uart_port_unlock_irqrestore(port, flags);
445
446 retval = request_irq(port->irq, serial_lpc32xx_interrupt,
447 0, MODNAME, port);
448 if (!retval)
449 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
450 LPC32XX_HSUART_CTRL(port->membase));
451
452 return retval;
453}
454
455/* port->lock is not held. */
456static void serial_lpc32xx_shutdown(struct uart_port *port)
457{
458 u32 tmp;
459 unsigned long flags;
460
461 uart_port_lock_irqsave(port, &flags);
462
463 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
464 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
465 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
466
467 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
468
469 uart_port_unlock_irqrestore(port, flags);
470
471 free_irq(port->irq, port);
472}
473
474/* port->lock is not held. */
475static void serial_lpc32xx_set_termios(struct uart_port *port,
476 struct ktermios *termios,
477 const struct ktermios *old)
478{
479 unsigned long flags;
480 unsigned int baud, quot;
481 u32 tmp;
482
483 /* Always 8-bit, no parity, 1 stop bit */
484 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
485 termios->c_cflag |= CS8;
486
487 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
488
489 baud = uart_get_baud_rate(port, termios, old, 0,
490 port->uartclk / 14);
491
492 quot = __serial_get_clock_div(port->uartclk, baud);
493
494 uart_port_lock_irqsave(port, &flags);
495
496 /* Ignore characters? */
497 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
498 if ((termios->c_cflag & CREAD) == 0)
499 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
500 else
501 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
502 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
503
504 writel(quot, LPC32XX_HSUART_RATE(port->membase));
505
506 uart_update_timeout(port, termios->c_cflag, baud);
507
508 uart_port_unlock_irqrestore(port, flags);
509
510 /* Don't rewrite B0 */
511 if (tty_termios_baud_rate(termios))
512 tty_termios_encode_baud_rate(termios, baud, baud);
513}
514
515static const char *serial_lpc32xx_type(struct uart_port *port)
516{
517 return MODNAME;
518}
519
520static void serial_lpc32xx_release_port(struct uart_port *port)
521{
522 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
523 if (port->flags & UPF_IOREMAP) {
524 iounmap(port->membase);
525 port->membase = NULL;
526 }
527
528 release_mem_region(port->mapbase, SZ_4K);
529 }
530}
531
532static int serial_lpc32xx_request_port(struct uart_port *port)
533{
534 int ret = -ENODEV;
535
536 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
537 ret = 0;
538
539 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
540 ret = -EBUSY;
541 else if (port->flags & UPF_IOREMAP) {
542 port->membase = ioremap(port->mapbase, SZ_4K);
543 if (!port->membase) {
544 release_mem_region(port->mapbase, SZ_4K);
545 ret = -ENOMEM;
546 }
547 }
548 }
549
550 return ret;
551}
552
553static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
554{
555 int ret;
556
557 ret = serial_lpc32xx_request_port(port);
558 if (ret < 0)
559 return;
560 port->type = PORT_UART00;
561 port->fifosize = 64;
562
563 __serial_uart_flush(port);
564
565 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
566 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
567 LPC32XX_HSUART_IIR(port->membase));
568
569 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
570
571 /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
572 and default FIFO trigger levels */
573 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
574 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
575 LPC32XX_HSUART_CTRL(port->membase));
576}
577
578static int serial_lpc32xx_verify_port(struct uart_port *port,
579 struct serial_struct *ser)
580{
581 int ret = 0;
582
583 if (ser->type != PORT_UART00)
584 ret = -EINVAL;
585
586 return ret;
587}
588
589static const struct uart_ops serial_lpc32xx_pops = {
590 .tx_empty = serial_lpc32xx_tx_empty,
591 .set_mctrl = serial_lpc32xx_set_mctrl,
592 .get_mctrl = serial_lpc32xx_get_mctrl,
593 .stop_tx = serial_lpc32xx_stop_tx,
594 .start_tx = serial_lpc32xx_start_tx,
595 .stop_rx = serial_lpc32xx_stop_rx,
596 .break_ctl = serial_lpc32xx_break_ctl,
597 .startup = serial_lpc32xx_startup,
598 .shutdown = serial_lpc32xx_shutdown,
599 .set_termios = serial_lpc32xx_set_termios,
600 .type = serial_lpc32xx_type,
601 .release_port = serial_lpc32xx_release_port,
602 .request_port = serial_lpc32xx_request_port,
603 .config_port = serial_lpc32xx_config_port,
604 .verify_port = serial_lpc32xx_verify_port,
605};
606
607/*
608 * Register a set of serial devices attached to a platform device
609 */
610static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
611{
612 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
613 int ret = 0;
614 struct resource *res;
615
616 if (uarts_registered >= MAX_PORTS) {
617 dev_err(&pdev->dev,
618 "Error: Number of possible ports exceeded (%d)!\n",
619 uarts_registered + 1);
620 return -ENXIO;
621 }
622
623 memset(p, 0, sizeof(*p));
624
625 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
626 if (!res) {
627 dev_err(&pdev->dev,
628 "Error getting mem resource for HS UART port %d\n",
629 uarts_registered);
630 return -ENXIO;
631 }
632 p->port.mapbase = res->start;
633 p->port.membase = NULL;
634
635 ret = platform_get_irq(pdev, 0);
636 if (ret < 0)
637 return ret;
638 p->port.irq = ret;
639
640 p->port.iotype = UPIO_MEM32;
641 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
642 p->port.regshift = 2;
643 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
644 p->port.dev = &pdev->dev;
645 p->port.ops = &serial_lpc32xx_pops;
646 p->port.line = uarts_registered++;
647 spin_lock_init(&p->port.lock);
648
649 /* send port to loopback mode by default */
650 lpc32xx_loopback_set(p->port.mapbase, 1);
651
652 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
653
654 platform_set_drvdata(pdev, p);
655
656 return ret;
657}
658
659/*
660 * Remove serial ports registered against a platform device.
661 */
662static void serial_hs_lpc32xx_remove(struct platform_device *pdev)
663{
664 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
665
666 uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
667}
668
669
670#ifdef CONFIG_PM
671static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
672 pm_message_t state)
673{
674 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
675
676 uart_suspend_port(&lpc32xx_hs_reg, &p->port);
677
678 return 0;
679}
680
681static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
682{
683 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
684
685 uart_resume_port(&lpc32xx_hs_reg, &p->port);
686
687 return 0;
688}
689#else
690#define serial_hs_lpc32xx_suspend NULL
691#define serial_hs_lpc32xx_resume NULL
692#endif
693
694static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
695 { .compatible = "nxp,lpc3220-hsuart" },
696 { /* sentinel */ }
697};
698
699MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
700
701static struct platform_driver serial_hs_lpc32xx_driver = {
702 .probe = serial_hs_lpc32xx_probe,
703 .remove_new = serial_hs_lpc32xx_remove,
704 .suspend = serial_hs_lpc32xx_suspend,
705 .resume = serial_hs_lpc32xx_resume,
706 .driver = {
707 .name = MODNAME,
708 .of_match_table = serial_hs_lpc32xx_dt_ids,
709 },
710};
711
712static int __init lpc32xx_hsuart_init(void)
713{
714 int ret;
715
716 ret = uart_register_driver(&lpc32xx_hs_reg);
717 if (ret)
718 return ret;
719
720 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
721 if (ret)
722 uart_unregister_driver(&lpc32xx_hs_reg);
723
724 return ret;
725}
726
727static void __exit lpc32xx_hsuart_exit(void)
728{
729 platform_driver_unregister(&serial_hs_lpc32xx_driver);
730 uart_unregister_driver(&lpc32xx_hs_reg);
731}
732
733module_init(lpc32xx_hsuart_init);
734module_exit(lpc32xx_hsuart_exit);
735
736MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
737MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
738MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
739MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * High Speed Serial Ports on NXP LPC32xx SoC
4 *
5 * Authors: Kevin Wells <kevin.wells@nxp.com>
6 * Roland Stigge <stigge@antcom.de>
7 *
8 * Copyright (C) 2010 NXP Semiconductors
9 * Copyright (C) 2012 Roland Stigge
10 */
11
12#include <linux/module.h>
13#include <linux/ioport.h>
14#include <linux/init.h>
15#include <linux/console.h>
16#include <linux/sysrq.h>
17#include <linux/tty.h>
18#include <linux/tty_flip.h>
19#include <linux/serial_core.h>
20#include <linux/serial.h>
21#include <linux/platform_device.h>
22#include <linux/delay.h>
23#include <linux/nmi.h>
24#include <linux/io.h>
25#include <linux/irq.h>
26#include <linux/gpio.h>
27#include <linux/of.h>
28#include <mach/platform.h>
29#include <mach/hardware.h>
30
31/*
32 * High Speed UART register offsets
33 */
34#define LPC32XX_HSUART_FIFO(x) ((x) + 0x00)
35#define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04)
36#define LPC32XX_HSUART_IIR(x) ((x) + 0x08)
37#define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C)
38#define LPC32XX_HSUART_RATE(x) ((x) + 0x10)
39
40#define LPC32XX_HSU_BREAK_DATA (1 << 10)
41#define LPC32XX_HSU_ERROR_DATA (1 << 9)
42#define LPC32XX_HSU_RX_EMPTY (1 << 8)
43
44#define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF)
45#define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF)
46
47#define LPC32XX_HSU_TX_INT_SET (1 << 6)
48#define LPC32XX_HSU_RX_OE_INT (1 << 5)
49#define LPC32XX_HSU_BRK_INT (1 << 4)
50#define LPC32XX_HSU_FE_INT (1 << 3)
51#define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2)
52#define LPC32XX_HSU_RX_TRIG_INT (1 << 1)
53#define LPC32XX_HSU_TX_INT (1 << 0)
54
55#define LPC32XX_HSU_HRTS_INV (1 << 21)
56#define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19)
57#define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19)
58#define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19)
59#define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19)
60#define LPC32XX_HSU_HRTS_EN (1 << 18)
61#define LPC32XX_HSU_TMO_DISABLED (0x0 << 16)
62#define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16)
63#define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16)
64#define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16)
65#define LPC32XX_HSU_HCTS_INV (1 << 15)
66#define LPC32XX_HSU_HCTS_EN (1 << 14)
67#define LPC32XX_HSU_OFFSET(n) ((n) << 9)
68#define LPC32XX_HSU_BREAK (1 << 8)
69#define LPC32XX_HSU_ERR_INT_EN (1 << 7)
70#define LPC32XX_HSU_RX_INT_EN (1 << 6)
71#define LPC32XX_HSU_TX_INT_EN (1 << 5)
72#define LPC32XX_HSU_RX_TL1B (0x0 << 2)
73#define LPC32XX_HSU_RX_TL4B (0x1 << 2)
74#define LPC32XX_HSU_RX_TL8B (0x2 << 2)
75#define LPC32XX_HSU_RX_TL16B (0x3 << 2)
76#define LPC32XX_HSU_RX_TL32B (0x4 << 2)
77#define LPC32XX_HSU_RX_TL48B (0x5 << 2)
78#define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0)
79#define LPC32XX_HSU_TX_TL0B (0x0 << 0)
80#define LPC32XX_HSU_TX_TL4B (0x1 << 0)
81#define LPC32XX_HSU_TX_TL8B (0x2 << 0)
82#define LPC32XX_HSU_TX_TL16B (0x3 << 0)
83
84#define MODNAME "lpc32xx_hsuart"
85
86struct lpc32xx_hsuart_port {
87 struct uart_port port;
88};
89
90#define FIFO_READ_LIMIT 128
91#define MAX_PORTS 3
92#define LPC32XX_TTY_NAME "ttyTX"
93static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS];
94
95#ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE
96static void wait_for_xmit_empty(struct uart_port *port)
97{
98 unsigned int timeout = 10000;
99
100 do {
101 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
102 port->membase))) == 0)
103 break;
104 if (--timeout == 0)
105 break;
106 udelay(1);
107 } while (1);
108}
109
110static void wait_for_xmit_ready(struct uart_port *port)
111{
112 unsigned int timeout = 10000;
113
114 while (1) {
115 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(
116 port->membase))) < 32)
117 break;
118 if (--timeout == 0)
119 break;
120 udelay(1);
121 }
122}
123
124static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch)
125{
126 wait_for_xmit_ready(port);
127 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase));
128}
129
130static void lpc32xx_hsuart_console_write(struct console *co, const char *s,
131 unsigned int count)
132{
133 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index];
134 unsigned long flags;
135 int locked = 1;
136
137 touch_nmi_watchdog();
138 local_irq_save(flags);
139 if (up->port.sysrq)
140 locked = 0;
141 else if (oops_in_progress)
142 locked = spin_trylock(&up->port.lock);
143 else
144 spin_lock(&up->port.lock);
145
146 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar);
147 wait_for_xmit_empty(&up->port);
148
149 if (locked)
150 spin_unlock(&up->port.lock);
151 local_irq_restore(flags);
152}
153
154static int __init lpc32xx_hsuart_console_setup(struct console *co,
155 char *options)
156{
157 struct uart_port *port;
158 int baud = 115200;
159 int bits = 8;
160 int parity = 'n';
161 int flow = 'n';
162
163 if (co->index >= MAX_PORTS)
164 co->index = 0;
165
166 port = &lpc32xx_hs_ports[co->index].port;
167 if (!port->membase)
168 return -ENODEV;
169
170 if (options)
171 uart_parse_options(options, &baud, &parity, &bits, &flow);
172
173 return uart_set_options(port, co, baud, parity, bits, flow);
174}
175
176static struct uart_driver lpc32xx_hsuart_reg;
177static struct console lpc32xx_hsuart_console = {
178 .name = LPC32XX_TTY_NAME,
179 .write = lpc32xx_hsuart_console_write,
180 .device = uart_console_device,
181 .setup = lpc32xx_hsuart_console_setup,
182 .flags = CON_PRINTBUFFER,
183 .index = -1,
184 .data = &lpc32xx_hsuart_reg,
185};
186
187static int __init lpc32xx_hsuart_console_init(void)
188{
189 register_console(&lpc32xx_hsuart_console);
190 return 0;
191}
192console_initcall(lpc32xx_hsuart_console_init);
193
194#define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console)
195#else
196#define LPC32XX_HSUART_CONSOLE NULL
197#endif
198
199static struct uart_driver lpc32xx_hs_reg = {
200 .owner = THIS_MODULE,
201 .driver_name = MODNAME,
202 .dev_name = LPC32XX_TTY_NAME,
203 .nr = MAX_PORTS,
204 .cons = LPC32XX_HSUART_CONSOLE,
205};
206static int uarts_registered;
207
208static unsigned int __serial_get_clock_div(unsigned long uartclk,
209 unsigned long rate)
210{
211 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate;
212 u32 rate_diff;
213
214 /* Find the closest divider to get the desired clock rate */
215 div = uartclk / rate;
216 goodrate = hsu_rate = (div / 14) - 1;
217 if (hsu_rate != 0)
218 hsu_rate--;
219
220 /* Tweak divider */
221 l_hsu_rate = hsu_rate + 3;
222 rate_diff = 0xFFFFFFFF;
223
224 while (hsu_rate < l_hsu_rate) {
225 comprate = uartclk / ((hsu_rate + 1) * 14);
226 if (abs(comprate - rate) < rate_diff) {
227 goodrate = hsu_rate;
228 rate_diff = abs(comprate - rate);
229 }
230
231 hsu_rate++;
232 }
233 if (hsu_rate > 0xFF)
234 hsu_rate = 0xFF;
235
236 return goodrate;
237}
238
239static void __serial_uart_flush(struct uart_port *port)
240{
241 u32 tmp;
242 int cnt = 0;
243
244 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) &&
245 (cnt++ < FIFO_READ_LIMIT))
246 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
247}
248
249static void __serial_lpc32xx_rx(struct uart_port *port)
250{
251 struct tty_port *tport = &port->state->port;
252 unsigned int tmp, flag;
253
254 /* Read data from FIFO and push into terminal */
255 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
256 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) {
257 flag = TTY_NORMAL;
258 port->icount.rx++;
259
260 if (tmp & LPC32XX_HSU_ERROR_DATA) {
261 /* Framing error */
262 writel(LPC32XX_HSU_FE_INT,
263 LPC32XX_HSUART_IIR(port->membase));
264 port->icount.frame++;
265 flag = TTY_FRAME;
266 tty_insert_flip_char(tport, 0, TTY_FRAME);
267 }
268
269 tty_insert_flip_char(tport, (tmp & 0xFF), flag);
270
271 tmp = readl(LPC32XX_HSUART_FIFO(port->membase));
272 }
273
274 spin_unlock(&port->lock);
275 tty_flip_buffer_push(tport);
276 spin_lock(&port->lock);
277}
278
279static void __serial_lpc32xx_tx(struct uart_port *port)
280{
281 struct circ_buf *xmit = &port->state->xmit;
282 unsigned int tmp;
283
284 if (port->x_char) {
285 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase));
286 port->icount.tx++;
287 port->x_char = 0;
288 return;
289 }
290
291 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
292 goto exit_tx;
293
294 /* Transfer data */
295 while (LPC32XX_HSU_TX_LEV(readl(
296 LPC32XX_HSUART_LEVEL(port->membase))) < 64) {
297 writel((u32) xmit->buf[xmit->tail],
298 LPC32XX_HSUART_FIFO(port->membase));
299 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
300 port->icount.tx++;
301 if (uart_circ_empty(xmit))
302 break;
303 }
304
305 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
306 uart_write_wakeup(port);
307
308exit_tx:
309 if (uart_circ_empty(xmit)) {
310 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
311 tmp &= ~LPC32XX_HSU_TX_INT_EN;
312 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
313 }
314}
315
316static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id)
317{
318 struct uart_port *port = dev_id;
319 struct tty_port *tport = &port->state->port;
320 u32 status;
321
322 spin_lock(&port->lock);
323
324 /* Read UART status and clear latched interrupts */
325 status = readl(LPC32XX_HSUART_IIR(port->membase));
326
327 if (status & LPC32XX_HSU_BRK_INT) {
328 /* Break received */
329 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase));
330 port->icount.brk++;
331 uart_handle_break(port);
332 }
333
334 /* Framing error */
335 if (status & LPC32XX_HSU_FE_INT)
336 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase));
337
338 if (status & LPC32XX_HSU_RX_OE_INT) {
339 /* Receive FIFO overrun */
340 writel(LPC32XX_HSU_RX_OE_INT,
341 LPC32XX_HSUART_IIR(port->membase));
342 port->icount.overrun++;
343 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
344 tty_schedule_flip(tport);
345 }
346
347 /* Data received? */
348 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT))
349 __serial_lpc32xx_rx(port);
350
351 /* Transmit data request? */
352 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) {
353 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase));
354 __serial_lpc32xx_tx(port);
355 }
356
357 spin_unlock(&port->lock);
358
359 return IRQ_HANDLED;
360}
361
362/* port->lock is not held. */
363static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port)
364{
365 unsigned int ret = 0;
366
367 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0)
368 ret = TIOCSER_TEMT;
369
370 return ret;
371}
372
373/* port->lock held by caller. */
374static void serial_lpc32xx_set_mctrl(struct uart_port *port,
375 unsigned int mctrl)
376{
377 /* No signals are supported on HS UARTs */
378}
379
380/* port->lock is held by caller and interrupts are disabled. */
381static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port)
382{
383 /* No signals are supported on HS UARTs */
384 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
385}
386
387/* port->lock held by caller. */
388static void serial_lpc32xx_stop_tx(struct uart_port *port)
389{
390 u32 tmp;
391
392 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
393 tmp &= ~LPC32XX_HSU_TX_INT_EN;
394 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
395}
396
397/* port->lock held by caller. */
398static void serial_lpc32xx_start_tx(struct uart_port *port)
399{
400 u32 tmp;
401
402 __serial_lpc32xx_tx(port);
403 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
404 tmp |= LPC32XX_HSU_TX_INT_EN;
405 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
406}
407
408/* port->lock held by caller. */
409static void serial_lpc32xx_stop_rx(struct uart_port *port)
410{
411 u32 tmp;
412
413 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
414 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
415 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
416
417 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT |
418 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase));
419}
420
421/* port->lock is not held. */
422static void serial_lpc32xx_break_ctl(struct uart_port *port,
423 int break_state)
424{
425 unsigned long flags;
426 u32 tmp;
427
428 spin_lock_irqsave(&port->lock, flags);
429 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
430 if (break_state != 0)
431 tmp |= LPC32XX_HSU_BREAK;
432 else
433 tmp &= ~LPC32XX_HSU_BREAK;
434 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
435 spin_unlock_irqrestore(&port->lock, flags);
436}
437
438/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
439static void lpc32xx_loopback_set(resource_size_t mapbase, int state)
440{
441 int bit;
442 u32 tmp;
443
444 switch (mapbase) {
445 case LPC32XX_HS_UART1_BASE:
446 bit = 0;
447 break;
448 case LPC32XX_HS_UART2_BASE:
449 bit = 1;
450 break;
451 case LPC32XX_HS_UART7_BASE:
452 bit = 6;
453 break;
454 default:
455 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
456 return;
457 }
458
459 tmp = readl(LPC32XX_UARTCTL_CLOOP);
460 if (state)
461 tmp |= (1 << bit);
462 else
463 tmp &= ~(1 << bit);
464 writel(tmp, LPC32XX_UARTCTL_CLOOP);
465}
466
467/* port->lock is not held. */
468static int serial_lpc32xx_startup(struct uart_port *port)
469{
470 int retval;
471 unsigned long flags;
472 u32 tmp;
473
474 spin_lock_irqsave(&port->lock, flags);
475
476 __serial_uart_flush(port);
477
478 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
479 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
480 LPC32XX_HSUART_IIR(port->membase));
481
482 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
483
484 /*
485 * Set receiver timeout, HSU offset of 20, no break, no interrupts,
486 * and default FIFO trigger levels
487 */
488 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
489 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
490 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
491
492 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */
493
494 spin_unlock_irqrestore(&port->lock, flags);
495
496 retval = request_irq(port->irq, serial_lpc32xx_interrupt,
497 0, MODNAME, port);
498 if (!retval)
499 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN),
500 LPC32XX_HSUART_CTRL(port->membase));
501
502 return retval;
503}
504
505/* port->lock is not held. */
506static void serial_lpc32xx_shutdown(struct uart_port *port)
507{
508 u32 tmp;
509 unsigned long flags;
510
511 spin_lock_irqsave(&port->lock, flags);
512
513 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
514 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B;
515 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
516
517 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */
518
519 spin_unlock_irqrestore(&port->lock, flags);
520
521 free_irq(port->irq, port);
522}
523
524/* port->lock is not held. */
525static void serial_lpc32xx_set_termios(struct uart_port *port,
526 struct ktermios *termios,
527 struct ktermios *old)
528{
529 unsigned long flags;
530 unsigned int baud, quot;
531 u32 tmp;
532
533 /* Always 8-bit, no parity, 1 stop bit */
534 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
535 termios->c_cflag |= CS8;
536
537 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS);
538
539 baud = uart_get_baud_rate(port, termios, old, 0,
540 port->uartclk / 14);
541
542 quot = __serial_get_clock_div(port->uartclk, baud);
543
544 spin_lock_irqsave(&port->lock, flags);
545
546 /* Ignore characters? */
547 tmp = readl(LPC32XX_HSUART_CTRL(port->membase));
548 if ((termios->c_cflag & CREAD) == 0)
549 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN);
550 else
551 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN;
552 writel(tmp, LPC32XX_HSUART_CTRL(port->membase));
553
554 writel(quot, LPC32XX_HSUART_RATE(port->membase));
555
556 uart_update_timeout(port, termios->c_cflag, baud);
557
558 spin_unlock_irqrestore(&port->lock, flags);
559
560 /* Don't rewrite B0 */
561 if (tty_termios_baud_rate(termios))
562 tty_termios_encode_baud_rate(termios, baud, baud);
563}
564
565static const char *serial_lpc32xx_type(struct uart_port *port)
566{
567 return MODNAME;
568}
569
570static void serial_lpc32xx_release_port(struct uart_port *port)
571{
572 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
573 if (port->flags & UPF_IOREMAP) {
574 iounmap(port->membase);
575 port->membase = NULL;
576 }
577
578 release_mem_region(port->mapbase, SZ_4K);
579 }
580}
581
582static int serial_lpc32xx_request_port(struct uart_port *port)
583{
584 int ret = -ENODEV;
585
586 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) {
587 ret = 0;
588
589 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME))
590 ret = -EBUSY;
591 else if (port->flags & UPF_IOREMAP) {
592 port->membase = ioremap(port->mapbase, SZ_4K);
593 if (!port->membase) {
594 release_mem_region(port->mapbase, SZ_4K);
595 ret = -ENOMEM;
596 }
597 }
598 }
599
600 return ret;
601}
602
603static void serial_lpc32xx_config_port(struct uart_port *port, int uflags)
604{
605 int ret;
606
607 ret = serial_lpc32xx_request_port(port);
608 if (ret < 0)
609 return;
610 port->type = PORT_UART00;
611 port->fifosize = 64;
612
613 __serial_uart_flush(port);
614
615 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT |
616 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT),
617 LPC32XX_HSUART_IIR(port->membase));
618
619 writel(0xFF, LPC32XX_HSUART_RATE(port->membase));
620
621 /* Set receiver timeout, HSU offset of 20, no break, no interrupts,
622 and default FIFO trigger levels */
623 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B |
624 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B,
625 LPC32XX_HSUART_CTRL(port->membase));
626}
627
628static int serial_lpc32xx_verify_port(struct uart_port *port,
629 struct serial_struct *ser)
630{
631 int ret = 0;
632
633 if (ser->type != PORT_UART00)
634 ret = -EINVAL;
635
636 return ret;
637}
638
639static const struct uart_ops serial_lpc32xx_pops = {
640 .tx_empty = serial_lpc32xx_tx_empty,
641 .set_mctrl = serial_lpc32xx_set_mctrl,
642 .get_mctrl = serial_lpc32xx_get_mctrl,
643 .stop_tx = serial_lpc32xx_stop_tx,
644 .start_tx = serial_lpc32xx_start_tx,
645 .stop_rx = serial_lpc32xx_stop_rx,
646 .break_ctl = serial_lpc32xx_break_ctl,
647 .startup = serial_lpc32xx_startup,
648 .shutdown = serial_lpc32xx_shutdown,
649 .set_termios = serial_lpc32xx_set_termios,
650 .type = serial_lpc32xx_type,
651 .release_port = serial_lpc32xx_release_port,
652 .request_port = serial_lpc32xx_request_port,
653 .config_port = serial_lpc32xx_config_port,
654 .verify_port = serial_lpc32xx_verify_port,
655};
656
657/*
658 * Register a set of serial devices attached to a platform device
659 */
660static int serial_hs_lpc32xx_probe(struct platform_device *pdev)
661{
662 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered];
663 int ret = 0;
664 struct resource *res;
665
666 if (uarts_registered >= MAX_PORTS) {
667 dev_err(&pdev->dev,
668 "Error: Number of possible ports exceeded (%d)!\n",
669 uarts_registered + 1);
670 return -ENXIO;
671 }
672
673 memset(p, 0, sizeof(*p));
674
675 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
676 if (!res) {
677 dev_err(&pdev->dev,
678 "Error getting mem resource for HS UART port %d\n",
679 uarts_registered);
680 return -ENXIO;
681 }
682 p->port.mapbase = res->start;
683 p->port.membase = NULL;
684
685 ret = platform_get_irq(pdev, 0);
686 if (ret < 0) {
687 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n",
688 uarts_registered);
689 return ret;
690 }
691 p->port.irq = ret;
692
693 p->port.iotype = UPIO_MEM32;
694 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ;
695 p->port.regshift = 2;
696 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP;
697 p->port.dev = &pdev->dev;
698 p->port.ops = &serial_lpc32xx_pops;
699 p->port.line = uarts_registered++;
700 spin_lock_init(&p->port.lock);
701
702 /* send port to loopback mode by default */
703 lpc32xx_loopback_set(p->port.mapbase, 1);
704
705 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port);
706
707 platform_set_drvdata(pdev, p);
708
709 return ret;
710}
711
712/*
713 * Remove serial ports registered against a platform device.
714 */
715static int serial_hs_lpc32xx_remove(struct platform_device *pdev)
716{
717 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
718
719 uart_remove_one_port(&lpc32xx_hs_reg, &p->port);
720
721 return 0;
722}
723
724
725#ifdef CONFIG_PM
726static int serial_hs_lpc32xx_suspend(struct platform_device *pdev,
727 pm_message_t state)
728{
729 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
730
731 uart_suspend_port(&lpc32xx_hs_reg, &p->port);
732
733 return 0;
734}
735
736static int serial_hs_lpc32xx_resume(struct platform_device *pdev)
737{
738 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev);
739
740 uart_resume_port(&lpc32xx_hs_reg, &p->port);
741
742 return 0;
743}
744#else
745#define serial_hs_lpc32xx_suspend NULL
746#define serial_hs_lpc32xx_resume NULL
747#endif
748
749static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = {
750 { .compatible = "nxp,lpc3220-hsuart" },
751 { /* sentinel */ }
752};
753
754MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids);
755
756static struct platform_driver serial_hs_lpc32xx_driver = {
757 .probe = serial_hs_lpc32xx_probe,
758 .remove = serial_hs_lpc32xx_remove,
759 .suspend = serial_hs_lpc32xx_suspend,
760 .resume = serial_hs_lpc32xx_resume,
761 .driver = {
762 .name = MODNAME,
763 .of_match_table = serial_hs_lpc32xx_dt_ids,
764 },
765};
766
767static int __init lpc32xx_hsuart_init(void)
768{
769 int ret;
770
771 ret = uart_register_driver(&lpc32xx_hs_reg);
772 if (ret)
773 return ret;
774
775 ret = platform_driver_register(&serial_hs_lpc32xx_driver);
776 if (ret)
777 uart_unregister_driver(&lpc32xx_hs_reg);
778
779 return ret;
780}
781
782static void __exit lpc32xx_hsuart_exit(void)
783{
784 platform_driver_unregister(&serial_hs_lpc32xx_driver);
785 uart_unregister_driver(&lpc32xx_hs_reg);
786}
787
788module_init(lpc32xx_hsuart_init);
789module_exit(lpc32xx_hsuart_exit);
790
791MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
792MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
793MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver");
794MODULE_LICENSE("GPL");