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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * SPI driver for NVIDIA's Tegra114 SPI Controller.
4 *
5 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
6 */
7
8#include <linux/clk.h>
9#include <linux/completion.h>
10#include <linux/delay.h>
11#include <linux/dmaengine.h>
12#include <linux/dma-mapping.h>
13#include <linux/dmapool.h>
14#include <linux/err.h>
15#include <linux/interrupt.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/kthread.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/of.h>
23#include <linux/reset.h>
24#include <linux/spi/spi.h>
25
26#define SPI_COMMAND1 0x000
27#define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
28#define SPI_PACKED (1 << 5)
29#define SPI_TX_EN (1 << 11)
30#define SPI_RX_EN (1 << 12)
31#define SPI_BOTH_EN_BYTE (1 << 13)
32#define SPI_BOTH_EN_BIT (1 << 14)
33#define SPI_LSBYTE_FE (1 << 15)
34#define SPI_LSBIT_FE (1 << 16)
35#define SPI_BIDIROE (1 << 17)
36#define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
37#define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
38#define SPI_IDLE_SDA_PULL_LOW (2 << 18)
39#define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
40#define SPI_IDLE_SDA_MASK (3 << 18)
41#define SPI_CS_SW_VAL (1 << 20)
42#define SPI_CS_SW_HW (1 << 21)
43/* SPI_CS_POL_INACTIVE bits are default high */
44 /* n from 0 to 3 */
45#define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
46#define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
47
48#define SPI_CS_SEL_0 (0 << 26)
49#define SPI_CS_SEL_1 (1 << 26)
50#define SPI_CS_SEL_2 (2 << 26)
51#define SPI_CS_SEL_3 (3 << 26)
52#define SPI_CS_SEL_MASK (3 << 26)
53#define SPI_CS_SEL(x) (((x) & 0x3) << 26)
54#define SPI_CONTROL_MODE_0 (0 << 28)
55#define SPI_CONTROL_MODE_1 (1 << 28)
56#define SPI_CONTROL_MODE_2 (2 << 28)
57#define SPI_CONTROL_MODE_3 (3 << 28)
58#define SPI_CONTROL_MODE_MASK (3 << 28)
59#define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
60#define SPI_M_S (1 << 30)
61#define SPI_PIO (1 << 31)
62
63#define SPI_COMMAND2 0x004
64#define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
65#define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
66
67#define SPI_CS_TIMING1 0x008
68#define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
69#define SPI_CS_SETUP_HOLD(reg, cs, val) \
70 ((((val) & 0xFFu) << ((cs) * 8)) | \
71 ((reg) & ~(0xFFu << ((cs) * 8))))
72
73#define SPI_CS_TIMING2 0x00C
74#define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
75#define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
76#define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
77#define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
78#define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
79#define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
80#define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
81#define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
82#define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
83 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
84 ((reg) & ~(1 << ((cs) * 8 + 5))))
85#define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
86 (reg = (((val) & 0x1F) << ((cs) * 8)) | \
87 ((reg) & ~(0x1F << ((cs) * 8))))
88#define MAX_SETUP_HOLD_CYCLES 16
89#define MAX_INACTIVE_CYCLES 32
90
91#define SPI_TRANS_STATUS 0x010
92#define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
93#define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
94#define SPI_RDY (1 << 30)
95
96#define SPI_FIFO_STATUS 0x014
97#define SPI_RX_FIFO_EMPTY (1 << 0)
98#define SPI_RX_FIFO_FULL (1 << 1)
99#define SPI_TX_FIFO_EMPTY (1 << 2)
100#define SPI_TX_FIFO_FULL (1 << 3)
101#define SPI_RX_FIFO_UNF (1 << 4)
102#define SPI_RX_FIFO_OVF (1 << 5)
103#define SPI_TX_FIFO_UNF (1 << 6)
104#define SPI_TX_FIFO_OVF (1 << 7)
105#define SPI_ERR (1 << 8)
106#define SPI_TX_FIFO_FLUSH (1 << 14)
107#define SPI_RX_FIFO_FLUSH (1 << 15)
108#define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
109#define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
110#define SPI_FRAME_END (1 << 30)
111#define SPI_CS_INACTIVE (1 << 31)
112
113#define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
114 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
115#define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
116
117#define SPI_TX_DATA 0x018
118#define SPI_RX_DATA 0x01C
119
120#define SPI_DMA_CTL 0x020
121#define SPI_TX_TRIG_1 (0 << 15)
122#define SPI_TX_TRIG_4 (1 << 15)
123#define SPI_TX_TRIG_8 (2 << 15)
124#define SPI_TX_TRIG_16 (3 << 15)
125#define SPI_TX_TRIG_MASK (3 << 15)
126#define SPI_RX_TRIG_1 (0 << 19)
127#define SPI_RX_TRIG_4 (1 << 19)
128#define SPI_RX_TRIG_8 (2 << 19)
129#define SPI_RX_TRIG_16 (3 << 19)
130#define SPI_RX_TRIG_MASK (3 << 19)
131#define SPI_IE_TX (1 << 28)
132#define SPI_IE_RX (1 << 29)
133#define SPI_CONT (1 << 30)
134#define SPI_DMA (1 << 31)
135#define SPI_DMA_EN SPI_DMA
136
137#define SPI_DMA_BLK 0x024
138#define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
139
140#define SPI_TX_FIFO 0x108
141#define SPI_RX_FIFO 0x188
142#define SPI_INTR_MASK 0x18c
143#define SPI_INTR_ALL_MASK (0x1fUL << 25)
144#define MAX_CHIP_SELECT 4
145#define SPI_FIFO_DEPTH 64
146#define DATA_DIR_TX (1 << 0)
147#define DATA_DIR_RX (1 << 1)
148
149#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
150#define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
151#define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
152#define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
153#define MAX_HOLD_CYCLES 16
154#define SPI_DEFAULT_SPEED 25000000
155
156struct tegra_spi_soc_data {
157 bool has_intr_mask_reg;
158};
159
160struct tegra_spi_client_data {
161 int tx_clk_tap_delay;
162 int rx_clk_tap_delay;
163};
164
165struct tegra_spi_data {
166 struct device *dev;
167 struct spi_controller *host;
168 spinlock_t lock;
169
170 struct clk *clk;
171 struct reset_control *rst;
172 void __iomem *base;
173 phys_addr_t phys;
174 unsigned irq;
175 u32 cur_speed;
176
177 struct spi_device *cur_spi;
178 struct spi_device *cs_control;
179 unsigned cur_pos;
180 unsigned words_per_32bit;
181 unsigned bytes_per_word;
182 unsigned curr_dma_words;
183 unsigned cur_direction;
184
185 unsigned cur_rx_pos;
186 unsigned cur_tx_pos;
187
188 unsigned dma_buf_size;
189 unsigned max_buf_size;
190 bool is_curr_dma_xfer;
191 bool use_hw_based_cs;
192
193 struct completion rx_dma_complete;
194 struct completion tx_dma_complete;
195
196 u32 tx_status;
197 u32 rx_status;
198 u32 status_reg;
199 bool is_packed;
200
201 u32 command1_reg;
202 u32 dma_control_reg;
203 u32 def_command1_reg;
204 u32 def_command2_reg;
205 u32 spi_cs_timing1;
206 u32 spi_cs_timing2;
207 u8 last_used_cs;
208
209 struct completion xfer_completion;
210 struct spi_transfer *curr_xfer;
211 struct dma_chan *rx_dma_chan;
212 u32 *rx_dma_buf;
213 dma_addr_t rx_dma_phys;
214 struct dma_async_tx_descriptor *rx_dma_desc;
215
216 struct dma_chan *tx_dma_chan;
217 u32 *tx_dma_buf;
218 dma_addr_t tx_dma_phys;
219 struct dma_async_tx_descriptor *tx_dma_desc;
220 const struct tegra_spi_soc_data *soc_data;
221};
222
223static int tegra_spi_runtime_suspend(struct device *dev);
224static int tegra_spi_runtime_resume(struct device *dev);
225
226static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
227 unsigned long reg)
228{
229 return readl(tspi->base + reg);
230}
231
232static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
233 u32 val, unsigned long reg)
234{
235 writel(val, tspi->base + reg);
236
237 /* Read back register to make sure that register writes completed */
238 if (reg != SPI_TX_FIFO)
239 readl(tspi->base + SPI_COMMAND1);
240}
241
242static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
243{
244 u32 val;
245
246 /* Write 1 to clear status register */
247 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
248 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
249
250 /* Clear fifo status error if any */
251 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
252 if (val & SPI_ERR)
253 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
254 SPI_FIFO_STATUS);
255}
256
257static unsigned tegra_spi_calculate_curr_xfer_param(
258 struct spi_device *spi, struct tegra_spi_data *tspi,
259 struct spi_transfer *t)
260{
261 unsigned remain_len = t->len - tspi->cur_pos;
262 unsigned max_word;
263 unsigned bits_per_word = t->bits_per_word;
264 unsigned max_len;
265 unsigned total_fifo_words;
266
267 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
268
269 if ((bits_per_word == 8 || bits_per_word == 16 ||
270 bits_per_word == 32) && t->len > 3) {
271 tspi->is_packed = true;
272 tspi->words_per_32bit = 32/bits_per_word;
273 } else {
274 tspi->is_packed = false;
275 tspi->words_per_32bit = 1;
276 }
277
278 if (tspi->is_packed) {
279 max_len = min(remain_len, tspi->max_buf_size);
280 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
281 total_fifo_words = (max_len + 3) / 4;
282 } else {
283 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
284 max_word = min(max_word, tspi->max_buf_size/4);
285 tspi->curr_dma_words = max_word;
286 total_fifo_words = max_word;
287 }
288 return total_fifo_words;
289}
290
291static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
292 struct tegra_spi_data *tspi, struct spi_transfer *t)
293{
294 unsigned nbytes;
295 unsigned tx_empty_count;
296 u32 fifo_status;
297 unsigned max_n_32bit;
298 unsigned i, count;
299 unsigned int written_words;
300 unsigned fifo_words_left;
301 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
302
303 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
304 tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
305
306 if (tspi->is_packed) {
307 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
308 written_words = min(fifo_words_left, tspi->curr_dma_words);
309 nbytes = written_words * tspi->bytes_per_word;
310 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
311 for (count = 0; count < max_n_32bit; count++) {
312 u32 x = 0;
313
314 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
315 x |= (u32)(*tx_buf++) << (i * 8);
316 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
317 }
318
319 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
320 } else {
321 unsigned int write_bytes;
322 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
323 written_words = max_n_32bit;
324 nbytes = written_words * tspi->bytes_per_word;
325 if (nbytes > t->len - tspi->cur_pos)
326 nbytes = t->len - tspi->cur_pos;
327 write_bytes = nbytes;
328 for (count = 0; count < max_n_32bit; count++) {
329 u32 x = 0;
330
331 for (i = 0; nbytes && (i < tspi->bytes_per_word);
332 i++, nbytes--)
333 x |= (u32)(*tx_buf++) << (i * 8);
334 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
335 }
336
337 tspi->cur_tx_pos += write_bytes;
338 }
339
340 return written_words;
341}
342
343static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
344 struct tegra_spi_data *tspi, struct spi_transfer *t)
345{
346 unsigned rx_full_count;
347 u32 fifo_status;
348 unsigned i, count;
349 unsigned int read_words = 0;
350 unsigned len;
351 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
352
353 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
354 rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
355 if (tspi->is_packed) {
356 len = tspi->curr_dma_words * tspi->bytes_per_word;
357 for (count = 0; count < rx_full_count; count++) {
358 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
359
360 for (i = 0; len && (i < 4); i++, len--)
361 *rx_buf++ = (x >> i*8) & 0xFF;
362 }
363 read_words += tspi->curr_dma_words;
364 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
365 } else {
366 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
367 u8 bytes_per_word = tspi->bytes_per_word;
368 unsigned int read_bytes;
369
370 len = rx_full_count * bytes_per_word;
371 if (len > t->len - tspi->cur_pos)
372 len = t->len - tspi->cur_pos;
373 read_bytes = len;
374 for (count = 0; count < rx_full_count; count++) {
375 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
376
377 for (i = 0; len && (i < bytes_per_word); i++, len--)
378 *rx_buf++ = (x >> (i*8)) & 0xFF;
379 }
380 read_words += rx_full_count;
381 tspi->cur_rx_pos += read_bytes;
382 }
383
384 return read_words;
385}
386
387static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
388 struct tegra_spi_data *tspi, struct spi_transfer *t)
389{
390 /* Make the dma buffer to read by cpu */
391 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
392 tspi->dma_buf_size, DMA_TO_DEVICE);
393
394 if (tspi->is_packed) {
395 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
396
397 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
398 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
399 } else {
400 unsigned int i;
401 unsigned int count;
402 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
403 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
404 unsigned int write_bytes;
405
406 if (consume > t->len - tspi->cur_pos)
407 consume = t->len - tspi->cur_pos;
408 write_bytes = consume;
409 for (count = 0; count < tspi->curr_dma_words; count++) {
410 u32 x = 0;
411
412 for (i = 0; consume && (i < tspi->bytes_per_word);
413 i++, consume--)
414 x |= (u32)(*tx_buf++) << (i * 8);
415 tspi->tx_dma_buf[count] = x;
416 }
417
418 tspi->cur_tx_pos += write_bytes;
419 }
420
421 /* Make the dma buffer to read by dma */
422 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
423 tspi->dma_buf_size, DMA_TO_DEVICE);
424}
425
426static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
427 struct tegra_spi_data *tspi, struct spi_transfer *t)
428{
429 /* Make the dma buffer to read by cpu */
430 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
431 tspi->dma_buf_size, DMA_FROM_DEVICE);
432
433 if (tspi->is_packed) {
434 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
435
436 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
437 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
438 } else {
439 unsigned int i;
440 unsigned int count;
441 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
442 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
443 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
444 unsigned int read_bytes;
445
446 if (consume > t->len - tspi->cur_pos)
447 consume = t->len - tspi->cur_pos;
448 read_bytes = consume;
449 for (count = 0; count < tspi->curr_dma_words; count++) {
450 u32 x = tspi->rx_dma_buf[count] & rx_mask;
451
452 for (i = 0; consume && (i < tspi->bytes_per_word);
453 i++, consume--)
454 *rx_buf++ = (x >> (i*8)) & 0xFF;
455 }
456
457 tspi->cur_rx_pos += read_bytes;
458 }
459
460 /* Make the dma buffer to read by dma */
461 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
462 tspi->dma_buf_size, DMA_FROM_DEVICE);
463}
464
465static void tegra_spi_dma_complete(void *args)
466{
467 struct completion *dma_complete = args;
468
469 complete(dma_complete);
470}
471
472static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
473{
474 reinit_completion(&tspi->tx_dma_complete);
475 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
476 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
477 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
478 if (!tspi->tx_dma_desc) {
479 dev_err(tspi->dev, "Not able to get desc for Tx\n");
480 return -EIO;
481 }
482
483 tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
484 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
485
486 dmaengine_submit(tspi->tx_dma_desc);
487 dma_async_issue_pending(tspi->tx_dma_chan);
488 return 0;
489}
490
491static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
492{
493 reinit_completion(&tspi->rx_dma_complete);
494 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
495 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
496 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
497 if (!tspi->rx_dma_desc) {
498 dev_err(tspi->dev, "Not able to get desc for Rx\n");
499 return -EIO;
500 }
501
502 tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
503 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
504
505 dmaengine_submit(tspi->rx_dma_desc);
506 dma_async_issue_pending(tspi->rx_dma_chan);
507 return 0;
508}
509
510static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
511{
512 unsigned long timeout = jiffies + HZ;
513 u32 status;
514
515 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
516 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
517 status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
518 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
519 while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
520 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
521 if (time_after(jiffies, timeout)) {
522 dev_err(tspi->dev,
523 "timeout waiting for fifo flush\n");
524 return -EIO;
525 }
526
527 udelay(1);
528 }
529 }
530
531 return 0;
532}
533
534static int tegra_spi_start_dma_based_transfer(
535 struct tegra_spi_data *tspi, struct spi_transfer *t)
536{
537 u32 val;
538 unsigned int len;
539 int ret = 0;
540 u8 dma_burst;
541 struct dma_slave_config dma_sconfig = {0};
542
543 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
544 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
545
546 if (tspi->is_packed)
547 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
548 4) * 4;
549 else
550 len = tspi->curr_dma_words * 4;
551
552 /* Set attention level based on length of transfer */
553 if (len & 0xF) {
554 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
555 dma_burst = 1;
556 } else if (((len) >> 4) & 0x1) {
557 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
558 dma_burst = 4;
559 } else {
560 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
561 dma_burst = 8;
562 }
563
564 if (!tspi->soc_data->has_intr_mask_reg) {
565 if (tspi->cur_direction & DATA_DIR_TX)
566 val |= SPI_IE_TX;
567
568 if (tspi->cur_direction & DATA_DIR_RX)
569 val |= SPI_IE_RX;
570 }
571
572 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
573 tspi->dma_control_reg = val;
574
575 dma_sconfig.device_fc = true;
576 if (tspi->cur_direction & DATA_DIR_TX) {
577 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
578 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
579 dma_sconfig.dst_maxburst = dma_burst;
580 ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig);
581 if (ret < 0) {
582 dev_err(tspi->dev,
583 "DMA slave config failed: %d\n", ret);
584 return ret;
585 }
586
587 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
588 ret = tegra_spi_start_tx_dma(tspi, len);
589 if (ret < 0) {
590 dev_err(tspi->dev,
591 "Starting tx dma failed, err %d\n", ret);
592 return ret;
593 }
594 }
595
596 if (tspi->cur_direction & DATA_DIR_RX) {
597 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
598 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
599 dma_sconfig.src_maxburst = dma_burst;
600 ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig);
601 if (ret < 0) {
602 dev_err(tspi->dev,
603 "DMA slave config failed: %d\n", ret);
604 return ret;
605 }
606
607 /* Make the dma buffer to read by dma */
608 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
609 tspi->dma_buf_size, DMA_FROM_DEVICE);
610
611 ret = tegra_spi_start_rx_dma(tspi, len);
612 if (ret < 0) {
613 dev_err(tspi->dev,
614 "Starting rx dma failed, err %d\n", ret);
615 if (tspi->cur_direction & DATA_DIR_TX)
616 dmaengine_terminate_all(tspi->tx_dma_chan);
617 return ret;
618 }
619 }
620 tspi->is_curr_dma_xfer = true;
621 tspi->dma_control_reg = val;
622
623 val |= SPI_DMA_EN;
624 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
625 return ret;
626}
627
628static int tegra_spi_start_cpu_based_transfer(
629 struct tegra_spi_data *tspi, struct spi_transfer *t)
630{
631 u32 val;
632 unsigned cur_words;
633
634 if (tspi->cur_direction & DATA_DIR_TX)
635 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
636 else
637 cur_words = tspi->curr_dma_words;
638
639 val = SPI_DMA_BLK_SET(cur_words - 1);
640 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
641
642 val = 0;
643 if (tspi->cur_direction & DATA_DIR_TX)
644 val |= SPI_IE_TX;
645
646 if (tspi->cur_direction & DATA_DIR_RX)
647 val |= SPI_IE_RX;
648
649 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
650 tspi->dma_control_reg = val;
651
652 tspi->is_curr_dma_xfer = false;
653
654 val = tspi->command1_reg;
655 val |= SPI_PIO;
656 tegra_spi_writel(tspi, val, SPI_COMMAND1);
657 return 0;
658}
659
660static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
661 bool dma_to_memory)
662{
663 struct dma_chan *dma_chan;
664 u32 *dma_buf;
665 dma_addr_t dma_phys;
666
667 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx");
668 if (IS_ERR(dma_chan))
669 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan),
670 "Dma channel is not available\n");
671
672 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
673 &dma_phys, GFP_KERNEL);
674 if (!dma_buf) {
675 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
676 dma_release_channel(dma_chan);
677 return -ENOMEM;
678 }
679
680 if (dma_to_memory) {
681 tspi->rx_dma_chan = dma_chan;
682 tspi->rx_dma_buf = dma_buf;
683 tspi->rx_dma_phys = dma_phys;
684 } else {
685 tspi->tx_dma_chan = dma_chan;
686 tspi->tx_dma_buf = dma_buf;
687 tspi->tx_dma_phys = dma_phys;
688 }
689 return 0;
690}
691
692static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
693 bool dma_to_memory)
694{
695 u32 *dma_buf;
696 dma_addr_t dma_phys;
697 struct dma_chan *dma_chan;
698
699 if (dma_to_memory) {
700 dma_buf = tspi->rx_dma_buf;
701 dma_chan = tspi->rx_dma_chan;
702 dma_phys = tspi->rx_dma_phys;
703 tspi->rx_dma_chan = NULL;
704 tspi->rx_dma_buf = NULL;
705 } else {
706 dma_buf = tspi->tx_dma_buf;
707 dma_chan = tspi->tx_dma_chan;
708 dma_phys = tspi->tx_dma_phys;
709 tspi->tx_dma_buf = NULL;
710 tspi->tx_dma_chan = NULL;
711 }
712 if (!dma_chan)
713 return;
714
715 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
716 dma_release_channel(dma_chan);
717}
718
719static int tegra_spi_set_hw_cs_timing(struct spi_device *spi)
720{
721 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
722 struct spi_delay *setup = &spi->cs_setup;
723 struct spi_delay *hold = &spi->cs_hold;
724 struct spi_delay *inactive = &spi->cs_inactive;
725 u8 setup_dly, hold_dly;
726 u32 setup_hold;
727 u32 spi_cs_timing;
728 u32 inactive_cycles;
729 u8 cs_state;
730
731 if (setup->unit != SPI_DELAY_UNIT_SCK ||
732 hold->unit != SPI_DELAY_UNIT_SCK ||
733 inactive->unit != SPI_DELAY_UNIT_SCK) {
734 dev_err(&spi->dev,
735 "Invalid delay unit %d, should be SPI_DELAY_UNIT_SCK\n",
736 SPI_DELAY_UNIT_SCK);
737 return -EINVAL;
738 }
739
740 setup_dly = min_t(u8, setup->value, MAX_SETUP_HOLD_CYCLES);
741 hold_dly = min_t(u8, hold->value, MAX_SETUP_HOLD_CYCLES);
742 if (setup_dly && hold_dly) {
743 setup_hold = SPI_SETUP_HOLD(setup_dly - 1, hold_dly - 1);
744 spi_cs_timing = SPI_CS_SETUP_HOLD(tspi->spi_cs_timing1,
745 spi_get_chipselect(spi, 0),
746 setup_hold);
747 if (tspi->spi_cs_timing1 != spi_cs_timing) {
748 tspi->spi_cs_timing1 = spi_cs_timing;
749 tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING1);
750 }
751 }
752
753 inactive_cycles = min_t(u8, inactive->value, MAX_INACTIVE_CYCLES);
754 if (inactive_cycles)
755 inactive_cycles--;
756 cs_state = inactive_cycles ? 0 : 1;
757 spi_cs_timing = tspi->spi_cs_timing2;
758 SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0),
759 cs_state);
760 SPI_SET_CYCLES_BETWEEN_PACKETS(spi_cs_timing, spi_get_chipselect(spi, 0),
761 inactive_cycles);
762 if (tspi->spi_cs_timing2 != spi_cs_timing) {
763 tspi->spi_cs_timing2 = spi_cs_timing;
764 tegra_spi_writel(tspi, spi_cs_timing, SPI_CS_TIMING2);
765 }
766
767 return 0;
768}
769
770static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
771 struct spi_transfer *t,
772 bool is_first_of_msg,
773 bool is_single_xfer)
774{
775 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
776 struct tegra_spi_client_data *cdata = spi->controller_data;
777 u32 speed = t->speed_hz;
778 u8 bits_per_word = t->bits_per_word;
779 u32 command1, command2;
780 int req_mode;
781 u32 tx_tap = 0, rx_tap = 0;
782
783 if (speed != tspi->cur_speed) {
784 clk_set_rate(tspi->clk, speed);
785 tspi->cur_speed = speed;
786 }
787
788 tspi->cur_spi = spi;
789 tspi->cur_pos = 0;
790 tspi->cur_rx_pos = 0;
791 tspi->cur_tx_pos = 0;
792 tspi->curr_xfer = t;
793
794 if (is_first_of_msg) {
795 tegra_spi_clear_status(tspi);
796
797 command1 = tspi->def_command1_reg;
798 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
799
800 command1 &= ~SPI_CONTROL_MODE_MASK;
801 req_mode = spi->mode & 0x3;
802 if (req_mode == SPI_MODE_0)
803 command1 |= SPI_CONTROL_MODE_0;
804 else if (req_mode == SPI_MODE_1)
805 command1 |= SPI_CONTROL_MODE_1;
806 else if (req_mode == SPI_MODE_2)
807 command1 |= SPI_CONTROL_MODE_2;
808 else if (req_mode == SPI_MODE_3)
809 command1 |= SPI_CONTROL_MODE_3;
810
811 if (spi->mode & SPI_LSB_FIRST)
812 command1 |= SPI_LSBIT_FE;
813 else
814 command1 &= ~SPI_LSBIT_FE;
815
816 if (spi->mode & SPI_3WIRE)
817 command1 |= SPI_BIDIROE;
818 else
819 command1 &= ~SPI_BIDIROE;
820
821 if (tspi->cs_control) {
822 if (tspi->cs_control != spi)
823 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
824 tspi->cs_control = NULL;
825 } else
826 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
827
828 /* GPIO based chip select control */
829 if (spi_get_csgpiod(spi, 0))
830 gpiod_set_value(spi_get_csgpiod(spi, 0), 1);
831
832 if (is_single_xfer && !(t->cs_change)) {
833 tspi->use_hw_based_cs = true;
834 command1 &= ~(SPI_CS_SW_HW | SPI_CS_SW_VAL);
835 } else {
836 tspi->use_hw_based_cs = false;
837 command1 |= SPI_CS_SW_HW;
838 if (spi->mode & SPI_CS_HIGH)
839 command1 |= SPI_CS_SW_VAL;
840 else
841 command1 &= ~SPI_CS_SW_VAL;
842 }
843
844 if (tspi->last_used_cs != spi_get_chipselect(spi, 0)) {
845 if (cdata && cdata->tx_clk_tap_delay)
846 tx_tap = cdata->tx_clk_tap_delay;
847 if (cdata && cdata->rx_clk_tap_delay)
848 rx_tap = cdata->rx_clk_tap_delay;
849 command2 = SPI_TX_TAP_DELAY(tx_tap) |
850 SPI_RX_TAP_DELAY(rx_tap);
851 if (command2 != tspi->def_command2_reg)
852 tegra_spi_writel(tspi, command2, SPI_COMMAND2);
853 tspi->last_used_cs = spi_get_chipselect(spi, 0);
854 }
855
856 } else {
857 command1 = tspi->command1_reg;
858 command1 &= ~SPI_BIT_LENGTH(~0);
859 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
860 }
861
862 return command1;
863}
864
865static int tegra_spi_start_transfer_one(struct spi_device *spi,
866 struct spi_transfer *t, u32 command1)
867{
868 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
869 unsigned total_fifo_words;
870 int ret;
871
872 total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
873
874 if (t->rx_nbits == SPI_NBITS_DUAL || t->tx_nbits == SPI_NBITS_DUAL)
875 command1 |= SPI_BOTH_EN_BIT;
876 else
877 command1 &= ~SPI_BOTH_EN_BIT;
878
879 if (tspi->is_packed)
880 command1 |= SPI_PACKED;
881 else
882 command1 &= ~SPI_PACKED;
883
884 command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
885 tspi->cur_direction = 0;
886 if (t->rx_buf) {
887 command1 |= SPI_RX_EN;
888 tspi->cur_direction |= DATA_DIR_RX;
889 }
890 if (t->tx_buf) {
891 command1 |= SPI_TX_EN;
892 tspi->cur_direction |= DATA_DIR_TX;
893 }
894 command1 |= SPI_CS_SEL(spi_get_chipselect(spi, 0));
895 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
896 tspi->command1_reg = command1;
897
898 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
899 tspi->def_command1_reg, (unsigned)command1);
900
901 ret = tegra_spi_flush_fifos(tspi);
902 if (ret < 0)
903 return ret;
904 if (total_fifo_words > SPI_FIFO_DEPTH)
905 ret = tegra_spi_start_dma_based_transfer(tspi, t);
906 else
907 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
908 return ret;
909}
910
911static struct tegra_spi_client_data
912 *tegra_spi_parse_cdata_dt(struct spi_device *spi)
913{
914 struct tegra_spi_client_data *cdata;
915 struct device_node *target_np;
916
917 target_np = spi->dev.of_node;
918 if (!target_np) {
919 dev_dbg(&spi->dev, "device node not found\n");
920 return NULL;
921 }
922
923 cdata = kzalloc(sizeof(*cdata), GFP_KERNEL);
924 if (!cdata)
925 return NULL;
926
927 of_property_read_u32(target_np, "nvidia,tx-clk-tap-delay",
928 &cdata->tx_clk_tap_delay);
929 of_property_read_u32(target_np, "nvidia,rx-clk-tap-delay",
930 &cdata->rx_clk_tap_delay);
931 return cdata;
932}
933
934static void tegra_spi_cleanup(struct spi_device *spi)
935{
936 struct tegra_spi_client_data *cdata = spi->controller_data;
937
938 spi->controller_data = NULL;
939 if (spi->dev.of_node)
940 kfree(cdata);
941}
942
943static int tegra_spi_setup(struct spi_device *spi)
944{
945 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
946 struct tegra_spi_client_data *cdata = spi->controller_data;
947 u32 val;
948 unsigned long flags;
949 int ret;
950
951 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
952 spi->bits_per_word,
953 spi->mode & SPI_CPOL ? "" : "~",
954 spi->mode & SPI_CPHA ? "" : "~",
955 spi->max_speed_hz);
956
957 if (!cdata) {
958 cdata = tegra_spi_parse_cdata_dt(spi);
959 spi->controller_data = cdata;
960 }
961
962 ret = pm_runtime_resume_and_get(tspi->dev);
963 if (ret < 0) {
964 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
965 if (cdata)
966 tegra_spi_cleanup(spi);
967 return ret;
968 }
969
970 if (tspi->soc_data->has_intr_mask_reg) {
971 val = tegra_spi_readl(tspi, SPI_INTR_MASK);
972 val &= ~SPI_INTR_ALL_MASK;
973 tegra_spi_writel(tspi, val, SPI_INTR_MASK);
974 }
975
976 spin_lock_irqsave(&tspi->lock, flags);
977 /* GPIO based chip select control */
978 if (spi_get_csgpiod(spi, 0))
979 gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
980
981 val = tspi->def_command1_reg;
982 if (spi->mode & SPI_CS_HIGH)
983 val &= ~SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
984 else
985 val |= SPI_CS_POL_INACTIVE(spi_get_chipselect(spi, 0));
986 tspi->def_command1_reg = val;
987 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
988 spin_unlock_irqrestore(&tspi->lock, flags);
989
990 pm_runtime_put(tspi->dev);
991 return 0;
992}
993
994static void tegra_spi_transfer_end(struct spi_device *spi)
995{
996 struct tegra_spi_data *tspi = spi_controller_get_devdata(spi->controller);
997 int cs_val = (spi->mode & SPI_CS_HIGH) ? 0 : 1;
998
999 /* GPIO based chip select control */
1000 if (spi_get_csgpiod(spi, 0))
1001 gpiod_set_value(spi_get_csgpiod(spi, 0), 0);
1002
1003 if (!tspi->use_hw_based_cs) {
1004 if (cs_val)
1005 tspi->command1_reg |= SPI_CS_SW_VAL;
1006 else
1007 tspi->command1_reg &= ~SPI_CS_SW_VAL;
1008 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1009 }
1010
1011 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1012}
1013
1014static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
1015{
1016 dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
1017 dev_dbg(tspi->dev, "Command1: 0x%08x | Command2: 0x%08x\n",
1018 tegra_spi_readl(tspi, SPI_COMMAND1),
1019 tegra_spi_readl(tspi, SPI_COMMAND2));
1020 dev_dbg(tspi->dev, "DMA_CTL: 0x%08x | DMA_BLK: 0x%08x\n",
1021 tegra_spi_readl(tspi, SPI_DMA_CTL),
1022 tegra_spi_readl(tspi, SPI_DMA_BLK));
1023 dev_dbg(tspi->dev, "TRANS_STAT: 0x%08x | FIFO_STATUS: 0x%08x\n",
1024 tegra_spi_readl(tspi, SPI_TRANS_STATUS),
1025 tegra_spi_readl(tspi, SPI_FIFO_STATUS));
1026}
1027
1028static int tegra_spi_transfer_one_message(struct spi_controller *host,
1029 struct spi_message *msg)
1030{
1031 bool is_first_msg = true;
1032 struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
1033 struct spi_transfer *xfer;
1034 struct spi_device *spi = msg->spi;
1035 int ret;
1036 bool skip = false;
1037 int single_xfer;
1038
1039 msg->status = 0;
1040 msg->actual_length = 0;
1041
1042 single_xfer = list_is_singular(&msg->transfers);
1043 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
1044 u32 cmd1;
1045
1046 reinit_completion(&tspi->xfer_completion);
1047
1048 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg,
1049 single_xfer);
1050
1051 if (!xfer->len) {
1052 ret = 0;
1053 skip = true;
1054 goto complete_xfer;
1055 }
1056
1057 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
1058 if (ret < 0) {
1059 dev_err(tspi->dev,
1060 "spi can not start transfer, err %d\n", ret);
1061 goto complete_xfer;
1062 }
1063
1064 is_first_msg = false;
1065 ret = wait_for_completion_timeout(&tspi->xfer_completion,
1066 SPI_DMA_TIMEOUT);
1067 if (WARN_ON(ret == 0)) {
1068 dev_err(tspi->dev, "spi transfer timeout\n");
1069 if (tspi->is_curr_dma_xfer &&
1070 (tspi->cur_direction & DATA_DIR_TX))
1071 dmaengine_terminate_all(tspi->tx_dma_chan);
1072 if (tspi->is_curr_dma_xfer &&
1073 (tspi->cur_direction & DATA_DIR_RX))
1074 dmaengine_terminate_all(tspi->rx_dma_chan);
1075 ret = -EIO;
1076 tegra_spi_dump_regs(tspi);
1077 tegra_spi_flush_fifos(tspi);
1078 reset_control_assert(tspi->rst);
1079 udelay(2);
1080 reset_control_deassert(tspi->rst);
1081 tspi->last_used_cs = host->num_chipselect + 1;
1082 goto complete_xfer;
1083 }
1084
1085 if (tspi->tx_status || tspi->rx_status) {
1086 dev_err(tspi->dev, "Error in Transfer\n");
1087 ret = -EIO;
1088 tegra_spi_dump_regs(tspi);
1089 goto complete_xfer;
1090 }
1091 msg->actual_length += xfer->len;
1092
1093complete_xfer:
1094 if (ret < 0 || skip) {
1095 tegra_spi_transfer_end(spi);
1096 spi_transfer_delay_exec(xfer);
1097 goto exit;
1098 } else if (list_is_last(&xfer->transfer_list,
1099 &msg->transfers)) {
1100 if (xfer->cs_change)
1101 tspi->cs_control = spi;
1102 else {
1103 tegra_spi_transfer_end(spi);
1104 spi_transfer_delay_exec(xfer);
1105 }
1106 } else if (xfer->cs_change) {
1107 tegra_spi_transfer_end(spi);
1108 spi_transfer_delay_exec(xfer);
1109 }
1110
1111 }
1112 ret = 0;
1113exit:
1114 msg->status = ret;
1115 spi_finalize_current_message(host);
1116 return ret;
1117}
1118
1119static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
1120{
1121 struct spi_transfer *t = tspi->curr_xfer;
1122 unsigned long flags;
1123
1124 spin_lock_irqsave(&tspi->lock, flags);
1125 if (tspi->tx_status || tspi->rx_status) {
1126 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
1127 tspi->status_reg);
1128 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
1129 tspi->command1_reg, tspi->dma_control_reg);
1130 tegra_spi_dump_regs(tspi);
1131 tegra_spi_flush_fifos(tspi);
1132 complete(&tspi->xfer_completion);
1133 spin_unlock_irqrestore(&tspi->lock, flags);
1134 reset_control_assert(tspi->rst);
1135 udelay(2);
1136 reset_control_deassert(tspi->rst);
1137 return IRQ_HANDLED;
1138 }
1139
1140 if (tspi->cur_direction & DATA_DIR_RX)
1141 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
1142
1143 if (tspi->cur_direction & DATA_DIR_TX)
1144 tspi->cur_pos = tspi->cur_tx_pos;
1145 else
1146 tspi->cur_pos = tspi->cur_rx_pos;
1147
1148 if (tspi->cur_pos == t->len) {
1149 complete(&tspi->xfer_completion);
1150 goto exit;
1151 }
1152
1153 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
1154 tegra_spi_start_cpu_based_transfer(tspi, t);
1155exit:
1156 spin_unlock_irqrestore(&tspi->lock, flags);
1157 return IRQ_HANDLED;
1158}
1159
1160static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
1161{
1162 struct spi_transfer *t = tspi->curr_xfer;
1163 long wait_status;
1164 int err = 0;
1165 unsigned total_fifo_words;
1166 unsigned long flags;
1167
1168 /* Abort dmas if any error */
1169 if (tspi->cur_direction & DATA_DIR_TX) {
1170 if (tspi->tx_status) {
1171 dmaengine_terminate_all(tspi->tx_dma_chan);
1172 err += 1;
1173 } else {
1174 wait_status = wait_for_completion_interruptible_timeout(
1175 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
1176 if (wait_status <= 0) {
1177 dmaengine_terminate_all(tspi->tx_dma_chan);
1178 dev_err(tspi->dev, "TxDma Xfer failed\n");
1179 err += 1;
1180 }
1181 }
1182 }
1183
1184 if (tspi->cur_direction & DATA_DIR_RX) {
1185 if (tspi->rx_status) {
1186 dmaengine_terminate_all(tspi->rx_dma_chan);
1187 err += 2;
1188 } else {
1189 wait_status = wait_for_completion_interruptible_timeout(
1190 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
1191 if (wait_status <= 0) {
1192 dmaengine_terminate_all(tspi->rx_dma_chan);
1193 dev_err(tspi->dev, "RxDma Xfer failed\n");
1194 err += 2;
1195 }
1196 }
1197 }
1198
1199 spin_lock_irqsave(&tspi->lock, flags);
1200 if (err) {
1201 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1202 tspi->status_reg);
1203 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1204 tspi->command1_reg, tspi->dma_control_reg);
1205 tegra_spi_dump_regs(tspi);
1206 tegra_spi_flush_fifos(tspi);
1207 complete(&tspi->xfer_completion);
1208 spin_unlock_irqrestore(&tspi->lock, flags);
1209 reset_control_assert(tspi->rst);
1210 udelay(2);
1211 reset_control_deassert(tspi->rst);
1212 return IRQ_HANDLED;
1213 }
1214
1215 if (tspi->cur_direction & DATA_DIR_RX)
1216 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1217
1218 if (tspi->cur_direction & DATA_DIR_TX)
1219 tspi->cur_pos = tspi->cur_tx_pos;
1220 else
1221 tspi->cur_pos = tspi->cur_rx_pos;
1222
1223 if (tspi->cur_pos == t->len) {
1224 complete(&tspi->xfer_completion);
1225 goto exit;
1226 }
1227
1228 /* Continue transfer in current message */
1229 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1230 tspi, t);
1231 if (total_fifo_words > SPI_FIFO_DEPTH)
1232 err = tegra_spi_start_dma_based_transfer(tspi, t);
1233 else
1234 err = tegra_spi_start_cpu_based_transfer(tspi, t);
1235
1236exit:
1237 spin_unlock_irqrestore(&tspi->lock, flags);
1238 return IRQ_HANDLED;
1239}
1240
1241static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1242{
1243 struct tegra_spi_data *tspi = context_data;
1244
1245 if (!tspi->is_curr_dma_xfer)
1246 return handle_cpu_based_xfer(tspi);
1247 return handle_dma_based_xfer(tspi);
1248}
1249
1250static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1251{
1252 struct tegra_spi_data *tspi = context_data;
1253
1254 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1255 if (tspi->cur_direction & DATA_DIR_TX)
1256 tspi->tx_status = tspi->status_reg &
1257 (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1258
1259 if (tspi->cur_direction & DATA_DIR_RX)
1260 tspi->rx_status = tspi->status_reg &
1261 (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1262 tegra_spi_clear_status(tspi);
1263
1264 return IRQ_WAKE_THREAD;
1265}
1266
1267static struct tegra_spi_soc_data tegra114_spi_soc_data = {
1268 .has_intr_mask_reg = false,
1269};
1270
1271static struct tegra_spi_soc_data tegra124_spi_soc_data = {
1272 .has_intr_mask_reg = false,
1273};
1274
1275static struct tegra_spi_soc_data tegra210_spi_soc_data = {
1276 .has_intr_mask_reg = true,
1277};
1278
1279static const struct of_device_id tegra_spi_of_match[] = {
1280 {
1281 .compatible = "nvidia,tegra114-spi",
1282 .data = &tegra114_spi_soc_data,
1283 }, {
1284 .compatible = "nvidia,tegra124-spi",
1285 .data = &tegra124_spi_soc_data,
1286 }, {
1287 .compatible = "nvidia,tegra210-spi",
1288 .data = &tegra210_spi_soc_data,
1289 },
1290 {}
1291};
1292MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1293
1294static int tegra_spi_probe(struct platform_device *pdev)
1295{
1296 struct spi_controller *host;
1297 struct tegra_spi_data *tspi;
1298 struct resource *r;
1299 int ret, spi_irq;
1300 int bus_num;
1301
1302 host = spi_alloc_host(&pdev->dev, sizeof(*tspi));
1303 if (!host) {
1304 dev_err(&pdev->dev, "host allocation failed\n");
1305 return -ENOMEM;
1306 }
1307 platform_set_drvdata(pdev, host);
1308 tspi = spi_controller_get_devdata(host);
1309
1310 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1311 &host->max_speed_hz))
1312 host->max_speed_hz = 25000000; /* 25MHz */
1313
1314 /* the spi->mode bits understood by this driver: */
1315 host->use_gpio_descriptors = true;
1316 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
1317 SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
1318 host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1319 host->setup = tegra_spi_setup;
1320 host->cleanup = tegra_spi_cleanup;
1321 host->transfer_one_message = tegra_spi_transfer_one_message;
1322 host->set_cs_timing = tegra_spi_set_hw_cs_timing;
1323 host->num_chipselect = MAX_CHIP_SELECT;
1324 host->auto_runtime_pm = true;
1325 bus_num = of_alias_get_id(pdev->dev.of_node, "spi");
1326 if (bus_num >= 0)
1327 host->bus_num = bus_num;
1328
1329 tspi->host = host;
1330 tspi->dev = &pdev->dev;
1331 spin_lock_init(&tspi->lock);
1332
1333 tspi->soc_data = of_device_get_match_data(&pdev->dev);
1334 if (!tspi->soc_data) {
1335 dev_err(&pdev->dev, "unsupported tegra\n");
1336 ret = -ENODEV;
1337 goto exit_free_host;
1338 }
1339
1340 tspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
1341 if (IS_ERR(tspi->base)) {
1342 ret = PTR_ERR(tspi->base);
1343 goto exit_free_host;
1344 }
1345 tspi->phys = r->start;
1346
1347 spi_irq = platform_get_irq(pdev, 0);
1348 if (spi_irq < 0) {
1349 ret = spi_irq;
1350 goto exit_free_host;
1351 }
1352 tspi->irq = spi_irq;
1353
1354 tspi->clk = devm_clk_get(&pdev->dev, "spi");
1355 if (IS_ERR(tspi->clk)) {
1356 dev_err(&pdev->dev, "can not get clock\n");
1357 ret = PTR_ERR(tspi->clk);
1358 goto exit_free_host;
1359 }
1360
1361 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1362 if (IS_ERR(tspi->rst)) {
1363 dev_err(&pdev->dev, "can not get reset\n");
1364 ret = PTR_ERR(tspi->rst);
1365 goto exit_free_host;
1366 }
1367
1368 tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1369 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1370
1371 ret = tegra_spi_init_dma_param(tspi, true);
1372 if (ret < 0)
1373 goto exit_free_host;
1374 ret = tegra_spi_init_dma_param(tspi, false);
1375 if (ret < 0)
1376 goto exit_rx_dma_free;
1377 tspi->max_buf_size = tspi->dma_buf_size;
1378 init_completion(&tspi->tx_dma_complete);
1379 init_completion(&tspi->rx_dma_complete);
1380
1381 init_completion(&tspi->xfer_completion);
1382
1383 pm_runtime_enable(&pdev->dev);
1384 if (!pm_runtime_enabled(&pdev->dev)) {
1385 ret = tegra_spi_runtime_resume(&pdev->dev);
1386 if (ret)
1387 goto exit_pm_disable;
1388 }
1389
1390 ret = pm_runtime_resume_and_get(&pdev->dev);
1391 if (ret < 0) {
1392 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1393 goto exit_pm_disable;
1394 }
1395
1396 reset_control_assert(tspi->rst);
1397 udelay(2);
1398 reset_control_deassert(tspi->rst);
1399 tspi->def_command1_reg = SPI_M_S;
1400 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1401 tspi->spi_cs_timing1 = tegra_spi_readl(tspi, SPI_CS_TIMING1);
1402 tspi->spi_cs_timing2 = tegra_spi_readl(tspi, SPI_CS_TIMING2);
1403 tspi->def_command2_reg = tegra_spi_readl(tspi, SPI_COMMAND2);
1404 tspi->last_used_cs = host->num_chipselect + 1;
1405 pm_runtime_put(&pdev->dev);
1406 ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1407 tegra_spi_isr_thread, IRQF_ONESHOT,
1408 dev_name(&pdev->dev), tspi);
1409 if (ret < 0) {
1410 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1411 tspi->irq);
1412 goto exit_pm_disable;
1413 }
1414
1415 host->dev.of_node = pdev->dev.of_node;
1416 ret = devm_spi_register_controller(&pdev->dev, host);
1417 if (ret < 0) {
1418 dev_err(&pdev->dev, "can not register to host err %d\n", ret);
1419 goto exit_free_irq;
1420 }
1421 return ret;
1422
1423exit_free_irq:
1424 free_irq(spi_irq, tspi);
1425exit_pm_disable:
1426 pm_runtime_disable(&pdev->dev);
1427 if (!pm_runtime_status_suspended(&pdev->dev))
1428 tegra_spi_runtime_suspend(&pdev->dev);
1429 tegra_spi_deinit_dma_param(tspi, false);
1430exit_rx_dma_free:
1431 tegra_spi_deinit_dma_param(tspi, true);
1432exit_free_host:
1433 spi_controller_put(host);
1434 return ret;
1435}
1436
1437static void tegra_spi_remove(struct platform_device *pdev)
1438{
1439 struct spi_controller *host = platform_get_drvdata(pdev);
1440 struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
1441
1442 free_irq(tspi->irq, tspi);
1443
1444 if (tspi->tx_dma_chan)
1445 tegra_spi_deinit_dma_param(tspi, false);
1446
1447 if (tspi->rx_dma_chan)
1448 tegra_spi_deinit_dma_param(tspi, true);
1449
1450 pm_runtime_disable(&pdev->dev);
1451 if (!pm_runtime_status_suspended(&pdev->dev))
1452 tegra_spi_runtime_suspend(&pdev->dev);
1453}
1454
1455#ifdef CONFIG_PM_SLEEP
1456static int tegra_spi_suspend(struct device *dev)
1457{
1458 struct spi_controller *host = dev_get_drvdata(dev);
1459
1460 return spi_controller_suspend(host);
1461}
1462
1463static int tegra_spi_resume(struct device *dev)
1464{
1465 struct spi_controller *host = dev_get_drvdata(dev);
1466 struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
1467 int ret;
1468
1469 ret = pm_runtime_resume_and_get(dev);
1470 if (ret < 0) {
1471 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1472 return ret;
1473 }
1474 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1475 tegra_spi_writel(tspi, tspi->def_command2_reg, SPI_COMMAND2);
1476 tspi->last_used_cs = host->num_chipselect + 1;
1477 pm_runtime_put(dev);
1478
1479 return spi_controller_resume(host);
1480}
1481#endif
1482
1483static int tegra_spi_runtime_suspend(struct device *dev)
1484{
1485 struct spi_controller *host = dev_get_drvdata(dev);
1486 struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
1487
1488 /* Flush all write which are in PPSB queue by reading back */
1489 tegra_spi_readl(tspi, SPI_COMMAND1);
1490
1491 clk_disable_unprepare(tspi->clk);
1492 return 0;
1493}
1494
1495static int tegra_spi_runtime_resume(struct device *dev)
1496{
1497 struct spi_controller *host = dev_get_drvdata(dev);
1498 struct tegra_spi_data *tspi = spi_controller_get_devdata(host);
1499 int ret;
1500
1501 ret = clk_prepare_enable(tspi->clk);
1502 if (ret < 0) {
1503 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1504 return ret;
1505 }
1506 return 0;
1507}
1508
1509static const struct dev_pm_ops tegra_spi_pm_ops = {
1510 SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1511 tegra_spi_runtime_resume, NULL)
1512 SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1513};
1514static struct platform_driver tegra_spi_driver = {
1515 .driver = {
1516 .name = "spi-tegra114",
1517 .pm = &tegra_spi_pm_ops,
1518 .of_match_table = tegra_spi_of_match,
1519 },
1520 .probe = tegra_spi_probe,
1521 .remove_new = tegra_spi_remove,
1522};
1523module_platform_driver(tegra_spi_driver);
1524
1525MODULE_ALIAS("platform:spi-tegra114");
1526MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1527MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1528MODULE_LICENSE("GPL v2");
1/*
2 * SPI driver for NVIDIA's Tegra114 SPI Controller.
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/clk.h>
20#include <linux/completion.h>
21#include <linux/delay.h>
22#include <linux/dmaengine.h>
23#include <linux/dma-mapping.h>
24#include <linux/dmapool.h>
25#include <linux/err.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/kernel.h>
29#include <linux/kthread.h>
30#include <linux/module.h>
31#include <linux/platform_device.h>
32#include <linux/pm_runtime.h>
33#include <linux/of.h>
34#include <linux/of_device.h>
35#include <linux/reset.h>
36#include <linux/spi/spi.h>
37
38#define SPI_COMMAND1 0x000
39#define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40#define SPI_PACKED (1 << 5)
41#define SPI_TX_EN (1 << 11)
42#define SPI_RX_EN (1 << 12)
43#define SPI_BOTH_EN_BYTE (1 << 13)
44#define SPI_BOTH_EN_BIT (1 << 14)
45#define SPI_LSBYTE_FE (1 << 15)
46#define SPI_LSBIT_FE (1 << 16)
47#define SPI_BIDIROE (1 << 17)
48#define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
49#define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
50#define SPI_IDLE_SDA_PULL_LOW (2 << 18)
51#define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
52#define SPI_IDLE_SDA_MASK (3 << 18)
53#define SPI_CS_SS_VAL (1 << 20)
54#define SPI_CS_SW_HW (1 << 21)
55/* SPI_CS_POL_INACTIVE bits are default high */
56 /* n from 0 to 3 */
57#define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
58#define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
59
60#define SPI_CS_SEL_0 (0 << 26)
61#define SPI_CS_SEL_1 (1 << 26)
62#define SPI_CS_SEL_2 (2 << 26)
63#define SPI_CS_SEL_3 (3 << 26)
64#define SPI_CS_SEL_MASK (3 << 26)
65#define SPI_CS_SEL(x) (((x) & 0x3) << 26)
66#define SPI_CONTROL_MODE_0 (0 << 28)
67#define SPI_CONTROL_MODE_1 (1 << 28)
68#define SPI_CONTROL_MODE_2 (2 << 28)
69#define SPI_CONTROL_MODE_3 (3 << 28)
70#define SPI_CONTROL_MODE_MASK (3 << 28)
71#define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
72#define SPI_M_S (1 << 30)
73#define SPI_PIO (1 << 31)
74
75#define SPI_COMMAND2 0x004
76#define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
77#define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
78
79#define SPI_CS_TIMING1 0x008
80#define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
81#define SPI_CS_SETUP_HOLD(reg, cs, val) \
82 ((((val) & 0xFFu) << ((cs) * 8)) | \
83 ((reg) & ~(0xFFu << ((cs) * 8))))
84
85#define SPI_CS_TIMING2 0x00C
86#define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
87#define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
88#define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
89#define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
90#define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
91#define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
92#define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
93#define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
94#define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
95 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
96 ((reg) & ~(1 << ((cs) * 8 + 5))))
97#define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
98 (reg = (((val) & 0xF) << ((cs) * 8)) | \
99 ((reg) & ~(0xF << ((cs) * 8))))
100
101#define SPI_TRANS_STATUS 0x010
102#define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
103#define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
104#define SPI_RDY (1 << 30)
105
106#define SPI_FIFO_STATUS 0x014
107#define SPI_RX_FIFO_EMPTY (1 << 0)
108#define SPI_RX_FIFO_FULL (1 << 1)
109#define SPI_TX_FIFO_EMPTY (1 << 2)
110#define SPI_TX_FIFO_FULL (1 << 3)
111#define SPI_RX_FIFO_UNF (1 << 4)
112#define SPI_RX_FIFO_OVF (1 << 5)
113#define SPI_TX_FIFO_UNF (1 << 6)
114#define SPI_TX_FIFO_OVF (1 << 7)
115#define SPI_ERR (1 << 8)
116#define SPI_TX_FIFO_FLUSH (1 << 14)
117#define SPI_RX_FIFO_FLUSH (1 << 15)
118#define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
119#define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
120#define SPI_FRAME_END (1 << 30)
121#define SPI_CS_INACTIVE (1 << 31)
122
123#define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
124 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
125#define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
126
127#define SPI_TX_DATA 0x018
128#define SPI_RX_DATA 0x01C
129
130#define SPI_DMA_CTL 0x020
131#define SPI_TX_TRIG_1 (0 << 15)
132#define SPI_TX_TRIG_4 (1 << 15)
133#define SPI_TX_TRIG_8 (2 << 15)
134#define SPI_TX_TRIG_16 (3 << 15)
135#define SPI_TX_TRIG_MASK (3 << 15)
136#define SPI_RX_TRIG_1 (0 << 19)
137#define SPI_RX_TRIG_4 (1 << 19)
138#define SPI_RX_TRIG_8 (2 << 19)
139#define SPI_RX_TRIG_16 (3 << 19)
140#define SPI_RX_TRIG_MASK (3 << 19)
141#define SPI_IE_TX (1 << 28)
142#define SPI_IE_RX (1 << 29)
143#define SPI_CONT (1 << 30)
144#define SPI_DMA (1 << 31)
145#define SPI_DMA_EN SPI_DMA
146
147#define SPI_DMA_BLK 0x024
148#define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
149
150#define SPI_TX_FIFO 0x108
151#define SPI_RX_FIFO 0x188
152#define MAX_CHIP_SELECT 4
153#define SPI_FIFO_DEPTH 64
154#define DATA_DIR_TX (1 << 0)
155#define DATA_DIR_RX (1 << 1)
156
157#define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
158#define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
159#define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
160#define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
161#define MAX_HOLD_CYCLES 16
162#define SPI_DEFAULT_SPEED 25000000
163
164struct tegra_spi_data {
165 struct device *dev;
166 struct spi_master *master;
167 spinlock_t lock;
168
169 struct clk *clk;
170 struct reset_control *rst;
171 void __iomem *base;
172 phys_addr_t phys;
173 unsigned irq;
174 u32 cur_speed;
175
176 struct spi_device *cur_spi;
177 struct spi_device *cs_control;
178 unsigned cur_pos;
179 unsigned words_per_32bit;
180 unsigned bytes_per_word;
181 unsigned curr_dma_words;
182 unsigned cur_direction;
183
184 unsigned cur_rx_pos;
185 unsigned cur_tx_pos;
186
187 unsigned dma_buf_size;
188 unsigned max_buf_size;
189 bool is_curr_dma_xfer;
190
191 struct completion rx_dma_complete;
192 struct completion tx_dma_complete;
193
194 u32 tx_status;
195 u32 rx_status;
196 u32 status_reg;
197 bool is_packed;
198
199 u32 command1_reg;
200 u32 dma_control_reg;
201 u32 def_command1_reg;
202
203 struct completion xfer_completion;
204 struct spi_transfer *curr_xfer;
205 struct dma_chan *rx_dma_chan;
206 u32 *rx_dma_buf;
207 dma_addr_t rx_dma_phys;
208 struct dma_async_tx_descriptor *rx_dma_desc;
209
210 struct dma_chan *tx_dma_chan;
211 u32 *tx_dma_buf;
212 dma_addr_t tx_dma_phys;
213 struct dma_async_tx_descriptor *tx_dma_desc;
214};
215
216static int tegra_spi_runtime_suspend(struct device *dev);
217static int tegra_spi_runtime_resume(struct device *dev);
218
219static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
220 unsigned long reg)
221{
222 return readl(tspi->base + reg);
223}
224
225static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
226 u32 val, unsigned long reg)
227{
228 writel(val, tspi->base + reg);
229
230 /* Read back register to make sure that register writes completed */
231 if (reg != SPI_TX_FIFO)
232 readl(tspi->base + SPI_COMMAND1);
233}
234
235static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
236{
237 u32 val;
238
239 /* Write 1 to clear status register */
240 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
241 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
242
243 /* Clear fifo status error if any */
244 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
245 if (val & SPI_ERR)
246 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
247 SPI_FIFO_STATUS);
248}
249
250static unsigned tegra_spi_calculate_curr_xfer_param(
251 struct spi_device *spi, struct tegra_spi_data *tspi,
252 struct spi_transfer *t)
253{
254 unsigned remain_len = t->len - tspi->cur_pos;
255 unsigned max_word;
256 unsigned bits_per_word = t->bits_per_word;
257 unsigned max_len;
258 unsigned total_fifo_words;
259
260 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
261
262 if (bits_per_word == 8 || bits_per_word == 16) {
263 tspi->is_packed = 1;
264 tspi->words_per_32bit = 32/bits_per_word;
265 } else {
266 tspi->is_packed = 0;
267 tspi->words_per_32bit = 1;
268 }
269
270 if (tspi->is_packed) {
271 max_len = min(remain_len, tspi->max_buf_size);
272 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
273 total_fifo_words = (max_len + 3) / 4;
274 } else {
275 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
276 max_word = min(max_word, tspi->max_buf_size/4);
277 tspi->curr_dma_words = max_word;
278 total_fifo_words = max_word;
279 }
280 return total_fifo_words;
281}
282
283static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
284 struct tegra_spi_data *tspi, struct spi_transfer *t)
285{
286 unsigned nbytes;
287 unsigned tx_empty_count;
288 u32 fifo_status;
289 unsigned max_n_32bit;
290 unsigned i, count;
291 unsigned int written_words;
292 unsigned fifo_words_left;
293 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
294
295 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
296 tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
297
298 if (tspi->is_packed) {
299 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
300 written_words = min(fifo_words_left, tspi->curr_dma_words);
301 nbytes = written_words * tspi->bytes_per_word;
302 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
303 for (count = 0; count < max_n_32bit; count++) {
304 u32 x = 0;
305
306 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
307 x |= (u32)(*tx_buf++) << (i * 8);
308 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
309 }
310 } else {
311 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
312 written_words = max_n_32bit;
313 nbytes = written_words * tspi->bytes_per_word;
314 for (count = 0; count < max_n_32bit; count++) {
315 u32 x = 0;
316
317 for (i = 0; nbytes && (i < tspi->bytes_per_word);
318 i++, nbytes--)
319 x |= (u32)(*tx_buf++) << (i * 8);
320 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
321 }
322 }
323 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
324 return written_words;
325}
326
327static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
328 struct tegra_spi_data *tspi, struct spi_transfer *t)
329{
330 unsigned rx_full_count;
331 u32 fifo_status;
332 unsigned i, count;
333 unsigned int read_words = 0;
334 unsigned len;
335 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
336
337 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
338 rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
339 if (tspi->is_packed) {
340 len = tspi->curr_dma_words * tspi->bytes_per_word;
341 for (count = 0; count < rx_full_count; count++) {
342 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
343
344 for (i = 0; len && (i < 4); i++, len--)
345 *rx_buf++ = (x >> i*8) & 0xFF;
346 }
347 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
348 read_words += tspi->curr_dma_words;
349 } else {
350 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
351
352 for (count = 0; count < rx_full_count; count++) {
353 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
354
355 for (i = 0; (i < tspi->bytes_per_word); i++)
356 *rx_buf++ = (x >> (i*8)) & 0xFF;
357 }
358 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word;
359 read_words += rx_full_count;
360 }
361 return read_words;
362}
363
364static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
365 struct tegra_spi_data *tspi, struct spi_transfer *t)
366{
367 /* Make the dma buffer to read by cpu */
368 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
369 tspi->dma_buf_size, DMA_TO_DEVICE);
370
371 if (tspi->is_packed) {
372 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
373
374 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
375 } else {
376 unsigned int i;
377 unsigned int count;
378 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
379 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
380
381 for (count = 0; count < tspi->curr_dma_words; count++) {
382 u32 x = 0;
383
384 for (i = 0; consume && (i < tspi->bytes_per_word);
385 i++, consume--)
386 x |= (u32)(*tx_buf++) << (i * 8);
387 tspi->tx_dma_buf[count] = x;
388 }
389 }
390 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
391
392 /* Make the dma buffer to read by dma */
393 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
394 tspi->dma_buf_size, DMA_TO_DEVICE);
395}
396
397static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
398 struct tegra_spi_data *tspi, struct spi_transfer *t)
399{
400 /* Make the dma buffer to read by cpu */
401 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
402 tspi->dma_buf_size, DMA_FROM_DEVICE);
403
404 if (tspi->is_packed) {
405 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
406
407 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
408 } else {
409 unsigned int i;
410 unsigned int count;
411 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
412 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
413
414 for (count = 0; count < tspi->curr_dma_words; count++) {
415 u32 x = tspi->rx_dma_buf[count] & rx_mask;
416
417 for (i = 0; (i < tspi->bytes_per_word); i++)
418 *rx_buf++ = (x >> (i*8)) & 0xFF;
419 }
420 }
421 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
422
423 /* Make the dma buffer to read by dma */
424 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
425 tspi->dma_buf_size, DMA_FROM_DEVICE);
426}
427
428static void tegra_spi_dma_complete(void *args)
429{
430 struct completion *dma_complete = args;
431
432 complete(dma_complete);
433}
434
435static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
436{
437 reinit_completion(&tspi->tx_dma_complete);
438 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
439 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
440 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
441 if (!tspi->tx_dma_desc) {
442 dev_err(tspi->dev, "Not able to get desc for Tx\n");
443 return -EIO;
444 }
445
446 tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
447 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
448
449 dmaengine_submit(tspi->tx_dma_desc);
450 dma_async_issue_pending(tspi->tx_dma_chan);
451 return 0;
452}
453
454static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
455{
456 reinit_completion(&tspi->rx_dma_complete);
457 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
458 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
459 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
460 if (!tspi->rx_dma_desc) {
461 dev_err(tspi->dev, "Not able to get desc for Rx\n");
462 return -EIO;
463 }
464
465 tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
466 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
467
468 dmaengine_submit(tspi->rx_dma_desc);
469 dma_async_issue_pending(tspi->rx_dma_chan);
470 return 0;
471}
472
473static int tegra_spi_start_dma_based_transfer(
474 struct tegra_spi_data *tspi, struct spi_transfer *t)
475{
476 u32 val;
477 unsigned int len;
478 int ret = 0;
479 u32 status;
480
481 /* Make sure that Rx and Tx fifo are empty */
482 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
483 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
484 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n",
485 (unsigned)status);
486 return -EIO;
487 }
488
489 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
490 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
491
492 if (tspi->is_packed)
493 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
494 4) * 4;
495 else
496 len = tspi->curr_dma_words * 4;
497
498 /* Set attention level based on length of transfer */
499 if (len & 0xF)
500 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
501 else if (((len) >> 4) & 0x1)
502 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
503 else
504 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
505
506 if (tspi->cur_direction & DATA_DIR_TX)
507 val |= SPI_IE_TX;
508
509 if (tspi->cur_direction & DATA_DIR_RX)
510 val |= SPI_IE_RX;
511
512 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
513 tspi->dma_control_reg = val;
514
515 if (tspi->cur_direction & DATA_DIR_TX) {
516 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
517 ret = tegra_spi_start_tx_dma(tspi, len);
518 if (ret < 0) {
519 dev_err(tspi->dev,
520 "Starting tx dma failed, err %d\n", ret);
521 return ret;
522 }
523 }
524
525 if (tspi->cur_direction & DATA_DIR_RX) {
526 /* Make the dma buffer to read by dma */
527 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
528 tspi->dma_buf_size, DMA_FROM_DEVICE);
529
530 ret = tegra_spi_start_rx_dma(tspi, len);
531 if (ret < 0) {
532 dev_err(tspi->dev,
533 "Starting rx dma failed, err %d\n", ret);
534 if (tspi->cur_direction & DATA_DIR_TX)
535 dmaengine_terminate_all(tspi->tx_dma_chan);
536 return ret;
537 }
538 }
539 tspi->is_curr_dma_xfer = true;
540 tspi->dma_control_reg = val;
541
542 val |= SPI_DMA_EN;
543 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
544 return ret;
545}
546
547static int tegra_spi_start_cpu_based_transfer(
548 struct tegra_spi_data *tspi, struct spi_transfer *t)
549{
550 u32 val;
551 unsigned cur_words;
552
553 if (tspi->cur_direction & DATA_DIR_TX)
554 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
555 else
556 cur_words = tspi->curr_dma_words;
557
558 val = SPI_DMA_BLK_SET(cur_words - 1);
559 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
560
561 val = 0;
562 if (tspi->cur_direction & DATA_DIR_TX)
563 val |= SPI_IE_TX;
564
565 if (tspi->cur_direction & DATA_DIR_RX)
566 val |= SPI_IE_RX;
567
568 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
569 tspi->dma_control_reg = val;
570
571 tspi->is_curr_dma_xfer = false;
572
573 val |= SPI_DMA_EN;
574 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
575 return 0;
576}
577
578static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
579 bool dma_to_memory)
580{
581 struct dma_chan *dma_chan;
582 u32 *dma_buf;
583 dma_addr_t dma_phys;
584 int ret;
585 struct dma_slave_config dma_sconfig;
586
587 dma_chan = dma_request_slave_channel_reason(tspi->dev,
588 dma_to_memory ? "rx" : "tx");
589 if (IS_ERR(dma_chan)) {
590 ret = PTR_ERR(dma_chan);
591 if (ret != -EPROBE_DEFER)
592 dev_err(tspi->dev,
593 "Dma channel is not available: %d\n", ret);
594 return ret;
595 }
596
597 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
598 &dma_phys, GFP_KERNEL);
599 if (!dma_buf) {
600 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
601 dma_release_channel(dma_chan);
602 return -ENOMEM;
603 }
604
605 if (dma_to_memory) {
606 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
607 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
608 dma_sconfig.src_maxburst = 0;
609 } else {
610 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
611 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
612 dma_sconfig.dst_maxburst = 0;
613 }
614
615 ret = dmaengine_slave_config(dma_chan, &dma_sconfig);
616 if (ret)
617 goto scrub;
618 if (dma_to_memory) {
619 tspi->rx_dma_chan = dma_chan;
620 tspi->rx_dma_buf = dma_buf;
621 tspi->rx_dma_phys = dma_phys;
622 } else {
623 tspi->tx_dma_chan = dma_chan;
624 tspi->tx_dma_buf = dma_buf;
625 tspi->tx_dma_phys = dma_phys;
626 }
627 return 0;
628
629scrub:
630 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
631 dma_release_channel(dma_chan);
632 return ret;
633}
634
635static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
636 bool dma_to_memory)
637{
638 u32 *dma_buf;
639 dma_addr_t dma_phys;
640 struct dma_chan *dma_chan;
641
642 if (dma_to_memory) {
643 dma_buf = tspi->rx_dma_buf;
644 dma_chan = tspi->rx_dma_chan;
645 dma_phys = tspi->rx_dma_phys;
646 tspi->rx_dma_chan = NULL;
647 tspi->rx_dma_buf = NULL;
648 } else {
649 dma_buf = tspi->tx_dma_buf;
650 dma_chan = tspi->tx_dma_chan;
651 dma_phys = tspi->tx_dma_phys;
652 tspi->tx_dma_buf = NULL;
653 tspi->tx_dma_chan = NULL;
654 }
655 if (!dma_chan)
656 return;
657
658 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
659 dma_release_channel(dma_chan);
660}
661
662static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
663 struct spi_transfer *t, bool is_first_of_msg)
664{
665 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
666 u32 speed = t->speed_hz;
667 u8 bits_per_word = t->bits_per_word;
668 u32 command1;
669 int req_mode;
670
671 if (speed != tspi->cur_speed) {
672 clk_set_rate(tspi->clk, speed);
673 tspi->cur_speed = speed;
674 }
675
676 tspi->cur_spi = spi;
677 tspi->cur_pos = 0;
678 tspi->cur_rx_pos = 0;
679 tspi->cur_tx_pos = 0;
680 tspi->curr_xfer = t;
681
682 if (is_first_of_msg) {
683 tegra_spi_clear_status(tspi);
684
685 command1 = tspi->def_command1_reg;
686 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
687
688 command1 &= ~SPI_CONTROL_MODE_MASK;
689 req_mode = spi->mode & 0x3;
690 if (req_mode == SPI_MODE_0)
691 command1 |= SPI_CONTROL_MODE_0;
692 else if (req_mode == SPI_MODE_1)
693 command1 |= SPI_CONTROL_MODE_1;
694 else if (req_mode == SPI_MODE_2)
695 command1 |= SPI_CONTROL_MODE_2;
696 else if (req_mode == SPI_MODE_3)
697 command1 |= SPI_CONTROL_MODE_3;
698
699 if (tspi->cs_control) {
700 if (tspi->cs_control != spi)
701 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
702 tspi->cs_control = NULL;
703 } else
704 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
705
706 command1 |= SPI_CS_SW_HW;
707 if (spi->mode & SPI_CS_HIGH)
708 command1 |= SPI_CS_SS_VAL;
709 else
710 command1 &= ~SPI_CS_SS_VAL;
711
712 tegra_spi_writel(tspi, 0, SPI_COMMAND2);
713 } else {
714 command1 = tspi->command1_reg;
715 command1 &= ~SPI_BIT_LENGTH(~0);
716 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
717 }
718
719 return command1;
720}
721
722static int tegra_spi_start_transfer_one(struct spi_device *spi,
723 struct spi_transfer *t, u32 command1)
724{
725 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
726 unsigned total_fifo_words;
727 int ret;
728
729 total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
730
731 if (tspi->is_packed)
732 command1 |= SPI_PACKED;
733
734 command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
735 tspi->cur_direction = 0;
736 if (t->rx_buf) {
737 command1 |= SPI_RX_EN;
738 tspi->cur_direction |= DATA_DIR_RX;
739 }
740 if (t->tx_buf) {
741 command1 |= SPI_TX_EN;
742 tspi->cur_direction |= DATA_DIR_TX;
743 }
744 command1 |= SPI_CS_SEL(spi->chip_select);
745 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
746 tspi->command1_reg = command1;
747
748 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
749 tspi->def_command1_reg, (unsigned)command1);
750
751 if (total_fifo_words > SPI_FIFO_DEPTH)
752 ret = tegra_spi_start_dma_based_transfer(tspi, t);
753 else
754 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
755 return ret;
756}
757
758static int tegra_spi_setup(struct spi_device *spi)
759{
760 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
761 u32 val;
762 unsigned long flags;
763 int ret;
764
765 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
766 spi->bits_per_word,
767 spi->mode & SPI_CPOL ? "" : "~",
768 spi->mode & SPI_CPHA ? "" : "~",
769 spi->max_speed_hz);
770
771 ret = pm_runtime_get_sync(tspi->dev);
772 if (ret < 0) {
773 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
774 return ret;
775 }
776
777 spin_lock_irqsave(&tspi->lock, flags);
778 val = tspi->def_command1_reg;
779 if (spi->mode & SPI_CS_HIGH)
780 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
781 else
782 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
783 tspi->def_command1_reg = val;
784 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
785 spin_unlock_irqrestore(&tspi->lock, flags);
786
787 pm_runtime_put(tspi->dev);
788 return 0;
789}
790
791static void tegra_spi_transfer_delay(int delay)
792{
793 if (!delay)
794 return;
795
796 if (delay >= 1000)
797 mdelay(delay / 1000);
798
799 udelay(delay % 1000);
800}
801
802static int tegra_spi_transfer_one_message(struct spi_master *master,
803 struct spi_message *msg)
804{
805 bool is_first_msg = true;
806 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
807 struct spi_transfer *xfer;
808 struct spi_device *spi = msg->spi;
809 int ret;
810 bool skip = false;
811
812 msg->status = 0;
813 msg->actual_length = 0;
814
815 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
816 u32 cmd1;
817
818 reinit_completion(&tspi->xfer_completion);
819
820 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
821
822 if (!xfer->len) {
823 ret = 0;
824 skip = true;
825 goto complete_xfer;
826 }
827
828 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
829 if (ret < 0) {
830 dev_err(tspi->dev,
831 "spi can not start transfer, err %d\n", ret);
832 goto complete_xfer;
833 }
834
835 is_first_msg = false;
836 ret = wait_for_completion_timeout(&tspi->xfer_completion,
837 SPI_DMA_TIMEOUT);
838 if (WARN_ON(ret == 0)) {
839 dev_err(tspi->dev,
840 "spi trasfer timeout, err %d\n", ret);
841 ret = -EIO;
842 goto complete_xfer;
843 }
844
845 if (tspi->tx_status || tspi->rx_status) {
846 dev_err(tspi->dev, "Error in Transfer\n");
847 ret = -EIO;
848 goto complete_xfer;
849 }
850 msg->actual_length += xfer->len;
851
852complete_xfer:
853 if (ret < 0 || skip) {
854 tegra_spi_writel(tspi, tspi->def_command1_reg,
855 SPI_COMMAND1);
856 tegra_spi_transfer_delay(xfer->delay_usecs);
857 goto exit;
858 } else if (list_is_last(&xfer->transfer_list,
859 &msg->transfers)) {
860 if (xfer->cs_change)
861 tspi->cs_control = spi;
862 else {
863 tegra_spi_writel(tspi, tspi->def_command1_reg,
864 SPI_COMMAND1);
865 tegra_spi_transfer_delay(xfer->delay_usecs);
866 }
867 } else if (xfer->cs_change) {
868 tegra_spi_writel(tspi, tspi->def_command1_reg,
869 SPI_COMMAND1);
870 tegra_spi_transfer_delay(xfer->delay_usecs);
871 }
872
873 }
874 ret = 0;
875exit:
876 msg->status = ret;
877 spi_finalize_current_message(master);
878 return ret;
879}
880
881static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
882{
883 struct spi_transfer *t = tspi->curr_xfer;
884 unsigned long flags;
885
886 spin_lock_irqsave(&tspi->lock, flags);
887 if (tspi->tx_status || tspi->rx_status) {
888 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
889 tspi->status_reg);
890 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
891 tspi->command1_reg, tspi->dma_control_reg);
892 reset_control_assert(tspi->rst);
893 udelay(2);
894 reset_control_deassert(tspi->rst);
895 complete(&tspi->xfer_completion);
896 goto exit;
897 }
898
899 if (tspi->cur_direction & DATA_DIR_RX)
900 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
901
902 if (tspi->cur_direction & DATA_DIR_TX)
903 tspi->cur_pos = tspi->cur_tx_pos;
904 else
905 tspi->cur_pos = tspi->cur_rx_pos;
906
907 if (tspi->cur_pos == t->len) {
908 complete(&tspi->xfer_completion);
909 goto exit;
910 }
911
912 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
913 tegra_spi_start_cpu_based_transfer(tspi, t);
914exit:
915 spin_unlock_irqrestore(&tspi->lock, flags);
916 return IRQ_HANDLED;
917}
918
919static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
920{
921 struct spi_transfer *t = tspi->curr_xfer;
922 long wait_status;
923 int err = 0;
924 unsigned total_fifo_words;
925 unsigned long flags;
926
927 /* Abort dmas if any error */
928 if (tspi->cur_direction & DATA_DIR_TX) {
929 if (tspi->tx_status) {
930 dmaengine_terminate_all(tspi->tx_dma_chan);
931 err += 1;
932 } else {
933 wait_status = wait_for_completion_interruptible_timeout(
934 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
935 if (wait_status <= 0) {
936 dmaengine_terminate_all(tspi->tx_dma_chan);
937 dev_err(tspi->dev, "TxDma Xfer failed\n");
938 err += 1;
939 }
940 }
941 }
942
943 if (tspi->cur_direction & DATA_DIR_RX) {
944 if (tspi->rx_status) {
945 dmaengine_terminate_all(tspi->rx_dma_chan);
946 err += 2;
947 } else {
948 wait_status = wait_for_completion_interruptible_timeout(
949 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
950 if (wait_status <= 0) {
951 dmaengine_terminate_all(tspi->rx_dma_chan);
952 dev_err(tspi->dev, "RxDma Xfer failed\n");
953 err += 2;
954 }
955 }
956 }
957
958 spin_lock_irqsave(&tspi->lock, flags);
959 if (err) {
960 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
961 tspi->status_reg);
962 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
963 tspi->command1_reg, tspi->dma_control_reg);
964 reset_control_assert(tspi->rst);
965 udelay(2);
966 reset_control_deassert(tspi->rst);
967 complete(&tspi->xfer_completion);
968 spin_unlock_irqrestore(&tspi->lock, flags);
969 return IRQ_HANDLED;
970 }
971
972 if (tspi->cur_direction & DATA_DIR_RX)
973 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
974
975 if (tspi->cur_direction & DATA_DIR_TX)
976 tspi->cur_pos = tspi->cur_tx_pos;
977 else
978 tspi->cur_pos = tspi->cur_rx_pos;
979
980 if (tspi->cur_pos == t->len) {
981 complete(&tspi->xfer_completion);
982 goto exit;
983 }
984
985 /* Continue transfer in current message */
986 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
987 tspi, t);
988 if (total_fifo_words > SPI_FIFO_DEPTH)
989 err = tegra_spi_start_dma_based_transfer(tspi, t);
990 else
991 err = tegra_spi_start_cpu_based_transfer(tspi, t);
992
993exit:
994 spin_unlock_irqrestore(&tspi->lock, flags);
995 return IRQ_HANDLED;
996}
997
998static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
999{
1000 struct tegra_spi_data *tspi = context_data;
1001
1002 if (!tspi->is_curr_dma_xfer)
1003 return handle_cpu_based_xfer(tspi);
1004 return handle_dma_based_xfer(tspi);
1005}
1006
1007static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1008{
1009 struct tegra_spi_data *tspi = context_data;
1010
1011 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1012 if (tspi->cur_direction & DATA_DIR_TX)
1013 tspi->tx_status = tspi->status_reg &
1014 (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1015
1016 if (tspi->cur_direction & DATA_DIR_RX)
1017 tspi->rx_status = tspi->status_reg &
1018 (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1019 tegra_spi_clear_status(tspi);
1020
1021 return IRQ_WAKE_THREAD;
1022}
1023
1024static const struct of_device_id tegra_spi_of_match[] = {
1025 { .compatible = "nvidia,tegra114-spi", },
1026 {}
1027};
1028MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1029
1030static int tegra_spi_probe(struct platform_device *pdev)
1031{
1032 struct spi_master *master;
1033 struct tegra_spi_data *tspi;
1034 struct resource *r;
1035 int ret, spi_irq;
1036
1037 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1038 if (!master) {
1039 dev_err(&pdev->dev, "master allocation failed\n");
1040 return -ENOMEM;
1041 }
1042 platform_set_drvdata(pdev, master);
1043 tspi = spi_master_get_devdata(master);
1044
1045 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1046 &master->max_speed_hz))
1047 master->max_speed_hz = 25000000; /* 25MHz */
1048
1049 /* the spi->mode bits understood by this driver: */
1050 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1051 master->setup = tegra_spi_setup;
1052 master->transfer_one_message = tegra_spi_transfer_one_message;
1053 master->num_chipselect = MAX_CHIP_SELECT;
1054 master->auto_runtime_pm = true;
1055
1056 tspi->master = master;
1057 tspi->dev = &pdev->dev;
1058 spin_lock_init(&tspi->lock);
1059
1060 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1061 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1062 if (IS_ERR(tspi->base)) {
1063 ret = PTR_ERR(tspi->base);
1064 goto exit_free_master;
1065 }
1066 tspi->phys = r->start;
1067
1068 spi_irq = platform_get_irq(pdev, 0);
1069 tspi->irq = spi_irq;
1070 ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1071 tegra_spi_isr_thread, IRQF_ONESHOT,
1072 dev_name(&pdev->dev), tspi);
1073 if (ret < 0) {
1074 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1075 tspi->irq);
1076 goto exit_free_master;
1077 }
1078
1079 tspi->clk = devm_clk_get(&pdev->dev, "spi");
1080 if (IS_ERR(tspi->clk)) {
1081 dev_err(&pdev->dev, "can not get clock\n");
1082 ret = PTR_ERR(tspi->clk);
1083 goto exit_free_irq;
1084 }
1085
1086 tspi->rst = devm_reset_control_get(&pdev->dev, "spi");
1087 if (IS_ERR(tspi->rst)) {
1088 dev_err(&pdev->dev, "can not get reset\n");
1089 ret = PTR_ERR(tspi->rst);
1090 goto exit_free_irq;
1091 }
1092
1093 tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1094 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1095
1096 ret = tegra_spi_init_dma_param(tspi, true);
1097 if (ret < 0)
1098 goto exit_free_irq;
1099 ret = tegra_spi_init_dma_param(tspi, false);
1100 if (ret < 0)
1101 goto exit_rx_dma_free;
1102 tspi->max_buf_size = tspi->dma_buf_size;
1103 init_completion(&tspi->tx_dma_complete);
1104 init_completion(&tspi->rx_dma_complete);
1105
1106 init_completion(&tspi->xfer_completion);
1107
1108 pm_runtime_enable(&pdev->dev);
1109 if (!pm_runtime_enabled(&pdev->dev)) {
1110 ret = tegra_spi_runtime_resume(&pdev->dev);
1111 if (ret)
1112 goto exit_pm_disable;
1113 }
1114
1115 ret = pm_runtime_get_sync(&pdev->dev);
1116 if (ret < 0) {
1117 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1118 goto exit_pm_disable;
1119 }
1120 tspi->def_command1_reg = SPI_M_S;
1121 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1122 pm_runtime_put(&pdev->dev);
1123
1124 master->dev.of_node = pdev->dev.of_node;
1125 ret = devm_spi_register_master(&pdev->dev, master);
1126 if (ret < 0) {
1127 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1128 goto exit_pm_disable;
1129 }
1130 return ret;
1131
1132exit_pm_disable:
1133 pm_runtime_disable(&pdev->dev);
1134 if (!pm_runtime_status_suspended(&pdev->dev))
1135 tegra_spi_runtime_suspend(&pdev->dev);
1136 tegra_spi_deinit_dma_param(tspi, false);
1137exit_rx_dma_free:
1138 tegra_spi_deinit_dma_param(tspi, true);
1139exit_free_irq:
1140 free_irq(spi_irq, tspi);
1141exit_free_master:
1142 spi_master_put(master);
1143 return ret;
1144}
1145
1146static int tegra_spi_remove(struct platform_device *pdev)
1147{
1148 struct spi_master *master = platform_get_drvdata(pdev);
1149 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1150
1151 free_irq(tspi->irq, tspi);
1152
1153 if (tspi->tx_dma_chan)
1154 tegra_spi_deinit_dma_param(tspi, false);
1155
1156 if (tspi->rx_dma_chan)
1157 tegra_spi_deinit_dma_param(tspi, true);
1158
1159 pm_runtime_disable(&pdev->dev);
1160 if (!pm_runtime_status_suspended(&pdev->dev))
1161 tegra_spi_runtime_suspend(&pdev->dev);
1162
1163 return 0;
1164}
1165
1166#ifdef CONFIG_PM_SLEEP
1167static int tegra_spi_suspend(struct device *dev)
1168{
1169 struct spi_master *master = dev_get_drvdata(dev);
1170
1171 return spi_master_suspend(master);
1172}
1173
1174static int tegra_spi_resume(struct device *dev)
1175{
1176 struct spi_master *master = dev_get_drvdata(dev);
1177 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1178 int ret;
1179
1180 ret = pm_runtime_get_sync(dev);
1181 if (ret < 0) {
1182 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1183 return ret;
1184 }
1185 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1186 pm_runtime_put(dev);
1187
1188 return spi_master_resume(master);
1189}
1190#endif
1191
1192static int tegra_spi_runtime_suspend(struct device *dev)
1193{
1194 struct spi_master *master = dev_get_drvdata(dev);
1195 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1196
1197 /* Flush all write which are in PPSB queue by reading back */
1198 tegra_spi_readl(tspi, SPI_COMMAND1);
1199
1200 clk_disable_unprepare(tspi->clk);
1201 return 0;
1202}
1203
1204static int tegra_spi_runtime_resume(struct device *dev)
1205{
1206 struct spi_master *master = dev_get_drvdata(dev);
1207 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1208 int ret;
1209
1210 ret = clk_prepare_enable(tspi->clk);
1211 if (ret < 0) {
1212 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1213 return ret;
1214 }
1215 return 0;
1216}
1217
1218static const struct dev_pm_ops tegra_spi_pm_ops = {
1219 SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1220 tegra_spi_runtime_resume, NULL)
1221 SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1222};
1223static struct platform_driver tegra_spi_driver = {
1224 .driver = {
1225 .name = "spi-tegra114",
1226 .pm = &tegra_spi_pm_ops,
1227 .of_match_table = tegra_spi_of_match,
1228 },
1229 .probe = tegra_spi_probe,
1230 .remove = tegra_spi_remove,
1231};
1232module_platform_driver(tegra_spi_driver);
1233
1234MODULE_ALIAS("platform:spi-tegra114");
1235MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1236MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1237MODULE_LICENSE("GPL v2");