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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the WinSystems WS16C48
4 * Copyright (C) 2016 William Breathitt Gray
5 */
6#include <linux/bitfield.h>
7#include <linux/bits.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/gpio/regmap.h>
11#include <linux/irq.h>
12#include <linux/isa.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/spinlock.h>
17#include <linux/regmap.h>
18#include <linux/types.h>
19
20#define WS16C48_EXTENT 11
21#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
22
23static unsigned int base[MAX_NUM_WS16C48];
24static unsigned int num_ws16c48;
25module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
26MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
27
28static unsigned int irq[MAX_NUM_WS16C48];
29static unsigned int num_irq;
30module_param_hw_array(irq, uint, irq, &num_irq, 0);
31MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
32
33#define WS16C48_DAT_BASE 0x0
34#define WS16C48_PAGE_LOCK 0x7
35#define WS16C48_PAGE_BASE 0x8
36#define WS16C48_POL WS16C48_PAGE_BASE
37#define WS16C48_ENAB WS16C48_PAGE_BASE
38#define WS16C48_INT_ID WS16C48_PAGE_BASE
39
40#define PAGE_LOCK_PAGE_FIELD GENMASK(7, 6)
41#define POL_PAGE u8_encode_bits(1, PAGE_LOCK_PAGE_FIELD)
42#define ENAB_PAGE u8_encode_bits(2, PAGE_LOCK_PAGE_FIELD)
43#define INT_ID_PAGE u8_encode_bits(3, PAGE_LOCK_PAGE_FIELD)
44
45static const struct regmap_range ws16c48_wr_ranges[] = {
46 regmap_reg_range(0x0, 0x5), regmap_reg_range(0x7, 0xA),
47};
48static const struct regmap_range ws16c48_rd_ranges[] = {
49 regmap_reg_range(0x0, 0xA),
50};
51static const struct regmap_range ws16c48_volatile_ranges[] = {
52 regmap_reg_range(0x0, 0x6), regmap_reg_range(0x8, 0xA),
53};
54static const struct regmap_access_table ws16c48_wr_table = {
55 .yes_ranges = ws16c48_wr_ranges,
56 .n_yes_ranges = ARRAY_SIZE(ws16c48_wr_ranges),
57};
58static const struct regmap_access_table ws16c48_rd_table = {
59 .yes_ranges = ws16c48_rd_ranges,
60 .n_yes_ranges = ARRAY_SIZE(ws16c48_rd_ranges),
61};
62static const struct regmap_access_table ws16c48_volatile_table = {
63 .yes_ranges = ws16c48_volatile_ranges,
64 .n_yes_ranges = ARRAY_SIZE(ws16c48_volatile_ranges),
65};
66static const struct regmap_config ws16c48_regmap_config = {
67 .reg_bits = 8,
68 .reg_stride = 1,
69 .val_bits = 8,
70 .io_port = true,
71 .wr_table = &ws16c48_wr_table,
72 .rd_table = &ws16c48_rd_table,
73 .volatile_table = &ws16c48_volatile_table,
74 .cache_type = REGCACHE_FLAT,
75 .use_raw_spinlock = true,
76};
77
78#define WS16C48_NGPIO_PER_REG 8
79#define WS16C48_REGMAP_IRQ(_id) \
80 [_id] = { \
81 .reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
82 .mask = BIT((_id) % WS16C48_NGPIO_PER_REG), \
83 .type = { \
84 .type_reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
85 .types_supported = IRQ_TYPE_EDGE_BOTH, \
86 }, \
87 }
88
89/* Only the first 24 lines (Port 0-2) support interrupts */
90#define WS16C48_NUM_IRQS 24
91static const struct regmap_irq ws16c48_regmap_irqs[WS16C48_NUM_IRQS] = {
92 WS16C48_REGMAP_IRQ(0), WS16C48_REGMAP_IRQ(1), WS16C48_REGMAP_IRQ(2), /* 0-2 */
93 WS16C48_REGMAP_IRQ(3), WS16C48_REGMAP_IRQ(4), WS16C48_REGMAP_IRQ(5), /* 3-5 */
94 WS16C48_REGMAP_IRQ(6), WS16C48_REGMAP_IRQ(7), WS16C48_REGMAP_IRQ(8), /* 6-8 */
95 WS16C48_REGMAP_IRQ(9), WS16C48_REGMAP_IRQ(10), WS16C48_REGMAP_IRQ(11), /* 9-11 */
96 WS16C48_REGMAP_IRQ(12), WS16C48_REGMAP_IRQ(13), WS16C48_REGMAP_IRQ(14), /* 12-14 */
97 WS16C48_REGMAP_IRQ(15), WS16C48_REGMAP_IRQ(16), WS16C48_REGMAP_IRQ(17), /* 15-17 */
98 WS16C48_REGMAP_IRQ(18), WS16C48_REGMAP_IRQ(19), WS16C48_REGMAP_IRQ(20), /* 18-20 */
99 WS16C48_REGMAP_IRQ(21), WS16C48_REGMAP_IRQ(22), WS16C48_REGMAP_IRQ(23), /* 21-23 */
100};
101
102/**
103 * struct ws16c48_gpio - GPIO device private data structure
104 * @map: regmap for the device
105 * @lock: synchronization lock to prevent I/O race conditions
106 * @irq_mask: I/O bits affected by interrupts
107 */
108struct ws16c48_gpio {
109 struct regmap *map;
110 raw_spinlock_t lock;
111 u8 irq_mask[WS16C48_NUM_IRQS / WS16C48_NGPIO_PER_REG];
112};
113
114static int ws16c48_handle_pre_irq(void *const irq_drv_data) __acquires(&ws16c48gpio->lock)
115{
116 struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
117
118 /* Lock to prevent Page/Lock register change while we handle IRQ */
119 raw_spin_lock(&ws16c48gpio->lock);
120
121 return 0;
122}
123
124static int ws16c48_handle_post_irq(void *const irq_drv_data) __releases(&ws16c48gpio->lock)
125{
126 struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
127
128 raw_spin_unlock(&ws16c48gpio->lock);
129
130 return 0;
131}
132
133static int ws16c48_handle_mask_sync(const int index, const unsigned int mask_buf_def,
134 const unsigned int mask_buf, void *const irq_drv_data)
135{
136 struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
137 unsigned long flags;
138 int ret = 0;
139
140 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
141
142 /* exit early if no change since the last mask sync */
143 if (mask_buf == ws16c48gpio->irq_mask[index])
144 goto exit_unlock;
145 ws16c48gpio->irq_mask[index] = mask_buf;
146
147 ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, ENAB_PAGE);
148 if (ret)
149 goto exit_unlock;
150
151 /* Update ENAB register (inverted mask) */
152 ret = regmap_write(ws16c48gpio->map, WS16C48_ENAB + index, ~mask_buf);
153 if (ret)
154 goto exit_unlock;
155
156 ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
157 if (ret)
158 goto exit_unlock;
159
160exit_unlock:
161 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
162
163 return ret;
164}
165
166static int ws16c48_set_type_config(unsigned int **const buf, const unsigned int type,
167 const struct regmap_irq *const irq_data, const int idx,
168 void *const irq_drv_data)
169{
170 struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
171 unsigned int polarity;
172 unsigned long flags;
173 int ret;
174
175 switch (type) {
176 case IRQ_TYPE_EDGE_RISING:
177 polarity = irq_data->mask;
178 break;
179 case IRQ_TYPE_EDGE_FALLING:
180 polarity = 0;
181 break;
182 default:
183 return -EINVAL;
184 }
185
186 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
187
188 ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, POL_PAGE);
189 if (ret)
190 goto exit_unlock;
191
192 /* Set interrupt polarity */
193 ret = regmap_update_bits(ws16c48gpio->map, WS16C48_POL + idx, irq_data->mask, polarity);
194 if (ret)
195 goto exit_unlock;
196
197 ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
198 if (ret)
199 goto exit_unlock;
200
201exit_unlock:
202 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
203
204 return ret;
205}
206
207#define WS16C48_NGPIO 48
208static const char *ws16c48_names[WS16C48_NGPIO] = {
209 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
210 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
211 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
212 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
213 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
214 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
215 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
216 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
217 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
218 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
219 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
220 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
221};
222
223static int ws16c48_irq_init_hw(struct regmap *const map)
224{
225 int err;
226
227 err = regmap_write(map, WS16C48_PAGE_LOCK, ENAB_PAGE);
228 if (err)
229 return err;
230
231 /* Disable interrupts for all lines */
232 err = regmap_write(map, WS16C48_ENAB + 0, 0x00);
233 if (err)
234 return err;
235 err = regmap_write(map, WS16C48_ENAB + 1, 0x00);
236 if (err)
237 return err;
238 err = regmap_write(map, WS16C48_ENAB + 2, 0x00);
239 if (err)
240 return err;
241
242 return regmap_write(map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
243}
244
245static int ws16c48_probe(struct device *dev, unsigned int id)
246{
247 struct ws16c48_gpio *ws16c48gpio;
248 const char *const name = dev_name(dev);
249 int err;
250 struct gpio_regmap_config gpio_config = {};
251 void __iomem *regs;
252 struct regmap_irq_chip *chip;
253 struct regmap_irq_chip_data *chip_data;
254
255 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
256 if (!ws16c48gpio)
257 return -ENOMEM;
258
259 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
260 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
261 base[id], base[id] + WS16C48_EXTENT);
262 return -EBUSY;
263 }
264
265 regs = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
266 if (!regs)
267 return -ENOMEM;
268
269 ws16c48gpio->map = devm_regmap_init_mmio(dev, regs, &ws16c48_regmap_config);
270 if (IS_ERR(ws16c48gpio->map))
271 return dev_err_probe(dev, PTR_ERR(ws16c48gpio->map),
272 "Unable to initialize register map\n");
273
274 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
275 if (!chip)
276 return -ENOMEM;
277
278 chip->name = name;
279 chip->status_base = WS16C48_INT_ID;
280 chip->mask_base = WS16C48_ENAB;
281 chip->ack_base = WS16C48_INT_ID;
282 chip->num_regs = 3;
283 chip->irqs = ws16c48_regmap_irqs;
284 chip->num_irqs = ARRAY_SIZE(ws16c48_regmap_irqs);
285 chip->handle_pre_irq = ws16c48_handle_pre_irq;
286 chip->handle_post_irq = ws16c48_handle_post_irq;
287 chip->handle_mask_sync = ws16c48_handle_mask_sync;
288 chip->set_type_config = ws16c48_set_type_config;
289 chip->irq_drv_data = ws16c48gpio;
290
291 raw_spin_lock_init(&ws16c48gpio->lock);
292
293 /* Initialize to prevent spurious interrupts before we're ready */
294 err = ws16c48_irq_init_hw(ws16c48gpio->map);
295 if (err)
296 return err;
297
298 err = devm_regmap_add_irq_chip(dev, ws16c48gpio->map, irq[id], 0, 0, chip, &chip_data);
299 if (err)
300 return dev_err_probe(dev, err, "IRQ registration failed\n");
301
302 gpio_config.parent = dev;
303 gpio_config.regmap = ws16c48gpio->map;
304 gpio_config.ngpio = WS16C48_NGPIO;
305 gpio_config.names = ws16c48_names;
306 gpio_config.reg_dat_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
307 gpio_config.reg_set_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
308 /* Setting a GPIO to 0 allows it to be used as an input */
309 gpio_config.reg_dir_out_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
310 gpio_config.ngpio_per_reg = WS16C48_NGPIO_PER_REG;
311 gpio_config.irq_domain = regmap_irq_get_domain(chip_data);
312
313 return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config));
314}
315
316static struct isa_driver ws16c48_driver = {
317 .probe = ws16c48_probe,
318 .driver = {
319 .name = "ws16c48"
320 },
321};
322
323module_isa_driver_with_irq(ws16c48_driver, num_ws16c48, num_irq);
324
325MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
326MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
327MODULE_LICENSE("GPL v2");
1/*
2 * GPIO driver for the WinSystems WS16C48
3 * Copyright (C) 2016 William Breathitt Gray
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 */
14#include <linux/bitops.h>
15#include <linux/device.h>
16#include <linux/errno.h>
17#include <linux/gpio/driver.h>
18#include <linux/io.h>
19#include <linux/ioport.h>
20#include <linux/interrupt.h>
21#include <linux/irqdesc.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/platform_device.h>
26#include <linux/spinlock.h>
27
28static unsigned ws16c48_base;
29module_param(ws16c48_base, uint, 0);
30MODULE_PARM_DESC(ws16c48_base, "WinSystems WS16C48 base address");
31static unsigned ws16c48_irq;
32module_param(ws16c48_irq, uint, 0);
33MODULE_PARM_DESC(ws16c48_irq, "WinSystems WS16C48 interrupt line number");
34
35/**
36 * struct ws16c48_gpio - GPIO device private data structure
37 * @chip: instance of the gpio_chip
38 * @io_state: bit I/O state (whether bit is set to input or output)
39 * @out_state: output bits state
40 * @lock: synchronization lock to prevent I/O race conditions
41 * @irq_mask: I/O bits affected by interrupts
42 * @flow_mask: IRQ flow type mask for the respective I/O bits
43 * @base: base port address of the GPIO device
44 * @irq: Interrupt line number
45 */
46struct ws16c48_gpio {
47 struct gpio_chip chip;
48 unsigned char io_state[6];
49 unsigned char out_state[6];
50 spinlock_t lock;
51 unsigned long irq_mask;
52 unsigned long flow_mask;
53 unsigned base;
54 unsigned irq;
55};
56
57static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
58{
59 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
60 const unsigned port = offset / 8;
61 const unsigned mask = BIT(offset % 8);
62
63 return !!(ws16c48gpio->io_state[port] & mask);
64}
65
66static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
67{
68 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
69 const unsigned port = offset / 8;
70 const unsigned mask = BIT(offset % 8);
71 unsigned long flags;
72
73 spin_lock_irqsave(&ws16c48gpio->lock, flags);
74
75 ws16c48gpio->io_state[port] |= mask;
76 ws16c48gpio->out_state[port] &= ~mask;
77 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
78
79 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
80
81 return 0;
82}
83
84static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
85 unsigned offset, int value)
86{
87 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
88 const unsigned port = offset / 8;
89 const unsigned mask = BIT(offset % 8);
90 unsigned long flags;
91
92 spin_lock_irqsave(&ws16c48gpio->lock, flags);
93
94 ws16c48gpio->io_state[port] &= ~mask;
95 if (value)
96 ws16c48gpio->out_state[port] |= mask;
97 else
98 ws16c48gpio->out_state[port] &= ~mask;
99 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
100
101 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
102
103 return 0;
104}
105
106static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
107{
108 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
109 const unsigned port = offset / 8;
110 const unsigned mask = BIT(offset % 8);
111 unsigned long flags;
112 unsigned port_state;
113
114 spin_lock_irqsave(&ws16c48gpio->lock, flags);
115
116 /* ensure that GPIO is set for input */
117 if (!(ws16c48gpio->io_state[port] & mask)) {
118 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
119 return -EINVAL;
120 }
121
122 port_state = inb(ws16c48gpio->base + port);
123
124 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
125
126 return !!(port_state & mask);
127}
128
129static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
130{
131 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
132 const unsigned port = offset / 8;
133 const unsigned mask = BIT(offset % 8);
134 unsigned long flags;
135
136 spin_lock_irqsave(&ws16c48gpio->lock, flags);
137
138 /* ensure that GPIO is set for output */
139 if (ws16c48gpio->io_state[port] & mask) {
140 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
141 return;
142 }
143
144 if (value)
145 ws16c48gpio->out_state[port] |= mask;
146 else
147 ws16c48gpio->out_state[port] &= ~mask;
148 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
149
150 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
151}
152
153static void ws16c48_irq_ack(struct irq_data *data)
154{
155 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
156 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
157 const unsigned long offset = irqd_to_hwirq(data);
158 const unsigned port = offset / 8;
159 const unsigned mask = BIT(offset % 8);
160 unsigned long flags;
161 unsigned port_state;
162
163 /* only the first 3 ports support interrupts */
164 if (port > 2)
165 return;
166
167 spin_lock_irqsave(&ws16c48gpio->lock, flags);
168
169 port_state = ws16c48gpio->irq_mask >> (8*port);
170
171 outb(0x80, ws16c48gpio->base + 7);
172 outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
173 outb(port_state | mask, ws16c48gpio->base + 8 + port);
174 outb(0xC0, ws16c48gpio->base + 7);
175
176 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
177}
178
179static void ws16c48_irq_mask(struct irq_data *data)
180{
181 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
182 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
183 const unsigned long offset = irqd_to_hwirq(data);
184 const unsigned long mask = BIT(offset);
185 const unsigned port = offset / 8;
186 unsigned long flags;
187
188 /* only the first 3 ports support interrupts */
189 if (port > 2)
190 return;
191
192 spin_lock_irqsave(&ws16c48gpio->lock, flags);
193
194 ws16c48gpio->irq_mask &= ~mask;
195
196 outb(0x80, ws16c48gpio->base + 7);
197 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
198 outb(0xC0, ws16c48gpio->base + 7);
199
200 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
201}
202
203static void ws16c48_irq_unmask(struct irq_data *data)
204{
205 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
206 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
207 const unsigned long offset = irqd_to_hwirq(data);
208 const unsigned long mask = BIT(offset);
209 const unsigned port = offset / 8;
210 unsigned long flags;
211
212 /* only the first 3 ports support interrupts */
213 if (port > 2)
214 return;
215
216 spin_lock_irqsave(&ws16c48gpio->lock, flags);
217
218 ws16c48gpio->irq_mask |= mask;
219
220 outb(0x80, ws16c48gpio->base + 7);
221 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
222 outb(0xC0, ws16c48gpio->base + 7);
223
224 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
225}
226
227static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
228{
229 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
230 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
231 const unsigned long offset = irqd_to_hwirq(data);
232 const unsigned long mask = BIT(offset);
233 const unsigned port = offset / 8;
234 unsigned long flags;
235
236 /* only the first 3 ports support interrupts */
237 if (port > 2)
238 return -EINVAL;
239
240 spin_lock_irqsave(&ws16c48gpio->lock, flags);
241
242 switch (flow_type) {
243 case IRQ_TYPE_NONE:
244 break;
245 case IRQ_TYPE_EDGE_RISING:
246 ws16c48gpio->flow_mask |= mask;
247 break;
248 case IRQ_TYPE_EDGE_FALLING:
249 ws16c48gpio->flow_mask &= ~mask;
250 break;
251 default:
252 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
253 return -EINVAL;
254 }
255
256 outb(0x40, ws16c48gpio->base + 7);
257 outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
258 outb(0xC0, ws16c48gpio->base + 7);
259
260 spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
261
262 return 0;
263}
264
265static struct irq_chip ws16c48_irqchip = {
266 .name = "ws16c48",
267 .irq_ack = ws16c48_irq_ack,
268 .irq_mask = ws16c48_irq_mask,
269 .irq_unmask = ws16c48_irq_unmask,
270 .irq_set_type = ws16c48_irq_set_type
271};
272
273static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
274{
275 struct ws16c48_gpio *const ws16c48gpio = dev_id;
276 struct gpio_chip *const chip = &ws16c48gpio->chip;
277 unsigned long int_pending;
278 unsigned long port;
279 unsigned long int_id;
280 unsigned long gpio;
281
282 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
283 if (!int_pending)
284 return IRQ_NONE;
285
286 /* loop until all pending interrupts are handled */
287 do {
288 for_each_set_bit(port, &int_pending, 3) {
289 int_id = inb(ws16c48gpio->base + 8 + port);
290 for_each_set_bit(gpio, &int_id, 8)
291 generic_handle_irq(irq_find_mapping(
292 chip->irqdomain, gpio + 8*port));
293 }
294
295 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
296 } while (int_pending);
297
298 return IRQ_HANDLED;
299}
300
301static int __init ws16c48_probe(struct platform_device *pdev)
302{
303 struct device *dev = &pdev->dev;
304 struct ws16c48_gpio *ws16c48gpio;
305 const unsigned base = ws16c48_base;
306 const unsigned extent = 16;
307 const char *const name = dev_name(dev);
308 int err;
309 const unsigned irq = ws16c48_irq;
310
311 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
312 if (!ws16c48gpio)
313 return -ENOMEM;
314
315 if (!devm_request_region(dev, base, extent, name)) {
316 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
317 base, base + extent);
318 return -EBUSY;
319 }
320
321 ws16c48gpio->chip.label = name;
322 ws16c48gpio->chip.parent = dev;
323 ws16c48gpio->chip.owner = THIS_MODULE;
324 ws16c48gpio->chip.base = -1;
325 ws16c48gpio->chip.ngpio = 48;
326 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
327 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
328 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
329 ws16c48gpio->chip.get = ws16c48_gpio_get;
330 ws16c48gpio->chip.set = ws16c48_gpio_set;
331 ws16c48gpio->base = base;
332 ws16c48gpio->irq = irq;
333
334 spin_lock_init(&ws16c48gpio->lock);
335
336 dev_set_drvdata(dev, ws16c48gpio);
337
338 err = gpiochip_add_data(&ws16c48gpio->chip, ws16c48gpio);
339 if (err) {
340 dev_err(dev, "GPIO registering failed (%d)\n", err);
341 return err;
342 }
343
344 /* Disable IRQ by default */
345 outb(0x80, base + 7);
346 outb(0, base + 8);
347 outb(0, base + 9);
348 outb(0, base + 10);
349 outb(0xC0, base + 7);
350
351 err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
352 handle_edge_irq, IRQ_TYPE_NONE);
353 if (err) {
354 dev_err(dev, "Could not add irqchip (%d)\n", err);
355 goto err_gpiochip_remove;
356 }
357
358 err = request_irq(irq, ws16c48_irq_handler, IRQF_SHARED, name,
359 ws16c48gpio);
360 if (err) {
361 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
362 goto err_gpiochip_remove;
363 }
364
365 return 0;
366
367err_gpiochip_remove:
368 gpiochip_remove(&ws16c48gpio->chip);
369 return err;
370}
371
372static int ws16c48_remove(struct platform_device *pdev)
373{
374 struct ws16c48_gpio *const ws16c48gpio = platform_get_drvdata(pdev);
375
376 free_irq(ws16c48gpio->irq, ws16c48gpio);
377 gpiochip_remove(&ws16c48gpio->chip);
378
379 return 0;
380}
381
382static struct platform_device *ws16c48_device;
383
384static struct platform_driver ws16c48_driver = {
385 .driver = {
386 .name = "ws16c48"
387 },
388 .remove = ws16c48_remove
389};
390
391static void __exit ws16c48_exit(void)
392{
393 platform_device_unregister(ws16c48_device);
394 platform_driver_unregister(&ws16c48_driver);
395}
396
397static int __init ws16c48_init(void)
398{
399 int err;
400
401 ws16c48_device = platform_device_alloc(ws16c48_driver.driver.name, -1);
402 if (!ws16c48_device)
403 return -ENOMEM;
404
405 err = platform_device_add(ws16c48_device);
406 if (err)
407 goto err_platform_device;
408
409 err = platform_driver_probe(&ws16c48_driver, ws16c48_probe);
410 if (err)
411 goto err_platform_driver;
412
413 return 0;
414
415err_platform_driver:
416 platform_device_del(ws16c48_device);
417err_platform_device:
418 platform_device_put(ws16c48_device);
419 return err;
420}
421
422module_init(ws16c48_init);
423module_exit(ws16c48_exit);
424
425MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
426MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
427MODULE_LICENSE("GPL v2");