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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GPIO driver for the WinSystems WS16C48
4 * Copyright (C) 2016 William Breathitt Gray
5 */
6#include <linux/bitfield.h>
7#include <linux/bits.h>
8#include <linux/device.h>
9#include <linux/err.h>
10#include <linux/gpio/regmap.h>
11#include <linux/irq.h>
12#include <linux/isa.h>
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/spinlock.h>
17#include <linux/regmap.h>
18#include <linux/types.h>
19
20#define WS16C48_EXTENT 11
21#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
22
23static unsigned int base[MAX_NUM_WS16C48];
24static unsigned int num_ws16c48;
25module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
26MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
27
28static unsigned int irq[MAX_NUM_WS16C48];
29static unsigned int num_irq;
30module_param_hw_array(irq, uint, irq, &num_irq, 0);
31MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
32
33#define WS16C48_DAT_BASE 0x0
34#define WS16C48_PAGE_LOCK 0x7
35#define WS16C48_PAGE_BASE 0x8
36#define WS16C48_POL WS16C48_PAGE_BASE
37#define WS16C48_ENAB WS16C48_PAGE_BASE
38#define WS16C48_INT_ID WS16C48_PAGE_BASE
39
40#define PAGE_LOCK_PAGE_FIELD GENMASK(7, 6)
41#define POL_PAGE u8_encode_bits(1, PAGE_LOCK_PAGE_FIELD)
42#define ENAB_PAGE u8_encode_bits(2, PAGE_LOCK_PAGE_FIELD)
43#define INT_ID_PAGE u8_encode_bits(3, PAGE_LOCK_PAGE_FIELD)
44
45static const struct regmap_range ws16c48_wr_ranges[] = {
46 regmap_reg_range(0x0, 0x5), regmap_reg_range(0x7, 0xA),
47};
48static const struct regmap_range ws16c48_rd_ranges[] = {
49 regmap_reg_range(0x0, 0xA),
50};
51static const struct regmap_range ws16c48_volatile_ranges[] = {
52 regmap_reg_range(0x0, 0x6), regmap_reg_range(0x8, 0xA),
53};
54static const struct regmap_access_table ws16c48_wr_table = {
55 .yes_ranges = ws16c48_wr_ranges,
56 .n_yes_ranges = ARRAY_SIZE(ws16c48_wr_ranges),
57};
58static const struct regmap_access_table ws16c48_rd_table = {
59 .yes_ranges = ws16c48_rd_ranges,
60 .n_yes_ranges = ARRAY_SIZE(ws16c48_rd_ranges),
61};
62static const struct regmap_access_table ws16c48_volatile_table = {
63 .yes_ranges = ws16c48_volatile_ranges,
64 .n_yes_ranges = ARRAY_SIZE(ws16c48_volatile_ranges),
65};
66static const struct regmap_config ws16c48_regmap_config = {
67 .reg_bits = 8,
68 .reg_stride = 1,
69 .val_bits = 8,
70 .io_port = true,
71 .wr_table = &ws16c48_wr_table,
72 .rd_table = &ws16c48_rd_table,
73 .volatile_table = &ws16c48_volatile_table,
74 .cache_type = REGCACHE_FLAT,
75 .use_raw_spinlock = true,
76};
77
78#define WS16C48_NGPIO_PER_REG 8
79#define WS16C48_REGMAP_IRQ(_id) \
80 [_id] = { \
81 .reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
82 .mask = BIT((_id) % WS16C48_NGPIO_PER_REG), \
83 .type = { \
84 .type_reg_offset = (_id) / WS16C48_NGPIO_PER_REG, \
85 .types_supported = IRQ_TYPE_EDGE_BOTH, \
86 }, \
87 }
88
89/* Only the first 24 lines (Port 0-2) support interrupts */
90#define WS16C48_NUM_IRQS 24
91static const struct regmap_irq ws16c48_regmap_irqs[WS16C48_NUM_IRQS] = {
92 WS16C48_REGMAP_IRQ(0), WS16C48_REGMAP_IRQ(1), WS16C48_REGMAP_IRQ(2), /* 0-2 */
93 WS16C48_REGMAP_IRQ(3), WS16C48_REGMAP_IRQ(4), WS16C48_REGMAP_IRQ(5), /* 3-5 */
94 WS16C48_REGMAP_IRQ(6), WS16C48_REGMAP_IRQ(7), WS16C48_REGMAP_IRQ(8), /* 6-8 */
95 WS16C48_REGMAP_IRQ(9), WS16C48_REGMAP_IRQ(10), WS16C48_REGMAP_IRQ(11), /* 9-11 */
96 WS16C48_REGMAP_IRQ(12), WS16C48_REGMAP_IRQ(13), WS16C48_REGMAP_IRQ(14), /* 12-14 */
97 WS16C48_REGMAP_IRQ(15), WS16C48_REGMAP_IRQ(16), WS16C48_REGMAP_IRQ(17), /* 15-17 */
98 WS16C48_REGMAP_IRQ(18), WS16C48_REGMAP_IRQ(19), WS16C48_REGMAP_IRQ(20), /* 18-20 */
99 WS16C48_REGMAP_IRQ(21), WS16C48_REGMAP_IRQ(22), WS16C48_REGMAP_IRQ(23), /* 21-23 */
100};
101
102/**
103 * struct ws16c48_gpio - GPIO device private data structure
104 * @map: regmap for the device
105 * @lock: synchronization lock to prevent I/O race conditions
106 * @irq_mask: I/O bits affected by interrupts
107 */
108struct ws16c48_gpio {
109 struct regmap *map;
110 raw_spinlock_t lock;
111 u8 irq_mask[WS16C48_NUM_IRQS / WS16C48_NGPIO_PER_REG];
112};
113
114static int ws16c48_handle_pre_irq(void *const irq_drv_data) __acquires(&ws16c48gpio->lock)
115{
116 struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
117
118 /* Lock to prevent Page/Lock register change while we handle IRQ */
119 raw_spin_lock(&ws16c48gpio->lock);
120
121 return 0;
122}
123
124static int ws16c48_handle_post_irq(void *const irq_drv_data) __releases(&ws16c48gpio->lock)
125{
126 struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
127
128 raw_spin_unlock(&ws16c48gpio->lock);
129
130 return 0;
131}
132
133static int ws16c48_handle_mask_sync(const int index, const unsigned int mask_buf_def,
134 const unsigned int mask_buf, void *const irq_drv_data)
135{
136 struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
137 unsigned long flags;
138 int ret = 0;
139
140 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
141
142 /* exit early if no change since the last mask sync */
143 if (mask_buf == ws16c48gpio->irq_mask[index])
144 goto exit_unlock;
145 ws16c48gpio->irq_mask[index] = mask_buf;
146
147 ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, ENAB_PAGE);
148 if (ret)
149 goto exit_unlock;
150
151 /* Update ENAB register (inverted mask) */
152 ret = regmap_write(ws16c48gpio->map, WS16C48_ENAB + index, ~mask_buf);
153 if (ret)
154 goto exit_unlock;
155
156 ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
157 if (ret)
158 goto exit_unlock;
159
160exit_unlock:
161 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
162
163 return ret;
164}
165
166static int ws16c48_set_type_config(unsigned int **const buf, const unsigned int type,
167 const struct regmap_irq *const irq_data, const int idx,
168 void *const irq_drv_data)
169{
170 struct ws16c48_gpio *const ws16c48gpio = irq_drv_data;
171 unsigned int polarity;
172 unsigned long flags;
173 int ret;
174
175 switch (type) {
176 case IRQ_TYPE_EDGE_RISING:
177 polarity = irq_data->mask;
178 break;
179 case IRQ_TYPE_EDGE_FALLING:
180 polarity = 0;
181 break;
182 default:
183 return -EINVAL;
184 }
185
186 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
187
188 ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, POL_PAGE);
189 if (ret)
190 goto exit_unlock;
191
192 /* Set interrupt polarity */
193 ret = regmap_update_bits(ws16c48gpio->map, WS16C48_POL + idx, irq_data->mask, polarity);
194 if (ret)
195 goto exit_unlock;
196
197 ret = regmap_write(ws16c48gpio->map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
198 if (ret)
199 goto exit_unlock;
200
201exit_unlock:
202 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
203
204 return ret;
205}
206
207#define WS16C48_NGPIO 48
208static const char *ws16c48_names[WS16C48_NGPIO] = {
209 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
210 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
211 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
212 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
213 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
214 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
215 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
216 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
217 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
218 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
219 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
220 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
221};
222
223static int ws16c48_irq_init_hw(struct regmap *const map)
224{
225 int err;
226
227 err = regmap_write(map, WS16C48_PAGE_LOCK, ENAB_PAGE);
228 if (err)
229 return err;
230
231 /* Disable interrupts for all lines */
232 err = regmap_write(map, WS16C48_ENAB + 0, 0x00);
233 if (err)
234 return err;
235 err = regmap_write(map, WS16C48_ENAB + 1, 0x00);
236 if (err)
237 return err;
238 err = regmap_write(map, WS16C48_ENAB + 2, 0x00);
239 if (err)
240 return err;
241
242 return regmap_write(map, WS16C48_PAGE_LOCK, INT_ID_PAGE);
243}
244
245static int ws16c48_probe(struct device *dev, unsigned int id)
246{
247 struct ws16c48_gpio *ws16c48gpio;
248 const char *const name = dev_name(dev);
249 int err;
250 struct gpio_regmap_config gpio_config = {};
251 void __iomem *regs;
252 struct regmap_irq_chip *chip;
253 struct regmap_irq_chip_data *chip_data;
254
255 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
256 if (!ws16c48gpio)
257 return -ENOMEM;
258
259 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
260 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
261 base[id], base[id] + WS16C48_EXTENT);
262 return -EBUSY;
263 }
264
265 regs = devm_ioport_map(dev, base[id], WS16C48_EXTENT);
266 if (!regs)
267 return -ENOMEM;
268
269 ws16c48gpio->map = devm_regmap_init_mmio(dev, regs, &ws16c48_regmap_config);
270 if (IS_ERR(ws16c48gpio->map))
271 return dev_err_probe(dev, PTR_ERR(ws16c48gpio->map),
272 "Unable to initialize register map\n");
273
274 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
275 if (!chip)
276 return -ENOMEM;
277
278 chip->name = name;
279 chip->status_base = WS16C48_INT_ID;
280 chip->mask_base = WS16C48_ENAB;
281 chip->ack_base = WS16C48_INT_ID;
282 chip->num_regs = 3;
283 chip->irqs = ws16c48_regmap_irqs;
284 chip->num_irqs = ARRAY_SIZE(ws16c48_regmap_irqs);
285 chip->handle_pre_irq = ws16c48_handle_pre_irq;
286 chip->handle_post_irq = ws16c48_handle_post_irq;
287 chip->handle_mask_sync = ws16c48_handle_mask_sync;
288 chip->set_type_config = ws16c48_set_type_config;
289 chip->irq_drv_data = ws16c48gpio;
290
291 raw_spin_lock_init(&ws16c48gpio->lock);
292
293 /* Initialize to prevent spurious interrupts before we're ready */
294 err = ws16c48_irq_init_hw(ws16c48gpio->map);
295 if (err)
296 return err;
297
298 err = devm_regmap_add_irq_chip(dev, ws16c48gpio->map, irq[id], 0, 0, chip, &chip_data);
299 if (err)
300 return dev_err_probe(dev, err, "IRQ registration failed\n");
301
302 gpio_config.parent = dev;
303 gpio_config.regmap = ws16c48gpio->map;
304 gpio_config.ngpio = WS16C48_NGPIO;
305 gpio_config.names = ws16c48_names;
306 gpio_config.reg_dat_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
307 gpio_config.reg_set_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
308 /* Setting a GPIO to 0 allows it to be used as an input */
309 gpio_config.reg_dir_out_base = GPIO_REGMAP_ADDR(WS16C48_DAT_BASE);
310 gpio_config.ngpio_per_reg = WS16C48_NGPIO_PER_REG;
311 gpio_config.irq_domain = regmap_irq_get_domain(chip_data);
312
313 return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpio_config));
314}
315
316static struct isa_driver ws16c48_driver = {
317 .probe = ws16c48_probe,
318 .driver = {
319 .name = "ws16c48"
320 },
321};
322
323module_isa_driver_with_irq(ws16c48_driver, num_ws16c48, num_irq);
324
325MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
326MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
327MODULE_LICENSE("GPL v2");
1/*
2 * GPIO driver for the WinSystems WS16C48
3 * Copyright (C) 2016 William Breathitt Gray
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 */
14#include <linux/bitmap.h>
15#include <linux/bitops.h>
16#include <linux/device.h>
17#include <linux/errno.h>
18#include <linux/gpio/driver.h>
19#include <linux/io.h>
20#include <linux/ioport.h>
21#include <linux/interrupt.h>
22#include <linux/irqdesc.h>
23#include <linux/isa.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/spinlock.h>
28
29#define WS16C48_EXTENT 16
30#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
31
32static unsigned int base[MAX_NUM_WS16C48];
33static unsigned int num_ws16c48;
34module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
35MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
36
37static unsigned int irq[MAX_NUM_WS16C48];
38module_param_hw_array(irq, uint, irq, NULL, 0);
39MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
40
41/**
42 * struct ws16c48_gpio - GPIO device private data structure
43 * @chip: instance of the gpio_chip
44 * @io_state: bit I/O state (whether bit is set to input or output)
45 * @out_state: output bits state
46 * @lock: synchronization lock to prevent I/O race conditions
47 * @irq_mask: I/O bits affected by interrupts
48 * @flow_mask: IRQ flow type mask for the respective I/O bits
49 * @base: base port address of the GPIO device
50 */
51struct ws16c48_gpio {
52 struct gpio_chip chip;
53 unsigned char io_state[6];
54 unsigned char out_state[6];
55 raw_spinlock_t lock;
56 unsigned long irq_mask;
57 unsigned long flow_mask;
58 unsigned base;
59};
60
61static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
62{
63 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
64 const unsigned port = offset / 8;
65 const unsigned mask = BIT(offset % 8);
66
67 return !!(ws16c48gpio->io_state[port] & mask);
68}
69
70static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
71{
72 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
73 const unsigned port = offset / 8;
74 const unsigned mask = BIT(offset % 8);
75 unsigned long flags;
76
77 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
78
79 ws16c48gpio->io_state[port] |= mask;
80 ws16c48gpio->out_state[port] &= ~mask;
81 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
82
83 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
84
85 return 0;
86}
87
88static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
89 unsigned offset, int value)
90{
91 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
92 const unsigned port = offset / 8;
93 const unsigned mask = BIT(offset % 8);
94 unsigned long flags;
95
96 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
97
98 ws16c48gpio->io_state[port] &= ~mask;
99 if (value)
100 ws16c48gpio->out_state[port] |= mask;
101 else
102 ws16c48gpio->out_state[port] &= ~mask;
103 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
104
105 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
106
107 return 0;
108}
109
110static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
111{
112 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
113 const unsigned port = offset / 8;
114 const unsigned mask = BIT(offset % 8);
115 unsigned long flags;
116 unsigned port_state;
117
118 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
119
120 /* ensure that GPIO is set for input */
121 if (!(ws16c48gpio->io_state[port] & mask)) {
122 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
123 return -EINVAL;
124 }
125
126 port_state = inb(ws16c48gpio->base + port);
127
128 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
129
130 return !!(port_state & mask);
131}
132
133static int ws16c48_gpio_get_multiple(struct gpio_chip *chip,
134 unsigned long *mask, unsigned long *bits)
135{
136 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
137 const unsigned int gpio_reg_size = 8;
138 size_t i;
139 const size_t num_ports = chip->ngpio / gpio_reg_size;
140 unsigned int bits_offset;
141 size_t word_index;
142 unsigned int word_offset;
143 unsigned long word_mask;
144 const unsigned long port_mask = GENMASK(gpio_reg_size - 1, 0);
145 unsigned long port_state;
146
147 /* clear bits array to a clean slate */
148 bitmap_zero(bits, chip->ngpio);
149
150 /* get bits are evaluated a gpio port register at a time */
151 for (i = 0; i < num_ports; i++) {
152 /* gpio offset in bits array */
153 bits_offset = i * gpio_reg_size;
154
155 /* word index for bits array */
156 word_index = BIT_WORD(bits_offset);
157
158 /* gpio offset within current word of bits array */
159 word_offset = bits_offset % BITS_PER_LONG;
160
161 /* mask of get bits for current gpio within current word */
162 word_mask = mask[word_index] & (port_mask << word_offset);
163 if (!word_mask) {
164 /* no get bits in this port so skip to next one */
165 continue;
166 }
167
168 /* read bits from current gpio port */
169 port_state = inb(ws16c48gpio->base + i);
170
171 /* store acquired bits at respective bits array offset */
172 bits[word_index] |= port_state << word_offset;
173 }
174
175 return 0;
176}
177
178static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
179{
180 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
181 const unsigned port = offset / 8;
182 const unsigned mask = BIT(offset % 8);
183 unsigned long flags;
184
185 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
186
187 /* ensure that GPIO is set for output */
188 if (ws16c48gpio->io_state[port] & mask) {
189 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
190 return;
191 }
192
193 if (value)
194 ws16c48gpio->out_state[port] |= mask;
195 else
196 ws16c48gpio->out_state[port] &= ~mask;
197 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
198
199 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
200}
201
202static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
203 unsigned long *mask, unsigned long *bits)
204{
205 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
206 unsigned int i;
207 const unsigned int gpio_reg_size = 8;
208 unsigned int port;
209 unsigned int iomask;
210 unsigned int bitmask;
211 unsigned long flags;
212
213 /* set bits are evaluated a gpio register size at a time */
214 for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
215 /* no more set bits in this mask word; skip to the next word */
216 if (!mask[BIT_WORD(i)]) {
217 i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
218 continue;
219 }
220
221 port = i / gpio_reg_size;
222
223 /* mask out GPIO configured for input */
224 iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port];
225 bitmask = iomask & bits[BIT_WORD(i)];
226
227 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
228
229 /* update output state data and set device gpio register */
230 ws16c48gpio->out_state[port] &= ~iomask;
231 ws16c48gpio->out_state[port] |= bitmask;
232 outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
233
234 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
235
236 /* prepare for next gpio register set */
237 mask[BIT_WORD(i)] >>= gpio_reg_size;
238 bits[BIT_WORD(i)] >>= gpio_reg_size;
239 }
240}
241
242static void ws16c48_irq_ack(struct irq_data *data)
243{
244 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
245 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
246 const unsigned long offset = irqd_to_hwirq(data);
247 const unsigned port = offset / 8;
248 const unsigned mask = BIT(offset % 8);
249 unsigned long flags;
250 unsigned port_state;
251
252 /* only the first 3 ports support interrupts */
253 if (port > 2)
254 return;
255
256 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
257
258 port_state = ws16c48gpio->irq_mask >> (8*port);
259
260 outb(0x80, ws16c48gpio->base + 7);
261 outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
262 outb(port_state | mask, ws16c48gpio->base + 8 + port);
263 outb(0xC0, ws16c48gpio->base + 7);
264
265 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
266}
267
268static void ws16c48_irq_mask(struct irq_data *data)
269{
270 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
271 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
272 const unsigned long offset = irqd_to_hwirq(data);
273 const unsigned long mask = BIT(offset);
274 const unsigned port = offset / 8;
275 unsigned long flags;
276
277 /* only the first 3 ports support interrupts */
278 if (port > 2)
279 return;
280
281 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
282
283 ws16c48gpio->irq_mask &= ~mask;
284
285 outb(0x80, ws16c48gpio->base + 7);
286 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
287 outb(0xC0, ws16c48gpio->base + 7);
288
289 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
290}
291
292static void ws16c48_irq_unmask(struct irq_data *data)
293{
294 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
295 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
296 const unsigned long offset = irqd_to_hwirq(data);
297 const unsigned long mask = BIT(offset);
298 const unsigned port = offset / 8;
299 unsigned long flags;
300
301 /* only the first 3 ports support interrupts */
302 if (port > 2)
303 return;
304
305 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
306
307 ws16c48gpio->irq_mask |= mask;
308
309 outb(0x80, ws16c48gpio->base + 7);
310 outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
311 outb(0xC0, ws16c48gpio->base + 7);
312
313 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
314}
315
316static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
317{
318 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
319 struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
320 const unsigned long offset = irqd_to_hwirq(data);
321 const unsigned long mask = BIT(offset);
322 const unsigned port = offset / 8;
323 unsigned long flags;
324
325 /* only the first 3 ports support interrupts */
326 if (port > 2)
327 return -EINVAL;
328
329 raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
330
331 switch (flow_type) {
332 case IRQ_TYPE_NONE:
333 break;
334 case IRQ_TYPE_EDGE_RISING:
335 ws16c48gpio->flow_mask |= mask;
336 break;
337 case IRQ_TYPE_EDGE_FALLING:
338 ws16c48gpio->flow_mask &= ~mask;
339 break;
340 default:
341 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
342 return -EINVAL;
343 }
344
345 outb(0x40, ws16c48gpio->base + 7);
346 outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
347 outb(0xC0, ws16c48gpio->base + 7);
348
349 raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
350
351 return 0;
352}
353
354static struct irq_chip ws16c48_irqchip = {
355 .name = "ws16c48",
356 .irq_ack = ws16c48_irq_ack,
357 .irq_mask = ws16c48_irq_mask,
358 .irq_unmask = ws16c48_irq_unmask,
359 .irq_set_type = ws16c48_irq_set_type
360};
361
362static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
363{
364 struct ws16c48_gpio *const ws16c48gpio = dev_id;
365 struct gpio_chip *const chip = &ws16c48gpio->chip;
366 unsigned long int_pending;
367 unsigned long port;
368 unsigned long int_id;
369 unsigned long gpio;
370
371 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
372 if (!int_pending)
373 return IRQ_NONE;
374
375 /* loop until all pending interrupts are handled */
376 do {
377 for_each_set_bit(port, &int_pending, 3) {
378 int_id = inb(ws16c48gpio->base + 8 + port);
379 for_each_set_bit(gpio, &int_id, 8)
380 generic_handle_irq(irq_find_mapping(
381 chip->irq.domain, gpio + 8*port));
382 }
383
384 int_pending = inb(ws16c48gpio->base + 6) & 0x7;
385 } while (int_pending);
386
387 return IRQ_HANDLED;
388}
389
390#define WS16C48_NGPIO 48
391static const char *ws16c48_names[WS16C48_NGPIO] = {
392 "Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
393 "Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
394 "Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
395 "Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
396 "Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
397 "Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
398 "Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
399 "Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
400 "Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
401 "Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
402 "Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
403 "Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
404};
405
406static int ws16c48_probe(struct device *dev, unsigned int id)
407{
408 struct ws16c48_gpio *ws16c48gpio;
409 const char *const name = dev_name(dev);
410 int err;
411
412 ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
413 if (!ws16c48gpio)
414 return -ENOMEM;
415
416 if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
417 dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
418 base[id], base[id] + WS16C48_EXTENT);
419 return -EBUSY;
420 }
421
422 ws16c48gpio->chip.label = name;
423 ws16c48gpio->chip.parent = dev;
424 ws16c48gpio->chip.owner = THIS_MODULE;
425 ws16c48gpio->chip.base = -1;
426 ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
427 ws16c48gpio->chip.names = ws16c48_names;
428 ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
429 ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
430 ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
431 ws16c48gpio->chip.get = ws16c48_gpio_get;
432 ws16c48gpio->chip.get_multiple = ws16c48_gpio_get_multiple;
433 ws16c48gpio->chip.set = ws16c48_gpio_set;
434 ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
435 ws16c48gpio->base = base[id];
436
437 raw_spin_lock_init(&ws16c48gpio->lock);
438
439 err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
440 if (err) {
441 dev_err(dev, "GPIO registering failed (%d)\n", err);
442 return err;
443 }
444
445 /* Disable IRQ by default */
446 outb(0x80, base[id] + 7);
447 outb(0, base[id] + 8);
448 outb(0, base[id] + 9);
449 outb(0, base[id] + 10);
450 outb(0xC0, base[id] + 7);
451
452 err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
453 handle_edge_irq, IRQ_TYPE_NONE);
454 if (err) {
455 dev_err(dev, "Could not add irqchip (%d)\n", err);
456 return err;
457 }
458
459 err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
460 name, ws16c48gpio);
461 if (err) {
462 dev_err(dev, "IRQ handler registering failed (%d)\n", err);
463 return err;
464 }
465
466 return 0;
467}
468
469static struct isa_driver ws16c48_driver = {
470 .probe = ws16c48_probe,
471 .driver = {
472 .name = "ws16c48"
473 },
474};
475
476module_isa_driver(ws16c48_driver, num_ws16c48);
477
478MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
479MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
480MODULE_LICENSE("GPL v2");