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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * arch/sparc64/mm/init.c
4 *
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 */
8
9#include <linux/extable.h>
10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/memblock.h>
15#include <linux/mm.h>
16#include <linux/hugetlb.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/poison.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
23#include <linux/kprobes.h>
24#include <linux/cache.h>
25#include <linux/sort.h>
26#include <linux/ioport.h>
27#include <linux/percpu.h>
28#include <linux/mmzone.h>
29#include <linux/gfp.h>
30#include <linux/bootmem_info.h>
31
32#include <asm/head.h>
33#include <asm/page.h>
34#include <asm/pgalloc.h>
35#include <asm/oplib.h>
36#include <asm/iommu.h>
37#include <asm/io.h>
38#include <linux/uaccess.h>
39#include <asm/mmu_context.h>
40#include <asm/tlbflush.h>
41#include <asm/dma.h>
42#include <asm/starfire.h>
43#include <asm/tlb.h>
44#include <asm/spitfire.h>
45#include <asm/sections.h>
46#include <asm/tsb.h>
47#include <asm/hypervisor.h>
48#include <asm/prom.h>
49#include <asm/mdesc.h>
50#include <asm/cpudata.h>
51#include <asm/setup.h>
52#include <asm/irq.h>
53
54#include "init_64.h"
55
56unsigned long kern_linear_pte_xor[4] __read_mostly;
57static unsigned long page_cache4v_flag;
58
59/* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
64 *
65 * 0 ==> 4MB
66 * 1 ==> 256MB
67 * 2 ==> 2GB
68 * 3 ==> 16GB
69 *
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
74 *
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
78 */
79
80#ifndef CONFIG_DEBUG_PAGEALLOC
81/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
84 */
85extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
86#endif
87extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
88
89static unsigned long cpu_pgsz_mask;
90
91#define MAX_BANKS 1024
92
93static struct linux_prom64_registers pavail[MAX_BANKS];
94static int pavail_ents;
95
96u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
97
98static int cmp_p64(const void *a, const void *b)
99{
100 const struct linux_prom64_registers *x = a, *y = b;
101
102 if (x->phys_addr > y->phys_addr)
103 return 1;
104 if (x->phys_addr < y->phys_addr)
105 return -1;
106 return 0;
107}
108
109static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
111 int *num_ents)
112{
113 phandle node = prom_finddevice("/memory");
114 int prop_size = prom_getproplen(node, property);
115 int ents, ret, i;
116
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
122 prom_halt();
123 }
124
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
126 if (ret == -1) {
127 prom_printf("Couldn't get %s property from /memory.\n",
128 property);
129 prom_halt();
130 }
131
132 /* Sanitize what we got from the firmware, by page aligning
133 * everything.
134 */
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
137
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
140
141 size &= PAGE_MASK;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
144
145 size -= new_base - base;
146 if ((long) size < 0L)
147 size = 0UL;
148 base = new_base;
149 }
150 if (size == 0UL) {
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
154 */
155 memmove(®s[i], ®s[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
157 i--;
158 ents--;
159 continue;
160 }
161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
163 }
164
165 *num_ents = ents;
166
167 sort(regs, ents, sizeof(struct linux_prom64_registers),
168 cmp_p64, NULL);
169}
170
171/* Kernel physical address base and size in bytes. */
172unsigned long kern_base __read_mostly;
173unsigned long kern_size __read_mostly;
174
175/* Initial ramdisk setup */
176extern unsigned long sparc_ramdisk_image64;
177extern unsigned int sparc_ramdisk_image;
178extern unsigned int sparc_ramdisk_size;
179
180struct page *mem_map_zero __read_mostly;
181EXPORT_SYMBOL(mem_map_zero);
182
183unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
184
185unsigned long sparc64_kern_pri_context __read_mostly;
186unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187unsigned long sparc64_kern_sec_context __read_mostly;
188
189int num_kernel_image_mappings;
190
191#ifdef CONFIG_DEBUG_DCFLUSH
192atomic_t dcpage_flushes = ATOMIC_INIT(0);
193#ifdef CONFIG_SMP
194atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
195#endif
196#endif
197
198inline void flush_dcache_folio_impl(struct folio *folio)
199{
200 unsigned int i, nr = folio_nr_pages(folio);
201
202 BUG_ON(tlb_type == hypervisor);
203#ifdef CONFIG_DEBUG_DCFLUSH
204 atomic_inc(&dcpage_flushes);
205#endif
206
207#ifdef DCACHE_ALIASING_POSSIBLE
208 for (i = 0; i < nr; i++)
209 __flush_dcache_page(folio_address(folio) + i * PAGE_SIZE,
210 ((tlb_type == spitfire) &&
211 folio_flush_mapping(folio) != NULL));
212#else
213 if (folio_flush_mapping(folio) != NULL &&
214 tlb_type == spitfire) {
215 for (i = 0; i < nr; i++)
216 __flush_icache_page((pfn + i) * PAGE_SIZE);
217 }
218#endif
219}
220
221#define PG_dcache_dirty PG_arch_1
222#define PG_dcache_cpu_shift 32UL
223#define PG_dcache_cpu_mask \
224 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
225
226#define dcache_dirty_cpu(folio) \
227 (((folio)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
228
229static inline void set_dcache_dirty(struct folio *folio, int this_cpu)
230{
231 unsigned long mask = this_cpu;
232 unsigned long non_cpu_bits;
233
234 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
235 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
236
237 __asm__ __volatile__("1:\n\t"
238 "ldx [%2], %%g7\n\t"
239 "and %%g7, %1, %%g1\n\t"
240 "or %%g1, %0, %%g1\n\t"
241 "casx [%2], %%g7, %%g1\n\t"
242 "cmp %%g7, %%g1\n\t"
243 "bne,pn %%xcc, 1b\n\t"
244 " nop"
245 : /* no outputs */
246 : "r" (mask), "r" (non_cpu_bits), "r" (&folio->flags)
247 : "g1", "g7");
248}
249
250static inline void clear_dcache_dirty_cpu(struct folio *folio, unsigned long cpu)
251{
252 unsigned long mask = (1UL << PG_dcache_dirty);
253
254 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
255 "1:\n\t"
256 "ldx [%2], %%g7\n\t"
257 "srlx %%g7, %4, %%g1\n\t"
258 "and %%g1, %3, %%g1\n\t"
259 "cmp %%g1, %0\n\t"
260 "bne,pn %%icc, 2f\n\t"
261 " andn %%g7, %1, %%g1\n\t"
262 "casx [%2], %%g7, %%g1\n\t"
263 "cmp %%g7, %%g1\n\t"
264 "bne,pn %%xcc, 1b\n\t"
265 " nop\n"
266 "2:"
267 : /* no outputs */
268 : "r" (cpu), "r" (mask), "r" (&folio->flags),
269 "i" (PG_dcache_cpu_mask),
270 "i" (PG_dcache_cpu_shift)
271 : "g1", "g7");
272}
273
274static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
275{
276 unsigned long tsb_addr = (unsigned long) ent;
277
278 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
279 tsb_addr = __pa(tsb_addr);
280
281 __tsb_insert(tsb_addr, tag, pte);
282}
283
284unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
285
286static void flush_dcache(unsigned long pfn)
287{
288 struct page *page;
289
290 page = pfn_to_page(pfn);
291 if (page) {
292 struct folio *folio = page_folio(page);
293 unsigned long pg_flags;
294
295 pg_flags = folio->flags;
296 if (pg_flags & (1UL << PG_dcache_dirty)) {
297 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
298 PG_dcache_cpu_mask);
299 int this_cpu = get_cpu();
300
301 /* This is just to optimize away some function calls
302 * in the SMP case.
303 */
304 if (cpu == this_cpu)
305 flush_dcache_folio_impl(folio);
306 else
307 smp_flush_dcache_folio_impl(folio, cpu);
308
309 clear_dcache_dirty_cpu(folio, cpu);
310
311 put_cpu();
312 }
313 }
314}
315
316/* mm->context.lock must be held */
317static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
318 unsigned long tsb_hash_shift, unsigned long address,
319 unsigned long tte)
320{
321 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
322 unsigned long tag;
323
324 if (unlikely(!tsb))
325 return;
326
327 tsb += ((address >> tsb_hash_shift) &
328 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
329 tag = (address >> 22UL);
330 tsb_insert(tsb, tag, tte);
331}
332
333#ifdef CONFIG_HUGETLB_PAGE
334static int __init hugetlbpage_init(void)
335{
336 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT);
337 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
338 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT);
339 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT);
340
341 return 0;
342}
343
344arch_initcall(hugetlbpage_init);
345
346static void __init pud_huge_patch(void)
347{
348 struct pud_huge_patch_entry *p;
349 unsigned long addr;
350
351 p = &__pud_huge_patch;
352 addr = p->addr;
353 *(unsigned int *)addr = p->insn;
354
355 __asm__ __volatile__("flush %0" : : "r" (addr));
356}
357
358bool __init arch_hugetlb_valid_size(unsigned long size)
359{
360 unsigned int hugepage_shift = ilog2(size);
361 unsigned short hv_pgsz_idx;
362 unsigned int hv_pgsz_mask;
363
364 switch (hugepage_shift) {
365 case HPAGE_16GB_SHIFT:
366 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
367 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
368 pud_huge_patch();
369 break;
370 case HPAGE_2GB_SHIFT:
371 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
372 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
373 break;
374 case HPAGE_256MB_SHIFT:
375 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
376 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
377 break;
378 case HPAGE_SHIFT:
379 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
380 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
381 break;
382 case HPAGE_64K_SHIFT:
383 hv_pgsz_mask = HV_PGSZ_MASK_64K;
384 hv_pgsz_idx = HV_PGSZ_IDX_64K;
385 break;
386 default:
387 hv_pgsz_mask = 0;
388 }
389
390 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
391 return false;
392
393 return true;
394}
395#endif /* CONFIG_HUGETLB_PAGE */
396
397void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
398 unsigned long address, pte_t *ptep, unsigned int nr)
399{
400 struct mm_struct *mm;
401 unsigned long flags;
402 bool is_huge_tsb;
403 pte_t pte = *ptep;
404 unsigned int i;
405
406 if (tlb_type != hypervisor) {
407 unsigned long pfn = pte_pfn(pte);
408
409 if (pfn_valid(pfn))
410 flush_dcache(pfn);
411 }
412
413 mm = vma->vm_mm;
414
415 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
416 if (!pte_accessible(mm, pte))
417 return;
418
419 spin_lock_irqsave(&mm->context.lock, flags);
420
421 is_huge_tsb = false;
422#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
423 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
424 unsigned long hugepage_size = PAGE_SIZE;
425
426 if (is_vm_hugetlb_page(vma))
427 hugepage_size = huge_page_size(hstate_vma(vma));
428
429 if (hugepage_size >= PUD_SIZE) {
430 unsigned long mask = 0x1ffc00000UL;
431
432 /* Transfer bits [32:22] from address to resolve
433 * at 4M granularity.
434 */
435 pte_val(pte) &= ~mask;
436 pte_val(pte) |= (address & mask);
437 } else if (hugepage_size >= PMD_SIZE) {
438 /* We are fabricating 8MB pages using 4MB
439 * real hw pages.
440 */
441 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
442 }
443
444 if (hugepage_size >= PMD_SIZE) {
445 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
446 REAL_HPAGE_SHIFT, address, pte_val(pte));
447 is_huge_tsb = true;
448 }
449 }
450#endif
451 if (!is_huge_tsb) {
452 for (i = 0; i < nr; i++) {
453 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
454 address, pte_val(pte));
455 address += PAGE_SIZE;
456 pte_val(pte) += PAGE_SIZE;
457 }
458 }
459
460 spin_unlock_irqrestore(&mm->context.lock, flags);
461}
462
463void flush_dcache_folio(struct folio *folio)
464{
465 unsigned long pfn = folio_pfn(folio);
466 struct address_space *mapping;
467 int this_cpu;
468
469 if (tlb_type == hypervisor)
470 return;
471
472 /* Do not bother with the expensive D-cache flush if it
473 * is merely the zero page. The 'bigcore' testcase in GDB
474 * causes this case to run millions of times.
475 */
476 if (is_zero_pfn(pfn))
477 return;
478
479 this_cpu = get_cpu();
480
481 mapping = folio_flush_mapping(folio);
482 if (mapping && !mapping_mapped(mapping)) {
483 bool dirty = test_bit(PG_dcache_dirty, &folio->flags);
484 if (dirty) {
485 int dirty_cpu = dcache_dirty_cpu(folio);
486
487 if (dirty_cpu == this_cpu)
488 goto out;
489 smp_flush_dcache_folio_impl(folio, dirty_cpu);
490 }
491 set_dcache_dirty(folio, this_cpu);
492 } else {
493 /* We could delay the flush for the !page_mapping
494 * case too. But that case is for exec env/arg
495 * pages and those are %99 certainly going to get
496 * faulted into the tlb (and thus flushed) anyways.
497 */
498 flush_dcache_folio_impl(folio);
499 }
500
501out:
502 put_cpu();
503}
504EXPORT_SYMBOL(flush_dcache_folio);
505
506void __kprobes flush_icache_range(unsigned long start, unsigned long end)
507{
508 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
509 if (tlb_type == spitfire) {
510 unsigned long kaddr;
511
512 /* This code only runs on Spitfire cpus so this is
513 * why we can assume _PAGE_PADDR_4U.
514 */
515 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
516 unsigned long paddr, mask = _PAGE_PADDR_4U;
517
518 if (kaddr >= PAGE_OFFSET)
519 paddr = kaddr & mask;
520 else {
521 pte_t *ptep = virt_to_kpte(kaddr);
522
523 paddr = pte_val(*ptep) & mask;
524 }
525 __flush_icache_page(paddr);
526 }
527 }
528}
529EXPORT_SYMBOL(flush_icache_range);
530
531void mmu_info(struct seq_file *m)
532{
533 static const char *pgsz_strings[] = {
534 "8K", "64K", "512K", "4MB", "32MB",
535 "256MB", "2GB", "16GB",
536 };
537 int i, printed;
538
539 if (tlb_type == cheetah)
540 seq_printf(m, "MMU Type\t: Cheetah\n");
541 else if (tlb_type == cheetah_plus)
542 seq_printf(m, "MMU Type\t: Cheetah+\n");
543 else if (tlb_type == spitfire)
544 seq_printf(m, "MMU Type\t: Spitfire\n");
545 else if (tlb_type == hypervisor)
546 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
547 else
548 seq_printf(m, "MMU Type\t: ???\n");
549
550 seq_printf(m, "MMU PGSZs\t: ");
551 printed = 0;
552 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
553 if (cpu_pgsz_mask & (1UL << i)) {
554 seq_printf(m, "%s%s",
555 printed ? "," : "", pgsz_strings[i]);
556 printed++;
557 }
558 }
559 seq_putc(m, '\n');
560
561#ifdef CONFIG_DEBUG_DCFLUSH
562 seq_printf(m, "DCPageFlushes\t: %d\n",
563 atomic_read(&dcpage_flushes));
564#ifdef CONFIG_SMP
565 seq_printf(m, "DCPageFlushesXC\t: %d\n",
566 atomic_read(&dcpage_flushes_xcall));
567#endif /* CONFIG_SMP */
568#endif /* CONFIG_DEBUG_DCFLUSH */
569}
570
571struct linux_prom_translation prom_trans[512] __read_mostly;
572unsigned int prom_trans_ents __read_mostly;
573
574unsigned long kern_locked_tte_data;
575
576/* The obp translations are saved based on 8k pagesize, since obp can
577 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
578 * HI_OBP_ADDRESS range are handled in ktlb.S.
579 */
580static inline int in_obp_range(unsigned long vaddr)
581{
582 return (vaddr >= LOW_OBP_ADDRESS &&
583 vaddr < HI_OBP_ADDRESS);
584}
585
586static int cmp_ptrans(const void *a, const void *b)
587{
588 const struct linux_prom_translation *x = a, *y = b;
589
590 if (x->virt > y->virt)
591 return 1;
592 if (x->virt < y->virt)
593 return -1;
594 return 0;
595}
596
597/* Read OBP translations property into 'prom_trans[]'. */
598static void __init read_obp_translations(void)
599{
600 int n, node, ents, first, last, i;
601
602 node = prom_finddevice("/virtual-memory");
603 n = prom_getproplen(node, "translations");
604 if (unlikely(n == 0 || n == -1)) {
605 prom_printf("prom_mappings: Couldn't get size.\n");
606 prom_halt();
607 }
608 if (unlikely(n > sizeof(prom_trans))) {
609 prom_printf("prom_mappings: Size %d is too big.\n", n);
610 prom_halt();
611 }
612
613 if ((n = prom_getproperty(node, "translations",
614 (char *)&prom_trans[0],
615 sizeof(prom_trans))) == -1) {
616 prom_printf("prom_mappings: Couldn't get property.\n");
617 prom_halt();
618 }
619
620 n = n / sizeof(struct linux_prom_translation);
621
622 ents = n;
623
624 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
625 cmp_ptrans, NULL);
626
627 /* Now kick out all the non-OBP entries. */
628 for (i = 0; i < ents; i++) {
629 if (in_obp_range(prom_trans[i].virt))
630 break;
631 }
632 first = i;
633 for (; i < ents; i++) {
634 if (!in_obp_range(prom_trans[i].virt))
635 break;
636 }
637 last = i;
638
639 for (i = 0; i < (last - first); i++) {
640 struct linux_prom_translation *src = &prom_trans[i + first];
641 struct linux_prom_translation *dest = &prom_trans[i];
642
643 *dest = *src;
644 }
645 for (; i < ents; i++) {
646 struct linux_prom_translation *dest = &prom_trans[i];
647 dest->virt = dest->size = dest->data = 0x0UL;
648 }
649
650 prom_trans_ents = last - first;
651
652 if (tlb_type == spitfire) {
653 /* Clear diag TTE bits. */
654 for (i = 0; i < prom_trans_ents; i++)
655 prom_trans[i].data &= ~0x0003fe0000000000UL;
656 }
657
658 /* Force execute bit on. */
659 for (i = 0; i < prom_trans_ents; i++)
660 prom_trans[i].data |= (tlb_type == hypervisor ?
661 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
662}
663
664static void __init hypervisor_tlb_lock(unsigned long vaddr,
665 unsigned long pte,
666 unsigned long mmu)
667{
668 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
669
670 if (ret != 0) {
671 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
672 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
673 prom_halt();
674 }
675}
676
677static unsigned long kern_large_tte(unsigned long paddr);
678
679static void __init remap_kernel(void)
680{
681 unsigned long phys_page, tte_vaddr, tte_data;
682 int i, tlb_ent = sparc64_highest_locked_tlbent();
683
684 tte_vaddr = (unsigned long) KERNBASE;
685 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
686 tte_data = kern_large_tte(phys_page);
687
688 kern_locked_tte_data = tte_data;
689
690 /* Now lock us into the TLBs via Hypervisor or OBP. */
691 if (tlb_type == hypervisor) {
692 for (i = 0; i < num_kernel_image_mappings; i++) {
693 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
694 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
695 tte_vaddr += 0x400000;
696 tte_data += 0x400000;
697 }
698 } else {
699 for (i = 0; i < num_kernel_image_mappings; i++) {
700 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
701 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
702 tte_vaddr += 0x400000;
703 tte_data += 0x400000;
704 }
705 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
706 }
707 if (tlb_type == cheetah_plus) {
708 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
709 CTX_CHEETAH_PLUS_NUC);
710 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
711 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
712 }
713}
714
715
716static void __init inherit_prom_mappings(void)
717{
718 /* Now fixup OBP's idea about where we really are mapped. */
719 printk("Remapping the kernel... ");
720 remap_kernel();
721 printk("done.\n");
722}
723
724void prom_world(int enter)
725{
726 /*
727 * No need to change the address space any more, just flush
728 * the register windows
729 */
730 __asm__ __volatile__("flushw");
731}
732
733void __flush_dcache_range(unsigned long start, unsigned long end)
734{
735 unsigned long va;
736
737 if (tlb_type == spitfire) {
738 int n = 0;
739
740 for (va = start; va < end; va += 32) {
741 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
742 if (++n >= 512)
743 break;
744 }
745 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
746 start = __pa(start);
747 end = __pa(end);
748 for (va = start; va < end; va += 32)
749 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
750 "membar #Sync"
751 : /* no outputs */
752 : "r" (va),
753 "i" (ASI_DCACHE_INVALIDATE));
754 }
755}
756EXPORT_SYMBOL(__flush_dcache_range);
757
758/* get_new_mmu_context() uses "cache + 1". */
759DEFINE_SPINLOCK(ctx_alloc_lock);
760unsigned long tlb_context_cache = CTX_FIRST_VERSION;
761#define MAX_CTX_NR (1UL << CTX_NR_BITS)
762#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
763DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
764DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
765
766static void mmu_context_wrap(void)
767{
768 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
769 unsigned long new_ver, new_ctx, old_ctx;
770 struct mm_struct *mm;
771 int cpu;
772
773 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
774
775 /* Reserve kernel context */
776 set_bit(0, mmu_context_bmap);
777
778 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
779 if (unlikely(new_ver == 0))
780 new_ver = CTX_FIRST_VERSION;
781 tlb_context_cache = new_ver;
782
783 /*
784 * Make sure that any new mm that are added into per_cpu_secondary_mm,
785 * are going to go through get_new_mmu_context() path.
786 */
787 mb();
788
789 /*
790 * Updated versions to current on those CPUs that had valid secondary
791 * contexts
792 */
793 for_each_online_cpu(cpu) {
794 /*
795 * If a new mm is stored after we took this mm from the array,
796 * it will go into get_new_mmu_context() path, because we
797 * already bumped the version in tlb_context_cache.
798 */
799 mm = per_cpu(per_cpu_secondary_mm, cpu);
800
801 if (unlikely(!mm || mm == &init_mm))
802 continue;
803
804 old_ctx = mm->context.sparc64_ctx_val;
805 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
806 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
807 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
808 mm->context.sparc64_ctx_val = new_ctx;
809 }
810 }
811}
812
813/* Caller does TLB context flushing on local CPU if necessary.
814 * The caller also ensures that CTX_VALID(mm->context) is false.
815 *
816 * We must be careful about boundary cases so that we never
817 * let the user have CTX 0 (nucleus) or we ever use a CTX
818 * version of zero (and thus NO_CONTEXT would not be caught
819 * by version mis-match tests in mmu_context.h).
820 *
821 * Always invoked with interrupts disabled.
822 */
823void get_new_mmu_context(struct mm_struct *mm)
824{
825 unsigned long ctx, new_ctx;
826 unsigned long orig_pgsz_bits;
827
828 spin_lock(&ctx_alloc_lock);
829retry:
830 /* wrap might have happened, test again if our context became valid */
831 if (unlikely(CTX_VALID(mm->context)))
832 goto out;
833 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
834 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
835 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
836 if (new_ctx >= (1 << CTX_NR_BITS)) {
837 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
838 if (new_ctx >= ctx) {
839 mmu_context_wrap();
840 goto retry;
841 }
842 }
843 if (mm->context.sparc64_ctx_val)
844 cpumask_clear(mm_cpumask(mm));
845 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
846 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
847 tlb_context_cache = new_ctx;
848 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
849out:
850 spin_unlock(&ctx_alloc_lock);
851}
852
853static int numa_enabled = 1;
854static int numa_debug;
855
856static int __init early_numa(char *p)
857{
858 if (!p)
859 return 0;
860
861 if (strstr(p, "off"))
862 numa_enabled = 0;
863
864 if (strstr(p, "debug"))
865 numa_debug = 1;
866
867 return 0;
868}
869early_param("numa", early_numa);
870
871#define numadbg(f, a...) \
872do { if (numa_debug) \
873 printk(KERN_INFO f, ## a); \
874} while (0)
875
876static void __init find_ramdisk(unsigned long phys_base)
877{
878#ifdef CONFIG_BLK_DEV_INITRD
879 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
880 unsigned long ramdisk_image;
881
882 /* Older versions of the bootloader only supported a
883 * 32-bit physical address for the ramdisk image
884 * location, stored at sparc_ramdisk_image. Newer
885 * SILO versions set sparc_ramdisk_image to zero and
886 * provide a full 64-bit physical address at
887 * sparc_ramdisk_image64.
888 */
889 ramdisk_image = sparc_ramdisk_image;
890 if (!ramdisk_image)
891 ramdisk_image = sparc_ramdisk_image64;
892
893 /* Another bootloader quirk. The bootloader normalizes
894 * the physical address to KERNBASE, so we have to
895 * factor that back out and add in the lowest valid
896 * physical page address to get the true physical address.
897 */
898 ramdisk_image -= KERNBASE;
899 ramdisk_image += phys_base;
900
901 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
902 ramdisk_image, sparc_ramdisk_size);
903
904 initrd_start = ramdisk_image;
905 initrd_end = ramdisk_image + sparc_ramdisk_size;
906
907 memblock_reserve(initrd_start, sparc_ramdisk_size);
908
909 initrd_start += PAGE_OFFSET;
910 initrd_end += PAGE_OFFSET;
911 }
912#endif
913}
914
915struct node_mem_mask {
916 unsigned long mask;
917 unsigned long match;
918};
919static struct node_mem_mask node_masks[MAX_NUMNODES];
920static int num_node_masks;
921
922#ifdef CONFIG_NUMA
923
924struct mdesc_mlgroup {
925 u64 node;
926 u64 latency;
927 u64 match;
928 u64 mask;
929};
930
931static struct mdesc_mlgroup *mlgroups;
932static int num_mlgroups;
933
934int numa_cpu_lookup_table[NR_CPUS];
935cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
936
937struct mdesc_mblock {
938 u64 base;
939 u64 size;
940 u64 offset; /* RA-to-PA */
941};
942static struct mdesc_mblock *mblocks;
943static int num_mblocks;
944
945static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
946{
947 struct mdesc_mblock *m = NULL;
948 int i;
949
950 for (i = 0; i < num_mblocks; i++) {
951 m = &mblocks[i];
952
953 if (addr >= m->base &&
954 addr < (m->base + m->size)) {
955 break;
956 }
957 }
958
959 return m;
960}
961
962static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
963{
964 int prev_nid, new_nid;
965
966 prev_nid = NUMA_NO_NODE;
967 for ( ; start < end; start += PAGE_SIZE) {
968 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
969 struct node_mem_mask *p = &node_masks[new_nid];
970
971 if ((start & p->mask) == p->match) {
972 if (prev_nid == NUMA_NO_NODE)
973 prev_nid = new_nid;
974 break;
975 }
976 }
977
978 if (new_nid == num_node_masks) {
979 prev_nid = 0;
980 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
981 start);
982 break;
983 }
984
985 if (prev_nid != new_nid)
986 break;
987 }
988 *nid = prev_nid;
989
990 return start > end ? end : start;
991}
992
993static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
994{
995 u64 ret_end, pa_start, m_mask, m_match, m_end;
996 struct mdesc_mblock *mblock;
997 int _nid, i;
998
999 if (tlb_type != hypervisor)
1000 return memblock_nid_range_sun4u(start, end, nid);
1001
1002 mblock = addr_to_mblock(start);
1003 if (!mblock) {
1004 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1005 start);
1006
1007 _nid = 0;
1008 ret_end = end;
1009 goto done;
1010 }
1011
1012 pa_start = start + mblock->offset;
1013 m_match = 0;
1014 m_mask = 0;
1015
1016 for (_nid = 0; _nid < num_node_masks; _nid++) {
1017 struct node_mem_mask *const m = &node_masks[_nid];
1018
1019 if ((pa_start & m->mask) == m->match) {
1020 m_match = m->match;
1021 m_mask = m->mask;
1022 break;
1023 }
1024 }
1025
1026 if (num_node_masks == _nid) {
1027 /* We could not find NUMA group, so default to 0, but lets
1028 * search for latency group, so we could calculate the correct
1029 * end address that we return
1030 */
1031 _nid = 0;
1032
1033 for (i = 0; i < num_mlgroups; i++) {
1034 struct mdesc_mlgroup *const m = &mlgroups[i];
1035
1036 if ((pa_start & m->mask) == m->match) {
1037 m_match = m->match;
1038 m_mask = m->mask;
1039 break;
1040 }
1041 }
1042
1043 if (i == num_mlgroups) {
1044 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1045 start);
1046
1047 ret_end = end;
1048 goto done;
1049 }
1050 }
1051
1052 /*
1053 * Each latency group has match and mask, and each memory block has an
1054 * offset. An address belongs to a latency group if its address matches
1055 * the following formula: ((addr + offset) & mask) == match
1056 * It is, however, slow to check every single page if it matches a
1057 * particular latency group. As optimization we calculate end value by
1058 * using bit arithmetics.
1059 */
1060 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1061 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1062 ret_end = m_end > end ? end : m_end;
1063
1064done:
1065 *nid = _nid;
1066 return ret_end;
1067}
1068#endif
1069
1070/* This must be invoked after performing all of the necessary
1071 * memblock_set_node() calls for 'nid'. We need to be able to get
1072 * correct data from get_pfn_range_for_nid().
1073 */
1074static void __init allocate_node_data(int nid)
1075{
1076 struct pglist_data *p;
1077 unsigned long start_pfn, end_pfn;
1078#ifdef CONFIG_NUMA
1079
1080 NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
1081 SMP_CACHE_BYTES, nid);
1082 if (!NODE_DATA(nid)) {
1083 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1084 prom_halt();
1085 }
1086
1087 NODE_DATA(nid)->node_id = nid;
1088#endif
1089
1090 p = NODE_DATA(nid);
1091
1092 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1093 p->node_start_pfn = start_pfn;
1094 p->node_spanned_pages = end_pfn - start_pfn;
1095}
1096
1097static void init_node_masks_nonnuma(void)
1098{
1099#ifdef CONFIG_NUMA
1100 int i;
1101#endif
1102
1103 numadbg("Initializing tables for non-numa.\n");
1104
1105 node_masks[0].mask = 0;
1106 node_masks[0].match = 0;
1107 num_node_masks = 1;
1108
1109#ifdef CONFIG_NUMA
1110 for (i = 0; i < NR_CPUS; i++)
1111 numa_cpu_lookup_table[i] = 0;
1112
1113 cpumask_setall(&numa_cpumask_lookup_table[0]);
1114#endif
1115}
1116
1117#ifdef CONFIG_NUMA
1118struct pglist_data *node_data[MAX_NUMNODES];
1119
1120EXPORT_SYMBOL(numa_cpu_lookup_table);
1121EXPORT_SYMBOL(numa_cpumask_lookup_table);
1122EXPORT_SYMBOL(node_data);
1123
1124static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1125 u32 cfg_handle)
1126{
1127 u64 arc;
1128
1129 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1130 u64 target = mdesc_arc_target(md, arc);
1131 const u64 *val;
1132
1133 val = mdesc_get_property(md, target,
1134 "cfg-handle", NULL);
1135 if (val && *val == cfg_handle)
1136 return 0;
1137 }
1138 return -ENODEV;
1139}
1140
1141static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1142 u32 cfg_handle)
1143{
1144 u64 arc, candidate, best_latency = ~(u64)0;
1145
1146 candidate = MDESC_NODE_NULL;
1147 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1148 u64 target = mdesc_arc_target(md, arc);
1149 const char *name = mdesc_node_name(md, target);
1150 const u64 *val;
1151
1152 if (strcmp(name, "pio-latency-group"))
1153 continue;
1154
1155 val = mdesc_get_property(md, target, "latency", NULL);
1156 if (!val)
1157 continue;
1158
1159 if (*val < best_latency) {
1160 candidate = target;
1161 best_latency = *val;
1162 }
1163 }
1164
1165 if (candidate == MDESC_NODE_NULL)
1166 return -ENODEV;
1167
1168 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1169}
1170
1171int of_node_to_nid(struct device_node *dp)
1172{
1173 const struct linux_prom64_registers *regs;
1174 struct mdesc_handle *md;
1175 u32 cfg_handle;
1176 int count, nid;
1177 u64 grp;
1178
1179 /* This is the right thing to do on currently supported
1180 * SUN4U NUMA platforms as well, as the PCI controller does
1181 * not sit behind any particular memory controller.
1182 */
1183 if (!mlgroups)
1184 return -1;
1185
1186 regs = of_get_property(dp, "reg", NULL);
1187 if (!regs)
1188 return -1;
1189
1190 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1191
1192 md = mdesc_grab();
1193
1194 count = 0;
1195 nid = NUMA_NO_NODE;
1196 mdesc_for_each_node_by_name(md, grp, "group") {
1197 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1198 nid = count;
1199 break;
1200 }
1201 count++;
1202 }
1203
1204 mdesc_release(md);
1205
1206 return nid;
1207}
1208
1209static void __init add_node_ranges(void)
1210{
1211 phys_addr_t start, end;
1212 unsigned long prev_max;
1213 u64 i;
1214
1215memblock_resized:
1216 prev_max = memblock.memory.max;
1217
1218 for_each_mem_range(i, &start, &end) {
1219 while (start < end) {
1220 unsigned long this_end;
1221 int nid;
1222
1223 this_end = memblock_nid_range(start, end, &nid);
1224
1225 numadbg("Setting memblock NUMA node nid[%d] "
1226 "start[%llx] end[%lx]\n",
1227 nid, start, this_end);
1228
1229 memblock_set_node(start, this_end - start,
1230 &memblock.memory, nid);
1231 if (memblock.memory.max != prev_max)
1232 goto memblock_resized;
1233 start = this_end;
1234 }
1235 }
1236}
1237
1238static int __init grab_mlgroups(struct mdesc_handle *md)
1239{
1240 unsigned long paddr;
1241 int count = 0;
1242 u64 node;
1243
1244 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1245 count++;
1246 if (!count)
1247 return -ENOENT;
1248
1249 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1250 SMP_CACHE_BYTES);
1251 if (!paddr)
1252 return -ENOMEM;
1253
1254 mlgroups = __va(paddr);
1255 num_mlgroups = count;
1256
1257 count = 0;
1258 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1259 struct mdesc_mlgroup *m = &mlgroups[count++];
1260 const u64 *val;
1261
1262 m->node = node;
1263
1264 val = mdesc_get_property(md, node, "latency", NULL);
1265 m->latency = *val;
1266 val = mdesc_get_property(md, node, "address-match", NULL);
1267 m->match = *val;
1268 val = mdesc_get_property(md, node, "address-mask", NULL);
1269 m->mask = *val;
1270
1271 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1272 "match[%llx] mask[%llx]\n",
1273 count - 1, m->node, m->latency, m->match, m->mask);
1274 }
1275
1276 return 0;
1277}
1278
1279static int __init grab_mblocks(struct mdesc_handle *md)
1280{
1281 unsigned long paddr;
1282 int count = 0;
1283 u64 node;
1284
1285 mdesc_for_each_node_by_name(md, node, "mblock")
1286 count++;
1287 if (!count)
1288 return -ENOENT;
1289
1290 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1291 SMP_CACHE_BYTES);
1292 if (!paddr)
1293 return -ENOMEM;
1294
1295 mblocks = __va(paddr);
1296 num_mblocks = count;
1297
1298 count = 0;
1299 mdesc_for_each_node_by_name(md, node, "mblock") {
1300 struct mdesc_mblock *m = &mblocks[count++];
1301 const u64 *val;
1302
1303 val = mdesc_get_property(md, node, "base", NULL);
1304 m->base = *val;
1305 val = mdesc_get_property(md, node, "size", NULL);
1306 m->size = *val;
1307 val = mdesc_get_property(md, node,
1308 "address-congruence-offset", NULL);
1309
1310 /* The address-congruence-offset property is optional.
1311 * Explicity zero it be identifty this.
1312 */
1313 if (val)
1314 m->offset = *val;
1315 else
1316 m->offset = 0UL;
1317
1318 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1319 count - 1, m->base, m->size, m->offset);
1320 }
1321
1322 return 0;
1323}
1324
1325static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1326 u64 grp, cpumask_t *mask)
1327{
1328 u64 arc;
1329
1330 cpumask_clear(mask);
1331
1332 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1333 u64 target = mdesc_arc_target(md, arc);
1334 const char *name = mdesc_node_name(md, target);
1335 const u64 *id;
1336
1337 if (strcmp(name, "cpu"))
1338 continue;
1339 id = mdesc_get_property(md, target, "id", NULL);
1340 if (*id < nr_cpu_ids)
1341 cpumask_set_cpu(*id, mask);
1342 }
1343}
1344
1345static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1346{
1347 int i;
1348
1349 for (i = 0; i < num_mlgroups; i++) {
1350 struct mdesc_mlgroup *m = &mlgroups[i];
1351 if (m->node == node)
1352 return m;
1353 }
1354 return NULL;
1355}
1356
1357int __node_distance(int from, int to)
1358{
1359 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1360 pr_warn("Returning default NUMA distance value for %d->%d\n",
1361 from, to);
1362 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1363 }
1364 return numa_latency[from][to];
1365}
1366EXPORT_SYMBOL(__node_distance);
1367
1368static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1369{
1370 int i;
1371
1372 for (i = 0; i < MAX_NUMNODES; i++) {
1373 struct node_mem_mask *n = &node_masks[i];
1374
1375 if ((grp->mask == n->mask) && (grp->match == n->match))
1376 break;
1377 }
1378 return i;
1379}
1380
1381static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1382 u64 grp, int index)
1383{
1384 u64 arc;
1385
1386 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1387 int tnode;
1388 u64 target = mdesc_arc_target(md, arc);
1389 struct mdesc_mlgroup *m = find_mlgroup(target);
1390
1391 if (!m)
1392 continue;
1393 tnode = find_best_numa_node_for_mlgroup(m);
1394 if (tnode == MAX_NUMNODES)
1395 continue;
1396 numa_latency[index][tnode] = m->latency;
1397 }
1398}
1399
1400static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1401 int index)
1402{
1403 struct mdesc_mlgroup *candidate = NULL;
1404 u64 arc, best_latency = ~(u64)0;
1405 struct node_mem_mask *n;
1406
1407 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1408 u64 target = mdesc_arc_target(md, arc);
1409 struct mdesc_mlgroup *m = find_mlgroup(target);
1410 if (!m)
1411 continue;
1412 if (m->latency < best_latency) {
1413 candidate = m;
1414 best_latency = m->latency;
1415 }
1416 }
1417 if (!candidate)
1418 return -ENOENT;
1419
1420 if (num_node_masks != index) {
1421 printk(KERN_ERR "Inconsistent NUMA state, "
1422 "index[%d] != num_node_masks[%d]\n",
1423 index, num_node_masks);
1424 return -EINVAL;
1425 }
1426
1427 n = &node_masks[num_node_masks++];
1428
1429 n->mask = candidate->mask;
1430 n->match = candidate->match;
1431
1432 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1433 index, n->mask, n->match, candidate->latency);
1434
1435 return 0;
1436}
1437
1438static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1439 int index)
1440{
1441 cpumask_t mask;
1442 int cpu;
1443
1444 numa_parse_mdesc_group_cpus(md, grp, &mask);
1445
1446 for_each_cpu(cpu, &mask)
1447 numa_cpu_lookup_table[cpu] = index;
1448 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1449
1450 if (numa_debug) {
1451 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1452 for_each_cpu(cpu, &mask)
1453 printk("%d ", cpu);
1454 printk("]\n");
1455 }
1456
1457 return numa_attach_mlgroup(md, grp, index);
1458}
1459
1460static int __init numa_parse_mdesc(void)
1461{
1462 struct mdesc_handle *md = mdesc_grab();
1463 int i, j, err, count;
1464 u64 node;
1465
1466 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1467 if (node == MDESC_NODE_NULL) {
1468 mdesc_release(md);
1469 return -ENOENT;
1470 }
1471
1472 err = grab_mblocks(md);
1473 if (err < 0)
1474 goto out;
1475
1476 err = grab_mlgroups(md);
1477 if (err < 0)
1478 goto out;
1479
1480 count = 0;
1481 mdesc_for_each_node_by_name(md, node, "group") {
1482 err = numa_parse_mdesc_group(md, node, count);
1483 if (err < 0)
1484 break;
1485 count++;
1486 }
1487
1488 count = 0;
1489 mdesc_for_each_node_by_name(md, node, "group") {
1490 find_numa_latencies_for_group(md, node, count);
1491 count++;
1492 }
1493
1494 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1495 for (i = 0; i < MAX_NUMNODES; i++) {
1496 u64 self_latency = numa_latency[i][i];
1497
1498 for (j = 0; j < MAX_NUMNODES; j++) {
1499 numa_latency[i][j] =
1500 (numa_latency[i][j] * LOCAL_DISTANCE) /
1501 self_latency;
1502 }
1503 }
1504
1505 add_node_ranges();
1506
1507 for (i = 0; i < num_node_masks; i++) {
1508 allocate_node_data(i);
1509 node_set_online(i);
1510 }
1511
1512 err = 0;
1513out:
1514 mdesc_release(md);
1515 return err;
1516}
1517
1518static int __init numa_parse_jbus(void)
1519{
1520 unsigned long cpu, index;
1521
1522 /* NUMA node id is encoded in bits 36 and higher, and there is
1523 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1524 */
1525 index = 0;
1526 for_each_present_cpu(cpu) {
1527 numa_cpu_lookup_table[cpu] = index;
1528 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1529 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1530 node_masks[index].match = cpu << 36UL;
1531
1532 index++;
1533 }
1534 num_node_masks = index;
1535
1536 add_node_ranges();
1537
1538 for (index = 0; index < num_node_masks; index++) {
1539 allocate_node_data(index);
1540 node_set_online(index);
1541 }
1542
1543 return 0;
1544}
1545
1546static int __init numa_parse_sun4u(void)
1547{
1548 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1549 unsigned long ver;
1550
1551 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1552 if ((ver >> 32UL) == __JALAPENO_ID ||
1553 (ver >> 32UL) == __SERRANO_ID)
1554 return numa_parse_jbus();
1555 }
1556 return -1;
1557}
1558
1559static int __init bootmem_init_numa(void)
1560{
1561 int i, j;
1562 int err = -1;
1563
1564 numadbg("bootmem_init_numa()\n");
1565
1566 /* Some sane defaults for numa latency values */
1567 for (i = 0; i < MAX_NUMNODES; i++) {
1568 for (j = 0; j < MAX_NUMNODES; j++)
1569 numa_latency[i][j] = (i == j) ?
1570 LOCAL_DISTANCE : REMOTE_DISTANCE;
1571 }
1572
1573 if (numa_enabled) {
1574 if (tlb_type == hypervisor)
1575 err = numa_parse_mdesc();
1576 else
1577 err = numa_parse_sun4u();
1578 }
1579 return err;
1580}
1581
1582#else
1583
1584static int bootmem_init_numa(void)
1585{
1586 return -1;
1587}
1588
1589#endif
1590
1591static void __init bootmem_init_nonnuma(void)
1592{
1593 unsigned long top_of_ram = memblock_end_of_DRAM();
1594 unsigned long total_ram = memblock_phys_mem_size();
1595
1596 numadbg("bootmem_init_nonnuma()\n");
1597
1598 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1599 top_of_ram, total_ram);
1600 printk(KERN_INFO "Memory hole size: %ldMB\n",
1601 (top_of_ram - total_ram) >> 20);
1602
1603 init_node_masks_nonnuma();
1604 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1605 allocate_node_data(0);
1606 node_set_online(0);
1607}
1608
1609static unsigned long __init bootmem_init(unsigned long phys_base)
1610{
1611 unsigned long end_pfn;
1612
1613 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1614 max_pfn = max_low_pfn = end_pfn;
1615 min_low_pfn = (phys_base >> PAGE_SHIFT);
1616
1617 if (bootmem_init_numa() < 0)
1618 bootmem_init_nonnuma();
1619
1620 /* Dump memblock with node info. */
1621 memblock_dump_all();
1622
1623 /* XXX cpu notifier XXX */
1624
1625 sparse_init();
1626
1627 return end_pfn;
1628}
1629
1630static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1631static int pall_ents __initdata;
1632
1633static unsigned long max_phys_bits = 40;
1634
1635bool kern_addr_valid(unsigned long addr)
1636{
1637 pgd_t *pgd;
1638 p4d_t *p4d;
1639 pud_t *pud;
1640 pmd_t *pmd;
1641 pte_t *pte;
1642
1643 if ((long)addr < 0L) {
1644 unsigned long pa = __pa(addr);
1645
1646 if ((pa >> max_phys_bits) != 0UL)
1647 return false;
1648
1649 return pfn_valid(pa >> PAGE_SHIFT);
1650 }
1651
1652 if (addr >= (unsigned long) KERNBASE &&
1653 addr < (unsigned long)&_end)
1654 return true;
1655
1656 pgd = pgd_offset_k(addr);
1657 if (pgd_none(*pgd))
1658 return false;
1659
1660 p4d = p4d_offset(pgd, addr);
1661 if (p4d_none(*p4d))
1662 return false;
1663
1664 pud = pud_offset(p4d, addr);
1665 if (pud_none(*pud))
1666 return false;
1667
1668 if (pud_large(*pud))
1669 return pfn_valid(pud_pfn(*pud));
1670
1671 pmd = pmd_offset(pud, addr);
1672 if (pmd_none(*pmd))
1673 return false;
1674
1675 if (pmd_large(*pmd))
1676 return pfn_valid(pmd_pfn(*pmd));
1677
1678 pte = pte_offset_kernel(pmd, addr);
1679 if (pte_none(*pte))
1680 return false;
1681
1682 return pfn_valid(pte_pfn(*pte));
1683}
1684
1685static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1686 unsigned long vend,
1687 pud_t *pud)
1688{
1689 const unsigned long mask16gb = (1UL << 34) - 1UL;
1690 u64 pte_val = vstart;
1691
1692 /* Each PUD is 8GB */
1693 if ((vstart & mask16gb) ||
1694 (vend - vstart <= mask16gb)) {
1695 pte_val ^= kern_linear_pte_xor[2];
1696 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1697
1698 return vstart + PUD_SIZE;
1699 }
1700
1701 pte_val ^= kern_linear_pte_xor[3];
1702 pte_val |= _PAGE_PUD_HUGE;
1703
1704 vend = vstart + mask16gb + 1UL;
1705 while (vstart < vend) {
1706 pud_val(*pud) = pte_val;
1707
1708 pte_val += PUD_SIZE;
1709 vstart += PUD_SIZE;
1710 pud++;
1711 }
1712 return vstart;
1713}
1714
1715static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1716 bool guard)
1717{
1718 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1719 return true;
1720
1721 return false;
1722}
1723
1724static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1725 unsigned long vend,
1726 pmd_t *pmd)
1727{
1728 const unsigned long mask256mb = (1UL << 28) - 1UL;
1729 const unsigned long mask2gb = (1UL << 31) - 1UL;
1730 u64 pte_val = vstart;
1731
1732 /* Each PMD is 8MB */
1733 if ((vstart & mask256mb) ||
1734 (vend - vstart <= mask256mb)) {
1735 pte_val ^= kern_linear_pte_xor[0];
1736 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1737
1738 return vstart + PMD_SIZE;
1739 }
1740
1741 if ((vstart & mask2gb) ||
1742 (vend - vstart <= mask2gb)) {
1743 pte_val ^= kern_linear_pte_xor[1];
1744 pte_val |= _PAGE_PMD_HUGE;
1745 vend = vstart + mask256mb + 1UL;
1746 } else {
1747 pte_val ^= kern_linear_pte_xor[2];
1748 pte_val |= _PAGE_PMD_HUGE;
1749 vend = vstart + mask2gb + 1UL;
1750 }
1751
1752 while (vstart < vend) {
1753 pmd_val(*pmd) = pte_val;
1754
1755 pte_val += PMD_SIZE;
1756 vstart += PMD_SIZE;
1757 pmd++;
1758 }
1759
1760 return vstart;
1761}
1762
1763static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1764 bool guard)
1765{
1766 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1767 return true;
1768
1769 return false;
1770}
1771
1772static unsigned long __ref kernel_map_range(unsigned long pstart,
1773 unsigned long pend, pgprot_t prot,
1774 bool use_huge)
1775{
1776 unsigned long vstart = PAGE_OFFSET + pstart;
1777 unsigned long vend = PAGE_OFFSET + pend;
1778 unsigned long alloc_bytes = 0UL;
1779
1780 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1781 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1782 vstart, vend);
1783 prom_halt();
1784 }
1785
1786 while (vstart < vend) {
1787 unsigned long this_end, paddr = __pa(vstart);
1788 pgd_t *pgd = pgd_offset_k(vstart);
1789 p4d_t *p4d;
1790 pud_t *pud;
1791 pmd_t *pmd;
1792 pte_t *pte;
1793
1794 if (pgd_none(*pgd)) {
1795 pud_t *new;
1796
1797 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1798 PAGE_SIZE);
1799 if (!new)
1800 goto err_alloc;
1801 alloc_bytes += PAGE_SIZE;
1802 pgd_populate(&init_mm, pgd, new);
1803 }
1804
1805 p4d = p4d_offset(pgd, vstart);
1806 if (p4d_none(*p4d)) {
1807 pud_t *new;
1808
1809 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1810 PAGE_SIZE);
1811 if (!new)
1812 goto err_alloc;
1813 alloc_bytes += PAGE_SIZE;
1814 p4d_populate(&init_mm, p4d, new);
1815 }
1816
1817 pud = pud_offset(p4d, vstart);
1818 if (pud_none(*pud)) {
1819 pmd_t *new;
1820
1821 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1822 vstart = kernel_map_hugepud(vstart, vend, pud);
1823 continue;
1824 }
1825 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1826 PAGE_SIZE);
1827 if (!new)
1828 goto err_alloc;
1829 alloc_bytes += PAGE_SIZE;
1830 pud_populate(&init_mm, pud, new);
1831 }
1832
1833 pmd = pmd_offset(pud, vstart);
1834 if (pmd_none(*pmd)) {
1835 pte_t *new;
1836
1837 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1838 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1839 continue;
1840 }
1841 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1842 PAGE_SIZE);
1843 if (!new)
1844 goto err_alloc;
1845 alloc_bytes += PAGE_SIZE;
1846 pmd_populate_kernel(&init_mm, pmd, new);
1847 }
1848
1849 pte = pte_offset_kernel(pmd, vstart);
1850 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1851 if (this_end > vend)
1852 this_end = vend;
1853
1854 while (vstart < this_end) {
1855 pte_val(*pte) = (paddr | pgprot_val(prot));
1856
1857 vstart += PAGE_SIZE;
1858 paddr += PAGE_SIZE;
1859 pte++;
1860 }
1861 }
1862
1863 return alloc_bytes;
1864
1865err_alloc:
1866 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1867 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1868 return -ENOMEM;
1869}
1870
1871static void __init flush_all_kernel_tsbs(void)
1872{
1873 int i;
1874
1875 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1876 struct tsb *ent = &swapper_tsb[i];
1877
1878 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1879 }
1880#ifndef CONFIG_DEBUG_PAGEALLOC
1881 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1882 struct tsb *ent = &swapper_4m_tsb[i];
1883
1884 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1885 }
1886#endif
1887}
1888
1889extern unsigned int kvmap_linear_patch[1];
1890
1891static void __init kernel_physical_mapping_init(void)
1892{
1893 unsigned long i, mem_alloced = 0UL;
1894 bool use_huge = true;
1895
1896#ifdef CONFIG_DEBUG_PAGEALLOC
1897 use_huge = false;
1898#endif
1899 for (i = 0; i < pall_ents; i++) {
1900 unsigned long phys_start, phys_end;
1901
1902 phys_start = pall[i].phys_addr;
1903 phys_end = phys_start + pall[i].reg_size;
1904
1905 mem_alloced += kernel_map_range(phys_start, phys_end,
1906 PAGE_KERNEL, use_huge);
1907 }
1908
1909 printk("Allocated %ld bytes for kernel page tables.\n",
1910 mem_alloced);
1911
1912 kvmap_linear_patch[0] = 0x01000000; /* nop */
1913 flushi(&kvmap_linear_patch[0]);
1914
1915 flush_all_kernel_tsbs();
1916
1917 __flush_tlb_all();
1918}
1919
1920#ifdef CONFIG_DEBUG_PAGEALLOC
1921void __kernel_map_pages(struct page *page, int numpages, int enable)
1922{
1923 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1924 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1925
1926 kernel_map_range(phys_start, phys_end,
1927 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1928
1929 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1930 PAGE_OFFSET + phys_end);
1931
1932 /* we should perform an IPI and flush all tlbs,
1933 * but that can deadlock->flush only current cpu.
1934 */
1935 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1936 PAGE_OFFSET + phys_end);
1937}
1938#endif
1939
1940unsigned long __init find_ecache_flush_span(unsigned long size)
1941{
1942 int i;
1943
1944 for (i = 0; i < pavail_ents; i++) {
1945 if (pavail[i].reg_size >= size)
1946 return pavail[i].phys_addr;
1947 }
1948
1949 return ~0UL;
1950}
1951
1952unsigned long PAGE_OFFSET;
1953EXPORT_SYMBOL(PAGE_OFFSET);
1954
1955unsigned long VMALLOC_END = 0x0000010000000000UL;
1956EXPORT_SYMBOL(VMALLOC_END);
1957
1958unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1959unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1960
1961static void __init setup_page_offset(void)
1962{
1963 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1964 /* Cheetah/Panther support a full 64-bit virtual
1965 * address, so we can use all that our page tables
1966 * support.
1967 */
1968 sparc64_va_hole_top = 0xfff0000000000000UL;
1969 sparc64_va_hole_bottom = 0x0010000000000000UL;
1970
1971 max_phys_bits = 42;
1972 } else if (tlb_type == hypervisor) {
1973 switch (sun4v_chip_type) {
1974 case SUN4V_CHIP_NIAGARA1:
1975 case SUN4V_CHIP_NIAGARA2:
1976 /* T1 and T2 support 48-bit virtual addresses. */
1977 sparc64_va_hole_top = 0xffff800000000000UL;
1978 sparc64_va_hole_bottom = 0x0000800000000000UL;
1979
1980 max_phys_bits = 39;
1981 break;
1982 case SUN4V_CHIP_NIAGARA3:
1983 /* T3 supports 48-bit virtual addresses. */
1984 sparc64_va_hole_top = 0xffff800000000000UL;
1985 sparc64_va_hole_bottom = 0x0000800000000000UL;
1986
1987 max_phys_bits = 43;
1988 break;
1989 case SUN4V_CHIP_NIAGARA4:
1990 case SUN4V_CHIP_NIAGARA5:
1991 case SUN4V_CHIP_SPARC64X:
1992 case SUN4V_CHIP_SPARC_M6:
1993 /* T4 and later support 52-bit virtual addresses. */
1994 sparc64_va_hole_top = 0xfff8000000000000UL;
1995 sparc64_va_hole_bottom = 0x0008000000000000UL;
1996 max_phys_bits = 47;
1997 break;
1998 case SUN4V_CHIP_SPARC_M7:
1999 case SUN4V_CHIP_SPARC_SN:
2000 /* M7 and later support 52-bit virtual addresses. */
2001 sparc64_va_hole_top = 0xfff8000000000000UL;
2002 sparc64_va_hole_bottom = 0x0008000000000000UL;
2003 max_phys_bits = 49;
2004 break;
2005 case SUN4V_CHIP_SPARC_M8:
2006 default:
2007 /* M8 and later support 54-bit virtual addresses.
2008 * However, restricting M8 and above VA bits to 53
2009 * as 4-level page table cannot support more than
2010 * 53 VA bits.
2011 */
2012 sparc64_va_hole_top = 0xfff0000000000000UL;
2013 sparc64_va_hole_bottom = 0x0010000000000000UL;
2014 max_phys_bits = 51;
2015 break;
2016 }
2017 }
2018
2019 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2020 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2021 max_phys_bits);
2022 prom_halt();
2023 }
2024
2025 PAGE_OFFSET = sparc64_va_hole_top;
2026 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2027 (sparc64_va_hole_bottom >> 2));
2028
2029 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2030 PAGE_OFFSET, max_phys_bits);
2031 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2032 VMALLOC_START, VMALLOC_END);
2033 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2034 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2035}
2036
2037static void __init tsb_phys_patch(void)
2038{
2039 struct tsb_ldquad_phys_patch_entry *pquad;
2040 struct tsb_phys_patch_entry *p;
2041
2042 pquad = &__tsb_ldquad_phys_patch;
2043 while (pquad < &__tsb_ldquad_phys_patch_end) {
2044 unsigned long addr = pquad->addr;
2045
2046 if (tlb_type == hypervisor)
2047 *(unsigned int *) addr = pquad->sun4v_insn;
2048 else
2049 *(unsigned int *) addr = pquad->sun4u_insn;
2050 wmb();
2051 __asm__ __volatile__("flush %0"
2052 : /* no outputs */
2053 : "r" (addr));
2054
2055 pquad++;
2056 }
2057
2058 p = &__tsb_phys_patch;
2059 while (p < &__tsb_phys_patch_end) {
2060 unsigned long addr = p->addr;
2061
2062 *(unsigned int *) addr = p->insn;
2063 wmb();
2064 __asm__ __volatile__("flush %0"
2065 : /* no outputs */
2066 : "r" (addr));
2067
2068 p++;
2069 }
2070}
2071
2072/* Don't mark as init, we give this to the Hypervisor. */
2073#ifndef CONFIG_DEBUG_PAGEALLOC
2074#define NUM_KTSB_DESCR 2
2075#else
2076#define NUM_KTSB_DESCR 1
2077#endif
2078static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2079
2080/* The swapper TSBs are loaded with a base sequence of:
2081 *
2082 * sethi %uhi(SYMBOL), REG1
2083 * sethi %hi(SYMBOL), REG2
2084 * or REG1, %ulo(SYMBOL), REG1
2085 * or REG2, %lo(SYMBOL), REG2
2086 * sllx REG1, 32, REG1
2087 * or REG1, REG2, REG1
2088 *
2089 * When we use physical addressing for the TSB accesses, we patch the
2090 * first four instructions in the above sequence.
2091 */
2092
2093static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2094{
2095 unsigned long high_bits, low_bits;
2096
2097 high_bits = (pa >> 32) & 0xffffffff;
2098 low_bits = (pa >> 0) & 0xffffffff;
2099
2100 while (start < end) {
2101 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2102
2103 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2104 __asm__ __volatile__("flush %0" : : "r" (ia));
2105
2106 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2107 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2108
2109 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2110 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2111
2112 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2113 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2114
2115 start++;
2116 }
2117}
2118
2119static void ktsb_phys_patch(void)
2120{
2121 extern unsigned int __swapper_tsb_phys_patch;
2122 extern unsigned int __swapper_tsb_phys_patch_end;
2123 unsigned long ktsb_pa;
2124
2125 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2126 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2127 &__swapper_tsb_phys_patch_end, ktsb_pa);
2128#ifndef CONFIG_DEBUG_PAGEALLOC
2129 {
2130 extern unsigned int __swapper_4m_tsb_phys_patch;
2131 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2132 ktsb_pa = (kern_base +
2133 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2134 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2135 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2136 }
2137#endif
2138}
2139
2140static void __init sun4v_ktsb_init(void)
2141{
2142 unsigned long ktsb_pa;
2143
2144 /* First KTSB for PAGE_SIZE mappings. */
2145 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2146
2147 switch (PAGE_SIZE) {
2148 case 8 * 1024:
2149 default:
2150 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2151 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2152 break;
2153
2154 case 64 * 1024:
2155 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2156 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2157 break;
2158
2159 case 512 * 1024:
2160 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2161 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2162 break;
2163
2164 case 4 * 1024 * 1024:
2165 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2166 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2167 break;
2168 }
2169
2170 ktsb_descr[0].assoc = 1;
2171 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2172 ktsb_descr[0].ctx_idx = 0;
2173 ktsb_descr[0].tsb_base = ktsb_pa;
2174 ktsb_descr[0].resv = 0;
2175
2176#ifndef CONFIG_DEBUG_PAGEALLOC
2177 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2178 ktsb_pa = (kern_base +
2179 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2180
2181 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2182 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2183 HV_PGSZ_MASK_256MB |
2184 HV_PGSZ_MASK_2GB |
2185 HV_PGSZ_MASK_16GB) &
2186 cpu_pgsz_mask);
2187 ktsb_descr[1].assoc = 1;
2188 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2189 ktsb_descr[1].ctx_idx = 0;
2190 ktsb_descr[1].tsb_base = ktsb_pa;
2191 ktsb_descr[1].resv = 0;
2192#endif
2193}
2194
2195void sun4v_ktsb_register(void)
2196{
2197 unsigned long pa, ret;
2198
2199 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2200
2201 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2202 if (ret != 0) {
2203 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2204 "errors with %lx\n", pa, ret);
2205 prom_halt();
2206 }
2207}
2208
2209static void __init sun4u_linear_pte_xor_finalize(void)
2210{
2211#ifndef CONFIG_DEBUG_PAGEALLOC
2212 /* This is where we would add Panther support for
2213 * 32MB and 256MB pages.
2214 */
2215#endif
2216}
2217
2218static void __init sun4v_linear_pte_xor_finalize(void)
2219{
2220 unsigned long pagecv_flag;
2221
2222 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2223 * enables MCD error. Do not set bit 9 on M7 processor.
2224 */
2225 switch (sun4v_chip_type) {
2226 case SUN4V_CHIP_SPARC_M7:
2227 case SUN4V_CHIP_SPARC_M8:
2228 case SUN4V_CHIP_SPARC_SN:
2229 pagecv_flag = 0x00;
2230 break;
2231 default:
2232 pagecv_flag = _PAGE_CV_4V;
2233 break;
2234 }
2235#ifndef CONFIG_DEBUG_PAGEALLOC
2236 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2237 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2238 PAGE_OFFSET;
2239 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2240 _PAGE_P_4V | _PAGE_W_4V);
2241 } else {
2242 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2243 }
2244
2245 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2246 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2247 PAGE_OFFSET;
2248 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2249 _PAGE_P_4V | _PAGE_W_4V);
2250 } else {
2251 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2252 }
2253
2254 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2255 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2256 PAGE_OFFSET;
2257 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2258 _PAGE_P_4V | _PAGE_W_4V);
2259 } else {
2260 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2261 }
2262#endif
2263}
2264
2265/* paging_init() sets up the page tables */
2266
2267static unsigned long last_valid_pfn;
2268
2269static void sun4u_pgprot_init(void);
2270static void sun4v_pgprot_init(void);
2271
2272#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2273#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2274#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2275#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2276#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2277#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2278
2279/* We need to exclude reserved regions. This exclusion will include
2280 * vmlinux and initrd. To be more precise the initrd size could be used to
2281 * compute a new lower limit because it is freed later during initialization.
2282 */
2283static void __init reduce_memory(phys_addr_t limit_ram)
2284{
2285 limit_ram += memblock_reserved_size();
2286 memblock_enforce_memory_limit(limit_ram);
2287}
2288
2289void __init paging_init(void)
2290{
2291 unsigned long end_pfn, shift, phys_base;
2292 unsigned long real_end, i;
2293
2294 setup_page_offset();
2295
2296 /* These build time checkes make sure that the dcache_dirty_cpu()
2297 * folio->flags usage will work.
2298 *
2299 * When a page gets marked as dcache-dirty, we store the
2300 * cpu number starting at bit 32 in the folio->flags. Also,
2301 * functions like clear_dcache_dirty_cpu use the cpu mask
2302 * in 13-bit signed-immediate instruction fields.
2303 */
2304
2305 /*
2306 * Page flags must not reach into upper 32 bits that are used
2307 * for the cpu number
2308 */
2309 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2310
2311 /*
2312 * The bit fields placed in the high range must not reach below
2313 * the 32 bit boundary. Otherwise we cannot place the cpu field
2314 * at the 32 bit boundary.
2315 */
2316 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2317 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2318
2319 BUILD_BUG_ON(NR_CPUS > 4096);
2320
2321 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2322 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2323
2324 /* Invalidate both kernel TSBs. */
2325 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2326#ifndef CONFIG_DEBUG_PAGEALLOC
2327 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2328#endif
2329
2330 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2331 * bit on M7 processor. This is a conflicting usage of the same
2332 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2333 * Detection error on all pages and this will lead to problems
2334 * later. Kernel does not run with MCD enabled and hence rest
2335 * of the required steps to fully configure memory corruption
2336 * detection are not taken. We need to ensure TTE.mcde is not
2337 * set on M7 processor. Compute the value of cacheability
2338 * flag for use later taking this into consideration.
2339 */
2340 switch (sun4v_chip_type) {
2341 case SUN4V_CHIP_SPARC_M7:
2342 case SUN4V_CHIP_SPARC_M8:
2343 case SUN4V_CHIP_SPARC_SN:
2344 page_cache4v_flag = _PAGE_CP_4V;
2345 break;
2346 default:
2347 page_cache4v_flag = _PAGE_CACHE_4V;
2348 break;
2349 }
2350
2351 if (tlb_type == hypervisor)
2352 sun4v_pgprot_init();
2353 else
2354 sun4u_pgprot_init();
2355
2356 if (tlb_type == cheetah_plus ||
2357 tlb_type == hypervisor) {
2358 tsb_phys_patch();
2359 ktsb_phys_patch();
2360 }
2361
2362 if (tlb_type == hypervisor)
2363 sun4v_patch_tlb_handlers();
2364
2365 /* Find available physical memory...
2366 *
2367 * Read it twice in order to work around a bug in openfirmware.
2368 * The call to grab this table itself can cause openfirmware to
2369 * allocate memory, which in turn can take away some space from
2370 * the list of available memory. Reading it twice makes sure
2371 * we really do get the final value.
2372 */
2373 read_obp_translations();
2374 read_obp_memory("reg", &pall[0], &pall_ents);
2375 read_obp_memory("available", &pavail[0], &pavail_ents);
2376 read_obp_memory("available", &pavail[0], &pavail_ents);
2377
2378 phys_base = 0xffffffffffffffffUL;
2379 for (i = 0; i < pavail_ents; i++) {
2380 phys_base = min(phys_base, pavail[i].phys_addr);
2381 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2382 }
2383
2384 memblock_reserve(kern_base, kern_size);
2385
2386 find_ramdisk(phys_base);
2387
2388 if (cmdline_memory_size)
2389 reduce_memory(cmdline_memory_size);
2390
2391 memblock_allow_resize();
2392 memblock_dump_all();
2393
2394 set_bit(0, mmu_context_bmap);
2395
2396 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2397
2398 real_end = (unsigned long)_end;
2399 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2400 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2401 num_kernel_image_mappings);
2402
2403 /* Set kernel pgd to upper alias so physical page computations
2404 * work.
2405 */
2406 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2407
2408 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2409
2410 inherit_prom_mappings();
2411
2412 /* Ok, we can use our TLB miss and window trap handlers safely. */
2413 setup_tba();
2414
2415 __flush_tlb_all();
2416
2417 prom_build_devicetree();
2418 of_populate_present_mask();
2419#ifndef CONFIG_SMP
2420 of_fill_in_cpu_data();
2421#endif
2422
2423 if (tlb_type == hypervisor) {
2424 sun4v_mdesc_init();
2425 mdesc_populate_present_mask(cpu_all_mask);
2426#ifndef CONFIG_SMP
2427 mdesc_fill_in_cpu_data(cpu_all_mask);
2428#endif
2429 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2430
2431 sun4v_linear_pte_xor_finalize();
2432
2433 sun4v_ktsb_init();
2434 sun4v_ktsb_register();
2435 } else {
2436 unsigned long impl, ver;
2437
2438 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2439 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2440
2441 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2442 impl = ((ver >> 32) & 0xffff);
2443 if (impl == PANTHER_IMPL)
2444 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2445 HV_PGSZ_MASK_256MB);
2446
2447 sun4u_linear_pte_xor_finalize();
2448 }
2449
2450 /* Flush the TLBs and the 4M TSB so that the updated linear
2451 * pte XOR settings are realized for all mappings.
2452 */
2453 __flush_tlb_all();
2454#ifndef CONFIG_DEBUG_PAGEALLOC
2455 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2456#endif
2457 __flush_tlb_all();
2458
2459 /* Setup bootmem... */
2460 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2461
2462 kernel_physical_mapping_init();
2463
2464 {
2465 unsigned long max_zone_pfns[MAX_NR_ZONES];
2466
2467 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2468
2469 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2470
2471 free_area_init(max_zone_pfns);
2472 }
2473
2474 printk("Booting Linux...\n");
2475}
2476
2477int page_in_phys_avail(unsigned long paddr)
2478{
2479 int i;
2480
2481 paddr &= PAGE_MASK;
2482
2483 for (i = 0; i < pavail_ents; i++) {
2484 unsigned long start, end;
2485
2486 start = pavail[i].phys_addr;
2487 end = start + pavail[i].reg_size;
2488
2489 if (paddr >= start && paddr < end)
2490 return 1;
2491 }
2492 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2493 return 1;
2494#ifdef CONFIG_BLK_DEV_INITRD
2495 if (paddr >= __pa(initrd_start) &&
2496 paddr < __pa(PAGE_ALIGN(initrd_end)))
2497 return 1;
2498#endif
2499
2500 return 0;
2501}
2502
2503static void __init register_page_bootmem_info(void)
2504{
2505#ifdef CONFIG_NUMA
2506 int i;
2507
2508 for_each_online_node(i)
2509 if (NODE_DATA(i)->node_spanned_pages)
2510 register_page_bootmem_info_node(NODE_DATA(i));
2511#endif
2512}
2513void __init mem_init(void)
2514{
2515 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2516
2517 memblock_free_all();
2518
2519 /*
2520 * Must be done after boot memory is put on freelist, because here we
2521 * might set fields in deferred struct pages that have not yet been
2522 * initialized, and memblock_free_all() initializes all the reserved
2523 * deferred pages for us.
2524 */
2525 register_page_bootmem_info();
2526
2527 /*
2528 * Set up the zero page, mark it reserved, so that page count
2529 * is not manipulated when freeing the page from user ptes.
2530 */
2531 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2532 if (mem_map_zero == NULL) {
2533 prom_printf("paging_init: Cannot alloc zero page.\n");
2534 prom_halt();
2535 }
2536 mark_page_reserved(mem_map_zero);
2537
2538
2539 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2540 cheetah_ecache_flush_init();
2541}
2542
2543void free_initmem(void)
2544{
2545 unsigned long addr, initend;
2546 int do_free = 1;
2547
2548 /* If the physical memory maps were trimmed by kernel command
2549 * line options, don't even try freeing this initmem stuff up.
2550 * The kernel image could have been in the trimmed out region
2551 * and if so the freeing below will free invalid page structs.
2552 */
2553 if (cmdline_memory_size)
2554 do_free = 0;
2555
2556 /*
2557 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2558 */
2559 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2560 initend = (unsigned long)(__init_end) & PAGE_MASK;
2561 for (; addr < initend; addr += PAGE_SIZE) {
2562 unsigned long page;
2563
2564 page = (addr +
2565 ((unsigned long) __va(kern_base)) -
2566 ((unsigned long) KERNBASE));
2567 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2568
2569 if (do_free)
2570 free_reserved_page(virt_to_page(page));
2571 }
2572}
2573
2574pgprot_t PAGE_KERNEL __read_mostly;
2575EXPORT_SYMBOL(PAGE_KERNEL);
2576
2577pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2578pgprot_t PAGE_COPY __read_mostly;
2579
2580pgprot_t PAGE_SHARED __read_mostly;
2581EXPORT_SYMBOL(PAGE_SHARED);
2582
2583unsigned long pg_iobits __read_mostly;
2584
2585unsigned long _PAGE_IE __read_mostly;
2586EXPORT_SYMBOL(_PAGE_IE);
2587
2588unsigned long _PAGE_E __read_mostly;
2589EXPORT_SYMBOL(_PAGE_E);
2590
2591unsigned long _PAGE_CACHE __read_mostly;
2592EXPORT_SYMBOL(_PAGE_CACHE);
2593
2594#ifdef CONFIG_SPARSEMEM_VMEMMAP
2595int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2596 int node, struct vmem_altmap *altmap)
2597{
2598 unsigned long pte_base;
2599
2600 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2601 _PAGE_CP_4U | _PAGE_CV_4U |
2602 _PAGE_P_4U | _PAGE_W_4U);
2603 if (tlb_type == hypervisor)
2604 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2605 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2606
2607 pte_base |= _PAGE_PMD_HUGE;
2608
2609 vstart = vstart & PMD_MASK;
2610 vend = ALIGN(vend, PMD_SIZE);
2611 for (; vstart < vend; vstart += PMD_SIZE) {
2612 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2613 unsigned long pte;
2614 p4d_t *p4d;
2615 pud_t *pud;
2616 pmd_t *pmd;
2617
2618 if (!pgd)
2619 return -ENOMEM;
2620
2621 p4d = vmemmap_p4d_populate(pgd, vstart, node);
2622 if (!p4d)
2623 return -ENOMEM;
2624
2625 pud = vmemmap_pud_populate(p4d, vstart, node);
2626 if (!pud)
2627 return -ENOMEM;
2628
2629 pmd = pmd_offset(pud, vstart);
2630 pte = pmd_val(*pmd);
2631 if (!(pte & _PAGE_VALID)) {
2632 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2633
2634 if (!block)
2635 return -ENOMEM;
2636
2637 pmd_val(*pmd) = pte_base | __pa(block);
2638 }
2639 }
2640
2641 return 0;
2642}
2643
2644void vmemmap_free(unsigned long start, unsigned long end,
2645 struct vmem_altmap *altmap)
2646{
2647}
2648#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2649
2650/* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
2651static pgprot_t protection_map[16] __ro_after_init;
2652
2653static void prot_init_common(unsigned long page_none,
2654 unsigned long page_shared,
2655 unsigned long page_copy,
2656 unsigned long page_readonly,
2657 unsigned long page_exec_bit)
2658{
2659 PAGE_COPY = __pgprot(page_copy);
2660 PAGE_SHARED = __pgprot(page_shared);
2661
2662 protection_map[0x0] = __pgprot(page_none);
2663 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2664 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2665 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2666 protection_map[0x4] = __pgprot(page_readonly);
2667 protection_map[0x5] = __pgprot(page_readonly);
2668 protection_map[0x6] = __pgprot(page_copy);
2669 protection_map[0x7] = __pgprot(page_copy);
2670 protection_map[0x8] = __pgprot(page_none);
2671 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2672 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2673 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2674 protection_map[0xc] = __pgprot(page_readonly);
2675 protection_map[0xd] = __pgprot(page_readonly);
2676 protection_map[0xe] = __pgprot(page_shared);
2677 protection_map[0xf] = __pgprot(page_shared);
2678}
2679
2680static void __init sun4u_pgprot_init(void)
2681{
2682 unsigned long page_none, page_shared, page_copy, page_readonly;
2683 unsigned long page_exec_bit;
2684 int i;
2685
2686 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2687 _PAGE_CACHE_4U | _PAGE_P_4U |
2688 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2689 _PAGE_EXEC_4U);
2690 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2691 _PAGE_CACHE_4U | _PAGE_P_4U |
2692 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2693 _PAGE_EXEC_4U | _PAGE_L_4U);
2694
2695 _PAGE_IE = _PAGE_IE_4U;
2696 _PAGE_E = _PAGE_E_4U;
2697 _PAGE_CACHE = _PAGE_CACHE_4U;
2698
2699 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2700 __ACCESS_BITS_4U | _PAGE_E_4U);
2701
2702#ifdef CONFIG_DEBUG_PAGEALLOC
2703 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2704#else
2705 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2706 PAGE_OFFSET;
2707#endif
2708 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2709 _PAGE_P_4U | _PAGE_W_4U);
2710
2711 for (i = 1; i < 4; i++)
2712 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2713
2714 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2715 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2716 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2717
2718
2719 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2720 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2721 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2722 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2723 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2724 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2725 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2726
2727 page_exec_bit = _PAGE_EXEC_4U;
2728
2729 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2730 page_exec_bit);
2731}
2732
2733static void __init sun4v_pgprot_init(void)
2734{
2735 unsigned long page_none, page_shared, page_copy, page_readonly;
2736 unsigned long page_exec_bit;
2737 int i;
2738
2739 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2740 page_cache4v_flag | _PAGE_P_4V |
2741 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2742 _PAGE_EXEC_4V);
2743 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2744
2745 _PAGE_IE = _PAGE_IE_4V;
2746 _PAGE_E = _PAGE_E_4V;
2747 _PAGE_CACHE = page_cache4v_flag;
2748
2749#ifdef CONFIG_DEBUG_PAGEALLOC
2750 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2751#else
2752 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2753 PAGE_OFFSET;
2754#endif
2755 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2756 _PAGE_W_4V);
2757
2758 for (i = 1; i < 4; i++)
2759 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2760
2761 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2762 __ACCESS_BITS_4V | _PAGE_E_4V);
2763
2764 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2765 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2766 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2767 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2768
2769 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2770 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2771 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2772 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2773 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2774 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2775 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2776
2777 page_exec_bit = _PAGE_EXEC_4V;
2778
2779 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2780 page_exec_bit);
2781}
2782
2783unsigned long pte_sz_bits(unsigned long sz)
2784{
2785 if (tlb_type == hypervisor) {
2786 switch (sz) {
2787 case 8 * 1024:
2788 default:
2789 return _PAGE_SZ8K_4V;
2790 case 64 * 1024:
2791 return _PAGE_SZ64K_4V;
2792 case 512 * 1024:
2793 return _PAGE_SZ512K_4V;
2794 case 4 * 1024 * 1024:
2795 return _PAGE_SZ4MB_4V;
2796 }
2797 } else {
2798 switch (sz) {
2799 case 8 * 1024:
2800 default:
2801 return _PAGE_SZ8K_4U;
2802 case 64 * 1024:
2803 return _PAGE_SZ64K_4U;
2804 case 512 * 1024:
2805 return _PAGE_SZ512K_4U;
2806 case 4 * 1024 * 1024:
2807 return _PAGE_SZ4MB_4U;
2808 }
2809 }
2810}
2811
2812pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2813{
2814 pte_t pte;
2815
2816 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2817 pte_val(pte) |= (((unsigned long)space) << 32);
2818 pte_val(pte) |= pte_sz_bits(page_size);
2819
2820 return pte;
2821}
2822
2823static unsigned long kern_large_tte(unsigned long paddr)
2824{
2825 unsigned long val;
2826
2827 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2828 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2829 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2830 if (tlb_type == hypervisor)
2831 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2832 page_cache4v_flag | _PAGE_P_4V |
2833 _PAGE_EXEC_4V | _PAGE_W_4V);
2834
2835 return val | paddr;
2836}
2837
2838/* If not locked, zap it. */
2839void __flush_tlb_all(void)
2840{
2841 unsigned long pstate;
2842 int i;
2843
2844 __asm__ __volatile__("flushw\n\t"
2845 "rdpr %%pstate, %0\n\t"
2846 "wrpr %0, %1, %%pstate"
2847 : "=r" (pstate)
2848 : "i" (PSTATE_IE));
2849 if (tlb_type == hypervisor) {
2850 sun4v_mmu_demap_all();
2851 } else if (tlb_type == spitfire) {
2852 for (i = 0; i < 64; i++) {
2853 /* Spitfire Errata #32 workaround */
2854 /* NOTE: Always runs on spitfire, so no
2855 * cheetah+ page size encodings.
2856 */
2857 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2858 "flush %%g6"
2859 : /* No outputs */
2860 : "r" (0),
2861 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2862
2863 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2864 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2865 "membar #Sync"
2866 : /* no outputs */
2867 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2868 spitfire_put_dtlb_data(i, 0x0UL);
2869 }
2870
2871 /* Spitfire Errata #32 workaround */
2872 /* NOTE: Always runs on spitfire, so no
2873 * cheetah+ page size encodings.
2874 */
2875 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2876 "flush %%g6"
2877 : /* No outputs */
2878 : "r" (0),
2879 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2880
2881 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2882 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2883 "membar #Sync"
2884 : /* no outputs */
2885 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2886 spitfire_put_itlb_data(i, 0x0UL);
2887 }
2888 }
2889 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2890 cheetah_flush_dtlb_all();
2891 cheetah_flush_itlb_all();
2892 }
2893 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2894 : : "r" (pstate));
2895}
2896
2897pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2898{
2899 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2900 pte_t *pte = NULL;
2901
2902 if (page)
2903 pte = (pte_t *) page_address(page);
2904
2905 return pte;
2906}
2907
2908pgtable_t pte_alloc_one(struct mm_struct *mm)
2909{
2910 struct ptdesc *ptdesc = pagetable_alloc(GFP_KERNEL | __GFP_ZERO, 0);
2911
2912 if (!ptdesc)
2913 return NULL;
2914 if (!pagetable_pte_ctor(ptdesc)) {
2915 pagetable_free(ptdesc);
2916 return NULL;
2917 }
2918 return ptdesc_address(ptdesc);
2919}
2920
2921void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2922{
2923 free_page((unsigned long)pte);
2924}
2925
2926static void __pte_free(pgtable_t pte)
2927{
2928 struct ptdesc *ptdesc = virt_to_ptdesc(pte);
2929
2930 pagetable_pte_dtor(ptdesc);
2931 pagetable_free(ptdesc);
2932}
2933
2934void pte_free(struct mm_struct *mm, pgtable_t pte)
2935{
2936 __pte_free(pte);
2937}
2938
2939void pgtable_free(void *table, bool is_page)
2940{
2941 if (is_page)
2942 __pte_free(table);
2943 else
2944 kmem_cache_free(pgtable_cache, table);
2945}
2946
2947#ifdef CONFIG_TRANSPARENT_HUGEPAGE
2948static void pte_free_now(struct rcu_head *head)
2949{
2950 struct page *page;
2951
2952 page = container_of(head, struct page, rcu_head);
2953 __pte_free((pgtable_t)page_address(page));
2954}
2955
2956void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable)
2957{
2958 struct page *page;
2959
2960 page = virt_to_page(pgtable);
2961 call_rcu(&page->rcu_head, pte_free_now);
2962}
2963
2964void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2965 pmd_t *pmd)
2966{
2967 unsigned long pte, flags;
2968 struct mm_struct *mm;
2969 pmd_t entry = *pmd;
2970
2971 if (!pmd_large(entry) || !pmd_young(entry))
2972 return;
2973
2974 pte = pmd_val(entry);
2975
2976 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2977 if (!(pte & _PAGE_VALID))
2978 return;
2979
2980 /* We are fabricating 8MB pages using 4MB real hw pages. */
2981 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2982
2983 mm = vma->vm_mm;
2984
2985 spin_lock_irqsave(&mm->context.lock, flags);
2986
2987 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2988 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2989 addr, pte);
2990
2991 spin_unlock_irqrestore(&mm->context.lock, flags);
2992}
2993#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2994
2995#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2996static void context_reload(void *__data)
2997{
2998 struct mm_struct *mm = __data;
2999
3000 if (mm == current->mm)
3001 load_secondary_context(mm);
3002}
3003
3004void hugetlb_setup(struct pt_regs *regs)
3005{
3006 struct mm_struct *mm = current->mm;
3007 struct tsb_config *tp;
3008
3009 if (faulthandler_disabled() || !mm) {
3010 const struct exception_table_entry *entry;
3011
3012 entry = search_exception_tables(regs->tpc);
3013 if (entry) {
3014 regs->tpc = entry->fixup;
3015 regs->tnpc = regs->tpc + 4;
3016 return;
3017 }
3018 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
3019 die_if_kernel("HugeTSB in atomic", regs);
3020 }
3021
3022 tp = &mm->context.tsb_block[MM_TSB_HUGE];
3023 if (likely(tp->tsb == NULL))
3024 tsb_grow(mm, MM_TSB_HUGE, 0);
3025
3026 tsb_context_switch(mm);
3027 smp_tsb_sync(mm);
3028
3029 /* On UltraSPARC-III+ and later, configure the second half of
3030 * the Data-TLB for huge pages.
3031 */
3032 if (tlb_type == cheetah_plus) {
3033 bool need_context_reload = false;
3034 unsigned long ctx;
3035
3036 spin_lock_irq(&ctx_alloc_lock);
3037 ctx = mm->context.sparc64_ctx_val;
3038 ctx &= ~CTX_PGSZ_MASK;
3039 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3040 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3041
3042 if (ctx != mm->context.sparc64_ctx_val) {
3043 /* When changing the page size fields, we
3044 * must perform a context flush so that no
3045 * stale entries match. This flush must
3046 * occur with the original context register
3047 * settings.
3048 */
3049 do_flush_tlb_mm(mm);
3050
3051 /* Reload the context register of all processors
3052 * also executing in this address space.
3053 */
3054 mm->context.sparc64_ctx_val = ctx;
3055 need_context_reload = true;
3056 }
3057 spin_unlock_irq(&ctx_alloc_lock);
3058
3059 if (need_context_reload)
3060 on_each_cpu(context_reload, mm, 0);
3061 }
3062}
3063#endif
3064
3065static struct resource code_resource = {
3066 .name = "Kernel code",
3067 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3068};
3069
3070static struct resource data_resource = {
3071 .name = "Kernel data",
3072 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3073};
3074
3075static struct resource bss_resource = {
3076 .name = "Kernel bss",
3077 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3078};
3079
3080static inline resource_size_t compute_kern_paddr(void *addr)
3081{
3082 return (resource_size_t) (addr - KERNBASE + kern_base);
3083}
3084
3085static void __init kernel_lds_init(void)
3086{
3087 code_resource.start = compute_kern_paddr(_text);
3088 code_resource.end = compute_kern_paddr(_etext - 1);
3089 data_resource.start = compute_kern_paddr(_etext);
3090 data_resource.end = compute_kern_paddr(_edata - 1);
3091 bss_resource.start = compute_kern_paddr(__bss_start);
3092 bss_resource.end = compute_kern_paddr(_end - 1);
3093}
3094
3095static int __init report_memory(void)
3096{
3097 int i;
3098 struct resource *res;
3099
3100 kernel_lds_init();
3101
3102 for (i = 0; i < pavail_ents; i++) {
3103 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3104
3105 if (!res) {
3106 pr_warn("Failed to allocate source.\n");
3107 break;
3108 }
3109
3110 res->name = "System RAM";
3111 res->start = pavail[i].phys_addr;
3112 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3113 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3114
3115 if (insert_resource(&iomem_resource, res) < 0) {
3116 pr_warn("Resource insertion failed.\n");
3117 break;
3118 }
3119
3120 insert_resource(res, &code_resource);
3121 insert_resource(res, &data_resource);
3122 insert_resource(res, &bss_resource);
3123 }
3124
3125 return 0;
3126}
3127arch_initcall(report_memory);
3128
3129#ifdef CONFIG_SMP
3130#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3131#else
3132#define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3133#endif
3134
3135void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3136{
3137 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3138 if (start < LOW_OBP_ADDRESS) {
3139 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3140 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3141 }
3142 if (end > HI_OBP_ADDRESS) {
3143 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3144 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3145 }
3146 } else {
3147 flush_tsb_kernel_range(start, end);
3148 do_flush_tlb_kernel_range(start, end);
3149 }
3150}
3151
3152void copy_user_highpage(struct page *to, struct page *from,
3153 unsigned long vaddr, struct vm_area_struct *vma)
3154{
3155 char *vfrom, *vto;
3156
3157 vfrom = kmap_atomic(from);
3158 vto = kmap_atomic(to);
3159 copy_user_page(vto, vfrom, vaddr, to);
3160 kunmap_atomic(vto);
3161 kunmap_atomic(vfrom);
3162
3163 /* If this page has ADI enabled, copy over any ADI tags
3164 * as well
3165 */
3166 if (vma->vm_flags & VM_SPARC_ADI) {
3167 unsigned long pfrom, pto, i, adi_tag;
3168
3169 pfrom = page_to_phys(from);
3170 pto = page_to_phys(to);
3171
3172 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3173 asm volatile("ldxa [%1] %2, %0\n\t"
3174 : "=r" (adi_tag)
3175 : "r" (i), "i" (ASI_MCD_REAL));
3176 asm volatile("stxa %0, [%1] %2\n\t"
3177 :
3178 : "r" (adi_tag), "r" (pto),
3179 "i" (ASI_MCD_REAL));
3180 pto += adi_blksize();
3181 }
3182 asm volatile("membar #Sync\n\t");
3183 }
3184}
3185EXPORT_SYMBOL(copy_user_highpage);
3186
3187void copy_highpage(struct page *to, struct page *from)
3188{
3189 char *vfrom, *vto;
3190
3191 vfrom = kmap_atomic(from);
3192 vto = kmap_atomic(to);
3193 copy_page(vto, vfrom);
3194 kunmap_atomic(vto);
3195 kunmap_atomic(vfrom);
3196
3197 /* If this platform is ADI enabled, copy any ADI tags
3198 * as well
3199 */
3200 if (adi_capable()) {
3201 unsigned long pfrom, pto, i, adi_tag;
3202
3203 pfrom = page_to_phys(from);
3204 pto = page_to_phys(to);
3205
3206 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3207 asm volatile("ldxa [%1] %2, %0\n\t"
3208 : "=r" (adi_tag)
3209 : "r" (i), "i" (ASI_MCD_REAL));
3210 asm volatile("stxa %0, [%1] %2\n\t"
3211 :
3212 : "r" (adi_tag), "r" (pto),
3213 "i" (ASI_MCD_REAL));
3214 pto += adi_blksize();
3215 }
3216 asm volatile("membar #Sync\n\t");
3217 }
3218}
3219EXPORT_SYMBOL(copy_highpage);
3220
3221pgprot_t vm_get_page_prot(unsigned long vm_flags)
3222{
3223 unsigned long prot = pgprot_val(protection_map[vm_flags &
3224 (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]);
3225
3226 if (vm_flags & VM_SPARC_ADI)
3227 prot |= _PAGE_MCD_4V;
3228
3229 return __pgprot(prot);
3230}
3231EXPORT_SYMBOL(vm_get_page_prot);
1/*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/initrd.h>
17#include <linux/swap.h>
18#include <linux/pagemap.h>
19#include <linux/poison.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
22#include <linux/kprobes.h>
23#include <linux/cache.h>
24#include <linux/sort.h>
25#include <linux/ioport.h>
26#include <linux/percpu.h>
27#include <linux/memblock.h>
28#include <linux/mmzone.h>
29#include <linux/gfp.h>
30
31#include <asm/head.h>
32#include <asm/page.h>
33#include <asm/pgalloc.h>
34#include <asm/pgtable.h>
35#include <asm/oplib.h>
36#include <asm/iommu.h>
37#include <asm/io.h>
38#include <asm/uaccess.h>
39#include <asm/mmu_context.h>
40#include <asm/tlbflush.h>
41#include <asm/dma.h>
42#include <asm/starfire.h>
43#include <asm/tlb.h>
44#include <asm/spitfire.h>
45#include <asm/sections.h>
46#include <asm/tsb.h>
47#include <asm/hypervisor.h>
48#include <asm/prom.h>
49#include <asm/mdesc.h>
50#include <asm/cpudata.h>
51#include <asm/setup.h>
52#include <asm/irq.h>
53
54#include "init_64.h"
55
56unsigned long kern_linear_pte_xor[4] __read_mostly;
57static unsigned long page_cache4v_flag;
58
59/* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
64 *
65 * 0 ==> 4MB
66 * 1 ==> 256MB
67 * 2 ==> 2GB
68 * 3 ==> 16GB
69 *
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
74 *
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
78 */
79
80#ifndef CONFIG_DEBUG_PAGEALLOC
81/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
84 */
85extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
86#endif
87extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
88
89static unsigned long cpu_pgsz_mask;
90
91#define MAX_BANKS 1024
92
93static struct linux_prom64_registers pavail[MAX_BANKS];
94static int pavail_ents;
95
96u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
97
98static int cmp_p64(const void *a, const void *b)
99{
100 const struct linux_prom64_registers *x = a, *y = b;
101
102 if (x->phys_addr > y->phys_addr)
103 return 1;
104 if (x->phys_addr < y->phys_addr)
105 return -1;
106 return 0;
107}
108
109static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
111 int *num_ents)
112{
113 phandle node = prom_finddevice("/memory");
114 int prop_size = prom_getproplen(node, property);
115 int ents, ret, i;
116
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
122 prom_halt();
123 }
124
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
126 if (ret == -1) {
127 prom_printf("Couldn't get %s property from /memory.\n",
128 property);
129 prom_halt();
130 }
131
132 /* Sanitize what we got from the firmware, by page aligning
133 * everything.
134 */
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
137
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
140
141 size &= PAGE_MASK;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
144
145 size -= new_base - base;
146 if ((long) size < 0L)
147 size = 0UL;
148 base = new_base;
149 }
150 if (size == 0UL) {
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
154 */
155 memmove(®s[i], ®s[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
157 i--;
158 ents--;
159 continue;
160 }
161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
163 }
164
165 *num_ents = ents;
166
167 sort(regs, ents, sizeof(struct linux_prom64_registers),
168 cmp_p64, NULL);
169}
170
171/* Kernel physical address base and size in bytes. */
172unsigned long kern_base __read_mostly;
173unsigned long kern_size __read_mostly;
174
175/* Initial ramdisk setup */
176extern unsigned long sparc_ramdisk_image64;
177extern unsigned int sparc_ramdisk_image;
178extern unsigned int sparc_ramdisk_size;
179
180struct page *mem_map_zero __read_mostly;
181EXPORT_SYMBOL(mem_map_zero);
182
183unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
184
185unsigned long sparc64_kern_pri_context __read_mostly;
186unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187unsigned long sparc64_kern_sec_context __read_mostly;
188
189int num_kernel_image_mappings;
190
191#ifdef CONFIG_DEBUG_DCFLUSH
192atomic_t dcpage_flushes = ATOMIC_INIT(0);
193#ifdef CONFIG_SMP
194atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
195#endif
196#endif
197
198inline void flush_dcache_page_impl(struct page *page)
199{
200 BUG_ON(tlb_type == hypervisor);
201#ifdef CONFIG_DEBUG_DCFLUSH
202 atomic_inc(&dcpage_flushes);
203#endif
204
205#ifdef DCACHE_ALIASING_POSSIBLE
206 __flush_dcache_page(page_address(page),
207 ((tlb_type == spitfire) &&
208 page_mapping(page) != NULL));
209#else
210 if (page_mapping(page) != NULL &&
211 tlb_type == spitfire)
212 __flush_icache_page(__pa(page_address(page)));
213#endif
214}
215
216#define PG_dcache_dirty PG_arch_1
217#define PG_dcache_cpu_shift 32UL
218#define PG_dcache_cpu_mask \
219 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
220
221#define dcache_dirty_cpu(page) \
222 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
223
224static inline void set_dcache_dirty(struct page *page, int this_cpu)
225{
226 unsigned long mask = this_cpu;
227 unsigned long non_cpu_bits;
228
229 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
230 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
231
232 __asm__ __volatile__("1:\n\t"
233 "ldx [%2], %%g7\n\t"
234 "and %%g7, %1, %%g1\n\t"
235 "or %%g1, %0, %%g1\n\t"
236 "casx [%2], %%g7, %%g1\n\t"
237 "cmp %%g7, %%g1\n\t"
238 "bne,pn %%xcc, 1b\n\t"
239 " nop"
240 : /* no outputs */
241 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
242 : "g1", "g7");
243}
244
245static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
246{
247 unsigned long mask = (1UL << PG_dcache_dirty);
248
249 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
250 "1:\n\t"
251 "ldx [%2], %%g7\n\t"
252 "srlx %%g7, %4, %%g1\n\t"
253 "and %%g1, %3, %%g1\n\t"
254 "cmp %%g1, %0\n\t"
255 "bne,pn %%icc, 2f\n\t"
256 " andn %%g7, %1, %%g1\n\t"
257 "casx [%2], %%g7, %%g1\n\t"
258 "cmp %%g7, %%g1\n\t"
259 "bne,pn %%xcc, 1b\n\t"
260 " nop\n"
261 "2:"
262 : /* no outputs */
263 : "r" (cpu), "r" (mask), "r" (&page->flags),
264 "i" (PG_dcache_cpu_mask),
265 "i" (PG_dcache_cpu_shift)
266 : "g1", "g7");
267}
268
269static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
270{
271 unsigned long tsb_addr = (unsigned long) ent;
272
273 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
274 tsb_addr = __pa(tsb_addr);
275
276 __tsb_insert(tsb_addr, tag, pte);
277}
278
279unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
280
281static void flush_dcache(unsigned long pfn)
282{
283 struct page *page;
284
285 page = pfn_to_page(pfn);
286 if (page) {
287 unsigned long pg_flags;
288
289 pg_flags = page->flags;
290 if (pg_flags & (1UL << PG_dcache_dirty)) {
291 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
292 PG_dcache_cpu_mask);
293 int this_cpu = get_cpu();
294
295 /* This is just to optimize away some function calls
296 * in the SMP case.
297 */
298 if (cpu == this_cpu)
299 flush_dcache_page_impl(page);
300 else
301 smp_flush_dcache_page_impl(page, cpu);
302
303 clear_dcache_dirty_cpu(page, cpu);
304
305 put_cpu();
306 }
307 }
308}
309
310/* mm->context.lock must be held */
311static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
312 unsigned long tsb_hash_shift, unsigned long address,
313 unsigned long tte)
314{
315 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
316 unsigned long tag;
317
318 if (unlikely(!tsb))
319 return;
320
321 tsb += ((address >> tsb_hash_shift) &
322 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
323 tag = (address >> 22UL);
324 tsb_insert(tsb, tag, tte);
325}
326
327#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
328static inline bool is_hugetlb_pte(pte_t pte)
329{
330 if ((tlb_type == hypervisor &&
331 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
332 (tlb_type != hypervisor &&
333 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
334 return true;
335 return false;
336}
337#endif
338
339void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
340{
341 struct mm_struct *mm;
342 unsigned long flags;
343 pte_t pte = *ptep;
344
345 if (tlb_type != hypervisor) {
346 unsigned long pfn = pte_pfn(pte);
347
348 if (pfn_valid(pfn))
349 flush_dcache(pfn);
350 }
351
352 mm = vma->vm_mm;
353
354 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
355 if (!pte_accessible(mm, pte))
356 return;
357
358 spin_lock_irqsave(&mm->context.lock, flags);
359
360#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
361 if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
362 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
363 address, pte_val(pte));
364 else
365#endif
366 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
367 address, pte_val(pte));
368
369 spin_unlock_irqrestore(&mm->context.lock, flags);
370}
371
372void flush_dcache_page(struct page *page)
373{
374 struct address_space *mapping;
375 int this_cpu;
376
377 if (tlb_type == hypervisor)
378 return;
379
380 /* Do not bother with the expensive D-cache flush if it
381 * is merely the zero page. The 'bigcore' testcase in GDB
382 * causes this case to run millions of times.
383 */
384 if (page == ZERO_PAGE(0))
385 return;
386
387 this_cpu = get_cpu();
388
389 mapping = page_mapping(page);
390 if (mapping && !mapping_mapped(mapping)) {
391 int dirty = test_bit(PG_dcache_dirty, &page->flags);
392 if (dirty) {
393 int dirty_cpu = dcache_dirty_cpu(page);
394
395 if (dirty_cpu == this_cpu)
396 goto out;
397 smp_flush_dcache_page_impl(page, dirty_cpu);
398 }
399 set_dcache_dirty(page, this_cpu);
400 } else {
401 /* We could delay the flush for the !page_mapping
402 * case too. But that case is for exec env/arg
403 * pages and those are %99 certainly going to get
404 * faulted into the tlb (and thus flushed) anyways.
405 */
406 flush_dcache_page_impl(page);
407 }
408
409out:
410 put_cpu();
411}
412EXPORT_SYMBOL(flush_dcache_page);
413
414void __kprobes flush_icache_range(unsigned long start, unsigned long end)
415{
416 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
417 if (tlb_type == spitfire) {
418 unsigned long kaddr;
419
420 /* This code only runs on Spitfire cpus so this is
421 * why we can assume _PAGE_PADDR_4U.
422 */
423 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
424 unsigned long paddr, mask = _PAGE_PADDR_4U;
425
426 if (kaddr >= PAGE_OFFSET)
427 paddr = kaddr & mask;
428 else {
429 pgd_t *pgdp = pgd_offset_k(kaddr);
430 pud_t *pudp = pud_offset(pgdp, kaddr);
431 pmd_t *pmdp = pmd_offset(pudp, kaddr);
432 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
433
434 paddr = pte_val(*ptep) & mask;
435 }
436 __flush_icache_page(paddr);
437 }
438 }
439}
440EXPORT_SYMBOL(flush_icache_range);
441
442void mmu_info(struct seq_file *m)
443{
444 static const char *pgsz_strings[] = {
445 "8K", "64K", "512K", "4MB", "32MB",
446 "256MB", "2GB", "16GB",
447 };
448 int i, printed;
449
450 if (tlb_type == cheetah)
451 seq_printf(m, "MMU Type\t: Cheetah\n");
452 else if (tlb_type == cheetah_plus)
453 seq_printf(m, "MMU Type\t: Cheetah+\n");
454 else if (tlb_type == spitfire)
455 seq_printf(m, "MMU Type\t: Spitfire\n");
456 else if (tlb_type == hypervisor)
457 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
458 else
459 seq_printf(m, "MMU Type\t: ???\n");
460
461 seq_printf(m, "MMU PGSZs\t: ");
462 printed = 0;
463 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
464 if (cpu_pgsz_mask & (1UL << i)) {
465 seq_printf(m, "%s%s",
466 printed ? "," : "", pgsz_strings[i]);
467 printed++;
468 }
469 }
470 seq_putc(m, '\n');
471
472#ifdef CONFIG_DEBUG_DCFLUSH
473 seq_printf(m, "DCPageFlushes\t: %d\n",
474 atomic_read(&dcpage_flushes));
475#ifdef CONFIG_SMP
476 seq_printf(m, "DCPageFlushesXC\t: %d\n",
477 atomic_read(&dcpage_flushes_xcall));
478#endif /* CONFIG_SMP */
479#endif /* CONFIG_DEBUG_DCFLUSH */
480}
481
482struct linux_prom_translation prom_trans[512] __read_mostly;
483unsigned int prom_trans_ents __read_mostly;
484
485unsigned long kern_locked_tte_data;
486
487/* The obp translations are saved based on 8k pagesize, since obp can
488 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
489 * HI_OBP_ADDRESS range are handled in ktlb.S.
490 */
491static inline int in_obp_range(unsigned long vaddr)
492{
493 return (vaddr >= LOW_OBP_ADDRESS &&
494 vaddr < HI_OBP_ADDRESS);
495}
496
497static int cmp_ptrans(const void *a, const void *b)
498{
499 const struct linux_prom_translation *x = a, *y = b;
500
501 if (x->virt > y->virt)
502 return 1;
503 if (x->virt < y->virt)
504 return -1;
505 return 0;
506}
507
508/* Read OBP translations property into 'prom_trans[]'. */
509static void __init read_obp_translations(void)
510{
511 int n, node, ents, first, last, i;
512
513 node = prom_finddevice("/virtual-memory");
514 n = prom_getproplen(node, "translations");
515 if (unlikely(n == 0 || n == -1)) {
516 prom_printf("prom_mappings: Couldn't get size.\n");
517 prom_halt();
518 }
519 if (unlikely(n > sizeof(prom_trans))) {
520 prom_printf("prom_mappings: Size %d is too big.\n", n);
521 prom_halt();
522 }
523
524 if ((n = prom_getproperty(node, "translations",
525 (char *)&prom_trans[0],
526 sizeof(prom_trans))) == -1) {
527 prom_printf("prom_mappings: Couldn't get property.\n");
528 prom_halt();
529 }
530
531 n = n / sizeof(struct linux_prom_translation);
532
533 ents = n;
534
535 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
536 cmp_ptrans, NULL);
537
538 /* Now kick out all the non-OBP entries. */
539 for (i = 0; i < ents; i++) {
540 if (in_obp_range(prom_trans[i].virt))
541 break;
542 }
543 first = i;
544 for (; i < ents; i++) {
545 if (!in_obp_range(prom_trans[i].virt))
546 break;
547 }
548 last = i;
549
550 for (i = 0; i < (last - first); i++) {
551 struct linux_prom_translation *src = &prom_trans[i + first];
552 struct linux_prom_translation *dest = &prom_trans[i];
553
554 *dest = *src;
555 }
556 for (; i < ents; i++) {
557 struct linux_prom_translation *dest = &prom_trans[i];
558 dest->virt = dest->size = dest->data = 0x0UL;
559 }
560
561 prom_trans_ents = last - first;
562
563 if (tlb_type == spitfire) {
564 /* Clear diag TTE bits. */
565 for (i = 0; i < prom_trans_ents; i++)
566 prom_trans[i].data &= ~0x0003fe0000000000UL;
567 }
568
569 /* Force execute bit on. */
570 for (i = 0; i < prom_trans_ents; i++)
571 prom_trans[i].data |= (tlb_type == hypervisor ?
572 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
573}
574
575static void __init hypervisor_tlb_lock(unsigned long vaddr,
576 unsigned long pte,
577 unsigned long mmu)
578{
579 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
580
581 if (ret != 0) {
582 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
583 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
584 prom_halt();
585 }
586}
587
588static unsigned long kern_large_tte(unsigned long paddr);
589
590static void __init remap_kernel(void)
591{
592 unsigned long phys_page, tte_vaddr, tte_data;
593 int i, tlb_ent = sparc64_highest_locked_tlbent();
594
595 tte_vaddr = (unsigned long) KERNBASE;
596 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
597 tte_data = kern_large_tte(phys_page);
598
599 kern_locked_tte_data = tte_data;
600
601 /* Now lock us into the TLBs via Hypervisor or OBP. */
602 if (tlb_type == hypervisor) {
603 for (i = 0; i < num_kernel_image_mappings; i++) {
604 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
605 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
606 tte_vaddr += 0x400000;
607 tte_data += 0x400000;
608 }
609 } else {
610 for (i = 0; i < num_kernel_image_mappings; i++) {
611 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
612 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
613 tte_vaddr += 0x400000;
614 tte_data += 0x400000;
615 }
616 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
617 }
618 if (tlb_type == cheetah_plus) {
619 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
620 CTX_CHEETAH_PLUS_NUC);
621 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
622 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
623 }
624}
625
626
627static void __init inherit_prom_mappings(void)
628{
629 /* Now fixup OBP's idea about where we really are mapped. */
630 printk("Remapping the kernel... ");
631 remap_kernel();
632 printk("done.\n");
633}
634
635void prom_world(int enter)
636{
637 if (!enter)
638 set_fs(get_fs());
639
640 __asm__ __volatile__("flushw");
641}
642
643void __flush_dcache_range(unsigned long start, unsigned long end)
644{
645 unsigned long va;
646
647 if (tlb_type == spitfire) {
648 int n = 0;
649
650 for (va = start; va < end; va += 32) {
651 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
652 if (++n >= 512)
653 break;
654 }
655 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
656 start = __pa(start);
657 end = __pa(end);
658 for (va = start; va < end; va += 32)
659 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
660 "membar #Sync"
661 : /* no outputs */
662 : "r" (va),
663 "i" (ASI_DCACHE_INVALIDATE));
664 }
665}
666EXPORT_SYMBOL(__flush_dcache_range);
667
668/* get_new_mmu_context() uses "cache + 1". */
669DEFINE_SPINLOCK(ctx_alloc_lock);
670unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
671#define MAX_CTX_NR (1UL << CTX_NR_BITS)
672#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
673DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
674
675/* Caller does TLB context flushing on local CPU if necessary.
676 * The caller also ensures that CTX_VALID(mm->context) is false.
677 *
678 * We must be careful about boundary cases so that we never
679 * let the user have CTX 0 (nucleus) or we ever use a CTX
680 * version of zero (and thus NO_CONTEXT would not be caught
681 * by version mis-match tests in mmu_context.h).
682 *
683 * Always invoked with interrupts disabled.
684 */
685void get_new_mmu_context(struct mm_struct *mm)
686{
687 unsigned long ctx, new_ctx;
688 unsigned long orig_pgsz_bits;
689 int new_version;
690
691 spin_lock(&ctx_alloc_lock);
692 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
693 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
694 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
695 new_version = 0;
696 if (new_ctx >= (1 << CTX_NR_BITS)) {
697 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
698 if (new_ctx >= ctx) {
699 int i;
700 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
701 CTX_FIRST_VERSION;
702 if (new_ctx == 1)
703 new_ctx = CTX_FIRST_VERSION;
704
705 /* Don't call memset, for 16 entries that's just
706 * plain silly...
707 */
708 mmu_context_bmap[0] = 3;
709 mmu_context_bmap[1] = 0;
710 mmu_context_bmap[2] = 0;
711 mmu_context_bmap[3] = 0;
712 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
713 mmu_context_bmap[i + 0] = 0;
714 mmu_context_bmap[i + 1] = 0;
715 mmu_context_bmap[i + 2] = 0;
716 mmu_context_bmap[i + 3] = 0;
717 }
718 new_version = 1;
719 goto out;
720 }
721 }
722 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
723 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
724out:
725 tlb_context_cache = new_ctx;
726 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
727 spin_unlock(&ctx_alloc_lock);
728
729 if (unlikely(new_version))
730 smp_new_mmu_context_version();
731}
732
733static int numa_enabled = 1;
734static int numa_debug;
735
736static int __init early_numa(char *p)
737{
738 if (!p)
739 return 0;
740
741 if (strstr(p, "off"))
742 numa_enabled = 0;
743
744 if (strstr(p, "debug"))
745 numa_debug = 1;
746
747 return 0;
748}
749early_param("numa", early_numa);
750
751#define numadbg(f, a...) \
752do { if (numa_debug) \
753 printk(KERN_INFO f, ## a); \
754} while (0)
755
756static void __init find_ramdisk(unsigned long phys_base)
757{
758#ifdef CONFIG_BLK_DEV_INITRD
759 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
760 unsigned long ramdisk_image;
761
762 /* Older versions of the bootloader only supported a
763 * 32-bit physical address for the ramdisk image
764 * location, stored at sparc_ramdisk_image. Newer
765 * SILO versions set sparc_ramdisk_image to zero and
766 * provide a full 64-bit physical address at
767 * sparc_ramdisk_image64.
768 */
769 ramdisk_image = sparc_ramdisk_image;
770 if (!ramdisk_image)
771 ramdisk_image = sparc_ramdisk_image64;
772
773 /* Another bootloader quirk. The bootloader normalizes
774 * the physical address to KERNBASE, so we have to
775 * factor that back out and add in the lowest valid
776 * physical page address to get the true physical address.
777 */
778 ramdisk_image -= KERNBASE;
779 ramdisk_image += phys_base;
780
781 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
782 ramdisk_image, sparc_ramdisk_size);
783
784 initrd_start = ramdisk_image;
785 initrd_end = ramdisk_image + sparc_ramdisk_size;
786
787 memblock_reserve(initrd_start, sparc_ramdisk_size);
788
789 initrd_start += PAGE_OFFSET;
790 initrd_end += PAGE_OFFSET;
791 }
792#endif
793}
794
795struct node_mem_mask {
796 unsigned long mask;
797 unsigned long val;
798};
799static struct node_mem_mask node_masks[MAX_NUMNODES];
800static int num_node_masks;
801
802#ifdef CONFIG_NEED_MULTIPLE_NODES
803
804int numa_cpu_lookup_table[NR_CPUS];
805cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
806
807struct mdesc_mblock {
808 u64 base;
809 u64 size;
810 u64 offset; /* RA-to-PA */
811};
812static struct mdesc_mblock *mblocks;
813static int num_mblocks;
814
815static unsigned long ra_to_pa(unsigned long addr)
816{
817 int i;
818
819 for (i = 0; i < num_mblocks; i++) {
820 struct mdesc_mblock *m = &mblocks[i];
821
822 if (addr >= m->base &&
823 addr < (m->base + m->size)) {
824 addr += m->offset;
825 break;
826 }
827 }
828 return addr;
829}
830
831static int find_node(unsigned long addr)
832{
833 int i;
834
835 addr = ra_to_pa(addr);
836 for (i = 0; i < num_node_masks; i++) {
837 struct node_mem_mask *p = &node_masks[i];
838
839 if ((addr & p->mask) == p->val)
840 return i;
841 }
842 /* The following condition has been observed on LDOM guests.*/
843 WARN_ONCE(1, "find_node: A physical address doesn't match a NUMA node"
844 " rule. Some physical memory will be owned by node 0.");
845 return 0;
846}
847
848static u64 memblock_nid_range(u64 start, u64 end, int *nid)
849{
850 *nid = find_node(start);
851 start += PAGE_SIZE;
852 while (start < end) {
853 int n = find_node(start);
854
855 if (n != *nid)
856 break;
857 start += PAGE_SIZE;
858 }
859
860 if (start > end)
861 start = end;
862
863 return start;
864}
865#endif
866
867/* This must be invoked after performing all of the necessary
868 * memblock_set_node() calls for 'nid'. We need to be able to get
869 * correct data from get_pfn_range_for_nid().
870 */
871static void __init allocate_node_data(int nid)
872{
873 struct pglist_data *p;
874 unsigned long start_pfn, end_pfn;
875#ifdef CONFIG_NEED_MULTIPLE_NODES
876 unsigned long paddr;
877
878 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
879 if (!paddr) {
880 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
881 prom_halt();
882 }
883 NODE_DATA(nid) = __va(paddr);
884 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
885
886 NODE_DATA(nid)->node_id = nid;
887#endif
888
889 p = NODE_DATA(nid);
890
891 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
892 p->node_start_pfn = start_pfn;
893 p->node_spanned_pages = end_pfn - start_pfn;
894}
895
896static void init_node_masks_nonnuma(void)
897{
898#ifdef CONFIG_NEED_MULTIPLE_NODES
899 int i;
900#endif
901
902 numadbg("Initializing tables for non-numa.\n");
903
904 node_masks[0].mask = node_masks[0].val = 0;
905 num_node_masks = 1;
906
907#ifdef CONFIG_NEED_MULTIPLE_NODES
908 for (i = 0; i < NR_CPUS; i++)
909 numa_cpu_lookup_table[i] = 0;
910
911 cpumask_setall(&numa_cpumask_lookup_table[0]);
912#endif
913}
914
915#ifdef CONFIG_NEED_MULTIPLE_NODES
916struct pglist_data *node_data[MAX_NUMNODES];
917
918EXPORT_SYMBOL(numa_cpu_lookup_table);
919EXPORT_SYMBOL(numa_cpumask_lookup_table);
920EXPORT_SYMBOL(node_data);
921
922struct mdesc_mlgroup {
923 u64 node;
924 u64 latency;
925 u64 match;
926 u64 mask;
927};
928static struct mdesc_mlgroup *mlgroups;
929static int num_mlgroups;
930
931static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
932 u32 cfg_handle)
933{
934 u64 arc;
935
936 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
937 u64 target = mdesc_arc_target(md, arc);
938 const u64 *val;
939
940 val = mdesc_get_property(md, target,
941 "cfg-handle", NULL);
942 if (val && *val == cfg_handle)
943 return 0;
944 }
945 return -ENODEV;
946}
947
948static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
949 u32 cfg_handle)
950{
951 u64 arc, candidate, best_latency = ~(u64)0;
952
953 candidate = MDESC_NODE_NULL;
954 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
955 u64 target = mdesc_arc_target(md, arc);
956 const char *name = mdesc_node_name(md, target);
957 const u64 *val;
958
959 if (strcmp(name, "pio-latency-group"))
960 continue;
961
962 val = mdesc_get_property(md, target, "latency", NULL);
963 if (!val)
964 continue;
965
966 if (*val < best_latency) {
967 candidate = target;
968 best_latency = *val;
969 }
970 }
971
972 if (candidate == MDESC_NODE_NULL)
973 return -ENODEV;
974
975 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
976}
977
978int of_node_to_nid(struct device_node *dp)
979{
980 const struct linux_prom64_registers *regs;
981 struct mdesc_handle *md;
982 u32 cfg_handle;
983 int count, nid;
984 u64 grp;
985
986 /* This is the right thing to do on currently supported
987 * SUN4U NUMA platforms as well, as the PCI controller does
988 * not sit behind any particular memory controller.
989 */
990 if (!mlgroups)
991 return -1;
992
993 regs = of_get_property(dp, "reg", NULL);
994 if (!regs)
995 return -1;
996
997 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
998
999 md = mdesc_grab();
1000
1001 count = 0;
1002 nid = -1;
1003 mdesc_for_each_node_by_name(md, grp, "group") {
1004 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1005 nid = count;
1006 break;
1007 }
1008 count++;
1009 }
1010
1011 mdesc_release(md);
1012
1013 return nid;
1014}
1015
1016static void __init add_node_ranges(void)
1017{
1018 struct memblock_region *reg;
1019
1020 for_each_memblock(memory, reg) {
1021 unsigned long size = reg->size;
1022 unsigned long start, end;
1023
1024 start = reg->base;
1025 end = start + size;
1026 while (start < end) {
1027 unsigned long this_end;
1028 int nid;
1029
1030 this_end = memblock_nid_range(start, end, &nid);
1031
1032 numadbg("Setting memblock NUMA node nid[%d] "
1033 "start[%lx] end[%lx]\n",
1034 nid, start, this_end);
1035
1036 memblock_set_node(start, this_end - start,
1037 &memblock.memory, nid);
1038 start = this_end;
1039 }
1040 }
1041}
1042
1043static int __init grab_mlgroups(struct mdesc_handle *md)
1044{
1045 unsigned long paddr;
1046 int count = 0;
1047 u64 node;
1048
1049 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1050 count++;
1051 if (!count)
1052 return -ENOENT;
1053
1054 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1055 SMP_CACHE_BYTES);
1056 if (!paddr)
1057 return -ENOMEM;
1058
1059 mlgroups = __va(paddr);
1060 num_mlgroups = count;
1061
1062 count = 0;
1063 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1064 struct mdesc_mlgroup *m = &mlgroups[count++];
1065 const u64 *val;
1066
1067 m->node = node;
1068
1069 val = mdesc_get_property(md, node, "latency", NULL);
1070 m->latency = *val;
1071 val = mdesc_get_property(md, node, "address-match", NULL);
1072 m->match = *val;
1073 val = mdesc_get_property(md, node, "address-mask", NULL);
1074 m->mask = *val;
1075
1076 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1077 "match[%llx] mask[%llx]\n",
1078 count - 1, m->node, m->latency, m->match, m->mask);
1079 }
1080
1081 return 0;
1082}
1083
1084static int __init grab_mblocks(struct mdesc_handle *md)
1085{
1086 unsigned long paddr;
1087 int count = 0;
1088 u64 node;
1089
1090 mdesc_for_each_node_by_name(md, node, "mblock")
1091 count++;
1092 if (!count)
1093 return -ENOENT;
1094
1095 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1096 SMP_CACHE_BYTES);
1097 if (!paddr)
1098 return -ENOMEM;
1099
1100 mblocks = __va(paddr);
1101 num_mblocks = count;
1102
1103 count = 0;
1104 mdesc_for_each_node_by_name(md, node, "mblock") {
1105 struct mdesc_mblock *m = &mblocks[count++];
1106 const u64 *val;
1107
1108 val = mdesc_get_property(md, node, "base", NULL);
1109 m->base = *val;
1110 val = mdesc_get_property(md, node, "size", NULL);
1111 m->size = *val;
1112 val = mdesc_get_property(md, node,
1113 "address-congruence-offset", NULL);
1114
1115 /* The address-congruence-offset property is optional.
1116 * Explicity zero it be identifty this.
1117 */
1118 if (val)
1119 m->offset = *val;
1120 else
1121 m->offset = 0UL;
1122
1123 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1124 count - 1, m->base, m->size, m->offset);
1125 }
1126
1127 return 0;
1128}
1129
1130static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1131 u64 grp, cpumask_t *mask)
1132{
1133 u64 arc;
1134
1135 cpumask_clear(mask);
1136
1137 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1138 u64 target = mdesc_arc_target(md, arc);
1139 const char *name = mdesc_node_name(md, target);
1140 const u64 *id;
1141
1142 if (strcmp(name, "cpu"))
1143 continue;
1144 id = mdesc_get_property(md, target, "id", NULL);
1145 if (*id < nr_cpu_ids)
1146 cpumask_set_cpu(*id, mask);
1147 }
1148}
1149
1150static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1151{
1152 int i;
1153
1154 for (i = 0; i < num_mlgroups; i++) {
1155 struct mdesc_mlgroup *m = &mlgroups[i];
1156 if (m->node == node)
1157 return m;
1158 }
1159 return NULL;
1160}
1161
1162int __node_distance(int from, int to)
1163{
1164 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1165 pr_warn("Returning default NUMA distance value for %d->%d\n",
1166 from, to);
1167 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1168 }
1169 return numa_latency[from][to];
1170}
1171
1172static int find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1173{
1174 int i;
1175
1176 for (i = 0; i < MAX_NUMNODES; i++) {
1177 struct node_mem_mask *n = &node_masks[i];
1178
1179 if ((grp->mask == n->mask) && (grp->match == n->val))
1180 break;
1181 }
1182 return i;
1183}
1184
1185static void find_numa_latencies_for_group(struct mdesc_handle *md, u64 grp,
1186 int index)
1187{
1188 u64 arc;
1189
1190 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1191 int tnode;
1192 u64 target = mdesc_arc_target(md, arc);
1193 struct mdesc_mlgroup *m = find_mlgroup(target);
1194
1195 if (!m)
1196 continue;
1197 tnode = find_best_numa_node_for_mlgroup(m);
1198 if (tnode == MAX_NUMNODES)
1199 continue;
1200 numa_latency[index][tnode] = m->latency;
1201 }
1202}
1203
1204static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1205 int index)
1206{
1207 struct mdesc_mlgroup *candidate = NULL;
1208 u64 arc, best_latency = ~(u64)0;
1209 struct node_mem_mask *n;
1210
1211 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1212 u64 target = mdesc_arc_target(md, arc);
1213 struct mdesc_mlgroup *m = find_mlgroup(target);
1214 if (!m)
1215 continue;
1216 if (m->latency < best_latency) {
1217 candidate = m;
1218 best_latency = m->latency;
1219 }
1220 }
1221 if (!candidate)
1222 return -ENOENT;
1223
1224 if (num_node_masks != index) {
1225 printk(KERN_ERR "Inconsistent NUMA state, "
1226 "index[%d] != num_node_masks[%d]\n",
1227 index, num_node_masks);
1228 return -EINVAL;
1229 }
1230
1231 n = &node_masks[num_node_masks++];
1232
1233 n->mask = candidate->mask;
1234 n->val = candidate->match;
1235
1236 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1237 index, n->mask, n->val, candidate->latency);
1238
1239 return 0;
1240}
1241
1242static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1243 int index)
1244{
1245 cpumask_t mask;
1246 int cpu;
1247
1248 numa_parse_mdesc_group_cpus(md, grp, &mask);
1249
1250 for_each_cpu(cpu, &mask)
1251 numa_cpu_lookup_table[cpu] = index;
1252 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1253
1254 if (numa_debug) {
1255 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1256 for_each_cpu(cpu, &mask)
1257 printk("%d ", cpu);
1258 printk("]\n");
1259 }
1260
1261 return numa_attach_mlgroup(md, grp, index);
1262}
1263
1264static int __init numa_parse_mdesc(void)
1265{
1266 struct mdesc_handle *md = mdesc_grab();
1267 int i, j, err, count;
1268 u64 node;
1269
1270 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1271 if (node == MDESC_NODE_NULL) {
1272 mdesc_release(md);
1273 return -ENOENT;
1274 }
1275
1276 err = grab_mblocks(md);
1277 if (err < 0)
1278 goto out;
1279
1280 err = grab_mlgroups(md);
1281 if (err < 0)
1282 goto out;
1283
1284 count = 0;
1285 mdesc_for_each_node_by_name(md, node, "group") {
1286 err = numa_parse_mdesc_group(md, node, count);
1287 if (err < 0)
1288 break;
1289 count++;
1290 }
1291
1292 count = 0;
1293 mdesc_for_each_node_by_name(md, node, "group") {
1294 find_numa_latencies_for_group(md, node, count);
1295 count++;
1296 }
1297
1298 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1299 for (i = 0; i < MAX_NUMNODES; i++) {
1300 u64 self_latency = numa_latency[i][i];
1301
1302 for (j = 0; j < MAX_NUMNODES; j++) {
1303 numa_latency[i][j] =
1304 (numa_latency[i][j] * LOCAL_DISTANCE) /
1305 self_latency;
1306 }
1307 }
1308
1309 add_node_ranges();
1310
1311 for (i = 0; i < num_node_masks; i++) {
1312 allocate_node_data(i);
1313 node_set_online(i);
1314 }
1315
1316 err = 0;
1317out:
1318 mdesc_release(md);
1319 return err;
1320}
1321
1322static int __init numa_parse_jbus(void)
1323{
1324 unsigned long cpu, index;
1325
1326 /* NUMA node id is encoded in bits 36 and higher, and there is
1327 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1328 */
1329 index = 0;
1330 for_each_present_cpu(cpu) {
1331 numa_cpu_lookup_table[cpu] = index;
1332 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1333 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1334 node_masks[index].val = cpu << 36UL;
1335
1336 index++;
1337 }
1338 num_node_masks = index;
1339
1340 add_node_ranges();
1341
1342 for (index = 0; index < num_node_masks; index++) {
1343 allocate_node_data(index);
1344 node_set_online(index);
1345 }
1346
1347 return 0;
1348}
1349
1350static int __init numa_parse_sun4u(void)
1351{
1352 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1353 unsigned long ver;
1354
1355 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1356 if ((ver >> 32UL) == __JALAPENO_ID ||
1357 (ver >> 32UL) == __SERRANO_ID)
1358 return numa_parse_jbus();
1359 }
1360 return -1;
1361}
1362
1363static int __init bootmem_init_numa(void)
1364{
1365 int i, j;
1366 int err = -1;
1367
1368 numadbg("bootmem_init_numa()\n");
1369
1370 /* Some sane defaults for numa latency values */
1371 for (i = 0; i < MAX_NUMNODES; i++) {
1372 for (j = 0; j < MAX_NUMNODES; j++)
1373 numa_latency[i][j] = (i == j) ?
1374 LOCAL_DISTANCE : REMOTE_DISTANCE;
1375 }
1376
1377 if (numa_enabled) {
1378 if (tlb_type == hypervisor)
1379 err = numa_parse_mdesc();
1380 else
1381 err = numa_parse_sun4u();
1382 }
1383 return err;
1384}
1385
1386#else
1387
1388static int bootmem_init_numa(void)
1389{
1390 return -1;
1391}
1392
1393#endif
1394
1395static void __init bootmem_init_nonnuma(void)
1396{
1397 unsigned long top_of_ram = memblock_end_of_DRAM();
1398 unsigned long total_ram = memblock_phys_mem_size();
1399
1400 numadbg("bootmem_init_nonnuma()\n");
1401
1402 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1403 top_of_ram, total_ram);
1404 printk(KERN_INFO "Memory hole size: %ldMB\n",
1405 (top_of_ram - total_ram) >> 20);
1406
1407 init_node_masks_nonnuma();
1408 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1409 allocate_node_data(0);
1410 node_set_online(0);
1411}
1412
1413static unsigned long __init bootmem_init(unsigned long phys_base)
1414{
1415 unsigned long end_pfn;
1416
1417 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1418 max_pfn = max_low_pfn = end_pfn;
1419 min_low_pfn = (phys_base >> PAGE_SHIFT);
1420
1421 if (bootmem_init_numa() < 0)
1422 bootmem_init_nonnuma();
1423
1424 /* Dump memblock with node info. */
1425 memblock_dump_all();
1426
1427 /* XXX cpu notifier XXX */
1428
1429 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1430 sparse_init();
1431
1432 return end_pfn;
1433}
1434
1435static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1436static int pall_ents __initdata;
1437
1438static unsigned long max_phys_bits = 40;
1439
1440bool kern_addr_valid(unsigned long addr)
1441{
1442 pgd_t *pgd;
1443 pud_t *pud;
1444 pmd_t *pmd;
1445 pte_t *pte;
1446
1447 if ((long)addr < 0L) {
1448 unsigned long pa = __pa(addr);
1449
1450 if ((addr >> max_phys_bits) != 0UL)
1451 return false;
1452
1453 return pfn_valid(pa >> PAGE_SHIFT);
1454 }
1455
1456 if (addr >= (unsigned long) KERNBASE &&
1457 addr < (unsigned long)&_end)
1458 return true;
1459
1460 pgd = pgd_offset_k(addr);
1461 if (pgd_none(*pgd))
1462 return 0;
1463
1464 pud = pud_offset(pgd, addr);
1465 if (pud_none(*pud))
1466 return 0;
1467
1468 if (pud_large(*pud))
1469 return pfn_valid(pud_pfn(*pud));
1470
1471 pmd = pmd_offset(pud, addr);
1472 if (pmd_none(*pmd))
1473 return 0;
1474
1475 if (pmd_large(*pmd))
1476 return pfn_valid(pmd_pfn(*pmd));
1477
1478 pte = pte_offset_kernel(pmd, addr);
1479 if (pte_none(*pte))
1480 return 0;
1481
1482 return pfn_valid(pte_pfn(*pte));
1483}
1484EXPORT_SYMBOL(kern_addr_valid);
1485
1486static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1487 unsigned long vend,
1488 pud_t *pud)
1489{
1490 const unsigned long mask16gb = (1UL << 34) - 1UL;
1491 u64 pte_val = vstart;
1492
1493 /* Each PUD is 8GB */
1494 if ((vstart & mask16gb) ||
1495 (vend - vstart <= mask16gb)) {
1496 pte_val ^= kern_linear_pte_xor[2];
1497 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1498
1499 return vstart + PUD_SIZE;
1500 }
1501
1502 pte_val ^= kern_linear_pte_xor[3];
1503 pte_val |= _PAGE_PUD_HUGE;
1504
1505 vend = vstart + mask16gb + 1UL;
1506 while (vstart < vend) {
1507 pud_val(*pud) = pte_val;
1508
1509 pte_val += PUD_SIZE;
1510 vstart += PUD_SIZE;
1511 pud++;
1512 }
1513 return vstart;
1514}
1515
1516static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1517 bool guard)
1518{
1519 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1520 return true;
1521
1522 return false;
1523}
1524
1525static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1526 unsigned long vend,
1527 pmd_t *pmd)
1528{
1529 const unsigned long mask256mb = (1UL << 28) - 1UL;
1530 const unsigned long mask2gb = (1UL << 31) - 1UL;
1531 u64 pte_val = vstart;
1532
1533 /* Each PMD is 8MB */
1534 if ((vstart & mask256mb) ||
1535 (vend - vstart <= mask256mb)) {
1536 pte_val ^= kern_linear_pte_xor[0];
1537 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1538
1539 return vstart + PMD_SIZE;
1540 }
1541
1542 if ((vstart & mask2gb) ||
1543 (vend - vstart <= mask2gb)) {
1544 pte_val ^= kern_linear_pte_xor[1];
1545 pte_val |= _PAGE_PMD_HUGE;
1546 vend = vstart + mask256mb + 1UL;
1547 } else {
1548 pte_val ^= kern_linear_pte_xor[2];
1549 pte_val |= _PAGE_PMD_HUGE;
1550 vend = vstart + mask2gb + 1UL;
1551 }
1552
1553 while (vstart < vend) {
1554 pmd_val(*pmd) = pte_val;
1555
1556 pte_val += PMD_SIZE;
1557 vstart += PMD_SIZE;
1558 pmd++;
1559 }
1560
1561 return vstart;
1562}
1563
1564static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1565 bool guard)
1566{
1567 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1568 return true;
1569
1570 return false;
1571}
1572
1573static unsigned long __ref kernel_map_range(unsigned long pstart,
1574 unsigned long pend, pgprot_t prot,
1575 bool use_huge)
1576{
1577 unsigned long vstart = PAGE_OFFSET + pstart;
1578 unsigned long vend = PAGE_OFFSET + pend;
1579 unsigned long alloc_bytes = 0UL;
1580
1581 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1582 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1583 vstart, vend);
1584 prom_halt();
1585 }
1586
1587 while (vstart < vend) {
1588 unsigned long this_end, paddr = __pa(vstart);
1589 pgd_t *pgd = pgd_offset_k(vstart);
1590 pud_t *pud;
1591 pmd_t *pmd;
1592 pte_t *pte;
1593
1594 if (pgd_none(*pgd)) {
1595 pud_t *new;
1596
1597 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1598 alloc_bytes += PAGE_SIZE;
1599 pgd_populate(&init_mm, pgd, new);
1600 }
1601 pud = pud_offset(pgd, vstart);
1602 if (pud_none(*pud)) {
1603 pmd_t *new;
1604
1605 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1606 vstart = kernel_map_hugepud(vstart, vend, pud);
1607 continue;
1608 }
1609 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1610 alloc_bytes += PAGE_SIZE;
1611 pud_populate(&init_mm, pud, new);
1612 }
1613
1614 pmd = pmd_offset(pud, vstart);
1615 if (pmd_none(*pmd)) {
1616 pte_t *new;
1617
1618 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1619 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1620 continue;
1621 }
1622 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1623 alloc_bytes += PAGE_SIZE;
1624 pmd_populate_kernel(&init_mm, pmd, new);
1625 }
1626
1627 pte = pte_offset_kernel(pmd, vstart);
1628 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1629 if (this_end > vend)
1630 this_end = vend;
1631
1632 while (vstart < this_end) {
1633 pte_val(*pte) = (paddr | pgprot_val(prot));
1634
1635 vstart += PAGE_SIZE;
1636 paddr += PAGE_SIZE;
1637 pte++;
1638 }
1639 }
1640
1641 return alloc_bytes;
1642}
1643
1644static void __init flush_all_kernel_tsbs(void)
1645{
1646 int i;
1647
1648 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1649 struct tsb *ent = &swapper_tsb[i];
1650
1651 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1652 }
1653#ifndef CONFIG_DEBUG_PAGEALLOC
1654 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1655 struct tsb *ent = &swapper_4m_tsb[i];
1656
1657 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1658 }
1659#endif
1660}
1661
1662extern unsigned int kvmap_linear_patch[1];
1663
1664static void __init kernel_physical_mapping_init(void)
1665{
1666 unsigned long i, mem_alloced = 0UL;
1667 bool use_huge = true;
1668
1669#ifdef CONFIG_DEBUG_PAGEALLOC
1670 use_huge = false;
1671#endif
1672 for (i = 0; i < pall_ents; i++) {
1673 unsigned long phys_start, phys_end;
1674
1675 phys_start = pall[i].phys_addr;
1676 phys_end = phys_start + pall[i].reg_size;
1677
1678 mem_alloced += kernel_map_range(phys_start, phys_end,
1679 PAGE_KERNEL, use_huge);
1680 }
1681
1682 printk("Allocated %ld bytes for kernel page tables.\n",
1683 mem_alloced);
1684
1685 kvmap_linear_patch[0] = 0x01000000; /* nop */
1686 flushi(&kvmap_linear_patch[0]);
1687
1688 flush_all_kernel_tsbs();
1689
1690 __flush_tlb_all();
1691}
1692
1693#ifdef CONFIG_DEBUG_PAGEALLOC
1694void __kernel_map_pages(struct page *page, int numpages, int enable)
1695{
1696 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1697 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1698
1699 kernel_map_range(phys_start, phys_end,
1700 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1701
1702 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1703 PAGE_OFFSET + phys_end);
1704
1705 /* we should perform an IPI and flush all tlbs,
1706 * but that can deadlock->flush only current cpu.
1707 */
1708 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1709 PAGE_OFFSET + phys_end);
1710}
1711#endif
1712
1713unsigned long __init find_ecache_flush_span(unsigned long size)
1714{
1715 int i;
1716
1717 for (i = 0; i < pavail_ents; i++) {
1718 if (pavail[i].reg_size >= size)
1719 return pavail[i].phys_addr;
1720 }
1721
1722 return ~0UL;
1723}
1724
1725unsigned long PAGE_OFFSET;
1726EXPORT_SYMBOL(PAGE_OFFSET);
1727
1728unsigned long VMALLOC_END = 0x0000010000000000UL;
1729EXPORT_SYMBOL(VMALLOC_END);
1730
1731unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1732unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1733
1734static void __init setup_page_offset(void)
1735{
1736 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1737 /* Cheetah/Panther support a full 64-bit virtual
1738 * address, so we can use all that our page tables
1739 * support.
1740 */
1741 sparc64_va_hole_top = 0xfff0000000000000UL;
1742 sparc64_va_hole_bottom = 0x0010000000000000UL;
1743
1744 max_phys_bits = 42;
1745 } else if (tlb_type == hypervisor) {
1746 switch (sun4v_chip_type) {
1747 case SUN4V_CHIP_NIAGARA1:
1748 case SUN4V_CHIP_NIAGARA2:
1749 /* T1 and T2 support 48-bit virtual addresses. */
1750 sparc64_va_hole_top = 0xffff800000000000UL;
1751 sparc64_va_hole_bottom = 0x0000800000000000UL;
1752
1753 max_phys_bits = 39;
1754 break;
1755 case SUN4V_CHIP_NIAGARA3:
1756 /* T3 supports 48-bit virtual addresses. */
1757 sparc64_va_hole_top = 0xffff800000000000UL;
1758 sparc64_va_hole_bottom = 0x0000800000000000UL;
1759
1760 max_phys_bits = 43;
1761 break;
1762 case SUN4V_CHIP_NIAGARA4:
1763 case SUN4V_CHIP_NIAGARA5:
1764 case SUN4V_CHIP_SPARC64X:
1765 case SUN4V_CHIP_SPARC_M6:
1766 /* T4 and later support 52-bit virtual addresses. */
1767 sparc64_va_hole_top = 0xfff8000000000000UL;
1768 sparc64_va_hole_bottom = 0x0008000000000000UL;
1769 max_phys_bits = 47;
1770 break;
1771 case SUN4V_CHIP_SPARC_M7:
1772 case SUN4V_CHIP_SPARC_SN:
1773 default:
1774 /* M7 and later support 52-bit virtual addresses. */
1775 sparc64_va_hole_top = 0xfff8000000000000UL;
1776 sparc64_va_hole_bottom = 0x0008000000000000UL;
1777 max_phys_bits = 49;
1778 break;
1779 }
1780 }
1781
1782 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
1783 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
1784 max_phys_bits);
1785 prom_halt();
1786 }
1787
1788 PAGE_OFFSET = sparc64_va_hole_top;
1789 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
1790 (sparc64_va_hole_bottom >> 2));
1791
1792 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
1793 PAGE_OFFSET, max_phys_bits);
1794 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
1795 VMALLOC_START, VMALLOC_END);
1796 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
1797 VMEMMAP_BASE, VMEMMAP_BASE << 1);
1798}
1799
1800static void __init tsb_phys_patch(void)
1801{
1802 struct tsb_ldquad_phys_patch_entry *pquad;
1803 struct tsb_phys_patch_entry *p;
1804
1805 pquad = &__tsb_ldquad_phys_patch;
1806 while (pquad < &__tsb_ldquad_phys_patch_end) {
1807 unsigned long addr = pquad->addr;
1808
1809 if (tlb_type == hypervisor)
1810 *(unsigned int *) addr = pquad->sun4v_insn;
1811 else
1812 *(unsigned int *) addr = pquad->sun4u_insn;
1813 wmb();
1814 __asm__ __volatile__("flush %0"
1815 : /* no outputs */
1816 : "r" (addr));
1817
1818 pquad++;
1819 }
1820
1821 p = &__tsb_phys_patch;
1822 while (p < &__tsb_phys_patch_end) {
1823 unsigned long addr = p->addr;
1824
1825 *(unsigned int *) addr = p->insn;
1826 wmb();
1827 __asm__ __volatile__("flush %0"
1828 : /* no outputs */
1829 : "r" (addr));
1830
1831 p++;
1832 }
1833}
1834
1835/* Don't mark as init, we give this to the Hypervisor. */
1836#ifndef CONFIG_DEBUG_PAGEALLOC
1837#define NUM_KTSB_DESCR 2
1838#else
1839#define NUM_KTSB_DESCR 1
1840#endif
1841static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1842
1843/* The swapper TSBs are loaded with a base sequence of:
1844 *
1845 * sethi %uhi(SYMBOL), REG1
1846 * sethi %hi(SYMBOL), REG2
1847 * or REG1, %ulo(SYMBOL), REG1
1848 * or REG2, %lo(SYMBOL), REG2
1849 * sllx REG1, 32, REG1
1850 * or REG1, REG2, REG1
1851 *
1852 * When we use physical addressing for the TSB accesses, we patch the
1853 * first four instructions in the above sequence.
1854 */
1855
1856static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1857{
1858 unsigned long high_bits, low_bits;
1859
1860 high_bits = (pa >> 32) & 0xffffffff;
1861 low_bits = (pa >> 0) & 0xffffffff;
1862
1863 while (start < end) {
1864 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1865
1866 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
1867 __asm__ __volatile__("flush %0" : : "r" (ia));
1868
1869 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
1870 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1871
1872 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
1873 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
1874
1875 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
1876 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
1877
1878 start++;
1879 }
1880}
1881
1882static void ktsb_phys_patch(void)
1883{
1884 extern unsigned int __swapper_tsb_phys_patch;
1885 extern unsigned int __swapper_tsb_phys_patch_end;
1886 unsigned long ktsb_pa;
1887
1888 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1889 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1890 &__swapper_tsb_phys_patch_end, ktsb_pa);
1891#ifndef CONFIG_DEBUG_PAGEALLOC
1892 {
1893 extern unsigned int __swapper_4m_tsb_phys_patch;
1894 extern unsigned int __swapper_4m_tsb_phys_patch_end;
1895 ktsb_pa = (kern_base +
1896 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1897 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1898 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1899 }
1900#endif
1901}
1902
1903static void __init sun4v_ktsb_init(void)
1904{
1905 unsigned long ktsb_pa;
1906
1907 /* First KTSB for PAGE_SIZE mappings. */
1908 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1909
1910 switch (PAGE_SIZE) {
1911 case 8 * 1024:
1912 default:
1913 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1914 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1915 break;
1916
1917 case 64 * 1024:
1918 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1919 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1920 break;
1921
1922 case 512 * 1024:
1923 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1924 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1925 break;
1926
1927 case 4 * 1024 * 1024:
1928 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1929 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1930 break;
1931 }
1932
1933 ktsb_descr[0].assoc = 1;
1934 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1935 ktsb_descr[0].ctx_idx = 0;
1936 ktsb_descr[0].tsb_base = ktsb_pa;
1937 ktsb_descr[0].resv = 0;
1938
1939#ifndef CONFIG_DEBUG_PAGEALLOC
1940 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
1941 ktsb_pa = (kern_base +
1942 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1943
1944 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1945 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1946 HV_PGSZ_MASK_256MB |
1947 HV_PGSZ_MASK_2GB |
1948 HV_PGSZ_MASK_16GB) &
1949 cpu_pgsz_mask);
1950 ktsb_descr[1].assoc = 1;
1951 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1952 ktsb_descr[1].ctx_idx = 0;
1953 ktsb_descr[1].tsb_base = ktsb_pa;
1954 ktsb_descr[1].resv = 0;
1955#endif
1956}
1957
1958void sun4v_ktsb_register(void)
1959{
1960 unsigned long pa, ret;
1961
1962 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1963
1964 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1965 if (ret != 0) {
1966 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1967 "errors with %lx\n", pa, ret);
1968 prom_halt();
1969 }
1970}
1971
1972static void __init sun4u_linear_pte_xor_finalize(void)
1973{
1974#ifndef CONFIG_DEBUG_PAGEALLOC
1975 /* This is where we would add Panther support for
1976 * 32MB and 256MB pages.
1977 */
1978#endif
1979}
1980
1981static void __init sun4v_linear_pte_xor_finalize(void)
1982{
1983 unsigned long pagecv_flag;
1984
1985 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
1986 * enables MCD error. Do not set bit 9 on M7 processor.
1987 */
1988 switch (sun4v_chip_type) {
1989 case SUN4V_CHIP_SPARC_M7:
1990 case SUN4V_CHIP_SPARC_SN:
1991 pagecv_flag = 0x00;
1992 break;
1993 default:
1994 pagecv_flag = _PAGE_CV_4V;
1995 break;
1996 }
1997#ifndef CONFIG_DEBUG_PAGEALLOC
1998 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1999 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2000 PAGE_OFFSET;
2001 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2002 _PAGE_P_4V | _PAGE_W_4V);
2003 } else {
2004 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2005 }
2006
2007 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2008 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2009 PAGE_OFFSET;
2010 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2011 _PAGE_P_4V | _PAGE_W_4V);
2012 } else {
2013 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2014 }
2015
2016 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2017 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2018 PAGE_OFFSET;
2019 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2020 _PAGE_P_4V | _PAGE_W_4V);
2021 } else {
2022 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2023 }
2024#endif
2025}
2026
2027/* paging_init() sets up the page tables */
2028
2029static unsigned long last_valid_pfn;
2030
2031static void sun4u_pgprot_init(void);
2032static void sun4v_pgprot_init(void);
2033
2034static phys_addr_t __init available_memory(void)
2035{
2036 phys_addr_t available = 0ULL;
2037 phys_addr_t pa_start, pa_end;
2038 u64 i;
2039
2040 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2041 &pa_end, NULL)
2042 available = available + (pa_end - pa_start);
2043
2044 return available;
2045}
2046
2047#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2048#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2049#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2050#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2051#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2052#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2053
2054/* We need to exclude reserved regions. This exclusion will include
2055 * vmlinux and initrd. To be more precise the initrd size could be used to
2056 * compute a new lower limit because it is freed later during initialization.
2057 */
2058static void __init reduce_memory(phys_addr_t limit_ram)
2059{
2060 phys_addr_t avail_ram = available_memory();
2061 phys_addr_t pa_start, pa_end;
2062 u64 i;
2063
2064 if (limit_ram >= avail_ram)
2065 return;
2066
2067 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2068 &pa_end, NULL) {
2069 phys_addr_t region_size = pa_end - pa_start;
2070 phys_addr_t clip_start = pa_start;
2071
2072 avail_ram = avail_ram - region_size;
2073 /* Are we consuming too much? */
2074 if (avail_ram < limit_ram) {
2075 phys_addr_t give_back = limit_ram - avail_ram;
2076
2077 region_size = region_size - give_back;
2078 clip_start = clip_start + give_back;
2079 }
2080
2081 memblock_remove(clip_start, region_size);
2082
2083 if (avail_ram <= limit_ram)
2084 break;
2085 i = 0UL;
2086 }
2087}
2088
2089void __init paging_init(void)
2090{
2091 unsigned long end_pfn, shift, phys_base;
2092 unsigned long real_end, i;
2093 int node;
2094
2095 setup_page_offset();
2096
2097 /* These build time checkes make sure that the dcache_dirty_cpu()
2098 * page->flags usage will work.
2099 *
2100 * When a page gets marked as dcache-dirty, we store the
2101 * cpu number starting at bit 32 in the page->flags. Also,
2102 * functions like clear_dcache_dirty_cpu use the cpu mask
2103 * in 13-bit signed-immediate instruction fields.
2104 */
2105
2106 /*
2107 * Page flags must not reach into upper 32 bits that are used
2108 * for the cpu number
2109 */
2110 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2111
2112 /*
2113 * The bit fields placed in the high range must not reach below
2114 * the 32 bit boundary. Otherwise we cannot place the cpu field
2115 * at the 32 bit boundary.
2116 */
2117 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2118 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2119
2120 BUILD_BUG_ON(NR_CPUS > 4096);
2121
2122 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2123 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2124
2125 /* Invalidate both kernel TSBs. */
2126 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2127#ifndef CONFIG_DEBUG_PAGEALLOC
2128 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2129#endif
2130
2131 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2132 * bit on M7 processor. This is a conflicting usage of the same
2133 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2134 * Detection error on all pages and this will lead to problems
2135 * later. Kernel does not run with MCD enabled and hence rest
2136 * of the required steps to fully configure memory corruption
2137 * detection are not taken. We need to ensure TTE.mcde is not
2138 * set on M7 processor. Compute the value of cacheability
2139 * flag for use later taking this into consideration.
2140 */
2141 switch (sun4v_chip_type) {
2142 case SUN4V_CHIP_SPARC_M7:
2143 case SUN4V_CHIP_SPARC_SN:
2144 page_cache4v_flag = _PAGE_CP_4V;
2145 break;
2146 default:
2147 page_cache4v_flag = _PAGE_CACHE_4V;
2148 break;
2149 }
2150
2151 if (tlb_type == hypervisor)
2152 sun4v_pgprot_init();
2153 else
2154 sun4u_pgprot_init();
2155
2156 if (tlb_type == cheetah_plus ||
2157 tlb_type == hypervisor) {
2158 tsb_phys_patch();
2159 ktsb_phys_patch();
2160 }
2161
2162 if (tlb_type == hypervisor)
2163 sun4v_patch_tlb_handlers();
2164
2165 /* Find available physical memory...
2166 *
2167 * Read it twice in order to work around a bug in openfirmware.
2168 * The call to grab this table itself can cause openfirmware to
2169 * allocate memory, which in turn can take away some space from
2170 * the list of available memory. Reading it twice makes sure
2171 * we really do get the final value.
2172 */
2173 read_obp_translations();
2174 read_obp_memory("reg", &pall[0], &pall_ents);
2175 read_obp_memory("available", &pavail[0], &pavail_ents);
2176 read_obp_memory("available", &pavail[0], &pavail_ents);
2177
2178 phys_base = 0xffffffffffffffffUL;
2179 for (i = 0; i < pavail_ents; i++) {
2180 phys_base = min(phys_base, pavail[i].phys_addr);
2181 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2182 }
2183
2184 memblock_reserve(kern_base, kern_size);
2185
2186 find_ramdisk(phys_base);
2187
2188 if (cmdline_memory_size)
2189 reduce_memory(cmdline_memory_size);
2190
2191 memblock_allow_resize();
2192 memblock_dump_all();
2193
2194 set_bit(0, mmu_context_bmap);
2195
2196 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2197
2198 real_end = (unsigned long)_end;
2199 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2200 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2201 num_kernel_image_mappings);
2202
2203 /* Set kernel pgd to upper alias so physical page computations
2204 * work.
2205 */
2206 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2207
2208 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2209
2210 inherit_prom_mappings();
2211
2212 /* Ok, we can use our TLB miss and window trap handlers safely. */
2213 setup_tba();
2214
2215 __flush_tlb_all();
2216
2217 prom_build_devicetree();
2218 of_populate_present_mask();
2219#ifndef CONFIG_SMP
2220 of_fill_in_cpu_data();
2221#endif
2222
2223 if (tlb_type == hypervisor) {
2224 sun4v_mdesc_init();
2225 mdesc_populate_present_mask(cpu_all_mask);
2226#ifndef CONFIG_SMP
2227 mdesc_fill_in_cpu_data(cpu_all_mask);
2228#endif
2229 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2230
2231 sun4v_linear_pte_xor_finalize();
2232
2233 sun4v_ktsb_init();
2234 sun4v_ktsb_register();
2235 } else {
2236 unsigned long impl, ver;
2237
2238 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2239 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2240
2241 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2242 impl = ((ver >> 32) & 0xffff);
2243 if (impl == PANTHER_IMPL)
2244 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2245 HV_PGSZ_MASK_256MB);
2246
2247 sun4u_linear_pte_xor_finalize();
2248 }
2249
2250 /* Flush the TLBs and the 4M TSB so that the updated linear
2251 * pte XOR settings are realized for all mappings.
2252 */
2253 __flush_tlb_all();
2254#ifndef CONFIG_DEBUG_PAGEALLOC
2255 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2256#endif
2257 __flush_tlb_all();
2258
2259 /* Setup bootmem... */
2260 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2261
2262 /* Once the OF device tree and MDESC have been setup, we know
2263 * the list of possible cpus. Therefore we can allocate the
2264 * IRQ stacks.
2265 */
2266 for_each_possible_cpu(i) {
2267 node = cpu_to_node(i);
2268
2269 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2270 THREAD_SIZE,
2271 THREAD_SIZE, 0);
2272 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
2273 THREAD_SIZE,
2274 THREAD_SIZE, 0);
2275 }
2276
2277 kernel_physical_mapping_init();
2278
2279 {
2280 unsigned long max_zone_pfns[MAX_NR_ZONES];
2281
2282 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2283
2284 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2285
2286 free_area_init_nodes(max_zone_pfns);
2287 }
2288
2289 printk("Booting Linux...\n");
2290}
2291
2292int page_in_phys_avail(unsigned long paddr)
2293{
2294 int i;
2295
2296 paddr &= PAGE_MASK;
2297
2298 for (i = 0; i < pavail_ents; i++) {
2299 unsigned long start, end;
2300
2301 start = pavail[i].phys_addr;
2302 end = start + pavail[i].reg_size;
2303
2304 if (paddr >= start && paddr < end)
2305 return 1;
2306 }
2307 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2308 return 1;
2309#ifdef CONFIG_BLK_DEV_INITRD
2310 if (paddr >= __pa(initrd_start) &&
2311 paddr < __pa(PAGE_ALIGN(initrd_end)))
2312 return 1;
2313#endif
2314
2315 return 0;
2316}
2317
2318static void __init register_page_bootmem_info(void)
2319{
2320#ifdef CONFIG_NEED_MULTIPLE_NODES
2321 int i;
2322
2323 for_each_online_node(i)
2324 if (NODE_DATA(i)->node_spanned_pages)
2325 register_page_bootmem_info_node(NODE_DATA(i));
2326#endif
2327}
2328void __init mem_init(void)
2329{
2330 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2331
2332 register_page_bootmem_info();
2333 free_all_bootmem();
2334
2335 /*
2336 * Set up the zero page, mark it reserved, so that page count
2337 * is not manipulated when freeing the page from user ptes.
2338 */
2339 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2340 if (mem_map_zero == NULL) {
2341 prom_printf("paging_init: Cannot alloc zero page.\n");
2342 prom_halt();
2343 }
2344 mark_page_reserved(mem_map_zero);
2345
2346 mem_init_print_info(NULL);
2347
2348 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2349 cheetah_ecache_flush_init();
2350}
2351
2352void free_initmem(void)
2353{
2354 unsigned long addr, initend;
2355 int do_free = 1;
2356
2357 /* If the physical memory maps were trimmed by kernel command
2358 * line options, don't even try freeing this initmem stuff up.
2359 * The kernel image could have been in the trimmed out region
2360 * and if so the freeing below will free invalid page structs.
2361 */
2362 if (cmdline_memory_size)
2363 do_free = 0;
2364
2365 /*
2366 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2367 */
2368 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2369 initend = (unsigned long)(__init_end) & PAGE_MASK;
2370 for (; addr < initend; addr += PAGE_SIZE) {
2371 unsigned long page;
2372
2373 page = (addr +
2374 ((unsigned long) __va(kern_base)) -
2375 ((unsigned long) KERNBASE));
2376 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2377
2378 if (do_free)
2379 free_reserved_page(virt_to_page(page));
2380 }
2381}
2382
2383#ifdef CONFIG_BLK_DEV_INITRD
2384void free_initrd_mem(unsigned long start, unsigned long end)
2385{
2386 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2387 "initrd");
2388}
2389#endif
2390
2391pgprot_t PAGE_KERNEL __read_mostly;
2392EXPORT_SYMBOL(PAGE_KERNEL);
2393
2394pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2395pgprot_t PAGE_COPY __read_mostly;
2396
2397pgprot_t PAGE_SHARED __read_mostly;
2398EXPORT_SYMBOL(PAGE_SHARED);
2399
2400unsigned long pg_iobits __read_mostly;
2401
2402unsigned long _PAGE_IE __read_mostly;
2403EXPORT_SYMBOL(_PAGE_IE);
2404
2405unsigned long _PAGE_E __read_mostly;
2406EXPORT_SYMBOL(_PAGE_E);
2407
2408unsigned long _PAGE_CACHE __read_mostly;
2409EXPORT_SYMBOL(_PAGE_CACHE);
2410
2411#ifdef CONFIG_SPARSEMEM_VMEMMAP
2412int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2413 int node)
2414{
2415 unsigned long pte_base;
2416
2417 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2418 _PAGE_CP_4U | _PAGE_CV_4U |
2419 _PAGE_P_4U | _PAGE_W_4U);
2420 if (tlb_type == hypervisor)
2421 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2422 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2423
2424 pte_base |= _PAGE_PMD_HUGE;
2425
2426 vstart = vstart & PMD_MASK;
2427 vend = ALIGN(vend, PMD_SIZE);
2428 for (; vstart < vend; vstart += PMD_SIZE) {
2429 pgd_t *pgd = pgd_offset_k(vstart);
2430 unsigned long pte;
2431 pud_t *pud;
2432 pmd_t *pmd;
2433
2434 if (pgd_none(*pgd)) {
2435 pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2436
2437 if (!new)
2438 return -ENOMEM;
2439 pgd_populate(&init_mm, pgd, new);
2440 }
2441
2442 pud = pud_offset(pgd, vstart);
2443 if (pud_none(*pud)) {
2444 pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node);
2445
2446 if (!new)
2447 return -ENOMEM;
2448 pud_populate(&init_mm, pud, new);
2449 }
2450
2451 pmd = pmd_offset(pud, vstart);
2452
2453 pte = pmd_val(*pmd);
2454 if (!(pte & _PAGE_VALID)) {
2455 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2456
2457 if (!block)
2458 return -ENOMEM;
2459
2460 pmd_val(*pmd) = pte_base | __pa(block);
2461 }
2462 }
2463
2464 return 0;
2465}
2466
2467void vmemmap_free(unsigned long start, unsigned long end)
2468{
2469}
2470#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2471
2472static void prot_init_common(unsigned long page_none,
2473 unsigned long page_shared,
2474 unsigned long page_copy,
2475 unsigned long page_readonly,
2476 unsigned long page_exec_bit)
2477{
2478 PAGE_COPY = __pgprot(page_copy);
2479 PAGE_SHARED = __pgprot(page_shared);
2480
2481 protection_map[0x0] = __pgprot(page_none);
2482 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2483 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2484 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2485 protection_map[0x4] = __pgprot(page_readonly);
2486 protection_map[0x5] = __pgprot(page_readonly);
2487 protection_map[0x6] = __pgprot(page_copy);
2488 protection_map[0x7] = __pgprot(page_copy);
2489 protection_map[0x8] = __pgprot(page_none);
2490 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2491 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2492 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2493 protection_map[0xc] = __pgprot(page_readonly);
2494 protection_map[0xd] = __pgprot(page_readonly);
2495 protection_map[0xe] = __pgprot(page_shared);
2496 protection_map[0xf] = __pgprot(page_shared);
2497}
2498
2499static void __init sun4u_pgprot_init(void)
2500{
2501 unsigned long page_none, page_shared, page_copy, page_readonly;
2502 unsigned long page_exec_bit;
2503 int i;
2504
2505 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2506 _PAGE_CACHE_4U | _PAGE_P_4U |
2507 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2508 _PAGE_EXEC_4U);
2509 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2510 _PAGE_CACHE_4U | _PAGE_P_4U |
2511 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2512 _PAGE_EXEC_4U | _PAGE_L_4U);
2513
2514 _PAGE_IE = _PAGE_IE_4U;
2515 _PAGE_E = _PAGE_E_4U;
2516 _PAGE_CACHE = _PAGE_CACHE_4U;
2517
2518 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2519 __ACCESS_BITS_4U | _PAGE_E_4U);
2520
2521#ifdef CONFIG_DEBUG_PAGEALLOC
2522 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2523#else
2524 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2525 PAGE_OFFSET;
2526#endif
2527 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2528 _PAGE_P_4U | _PAGE_W_4U);
2529
2530 for (i = 1; i < 4; i++)
2531 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2532
2533 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2534 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2535 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2536
2537
2538 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2539 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2540 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2541 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2542 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2543 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2544 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2545
2546 page_exec_bit = _PAGE_EXEC_4U;
2547
2548 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2549 page_exec_bit);
2550}
2551
2552static void __init sun4v_pgprot_init(void)
2553{
2554 unsigned long page_none, page_shared, page_copy, page_readonly;
2555 unsigned long page_exec_bit;
2556 int i;
2557
2558 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2559 page_cache4v_flag | _PAGE_P_4V |
2560 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2561 _PAGE_EXEC_4V);
2562 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2563
2564 _PAGE_IE = _PAGE_IE_4V;
2565 _PAGE_E = _PAGE_E_4V;
2566 _PAGE_CACHE = page_cache4v_flag;
2567
2568#ifdef CONFIG_DEBUG_PAGEALLOC
2569 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2570#else
2571 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2572 PAGE_OFFSET;
2573#endif
2574 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2575 _PAGE_W_4V);
2576
2577 for (i = 1; i < 4; i++)
2578 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2579
2580 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2581 __ACCESS_BITS_4V | _PAGE_E_4V);
2582
2583 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2584 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2585 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2586 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2587
2588 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2589 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2590 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2591 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2592 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2593 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2594 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2595
2596 page_exec_bit = _PAGE_EXEC_4V;
2597
2598 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2599 page_exec_bit);
2600}
2601
2602unsigned long pte_sz_bits(unsigned long sz)
2603{
2604 if (tlb_type == hypervisor) {
2605 switch (sz) {
2606 case 8 * 1024:
2607 default:
2608 return _PAGE_SZ8K_4V;
2609 case 64 * 1024:
2610 return _PAGE_SZ64K_4V;
2611 case 512 * 1024:
2612 return _PAGE_SZ512K_4V;
2613 case 4 * 1024 * 1024:
2614 return _PAGE_SZ4MB_4V;
2615 }
2616 } else {
2617 switch (sz) {
2618 case 8 * 1024:
2619 default:
2620 return _PAGE_SZ8K_4U;
2621 case 64 * 1024:
2622 return _PAGE_SZ64K_4U;
2623 case 512 * 1024:
2624 return _PAGE_SZ512K_4U;
2625 case 4 * 1024 * 1024:
2626 return _PAGE_SZ4MB_4U;
2627 }
2628 }
2629}
2630
2631pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2632{
2633 pte_t pte;
2634
2635 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2636 pte_val(pte) |= (((unsigned long)space) << 32);
2637 pte_val(pte) |= pte_sz_bits(page_size);
2638
2639 return pte;
2640}
2641
2642static unsigned long kern_large_tte(unsigned long paddr)
2643{
2644 unsigned long val;
2645
2646 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2647 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2648 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2649 if (tlb_type == hypervisor)
2650 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2651 page_cache4v_flag | _PAGE_P_4V |
2652 _PAGE_EXEC_4V | _PAGE_W_4V);
2653
2654 return val | paddr;
2655}
2656
2657/* If not locked, zap it. */
2658void __flush_tlb_all(void)
2659{
2660 unsigned long pstate;
2661 int i;
2662
2663 __asm__ __volatile__("flushw\n\t"
2664 "rdpr %%pstate, %0\n\t"
2665 "wrpr %0, %1, %%pstate"
2666 : "=r" (pstate)
2667 : "i" (PSTATE_IE));
2668 if (tlb_type == hypervisor) {
2669 sun4v_mmu_demap_all();
2670 } else if (tlb_type == spitfire) {
2671 for (i = 0; i < 64; i++) {
2672 /* Spitfire Errata #32 workaround */
2673 /* NOTE: Always runs on spitfire, so no
2674 * cheetah+ page size encodings.
2675 */
2676 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2677 "flush %%g6"
2678 : /* No outputs */
2679 : "r" (0),
2680 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2681
2682 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2683 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2684 "membar #Sync"
2685 : /* no outputs */
2686 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2687 spitfire_put_dtlb_data(i, 0x0UL);
2688 }
2689
2690 /* Spitfire Errata #32 workaround */
2691 /* NOTE: Always runs on spitfire, so no
2692 * cheetah+ page size encodings.
2693 */
2694 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2695 "flush %%g6"
2696 : /* No outputs */
2697 : "r" (0),
2698 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2699
2700 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2701 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2702 "membar #Sync"
2703 : /* no outputs */
2704 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2705 spitfire_put_itlb_data(i, 0x0UL);
2706 }
2707 }
2708 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2709 cheetah_flush_dtlb_all();
2710 cheetah_flush_itlb_all();
2711 }
2712 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2713 : : "r" (pstate));
2714}
2715
2716pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2717 unsigned long address)
2718{
2719 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2720 __GFP_REPEAT | __GFP_ZERO);
2721 pte_t *pte = NULL;
2722
2723 if (page)
2724 pte = (pte_t *) page_address(page);
2725
2726 return pte;
2727}
2728
2729pgtable_t pte_alloc_one(struct mm_struct *mm,
2730 unsigned long address)
2731{
2732 struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2733 __GFP_REPEAT | __GFP_ZERO);
2734 if (!page)
2735 return NULL;
2736 if (!pgtable_page_ctor(page)) {
2737 free_hot_cold_page(page, 0);
2738 return NULL;
2739 }
2740 return (pte_t *) page_address(page);
2741}
2742
2743void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2744{
2745 free_page((unsigned long)pte);
2746}
2747
2748static void __pte_free(pgtable_t pte)
2749{
2750 struct page *page = virt_to_page(pte);
2751
2752 pgtable_page_dtor(page);
2753 __free_page(page);
2754}
2755
2756void pte_free(struct mm_struct *mm, pgtable_t pte)
2757{
2758 __pte_free(pte);
2759}
2760
2761void pgtable_free(void *table, bool is_page)
2762{
2763 if (is_page)
2764 __pte_free(table);
2765 else
2766 kmem_cache_free(pgtable_cache, table);
2767}
2768
2769#ifdef CONFIG_TRANSPARENT_HUGEPAGE
2770void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2771 pmd_t *pmd)
2772{
2773 unsigned long pte, flags;
2774 struct mm_struct *mm;
2775 pmd_t entry = *pmd;
2776
2777 if (!pmd_large(entry) || !pmd_young(entry))
2778 return;
2779
2780 pte = pmd_val(entry);
2781
2782 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2783 if (!(pte & _PAGE_VALID))
2784 return;
2785
2786 /* We are fabricating 8MB pages using 4MB real hw pages. */
2787 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2788
2789 mm = vma->vm_mm;
2790
2791 spin_lock_irqsave(&mm->context.lock, flags);
2792
2793 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2794 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2795 addr, pte);
2796
2797 spin_unlock_irqrestore(&mm->context.lock, flags);
2798}
2799#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2800
2801#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2802static void context_reload(void *__data)
2803{
2804 struct mm_struct *mm = __data;
2805
2806 if (mm == current->mm)
2807 load_secondary_context(mm);
2808}
2809
2810void hugetlb_setup(struct pt_regs *regs)
2811{
2812 struct mm_struct *mm = current->mm;
2813 struct tsb_config *tp;
2814
2815 if (faulthandler_disabled() || !mm) {
2816 const struct exception_table_entry *entry;
2817
2818 entry = search_exception_tables(regs->tpc);
2819 if (entry) {
2820 regs->tpc = entry->fixup;
2821 regs->tnpc = regs->tpc + 4;
2822 return;
2823 }
2824 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2825 die_if_kernel("HugeTSB in atomic", regs);
2826 }
2827
2828 tp = &mm->context.tsb_block[MM_TSB_HUGE];
2829 if (likely(tp->tsb == NULL))
2830 tsb_grow(mm, MM_TSB_HUGE, 0);
2831
2832 tsb_context_switch(mm);
2833 smp_tsb_sync(mm);
2834
2835 /* On UltraSPARC-III+ and later, configure the second half of
2836 * the Data-TLB for huge pages.
2837 */
2838 if (tlb_type == cheetah_plus) {
2839 unsigned long ctx;
2840
2841 spin_lock(&ctx_alloc_lock);
2842 ctx = mm->context.sparc64_ctx_val;
2843 ctx &= ~CTX_PGSZ_MASK;
2844 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2845 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2846
2847 if (ctx != mm->context.sparc64_ctx_val) {
2848 /* When changing the page size fields, we
2849 * must perform a context flush so that no
2850 * stale entries match. This flush must
2851 * occur with the original context register
2852 * settings.
2853 */
2854 do_flush_tlb_mm(mm);
2855
2856 /* Reload the context register of all processors
2857 * also executing in this address space.
2858 */
2859 mm->context.sparc64_ctx_val = ctx;
2860 on_each_cpu(context_reload, mm, 0);
2861 }
2862 spin_unlock(&ctx_alloc_lock);
2863 }
2864}
2865#endif
2866
2867static struct resource code_resource = {
2868 .name = "Kernel code",
2869 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
2870};
2871
2872static struct resource data_resource = {
2873 .name = "Kernel data",
2874 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
2875};
2876
2877static struct resource bss_resource = {
2878 .name = "Kernel bss",
2879 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
2880};
2881
2882static inline resource_size_t compute_kern_paddr(void *addr)
2883{
2884 return (resource_size_t) (addr - KERNBASE + kern_base);
2885}
2886
2887static void __init kernel_lds_init(void)
2888{
2889 code_resource.start = compute_kern_paddr(_text);
2890 code_resource.end = compute_kern_paddr(_etext - 1);
2891 data_resource.start = compute_kern_paddr(_etext);
2892 data_resource.end = compute_kern_paddr(_edata - 1);
2893 bss_resource.start = compute_kern_paddr(__bss_start);
2894 bss_resource.end = compute_kern_paddr(_end - 1);
2895}
2896
2897static int __init report_memory(void)
2898{
2899 int i;
2900 struct resource *res;
2901
2902 kernel_lds_init();
2903
2904 for (i = 0; i < pavail_ents; i++) {
2905 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
2906
2907 if (!res) {
2908 pr_warn("Failed to allocate source.\n");
2909 break;
2910 }
2911
2912 res->name = "System RAM";
2913 res->start = pavail[i].phys_addr;
2914 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
2915 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
2916
2917 if (insert_resource(&iomem_resource, res) < 0) {
2918 pr_warn("Resource insertion failed.\n");
2919 break;
2920 }
2921
2922 insert_resource(res, &code_resource);
2923 insert_resource(res, &data_resource);
2924 insert_resource(res, &bss_resource);
2925 }
2926
2927 return 0;
2928}
2929arch_initcall(report_memory);
2930
2931#ifdef CONFIG_SMP
2932#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
2933#else
2934#define do_flush_tlb_kernel_range __flush_tlb_kernel_range
2935#endif
2936
2937void flush_tlb_kernel_range(unsigned long start, unsigned long end)
2938{
2939 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
2940 if (start < LOW_OBP_ADDRESS) {
2941 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
2942 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
2943 }
2944 if (end > HI_OBP_ADDRESS) {
2945 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
2946 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
2947 }
2948 } else {
2949 flush_tsb_kernel_range(start, end);
2950 do_flush_tlb_kernel_range(start, end);
2951 }
2952}