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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MUSB OTG driver core code
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 */
9
10/*
11 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
12 *
13 * This consists of a Host Controller Driver (HCD) and a peripheral
14 * controller driver implementing the "Gadget" API; OTG support is
15 * in the works. These are normal Linux-USB controller drivers which
16 * use IRQs and have no dedicated thread.
17 *
18 * This version of the driver has only been used with products from
19 * Texas Instruments. Those products integrate the Inventra logic
20 * with other DMA, IRQ, and bus modules, as well as other logic that
21 * needs to be reflected in this driver.
22 *
23 *
24 * NOTE: the original Mentor code here was pretty much a collection
25 * of mechanisms that don't seem to have been fully integrated/working
26 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
27 * Key open issues include:
28 *
29 * - Lack of host-side transaction scheduling, for all transfer types.
30 * The hardware doesn't do it; instead, software must.
31 *
32 * This is not an issue for OTG devices that don't support external
33 * hubs, but for more "normal" USB hosts it's a user issue that the
34 * "multipoint" support doesn't scale in the expected ways. That
35 * includes DaVinci EVM in a common non-OTG mode.
36 *
37 * * Control and bulk use dedicated endpoints, and there's as
38 * yet no mechanism to either (a) reclaim the hardware when
39 * peripherals are NAKing, which gets complicated with bulk
40 * endpoints, or (b) use more than a single bulk endpoint in
41 * each direction.
42 *
43 * RESULT: one device may be perceived as blocking another one.
44 *
45 * * Interrupt and isochronous will dynamically allocate endpoint
46 * hardware, but (a) there's no record keeping for bandwidth;
47 * (b) in the common case that few endpoints are available, there
48 * is no mechanism to reuse endpoints to talk to multiple devices.
49 *
50 * RESULT: At one extreme, bandwidth can be overcommitted in
51 * some hardware configurations, no faults will be reported.
52 * At the other extreme, the bandwidth capabilities which do
53 * exist tend to be severely undercommitted. You can't yet hook
54 * up both a keyboard and a mouse to an external USB hub.
55 */
56
57/*
58 * This gets many kinds of configuration information:
59 * - Kconfig for everything user-configurable
60 * - platform_device for addressing, irq, and platform_data
61 * - platform_data is mostly for board-specific information
62 * (plus recentrly, SOC or family details)
63 *
64 * Most of the conditional compilation will (someday) vanish.
65 */
66
67#include <linux/module.h>
68#include <linux/kernel.h>
69#include <linux/sched.h>
70#include <linux/slab.h>
71#include <linux/list.h>
72#include <linux/kobject.h>
73#include <linux/prefetch.h>
74#include <linux/platform_device.h>
75#include <linux/io.h>
76#include <linux/iopoll.h>
77#include <linux/dma-mapping.h>
78#include <linux/usb.h>
79#include <linux/usb/of.h>
80
81#include "musb_core.h"
82#include "musb_trace.h"
83
84#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
85
86
87#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
88#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
89
90#define MUSB_VERSION "6.0"
91
92#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
93
94#define MUSB_DRIVER_NAME "musb-hdrc"
95const char musb_driver_name[] = MUSB_DRIVER_NAME;
96
97MODULE_DESCRIPTION(DRIVER_INFO);
98MODULE_AUTHOR(DRIVER_AUTHOR);
99MODULE_LICENSE("GPL");
100MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
101
102
103/*-------------------------------------------------------------------------*/
104
105static inline struct musb *dev_to_musb(struct device *dev)
106{
107 return dev_get_drvdata(dev);
108}
109
110enum musb_mode musb_get_mode(struct device *dev)
111{
112 enum usb_dr_mode mode;
113
114 mode = usb_get_dr_mode(dev);
115 switch (mode) {
116 case USB_DR_MODE_HOST:
117 return MUSB_HOST;
118 case USB_DR_MODE_PERIPHERAL:
119 return MUSB_PERIPHERAL;
120 case USB_DR_MODE_OTG:
121 case USB_DR_MODE_UNKNOWN:
122 default:
123 return MUSB_OTG;
124 }
125}
126EXPORT_SYMBOL_GPL(musb_get_mode);
127
128/*-------------------------------------------------------------------------*/
129
130static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
131{
132 void __iomem *addr = phy->io_priv;
133 int i = 0;
134 u8 r;
135 u8 power;
136 int ret;
137
138 pm_runtime_get_sync(phy->io_dev);
139
140 /* Make sure the transceiver is not in low power mode */
141 power = musb_readb(addr, MUSB_POWER);
142 power &= ~MUSB_POWER_SUSPENDM;
143 musb_writeb(addr, MUSB_POWER, power);
144
145 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
146 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
147 */
148
149 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
150 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
151 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
152
153 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
154 & MUSB_ULPI_REG_CMPLT)) {
155 i++;
156 if (i == 10000) {
157 ret = -ETIMEDOUT;
158 goto out;
159 }
160
161 }
162 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
163 r &= ~MUSB_ULPI_REG_CMPLT;
164 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
165
166 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
167
168out:
169 pm_runtime_put(phy->io_dev);
170
171 return ret;
172}
173
174static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
175{
176 void __iomem *addr = phy->io_priv;
177 int i = 0;
178 u8 r = 0;
179 u8 power;
180 int ret = 0;
181
182 pm_runtime_get_sync(phy->io_dev);
183
184 /* Make sure the transceiver is not in low power mode */
185 power = musb_readb(addr, MUSB_POWER);
186 power &= ~MUSB_POWER_SUSPENDM;
187 musb_writeb(addr, MUSB_POWER, power);
188
189 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
190 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
191 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
192
193 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
194 & MUSB_ULPI_REG_CMPLT)) {
195 i++;
196 if (i == 10000) {
197 ret = -ETIMEDOUT;
198 goto out;
199 }
200 }
201
202 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
203 r &= ~MUSB_ULPI_REG_CMPLT;
204 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
205
206out:
207 pm_runtime_put(phy->io_dev);
208
209 return ret;
210}
211
212static struct usb_phy_io_ops musb_ulpi_access = {
213 .read = musb_ulpi_read,
214 .write = musb_ulpi_write,
215};
216
217/*-------------------------------------------------------------------------*/
218
219static u32 musb_default_fifo_offset(u8 epnum)
220{
221 return 0x20 + (epnum * 4);
222}
223
224/* "flat" mapping: each endpoint has its own i/o address */
225static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
226{
227}
228
229static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
230{
231 return 0x100 + (0x10 * epnum) + offset;
232}
233
234/* "indexed" mapping: INDEX register controls register bank select */
235static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
236{
237 musb_writeb(mbase, MUSB_INDEX, epnum);
238}
239
240static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
241{
242 return 0x10 + offset;
243}
244
245static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
246{
247 return 0x80 + (0x08 * epnum) + offset;
248}
249
250static u8 musb_default_readb(void __iomem *addr, u32 offset)
251{
252 u8 data = __raw_readb(addr + offset);
253
254 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
255 return data;
256}
257
258static void musb_default_writeb(void __iomem *addr, u32 offset, u8 data)
259{
260 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
261 __raw_writeb(data, addr + offset);
262}
263
264static u16 musb_default_readw(void __iomem *addr, u32 offset)
265{
266 u16 data = __raw_readw(addr + offset);
267
268 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
269 return data;
270}
271
272static void musb_default_writew(void __iomem *addr, u32 offset, u16 data)
273{
274 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
275 __raw_writew(data, addr + offset);
276}
277
278static u16 musb_default_get_toggle(struct musb_qh *qh, int is_out)
279{
280 void __iomem *epio = qh->hw_ep->regs;
281 u16 csr;
282
283 if (is_out)
284 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
285 else
286 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
287
288 return csr;
289}
290
291static u16 musb_default_set_toggle(struct musb_qh *qh, int is_out,
292 struct urb *urb)
293{
294 u16 csr;
295 u16 toggle;
296
297 toggle = usb_gettoggle(urb->dev, qh->epnum, is_out);
298
299 if (is_out)
300 csr = toggle ? (MUSB_TXCSR_H_WR_DATATOGGLE
301 | MUSB_TXCSR_H_DATATOGGLE)
302 : MUSB_TXCSR_CLRDATATOG;
303 else
304 csr = toggle ? (MUSB_RXCSR_H_WR_DATATOGGLE
305 | MUSB_RXCSR_H_DATATOGGLE) : 0;
306
307 return csr;
308}
309
310/*
311 * Load an endpoint's FIFO
312 */
313static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
314 const u8 *src)
315{
316 struct musb *musb = hw_ep->musb;
317 void __iomem *fifo = hw_ep->fifo;
318
319 if (unlikely(len == 0))
320 return;
321
322 prefetch((u8 *)src);
323
324 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
325 'T', hw_ep->epnum, fifo, len, src);
326
327 /* we can't assume unaligned reads work */
328 if (likely((0x01 & (unsigned long) src) == 0)) {
329 u16 index = 0;
330
331 /* best case is 32bit-aligned source address */
332 if ((0x02 & (unsigned long) src) == 0) {
333 if (len >= 4) {
334 iowrite32_rep(fifo, src + index, len >> 2);
335 index += len & ~0x03;
336 }
337 if (len & 0x02) {
338 __raw_writew(*(u16 *)&src[index], fifo);
339 index += 2;
340 }
341 } else {
342 if (len >= 2) {
343 iowrite16_rep(fifo, src + index, len >> 1);
344 index += len & ~0x01;
345 }
346 }
347 if (len & 0x01)
348 __raw_writeb(src[index], fifo);
349 } else {
350 /* byte aligned */
351 iowrite8_rep(fifo, src, len);
352 }
353}
354
355/*
356 * Unload an endpoint's FIFO
357 */
358static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
359{
360 struct musb *musb = hw_ep->musb;
361 void __iomem *fifo = hw_ep->fifo;
362
363 if (unlikely(len == 0))
364 return;
365
366 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
367 'R', hw_ep->epnum, fifo, len, dst);
368
369 /* we can't assume unaligned writes work */
370 if (likely((0x01 & (unsigned long) dst) == 0)) {
371 u16 index = 0;
372
373 /* best case is 32bit-aligned destination address */
374 if ((0x02 & (unsigned long) dst) == 0) {
375 if (len >= 4) {
376 ioread32_rep(fifo, dst, len >> 2);
377 index = len & ~0x03;
378 }
379 if (len & 0x02) {
380 *(u16 *)&dst[index] = __raw_readw(fifo);
381 index += 2;
382 }
383 } else {
384 if (len >= 2) {
385 ioread16_rep(fifo, dst, len >> 1);
386 index = len & ~0x01;
387 }
388 }
389 if (len & 0x01)
390 dst[index] = __raw_readb(fifo);
391 } else {
392 /* byte aligned */
393 ioread8_rep(fifo, dst, len);
394 }
395}
396
397/*
398 * Old style IO functions
399 */
400u8 (*musb_readb)(void __iomem *addr, u32 offset);
401EXPORT_SYMBOL_GPL(musb_readb);
402
403void (*musb_writeb)(void __iomem *addr, u32 offset, u8 data);
404EXPORT_SYMBOL_GPL(musb_writeb);
405
406u8 (*musb_clearb)(void __iomem *addr, u32 offset);
407EXPORT_SYMBOL_GPL(musb_clearb);
408
409u16 (*musb_readw)(void __iomem *addr, u32 offset);
410EXPORT_SYMBOL_GPL(musb_readw);
411
412void (*musb_writew)(void __iomem *addr, u32 offset, u16 data);
413EXPORT_SYMBOL_GPL(musb_writew);
414
415u16 (*musb_clearw)(void __iomem *addr, u32 offset);
416EXPORT_SYMBOL_GPL(musb_clearw);
417
418u32 musb_readl(void __iomem *addr, u32 offset)
419{
420 u32 data = __raw_readl(addr + offset);
421
422 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
423 return data;
424}
425EXPORT_SYMBOL_GPL(musb_readl);
426
427void musb_writel(void __iomem *addr, u32 offset, u32 data)
428{
429 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
430 __raw_writel(data, addr + offset);
431}
432EXPORT_SYMBOL_GPL(musb_writel);
433
434#ifndef CONFIG_MUSB_PIO_ONLY
435struct dma_controller *
436(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
437EXPORT_SYMBOL(musb_dma_controller_create);
438
439void (*musb_dma_controller_destroy)(struct dma_controller *c);
440EXPORT_SYMBOL(musb_dma_controller_destroy);
441#endif
442
443/*
444 * New style IO functions
445 */
446void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
447{
448 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
449}
450
451void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
452{
453 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
454}
455
456static u8 musb_read_devctl(struct musb *musb)
457{
458 return musb_readb(musb->mregs, MUSB_DEVCTL);
459}
460
461/**
462 * musb_set_host - set and initialize host mode
463 * @musb: musb controller driver data
464 *
465 * At least some musb revisions need to enable devctl session bit in
466 * peripheral mode to switch to host mode. Initializes things to host
467 * mode and sets A_IDLE. SoC glue needs to advance state further
468 * based on phy provided VBUS state.
469 *
470 * Note that the SoC glue code may need to wait for musb to settle
471 * on enable before calling this to avoid babble.
472 */
473int musb_set_host(struct musb *musb)
474{
475 int error = 0;
476 u8 devctl;
477
478 if (!musb)
479 return -EINVAL;
480
481 devctl = musb_read_devctl(musb);
482 if (!(devctl & MUSB_DEVCTL_BDEVICE)) {
483 trace_musb_state(musb, devctl, "Already in host mode");
484 goto init_data;
485 }
486
487 devctl |= MUSB_DEVCTL_SESSION;
488 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
489
490 error = readx_poll_timeout(musb_read_devctl, musb, devctl,
491 !(devctl & MUSB_DEVCTL_BDEVICE), 5000,
492 1000000);
493 if (error) {
494 dev_err(musb->controller, "%s: could not set host: %02x\n",
495 __func__, devctl);
496
497 return error;
498 }
499
500 devctl = musb_read_devctl(musb);
501 trace_musb_state(musb, devctl, "Host mode set");
502
503init_data:
504 musb->is_active = 1;
505 musb_set_state(musb, OTG_STATE_A_IDLE);
506 MUSB_HST_MODE(musb);
507
508 return error;
509}
510EXPORT_SYMBOL_GPL(musb_set_host);
511
512/**
513 * musb_set_peripheral - set and initialize peripheral mode
514 * @musb: musb controller driver data
515 *
516 * Clears devctl session bit and initializes things for peripheral
517 * mode and sets B_IDLE. SoC glue needs to advance state further
518 * based on phy provided VBUS state.
519 */
520int musb_set_peripheral(struct musb *musb)
521{
522 int error = 0;
523 u8 devctl;
524
525 if (!musb)
526 return -EINVAL;
527
528 devctl = musb_read_devctl(musb);
529 if (devctl & MUSB_DEVCTL_BDEVICE) {
530 trace_musb_state(musb, devctl, "Already in peripheral mode");
531 goto init_data;
532 }
533
534 devctl &= ~MUSB_DEVCTL_SESSION;
535 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
536
537 error = readx_poll_timeout(musb_read_devctl, musb, devctl,
538 devctl & MUSB_DEVCTL_BDEVICE, 5000,
539 1000000);
540 if (error) {
541 dev_err(musb->controller, "%s: could not set peripheral: %02x\n",
542 __func__, devctl);
543
544 return error;
545 }
546
547 devctl = musb_read_devctl(musb);
548 trace_musb_state(musb, devctl, "Peripheral mode set");
549
550init_data:
551 musb->is_active = 0;
552 musb_set_state(musb, OTG_STATE_B_IDLE);
553 MUSB_DEV_MODE(musb);
554
555 return error;
556}
557EXPORT_SYMBOL_GPL(musb_set_peripheral);
558
559/*-------------------------------------------------------------------------*/
560
561/* for high speed test mode; see USB 2.0 spec 7.1.20 */
562static const u8 musb_test_packet[53] = {
563 /* implicit SYNC then DATA0 to start */
564
565 /* JKJKJKJK x9 */
566 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
567 /* JJKKJJKK x8 */
568 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
569 /* JJJJKKKK x8 */
570 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
571 /* JJJJJJJKKKKKKK x8 */
572 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
573 /* JJJJJJJK x8 */
574 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
575 /* JKKKKKKK x10, JK */
576 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
577
578 /* implicit CRC16 then EOP to end */
579};
580
581void musb_load_testpacket(struct musb *musb)
582{
583 void __iomem *regs = musb->endpoints[0].regs;
584
585 musb_ep_select(musb->mregs, 0);
586 musb_write_fifo(musb->control_ep,
587 sizeof(musb_test_packet), musb_test_packet);
588 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
589}
590
591/*-------------------------------------------------------------------------*/
592
593/*
594 * Handles OTG hnp timeouts, such as b_ase0_brst
595 */
596static void musb_otg_timer_func(struct timer_list *t)
597{
598 struct musb *musb = from_timer(musb, t, otg_timer);
599 unsigned long flags;
600
601 spin_lock_irqsave(&musb->lock, flags);
602 switch (musb_get_state(musb)) {
603 case OTG_STATE_B_WAIT_ACON:
604 musb_dbg(musb,
605 "HNP: b_wait_acon timeout; back to b_peripheral");
606 musb_g_disconnect(musb);
607 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
608 musb->is_active = 0;
609 break;
610 case OTG_STATE_A_SUSPEND:
611 case OTG_STATE_A_WAIT_BCON:
612 musb_dbg(musb, "HNP: %s timeout",
613 musb_otg_state_string(musb));
614 musb_platform_set_vbus(musb, 0);
615 musb_set_state(musb, OTG_STATE_A_WAIT_VFALL);
616 break;
617 default:
618 musb_dbg(musb, "HNP: Unhandled mode %s",
619 musb_otg_state_string(musb));
620 }
621 spin_unlock_irqrestore(&musb->lock, flags);
622}
623
624/*
625 * Stops the HNP transition. Caller must take care of locking.
626 */
627void musb_hnp_stop(struct musb *musb)
628{
629 struct usb_hcd *hcd = musb->hcd;
630 void __iomem *mbase = musb->mregs;
631 u8 reg;
632
633 musb_dbg(musb, "HNP: stop from %s", musb_otg_state_string(musb));
634
635 switch (musb_get_state(musb)) {
636 case OTG_STATE_A_PERIPHERAL:
637 musb_g_disconnect(musb);
638 musb_dbg(musb, "HNP: back to %s", musb_otg_state_string(musb));
639 break;
640 case OTG_STATE_B_HOST:
641 musb_dbg(musb, "HNP: Disabling HR");
642 if (hcd)
643 hcd->self.is_b_host = 0;
644 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
645 MUSB_DEV_MODE(musb);
646 reg = musb_readb(mbase, MUSB_POWER);
647 reg |= MUSB_POWER_SUSPENDM;
648 musb_writeb(mbase, MUSB_POWER, reg);
649 /* REVISIT: Start SESSION_REQUEST here? */
650 break;
651 default:
652 musb_dbg(musb, "HNP: Stopping in unknown state %s",
653 musb_otg_state_string(musb));
654 }
655
656 /*
657 * When returning to A state after HNP, avoid hub_port_rebounce(),
658 * which cause occasional OPT A "Did not receive reset after connect"
659 * errors.
660 */
661 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
662}
663
664static void musb_recover_from_babble(struct musb *musb);
665
666static void musb_handle_intr_resume(struct musb *musb, u8 devctl)
667{
668 musb_dbg(musb, "RESUME (%s)", musb_otg_state_string(musb));
669
670 if (devctl & MUSB_DEVCTL_HM) {
671 switch (musb_get_state(musb)) {
672 case OTG_STATE_A_SUSPEND:
673 /* remote wakeup? */
674 musb->port1_status |=
675 (USB_PORT_STAT_C_SUSPEND << 16)
676 | MUSB_PORT_STAT_RESUME;
677 musb->rh_timer = jiffies
678 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
679 musb_set_state(musb, OTG_STATE_A_HOST);
680 musb->is_active = 1;
681 musb_host_resume_root_hub(musb);
682 schedule_delayed_work(&musb->finish_resume_work,
683 msecs_to_jiffies(USB_RESUME_TIMEOUT));
684 break;
685 case OTG_STATE_B_WAIT_ACON:
686 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
687 musb->is_active = 1;
688 MUSB_DEV_MODE(musb);
689 break;
690 default:
691 WARNING("bogus %s RESUME (%s)\n",
692 "host",
693 musb_otg_state_string(musb));
694 }
695 } else {
696 switch (musb_get_state(musb)) {
697 case OTG_STATE_A_SUSPEND:
698 /* possibly DISCONNECT is upcoming */
699 musb_set_state(musb, OTG_STATE_A_HOST);
700 musb_host_resume_root_hub(musb);
701 break;
702 case OTG_STATE_B_WAIT_ACON:
703 case OTG_STATE_B_PERIPHERAL:
704 /* disconnect while suspended? we may
705 * not get a disconnect irq...
706 */
707 if ((devctl & MUSB_DEVCTL_VBUS)
708 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
709 ) {
710 musb->int_usb |= MUSB_INTR_DISCONNECT;
711 musb->int_usb &= ~MUSB_INTR_SUSPEND;
712 break;
713 }
714 musb_g_resume(musb);
715 break;
716 case OTG_STATE_B_IDLE:
717 musb->int_usb &= ~MUSB_INTR_SUSPEND;
718 break;
719 default:
720 WARNING("bogus %s RESUME (%s)\n",
721 "peripheral",
722 musb_otg_state_string(musb));
723 }
724 }
725}
726
727/* return IRQ_HANDLED to tell the caller to return immediately */
728static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl)
729{
730 void __iomem *mbase = musb->mregs;
731
732 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
733 && (devctl & MUSB_DEVCTL_BDEVICE)) {
734 musb_dbg(musb, "SessReq while on B state");
735 return IRQ_HANDLED;
736 }
737
738 musb_dbg(musb, "SESSION_REQUEST (%s)", musb_otg_state_string(musb));
739
740 /* IRQ arrives from ID pin sense or (later, if VBUS power
741 * is removed) SRP. responses are time critical:
742 * - turn on VBUS (with silicon-specific mechanism)
743 * - go through A_WAIT_VRISE
744 * - ... to A_WAIT_BCON.
745 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
746 */
747 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
748 musb->ep0_stage = MUSB_EP0_START;
749 musb_set_state(musb, OTG_STATE_A_IDLE);
750 MUSB_HST_MODE(musb);
751 musb_platform_set_vbus(musb, 1);
752
753 return IRQ_NONE;
754}
755
756static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl)
757{
758 int ignore = 0;
759
760 /* During connection as an A-Device, we may see a short
761 * current spikes causing voltage drop, because of cable
762 * and peripheral capacitance combined with vbus draw.
763 * (So: less common with truly self-powered devices, where
764 * vbus doesn't act like a power supply.)
765 *
766 * Such spikes are short; usually less than ~500 usec, max
767 * of ~2 msec. That is, they're not sustained overcurrent
768 * errors, though they're reported using VBUSERROR irqs.
769 *
770 * Workarounds: (a) hardware: use self powered devices.
771 * (b) software: ignore non-repeated VBUS errors.
772 *
773 * REVISIT: do delays from lots of DEBUG_KERNEL checks
774 * make trouble here, keeping VBUS < 4.4V ?
775 */
776 switch (musb_get_state(musb)) {
777 case OTG_STATE_A_HOST:
778 /* recovery is dicey once we've gotten past the
779 * initial stages of enumeration, but if VBUS
780 * stayed ok at the other end of the link, and
781 * another reset is due (at least for high speed,
782 * to redo the chirp etc), it might work OK...
783 */
784 case OTG_STATE_A_WAIT_BCON:
785 case OTG_STATE_A_WAIT_VRISE:
786 if (musb->vbuserr_retry) {
787 void __iomem *mbase = musb->mregs;
788
789 musb->vbuserr_retry--;
790 ignore = 1;
791 devctl |= MUSB_DEVCTL_SESSION;
792 musb_writeb(mbase, MUSB_DEVCTL, devctl);
793 } else {
794 musb->port1_status |=
795 USB_PORT_STAT_OVERCURRENT
796 | (USB_PORT_STAT_C_OVERCURRENT << 16);
797 }
798 break;
799 default:
800 break;
801 }
802
803 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
804 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
805 musb_otg_state_string(musb),
806 devctl,
807 ({ char *s;
808 switch (devctl & MUSB_DEVCTL_VBUS) {
809 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
810 s = "<SessEnd"; break;
811 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
812 s = "<AValid"; break;
813 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
814 s = "<VBusValid"; break;
815 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
816 default:
817 s = "VALID"; break;
818 } s; }),
819 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
820 musb->port1_status);
821
822 /* go through A_WAIT_VFALL then start a new session */
823 if (!ignore)
824 musb_platform_set_vbus(musb, 0);
825}
826
827static void musb_handle_intr_suspend(struct musb *musb, u8 devctl)
828{
829 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
830 musb_otg_state_string(musb), devctl);
831
832 switch (musb_get_state(musb)) {
833 case OTG_STATE_A_PERIPHERAL:
834 /* We also come here if the cable is removed, since
835 * this silicon doesn't report ID-no-longer-grounded.
836 *
837 * We depend on T(a_wait_bcon) to shut us down, and
838 * hope users don't do anything dicey during this
839 * undesired detour through A_WAIT_BCON.
840 */
841 musb_hnp_stop(musb);
842 musb_host_resume_root_hub(musb);
843 musb_root_disconnect(musb);
844 musb_platform_try_idle(musb, jiffies
845 + msecs_to_jiffies(musb->a_wait_bcon
846 ? : OTG_TIME_A_WAIT_BCON));
847
848 break;
849 case OTG_STATE_B_IDLE:
850 if (!musb->is_active)
851 break;
852 fallthrough;
853 case OTG_STATE_B_PERIPHERAL:
854 musb_g_suspend(musb);
855 musb->is_active = musb->g.b_hnp_enable;
856 if (musb->is_active) {
857 musb_set_state(musb, OTG_STATE_B_WAIT_ACON);
858 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
859 mod_timer(&musb->otg_timer, jiffies
860 + msecs_to_jiffies(
861 OTG_TIME_B_ASE0_BRST));
862 }
863 break;
864 case OTG_STATE_A_WAIT_BCON:
865 if (musb->a_wait_bcon != 0)
866 musb_platform_try_idle(musb, jiffies
867 + msecs_to_jiffies(musb->a_wait_bcon));
868 break;
869 case OTG_STATE_A_HOST:
870 musb_set_state(musb, OTG_STATE_A_SUSPEND);
871 musb->is_active = musb->hcd->self.b_hnp_enable;
872 break;
873 case OTG_STATE_B_HOST:
874 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
875 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
876 break;
877 default:
878 /* "should not happen" */
879 musb->is_active = 0;
880 break;
881 }
882}
883
884static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb)
885{
886 struct usb_hcd *hcd = musb->hcd;
887
888 musb->is_active = 1;
889 musb->ep0_stage = MUSB_EP0_START;
890
891 musb->intrtxe = musb->epmask;
892 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
893 musb->intrrxe = musb->epmask & 0xfffe;
894 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
895 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
896 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
897 |USB_PORT_STAT_HIGH_SPEED
898 |USB_PORT_STAT_ENABLE
899 );
900 musb->port1_status |= USB_PORT_STAT_CONNECTION
901 |(USB_PORT_STAT_C_CONNECTION << 16);
902
903 /* high vs full speed is just a guess until after reset */
904 if (devctl & MUSB_DEVCTL_LSDEV)
905 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
906
907 /* indicate new connection to OTG machine */
908 switch (musb_get_state(musb)) {
909 case OTG_STATE_B_PERIPHERAL:
910 if (int_usb & MUSB_INTR_SUSPEND) {
911 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
912 int_usb &= ~MUSB_INTR_SUSPEND;
913 goto b_host;
914 } else
915 musb_dbg(musb, "CONNECT as b_peripheral???");
916 break;
917 case OTG_STATE_B_WAIT_ACON:
918 musb_dbg(musb, "HNP: CONNECT, now b_host");
919b_host:
920 musb_set_state(musb, OTG_STATE_B_HOST);
921 if (musb->hcd)
922 musb->hcd->self.is_b_host = 1;
923 del_timer(&musb->otg_timer);
924 break;
925 default:
926 if ((devctl & MUSB_DEVCTL_VBUS)
927 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
928 musb_set_state(musb, OTG_STATE_A_HOST);
929 if (hcd)
930 hcd->self.is_b_host = 0;
931 }
932 break;
933 }
934
935 musb_host_poke_root_hub(musb);
936
937 musb_dbg(musb, "CONNECT (%s) devctl %02x",
938 musb_otg_state_string(musb), devctl);
939}
940
941static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
942{
943 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
944 musb_otg_state_string(musb),
945 MUSB_MODE(musb), devctl);
946
947 switch (musb_get_state(musb)) {
948 case OTG_STATE_A_HOST:
949 case OTG_STATE_A_SUSPEND:
950 musb_host_resume_root_hub(musb);
951 musb_root_disconnect(musb);
952 if (musb->a_wait_bcon != 0)
953 musb_platform_try_idle(musb, jiffies
954 + msecs_to_jiffies(musb->a_wait_bcon));
955 break;
956 case OTG_STATE_B_HOST:
957 /* REVISIT this behaves for "real disconnect"
958 * cases; make sure the other transitions from
959 * from B_HOST act right too. The B_HOST code
960 * in hnp_stop() is currently not used...
961 */
962 musb_root_disconnect(musb);
963 if (musb->hcd)
964 musb->hcd->self.is_b_host = 0;
965 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
966 MUSB_DEV_MODE(musb);
967 musb_g_disconnect(musb);
968 break;
969 case OTG_STATE_A_PERIPHERAL:
970 musb_hnp_stop(musb);
971 musb_root_disconnect(musb);
972 fallthrough;
973 case OTG_STATE_B_WAIT_ACON:
974 case OTG_STATE_B_PERIPHERAL:
975 case OTG_STATE_B_IDLE:
976 musb_g_disconnect(musb);
977 break;
978 default:
979 WARNING("unhandled DISCONNECT transition (%s)\n",
980 musb_otg_state_string(musb));
981 break;
982 }
983}
984
985/*
986 * mentor saves a bit: bus reset and babble share the same irq.
987 * only host sees babble; only peripheral sees bus reset.
988 */
989static void musb_handle_intr_reset(struct musb *musb)
990{
991 if (is_host_active(musb)) {
992 /*
993 * When BABBLE happens what we can depends on which
994 * platform MUSB is running, because some platforms
995 * implemented proprietary means for 'recovering' from
996 * Babble conditions. One such platform is AM335x. In
997 * most cases, however, the only thing we can do is
998 * drop the session.
999 */
1000 dev_err(musb->controller, "Babble\n");
1001 musb_recover_from_babble(musb);
1002 } else {
1003 musb_dbg(musb, "BUS RESET as %s", musb_otg_state_string(musb));
1004 switch (musb_get_state(musb)) {
1005 case OTG_STATE_A_SUSPEND:
1006 musb_g_reset(musb);
1007 fallthrough;
1008 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
1009 /* never use invalid T(a_wait_bcon) */
1010 musb_dbg(musb, "HNP: in %s, %d msec timeout",
1011 musb_otg_state_string(musb),
1012 TA_WAIT_BCON(musb));
1013 mod_timer(&musb->otg_timer, jiffies
1014 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
1015 break;
1016 case OTG_STATE_A_PERIPHERAL:
1017 del_timer(&musb->otg_timer);
1018 musb_g_reset(musb);
1019 break;
1020 case OTG_STATE_B_WAIT_ACON:
1021 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
1022 musb_otg_state_string(musb));
1023 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
1024 musb_g_reset(musb);
1025 break;
1026 case OTG_STATE_B_IDLE:
1027 musb_set_state(musb, OTG_STATE_B_PERIPHERAL);
1028 fallthrough;
1029 case OTG_STATE_B_PERIPHERAL:
1030 musb_g_reset(musb);
1031 break;
1032 default:
1033 musb_dbg(musb, "Unhandled BUS RESET as %s",
1034 musb_otg_state_string(musb));
1035 }
1036 }
1037}
1038
1039/*
1040 * Interrupt Service Routine to record USB "global" interrupts.
1041 * Since these do not happen often and signify things of
1042 * paramount importance, it seems OK to check them individually;
1043 * the order of the tests is specified in the manual
1044 *
1045 * @param musb instance pointer
1046 * @param int_usb register contents
1047 * @param devctl
1048 */
1049
1050static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
1051 u8 devctl)
1052{
1053 irqreturn_t handled = IRQ_NONE;
1054
1055 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
1056
1057 /* in host mode, the peripheral may issue remote wakeup.
1058 * in peripheral mode, the host may resume the link.
1059 * spurious RESUME irqs happen too, paired with SUSPEND.
1060 */
1061 if (int_usb & MUSB_INTR_RESUME) {
1062 musb_handle_intr_resume(musb, devctl);
1063 handled = IRQ_HANDLED;
1064 }
1065
1066 /* see manual for the order of the tests */
1067 if (int_usb & MUSB_INTR_SESSREQ) {
1068 if (musb_handle_intr_sessreq(musb, devctl))
1069 return IRQ_HANDLED;
1070 handled = IRQ_HANDLED;
1071 }
1072
1073 if (int_usb & MUSB_INTR_VBUSERROR) {
1074 musb_handle_intr_vbuserr(musb, devctl);
1075 handled = IRQ_HANDLED;
1076 }
1077
1078 if (int_usb & MUSB_INTR_SUSPEND) {
1079 musb_handle_intr_suspend(musb, devctl);
1080 handled = IRQ_HANDLED;
1081 }
1082
1083 if (int_usb & MUSB_INTR_CONNECT) {
1084 musb_handle_intr_connect(musb, devctl, int_usb);
1085 handled = IRQ_HANDLED;
1086 }
1087
1088 if (int_usb & MUSB_INTR_DISCONNECT) {
1089 musb_handle_intr_disconnect(musb, devctl);
1090 handled = IRQ_HANDLED;
1091 }
1092
1093 if (int_usb & MUSB_INTR_RESET) {
1094 musb_handle_intr_reset(musb);
1095 handled = IRQ_HANDLED;
1096 }
1097
1098#if 0
1099/* REVISIT ... this would be for multiplexing periodic endpoints, or
1100 * supporting transfer phasing to prevent exceeding ISO bandwidth
1101 * limits of a given frame or microframe.
1102 *
1103 * It's not needed for peripheral side, which dedicates endpoints;
1104 * though it _might_ use SOF irqs for other purposes.
1105 *
1106 * And it's not currently needed for host side, which also dedicates
1107 * endpoints, relies on TX/RX interval registers, and isn't claimed
1108 * to support ISO transfers yet.
1109 */
1110 if (int_usb & MUSB_INTR_SOF) {
1111 void __iomem *mbase = musb->mregs;
1112 struct musb_hw_ep *ep;
1113 u8 epnum;
1114 u16 frame;
1115
1116 dev_dbg(musb->controller, "START_OF_FRAME\n");
1117 handled = IRQ_HANDLED;
1118
1119 /* start any periodic Tx transfers waiting for current frame */
1120 frame = musb_readw(mbase, MUSB_FRAME);
1121 ep = musb->endpoints;
1122 for (epnum = 1; (epnum < musb->nr_endpoints)
1123 && (musb->epmask >= (1 << epnum));
1124 epnum++, ep++) {
1125 /*
1126 * FIXME handle framecounter wraps (12 bits)
1127 * eliminate duplicated StartUrb logic
1128 */
1129 if (ep->dwWaitFrame >= frame) {
1130 ep->dwWaitFrame = 0;
1131 pr_debug("SOF --> periodic TX%s on %d\n",
1132 ep->tx_channel ? " DMA" : "",
1133 epnum);
1134 if (!ep->tx_channel)
1135 musb_h_tx_start(musb, epnum);
1136 else
1137 cppi_hostdma_start(musb, epnum);
1138 }
1139 } /* end of for loop */
1140 }
1141#endif
1142
1143 schedule_delayed_work(&musb->irq_work, 0);
1144
1145 return handled;
1146}
1147
1148/*-------------------------------------------------------------------------*/
1149
1150static void musb_disable_interrupts(struct musb *musb)
1151{
1152 void __iomem *mbase = musb->mregs;
1153
1154 /* disable interrupts */
1155 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1156 musb->intrtxe = 0;
1157 musb_writew(mbase, MUSB_INTRTXE, 0);
1158 musb->intrrxe = 0;
1159 musb_writew(mbase, MUSB_INTRRXE, 0);
1160
1161 /* flush pending interrupts */
1162 musb_clearb(mbase, MUSB_INTRUSB);
1163 musb_clearw(mbase, MUSB_INTRTX);
1164 musb_clearw(mbase, MUSB_INTRRX);
1165}
1166
1167static void musb_enable_interrupts(struct musb *musb)
1168{
1169 void __iomem *regs = musb->mregs;
1170
1171 /* Set INT enable registers, enable interrupts */
1172 musb->intrtxe = musb->epmask;
1173 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1174 musb->intrrxe = musb->epmask & 0xfffe;
1175 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1176 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1177
1178}
1179
1180/*
1181 * Program the HDRC to start (enable interrupts, dma, etc.).
1182 */
1183void musb_start(struct musb *musb)
1184{
1185 void __iomem *regs = musb->mregs;
1186 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1187 u8 power;
1188
1189 musb_dbg(musb, "<== devctl %02x", devctl);
1190
1191 musb_enable_interrupts(musb);
1192 musb_writeb(regs, MUSB_TESTMODE, 0);
1193
1194 power = MUSB_POWER_ISOUPDATE;
1195 /*
1196 * treating UNKNOWN as unspecified maximum speed, in which case
1197 * we will default to high-speed.
1198 */
1199 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1200 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1201 power |= MUSB_POWER_HSENAB;
1202 musb_writeb(regs, MUSB_POWER, power);
1203
1204 musb->is_active = 0;
1205 devctl = musb_readb(regs, MUSB_DEVCTL);
1206 devctl &= ~MUSB_DEVCTL_SESSION;
1207
1208 /* session started after:
1209 * (a) ID-grounded irq, host mode;
1210 * (b) vbus present/connect IRQ, peripheral mode;
1211 * (c) peripheral initiates, using SRP
1212 */
1213 if (musb->port_mode != MUSB_HOST &&
1214 musb_get_state(musb) != OTG_STATE_A_WAIT_BCON &&
1215 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1216 musb->is_active = 1;
1217 } else {
1218 devctl |= MUSB_DEVCTL_SESSION;
1219 }
1220
1221 musb_platform_enable(musb);
1222 musb_writeb(regs, MUSB_DEVCTL, devctl);
1223}
1224
1225/*
1226 * Make the HDRC stop (disable interrupts, etc.);
1227 * reversible by musb_start
1228 * called on gadget driver unregister
1229 * with controller locked, irqs blocked
1230 * acts as a NOP unless some role activated the hardware
1231 */
1232void musb_stop(struct musb *musb)
1233{
1234 /* stop IRQs, timers, ... */
1235 musb_platform_disable(musb);
1236 musb_disable_interrupts(musb);
1237 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1238
1239 /* FIXME
1240 * - mark host and/or peripheral drivers unusable/inactive
1241 * - disable DMA (and enable it in HdrcStart)
1242 * - make sure we can musb_start() after musb_stop(); with
1243 * OTG mode, gadget driver module rmmod/modprobe cycles that
1244 * - ...
1245 */
1246 musb_platform_try_idle(musb, 0);
1247}
1248
1249/*-------------------------------------------------------------------------*/
1250
1251/*
1252 * The silicon either has hard-wired endpoint configurations, or else
1253 * "dynamic fifo" sizing. The driver has support for both, though at this
1254 * writing only the dynamic sizing is very well tested. Since we switched
1255 * away from compile-time hardware parameters, we can no longer rely on
1256 * dead code elimination to leave only the relevant one in the object file.
1257 *
1258 * We don't currently use dynamic fifo setup capability to do anything
1259 * more than selecting one of a bunch of predefined configurations.
1260 */
1261static ushort fifo_mode;
1262
1263/* "modprobe ... fifo_mode=1" etc */
1264module_param(fifo_mode, ushort, 0);
1265MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1266
1267/*
1268 * tables defining fifo_mode values. define more if you like.
1269 * for host side, make sure both halves of ep1 are set up.
1270 */
1271
1272/* mode 0 - fits in 2KB */
1273static struct musb_fifo_cfg mode_0_cfg[] = {
1274{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1275{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1276{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1277{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1278{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1279};
1280
1281/* mode 1 - fits in 4KB */
1282static struct musb_fifo_cfg mode_1_cfg[] = {
1283{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1284{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1285{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1286{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1287{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1288};
1289
1290/* mode 2 - fits in 4KB */
1291static struct musb_fifo_cfg mode_2_cfg[] = {
1292{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1293{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1294{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1295{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1296{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
1297{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
1298};
1299
1300/* mode 3 - fits in 4KB */
1301static struct musb_fifo_cfg mode_3_cfg[] = {
1302{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1303{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1304{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1305{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1306{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1307{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1308};
1309
1310/* mode 4 - fits in 16KB */
1311static struct musb_fifo_cfg mode_4_cfg[] = {
1312{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1313{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1314{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1315{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1316{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1317{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1318{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1319{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1320{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1321{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1322{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1323{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1324{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1325{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1326{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1327{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1328{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1329{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1330{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1331{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1332{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1333{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1334{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1335{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1336{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1337{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1338{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1339};
1340
1341/* mode 5 - fits in 8KB */
1342static struct musb_fifo_cfg mode_5_cfg[] = {
1343{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1344{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1345{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1346{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1347{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1348{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1349{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1350{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1351{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1352{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1353{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1354{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1355{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1356{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1357{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1358{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1359{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1360{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1361{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1362{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1363{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1364{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1365{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1366{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1367{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1368{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1369{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1370};
1371
1372/*
1373 * configure a fifo; for non-shared endpoints, this may be called
1374 * once for a tx fifo and once for an rx fifo.
1375 *
1376 * returns negative errno or offset for next fifo.
1377 */
1378static int
1379fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1380 const struct musb_fifo_cfg *cfg, u16 offset)
1381{
1382 void __iomem *mbase = musb->mregs;
1383 int size = 0;
1384 u16 maxpacket = cfg->maxpacket;
1385 u16 c_off = offset >> 3;
1386 u8 c_size;
1387
1388 /* expect hw_ep has already been zero-initialized */
1389
1390 size = ffs(max(maxpacket, (u16) 8)) - 1;
1391 maxpacket = 1 << size;
1392
1393 c_size = size - 3;
1394 if (cfg->mode == BUF_DOUBLE) {
1395 if ((offset + (maxpacket << 1)) >
1396 (1 << (musb->config->ram_bits + 2)))
1397 return -EMSGSIZE;
1398 c_size |= MUSB_FIFOSZ_DPB;
1399 } else {
1400 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1401 return -EMSGSIZE;
1402 }
1403
1404 /* configure the FIFO */
1405 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1406
1407 /* EP0 reserved endpoint for control, bidirectional;
1408 * EP1 reserved for bulk, two unidirectional halves.
1409 */
1410 if (hw_ep->epnum == 1)
1411 musb->bulk_ep = hw_ep;
1412 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1413 switch (cfg->style) {
1414 case FIFO_TX:
1415 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1416 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1417 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1418 hw_ep->max_packet_sz_tx = maxpacket;
1419 break;
1420 case FIFO_RX:
1421 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1422 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1423 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1424 hw_ep->max_packet_sz_rx = maxpacket;
1425 break;
1426 case FIFO_RXTX:
1427 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1428 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1429 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1430 hw_ep->max_packet_sz_rx = maxpacket;
1431
1432 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1433 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1434 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1435 hw_ep->max_packet_sz_tx = maxpacket;
1436
1437 hw_ep->is_shared_fifo = true;
1438 break;
1439 }
1440
1441 /* NOTE rx and tx endpoint irqs aren't managed separately,
1442 * which happens to be ok
1443 */
1444 musb->epmask |= (1 << hw_ep->epnum);
1445
1446 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1447}
1448
1449static struct musb_fifo_cfg ep0_cfg = {
1450 .style = FIFO_RXTX, .maxpacket = 64,
1451};
1452
1453static int ep_config_from_table(struct musb *musb)
1454{
1455 const struct musb_fifo_cfg *cfg;
1456 unsigned i, n;
1457 int offset;
1458 struct musb_hw_ep *hw_ep = musb->endpoints;
1459
1460 if (musb->config->fifo_cfg) {
1461 cfg = musb->config->fifo_cfg;
1462 n = musb->config->fifo_cfg_size;
1463 goto done;
1464 }
1465
1466 switch (fifo_mode) {
1467 default:
1468 fifo_mode = 0;
1469 fallthrough;
1470 case 0:
1471 cfg = mode_0_cfg;
1472 n = ARRAY_SIZE(mode_0_cfg);
1473 break;
1474 case 1:
1475 cfg = mode_1_cfg;
1476 n = ARRAY_SIZE(mode_1_cfg);
1477 break;
1478 case 2:
1479 cfg = mode_2_cfg;
1480 n = ARRAY_SIZE(mode_2_cfg);
1481 break;
1482 case 3:
1483 cfg = mode_3_cfg;
1484 n = ARRAY_SIZE(mode_3_cfg);
1485 break;
1486 case 4:
1487 cfg = mode_4_cfg;
1488 n = ARRAY_SIZE(mode_4_cfg);
1489 break;
1490 case 5:
1491 cfg = mode_5_cfg;
1492 n = ARRAY_SIZE(mode_5_cfg);
1493 break;
1494 }
1495
1496 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1497
1498
1499done:
1500 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1501 /* assert(offset > 0) */
1502
1503 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1504 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1505 */
1506
1507 for (i = 0; i < n; i++) {
1508 u8 epn = cfg->hw_ep_num;
1509
1510 if (epn >= musb->config->num_eps) {
1511 pr_debug("%s: invalid ep %d\n",
1512 musb_driver_name, epn);
1513 return -EINVAL;
1514 }
1515 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1516 if (offset < 0) {
1517 pr_debug("%s: mem overrun, ep %d\n",
1518 musb_driver_name, epn);
1519 return offset;
1520 }
1521 epn++;
1522 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1523 }
1524
1525 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1526 musb_driver_name,
1527 n + 1, musb->config->num_eps * 2 - 1,
1528 offset, (1 << (musb->config->ram_bits + 2)));
1529
1530 if (!musb->bulk_ep) {
1531 pr_debug("%s: missing bulk\n", musb_driver_name);
1532 return -EINVAL;
1533 }
1534
1535 return 0;
1536}
1537
1538
1539/*
1540 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1541 * @param musb the controller
1542 */
1543static int ep_config_from_hw(struct musb *musb)
1544{
1545 u8 epnum = 0;
1546 struct musb_hw_ep *hw_ep;
1547 void __iomem *mbase = musb->mregs;
1548 int ret = 0;
1549
1550 musb_dbg(musb, "<== static silicon ep config");
1551
1552 /* FIXME pick up ep0 maxpacket size */
1553
1554 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1555 musb_ep_select(mbase, epnum);
1556 hw_ep = musb->endpoints + epnum;
1557
1558 ret = musb_read_fifosize(musb, hw_ep, epnum);
1559 if (ret < 0)
1560 break;
1561
1562 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1563
1564 /* pick an RX/TX endpoint for bulk */
1565 if (hw_ep->max_packet_sz_tx < 512
1566 || hw_ep->max_packet_sz_rx < 512)
1567 continue;
1568
1569 /* REVISIT: this algorithm is lazy, we should at least
1570 * try to pick a double buffered endpoint.
1571 */
1572 if (musb->bulk_ep)
1573 continue;
1574 musb->bulk_ep = hw_ep;
1575 }
1576
1577 if (!musb->bulk_ep) {
1578 pr_debug("%s: missing bulk\n", musb_driver_name);
1579 return -EINVAL;
1580 }
1581
1582 return 0;
1583}
1584
1585enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1586
1587/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1588 * configure endpoints, or take their config from silicon
1589 */
1590static int musb_core_init(u16 musb_type, struct musb *musb)
1591{
1592 u8 reg;
1593 char *type;
1594 char aInfo[90];
1595 void __iomem *mbase = musb->mregs;
1596 int status = 0;
1597 int i;
1598
1599 /* log core options (read using indexed model) */
1600 reg = musb_read_configdata(mbase);
1601
1602 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1603 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1604 strcat(aInfo, ", dyn FIFOs");
1605 musb->dyn_fifo = true;
1606 }
1607 if (reg & MUSB_CONFIGDATA_MPRXE) {
1608 strcat(aInfo, ", bulk combine");
1609 musb->bulk_combine = true;
1610 }
1611 if (reg & MUSB_CONFIGDATA_MPTXE) {
1612 strcat(aInfo, ", bulk split");
1613 musb->bulk_split = true;
1614 }
1615 if (reg & MUSB_CONFIGDATA_HBRXE) {
1616 strcat(aInfo, ", HB-ISO Rx");
1617 musb->hb_iso_rx = true;
1618 }
1619 if (reg & MUSB_CONFIGDATA_HBTXE) {
1620 strcat(aInfo, ", HB-ISO Tx");
1621 musb->hb_iso_tx = true;
1622 }
1623 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1624 strcat(aInfo, ", SoftConn");
1625
1626 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1627
1628 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1629 musb->is_multipoint = 1;
1630 type = "M";
1631 } else {
1632 musb->is_multipoint = 0;
1633 type = "";
1634 if (IS_ENABLED(CONFIG_USB) &&
1635 !IS_ENABLED(CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB)) {
1636 pr_err("%s: kernel must disable external hubs, please fix the configuration\n",
1637 musb_driver_name);
1638 }
1639 }
1640
1641 /* log release info */
1642 musb->hwvers = musb_readw(mbase, MUSB_HWVERS);
1643 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1644 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1645 MUSB_HWVERS_MINOR(musb->hwvers),
1646 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1647
1648 /* configure ep0 */
1649 musb_configure_ep0(musb);
1650
1651 /* discover endpoint configuration */
1652 musb->nr_endpoints = 1;
1653 musb->epmask = 1;
1654
1655 if (musb->dyn_fifo)
1656 status = ep_config_from_table(musb);
1657 else
1658 status = ep_config_from_hw(musb);
1659
1660 if (status < 0)
1661 return status;
1662
1663 /* finish init, and print endpoint config */
1664 for (i = 0; i < musb->nr_endpoints; i++) {
1665 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1666
1667 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1668#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1669 if (musb->ops->quirks & MUSB_IN_TUSB) {
1670 hw_ep->fifo_async = musb->async + 0x400 +
1671 musb->io.fifo_offset(i);
1672 hw_ep->fifo_sync = musb->sync + 0x400 +
1673 musb->io.fifo_offset(i);
1674 hw_ep->fifo_sync_va =
1675 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1676
1677 if (i == 0)
1678 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1679 else
1680 hw_ep->conf = mbase + 0x400 +
1681 (((i - 1) & 0xf) << 2);
1682 }
1683#endif
1684
1685 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1686 hw_ep->rx_reinit = 1;
1687 hw_ep->tx_reinit = 1;
1688
1689 if (hw_ep->max_packet_sz_tx) {
1690 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1691 musb_driver_name, i,
1692 hw_ep->is_shared_fifo ? "shared" : "tx",
1693 hw_ep->tx_double_buffered
1694 ? "doublebuffer, " : "",
1695 hw_ep->max_packet_sz_tx);
1696 }
1697 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1698 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1699 musb_driver_name, i,
1700 "rx",
1701 hw_ep->rx_double_buffered
1702 ? "doublebuffer, " : "",
1703 hw_ep->max_packet_sz_rx);
1704 }
1705 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1706 musb_dbg(musb, "hw_ep %d not configured", i);
1707 }
1708
1709 return 0;
1710}
1711
1712/*-------------------------------------------------------------------------*/
1713
1714/*
1715 * handle all the irqs defined by the HDRC core. for now we expect: other
1716 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1717 * will be assigned, and the irq will already have been acked.
1718 *
1719 * called in irq context with spinlock held, irqs blocked
1720 */
1721irqreturn_t musb_interrupt(struct musb *musb)
1722{
1723 irqreturn_t retval = IRQ_NONE;
1724 unsigned long status;
1725 unsigned long epnum;
1726 u8 devctl;
1727
1728 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1729 return IRQ_NONE;
1730
1731 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1732
1733 trace_musb_isr(musb);
1734
1735 /**
1736 * According to Mentor Graphics' documentation, flowchart on page 98,
1737 * IRQ should be handled as follows:
1738 *
1739 * . Resume IRQ
1740 * . Session Request IRQ
1741 * . VBUS Error IRQ
1742 * . Suspend IRQ
1743 * . Connect IRQ
1744 * . Disconnect IRQ
1745 * . Reset/Babble IRQ
1746 * . SOF IRQ (we're not using this one)
1747 * . Endpoint 0 IRQ
1748 * . TX Endpoints
1749 * . RX Endpoints
1750 *
1751 * We will be following that flowchart in order to avoid any problems
1752 * that might arise with internal Finite State Machine.
1753 */
1754
1755 if (musb->int_usb)
1756 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1757
1758 if (musb->int_tx & 1) {
1759 if (is_host_active(musb))
1760 retval |= musb_h_ep0_irq(musb);
1761 else
1762 retval |= musb_g_ep0_irq(musb);
1763
1764 /* we have just handled endpoint 0 IRQ, clear it */
1765 musb->int_tx &= ~BIT(0);
1766 }
1767
1768 status = musb->int_tx;
1769
1770 for_each_set_bit(epnum, &status, 16) {
1771 retval = IRQ_HANDLED;
1772 if (is_host_active(musb))
1773 musb_host_tx(musb, epnum);
1774 else
1775 musb_g_tx(musb, epnum);
1776 }
1777
1778 status = musb->int_rx;
1779
1780 for_each_set_bit(epnum, &status, 16) {
1781 retval = IRQ_HANDLED;
1782 if (is_host_active(musb))
1783 musb_host_rx(musb, epnum);
1784 else
1785 musb_g_rx(musb, epnum);
1786 }
1787
1788 return retval;
1789}
1790EXPORT_SYMBOL_GPL(musb_interrupt);
1791
1792#ifndef CONFIG_MUSB_PIO_ONLY
1793static bool use_dma = true;
1794
1795/* "modprobe ... use_dma=0" etc */
1796module_param(use_dma, bool, 0644);
1797MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1798
1799void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1800{
1801 /* called with controller lock already held */
1802
1803 if (!epnum) {
1804 if (!is_cppi_enabled(musb)) {
1805 /* endpoint 0 */
1806 if (is_host_active(musb))
1807 musb_h_ep0_irq(musb);
1808 else
1809 musb_g_ep0_irq(musb);
1810 }
1811 } else {
1812 /* endpoints 1..15 */
1813 if (transmit) {
1814 if (is_host_active(musb))
1815 musb_host_tx(musb, epnum);
1816 else
1817 musb_g_tx(musb, epnum);
1818 } else {
1819 /* receive */
1820 if (is_host_active(musb))
1821 musb_host_rx(musb, epnum);
1822 else
1823 musb_g_rx(musb, epnum);
1824 }
1825 }
1826}
1827EXPORT_SYMBOL_GPL(musb_dma_completion);
1828
1829#else
1830#define use_dma 0
1831#endif
1832
1833static int (*musb_phy_callback)(enum musb_vbus_id_status status);
1834
1835/*
1836 * musb_mailbox - optional phy notifier function
1837 * @status phy state change
1838 *
1839 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1840 * disabled at the point the phy_callback is registered or unregistered.
1841 */
1842int musb_mailbox(enum musb_vbus_id_status status)
1843{
1844 if (musb_phy_callback)
1845 return musb_phy_callback(status);
1846
1847 return -ENODEV;
1848};
1849EXPORT_SYMBOL_GPL(musb_mailbox);
1850
1851/*-------------------------------------------------------------------------*/
1852
1853static ssize_t
1854mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1855{
1856 struct musb *musb = dev_to_musb(dev);
1857 unsigned long flags;
1858 int ret;
1859
1860 spin_lock_irqsave(&musb->lock, flags);
1861 ret = sprintf(buf, "%s\n", musb_otg_state_string(musb));
1862 spin_unlock_irqrestore(&musb->lock, flags);
1863
1864 return ret;
1865}
1866
1867static ssize_t
1868mode_store(struct device *dev, struct device_attribute *attr,
1869 const char *buf, size_t n)
1870{
1871 struct musb *musb = dev_to_musb(dev);
1872 unsigned long flags;
1873 int status;
1874
1875 spin_lock_irqsave(&musb->lock, flags);
1876 if (sysfs_streq(buf, "host"))
1877 status = musb_platform_set_mode(musb, MUSB_HOST);
1878 else if (sysfs_streq(buf, "peripheral"))
1879 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1880 else if (sysfs_streq(buf, "otg"))
1881 status = musb_platform_set_mode(musb, MUSB_OTG);
1882 else
1883 status = -EINVAL;
1884 spin_unlock_irqrestore(&musb->lock, flags);
1885
1886 return (status == 0) ? n : status;
1887}
1888static DEVICE_ATTR_RW(mode);
1889
1890static ssize_t
1891vbus_store(struct device *dev, struct device_attribute *attr,
1892 const char *buf, size_t n)
1893{
1894 struct musb *musb = dev_to_musb(dev);
1895 unsigned long flags;
1896 unsigned long val;
1897
1898 if (sscanf(buf, "%lu", &val) < 1) {
1899 dev_err(dev, "Invalid VBUS timeout ms value\n");
1900 return -EINVAL;
1901 }
1902
1903 spin_lock_irqsave(&musb->lock, flags);
1904 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1905 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1906 if (musb_get_state(musb) == OTG_STATE_A_WAIT_BCON)
1907 musb->is_active = 0;
1908 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1909 spin_unlock_irqrestore(&musb->lock, flags);
1910
1911 return n;
1912}
1913
1914static ssize_t
1915vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1916{
1917 struct musb *musb = dev_to_musb(dev);
1918 unsigned long flags;
1919 unsigned long val;
1920 int vbus;
1921 u8 devctl;
1922
1923 pm_runtime_get_sync(dev);
1924 spin_lock_irqsave(&musb->lock, flags);
1925 val = musb->a_wait_bcon;
1926 vbus = musb_platform_get_vbus_status(musb);
1927 if (vbus < 0) {
1928 /* Use default MUSB method by means of DEVCTL register */
1929 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1930 if ((devctl & MUSB_DEVCTL_VBUS)
1931 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1932 vbus = 1;
1933 else
1934 vbus = 0;
1935 }
1936 spin_unlock_irqrestore(&musb->lock, flags);
1937 pm_runtime_put_sync(dev);
1938
1939 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1940 vbus ? "on" : "off", val);
1941}
1942static DEVICE_ATTR_RW(vbus);
1943
1944/* Gadget drivers can't know that a host is connected so they might want
1945 * to start SRP, but users can. This allows userspace to trigger SRP.
1946 */
1947static ssize_t srp_store(struct device *dev, struct device_attribute *attr,
1948 const char *buf, size_t n)
1949{
1950 struct musb *musb = dev_to_musb(dev);
1951 unsigned short srp;
1952
1953 if (sscanf(buf, "%hu", &srp) != 1
1954 || (srp != 1)) {
1955 dev_err(dev, "SRP: Value must be 1\n");
1956 return -EINVAL;
1957 }
1958
1959 if (srp == 1)
1960 musb_g_wakeup(musb);
1961
1962 return n;
1963}
1964static DEVICE_ATTR_WO(srp);
1965
1966static struct attribute *musb_attrs[] = {
1967 &dev_attr_mode.attr,
1968 &dev_attr_vbus.attr,
1969 &dev_attr_srp.attr,
1970 NULL
1971};
1972ATTRIBUTE_GROUPS(musb);
1973
1974#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1975 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1976 MUSB_DEVCTL_SESSION)
1977#define MUSB_QUIRK_B_DISCONNECT_99 (MUSB_DEVCTL_BDEVICE | \
1978 (3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1979 MUSB_DEVCTL_SESSION)
1980#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1981 MUSB_DEVCTL_SESSION)
1982
1983static bool musb_state_needs_recheck(struct musb *musb, u8 devctl,
1984 const char *desc)
1985{
1986 if (musb->quirk_retries && !musb->flush_irq_work) {
1987 trace_musb_state(musb, devctl, desc);
1988 schedule_delayed_work(&musb->irq_work,
1989 msecs_to_jiffies(1000));
1990 musb->quirk_retries--;
1991
1992 return true;
1993 }
1994
1995 return false;
1996}
1997
1998/*
1999 * Check the musb devctl session bit to determine if we want to
2000 * allow PM runtime for the device. In general, we want to keep things
2001 * active when the session bit is set except after host disconnect.
2002 *
2003 * Only called from musb_irq_work. If this ever needs to get called
2004 * elsewhere, proper locking must be implemented for musb->session.
2005 */
2006static void musb_pm_runtime_check_session(struct musb *musb)
2007{
2008 u8 devctl, s;
2009 int error;
2010
2011 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2012
2013 /* Handle session status quirks first */
2014 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
2015 MUSB_DEVCTL_HR;
2016 switch (devctl & ~s) {
2017 case MUSB_QUIRK_B_DISCONNECT_99:
2018 musb_state_needs_recheck(musb, devctl,
2019 "Poll devctl in case of suspend after disconnect");
2020 break;
2021 case MUSB_QUIRK_B_INVALID_VBUS_91:
2022 if (musb_state_needs_recheck(musb, devctl,
2023 "Poll devctl on invalid vbus, assume no session"))
2024 return;
2025 fallthrough;
2026 case MUSB_QUIRK_A_DISCONNECT_19:
2027 if (musb_state_needs_recheck(musb, devctl,
2028 "Poll devctl on possible host mode disconnect"))
2029 return;
2030 if (!musb->session)
2031 break;
2032 trace_musb_state(musb, devctl, "Allow PM on possible host mode disconnect");
2033 pm_runtime_mark_last_busy(musb->controller);
2034 pm_runtime_put_autosuspend(musb->controller);
2035 musb->session = false;
2036 return;
2037 default:
2038 break;
2039 }
2040
2041 /* No need to do anything if session has not changed */
2042 s = devctl & MUSB_DEVCTL_SESSION;
2043 if (s == musb->session)
2044 return;
2045
2046 /* Block PM or allow PM? */
2047 if (s) {
2048 trace_musb_state(musb, devctl, "Block PM on active session");
2049 error = pm_runtime_get_sync(musb->controller);
2050 if (error < 0)
2051 dev_err(musb->controller, "Could not enable: %i\n",
2052 error);
2053 musb->quirk_retries = 3;
2054
2055 /*
2056 * We can get a spurious MUSB_INTR_SESSREQ interrupt on start-up
2057 * in B-peripheral mode with nothing connected and the session
2058 * bit clears silently. Check status again in 3 seconds.
2059 */
2060 if (devctl & MUSB_DEVCTL_BDEVICE)
2061 schedule_delayed_work(&musb->irq_work,
2062 msecs_to_jiffies(3000));
2063 } else {
2064 trace_musb_state(musb, devctl, "Allow PM with no session");
2065 pm_runtime_mark_last_busy(musb->controller);
2066 pm_runtime_put_autosuspend(musb->controller);
2067 }
2068
2069 musb->session = s;
2070}
2071
2072/* Only used to provide driver mode change events */
2073static void musb_irq_work(struct work_struct *data)
2074{
2075 struct musb *musb = container_of(data, struct musb, irq_work.work);
2076 int error;
2077
2078 error = pm_runtime_resume_and_get(musb->controller);
2079 if (error < 0) {
2080 dev_err(musb->controller, "Could not enable: %i\n", error);
2081
2082 return;
2083 }
2084
2085 musb_pm_runtime_check_session(musb);
2086
2087 if (musb_get_state(musb) != musb->xceiv_old_state) {
2088 musb->xceiv_old_state = musb_get_state(musb);
2089 sysfs_notify(&musb->controller->kobj, NULL, "mode");
2090 }
2091
2092 pm_runtime_mark_last_busy(musb->controller);
2093 pm_runtime_put_autosuspend(musb->controller);
2094}
2095
2096static void musb_recover_from_babble(struct musb *musb)
2097{
2098 int ret;
2099 u8 devctl;
2100
2101 musb_disable_interrupts(musb);
2102
2103 /*
2104 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
2105 * it some slack and wait for 10us.
2106 */
2107 udelay(10);
2108
2109 ret = musb_platform_recover(musb);
2110 if (ret) {
2111 musb_enable_interrupts(musb);
2112 return;
2113 }
2114
2115 /* drop session bit */
2116 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2117 devctl &= ~MUSB_DEVCTL_SESSION;
2118 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
2119
2120 /* tell usbcore about it */
2121 musb_root_disconnect(musb);
2122
2123 /*
2124 * When a babble condition occurs, the musb controller
2125 * removes the session bit and the endpoint config is lost.
2126 */
2127 if (musb->dyn_fifo)
2128 ret = ep_config_from_table(musb);
2129 else
2130 ret = ep_config_from_hw(musb);
2131
2132 /* restart session */
2133 if (ret == 0)
2134 musb_start(musb);
2135}
2136
2137/* --------------------------------------------------------------------------
2138 * Init support
2139 */
2140
2141static struct musb *allocate_instance(struct device *dev,
2142 const struct musb_hdrc_config *config, void __iomem *mbase)
2143{
2144 struct musb *musb;
2145 struct musb_hw_ep *ep;
2146 int epnum;
2147 int ret;
2148
2149 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
2150 if (!musb)
2151 return NULL;
2152
2153 INIT_LIST_HEAD(&musb->control);
2154 INIT_LIST_HEAD(&musb->in_bulk);
2155 INIT_LIST_HEAD(&musb->out_bulk);
2156 INIT_LIST_HEAD(&musb->pending_list);
2157
2158 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2159 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
2160 musb->mregs = mbase;
2161 musb->ctrl_base = mbase;
2162 musb->nIrq = -ENODEV;
2163 musb->config = config;
2164 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2165 for (epnum = 0, ep = musb->endpoints;
2166 epnum < musb->config->num_eps;
2167 epnum++, ep++) {
2168 ep->musb = musb;
2169 ep->epnum = epnum;
2170 }
2171
2172 musb->controller = dev;
2173
2174 ret = musb_host_alloc(musb);
2175 if (ret < 0)
2176 goto err_free;
2177
2178 dev_set_drvdata(dev, musb);
2179
2180 return musb;
2181
2182err_free:
2183 return NULL;
2184}
2185
2186static void musb_free(struct musb *musb)
2187{
2188 /* this has multiple entry modes. it handles fault cleanup after
2189 * probe(), where things may be partially set up, as well as rmmod
2190 * cleanup after everything's been de-activated.
2191 */
2192
2193 if (musb->nIrq >= 0) {
2194 if (musb->irq_wake)
2195 disable_irq_wake(musb->nIrq);
2196 free_irq(musb->nIrq, musb);
2197 }
2198
2199 musb_host_free(musb);
2200}
2201
2202struct musb_pending_work {
2203 int (*callback)(struct musb *musb, void *data);
2204 void *data;
2205 struct list_head node;
2206};
2207
2208#ifdef CONFIG_PM
2209/*
2210 * Called from musb_runtime_resume(), musb_resume(), and
2211 * musb_queue_resume_work(). Callers must take musb->lock.
2212 */
2213static int musb_run_resume_work(struct musb *musb)
2214{
2215 struct musb_pending_work *w, *_w;
2216 unsigned long flags;
2217 int error = 0;
2218
2219 spin_lock_irqsave(&musb->list_lock, flags);
2220 list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2221 if (w->callback) {
2222 error = w->callback(musb, w->data);
2223 if (error < 0) {
2224 dev_err(musb->controller,
2225 "resume callback %p failed: %i\n",
2226 w->callback, error);
2227 }
2228 }
2229 list_del(&w->node);
2230 devm_kfree(musb->controller, w);
2231 }
2232 spin_unlock_irqrestore(&musb->list_lock, flags);
2233
2234 return error;
2235}
2236#endif
2237
2238/*
2239 * Called to run work if device is active or else queue the work to happen
2240 * on resume. Caller must take musb->lock and must hold an RPM reference.
2241 *
2242 * Note that we cowardly refuse queuing work after musb PM runtime
2243 * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2244 * instead.
2245 */
2246int musb_queue_resume_work(struct musb *musb,
2247 int (*callback)(struct musb *musb, void *data),
2248 void *data)
2249{
2250 struct musb_pending_work *w;
2251 unsigned long flags;
2252 bool is_suspended;
2253 int error;
2254
2255 if (WARN_ON(!callback))
2256 return -EINVAL;
2257
2258 spin_lock_irqsave(&musb->list_lock, flags);
2259 is_suspended = musb->is_runtime_suspended;
2260
2261 if (is_suspended) {
2262 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2263 if (!w) {
2264 error = -ENOMEM;
2265 goto out_unlock;
2266 }
2267
2268 w->callback = callback;
2269 w->data = data;
2270
2271 list_add_tail(&w->node, &musb->pending_list);
2272 error = 0;
2273 }
2274
2275out_unlock:
2276 spin_unlock_irqrestore(&musb->list_lock, flags);
2277
2278 if (!is_suspended)
2279 error = callback(musb, data);
2280
2281 return error;
2282}
2283EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2284
2285static void musb_deassert_reset(struct work_struct *work)
2286{
2287 struct musb *musb;
2288 unsigned long flags;
2289
2290 musb = container_of(work, struct musb, deassert_reset_work.work);
2291
2292 spin_lock_irqsave(&musb->lock, flags);
2293
2294 if (musb->port1_status & USB_PORT_STAT_RESET)
2295 musb_port_reset(musb, false);
2296
2297 spin_unlock_irqrestore(&musb->lock, flags);
2298}
2299
2300/*
2301 * Perform generic per-controller initialization.
2302 *
2303 * @dev: the controller (already clocked, etc)
2304 * @nIrq: IRQ number
2305 * @ctrl: virtual address of controller registers,
2306 * not yet corrected for platform-specific offsets
2307 */
2308static int
2309musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2310{
2311 int status;
2312 struct musb *musb;
2313 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
2314
2315 /* The driver might handle more features than the board; OK.
2316 * Fail when the board needs a feature that's not enabled.
2317 */
2318 if (!plat) {
2319 dev_err(dev, "no platform_data?\n");
2320 status = -ENODEV;
2321 goto fail0;
2322 }
2323
2324 /* allocate */
2325 musb = allocate_instance(dev, plat->config, ctrl);
2326 if (!musb) {
2327 status = -ENOMEM;
2328 goto fail0;
2329 }
2330
2331 spin_lock_init(&musb->lock);
2332 spin_lock_init(&musb->list_lock);
2333 musb->min_power = plat->min_power;
2334 musb->ops = plat->platform_ops;
2335 musb->port_mode = plat->mode;
2336
2337 /*
2338 * Initialize the default IO functions. At least omap2430 needs
2339 * these early. We initialize the platform specific IO functions
2340 * later on.
2341 */
2342 musb_readb = musb_default_readb;
2343 musb_writeb = musb_default_writeb;
2344 musb_readw = musb_default_readw;
2345 musb_writew = musb_default_writew;
2346
2347 /* The musb_platform_init() call:
2348 * - adjusts musb->mregs
2349 * - sets the musb->isr
2350 * - may initialize an integrated transceiver
2351 * - initializes musb->xceiv, usually by otg_get_phy()
2352 * - stops powering VBUS
2353 *
2354 * There are various transceiver configurations.
2355 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2356 * external/discrete ones in various flavors (twl4030 family,
2357 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2358 */
2359 status = musb_platform_init(musb);
2360 if (status < 0)
2361 goto fail1;
2362
2363 if (!musb->isr) {
2364 status = -ENODEV;
2365 goto fail2;
2366 }
2367
2368
2369 /* Most devices use indexed offset or flat offset */
2370 if (musb->ops->quirks & MUSB_INDEXED_EP) {
2371 musb->io.ep_offset = musb_indexed_ep_offset;
2372 musb->io.ep_select = musb_indexed_ep_select;
2373 } else {
2374 musb->io.ep_offset = musb_flat_ep_offset;
2375 musb->io.ep_select = musb_flat_ep_select;
2376 }
2377
2378 if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE)
2379 musb->g.quirk_avoids_skb_reserve = 1;
2380
2381 /* At least tusb6010 has its own offsets */
2382 if (musb->ops->ep_offset)
2383 musb->io.ep_offset = musb->ops->ep_offset;
2384 if (musb->ops->ep_select)
2385 musb->io.ep_select = musb->ops->ep_select;
2386
2387 if (musb->ops->fifo_mode)
2388 fifo_mode = musb->ops->fifo_mode;
2389 else
2390 fifo_mode = 4;
2391
2392 if (musb->ops->fifo_offset)
2393 musb->io.fifo_offset = musb->ops->fifo_offset;
2394 else
2395 musb->io.fifo_offset = musb_default_fifo_offset;
2396
2397 if (musb->ops->busctl_offset)
2398 musb->io.busctl_offset = musb->ops->busctl_offset;
2399 else
2400 musb->io.busctl_offset = musb_default_busctl_offset;
2401
2402 if (musb->ops->readb)
2403 musb_readb = musb->ops->readb;
2404 if (musb->ops->writeb)
2405 musb_writeb = musb->ops->writeb;
2406 if (musb->ops->clearb)
2407 musb_clearb = musb->ops->clearb;
2408 else
2409 musb_clearb = musb_readb;
2410
2411 if (musb->ops->readw)
2412 musb_readw = musb->ops->readw;
2413 if (musb->ops->writew)
2414 musb_writew = musb->ops->writew;
2415 if (musb->ops->clearw)
2416 musb_clearw = musb->ops->clearw;
2417 else
2418 musb_clearw = musb_readw;
2419
2420#ifndef CONFIG_MUSB_PIO_ONLY
2421 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2422 dev_err(dev, "DMA controller not set\n");
2423 status = -ENODEV;
2424 goto fail2;
2425 }
2426 musb_dma_controller_create = musb->ops->dma_init;
2427 musb_dma_controller_destroy = musb->ops->dma_exit;
2428#endif
2429
2430 if (musb->ops->read_fifo)
2431 musb->io.read_fifo = musb->ops->read_fifo;
2432 else
2433 musb->io.read_fifo = musb_default_read_fifo;
2434
2435 if (musb->ops->write_fifo)
2436 musb->io.write_fifo = musb->ops->write_fifo;
2437 else
2438 musb->io.write_fifo = musb_default_write_fifo;
2439
2440 if (musb->ops->get_toggle)
2441 musb->io.get_toggle = musb->ops->get_toggle;
2442 else
2443 musb->io.get_toggle = musb_default_get_toggle;
2444
2445 if (musb->ops->set_toggle)
2446 musb->io.set_toggle = musb->ops->set_toggle;
2447 else
2448 musb->io.set_toggle = musb_default_set_toggle;
2449
2450 if (IS_ENABLED(CONFIG_USB_PHY) && musb->xceiv && !musb->xceiv->io_ops) {
2451 musb->xceiv->io_dev = musb->controller;
2452 musb->xceiv->io_priv = musb->mregs;
2453 musb->xceiv->io_ops = &musb_ulpi_access;
2454 }
2455
2456 if (musb->ops->phy_callback)
2457 musb_phy_callback = musb->ops->phy_callback;
2458
2459 /*
2460 * We need musb_read/write functions initialized for PM.
2461 * Note that at least 2430 glue needs autosuspend delay
2462 * somewhere above 300 ms for the hardware to idle properly
2463 * after disconnecting the cable in host mode. Let's use
2464 * 500 ms for some margin.
2465 */
2466 pm_runtime_use_autosuspend(musb->controller);
2467 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2468 pm_runtime_enable(musb->controller);
2469 pm_runtime_get_sync(musb->controller);
2470
2471 status = usb_phy_init(musb->xceiv);
2472 if (status < 0)
2473 goto err_usb_phy_init;
2474
2475 if (use_dma && dev->dma_mask) {
2476 musb->dma_controller =
2477 musb_dma_controller_create(musb, musb->mregs);
2478 if (IS_ERR(musb->dma_controller)) {
2479 status = PTR_ERR(musb->dma_controller);
2480 goto fail2_5;
2481 }
2482 }
2483
2484 /* be sure interrupts are disabled before connecting ISR */
2485 musb_platform_disable(musb);
2486 musb_disable_interrupts(musb);
2487 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2488
2489 /* MUSB_POWER_SOFTCONN might be already set, JZ4740 does this. */
2490 musb_writeb(musb->mregs, MUSB_POWER, 0);
2491
2492 /* Init IRQ workqueue before request_irq */
2493 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
2494 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2495 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2496
2497 /* setup musb parts of the core (especially endpoints) */
2498 status = musb_core_init(plat->config->multipoint
2499 ? MUSB_CONTROLLER_MHDRC
2500 : MUSB_CONTROLLER_HDRC, musb);
2501 if (status < 0)
2502 goto fail3;
2503
2504 timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
2505
2506 /* attach to the IRQ */
2507 if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
2508 dev_err(dev, "request_irq %d failed!\n", nIrq);
2509 status = -ENODEV;
2510 goto fail3;
2511 }
2512 musb->nIrq = nIrq;
2513 /* FIXME this handles wakeup irqs wrong */
2514 if (enable_irq_wake(nIrq) == 0) {
2515 musb->irq_wake = 1;
2516 device_init_wakeup(dev, 1);
2517 } else {
2518 musb->irq_wake = 0;
2519 }
2520
2521 /* program PHY to use external vBus if required */
2522 if (plat->extvbus) {
2523 u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
2524 busctl |= MUSB_ULPI_USE_EXTVBUS;
2525 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
2526 }
2527
2528 MUSB_DEV_MODE(musb);
2529 musb_set_state(musb, OTG_STATE_B_IDLE);
2530
2531 switch (musb->port_mode) {
2532 case MUSB_HOST:
2533 status = musb_host_setup(musb, plat->power);
2534 if (status < 0)
2535 goto fail3;
2536 status = musb_platform_set_mode(musb, MUSB_HOST);
2537 break;
2538 case MUSB_PERIPHERAL:
2539 status = musb_gadget_setup(musb);
2540 if (status < 0)
2541 goto fail3;
2542 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2543 break;
2544 case MUSB_OTG:
2545 status = musb_host_setup(musb, plat->power);
2546 if (status < 0)
2547 goto fail3;
2548 status = musb_gadget_setup(musb);
2549 if (status) {
2550 musb_host_cleanup(musb);
2551 goto fail3;
2552 }
2553 status = musb_platform_set_mode(musb, MUSB_OTG);
2554 break;
2555 default:
2556 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2557 break;
2558 }
2559
2560 if (status < 0)
2561 goto fail3;
2562
2563 musb_init_debugfs(musb);
2564
2565 musb->is_initialized = 1;
2566 pm_runtime_mark_last_busy(musb->controller);
2567 pm_runtime_put_autosuspend(musb->controller);
2568
2569 return 0;
2570
2571fail3:
2572 cancel_delayed_work_sync(&musb->irq_work);
2573 cancel_delayed_work_sync(&musb->finish_resume_work);
2574 cancel_delayed_work_sync(&musb->deassert_reset_work);
2575 if (musb->dma_controller)
2576 musb_dma_controller_destroy(musb->dma_controller);
2577
2578fail2_5:
2579 usb_phy_shutdown(musb->xceiv);
2580
2581err_usb_phy_init:
2582 pm_runtime_dont_use_autosuspend(musb->controller);
2583 pm_runtime_put_sync(musb->controller);
2584 pm_runtime_disable(musb->controller);
2585
2586fail2:
2587 if (musb->irq_wake)
2588 device_init_wakeup(dev, 0);
2589 musb_platform_exit(musb);
2590
2591fail1:
2592 dev_err_probe(musb->controller, status, "%s failed\n", __func__);
2593
2594 musb_free(musb);
2595
2596fail0:
2597
2598 return status;
2599
2600}
2601
2602/*-------------------------------------------------------------------------*/
2603
2604/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2605 * bridge to a platform device; this driver then suffices.
2606 */
2607static int musb_probe(struct platform_device *pdev)
2608{
2609 struct device *dev = &pdev->dev;
2610 int irq = platform_get_irq_byname(pdev, "mc");
2611 void __iomem *base;
2612
2613 if (irq < 0)
2614 return irq;
2615
2616 base = devm_platform_ioremap_resource(pdev, 0);
2617 if (IS_ERR(base))
2618 return PTR_ERR(base);
2619
2620 return musb_init_controller(dev, irq, base);
2621}
2622
2623static void musb_remove(struct platform_device *pdev)
2624{
2625 struct device *dev = &pdev->dev;
2626 struct musb *musb = dev_to_musb(dev);
2627 unsigned long flags;
2628
2629 /* this gets called on rmmod.
2630 * - Host mode: host may still be active
2631 * - Peripheral mode: peripheral is deactivated (or never-activated)
2632 * - OTG mode: both roles are deactivated (or never-activated)
2633 */
2634 musb_exit_debugfs(musb);
2635
2636 cancel_delayed_work_sync(&musb->irq_work);
2637 cancel_delayed_work_sync(&musb->finish_resume_work);
2638 cancel_delayed_work_sync(&musb->deassert_reset_work);
2639 pm_runtime_get_sync(musb->controller);
2640 musb_host_cleanup(musb);
2641 musb_gadget_cleanup(musb);
2642
2643 musb_platform_disable(musb);
2644 spin_lock_irqsave(&musb->lock, flags);
2645 musb_disable_interrupts(musb);
2646 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2647 spin_unlock_irqrestore(&musb->lock, flags);
2648 musb_platform_exit(musb);
2649
2650 pm_runtime_dont_use_autosuspend(musb->controller);
2651 pm_runtime_put_sync(musb->controller);
2652 pm_runtime_disable(musb->controller);
2653 musb_phy_callback = NULL;
2654 if (musb->dma_controller)
2655 musb_dma_controller_destroy(musb->dma_controller);
2656 usb_phy_shutdown(musb->xceiv);
2657 musb_free(musb);
2658 device_init_wakeup(dev, 0);
2659}
2660
2661#ifdef CONFIG_PM
2662
2663static void musb_save_context(struct musb *musb)
2664{
2665 int i;
2666 void __iomem *musb_base = musb->mregs;
2667 void __iomem *epio;
2668
2669 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2670 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2671 musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL);
2672 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2673 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2674 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2675 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2676
2677 for (i = 0; i < musb->config->num_eps; ++i) {
2678 epio = musb->endpoints[i].regs;
2679 if (!epio)
2680 continue;
2681
2682 musb_writeb(musb_base, MUSB_INDEX, i);
2683 musb->context.index_regs[i].txmaxp =
2684 musb_readw(epio, MUSB_TXMAXP);
2685 musb->context.index_regs[i].txcsr =
2686 musb_readw(epio, MUSB_TXCSR);
2687 musb->context.index_regs[i].rxmaxp =
2688 musb_readw(epio, MUSB_RXMAXP);
2689 musb->context.index_regs[i].rxcsr =
2690 musb_readw(epio, MUSB_RXCSR);
2691
2692 if (musb->dyn_fifo) {
2693 musb->context.index_regs[i].txfifoadd =
2694 musb_readw(musb_base, MUSB_TXFIFOADD);
2695 musb->context.index_regs[i].rxfifoadd =
2696 musb_readw(musb_base, MUSB_RXFIFOADD);
2697 musb->context.index_regs[i].txfifosz =
2698 musb_readb(musb_base, MUSB_TXFIFOSZ);
2699 musb->context.index_regs[i].rxfifosz =
2700 musb_readb(musb_base, MUSB_RXFIFOSZ);
2701 }
2702
2703 musb->context.index_regs[i].txtype =
2704 musb_readb(epio, MUSB_TXTYPE);
2705 musb->context.index_regs[i].txinterval =
2706 musb_readb(epio, MUSB_TXINTERVAL);
2707 musb->context.index_regs[i].rxtype =
2708 musb_readb(epio, MUSB_RXTYPE);
2709 musb->context.index_regs[i].rxinterval =
2710 musb_readb(epio, MUSB_RXINTERVAL);
2711
2712 musb->context.index_regs[i].txfunaddr =
2713 musb_read_txfunaddr(musb, i);
2714 musb->context.index_regs[i].txhubaddr =
2715 musb_read_txhubaddr(musb, i);
2716 musb->context.index_regs[i].txhubport =
2717 musb_read_txhubport(musb, i);
2718
2719 musb->context.index_regs[i].rxfunaddr =
2720 musb_read_rxfunaddr(musb, i);
2721 musb->context.index_regs[i].rxhubaddr =
2722 musb_read_rxhubaddr(musb, i);
2723 musb->context.index_regs[i].rxhubport =
2724 musb_read_rxhubport(musb, i);
2725 }
2726}
2727
2728static void musb_restore_context(struct musb *musb)
2729{
2730 int i;
2731 void __iomem *musb_base = musb->mregs;
2732 void __iomem *epio;
2733 u8 power;
2734
2735 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2736 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2737 musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl);
2738
2739 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2740 power = musb_readb(musb_base, MUSB_POWER);
2741 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2742 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2743 power |= musb->context.power;
2744 musb_writeb(musb_base, MUSB_POWER, power);
2745
2746 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2747 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2748 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2749 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2750 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2751
2752 for (i = 0; i < musb->config->num_eps; ++i) {
2753 epio = musb->endpoints[i].regs;
2754 if (!epio)
2755 continue;
2756
2757 musb_writeb(musb_base, MUSB_INDEX, i);
2758 musb_writew(epio, MUSB_TXMAXP,
2759 musb->context.index_regs[i].txmaxp);
2760 musb_writew(epio, MUSB_TXCSR,
2761 musb->context.index_regs[i].txcsr);
2762 musb_writew(epio, MUSB_RXMAXP,
2763 musb->context.index_regs[i].rxmaxp);
2764 musb_writew(epio, MUSB_RXCSR,
2765 musb->context.index_regs[i].rxcsr);
2766
2767 if (musb->dyn_fifo) {
2768 musb_writeb(musb_base, MUSB_TXFIFOSZ,
2769 musb->context.index_regs[i].txfifosz);
2770 musb_writeb(musb_base, MUSB_RXFIFOSZ,
2771 musb->context.index_regs[i].rxfifosz);
2772 musb_writew(musb_base, MUSB_TXFIFOADD,
2773 musb->context.index_regs[i].txfifoadd);
2774 musb_writew(musb_base, MUSB_RXFIFOADD,
2775 musb->context.index_regs[i].rxfifoadd);
2776 }
2777
2778 musb_writeb(epio, MUSB_TXTYPE,
2779 musb->context.index_regs[i].txtype);
2780 musb_writeb(epio, MUSB_TXINTERVAL,
2781 musb->context.index_regs[i].txinterval);
2782 musb_writeb(epio, MUSB_RXTYPE,
2783 musb->context.index_regs[i].rxtype);
2784 musb_writeb(epio, MUSB_RXINTERVAL,
2785
2786 musb->context.index_regs[i].rxinterval);
2787 musb_write_txfunaddr(musb, i,
2788 musb->context.index_regs[i].txfunaddr);
2789 musb_write_txhubaddr(musb, i,
2790 musb->context.index_regs[i].txhubaddr);
2791 musb_write_txhubport(musb, i,
2792 musb->context.index_regs[i].txhubport);
2793
2794 musb_write_rxfunaddr(musb, i,
2795 musb->context.index_regs[i].rxfunaddr);
2796 musb_write_rxhubaddr(musb, i,
2797 musb->context.index_regs[i].rxhubaddr);
2798 musb_write_rxhubport(musb, i,
2799 musb->context.index_regs[i].rxhubport);
2800 }
2801 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2802}
2803
2804static int musb_suspend(struct device *dev)
2805{
2806 struct musb *musb = dev_to_musb(dev);
2807 unsigned long flags;
2808 int ret;
2809
2810 ret = pm_runtime_get_sync(dev);
2811 if (ret < 0) {
2812 pm_runtime_put_noidle(dev);
2813 return ret;
2814 }
2815
2816 musb_platform_disable(musb);
2817 musb_disable_interrupts(musb);
2818
2819 musb->flush_irq_work = true;
2820 while (flush_delayed_work(&musb->irq_work))
2821 ;
2822 musb->flush_irq_work = false;
2823
2824 if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION))
2825 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2826
2827 WARN_ON(!list_empty(&musb->pending_list));
2828
2829 spin_lock_irqsave(&musb->lock, flags);
2830
2831 if (is_peripheral_active(musb)) {
2832 /* FIXME force disconnect unless we know USB will wake
2833 * the system up quickly enough to respond ...
2834 */
2835 } else if (is_host_active(musb)) {
2836 /* we know all the children are suspended; sometimes
2837 * they will even be wakeup-enabled.
2838 */
2839 }
2840
2841 musb_save_context(musb);
2842
2843 spin_unlock_irqrestore(&musb->lock, flags);
2844 return 0;
2845}
2846
2847static int musb_resume(struct device *dev)
2848{
2849 struct musb *musb = dev_to_musb(dev);
2850 unsigned long flags;
2851 int error;
2852 u8 devctl;
2853 u8 mask;
2854
2855 /*
2856 * For static cmos like DaVinci, register values were preserved
2857 * unless for some reason the whole soc powered down or the USB
2858 * module got reset through the PSC (vs just being disabled).
2859 *
2860 * For the DSPS glue layer though, a full register restore has to
2861 * be done. As it shouldn't harm other platforms, we do it
2862 * unconditionally.
2863 */
2864
2865 musb_restore_context(musb);
2866
2867 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2868 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2869 if ((devctl & mask) != (musb->context.devctl & mask))
2870 musb->port1_status = 0;
2871
2872 musb_enable_interrupts(musb);
2873 musb_platform_enable(musb);
2874
2875 /* session might be disabled in suspend */
2876 if (musb->port_mode == MUSB_HOST &&
2877 !(musb->ops->quirks & MUSB_PRESERVE_SESSION)) {
2878 devctl |= MUSB_DEVCTL_SESSION;
2879 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
2880 }
2881
2882 spin_lock_irqsave(&musb->lock, flags);
2883 error = musb_run_resume_work(musb);
2884 if (error)
2885 dev_err(musb->controller, "resume work failed with %i\n",
2886 error);
2887 spin_unlock_irqrestore(&musb->lock, flags);
2888
2889 pm_runtime_mark_last_busy(dev);
2890 pm_runtime_put_autosuspend(dev);
2891
2892 return 0;
2893}
2894
2895static int musb_runtime_suspend(struct device *dev)
2896{
2897 struct musb *musb = dev_to_musb(dev);
2898
2899 musb_save_context(musb);
2900 musb->is_runtime_suspended = 1;
2901
2902 return 0;
2903}
2904
2905static int musb_runtime_resume(struct device *dev)
2906{
2907 struct musb *musb = dev_to_musb(dev);
2908 unsigned long flags;
2909 int error;
2910
2911 /*
2912 * When pm_runtime_get_sync called for the first time in driver
2913 * init, some of the structure is still not initialized which is
2914 * used in restore function. But clock needs to be
2915 * enabled before any register access, so
2916 * pm_runtime_get_sync has to be called.
2917 * Also context restore without save does not make
2918 * any sense
2919 */
2920 if (!musb->is_initialized)
2921 return 0;
2922
2923 musb_restore_context(musb);
2924
2925 spin_lock_irqsave(&musb->lock, flags);
2926 error = musb_run_resume_work(musb);
2927 if (error)
2928 dev_err(musb->controller, "resume work failed with %i\n",
2929 error);
2930 musb->is_runtime_suspended = 0;
2931 spin_unlock_irqrestore(&musb->lock, flags);
2932
2933 return 0;
2934}
2935
2936static const struct dev_pm_ops musb_dev_pm_ops = {
2937 .suspend = musb_suspend,
2938 .resume = musb_resume,
2939 .runtime_suspend = musb_runtime_suspend,
2940 .runtime_resume = musb_runtime_resume,
2941};
2942
2943#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2944#else
2945#define MUSB_DEV_PM_OPS NULL
2946#endif
2947
2948static struct platform_driver musb_driver = {
2949 .driver = {
2950 .name = musb_driver_name,
2951 .bus = &platform_bus_type,
2952 .pm = MUSB_DEV_PM_OPS,
2953 .dev_groups = musb_groups,
2954 },
2955 .probe = musb_probe,
2956 .remove_new = musb_remove,
2957};
2958
2959module_platform_driver(musb_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * MUSB OTG driver core code
4 *
5 * Copyright 2005 Mentor Graphics Corporation
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 */
9
10/*
11 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
12 *
13 * This consists of a Host Controller Driver (HCD) and a peripheral
14 * controller driver implementing the "Gadget" API; OTG support is
15 * in the works. These are normal Linux-USB controller drivers which
16 * use IRQs and have no dedicated thread.
17 *
18 * This version of the driver has only been used with products from
19 * Texas Instruments. Those products integrate the Inventra logic
20 * with other DMA, IRQ, and bus modules, as well as other logic that
21 * needs to be reflected in this driver.
22 *
23 *
24 * NOTE: the original Mentor code here was pretty much a collection
25 * of mechanisms that don't seem to have been fully integrated/working
26 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
27 * Key open issues include:
28 *
29 * - Lack of host-side transaction scheduling, for all transfer types.
30 * The hardware doesn't do it; instead, software must.
31 *
32 * This is not an issue for OTG devices that don't support external
33 * hubs, but for more "normal" USB hosts it's a user issue that the
34 * "multipoint" support doesn't scale in the expected ways. That
35 * includes DaVinci EVM in a common non-OTG mode.
36 *
37 * * Control and bulk use dedicated endpoints, and there's as
38 * yet no mechanism to either (a) reclaim the hardware when
39 * peripherals are NAKing, which gets complicated with bulk
40 * endpoints, or (b) use more than a single bulk endpoint in
41 * each direction.
42 *
43 * RESULT: one device may be perceived as blocking another one.
44 *
45 * * Interrupt and isochronous will dynamically allocate endpoint
46 * hardware, but (a) there's no record keeping for bandwidth;
47 * (b) in the common case that few endpoints are available, there
48 * is no mechanism to reuse endpoints to talk to multiple devices.
49 *
50 * RESULT: At one extreme, bandwidth can be overcommitted in
51 * some hardware configurations, no faults will be reported.
52 * At the other extreme, the bandwidth capabilities which do
53 * exist tend to be severely undercommitted. You can't yet hook
54 * up both a keyboard and a mouse to an external USB hub.
55 */
56
57/*
58 * This gets many kinds of configuration information:
59 * - Kconfig for everything user-configurable
60 * - platform_device for addressing, irq, and platform_data
61 * - platform_data is mostly for board-specific information
62 * (plus recentrly, SOC or family details)
63 *
64 * Most of the conditional compilation will (someday) vanish.
65 */
66
67#include <linux/module.h>
68#include <linux/kernel.h>
69#include <linux/sched.h>
70#include <linux/slab.h>
71#include <linux/list.h>
72#include <linux/kobject.h>
73#include <linux/prefetch.h>
74#include <linux/platform_device.h>
75#include <linux/io.h>
76#include <linux/dma-mapping.h>
77#include <linux/usb.h>
78#include <linux/usb/of.h>
79
80#include "musb_core.h"
81#include "musb_trace.h"
82
83#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
84
85
86#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
87#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
88
89#define MUSB_VERSION "6.0"
90
91#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
92
93#define MUSB_DRIVER_NAME "musb-hdrc"
94const char musb_driver_name[] = MUSB_DRIVER_NAME;
95
96MODULE_DESCRIPTION(DRIVER_INFO);
97MODULE_AUTHOR(DRIVER_AUTHOR);
98MODULE_LICENSE("GPL");
99MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
100
101
102/*-------------------------------------------------------------------------*/
103
104static inline struct musb *dev_to_musb(struct device *dev)
105{
106 return dev_get_drvdata(dev);
107}
108
109enum musb_mode musb_get_mode(struct device *dev)
110{
111 enum usb_dr_mode mode;
112
113 mode = usb_get_dr_mode(dev);
114 switch (mode) {
115 case USB_DR_MODE_HOST:
116 return MUSB_HOST;
117 case USB_DR_MODE_PERIPHERAL:
118 return MUSB_PERIPHERAL;
119 case USB_DR_MODE_OTG:
120 case USB_DR_MODE_UNKNOWN:
121 default:
122 return MUSB_OTG;
123 }
124}
125EXPORT_SYMBOL_GPL(musb_get_mode);
126
127/*-------------------------------------------------------------------------*/
128
129static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
130{
131 void __iomem *addr = phy->io_priv;
132 int i = 0;
133 u8 r;
134 u8 power;
135 int ret;
136
137 pm_runtime_get_sync(phy->io_dev);
138
139 /* Make sure the transceiver is not in low power mode */
140 power = musb_readb(addr, MUSB_POWER);
141 power &= ~MUSB_POWER_SUSPENDM;
142 musb_writeb(addr, MUSB_POWER, power);
143
144 /* REVISIT: musbhdrc_ulpi_an.pdf recommends setting the
145 * ULPICarKitControlDisableUTMI after clearing POWER_SUSPENDM.
146 */
147
148 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
149 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
150 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
151
152 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
153 & MUSB_ULPI_REG_CMPLT)) {
154 i++;
155 if (i == 10000) {
156 ret = -ETIMEDOUT;
157 goto out;
158 }
159
160 }
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
164
165 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
166
167out:
168 pm_runtime_put(phy->io_dev);
169
170 return ret;
171}
172
173static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
174{
175 void __iomem *addr = phy->io_priv;
176 int i = 0;
177 u8 r = 0;
178 u8 power;
179 int ret = 0;
180
181 pm_runtime_get_sync(phy->io_dev);
182
183 /* Make sure the transceiver is not in low power mode */
184 power = musb_readb(addr, MUSB_POWER);
185 power &= ~MUSB_POWER_SUSPENDM;
186 musb_writeb(addr, MUSB_POWER, power);
187
188 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
189 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
190 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
191
192 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
193 & MUSB_ULPI_REG_CMPLT)) {
194 i++;
195 if (i == 10000) {
196 ret = -ETIMEDOUT;
197 goto out;
198 }
199 }
200
201 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
202 r &= ~MUSB_ULPI_REG_CMPLT;
203 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
204
205out:
206 pm_runtime_put(phy->io_dev);
207
208 return ret;
209}
210
211static struct usb_phy_io_ops musb_ulpi_access = {
212 .read = musb_ulpi_read,
213 .write = musb_ulpi_write,
214};
215
216/*-------------------------------------------------------------------------*/
217
218static u32 musb_default_fifo_offset(u8 epnum)
219{
220 return 0x20 + (epnum * 4);
221}
222
223/* "flat" mapping: each endpoint has its own i/o address */
224static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
225{
226}
227
228static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
229{
230 return 0x100 + (0x10 * epnum) + offset;
231}
232
233/* "indexed" mapping: INDEX register controls register bank select */
234static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
235{
236 musb_writeb(mbase, MUSB_INDEX, epnum);
237}
238
239static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
240{
241 return 0x10 + offset;
242}
243
244static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
245{
246 return 0x80 + (0x08 * epnum) + offset;
247}
248
249static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
250{
251 u8 data = __raw_readb(addr + offset);
252
253 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
254 return data;
255}
256
257static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
258{
259 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
260 __raw_writeb(data, addr + offset);
261}
262
263static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264{
265 u16 data = __raw_readw(addr + offset);
266
267 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
268 return data;
269}
270
271static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
272{
273 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
274 __raw_writew(data, addr + offset);
275}
276
277static u32 musb_default_readl(const void __iomem *addr, unsigned offset)
278{
279 u32 data = __raw_readl(addr + offset);
280
281 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
282 return data;
283}
284
285static void musb_default_writel(void __iomem *addr, unsigned offset, u32 data)
286{
287 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
288 __raw_writel(data, addr + offset);
289}
290
291/*
292 * Load an endpoint's FIFO
293 */
294static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
295 const u8 *src)
296{
297 struct musb *musb = hw_ep->musb;
298 void __iomem *fifo = hw_ep->fifo;
299
300 if (unlikely(len == 0))
301 return;
302
303 prefetch((u8 *)src);
304
305 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
306 'T', hw_ep->epnum, fifo, len, src);
307
308 /* we can't assume unaligned reads work */
309 if (likely((0x01 & (unsigned long) src) == 0)) {
310 u16 index = 0;
311
312 /* best case is 32bit-aligned source address */
313 if ((0x02 & (unsigned long) src) == 0) {
314 if (len >= 4) {
315 iowrite32_rep(fifo, src + index, len >> 2);
316 index += len & ~0x03;
317 }
318 if (len & 0x02) {
319 __raw_writew(*(u16 *)&src[index], fifo);
320 index += 2;
321 }
322 } else {
323 if (len >= 2) {
324 iowrite16_rep(fifo, src + index, len >> 1);
325 index += len & ~0x01;
326 }
327 }
328 if (len & 0x01)
329 __raw_writeb(src[index], fifo);
330 } else {
331 /* byte aligned */
332 iowrite8_rep(fifo, src, len);
333 }
334}
335
336/*
337 * Unload an endpoint's FIFO
338 */
339static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
340{
341 struct musb *musb = hw_ep->musb;
342 void __iomem *fifo = hw_ep->fifo;
343
344 if (unlikely(len == 0))
345 return;
346
347 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
348 'R', hw_ep->epnum, fifo, len, dst);
349
350 /* we can't assume unaligned writes work */
351 if (likely((0x01 & (unsigned long) dst) == 0)) {
352 u16 index = 0;
353
354 /* best case is 32bit-aligned destination address */
355 if ((0x02 & (unsigned long) dst) == 0) {
356 if (len >= 4) {
357 ioread32_rep(fifo, dst, len >> 2);
358 index = len & ~0x03;
359 }
360 if (len & 0x02) {
361 *(u16 *)&dst[index] = __raw_readw(fifo);
362 index += 2;
363 }
364 } else {
365 if (len >= 2) {
366 ioread16_rep(fifo, dst, len >> 1);
367 index = len & ~0x01;
368 }
369 }
370 if (len & 0x01)
371 dst[index] = __raw_readb(fifo);
372 } else {
373 /* byte aligned */
374 ioread8_rep(fifo, dst, len);
375 }
376}
377
378/*
379 * Old style IO functions
380 */
381u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
382EXPORT_SYMBOL_GPL(musb_readb);
383
384void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
385EXPORT_SYMBOL_GPL(musb_writeb);
386
387u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
388EXPORT_SYMBOL_GPL(musb_readw);
389
390void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
391EXPORT_SYMBOL_GPL(musb_writew);
392
393u32 (*musb_readl)(const void __iomem *addr, unsigned offset);
394EXPORT_SYMBOL_GPL(musb_readl);
395
396void (*musb_writel)(void __iomem *addr, unsigned offset, u32 data);
397EXPORT_SYMBOL_GPL(musb_writel);
398
399#ifndef CONFIG_MUSB_PIO_ONLY
400struct dma_controller *
401(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
402EXPORT_SYMBOL(musb_dma_controller_create);
403
404void (*musb_dma_controller_destroy)(struct dma_controller *c);
405EXPORT_SYMBOL(musb_dma_controller_destroy);
406#endif
407
408/*
409 * New style IO functions
410 */
411void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
412{
413 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
414}
415
416void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
417{
418 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
419}
420
421/*-------------------------------------------------------------------------*/
422
423/* for high speed test mode; see USB 2.0 spec 7.1.20 */
424static const u8 musb_test_packet[53] = {
425 /* implicit SYNC then DATA0 to start */
426
427 /* JKJKJKJK x9 */
428 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
429 /* JJKKJJKK x8 */
430 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
431 /* JJJJKKKK x8 */
432 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
433 /* JJJJJJJKKKKKKK x8 */
434 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
435 /* JJJJJJJK x8 */
436 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
437 /* JKKKKKKK x10, JK */
438 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
439
440 /* implicit CRC16 then EOP to end */
441};
442
443void musb_load_testpacket(struct musb *musb)
444{
445 void __iomem *regs = musb->endpoints[0].regs;
446
447 musb_ep_select(musb->mregs, 0);
448 musb_write_fifo(musb->control_ep,
449 sizeof(musb_test_packet), musb_test_packet);
450 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
451}
452
453/*-------------------------------------------------------------------------*/
454
455/*
456 * Handles OTG hnp timeouts, such as b_ase0_brst
457 */
458static void musb_otg_timer_func(struct timer_list *t)
459{
460 struct musb *musb = from_timer(musb, t, otg_timer);
461 unsigned long flags;
462
463 spin_lock_irqsave(&musb->lock, flags);
464 switch (musb->xceiv->otg->state) {
465 case OTG_STATE_B_WAIT_ACON:
466 musb_dbg(musb,
467 "HNP: b_wait_acon timeout; back to b_peripheral");
468 musb_g_disconnect(musb);
469 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
470 musb->is_active = 0;
471 break;
472 case OTG_STATE_A_SUSPEND:
473 case OTG_STATE_A_WAIT_BCON:
474 musb_dbg(musb, "HNP: %s timeout",
475 usb_otg_state_string(musb->xceiv->otg->state));
476 musb_platform_set_vbus(musb, 0);
477 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
478 break;
479 default:
480 musb_dbg(musb, "HNP: Unhandled mode %s",
481 usb_otg_state_string(musb->xceiv->otg->state));
482 }
483 spin_unlock_irqrestore(&musb->lock, flags);
484}
485
486/*
487 * Stops the HNP transition. Caller must take care of locking.
488 */
489void musb_hnp_stop(struct musb *musb)
490{
491 struct usb_hcd *hcd = musb->hcd;
492 void __iomem *mbase = musb->mregs;
493 u8 reg;
494
495 musb_dbg(musb, "HNP: stop from %s",
496 usb_otg_state_string(musb->xceiv->otg->state));
497
498 switch (musb->xceiv->otg->state) {
499 case OTG_STATE_A_PERIPHERAL:
500 musb_g_disconnect(musb);
501 musb_dbg(musb, "HNP: back to %s",
502 usb_otg_state_string(musb->xceiv->otg->state));
503 break;
504 case OTG_STATE_B_HOST:
505 musb_dbg(musb, "HNP: Disabling HR");
506 if (hcd)
507 hcd->self.is_b_host = 0;
508 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
509 MUSB_DEV_MODE(musb);
510 reg = musb_readb(mbase, MUSB_POWER);
511 reg |= MUSB_POWER_SUSPENDM;
512 musb_writeb(mbase, MUSB_POWER, reg);
513 /* REVISIT: Start SESSION_REQUEST here? */
514 break;
515 default:
516 musb_dbg(musb, "HNP: Stopping in unknown state %s",
517 usb_otg_state_string(musb->xceiv->otg->state));
518 }
519
520 /*
521 * When returning to A state after HNP, avoid hub_port_rebounce(),
522 * which cause occasional OPT A "Did not receive reset after connect"
523 * errors.
524 */
525 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
526}
527
528static void musb_recover_from_babble(struct musb *musb);
529
530/*
531 * Interrupt Service Routine to record USB "global" interrupts.
532 * Since these do not happen often and signify things of
533 * paramount importance, it seems OK to check them individually;
534 * the order of the tests is specified in the manual
535 *
536 * @param musb instance pointer
537 * @param int_usb register contents
538 * @param devctl
539 * @param power
540 */
541
542static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
543 u8 devctl)
544{
545 irqreturn_t handled = IRQ_NONE;
546
547 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
548
549 /* in host mode, the peripheral may issue remote wakeup.
550 * in peripheral mode, the host may resume the link.
551 * spurious RESUME irqs happen too, paired with SUSPEND.
552 */
553 if (int_usb & MUSB_INTR_RESUME) {
554 handled = IRQ_HANDLED;
555 musb_dbg(musb, "RESUME (%s)",
556 usb_otg_state_string(musb->xceiv->otg->state));
557
558 if (devctl & MUSB_DEVCTL_HM) {
559 switch (musb->xceiv->otg->state) {
560 case OTG_STATE_A_SUSPEND:
561 /* remote wakeup? */
562 musb->port1_status |=
563 (USB_PORT_STAT_C_SUSPEND << 16)
564 | MUSB_PORT_STAT_RESUME;
565 musb->rh_timer = jiffies
566 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
567 musb->xceiv->otg->state = OTG_STATE_A_HOST;
568 musb->is_active = 1;
569 musb_host_resume_root_hub(musb);
570 schedule_delayed_work(&musb->finish_resume_work,
571 msecs_to_jiffies(USB_RESUME_TIMEOUT));
572 break;
573 case OTG_STATE_B_WAIT_ACON:
574 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
575 musb->is_active = 1;
576 MUSB_DEV_MODE(musb);
577 break;
578 default:
579 WARNING("bogus %s RESUME (%s)\n",
580 "host",
581 usb_otg_state_string(musb->xceiv->otg->state));
582 }
583 } else {
584 switch (musb->xceiv->otg->state) {
585 case OTG_STATE_A_SUSPEND:
586 /* possibly DISCONNECT is upcoming */
587 musb->xceiv->otg->state = OTG_STATE_A_HOST;
588 musb_host_resume_root_hub(musb);
589 break;
590 case OTG_STATE_B_WAIT_ACON:
591 case OTG_STATE_B_PERIPHERAL:
592 /* disconnect while suspended? we may
593 * not get a disconnect irq...
594 */
595 if ((devctl & MUSB_DEVCTL_VBUS)
596 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
597 ) {
598 musb->int_usb |= MUSB_INTR_DISCONNECT;
599 musb->int_usb &= ~MUSB_INTR_SUSPEND;
600 break;
601 }
602 musb_g_resume(musb);
603 break;
604 case OTG_STATE_B_IDLE:
605 musb->int_usb &= ~MUSB_INTR_SUSPEND;
606 break;
607 default:
608 WARNING("bogus %s RESUME (%s)\n",
609 "peripheral",
610 usb_otg_state_string(musb->xceiv->otg->state));
611 }
612 }
613 }
614
615 /* see manual for the order of the tests */
616 if (int_usb & MUSB_INTR_SESSREQ) {
617 void __iomem *mbase = musb->mregs;
618
619 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
620 && (devctl & MUSB_DEVCTL_BDEVICE)) {
621 musb_dbg(musb, "SessReq while on B state");
622 return IRQ_HANDLED;
623 }
624
625 musb_dbg(musb, "SESSION_REQUEST (%s)",
626 usb_otg_state_string(musb->xceiv->otg->state));
627
628 /* IRQ arrives from ID pin sense or (later, if VBUS power
629 * is removed) SRP. responses are time critical:
630 * - turn on VBUS (with silicon-specific mechanism)
631 * - go through A_WAIT_VRISE
632 * - ... to A_WAIT_BCON.
633 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
634 */
635 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
636 musb->ep0_stage = MUSB_EP0_START;
637 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
638 MUSB_HST_MODE(musb);
639 musb_platform_set_vbus(musb, 1);
640
641 handled = IRQ_HANDLED;
642 }
643
644 if (int_usb & MUSB_INTR_VBUSERROR) {
645 int ignore = 0;
646
647 /* During connection as an A-Device, we may see a short
648 * current spikes causing voltage drop, because of cable
649 * and peripheral capacitance combined with vbus draw.
650 * (So: less common with truly self-powered devices, where
651 * vbus doesn't act like a power supply.)
652 *
653 * Such spikes are short; usually less than ~500 usec, max
654 * of ~2 msec. That is, they're not sustained overcurrent
655 * errors, though they're reported using VBUSERROR irqs.
656 *
657 * Workarounds: (a) hardware: use self powered devices.
658 * (b) software: ignore non-repeated VBUS errors.
659 *
660 * REVISIT: do delays from lots of DEBUG_KERNEL checks
661 * make trouble here, keeping VBUS < 4.4V ?
662 */
663 switch (musb->xceiv->otg->state) {
664 case OTG_STATE_A_HOST:
665 /* recovery is dicey once we've gotten past the
666 * initial stages of enumeration, but if VBUS
667 * stayed ok at the other end of the link, and
668 * another reset is due (at least for high speed,
669 * to redo the chirp etc), it might work OK...
670 */
671 case OTG_STATE_A_WAIT_BCON:
672 case OTG_STATE_A_WAIT_VRISE:
673 if (musb->vbuserr_retry) {
674 void __iomem *mbase = musb->mregs;
675
676 musb->vbuserr_retry--;
677 ignore = 1;
678 devctl |= MUSB_DEVCTL_SESSION;
679 musb_writeb(mbase, MUSB_DEVCTL, devctl);
680 } else {
681 musb->port1_status |=
682 USB_PORT_STAT_OVERCURRENT
683 | (USB_PORT_STAT_C_OVERCURRENT << 16);
684 }
685 break;
686 default:
687 break;
688 }
689
690 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
691 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
692 usb_otg_state_string(musb->xceiv->otg->state),
693 devctl,
694 ({ char *s;
695 switch (devctl & MUSB_DEVCTL_VBUS) {
696 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
697 s = "<SessEnd"; break;
698 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
699 s = "<AValid"; break;
700 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
701 s = "<VBusValid"; break;
702 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
703 default:
704 s = "VALID"; break;
705 } s; }),
706 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
707 musb->port1_status);
708
709 /* go through A_WAIT_VFALL then start a new session */
710 if (!ignore)
711 musb_platform_set_vbus(musb, 0);
712 handled = IRQ_HANDLED;
713 }
714
715 if (int_usb & MUSB_INTR_SUSPEND) {
716 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
717 usb_otg_state_string(musb->xceiv->otg->state), devctl);
718 handled = IRQ_HANDLED;
719
720 switch (musb->xceiv->otg->state) {
721 case OTG_STATE_A_PERIPHERAL:
722 /* We also come here if the cable is removed, since
723 * this silicon doesn't report ID-no-longer-grounded.
724 *
725 * We depend on T(a_wait_bcon) to shut us down, and
726 * hope users don't do anything dicey during this
727 * undesired detour through A_WAIT_BCON.
728 */
729 musb_hnp_stop(musb);
730 musb_host_resume_root_hub(musb);
731 musb_root_disconnect(musb);
732 musb_platform_try_idle(musb, jiffies
733 + msecs_to_jiffies(musb->a_wait_bcon
734 ? : OTG_TIME_A_WAIT_BCON));
735
736 break;
737 case OTG_STATE_B_IDLE:
738 if (!musb->is_active)
739 break;
740 /* fall through */
741 case OTG_STATE_B_PERIPHERAL:
742 musb_g_suspend(musb);
743 musb->is_active = musb->g.b_hnp_enable;
744 if (musb->is_active) {
745 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
746 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
747 mod_timer(&musb->otg_timer, jiffies
748 + msecs_to_jiffies(
749 OTG_TIME_B_ASE0_BRST));
750 }
751 break;
752 case OTG_STATE_A_WAIT_BCON:
753 if (musb->a_wait_bcon != 0)
754 musb_platform_try_idle(musb, jiffies
755 + msecs_to_jiffies(musb->a_wait_bcon));
756 break;
757 case OTG_STATE_A_HOST:
758 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
759 musb->is_active = musb->hcd->self.b_hnp_enable;
760 break;
761 case OTG_STATE_B_HOST:
762 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
763 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
764 break;
765 default:
766 /* "should not happen" */
767 musb->is_active = 0;
768 break;
769 }
770 }
771
772 if (int_usb & MUSB_INTR_CONNECT) {
773 struct usb_hcd *hcd = musb->hcd;
774
775 handled = IRQ_HANDLED;
776 musb->is_active = 1;
777
778 musb->ep0_stage = MUSB_EP0_START;
779
780 musb->intrtxe = musb->epmask;
781 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
782 musb->intrrxe = musb->epmask & 0xfffe;
783 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
784 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
785 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
786 |USB_PORT_STAT_HIGH_SPEED
787 |USB_PORT_STAT_ENABLE
788 );
789 musb->port1_status |= USB_PORT_STAT_CONNECTION
790 |(USB_PORT_STAT_C_CONNECTION << 16);
791
792 /* high vs full speed is just a guess until after reset */
793 if (devctl & MUSB_DEVCTL_LSDEV)
794 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
795
796 /* indicate new connection to OTG machine */
797 switch (musb->xceiv->otg->state) {
798 case OTG_STATE_B_PERIPHERAL:
799 if (int_usb & MUSB_INTR_SUSPEND) {
800 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
801 int_usb &= ~MUSB_INTR_SUSPEND;
802 goto b_host;
803 } else
804 musb_dbg(musb, "CONNECT as b_peripheral???");
805 break;
806 case OTG_STATE_B_WAIT_ACON:
807 musb_dbg(musb, "HNP: CONNECT, now b_host");
808b_host:
809 musb->xceiv->otg->state = OTG_STATE_B_HOST;
810 if (musb->hcd)
811 musb->hcd->self.is_b_host = 1;
812 del_timer(&musb->otg_timer);
813 break;
814 default:
815 if ((devctl & MUSB_DEVCTL_VBUS)
816 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
817 musb->xceiv->otg->state = OTG_STATE_A_HOST;
818 if (hcd)
819 hcd->self.is_b_host = 0;
820 }
821 break;
822 }
823
824 musb_host_poke_root_hub(musb);
825
826 musb_dbg(musb, "CONNECT (%s) devctl %02x",
827 usb_otg_state_string(musb->xceiv->otg->state), devctl);
828 }
829
830 if (int_usb & MUSB_INTR_DISCONNECT) {
831 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
832 usb_otg_state_string(musb->xceiv->otg->state),
833 MUSB_MODE(musb), devctl);
834 handled = IRQ_HANDLED;
835
836 switch (musb->xceiv->otg->state) {
837 case OTG_STATE_A_HOST:
838 case OTG_STATE_A_SUSPEND:
839 musb_host_resume_root_hub(musb);
840 musb_root_disconnect(musb);
841 if (musb->a_wait_bcon != 0)
842 musb_platform_try_idle(musb, jiffies
843 + msecs_to_jiffies(musb->a_wait_bcon));
844 break;
845 case OTG_STATE_B_HOST:
846 /* REVISIT this behaves for "real disconnect"
847 * cases; make sure the other transitions from
848 * from B_HOST act right too. The B_HOST code
849 * in hnp_stop() is currently not used...
850 */
851 musb_root_disconnect(musb);
852 if (musb->hcd)
853 musb->hcd->self.is_b_host = 0;
854 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
855 MUSB_DEV_MODE(musb);
856 musb_g_disconnect(musb);
857 break;
858 case OTG_STATE_A_PERIPHERAL:
859 musb_hnp_stop(musb);
860 musb_root_disconnect(musb);
861 /* FALLTHROUGH */
862 case OTG_STATE_B_WAIT_ACON:
863 /* FALLTHROUGH */
864 case OTG_STATE_B_PERIPHERAL:
865 case OTG_STATE_B_IDLE:
866 musb_g_disconnect(musb);
867 break;
868 default:
869 WARNING("unhandled DISCONNECT transition (%s)\n",
870 usb_otg_state_string(musb->xceiv->otg->state));
871 break;
872 }
873 }
874
875 /* mentor saves a bit: bus reset and babble share the same irq.
876 * only host sees babble; only peripheral sees bus reset.
877 */
878 if (int_usb & MUSB_INTR_RESET) {
879 handled = IRQ_HANDLED;
880 if (is_host_active(musb)) {
881 /*
882 * When BABBLE happens what we can depends on which
883 * platform MUSB is running, because some platforms
884 * implemented proprietary means for 'recovering' from
885 * Babble conditions. One such platform is AM335x. In
886 * most cases, however, the only thing we can do is
887 * drop the session.
888 */
889 dev_err(musb->controller, "Babble\n");
890 musb_recover_from_babble(musb);
891 } else {
892 musb_dbg(musb, "BUS RESET as %s",
893 usb_otg_state_string(musb->xceiv->otg->state));
894 switch (musb->xceiv->otg->state) {
895 case OTG_STATE_A_SUSPEND:
896 musb_g_reset(musb);
897 /* FALLTHROUGH */
898 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
899 /* never use invalid T(a_wait_bcon) */
900 musb_dbg(musb, "HNP: in %s, %d msec timeout",
901 usb_otg_state_string(musb->xceiv->otg->state),
902 TA_WAIT_BCON(musb));
903 mod_timer(&musb->otg_timer, jiffies
904 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
905 break;
906 case OTG_STATE_A_PERIPHERAL:
907 del_timer(&musb->otg_timer);
908 musb_g_reset(musb);
909 break;
910 case OTG_STATE_B_WAIT_ACON:
911 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
912 usb_otg_state_string(musb->xceiv->otg->state));
913 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
914 musb_g_reset(musb);
915 break;
916 case OTG_STATE_B_IDLE:
917 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
918 /* FALLTHROUGH */
919 case OTG_STATE_B_PERIPHERAL:
920 musb_g_reset(musb);
921 break;
922 default:
923 musb_dbg(musb, "Unhandled BUS RESET as %s",
924 usb_otg_state_string(musb->xceiv->otg->state));
925 }
926 }
927 }
928
929#if 0
930/* REVISIT ... this would be for multiplexing periodic endpoints, or
931 * supporting transfer phasing to prevent exceeding ISO bandwidth
932 * limits of a given frame or microframe.
933 *
934 * It's not needed for peripheral side, which dedicates endpoints;
935 * though it _might_ use SOF irqs for other purposes.
936 *
937 * And it's not currently needed for host side, which also dedicates
938 * endpoints, relies on TX/RX interval registers, and isn't claimed
939 * to support ISO transfers yet.
940 */
941 if (int_usb & MUSB_INTR_SOF) {
942 void __iomem *mbase = musb->mregs;
943 struct musb_hw_ep *ep;
944 u8 epnum;
945 u16 frame;
946
947 dev_dbg(musb->controller, "START_OF_FRAME\n");
948 handled = IRQ_HANDLED;
949
950 /* start any periodic Tx transfers waiting for current frame */
951 frame = musb_readw(mbase, MUSB_FRAME);
952 ep = musb->endpoints;
953 for (epnum = 1; (epnum < musb->nr_endpoints)
954 && (musb->epmask >= (1 << epnum));
955 epnum++, ep++) {
956 /*
957 * FIXME handle framecounter wraps (12 bits)
958 * eliminate duplicated StartUrb logic
959 */
960 if (ep->dwWaitFrame >= frame) {
961 ep->dwWaitFrame = 0;
962 pr_debug("SOF --> periodic TX%s on %d\n",
963 ep->tx_channel ? " DMA" : "",
964 epnum);
965 if (!ep->tx_channel)
966 musb_h_tx_start(musb, epnum);
967 else
968 cppi_hostdma_start(musb, epnum);
969 }
970 } /* end of for loop */
971 }
972#endif
973
974 schedule_delayed_work(&musb->irq_work, 0);
975
976 return handled;
977}
978
979/*-------------------------------------------------------------------------*/
980
981static void musb_disable_interrupts(struct musb *musb)
982{
983 void __iomem *mbase = musb->mregs;
984 u16 temp;
985
986 /* disable interrupts */
987 musb_writeb(mbase, MUSB_INTRUSBE, 0);
988 musb->intrtxe = 0;
989 musb_writew(mbase, MUSB_INTRTXE, 0);
990 musb->intrrxe = 0;
991 musb_writew(mbase, MUSB_INTRRXE, 0);
992
993 /* flush pending interrupts */
994 temp = musb_readb(mbase, MUSB_INTRUSB);
995 temp = musb_readw(mbase, MUSB_INTRTX);
996 temp = musb_readw(mbase, MUSB_INTRRX);
997}
998
999static void musb_enable_interrupts(struct musb *musb)
1000{
1001 void __iomem *regs = musb->mregs;
1002
1003 /* Set INT enable registers, enable interrupts */
1004 musb->intrtxe = musb->epmask;
1005 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1006 musb->intrrxe = musb->epmask & 0xfffe;
1007 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1008 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1009
1010}
1011
1012/*
1013 * Program the HDRC to start (enable interrupts, dma, etc.).
1014 */
1015void musb_start(struct musb *musb)
1016{
1017 void __iomem *regs = musb->mregs;
1018 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1019 u8 power;
1020
1021 musb_dbg(musb, "<== devctl %02x", devctl);
1022
1023 musb_enable_interrupts(musb);
1024 musb_writeb(regs, MUSB_TESTMODE, 0);
1025
1026 power = MUSB_POWER_ISOUPDATE;
1027 /*
1028 * treating UNKNOWN as unspecified maximum speed, in which case
1029 * we will default to high-speed.
1030 */
1031 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1032 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1033 power |= MUSB_POWER_HSENAB;
1034 musb_writeb(regs, MUSB_POWER, power);
1035
1036 musb->is_active = 0;
1037 devctl = musb_readb(regs, MUSB_DEVCTL);
1038 devctl &= ~MUSB_DEVCTL_SESSION;
1039
1040 /* session started after:
1041 * (a) ID-grounded irq, host mode;
1042 * (b) vbus present/connect IRQ, peripheral mode;
1043 * (c) peripheral initiates, using SRP
1044 */
1045 if (musb->port_mode != MUSB_PORT_MODE_HOST &&
1046 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1047 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1048 musb->is_active = 1;
1049 } else {
1050 devctl |= MUSB_DEVCTL_SESSION;
1051 }
1052
1053 musb_platform_enable(musb);
1054 musb_writeb(regs, MUSB_DEVCTL, devctl);
1055}
1056
1057/*
1058 * Make the HDRC stop (disable interrupts, etc.);
1059 * reversible by musb_start
1060 * called on gadget driver unregister
1061 * with controller locked, irqs blocked
1062 * acts as a NOP unless some role activated the hardware
1063 */
1064void musb_stop(struct musb *musb)
1065{
1066 /* stop IRQs, timers, ... */
1067 musb_platform_disable(musb);
1068 musb_disable_interrupts(musb);
1069 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1070
1071 /* FIXME
1072 * - mark host and/or peripheral drivers unusable/inactive
1073 * - disable DMA (and enable it in HdrcStart)
1074 * - make sure we can musb_start() after musb_stop(); with
1075 * OTG mode, gadget driver module rmmod/modprobe cycles that
1076 * - ...
1077 */
1078 musb_platform_try_idle(musb, 0);
1079}
1080
1081/*-------------------------------------------------------------------------*/
1082
1083/*
1084 * The silicon either has hard-wired endpoint configurations, or else
1085 * "dynamic fifo" sizing. The driver has support for both, though at this
1086 * writing only the dynamic sizing is very well tested. Since we switched
1087 * away from compile-time hardware parameters, we can no longer rely on
1088 * dead code elimination to leave only the relevant one in the object file.
1089 *
1090 * We don't currently use dynamic fifo setup capability to do anything
1091 * more than selecting one of a bunch of predefined configurations.
1092 */
1093static ushort fifo_mode;
1094
1095/* "modprobe ... fifo_mode=1" etc */
1096module_param(fifo_mode, ushort, 0);
1097MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1098
1099/*
1100 * tables defining fifo_mode values. define more if you like.
1101 * for host side, make sure both halves of ep1 are set up.
1102 */
1103
1104/* mode 0 - fits in 2KB */
1105static struct musb_fifo_cfg mode_0_cfg[] = {
1106{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1107{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1108{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1109{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1110{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1111};
1112
1113/* mode 1 - fits in 4KB */
1114static struct musb_fifo_cfg mode_1_cfg[] = {
1115{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1116{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1117{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1118{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1119{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1120};
1121
1122/* mode 2 - fits in 4KB */
1123static struct musb_fifo_cfg mode_2_cfg[] = {
1124{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1125{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1126{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1127{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1128{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
1129{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
1130};
1131
1132/* mode 3 - fits in 4KB */
1133static struct musb_fifo_cfg mode_3_cfg[] = {
1134{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1135{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1136{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1137{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1138{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1139{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1140};
1141
1142/* mode 4 - fits in 16KB */
1143static struct musb_fifo_cfg mode_4_cfg[] = {
1144{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1145{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1146{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1147{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1148{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1149{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1150{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1151{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1152{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1153{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1154{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1155{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1156{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1157{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1158{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1159{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1160{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1161{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1162{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1163{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1164{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1165{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1166{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1167{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1168{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1169{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1170{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1171};
1172
1173/* mode 5 - fits in 8KB */
1174static struct musb_fifo_cfg mode_5_cfg[] = {
1175{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1176{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1177{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1178{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1179{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1180{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1181{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1182{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1183{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1184{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1185{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1186{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1187{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1188{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1189{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1190{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1191{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1192{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1193{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1194{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1195{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1196{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1197{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1198{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1199{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1200{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1201{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1202};
1203
1204/*
1205 * configure a fifo; for non-shared endpoints, this may be called
1206 * once for a tx fifo and once for an rx fifo.
1207 *
1208 * returns negative errno or offset for next fifo.
1209 */
1210static int
1211fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1212 const struct musb_fifo_cfg *cfg, u16 offset)
1213{
1214 void __iomem *mbase = musb->mregs;
1215 int size = 0;
1216 u16 maxpacket = cfg->maxpacket;
1217 u16 c_off = offset >> 3;
1218 u8 c_size;
1219
1220 /* expect hw_ep has already been zero-initialized */
1221
1222 size = ffs(max(maxpacket, (u16) 8)) - 1;
1223 maxpacket = 1 << size;
1224
1225 c_size = size - 3;
1226 if (cfg->mode == BUF_DOUBLE) {
1227 if ((offset + (maxpacket << 1)) >
1228 (1 << (musb->config->ram_bits + 2)))
1229 return -EMSGSIZE;
1230 c_size |= MUSB_FIFOSZ_DPB;
1231 } else {
1232 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1233 return -EMSGSIZE;
1234 }
1235
1236 /* configure the FIFO */
1237 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1238
1239 /* EP0 reserved endpoint for control, bidirectional;
1240 * EP1 reserved for bulk, two unidirectional halves.
1241 */
1242 if (hw_ep->epnum == 1)
1243 musb->bulk_ep = hw_ep;
1244 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1245 switch (cfg->style) {
1246 case FIFO_TX:
1247 musb_write_txfifosz(mbase, c_size);
1248 musb_write_txfifoadd(mbase, c_off);
1249 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1250 hw_ep->max_packet_sz_tx = maxpacket;
1251 break;
1252 case FIFO_RX:
1253 musb_write_rxfifosz(mbase, c_size);
1254 musb_write_rxfifoadd(mbase, c_off);
1255 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1256 hw_ep->max_packet_sz_rx = maxpacket;
1257 break;
1258 case FIFO_RXTX:
1259 musb_write_txfifosz(mbase, c_size);
1260 musb_write_txfifoadd(mbase, c_off);
1261 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1262 hw_ep->max_packet_sz_rx = maxpacket;
1263
1264 musb_write_rxfifosz(mbase, c_size);
1265 musb_write_rxfifoadd(mbase, c_off);
1266 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1267 hw_ep->max_packet_sz_tx = maxpacket;
1268
1269 hw_ep->is_shared_fifo = true;
1270 break;
1271 }
1272
1273 /* NOTE rx and tx endpoint irqs aren't managed separately,
1274 * which happens to be ok
1275 */
1276 musb->epmask |= (1 << hw_ep->epnum);
1277
1278 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1279}
1280
1281static struct musb_fifo_cfg ep0_cfg = {
1282 .style = FIFO_RXTX, .maxpacket = 64,
1283};
1284
1285static int ep_config_from_table(struct musb *musb)
1286{
1287 const struct musb_fifo_cfg *cfg;
1288 unsigned i, n;
1289 int offset;
1290 struct musb_hw_ep *hw_ep = musb->endpoints;
1291
1292 if (musb->config->fifo_cfg) {
1293 cfg = musb->config->fifo_cfg;
1294 n = musb->config->fifo_cfg_size;
1295 goto done;
1296 }
1297
1298 switch (fifo_mode) {
1299 default:
1300 fifo_mode = 0;
1301 /* FALLTHROUGH */
1302 case 0:
1303 cfg = mode_0_cfg;
1304 n = ARRAY_SIZE(mode_0_cfg);
1305 break;
1306 case 1:
1307 cfg = mode_1_cfg;
1308 n = ARRAY_SIZE(mode_1_cfg);
1309 break;
1310 case 2:
1311 cfg = mode_2_cfg;
1312 n = ARRAY_SIZE(mode_2_cfg);
1313 break;
1314 case 3:
1315 cfg = mode_3_cfg;
1316 n = ARRAY_SIZE(mode_3_cfg);
1317 break;
1318 case 4:
1319 cfg = mode_4_cfg;
1320 n = ARRAY_SIZE(mode_4_cfg);
1321 break;
1322 case 5:
1323 cfg = mode_5_cfg;
1324 n = ARRAY_SIZE(mode_5_cfg);
1325 break;
1326 }
1327
1328 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1329
1330
1331done:
1332 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1333 /* assert(offset > 0) */
1334
1335 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1336 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1337 */
1338
1339 for (i = 0; i < n; i++) {
1340 u8 epn = cfg->hw_ep_num;
1341
1342 if (epn >= musb->config->num_eps) {
1343 pr_debug("%s: invalid ep %d\n",
1344 musb_driver_name, epn);
1345 return -EINVAL;
1346 }
1347 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1348 if (offset < 0) {
1349 pr_debug("%s: mem overrun, ep %d\n",
1350 musb_driver_name, epn);
1351 return offset;
1352 }
1353 epn++;
1354 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1355 }
1356
1357 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1358 musb_driver_name,
1359 n + 1, musb->config->num_eps * 2 - 1,
1360 offset, (1 << (musb->config->ram_bits + 2)));
1361
1362 if (!musb->bulk_ep) {
1363 pr_debug("%s: missing bulk\n", musb_driver_name);
1364 return -EINVAL;
1365 }
1366
1367 return 0;
1368}
1369
1370
1371/*
1372 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1373 * @param musb the controller
1374 */
1375static int ep_config_from_hw(struct musb *musb)
1376{
1377 u8 epnum = 0;
1378 struct musb_hw_ep *hw_ep;
1379 void __iomem *mbase = musb->mregs;
1380 int ret = 0;
1381
1382 musb_dbg(musb, "<== static silicon ep config");
1383
1384 /* FIXME pick up ep0 maxpacket size */
1385
1386 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1387 musb_ep_select(mbase, epnum);
1388 hw_ep = musb->endpoints + epnum;
1389
1390 ret = musb_read_fifosize(musb, hw_ep, epnum);
1391 if (ret < 0)
1392 break;
1393
1394 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1395
1396 /* pick an RX/TX endpoint for bulk */
1397 if (hw_ep->max_packet_sz_tx < 512
1398 || hw_ep->max_packet_sz_rx < 512)
1399 continue;
1400
1401 /* REVISIT: this algorithm is lazy, we should at least
1402 * try to pick a double buffered endpoint.
1403 */
1404 if (musb->bulk_ep)
1405 continue;
1406 musb->bulk_ep = hw_ep;
1407 }
1408
1409 if (!musb->bulk_ep) {
1410 pr_debug("%s: missing bulk\n", musb_driver_name);
1411 return -EINVAL;
1412 }
1413
1414 return 0;
1415}
1416
1417enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1418
1419/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1420 * configure endpoints, or take their config from silicon
1421 */
1422static int musb_core_init(u16 musb_type, struct musb *musb)
1423{
1424 u8 reg;
1425 char *type;
1426 char aInfo[90];
1427 void __iomem *mbase = musb->mregs;
1428 int status = 0;
1429 int i;
1430
1431 /* log core options (read using indexed model) */
1432 reg = musb_read_configdata(mbase);
1433
1434 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1435 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1436 strcat(aInfo, ", dyn FIFOs");
1437 musb->dyn_fifo = true;
1438 }
1439 if (reg & MUSB_CONFIGDATA_MPRXE) {
1440 strcat(aInfo, ", bulk combine");
1441 musb->bulk_combine = true;
1442 }
1443 if (reg & MUSB_CONFIGDATA_MPTXE) {
1444 strcat(aInfo, ", bulk split");
1445 musb->bulk_split = true;
1446 }
1447 if (reg & MUSB_CONFIGDATA_HBRXE) {
1448 strcat(aInfo, ", HB-ISO Rx");
1449 musb->hb_iso_rx = true;
1450 }
1451 if (reg & MUSB_CONFIGDATA_HBTXE) {
1452 strcat(aInfo, ", HB-ISO Tx");
1453 musb->hb_iso_tx = true;
1454 }
1455 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1456 strcat(aInfo, ", SoftConn");
1457
1458 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1459
1460 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1461 musb->is_multipoint = 1;
1462 type = "M";
1463 } else {
1464 musb->is_multipoint = 0;
1465 type = "";
1466#ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1467 pr_err("%s: kernel must blacklist external hubs\n",
1468 musb_driver_name);
1469#endif
1470 }
1471
1472 /* log release info */
1473 musb->hwvers = musb_read_hwvers(mbase);
1474 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1475 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1476 MUSB_HWVERS_MINOR(musb->hwvers),
1477 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1478
1479 /* configure ep0 */
1480 musb_configure_ep0(musb);
1481
1482 /* discover endpoint configuration */
1483 musb->nr_endpoints = 1;
1484 musb->epmask = 1;
1485
1486 if (musb->dyn_fifo)
1487 status = ep_config_from_table(musb);
1488 else
1489 status = ep_config_from_hw(musb);
1490
1491 if (status < 0)
1492 return status;
1493
1494 /* finish init, and print endpoint config */
1495 for (i = 0; i < musb->nr_endpoints; i++) {
1496 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1497
1498 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1499#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1500 if (musb->io.quirks & MUSB_IN_TUSB) {
1501 hw_ep->fifo_async = musb->async + 0x400 +
1502 musb->io.fifo_offset(i);
1503 hw_ep->fifo_sync = musb->sync + 0x400 +
1504 musb->io.fifo_offset(i);
1505 hw_ep->fifo_sync_va =
1506 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1507
1508 if (i == 0)
1509 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1510 else
1511 hw_ep->conf = mbase + 0x400 +
1512 (((i - 1) & 0xf) << 2);
1513 }
1514#endif
1515
1516 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1517 hw_ep->rx_reinit = 1;
1518 hw_ep->tx_reinit = 1;
1519
1520 if (hw_ep->max_packet_sz_tx) {
1521 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1522 musb_driver_name, i,
1523 hw_ep->is_shared_fifo ? "shared" : "tx",
1524 hw_ep->tx_double_buffered
1525 ? "doublebuffer, " : "",
1526 hw_ep->max_packet_sz_tx);
1527 }
1528 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1529 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1530 musb_driver_name, i,
1531 "rx",
1532 hw_ep->rx_double_buffered
1533 ? "doublebuffer, " : "",
1534 hw_ep->max_packet_sz_rx);
1535 }
1536 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1537 musb_dbg(musb, "hw_ep %d not configured", i);
1538 }
1539
1540 return 0;
1541}
1542
1543/*-------------------------------------------------------------------------*/
1544
1545/*
1546 * handle all the irqs defined by the HDRC core. for now we expect: other
1547 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1548 * will be assigned, and the irq will already have been acked.
1549 *
1550 * called in irq context with spinlock held, irqs blocked
1551 */
1552irqreturn_t musb_interrupt(struct musb *musb)
1553{
1554 irqreturn_t retval = IRQ_NONE;
1555 unsigned long status;
1556 unsigned long epnum;
1557 u8 devctl;
1558
1559 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1560 return IRQ_NONE;
1561
1562 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1563
1564 trace_musb_isr(musb);
1565
1566 /**
1567 * According to Mentor Graphics' documentation, flowchart on page 98,
1568 * IRQ should be handled as follows:
1569 *
1570 * . Resume IRQ
1571 * . Session Request IRQ
1572 * . VBUS Error IRQ
1573 * . Suspend IRQ
1574 * . Connect IRQ
1575 * . Disconnect IRQ
1576 * . Reset/Babble IRQ
1577 * . SOF IRQ (we're not using this one)
1578 * . Endpoint 0 IRQ
1579 * . TX Endpoints
1580 * . RX Endpoints
1581 *
1582 * We will be following that flowchart in order to avoid any problems
1583 * that might arise with internal Finite State Machine.
1584 */
1585
1586 if (musb->int_usb)
1587 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1588
1589 if (musb->int_tx & 1) {
1590 if (is_host_active(musb))
1591 retval |= musb_h_ep0_irq(musb);
1592 else
1593 retval |= musb_g_ep0_irq(musb);
1594
1595 /* we have just handled endpoint 0 IRQ, clear it */
1596 musb->int_tx &= ~BIT(0);
1597 }
1598
1599 status = musb->int_tx;
1600
1601 for_each_set_bit(epnum, &status, 16) {
1602 retval = IRQ_HANDLED;
1603 if (is_host_active(musb))
1604 musb_host_tx(musb, epnum);
1605 else
1606 musb_g_tx(musb, epnum);
1607 }
1608
1609 status = musb->int_rx;
1610
1611 for_each_set_bit(epnum, &status, 16) {
1612 retval = IRQ_HANDLED;
1613 if (is_host_active(musb))
1614 musb_host_rx(musb, epnum);
1615 else
1616 musb_g_rx(musb, epnum);
1617 }
1618
1619 return retval;
1620}
1621EXPORT_SYMBOL_GPL(musb_interrupt);
1622
1623#ifndef CONFIG_MUSB_PIO_ONLY
1624static bool use_dma = 1;
1625
1626/* "modprobe ... use_dma=0" etc */
1627module_param(use_dma, bool, 0644);
1628MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1629
1630void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1631{
1632 /* called with controller lock already held */
1633
1634 if (!epnum) {
1635 if (!is_cppi_enabled(musb)) {
1636 /* endpoint 0 */
1637 if (is_host_active(musb))
1638 musb_h_ep0_irq(musb);
1639 else
1640 musb_g_ep0_irq(musb);
1641 }
1642 } else {
1643 /* endpoints 1..15 */
1644 if (transmit) {
1645 if (is_host_active(musb))
1646 musb_host_tx(musb, epnum);
1647 else
1648 musb_g_tx(musb, epnum);
1649 } else {
1650 /* receive */
1651 if (is_host_active(musb))
1652 musb_host_rx(musb, epnum);
1653 else
1654 musb_g_rx(musb, epnum);
1655 }
1656 }
1657}
1658EXPORT_SYMBOL_GPL(musb_dma_completion);
1659
1660#else
1661#define use_dma 0
1662#endif
1663
1664static int (*musb_phy_callback)(enum musb_vbus_id_status status);
1665
1666/*
1667 * musb_mailbox - optional phy notifier function
1668 * @status phy state change
1669 *
1670 * Optionally gets called from the USB PHY. Note that the USB PHY must be
1671 * disabled at the point the phy_callback is registered or unregistered.
1672 */
1673int musb_mailbox(enum musb_vbus_id_status status)
1674{
1675 if (musb_phy_callback)
1676 return musb_phy_callback(status);
1677
1678 return -ENODEV;
1679};
1680EXPORT_SYMBOL_GPL(musb_mailbox);
1681
1682/*-------------------------------------------------------------------------*/
1683
1684static ssize_t
1685mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1686{
1687 struct musb *musb = dev_to_musb(dev);
1688 unsigned long flags;
1689 int ret = -EINVAL;
1690
1691 spin_lock_irqsave(&musb->lock, flags);
1692 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1693 spin_unlock_irqrestore(&musb->lock, flags);
1694
1695 return ret;
1696}
1697
1698static ssize_t
1699mode_store(struct device *dev, struct device_attribute *attr,
1700 const char *buf, size_t n)
1701{
1702 struct musb *musb = dev_to_musb(dev);
1703 unsigned long flags;
1704 int status;
1705
1706 spin_lock_irqsave(&musb->lock, flags);
1707 if (sysfs_streq(buf, "host"))
1708 status = musb_platform_set_mode(musb, MUSB_HOST);
1709 else if (sysfs_streq(buf, "peripheral"))
1710 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1711 else if (sysfs_streq(buf, "otg"))
1712 status = musb_platform_set_mode(musb, MUSB_OTG);
1713 else
1714 status = -EINVAL;
1715 spin_unlock_irqrestore(&musb->lock, flags);
1716
1717 return (status == 0) ? n : status;
1718}
1719static DEVICE_ATTR_RW(mode);
1720
1721static ssize_t
1722vbus_store(struct device *dev, struct device_attribute *attr,
1723 const char *buf, size_t n)
1724{
1725 struct musb *musb = dev_to_musb(dev);
1726 unsigned long flags;
1727 unsigned long val;
1728
1729 if (sscanf(buf, "%lu", &val) < 1) {
1730 dev_err(dev, "Invalid VBUS timeout ms value\n");
1731 return -EINVAL;
1732 }
1733
1734 spin_lock_irqsave(&musb->lock, flags);
1735 /* force T(a_wait_bcon) to be zero/unlimited *OR* valid */
1736 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1737 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1738 musb->is_active = 0;
1739 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1740 spin_unlock_irqrestore(&musb->lock, flags);
1741
1742 return n;
1743}
1744
1745static ssize_t
1746vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1747{
1748 struct musb *musb = dev_to_musb(dev);
1749 unsigned long flags;
1750 unsigned long val;
1751 int vbus;
1752 u8 devctl;
1753
1754 pm_runtime_get_sync(dev);
1755 spin_lock_irqsave(&musb->lock, flags);
1756 val = musb->a_wait_bcon;
1757 vbus = musb_platform_get_vbus_status(musb);
1758 if (vbus < 0) {
1759 /* Use default MUSB method by means of DEVCTL register */
1760 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1761 if ((devctl & MUSB_DEVCTL_VBUS)
1762 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1763 vbus = 1;
1764 else
1765 vbus = 0;
1766 }
1767 spin_unlock_irqrestore(&musb->lock, flags);
1768 pm_runtime_put_sync(dev);
1769
1770 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1771 vbus ? "on" : "off", val);
1772}
1773static DEVICE_ATTR_RW(vbus);
1774
1775/* Gadget drivers can't know that a host is connected so they might want
1776 * to start SRP, but users can. This allows userspace to trigger SRP.
1777 */
1778static ssize_t srp_store(struct device *dev, struct device_attribute *attr,
1779 const char *buf, size_t n)
1780{
1781 struct musb *musb = dev_to_musb(dev);
1782 unsigned short srp;
1783
1784 if (sscanf(buf, "%hu", &srp) != 1
1785 || (srp != 1)) {
1786 dev_err(dev, "SRP: Value must be 1\n");
1787 return -EINVAL;
1788 }
1789
1790 if (srp == 1)
1791 musb_g_wakeup(musb);
1792
1793 return n;
1794}
1795static DEVICE_ATTR_WO(srp);
1796
1797static struct attribute *musb_attributes[] = {
1798 &dev_attr_mode.attr,
1799 &dev_attr_vbus.attr,
1800 &dev_attr_srp.attr,
1801 NULL
1802};
1803
1804static const struct attribute_group musb_attr_group = {
1805 .attrs = musb_attributes,
1806};
1807
1808#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1809 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1810 MUSB_DEVCTL_SESSION)
1811#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1812 MUSB_DEVCTL_SESSION)
1813
1814/*
1815 * Check the musb devctl session bit to determine if we want to
1816 * allow PM runtime for the device. In general, we want to keep things
1817 * active when the session bit is set except after host disconnect.
1818 *
1819 * Only called from musb_irq_work. If this ever needs to get called
1820 * elsewhere, proper locking must be implemented for musb->session.
1821 */
1822static void musb_pm_runtime_check_session(struct musb *musb)
1823{
1824 u8 devctl, s;
1825 int error;
1826
1827 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1828
1829 /* Handle session status quirks first */
1830 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1831 MUSB_DEVCTL_HR;
1832 switch (devctl & ~s) {
1833 case MUSB_QUIRK_B_INVALID_VBUS_91:
1834 if (musb->quirk_retries && !musb->flush_irq_work) {
1835 musb_dbg(musb,
1836 "Poll devctl on invalid vbus, assume no session");
1837 schedule_delayed_work(&musb->irq_work,
1838 msecs_to_jiffies(1000));
1839 musb->quirk_retries--;
1840 return;
1841 }
1842 /* fall through */
1843 case MUSB_QUIRK_A_DISCONNECT_19:
1844 if (musb->quirk_retries && !musb->flush_irq_work) {
1845 musb_dbg(musb,
1846 "Poll devctl on possible host mode disconnect");
1847 schedule_delayed_work(&musb->irq_work,
1848 msecs_to_jiffies(1000));
1849 musb->quirk_retries--;
1850 return;
1851 }
1852 if (!musb->session)
1853 break;
1854 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1855 pm_runtime_mark_last_busy(musb->controller);
1856 pm_runtime_put_autosuspend(musb->controller);
1857 musb->session = false;
1858 return;
1859 default:
1860 break;
1861 }
1862
1863 /* No need to do anything if session has not changed */
1864 s = devctl & MUSB_DEVCTL_SESSION;
1865 if (s == musb->session)
1866 return;
1867
1868 /* Block PM or allow PM? */
1869 if (s) {
1870 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1871 error = pm_runtime_get_sync(musb->controller);
1872 if (error < 0)
1873 dev_err(musb->controller, "Could not enable: %i\n",
1874 error);
1875 musb->quirk_retries = 3;
1876 } else {
1877 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
1878 pm_runtime_mark_last_busy(musb->controller);
1879 pm_runtime_put_autosuspend(musb->controller);
1880 }
1881
1882 musb->session = s;
1883}
1884
1885/* Only used to provide driver mode change events */
1886static void musb_irq_work(struct work_struct *data)
1887{
1888 struct musb *musb = container_of(data, struct musb, irq_work.work);
1889 int error;
1890
1891 error = pm_runtime_get_sync(musb->controller);
1892 if (error < 0) {
1893 dev_err(musb->controller, "Could not enable: %i\n", error);
1894
1895 return;
1896 }
1897
1898 musb_pm_runtime_check_session(musb);
1899
1900 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1901 musb->xceiv_old_state = musb->xceiv->otg->state;
1902 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1903 }
1904
1905 pm_runtime_mark_last_busy(musb->controller);
1906 pm_runtime_put_autosuspend(musb->controller);
1907}
1908
1909static void musb_recover_from_babble(struct musb *musb)
1910{
1911 int ret;
1912 u8 devctl;
1913
1914 musb_disable_interrupts(musb);
1915
1916 /*
1917 * wait at least 320 cycles of 60MHz clock. That's 5.3us, we will give
1918 * it some slack and wait for 10us.
1919 */
1920 udelay(10);
1921
1922 ret = musb_platform_recover(musb);
1923 if (ret) {
1924 musb_enable_interrupts(musb);
1925 return;
1926 }
1927
1928 /* drop session bit */
1929 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1930 devctl &= ~MUSB_DEVCTL_SESSION;
1931 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1932
1933 /* tell usbcore about it */
1934 musb_root_disconnect(musb);
1935
1936 /*
1937 * When a babble condition occurs, the musb controller
1938 * removes the session bit and the endpoint config is lost.
1939 */
1940 if (musb->dyn_fifo)
1941 ret = ep_config_from_table(musb);
1942 else
1943 ret = ep_config_from_hw(musb);
1944
1945 /* restart session */
1946 if (ret == 0)
1947 musb_start(musb);
1948}
1949
1950/* --------------------------------------------------------------------------
1951 * Init support
1952 */
1953
1954static struct musb *allocate_instance(struct device *dev,
1955 const struct musb_hdrc_config *config, void __iomem *mbase)
1956{
1957 struct musb *musb;
1958 struct musb_hw_ep *ep;
1959 int epnum;
1960 int ret;
1961
1962 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1963 if (!musb)
1964 return NULL;
1965
1966 INIT_LIST_HEAD(&musb->control);
1967 INIT_LIST_HEAD(&musb->in_bulk);
1968 INIT_LIST_HEAD(&musb->out_bulk);
1969 INIT_LIST_HEAD(&musb->pending_list);
1970
1971 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
1972 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
1973 musb->mregs = mbase;
1974 musb->ctrl_base = mbase;
1975 musb->nIrq = -ENODEV;
1976 musb->config = config;
1977 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
1978 for (epnum = 0, ep = musb->endpoints;
1979 epnum < musb->config->num_eps;
1980 epnum++, ep++) {
1981 ep->musb = musb;
1982 ep->epnum = epnum;
1983 }
1984
1985 musb->controller = dev;
1986
1987 ret = musb_host_alloc(musb);
1988 if (ret < 0)
1989 goto err_free;
1990
1991 dev_set_drvdata(dev, musb);
1992
1993 return musb;
1994
1995err_free:
1996 return NULL;
1997}
1998
1999static void musb_free(struct musb *musb)
2000{
2001 /* this has multiple entry modes. it handles fault cleanup after
2002 * probe(), where things may be partially set up, as well as rmmod
2003 * cleanup after everything's been de-activated.
2004 */
2005
2006#ifdef CONFIG_SYSFS
2007 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
2008#endif
2009
2010 if (musb->nIrq >= 0) {
2011 if (musb->irq_wake)
2012 disable_irq_wake(musb->nIrq);
2013 free_irq(musb->nIrq, musb);
2014 }
2015
2016 musb_host_free(musb);
2017}
2018
2019struct musb_pending_work {
2020 int (*callback)(struct musb *musb, void *data);
2021 void *data;
2022 struct list_head node;
2023};
2024
2025#ifdef CONFIG_PM
2026/*
2027 * Called from musb_runtime_resume(), musb_resume(), and
2028 * musb_queue_resume_work(). Callers must take musb->lock.
2029 */
2030static int musb_run_resume_work(struct musb *musb)
2031{
2032 struct musb_pending_work *w, *_w;
2033 unsigned long flags;
2034 int error = 0;
2035
2036 spin_lock_irqsave(&musb->list_lock, flags);
2037 list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2038 if (w->callback) {
2039 error = w->callback(musb, w->data);
2040 if (error < 0) {
2041 dev_err(musb->controller,
2042 "resume callback %p failed: %i\n",
2043 w->callback, error);
2044 }
2045 }
2046 list_del(&w->node);
2047 devm_kfree(musb->controller, w);
2048 }
2049 spin_unlock_irqrestore(&musb->list_lock, flags);
2050
2051 return error;
2052}
2053#endif
2054
2055/*
2056 * Called to run work if device is active or else queue the work to happen
2057 * on resume. Caller must take musb->lock and must hold an RPM reference.
2058 *
2059 * Note that we cowardly refuse queuing work after musb PM runtime
2060 * resume is done calling musb_run_resume_work() and return -EINPROGRESS
2061 * instead.
2062 */
2063int musb_queue_resume_work(struct musb *musb,
2064 int (*callback)(struct musb *musb, void *data),
2065 void *data)
2066{
2067 struct musb_pending_work *w;
2068 unsigned long flags;
2069 int error;
2070
2071 if (WARN_ON(!callback))
2072 return -EINVAL;
2073
2074 if (pm_runtime_active(musb->controller))
2075 return callback(musb, data);
2076
2077 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2078 if (!w)
2079 return -ENOMEM;
2080
2081 w->callback = callback;
2082 w->data = data;
2083 spin_lock_irqsave(&musb->list_lock, flags);
2084 if (musb->is_runtime_suspended) {
2085 list_add_tail(&w->node, &musb->pending_list);
2086 error = 0;
2087 } else {
2088 dev_err(musb->controller, "could not add resume work %p\n",
2089 callback);
2090 devm_kfree(musb->controller, w);
2091 error = -EINPROGRESS;
2092 }
2093 spin_unlock_irqrestore(&musb->list_lock, flags);
2094
2095 return error;
2096}
2097EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2098
2099static void musb_deassert_reset(struct work_struct *work)
2100{
2101 struct musb *musb;
2102 unsigned long flags;
2103
2104 musb = container_of(work, struct musb, deassert_reset_work.work);
2105
2106 spin_lock_irqsave(&musb->lock, flags);
2107
2108 if (musb->port1_status & USB_PORT_STAT_RESET)
2109 musb_port_reset(musb, false);
2110
2111 spin_unlock_irqrestore(&musb->lock, flags);
2112}
2113
2114/*
2115 * Perform generic per-controller initialization.
2116 *
2117 * @dev: the controller (already clocked, etc)
2118 * @nIrq: IRQ number
2119 * @ctrl: virtual address of controller registers,
2120 * not yet corrected for platform-specific offsets
2121 */
2122static int
2123musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2124{
2125 int status;
2126 struct musb *musb;
2127 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
2128
2129 /* The driver might handle more features than the board; OK.
2130 * Fail when the board needs a feature that's not enabled.
2131 */
2132 if (!plat) {
2133 dev_err(dev, "no platform_data?\n");
2134 status = -ENODEV;
2135 goto fail0;
2136 }
2137
2138 /* allocate */
2139 musb = allocate_instance(dev, plat->config, ctrl);
2140 if (!musb) {
2141 status = -ENOMEM;
2142 goto fail0;
2143 }
2144
2145 spin_lock_init(&musb->lock);
2146 spin_lock_init(&musb->list_lock);
2147 musb->board_set_power = plat->set_power;
2148 musb->min_power = plat->min_power;
2149 musb->ops = plat->platform_ops;
2150 musb->port_mode = plat->mode;
2151
2152 /*
2153 * Initialize the default IO functions. At least omap2430 needs
2154 * these early. We initialize the platform specific IO functions
2155 * later on.
2156 */
2157 musb_readb = musb_default_readb;
2158 musb_writeb = musb_default_writeb;
2159 musb_readw = musb_default_readw;
2160 musb_writew = musb_default_writew;
2161 musb_readl = musb_default_readl;
2162 musb_writel = musb_default_writel;
2163
2164 /* The musb_platform_init() call:
2165 * - adjusts musb->mregs
2166 * - sets the musb->isr
2167 * - may initialize an integrated transceiver
2168 * - initializes musb->xceiv, usually by otg_get_phy()
2169 * - stops powering VBUS
2170 *
2171 * There are various transceiver configurations.
2172 * DaVinci, TUSB60x0, and others integrate them. OMAP3 uses
2173 * external/discrete ones in various flavors (twl4030 family,
2174 * isp1504, non-OTG, etc) mostly hooking up through ULPI.
2175 */
2176 status = musb_platform_init(musb);
2177 if (status < 0)
2178 goto fail1;
2179
2180 if (!musb->isr) {
2181 status = -ENODEV;
2182 goto fail2;
2183 }
2184
2185 if (musb->ops->quirks)
2186 musb->io.quirks = musb->ops->quirks;
2187
2188 /* Most devices use indexed offset or flat offset */
2189 if (musb->io.quirks & MUSB_INDEXED_EP) {
2190 musb->io.ep_offset = musb_indexed_ep_offset;
2191 musb->io.ep_select = musb_indexed_ep_select;
2192 } else {
2193 musb->io.ep_offset = musb_flat_ep_offset;
2194 musb->io.ep_select = musb_flat_ep_select;
2195 }
2196
2197 if (musb->io.quirks & MUSB_G_NO_SKB_RESERVE)
2198 musb->g.quirk_avoids_skb_reserve = 1;
2199
2200 /* At least tusb6010 has its own offsets */
2201 if (musb->ops->ep_offset)
2202 musb->io.ep_offset = musb->ops->ep_offset;
2203 if (musb->ops->ep_select)
2204 musb->io.ep_select = musb->ops->ep_select;
2205
2206 if (musb->ops->fifo_mode)
2207 fifo_mode = musb->ops->fifo_mode;
2208 else
2209 fifo_mode = 4;
2210
2211 if (musb->ops->fifo_offset)
2212 musb->io.fifo_offset = musb->ops->fifo_offset;
2213 else
2214 musb->io.fifo_offset = musb_default_fifo_offset;
2215
2216 if (musb->ops->busctl_offset)
2217 musb->io.busctl_offset = musb->ops->busctl_offset;
2218 else
2219 musb->io.busctl_offset = musb_default_busctl_offset;
2220
2221 if (musb->ops->readb)
2222 musb_readb = musb->ops->readb;
2223 if (musb->ops->writeb)
2224 musb_writeb = musb->ops->writeb;
2225 if (musb->ops->readw)
2226 musb_readw = musb->ops->readw;
2227 if (musb->ops->writew)
2228 musb_writew = musb->ops->writew;
2229 if (musb->ops->readl)
2230 musb_readl = musb->ops->readl;
2231 if (musb->ops->writel)
2232 musb_writel = musb->ops->writel;
2233
2234#ifndef CONFIG_MUSB_PIO_ONLY
2235 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2236 dev_err(dev, "DMA controller not set\n");
2237 status = -ENODEV;
2238 goto fail2;
2239 }
2240 musb_dma_controller_create = musb->ops->dma_init;
2241 musb_dma_controller_destroy = musb->ops->dma_exit;
2242#endif
2243
2244 if (musb->ops->read_fifo)
2245 musb->io.read_fifo = musb->ops->read_fifo;
2246 else
2247 musb->io.read_fifo = musb_default_read_fifo;
2248
2249 if (musb->ops->write_fifo)
2250 musb->io.write_fifo = musb->ops->write_fifo;
2251 else
2252 musb->io.write_fifo = musb_default_write_fifo;
2253
2254 if (!musb->xceiv->io_ops) {
2255 musb->xceiv->io_dev = musb->controller;
2256 musb->xceiv->io_priv = musb->mregs;
2257 musb->xceiv->io_ops = &musb_ulpi_access;
2258 }
2259
2260 if (musb->ops->phy_callback)
2261 musb_phy_callback = musb->ops->phy_callback;
2262
2263 /*
2264 * We need musb_read/write functions initialized for PM.
2265 * Note that at least 2430 glue needs autosuspend delay
2266 * somewhere above 300 ms for the hardware to idle properly
2267 * after disconnecting the cable in host mode. Let's use
2268 * 500 ms for some margin.
2269 */
2270 pm_runtime_use_autosuspend(musb->controller);
2271 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2272 pm_runtime_enable(musb->controller);
2273 pm_runtime_get_sync(musb->controller);
2274
2275 status = usb_phy_init(musb->xceiv);
2276 if (status < 0)
2277 goto err_usb_phy_init;
2278
2279 if (use_dma && dev->dma_mask) {
2280 musb->dma_controller =
2281 musb_dma_controller_create(musb, musb->mregs);
2282 if (IS_ERR(musb->dma_controller)) {
2283 status = PTR_ERR(musb->dma_controller);
2284 goto fail2_5;
2285 }
2286 }
2287
2288 /* be sure interrupts are disabled before connecting ISR */
2289 musb_platform_disable(musb);
2290 musb_disable_interrupts(musb);
2291 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2292
2293 /* Init IRQ workqueue before request_irq */
2294 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
2295 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2296 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2297
2298 /* setup musb parts of the core (especially endpoints) */
2299 status = musb_core_init(plat->config->multipoint
2300 ? MUSB_CONTROLLER_MHDRC
2301 : MUSB_CONTROLLER_HDRC, musb);
2302 if (status < 0)
2303 goto fail3;
2304
2305 timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
2306
2307 /* attach to the IRQ */
2308 if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
2309 dev_err(dev, "request_irq %d failed!\n", nIrq);
2310 status = -ENODEV;
2311 goto fail3;
2312 }
2313 musb->nIrq = nIrq;
2314 /* FIXME this handles wakeup irqs wrong */
2315 if (enable_irq_wake(nIrq) == 0) {
2316 musb->irq_wake = 1;
2317 device_init_wakeup(dev, 1);
2318 } else {
2319 musb->irq_wake = 0;
2320 }
2321
2322 /* program PHY to use external vBus if required */
2323 if (plat->extvbus) {
2324 u8 busctl = musb_read_ulpi_buscontrol(musb->mregs);
2325 busctl |= MUSB_ULPI_USE_EXTVBUS;
2326 musb_write_ulpi_buscontrol(musb->mregs, busctl);
2327 }
2328
2329 if (musb->xceiv->otg->default_a) {
2330 MUSB_HST_MODE(musb);
2331 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
2332 } else {
2333 MUSB_DEV_MODE(musb);
2334 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2335 }
2336
2337 switch (musb->port_mode) {
2338 case MUSB_PORT_MODE_HOST:
2339 status = musb_host_setup(musb, plat->power);
2340 if (status < 0)
2341 goto fail3;
2342 status = musb_platform_set_mode(musb, MUSB_HOST);
2343 break;
2344 case MUSB_PORT_MODE_GADGET:
2345 status = musb_gadget_setup(musb);
2346 if (status < 0)
2347 goto fail3;
2348 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2349 break;
2350 case MUSB_PORT_MODE_DUAL_ROLE:
2351 status = musb_host_setup(musb, plat->power);
2352 if (status < 0)
2353 goto fail3;
2354 status = musb_gadget_setup(musb);
2355 if (status) {
2356 musb_host_cleanup(musb);
2357 goto fail3;
2358 }
2359 status = musb_platform_set_mode(musb, MUSB_OTG);
2360 break;
2361 default:
2362 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2363 break;
2364 }
2365
2366 if (status < 0)
2367 goto fail3;
2368
2369 status = musb_init_debugfs(musb);
2370 if (status < 0)
2371 goto fail4;
2372
2373 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2374 if (status)
2375 goto fail5;
2376
2377 musb->is_initialized = 1;
2378 pm_runtime_mark_last_busy(musb->controller);
2379 pm_runtime_put_autosuspend(musb->controller);
2380
2381 return 0;
2382
2383fail5:
2384 musb_exit_debugfs(musb);
2385
2386fail4:
2387 musb_gadget_cleanup(musb);
2388 musb_host_cleanup(musb);
2389
2390fail3:
2391 cancel_delayed_work_sync(&musb->irq_work);
2392 cancel_delayed_work_sync(&musb->finish_resume_work);
2393 cancel_delayed_work_sync(&musb->deassert_reset_work);
2394 if (musb->dma_controller)
2395 musb_dma_controller_destroy(musb->dma_controller);
2396
2397fail2_5:
2398 usb_phy_shutdown(musb->xceiv);
2399
2400err_usb_phy_init:
2401 pm_runtime_dont_use_autosuspend(musb->controller);
2402 pm_runtime_put_sync(musb->controller);
2403 pm_runtime_disable(musb->controller);
2404
2405fail2:
2406 if (musb->irq_wake)
2407 device_init_wakeup(dev, 0);
2408 musb_platform_exit(musb);
2409
2410fail1:
2411 if (status != -EPROBE_DEFER)
2412 dev_err(musb->controller,
2413 "%s failed with status %d\n", __func__, status);
2414
2415 musb_free(musb);
2416
2417fail0:
2418
2419 return status;
2420
2421}
2422
2423/*-------------------------------------------------------------------------*/
2424
2425/* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2426 * bridge to a platform device; this driver then suffices.
2427 */
2428static int musb_probe(struct platform_device *pdev)
2429{
2430 struct device *dev = &pdev->dev;
2431 int irq = platform_get_irq_byname(pdev, "mc");
2432 struct resource *iomem;
2433 void __iomem *base;
2434
2435 if (irq <= 0)
2436 return -ENODEV;
2437
2438 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2439 base = devm_ioremap_resource(dev, iomem);
2440 if (IS_ERR(base))
2441 return PTR_ERR(base);
2442
2443 return musb_init_controller(dev, irq, base);
2444}
2445
2446static int musb_remove(struct platform_device *pdev)
2447{
2448 struct device *dev = &pdev->dev;
2449 struct musb *musb = dev_to_musb(dev);
2450 unsigned long flags;
2451
2452 /* this gets called on rmmod.
2453 * - Host mode: host may still be active
2454 * - Peripheral mode: peripheral is deactivated (or never-activated)
2455 * - OTG mode: both roles are deactivated (or never-activated)
2456 */
2457 musb_exit_debugfs(musb);
2458
2459 cancel_delayed_work_sync(&musb->irq_work);
2460 cancel_delayed_work_sync(&musb->finish_resume_work);
2461 cancel_delayed_work_sync(&musb->deassert_reset_work);
2462 pm_runtime_get_sync(musb->controller);
2463 musb_host_cleanup(musb);
2464 musb_gadget_cleanup(musb);
2465
2466 musb_platform_disable(musb);
2467 spin_lock_irqsave(&musb->lock, flags);
2468 musb_disable_interrupts(musb);
2469 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2470 spin_unlock_irqrestore(&musb->lock, flags);
2471 musb_platform_exit(musb);
2472
2473 pm_runtime_dont_use_autosuspend(musb->controller);
2474 pm_runtime_put_sync(musb->controller);
2475 pm_runtime_disable(musb->controller);
2476 musb_phy_callback = NULL;
2477 if (musb->dma_controller)
2478 musb_dma_controller_destroy(musb->dma_controller);
2479 usb_phy_shutdown(musb->xceiv);
2480 musb_free(musb);
2481 device_init_wakeup(dev, 0);
2482 return 0;
2483}
2484
2485#ifdef CONFIG_PM
2486
2487static void musb_save_context(struct musb *musb)
2488{
2489 int i;
2490 void __iomem *musb_base = musb->mregs;
2491 void __iomem *epio;
2492
2493 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2494 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2495 musb->context.busctl = musb_read_ulpi_buscontrol(musb->mregs);
2496 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2497 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2498 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2499 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2500
2501 for (i = 0; i < musb->config->num_eps; ++i) {
2502 struct musb_hw_ep *hw_ep;
2503
2504 hw_ep = &musb->endpoints[i];
2505 if (!hw_ep)
2506 continue;
2507
2508 epio = hw_ep->regs;
2509 if (!epio)
2510 continue;
2511
2512 musb_writeb(musb_base, MUSB_INDEX, i);
2513 musb->context.index_regs[i].txmaxp =
2514 musb_readw(epio, MUSB_TXMAXP);
2515 musb->context.index_regs[i].txcsr =
2516 musb_readw(epio, MUSB_TXCSR);
2517 musb->context.index_regs[i].rxmaxp =
2518 musb_readw(epio, MUSB_RXMAXP);
2519 musb->context.index_regs[i].rxcsr =
2520 musb_readw(epio, MUSB_RXCSR);
2521
2522 if (musb->dyn_fifo) {
2523 musb->context.index_regs[i].txfifoadd =
2524 musb_read_txfifoadd(musb_base);
2525 musb->context.index_regs[i].rxfifoadd =
2526 musb_read_rxfifoadd(musb_base);
2527 musb->context.index_regs[i].txfifosz =
2528 musb_read_txfifosz(musb_base);
2529 musb->context.index_regs[i].rxfifosz =
2530 musb_read_rxfifosz(musb_base);
2531 }
2532
2533 musb->context.index_regs[i].txtype =
2534 musb_readb(epio, MUSB_TXTYPE);
2535 musb->context.index_regs[i].txinterval =
2536 musb_readb(epio, MUSB_TXINTERVAL);
2537 musb->context.index_regs[i].rxtype =
2538 musb_readb(epio, MUSB_RXTYPE);
2539 musb->context.index_regs[i].rxinterval =
2540 musb_readb(epio, MUSB_RXINTERVAL);
2541
2542 musb->context.index_regs[i].txfunaddr =
2543 musb_read_txfunaddr(musb, i);
2544 musb->context.index_regs[i].txhubaddr =
2545 musb_read_txhubaddr(musb, i);
2546 musb->context.index_regs[i].txhubport =
2547 musb_read_txhubport(musb, i);
2548
2549 musb->context.index_regs[i].rxfunaddr =
2550 musb_read_rxfunaddr(musb, i);
2551 musb->context.index_regs[i].rxhubaddr =
2552 musb_read_rxhubaddr(musb, i);
2553 musb->context.index_regs[i].rxhubport =
2554 musb_read_rxhubport(musb, i);
2555 }
2556}
2557
2558static void musb_restore_context(struct musb *musb)
2559{
2560 int i;
2561 void __iomem *musb_base = musb->mregs;
2562 void __iomem *epio;
2563 u8 power;
2564
2565 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2566 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2567 musb_write_ulpi_buscontrol(musb->mregs, musb->context.busctl);
2568
2569 /* Don't affect SUSPENDM/RESUME bits in POWER reg */
2570 power = musb_readb(musb_base, MUSB_POWER);
2571 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2572 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2573 power |= musb->context.power;
2574 musb_writeb(musb_base, MUSB_POWER, power);
2575
2576 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2577 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2578 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2579 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2580 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2581
2582 for (i = 0; i < musb->config->num_eps; ++i) {
2583 struct musb_hw_ep *hw_ep;
2584
2585 hw_ep = &musb->endpoints[i];
2586 if (!hw_ep)
2587 continue;
2588
2589 epio = hw_ep->regs;
2590 if (!epio)
2591 continue;
2592
2593 musb_writeb(musb_base, MUSB_INDEX, i);
2594 musb_writew(epio, MUSB_TXMAXP,
2595 musb->context.index_regs[i].txmaxp);
2596 musb_writew(epio, MUSB_TXCSR,
2597 musb->context.index_regs[i].txcsr);
2598 musb_writew(epio, MUSB_RXMAXP,
2599 musb->context.index_regs[i].rxmaxp);
2600 musb_writew(epio, MUSB_RXCSR,
2601 musb->context.index_regs[i].rxcsr);
2602
2603 if (musb->dyn_fifo) {
2604 musb_write_txfifosz(musb_base,
2605 musb->context.index_regs[i].txfifosz);
2606 musb_write_rxfifosz(musb_base,
2607 musb->context.index_regs[i].rxfifosz);
2608 musb_write_txfifoadd(musb_base,
2609 musb->context.index_regs[i].txfifoadd);
2610 musb_write_rxfifoadd(musb_base,
2611 musb->context.index_regs[i].rxfifoadd);
2612 }
2613
2614 musb_writeb(epio, MUSB_TXTYPE,
2615 musb->context.index_regs[i].txtype);
2616 musb_writeb(epio, MUSB_TXINTERVAL,
2617 musb->context.index_regs[i].txinterval);
2618 musb_writeb(epio, MUSB_RXTYPE,
2619 musb->context.index_regs[i].rxtype);
2620 musb_writeb(epio, MUSB_RXINTERVAL,
2621
2622 musb->context.index_regs[i].rxinterval);
2623 musb_write_txfunaddr(musb, i,
2624 musb->context.index_regs[i].txfunaddr);
2625 musb_write_txhubaddr(musb, i,
2626 musb->context.index_regs[i].txhubaddr);
2627 musb_write_txhubport(musb, i,
2628 musb->context.index_regs[i].txhubport);
2629
2630 musb_write_rxfunaddr(musb, i,
2631 musb->context.index_regs[i].rxfunaddr);
2632 musb_write_rxhubaddr(musb, i,
2633 musb->context.index_regs[i].rxhubaddr);
2634 musb_write_rxhubport(musb, i,
2635 musb->context.index_regs[i].rxhubport);
2636 }
2637 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2638}
2639
2640static int musb_suspend(struct device *dev)
2641{
2642 struct musb *musb = dev_to_musb(dev);
2643 unsigned long flags;
2644 int ret;
2645
2646 ret = pm_runtime_get_sync(dev);
2647 if (ret < 0) {
2648 pm_runtime_put_noidle(dev);
2649 return ret;
2650 }
2651
2652 musb_platform_disable(musb);
2653 musb_disable_interrupts(musb);
2654
2655 musb->flush_irq_work = true;
2656 while (flush_delayed_work(&musb->irq_work))
2657 ;
2658 musb->flush_irq_work = false;
2659
2660 if (!(musb->io.quirks & MUSB_PRESERVE_SESSION))
2661 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2662
2663 WARN_ON(!list_empty(&musb->pending_list));
2664
2665 spin_lock_irqsave(&musb->lock, flags);
2666
2667 if (is_peripheral_active(musb)) {
2668 /* FIXME force disconnect unless we know USB will wake
2669 * the system up quickly enough to respond ...
2670 */
2671 } else if (is_host_active(musb)) {
2672 /* we know all the children are suspended; sometimes
2673 * they will even be wakeup-enabled.
2674 */
2675 }
2676
2677 musb_save_context(musb);
2678
2679 spin_unlock_irqrestore(&musb->lock, flags);
2680 return 0;
2681}
2682
2683static int musb_resume(struct device *dev)
2684{
2685 struct musb *musb = dev_to_musb(dev);
2686 unsigned long flags;
2687 int error;
2688 u8 devctl;
2689 u8 mask;
2690
2691 /*
2692 * For static cmos like DaVinci, register values were preserved
2693 * unless for some reason the whole soc powered down or the USB
2694 * module got reset through the PSC (vs just being disabled).
2695 *
2696 * For the DSPS glue layer though, a full register restore has to
2697 * be done. As it shouldn't harm other platforms, we do it
2698 * unconditionally.
2699 */
2700
2701 musb_restore_context(musb);
2702
2703 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2704 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2705 if ((devctl & mask) != (musb->context.devctl & mask))
2706 musb->port1_status = 0;
2707
2708 musb_enable_interrupts(musb);
2709 musb_platform_enable(musb);
2710
2711 spin_lock_irqsave(&musb->lock, flags);
2712 error = musb_run_resume_work(musb);
2713 if (error)
2714 dev_err(musb->controller, "resume work failed with %i\n",
2715 error);
2716 spin_unlock_irqrestore(&musb->lock, flags);
2717
2718 pm_runtime_mark_last_busy(dev);
2719 pm_runtime_put_autosuspend(dev);
2720
2721 return 0;
2722}
2723
2724static int musb_runtime_suspend(struct device *dev)
2725{
2726 struct musb *musb = dev_to_musb(dev);
2727
2728 musb_save_context(musb);
2729 musb->is_runtime_suspended = 1;
2730
2731 return 0;
2732}
2733
2734static int musb_runtime_resume(struct device *dev)
2735{
2736 struct musb *musb = dev_to_musb(dev);
2737 unsigned long flags;
2738 int error;
2739
2740 /*
2741 * When pm_runtime_get_sync called for the first time in driver
2742 * init, some of the structure is still not initialized which is
2743 * used in restore function. But clock needs to be
2744 * enabled before any register access, so
2745 * pm_runtime_get_sync has to be called.
2746 * Also context restore without save does not make
2747 * any sense
2748 */
2749 if (!musb->is_initialized)
2750 return 0;
2751
2752 musb_restore_context(musb);
2753
2754 spin_lock_irqsave(&musb->lock, flags);
2755 error = musb_run_resume_work(musb);
2756 if (error)
2757 dev_err(musb->controller, "resume work failed with %i\n",
2758 error);
2759 musb->is_runtime_suspended = 0;
2760 spin_unlock_irqrestore(&musb->lock, flags);
2761
2762 return 0;
2763}
2764
2765static const struct dev_pm_ops musb_dev_pm_ops = {
2766 .suspend = musb_suspend,
2767 .resume = musb_resume,
2768 .runtime_suspend = musb_runtime_suspend,
2769 .runtime_resume = musb_runtime_resume,
2770};
2771
2772#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2773#else
2774#define MUSB_DEV_PM_OPS NULL
2775#endif
2776
2777static struct platform_driver musb_driver = {
2778 .driver = {
2779 .name = (char *)musb_driver_name,
2780 .bus = &platform_bus_type,
2781 .pm = MUSB_DEV_PM_OPS,
2782 },
2783 .probe = musb_probe,
2784 .remove = musb_remove,
2785};
2786
2787module_platform_driver(musb_driver);