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v6.8
   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  NXP (Philips) SCC+++(SCN+++) serial driver
   4 *
   5 *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
   6 *
   7 *  Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
   8 */
   9
 
 
 
 
  10#include <linux/clk.h>
  11#include <linux/delay.h>
  12#include <linux/err.h>
  13#include <linux/module.h>
  14#include <linux/mod_devicetable.h>
  15#include <linux/device.h>
  16#include <linux/console.h>
  17#include <linux/serial_core.h>
  18#include <linux/serial.h>
  19#include <linux/io.h>
  20#include <linux/tty.h>
  21#include <linux/tty_flip.h>
  22#include <linux/spinlock.h>
  23#include <linux/platform_device.h>
  24#include <linux/platform_data/serial-sccnxp.h>
  25#include <linux/regulator/consumer.h>
  26
  27#define SCCNXP_NAME			"uart-sccnxp"
  28#define SCCNXP_MAJOR			204
  29#define SCCNXP_MINOR			205
  30
  31#define SCCNXP_MR_REG			(0x00)
  32#	define MR0_BAUD_NORMAL		(0 << 0)
  33#	define MR0_BAUD_EXT1		(1 << 0)
  34#	define MR0_BAUD_EXT2		(5 << 0)
  35#	define MR0_FIFO			(1 << 3)
  36#	define MR0_TXLVL		(1 << 4)
  37#	define MR1_BITS_5		(0 << 0)
  38#	define MR1_BITS_6		(1 << 0)
  39#	define MR1_BITS_7		(2 << 0)
  40#	define MR1_BITS_8		(3 << 0)
  41#	define MR1_PAR_EVN		(0 << 2)
  42#	define MR1_PAR_ODD		(1 << 2)
  43#	define MR1_PAR_NO		(4 << 2)
  44#	define MR2_STOP1		(7 << 0)
  45#	define MR2_STOP2		(0xf << 0)
  46#define SCCNXP_SR_REG			(0x01)
 
  47#	define SR_RXRDY			(1 << 0)
  48#	define SR_FULL			(1 << 1)
  49#	define SR_TXRDY			(1 << 2)
  50#	define SR_TXEMT			(1 << 3)
  51#	define SR_OVR			(1 << 4)
  52#	define SR_PE			(1 << 5)
  53#	define SR_FE			(1 << 6)
  54#	define SR_BRK			(1 << 7)
  55#define SCCNXP_CSR_REG			(SCCNXP_SR_REG)
  56#	define CSR_TIMER_MODE		(0x0d)
  57#define SCCNXP_CR_REG			(0x02)
  58#	define CR_RX_ENABLE		(1 << 0)
  59#	define CR_RX_DISABLE		(1 << 1)
  60#	define CR_TX_ENABLE		(1 << 2)
  61#	define CR_TX_DISABLE		(1 << 3)
  62#	define CR_CMD_MRPTR1		(0x01 << 4)
  63#	define CR_CMD_RX_RESET		(0x02 << 4)
  64#	define CR_CMD_TX_RESET		(0x03 << 4)
  65#	define CR_CMD_STATUS_RESET	(0x04 << 4)
  66#	define CR_CMD_BREAK_RESET	(0x05 << 4)
  67#	define CR_CMD_START_BREAK	(0x06 << 4)
  68#	define CR_CMD_STOP_BREAK	(0x07 << 4)
  69#	define CR_CMD_MRPTR0		(0x0b << 4)
  70#define SCCNXP_RHR_REG			(0x03)
  71#define SCCNXP_THR_REG			SCCNXP_RHR_REG
  72#define SCCNXP_IPCR_REG			(0x04)
  73#define SCCNXP_ACR_REG			SCCNXP_IPCR_REG
  74#	define ACR_BAUD0		(0 << 7)
  75#	define ACR_BAUD1		(1 << 7)
  76#	define ACR_TIMER_MODE		(6 << 4)
  77#define SCCNXP_ISR_REG			(0x05)
  78#define SCCNXP_IMR_REG			SCCNXP_ISR_REG
  79#	define IMR_TXRDY		(1 << 0)
  80#	define IMR_RXRDY		(1 << 1)
  81#	define ISR_TXRDY(x)		(1 << ((x * 4) + 0))
  82#	define ISR_RXRDY(x)		(1 << ((x * 4) + 1))
  83#define SCCNXP_CTPU_REG			(0x06)
  84#define SCCNXP_CTPL_REG			(0x07)
  85#define SCCNXP_IPR_REG			(0x0d)
  86#define SCCNXP_OPCR_REG			SCCNXP_IPR_REG
  87#define SCCNXP_SOP_REG			(0x0e)
  88#define SCCNXP_START_COUNTER_REG	SCCNXP_SOP_REG
  89#define SCCNXP_ROP_REG			(0x0f)
  90
  91/* Route helpers */
  92#define MCTRL_MASK(sig)			(0xf << (sig))
  93#define MCTRL_IBIT(cfg, sig)		((((cfg) >> (sig)) & 0xf) - LINE_IP0)
  94#define MCTRL_OBIT(cfg, sig)		((((cfg) >> (sig)) & 0xf) - LINE_OP0)
  95
  96#define SCCNXP_HAVE_IO		0x00000001
  97#define SCCNXP_HAVE_MR0		0x00000002
  98
  99struct sccnxp_chip {
 100	const char		*name;
 101	unsigned int		nr;
 102	unsigned long		freq_min;
 103	unsigned long		freq_std;
 104	unsigned long		freq_max;
 105	unsigned int		flags;
 106	unsigned int		fifosize;
 107	/* Time between read/write cycles */
 108	unsigned int		trwd;
 109};
 110
 111struct sccnxp_port {
 112	struct uart_driver	uart;
 113	struct uart_port	port[SCCNXP_MAX_UARTS];
 114	bool			opened[SCCNXP_MAX_UARTS];
 115
 116	int			irq;
 117	u8			imr;
 118
 119	struct sccnxp_chip	*chip;
 120
 121#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
 122	struct console		console;
 123#endif
 124
 125	spinlock_t		lock;
 126
 127	bool			poll;
 128	struct timer_list	timer;
 129
 130	struct sccnxp_pdata	pdata;
 131
 132	struct regulator	*regulator;
 133};
 134
 135static const struct sccnxp_chip sc2681 = {
 136	.name		= "SC2681",
 137	.nr		= 2,
 138	.freq_min	= 1000000,
 139	.freq_std	= 3686400,
 140	.freq_max	= 4000000,
 141	.flags		= SCCNXP_HAVE_IO,
 142	.fifosize	= 3,
 143	.trwd		= 200,
 144};
 145
 146static const struct sccnxp_chip sc2691 = {
 147	.name		= "SC2691",
 148	.nr		= 1,
 149	.freq_min	= 1000000,
 150	.freq_std	= 3686400,
 151	.freq_max	= 4000000,
 152	.flags		= 0,
 153	.fifosize	= 3,
 154	.trwd		= 150,
 155};
 156
 157static const struct sccnxp_chip sc2692 = {
 158	.name		= "SC2692",
 159	.nr		= 2,
 160	.freq_min	= 1000000,
 161	.freq_std	= 3686400,
 162	.freq_max	= 4000000,
 163	.flags		= SCCNXP_HAVE_IO,
 164	.fifosize	= 3,
 165	.trwd		= 30,
 166};
 167
 168static const struct sccnxp_chip sc2891 = {
 169	.name		= "SC2891",
 170	.nr		= 1,
 171	.freq_min	= 100000,
 172	.freq_std	= 3686400,
 173	.freq_max	= 8000000,
 174	.flags		= SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
 175	.fifosize	= 16,
 176	.trwd		= 27,
 177};
 178
 179static const struct sccnxp_chip sc2892 = {
 180	.name		= "SC2892",
 181	.nr		= 2,
 182	.freq_min	= 100000,
 183	.freq_std	= 3686400,
 184	.freq_max	= 8000000,
 185	.flags		= SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
 186	.fifosize	= 16,
 187	.trwd		= 17,
 188};
 189
 190static const struct sccnxp_chip sc28202 = {
 191	.name		= "SC28202",
 192	.nr		= 2,
 193	.freq_min	= 1000000,
 194	.freq_std	= 14745600,
 195	.freq_max	= 50000000,
 196	.flags		= SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
 197	.fifosize	= 256,
 198	.trwd		= 10,
 199};
 200
 201static const struct sccnxp_chip sc68681 = {
 202	.name		= "SC68681",
 203	.nr		= 2,
 204	.freq_min	= 1000000,
 205	.freq_std	= 3686400,
 206	.freq_max	= 4000000,
 207	.flags		= SCCNXP_HAVE_IO,
 208	.fifosize	= 3,
 209	.trwd		= 200,
 210};
 211
 212static const struct sccnxp_chip sc68692 = {
 213	.name		= "SC68692",
 214	.nr		= 2,
 215	.freq_min	= 1000000,
 216	.freq_std	= 3686400,
 217	.freq_max	= 4000000,
 218	.flags		= SCCNXP_HAVE_IO,
 219	.fifosize	= 3,
 220	.trwd		= 200,
 221};
 222
 223static u8 sccnxp_read(struct uart_port *port, u8 reg)
 224{
 225	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 226	u8 ret;
 227
 228	ret = readb(port->membase + (reg << port->regshift));
 229
 230	ndelay(s->chip->trwd);
 231
 232	return ret;
 233}
 234
 235static void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
 236{
 237	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 238
 239	writeb(v, port->membase + (reg << port->regshift));
 240
 241	ndelay(s->chip->trwd);
 242}
 243
 244static u8 sccnxp_port_read(struct uart_port *port, u8 reg)
 245{
 246	return sccnxp_read(port, (port->line << 3) + reg);
 247}
 248
 249static void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
 250{
 251	sccnxp_write(port, (port->line << 3) + reg, v);
 252}
 253
 254static int sccnxp_update_best_err(int a, int b, int *besterr)
 255{
 256	int err = abs(a - b);
 257
 258	if (*besterr > err) {
 259		*besterr = err;
 260		return 0;
 261	}
 262
 263	return 1;
 264}
 265
 266static const struct {
 267	u8	csr;
 268	u8	acr;
 269	u8	mr0;
 270	int	baud;
 271} baud_std[] = {
 272	{ 0,	ACR_BAUD0,	MR0_BAUD_NORMAL,	50, },
 273	{ 0,	ACR_BAUD1,	MR0_BAUD_NORMAL,	75, },
 274	{ 1,	ACR_BAUD0,	MR0_BAUD_NORMAL,	110, },
 275	{ 2,	ACR_BAUD0,	MR0_BAUD_NORMAL,	134, },
 276	{ 3,	ACR_BAUD1,	MR0_BAUD_NORMAL,	150, },
 277	{ 3,	ACR_BAUD0,	MR0_BAUD_NORMAL,	200, },
 278	{ 4,	ACR_BAUD0,	MR0_BAUD_NORMAL,	300, },
 279	{ 0,	ACR_BAUD1,	MR0_BAUD_EXT1,		450, },
 280	{ 1,	ACR_BAUD0,	MR0_BAUD_EXT2,		880, },
 281	{ 3,	ACR_BAUD1,	MR0_BAUD_EXT1,		900, },
 282	{ 5,	ACR_BAUD0,	MR0_BAUD_NORMAL,	600, },
 283	{ 7,	ACR_BAUD0,	MR0_BAUD_NORMAL,	1050, },
 284	{ 2,	ACR_BAUD0,	MR0_BAUD_EXT2,		1076, },
 285	{ 6,	ACR_BAUD0,	MR0_BAUD_NORMAL,	1200, },
 286	{ 10,	ACR_BAUD1,	MR0_BAUD_NORMAL,	1800, },
 287	{ 7,	ACR_BAUD1,	MR0_BAUD_NORMAL,	2000, },
 288	{ 8,	ACR_BAUD0,	MR0_BAUD_NORMAL,	2400, },
 289	{ 5,	ACR_BAUD1,	MR0_BAUD_EXT1,		3600, },
 290	{ 9,	ACR_BAUD0,	MR0_BAUD_NORMAL,	4800, },
 291	{ 10,	ACR_BAUD0,	MR0_BAUD_NORMAL,	7200, },
 292	{ 11,	ACR_BAUD0,	MR0_BAUD_NORMAL,	9600, },
 293	{ 8,	ACR_BAUD0,	MR0_BAUD_EXT1,		14400, },
 294	{ 12,	ACR_BAUD1,	MR0_BAUD_NORMAL,	19200, },
 295	{ 9,	ACR_BAUD0,	MR0_BAUD_EXT1,		28800, },
 296	{ 12,	ACR_BAUD0,	MR0_BAUD_NORMAL,	38400, },
 297	{ 11,	ACR_BAUD0,	MR0_BAUD_EXT1,		57600, },
 298	{ 12,	ACR_BAUD1,	MR0_BAUD_EXT1,		115200, },
 299	{ 12,	ACR_BAUD0,	MR0_BAUD_EXT1,		230400, },
 300	{ 0, 0, 0, 0 }
 301};
 302
 303static int sccnxp_set_baud(struct uart_port *port, int baud)
 304{
 305	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 306	int div_std, tmp_baud, bestbaud = INT_MAX, besterr = INT_MAX;
 307	struct sccnxp_chip *chip = s->chip;
 308	u8 i, acr = 0, csr = 0, mr0 = 0;
 309
 310	/* Find divisor to load to the timer preset registers */
 311	div_std = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * baud);
 312	if ((div_std >= 2) && (div_std <= 0xffff)) {
 313		bestbaud = DIV_ROUND_CLOSEST(port->uartclk, 2 * 16 * div_std);
 314		sccnxp_update_best_err(baud, bestbaud, &besterr);
 315		csr = CSR_TIMER_MODE;
 316		sccnxp_port_write(port, SCCNXP_CTPU_REG, div_std >> 8);
 317		sccnxp_port_write(port, SCCNXP_CTPL_REG, div_std);
 318		/* Issue start timer/counter command */
 319		sccnxp_port_read(port, SCCNXP_START_COUNTER_REG);
 320	}
 321
 322	/* Find best baud from table */
 323	for (i = 0; baud_std[i].baud && besterr; i++) {
 324		if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
 325			continue;
 326		div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
 327		tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
 328		if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
 329			acr = baud_std[i].acr;
 330			csr = baud_std[i].csr;
 331			mr0 = baud_std[i].mr0;
 332			bestbaud = tmp_baud;
 333		}
 334	}
 335
 336	if (chip->flags & SCCNXP_HAVE_MR0) {
 337		/* Enable FIFO, set half level for TX */
 338		mr0 |= MR0_FIFO | MR0_TXLVL;
 339		/* Update MR0 */
 340		sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
 341		sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
 342	}
 343
 344	sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
 345	sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
 346
 347	if (baud != bestbaud)
 348		dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
 349			baud, bestbaud);
 350
 351	return bestbaud;
 352}
 353
 354static void sccnxp_enable_irq(struct uart_port *port, int mask)
 355{
 356	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 357
 358	s->imr |= mask << (port->line * 4);
 359	sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
 360}
 361
 362static void sccnxp_disable_irq(struct uart_port *port, int mask)
 363{
 364	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 365
 366	s->imr &= ~(mask << (port->line * 4));
 367	sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
 368}
 369
 370static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
 371{
 372	u8 bitmask;
 373	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 374
 375	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
 376		bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
 377		if (state)
 378			sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
 379		else
 380			sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
 381	}
 382}
 383
 384static void sccnxp_handle_rx(struct uart_port *port)
 385{
 386	u8 sr, ch, flag;
 
 387
 388	for (;;) {
 389		sr = sccnxp_port_read(port, SCCNXP_SR_REG);
 390		if (!(sr & SR_RXRDY))
 391			break;
 392		sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
 393
 394		ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
 395
 396		port->icount.rx++;
 397		flag = TTY_NORMAL;
 398
 399		if (unlikely(sr)) {
 400			if (sr & SR_BRK) {
 401				port->icount.brk++;
 402				sccnxp_port_write(port, SCCNXP_CR_REG,
 403						  CR_CMD_BREAK_RESET);
 404				if (uart_handle_break(port))
 405					continue;
 406			} else if (sr & SR_PE)
 407				port->icount.parity++;
 408			else if (sr & SR_FE)
 409				port->icount.frame++;
 410			else if (sr & SR_OVR) {
 411				port->icount.overrun++;
 412				sccnxp_port_write(port, SCCNXP_CR_REG,
 413						  CR_CMD_STATUS_RESET);
 414			}
 415
 416			sr &= port->read_status_mask;
 417			if (sr & SR_BRK)
 418				flag = TTY_BREAK;
 419			else if (sr & SR_PE)
 420				flag = TTY_PARITY;
 421			else if (sr & SR_FE)
 422				flag = TTY_FRAME;
 423			else if (sr & SR_OVR)
 424				flag = TTY_OVERRUN;
 425		}
 426
 427		if (uart_handle_sysrq_char(port, ch))
 428			continue;
 429
 430		if (sr & port->ignore_status_mask)
 431			continue;
 432
 433		uart_insert_char(port, sr, SR_OVR, ch, flag);
 434	}
 435
 436	tty_flip_buffer_push(&port->state->port);
 437}
 438
 439static void sccnxp_handle_tx(struct uart_port *port)
 440{
 441	u8 sr;
 442	struct circ_buf *xmit = &port->state->xmit;
 443	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 444
 445	if (unlikely(port->x_char)) {
 446		sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
 447		port->icount.tx++;
 448		port->x_char = 0;
 449		return;
 450	}
 451
 452	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 453		/* Disable TX if FIFO is empty */
 454		if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
 455			sccnxp_disable_irq(port, IMR_TXRDY);
 456
 457			/* Set direction to input */
 458			if (s->chip->flags & SCCNXP_HAVE_IO)
 459				sccnxp_set_bit(port, DIR_OP, 0);
 460		}
 461		return;
 462	}
 463
 464	while (!uart_circ_empty(xmit)) {
 465		sr = sccnxp_port_read(port, SCCNXP_SR_REG);
 466		if (!(sr & SR_TXRDY))
 467			break;
 468
 469		sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
 470		uart_xmit_advance(port, 1);
 
 471	}
 472
 473	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 474		uart_write_wakeup(port);
 475}
 476
 477static void sccnxp_handle_events(struct sccnxp_port *s)
 478{
 479	int i;
 480	u8 isr;
 481
 482	do {
 483		isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
 484		isr &= s->imr;
 485		if (!isr)
 486			break;
 487
 488		for (i = 0; i < s->uart.nr; i++) {
 489			if (s->opened[i] && (isr & ISR_RXRDY(i)))
 490				sccnxp_handle_rx(&s->port[i]);
 491			if (s->opened[i] && (isr & ISR_TXRDY(i)))
 492				sccnxp_handle_tx(&s->port[i]);
 493		}
 494	} while (1);
 495}
 496
 497static void sccnxp_timer(struct timer_list *t)
 498{
 499	struct sccnxp_port *s = from_timer(s, t, timer);
 500	unsigned long flags;
 501
 502	spin_lock_irqsave(&s->lock, flags);
 503	sccnxp_handle_events(s);
 504	spin_unlock_irqrestore(&s->lock, flags);
 505
 506	mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
 507}
 508
 509static irqreturn_t sccnxp_ist(int irq, void *dev_id)
 510{
 511	struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
 512	unsigned long flags;
 513
 514	spin_lock_irqsave(&s->lock, flags);
 515	sccnxp_handle_events(s);
 516	spin_unlock_irqrestore(&s->lock, flags);
 517
 518	return IRQ_HANDLED;
 519}
 520
 521static void sccnxp_start_tx(struct uart_port *port)
 522{
 523	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 524	unsigned long flags;
 525
 526	spin_lock_irqsave(&s->lock, flags);
 527
 528	/* Set direction to output */
 529	if (s->chip->flags & SCCNXP_HAVE_IO)
 530		sccnxp_set_bit(port, DIR_OP, 1);
 531
 532	sccnxp_enable_irq(port, IMR_TXRDY);
 533
 534	spin_unlock_irqrestore(&s->lock, flags);
 535}
 536
 537static void sccnxp_stop_tx(struct uart_port *port)
 538{
 539	/* Do nothing */
 540}
 541
 542static void sccnxp_stop_rx(struct uart_port *port)
 543{
 544	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 545	unsigned long flags;
 546
 547	spin_lock_irqsave(&s->lock, flags);
 548	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
 549	spin_unlock_irqrestore(&s->lock, flags);
 550}
 551
 552static unsigned int sccnxp_tx_empty(struct uart_port *port)
 553{
 554	u8 val;
 555	unsigned long flags;
 556	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 557
 558	spin_lock_irqsave(&s->lock, flags);
 559	val = sccnxp_port_read(port, SCCNXP_SR_REG);
 560	spin_unlock_irqrestore(&s->lock, flags);
 561
 562	return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
 563}
 564
 565static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
 566{
 567	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 568	unsigned long flags;
 569
 570	if (!(s->chip->flags & SCCNXP_HAVE_IO))
 571		return;
 572
 573	spin_lock_irqsave(&s->lock, flags);
 574
 575	sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
 576	sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
 577
 578	spin_unlock_irqrestore(&s->lock, flags);
 579}
 580
 581static unsigned int sccnxp_get_mctrl(struct uart_port *port)
 582{
 583	u8 bitmask, ipr;
 584	unsigned long flags;
 585	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 586	unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
 587
 588	if (!(s->chip->flags & SCCNXP_HAVE_IO))
 589		return mctrl;
 590
 591	spin_lock_irqsave(&s->lock, flags);
 592
 593	ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
 594
 595	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
 596		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 597					  DSR_IP);
 598		mctrl &= ~TIOCM_DSR;
 599		mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
 600	}
 601	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
 602		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 603					  CTS_IP);
 604		mctrl &= ~TIOCM_CTS;
 605		mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
 606	}
 607	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
 608		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 609					  DCD_IP);
 610		mctrl &= ~TIOCM_CAR;
 611		mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
 612	}
 613	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
 614		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 615					  RNG_IP);
 616		mctrl &= ~TIOCM_RNG;
 617		mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
 618	}
 619
 620	spin_unlock_irqrestore(&s->lock, flags);
 621
 622	return mctrl;
 623}
 624
 625static void sccnxp_break_ctl(struct uart_port *port, int break_state)
 626{
 627	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 628	unsigned long flags;
 629
 630	spin_lock_irqsave(&s->lock, flags);
 631	sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
 632			  CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
 633	spin_unlock_irqrestore(&s->lock, flags);
 634}
 635
 636static void sccnxp_set_termios(struct uart_port *port,
 637			       struct ktermios *termios,
 638			       const struct ktermios *old)
 639{
 640	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 641	unsigned long flags;
 642	u8 mr1, mr2;
 643	int baud;
 644
 645	spin_lock_irqsave(&s->lock, flags);
 646
 647	/* Mask termios capabilities we don't support */
 648	termios->c_cflag &= ~CMSPAR;
 649
 650	/* Disable RX & TX, reset break condition, status and FIFOs */
 651	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
 652					       CR_RX_DISABLE | CR_TX_DISABLE);
 653	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
 654	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
 655	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
 656
 657	/* Word size */
 658	switch (termios->c_cflag & CSIZE) {
 659	case CS5:
 660		mr1 = MR1_BITS_5;
 661		break;
 662	case CS6:
 663		mr1 = MR1_BITS_6;
 664		break;
 665	case CS7:
 666		mr1 = MR1_BITS_7;
 667		break;
 668	case CS8:
 669	default:
 670		mr1 = MR1_BITS_8;
 671		break;
 672	}
 673
 674	/* Parity */
 675	if (termios->c_cflag & PARENB) {
 676		if (termios->c_cflag & PARODD)
 677			mr1 |= MR1_PAR_ODD;
 678	} else
 679		mr1 |= MR1_PAR_NO;
 680
 681	/* Stop bits */
 682	mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
 683
 684	/* Update desired format */
 685	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
 686	sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
 687	sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
 688
 689	/* Set read status mask */
 690	port->read_status_mask = SR_OVR;
 691	if (termios->c_iflag & INPCK)
 692		port->read_status_mask |= SR_PE | SR_FE;
 693	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 694		port->read_status_mask |= SR_BRK;
 695
 696	/* Set status ignore mask */
 697	port->ignore_status_mask = 0;
 698	if (termios->c_iflag & IGNBRK)
 699		port->ignore_status_mask |= SR_BRK;
 700	if (termios->c_iflag & IGNPAR)
 701		port->ignore_status_mask |= SR_PE;
 702	if (!(termios->c_cflag & CREAD))
 703		port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
 704
 705	/* Setup baudrate */
 706	baud = uart_get_baud_rate(port, termios, old, 50,
 707				  (s->chip->flags & SCCNXP_HAVE_MR0) ?
 708				  230400 : 38400);
 709	baud = sccnxp_set_baud(port, baud);
 710
 711	/* Update timeout according to new baud rate */
 712	uart_update_timeout(port, termios->c_cflag, baud);
 713
 714	/* Report actual baudrate back to core */
 715	if (tty_termios_baud_rate(termios))
 716		tty_termios_encode_baud_rate(termios, baud, baud);
 717
 718	/* Enable RX & TX */
 719	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
 720
 721	spin_unlock_irqrestore(&s->lock, flags);
 722}
 723
 724static int sccnxp_startup(struct uart_port *port)
 725{
 726	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 727	unsigned long flags;
 728
 729	spin_lock_irqsave(&s->lock, flags);
 730
 731	if (s->chip->flags & SCCNXP_HAVE_IO) {
 732		/* Outputs are controlled manually */
 733		sccnxp_write(port, SCCNXP_OPCR_REG, 0);
 734	}
 735
 736	/* Reset break condition, status and FIFOs */
 737	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
 738	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
 739	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
 740	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
 741
 742	/* Enable RX & TX */
 743	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
 744
 745	/* Enable RX interrupt */
 746	sccnxp_enable_irq(port, IMR_RXRDY);
 747
 748	s->opened[port->line] = 1;
 749
 750	spin_unlock_irqrestore(&s->lock, flags);
 751
 752	return 0;
 753}
 754
 755static void sccnxp_shutdown(struct uart_port *port)
 756{
 757	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 758	unsigned long flags;
 759
 760	spin_lock_irqsave(&s->lock, flags);
 761
 762	s->opened[port->line] = 0;
 763
 764	/* Disable interrupts */
 765	sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
 766
 767	/* Disable TX & RX */
 768	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
 769
 770	/* Leave direction to input */
 771	if (s->chip->flags & SCCNXP_HAVE_IO)
 772		sccnxp_set_bit(port, DIR_OP, 0);
 773
 774	spin_unlock_irqrestore(&s->lock, flags);
 775}
 776
 777static const char *sccnxp_type(struct uart_port *port)
 778{
 779	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 780
 781	return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
 782}
 783
 784static void sccnxp_release_port(struct uart_port *port)
 785{
 786	/* Do nothing */
 787}
 788
 789static int sccnxp_request_port(struct uart_port *port)
 790{
 791	/* Do nothing */
 792	return 0;
 793}
 794
 795static void sccnxp_config_port(struct uart_port *port, int flags)
 796{
 797	if (flags & UART_CONFIG_TYPE)
 798		port->type = PORT_SC26XX;
 799}
 800
 801static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
 802{
 803	if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
 804		return 0;
 805	if (s->irq == port->irq)
 806		return 0;
 807
 808	return -EINVAL;
 809}
 810
 811static const struct uart_ops sccnxp_ops = {
 812	.tx_empty	= sccnxp_tx_empty,
 813	.set_mctrl	= sccnxp_set_mctrl,
 814	.get_mctrl	= sccnxp_get_mctrl,
 815	.stop_tx	= sccnxp_stop_tx,
 816	.start_tx	= sccnxp_start_tx,
 817	.stop_rx	= sccnxp_stop_rx,
 818	.break_ctl	= sccnxp_break_ctl,
 819	.startup	= sccnxp_startup,
 820	.shutdown	= sccnxp_shutdown,
 821	.set_termios	= sccnxp_set_termios,
 822	.type		= sccnxp_type,
 823	.release_port	= sccnxp_release_port,
 824	.request_port	= sccnxp_request_port,
 825	.config_port	= sccnxp_config_port,
 826	.verify_port	= sccnxp_verify_port,
 827};
 828
 829#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
 830static void sccnxp_console_putchar(struct uart_port *port, unsigned char c)
 831{
 832	int tryes = 100000;
 833
 834	while (tryes--) {
 835		if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
 836			sccnxp_port_write(port, SCCNXP_THR_REG, c);
 837			break;
 838		}
 839		barrier();
 840	}
 841}
 842
 843static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
 844{
 845	struct sccnxp_port *s = (struct sccnxp_port *)co->data;
 846	struct uart_port *port = &s->port[co->index];
 847	unsigned long flags;
 848
 849	spin_lock_irqsave(&s->lock, flags);
 850	uart_console_write(port, c, n, sccnxp_console_putchar);
 851	spin_unlock_irqrestore(&s->lock, flags);
 852}
 853
 854static int sccnxp_console_setup(struct console *co, char *options)
 855{
 856	struct sccnxp_port *s = (struct sccnxp_port *)co->data;
 857	struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
 858	int baud = 9600, bits = 8, parity = 'n', flow = 'n';
 859
 860	if (options)
 861		uart_parse_options(options, &baud, &parity, &bits, &flow);
 862
 863	return uart_set_options(port, co, baud, parity, bits, flow);
 864}
 865#endif
 866
 867static const struct platform_device_id sccnxp_id_table[] = {
 868	{ .name = "sc2681",	.driver_data = (kernel_ulong_t)&sc2681, },
 869	{ .name = "sc2691",	.driver_data = (kernel_ulong_t)&sc2691, },
 870	{ .name = "sc2692",	.driver_data = (kernel_ulong_t)&sc2692, },
 871	{ .name = "sc2891",	.driver_data = (kernel_ulong_t)&sc2891, },
 872	{ .name = "sc2892",	.driver_data = (kernel_ulong_t)&sc2892, },
 873	{ .name = "sc28202",	.driver_data = (kernel_ulong_t)&sc28202, },
 874	{ .name = "sc68681",	.driver_data = (kernel_ulong_t)&sc68681, },
 875	{ .name = "sc68692",	.driver_data = (kernel_ulong_t)&sc68692, },
 876	{ }
 877};
 878MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
 879
 880static int sccnxp_probe(struct platform_device *pdev)
 881{
 
 882	struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
 883	struct resource *res;
 884	int i, ret, uartclk;
 885	struct sccnxp_port *s;
 886	void __iomem *membase;
 887	struct clk *clk;
 888
 889	membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 890	if (IS_ERR(membase))
 891		return PTR_ERR(membase);
 892
 893	s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
 894	if (!s) {
 895		dev_err(&pdev->dev, "Error allocating port structure\n");
 896		return -ENOMEM;
 897	}
 898	platform_set_drvdata(pdev, s);
 899
 900	spin_lock_init(&s->lock);
 901
 902	s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
 903
 904	s->regulator = devm_regulator_get(&pdev->dev, "vcc");
 905	if (!IS_ERR(s->regulator)) {
 906		ret = regulator_enable(s->regulator);
 907		if (ret) {
 908			dev_err(&pdev->dev,
 909				"Failed to enable regulator: %i\n", ret);
 910			return ret;
 911		}
 912	} else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
 913		return -EPROBE_DEFER;
 914
 915	clk = devm_clk_get_enabled(&pdev->dev, NULL);
 916	if (IS_ERR(clk)) {
 917		ret = PTR_ERR(clk);
 918		if (ret == -EPROBE_DEFER)
 919			goto err_out;
 920		uartclk = 0;
 921	} else {
 
 
 
 
 
 
 
 
 
 
 922		uartclk = clk_get_rate(clk);
 923	}
 924
 925	if (!uartclk) {
 926		dev_notice(&pdev->dev, "Using default clock frequency\n");
 927		uartclk = s->chip->freq_std;
 928	}
 929
 930	/* Check input frequency */
 931	if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
 932		dev_err(&pdev->dev, "Frequency out of bounds\n");
 933		ret = -EINVAL;
 934		goto err_out;
 935	}
 936
 937	if (pdata)
 938		memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
 939
 940	if (s->pdata.poll_time_us) {
 941		dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
 942			 s->pdata.poll_time_us);
 943		s->poll = 1;
 944	}
 945
 946	if (!s->poll) {
 947		s->irq = platform_get_irq(pdev, 0);
 948		if (s->irq < 0) {
 
 949			ret = -ENXIO;
 950			goto err_out;
 951		}
 952	}
 953
 954	s->uart.owner		= THIS_MODULE;
 955	s->uart.dev_name	= "ttySC";
 956	s->uart.major		= SCCNXP_MAJOR;
 957	s->uart.minor		= SCCNXP_MINOR;
 958	s->uart.nr		= s->chip->nr;
 959#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
 960	s->uart.cons		= &s->console;
 961	s->uart.cons->device	= uart_console_device;
 962	s->uart.cons->write	= sccnxp_console_write;
 963	s->uart.cons->setup	= sccnxp_console_setup;
 964	s->uart.cons->flags	= CON_PRINTBUFFER;
 965	s->uart.cons->index	= -1;
 966	s->uart.cons->data	= s;
 967	strcpy(s->uart.cons->name, "ttySC");
 968#endif
 969	ret = uart_register_driver(&s->uart);
 970	if (ret) {
 971		dev_err(&pdev->dev, "Registering UART driver failed\n");
 972		goto err_out;
 973	}
 974
 975	for (i = 0; i < s->uart.nr; i++) {
 976		s->port[i].line		= i;
 977		s->port[i].dev		= &pdev->dev;
 978		s->port[i].irq		= s->irq;
 979		s->port[i].type		= PORT_SC26XX;
 980		s->port[i].fifosize	= s->chip->fifosize;
 981		s->port[i].flags	= UPF_SKIP_TEST | UPF_FIXED_TYPE;
 982		s->port[i].iotype	= UPIO_MEM;
 983		s->port[i].mapbase	= res->start;
 984		s->port[i].membase	= membase;
 985		s->port[i].regshift	= s->pdata.reg_shift;
 986		s->port[i].uartclk	= uartclk;
 987		s->port[i].ops		= &sccnxp_ops;
 988		s->port[i].has_sysrq = IS_ENABLED(CONFIG_SERIAL_SCCNXP_CONSOLE);
 989		uart_add_one_port(&s->uart, &s->port[i]);
 990		/* Set direction to input */
 991		if (s->chip->flags & SCCNXP_HAVE_IO)
 992			sccnxp_set_bit(&s->port[i], DIR_OP, 0);
 993	}
 994
 995	/* Disable interrupts */
 996	s->imr = 0;
 997	sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
 998
 999	if (!s->poll) {
1000		ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
1001						sccnxp_ist,
1002						IRQF_TRIGGER_FALLING |
1003						IRQF_ONESHOT,
1004						dev_name(&pdev->dev), s);
1005		if (!ret)
1006			return 0;
1007
1008		dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
1009	} else {
1010		timer_setup(&s->timer, sccnxp_timer, 0);
1011		mod_timer(&s->timer, jiffies +
1012			  usecs_to_jiffies(s->pdata.poll_time_us));
1013		return 0;
1014	}
1015
1016	uart_unregister_driver(&s->uart);
1017err_out:
1018	if (!IS_ERR(s->regulator))
1019		regulator_disable(s->regulator);
1020
1021	return ret;
1022}
1023
1024static void sccnxp_remove(struct platform_device *pdev)
1025{
1026	int i;
1027	struct sccnxp_port *s = platform_get_drvdata(pdev);
1028
1029	if (!s->poll)
1030		devm_free_irq(&pdev->dev, s->irq, s);
1031	else
1032		del_timer_sync(&s->timer);
1033
1034	for (i = 0; i < s->uart.nr; i++)
1035		uart_remove_one_port(&s->uart, &s->port[i]);
1036
1037	uart_unregister_driver(&s->uart);
1038
1039	if (!IS_ERR(s->regulator)) {
1040		int ret = regulator_disable(s->regulator);
1041		if (ret)
1042			dev_err(&pdev->dev, "Failed to disable regulator\n");
1043	}
1044}
1045
1046static struct platform_driver sccnxp_uart_driver = {
1047	.driver = {
1048		.name	= SCCNXP_NAME,
1049	},
1050	.probe		= sccnxp_probe,
1051	.remove_new	= sccnxp_remove,
1052	.id_table	= sccnxp_id_table,
1053};
1054module_platform_driver(sccnxp_uart_driver);
1055
1056MODULE_LICENSE("GPL v2");
1057MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1058MODULE_DESCRIPTION("SCCNXP serial driver");
v4.17
   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 *  NXP (Philips) SCC+++(SCN+++) serial driver
   4 *
   5 *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
   6 *
   7 *  Based on sc26xx.c, by Thomas Bogendörfer (tsbogend@alpha.franken.de)
   8 */
   9
  10#if defined(CONFIG_SERIAL_SCCNXP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  11#define SUPPORT_SYSRQ
  12#endif
  13
  14#include <linux/clk.h>
 
  15#include <linux/err.h>
  16#include <linux/module.h>
 
  17#include <linux/device.h>
  18#include <linux/console.h>
  19#include <linux/serial_core.h>
  20#include <linux/serial.h>
  21#include <linux/io.h>
  22#include <linux/tty.h>
  23#include <linux/tty_flip.h>
  24#include <linux/spinlock.h>
  25#include <linux/platform_device.h>
  26#include <linux/platform_data/serial-sccnxp.h>
  27#include <linux/regulator/consumer.h>
  28
  29#define SCCNXP_NAME			"uart-sccnxp"
  30#define SCCNXP_MAJOR			204
  31#define SCCNXP_MINOR			205
  32
  33#define SCCNXP_MR_REG			(0x00)
  34#	define MR0_BAUD_NORMAL		(0 << 0)
  35#	define MR0_BAUD_EXT1		(1 << 0)
  36#	define MR0_BAUD_EXT2		(5 << 0)
  37#	define MR0_FIFO			(1 << 3)
  38#	define MR0_TXLVL		(1 << 4)
  39#	define MR1_BITS_5		(0 << 0)
  40#	define MR1_BITS_6		(1 << 0)
  41#	define MR1_BITS_7		(2 << 0)
  42#	define MR1_BITS_8		(3 << 0)
  43#	define MR1_PAR_EVN		(0 << 2)
  44#	define MR1_PAR_ODD		(1 << 2)
  45#	define MR1_PAR_NO		(4 << 2)
  46#	define MR2_STOP1		(7 << 0)
  47#	define MR2_STOP2		(0xf << 0)
  48#define SCCNXP_SR_REG			(0x01)
  49#define SCCNXP_CSR_REG			SCCNXP_SR_REG
  50#	define SR_RXRDY			(1 << 0)
  51#	define SR_FULL			(1 << 1)
  52#	define SR_TXRDY			(1 << 2)
  53#	define SR_TXEMT			(1 << 3)
  54#	define SR_OVR			(1 << 4)
  55#	define SR_PE			(1 << 5)
  56#	define SR_FE			(1 << 6)
  57#	define SR_BRK			(1 << 7)
 
 
  58#define SCCNXP_CR_REG			(0x02)
  59#	define CR_RX_ENABLE		(1 << 0)
  60#	define CR_RX_DISABLE		(1 << 1)
  61#	define CR_TX_ENABLE		(1 << 2)
  62#	define CR_TX_DISABLE		(1 << 3)
  63#	define CR_CMD_MRPTR1		(0x01 << 4)
  64#	define CR_CMD_RX_RESET		(0x02 << 4)
  65#	define CR_CMD_TX_RESET		(0x03 << 4)
  66#	define CR_CMD_STATUS_RESET	(0x04 << 4)
  67#	define CR_CMD_BREAK_RESET	(0x05 << 4)
  68#	define CR_CMD_START_BREAK	(0x06 << 4)
  69#	define CR_CMD_STOP_BREAK	(0x07 << 4)
  70#	define CR_CMD_MRPTR0		(0x0b << 4)
  71#define SCCNXP_RHR_REG			(0x03)
  72#define SCCNXP_THR_REG			SCCNXP_RHR_REG
  73#define SCCNXP_IPCR_REG			(0x04)
  74#define SCCNXP_ACR_REG			SCCNXP_IPCR_REG
  75#	define ACR_BAUD0		(0 << 7)
  76#	define ACR_BAUD1		(1 << 7)
  77#	define ACR_TIMER_MODE		(6 << 4)
  78#define SCCNXP_ISR_REG			(0x05)
  79#define SCCNXP_IMR_REG			SCCNXP_ISR_REG
  80#	define IMR_TXRDY		(1 << 0)
  81#	define IMR_RXRDY		(1 << 1)
  82#	define ISR_TXRDY(x)		(1 << ((x * 4) + 0))
  83#	define ISR_RXRDY(x)		(1 << ((x * 4) + 1))
 
 
  84#define SCCNXP_IPR_REG			(0x0d)
  85#define SCCNXP_OPCR_REG			SCCNXP_IPR_REG
  86#define SCCNXP_SOP_REG			(0x0e)
 
  87#define SCCNXP_ROP_REG			(0x0f)
  88
  89/* Route helpers */
  90#define MCTRL_MASK(sig)			(0xf << (sig))
  91#define MCTRL_IBIT(cfg, sig)		((((cfg) >> (sig)) & 0xf) - LINE_IP0)
  92#define MCTRL_OBIT(cfg, sig)		((((cfg) >> (sig)) & 0xf) - LINE_OP0)
  93
  94#define SCCNXP_HAVE_IO		0x00000001
  95#define SCCNXP_HAVE_MR0		0x00000002
  96
  97struct sccnxp_chip {
  98	const char		*name;
  99	unsigned int		nr;
 100	unsigned long		freq_min;
 101	unsigned long		freq_std;
 102	unsigned long		freq_max;
 103	unsigned int		flags;
 104	unsigned int		fifosize;
 
 
 105};
 106
 107struct sccnxp_port {
 108	struct uart_driver	uart;
 109	struct uart_port	port[SCCNXP_MAX_UARTS];
 110	bool			opened[SCCNXP_MAX_UARTS];
 111
 112	int			irq;
 113	u8			imr;
 114
 115	struct sccnxp_chip	*chip;
 116
 117#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
 118	struct console		console;
 119#endif
 120
 121	spinlock_t		lock;
 122
 123	bool			poll;
 124	struct timer_list	timer;
 125
 126	struct sccnxp_pdata	pdata;
 127
 128	struct regulator	*regulator;
 129};
 130
 131static const struct sccnxp_chip sc2681 = {
 132	.name		= "SC2681",
 133	.nr		= 2,
 134	.freq_min	= 1000000,
 135	.freq_std	= 3686400,
 136	.freq_max	= 4000000,
 137	.flags		= SCCNXP_HAVE_IO,
 138	.fifosize	= 3,
 
 139};
 140
 141static const struct sccnxp_chip sc2691 = {
 142	.name		= "SC2691",
 143	.nr		= 1,
 144	.freq_min	= 1000000,
 145	.freq_std	= 3686400,
 146	.freq_max	= 4000000,
 147	.flags		= 0,
 148	.fifosize	= 3,
 
 149};
 150
 151static const struct sccnxp_chip sc2692 = {
 152	.name		= "SC2692",
 153	.nr		= 2,
 154	.freq_min	= 1000000,
 155	.freq_std	= 3686400,
 156	.freq_max	= 4000000,
 157	.flags		= SCCNXP_HAVE_IO,
 158	.fifosize	= 3,
 
 159};
 160
 161static const struct sccnxp_chip sc2891 = {
 162	.name		= "SC2891",
 163	.nr		= 1,
 164	.freq_min	= 100000,
 165	.freq_std	= 3686400,
 166	.freq_max	= 8000000,
 167	.flags		= SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
 168	.fifosize	= 16,
 
 169};
 170
 171static const struct sccnxp_chip sc2892 = {
 172	.name		= "SC2892",
 173	.nr		= 2,
 174	.freq_min	= 100000,
 175	.freq_std	= 3686400,
 176	.freq_max	= 8000000,
 177	.flags		= SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
 178	.fifosize	= 16,
 
 179};
 180
 181static const struct sccnxp_chip sc28202 = {
 182	.name		= "SC28202",
 183	.nr		= 2,
 184	.freq_min	= 1000000,
 185	.freq_std	= 14745600,
 186	.freq_max	= 50000000,
 187	.flags		= SCCNXP_HAVE_IO | SCCNXP_HAVE_MR0,
 188	.fifosize	= 256,
 
 189};
 190
 191static const struct sccnxp_chip sc68681 = {
 192	.name		= "SC68681",
 193	.nr		= 2,
 194	.freq_min	= 1000000,
 195	.freq_std	= 3686400,
 196	.freq_max	= 4000000,
 197	.flags		= SCCNXP_HAVE_IO,
 198	.fifosize	= 3,
 
 199};
 200
 201static const struct sccnxp_chip sc68692 = {
 202	.name		= "SC68692",
 203	.nr		= 2,
 204	.freq_min	= 1000000,
 205	.freq_std	= 3686400,
 206	.freq_max	= 4000000,
 207	.flags		= SCCNXP_HAVE_IO,
 208	.fifosize	= 3,
 
 209};
 210
 211static inline u8 sccnxp_read(struct uart_port *port, u8 reg)
 212{
 213	return readb(port->membase + (reg << port->regshift));
 
 
 
 
 
 
 
 214}
 215
 216static inline void sccnxp_write(struct uart_port *port, u8 reg, u8 v)
 217{
 
 
 218	writeb(v, port->membase + (reg << port->regshift));
 
 
 219}
 220
 221static inline u8 sccnxp_port_read(struct uart_port *port, u8 reg)
 222{
 223	return sccnxp_read(port, (port->line << 3) + reg);
 224}
 225
 226static inline void sccnxp_port_write(struct uart_port *port, u8 reg, u8 v)
 227{
 228	sccnxp_write(port, (port->line << 3) + reg, v);
 229}
 230
 231static int sccnxp_update_best_err(int a, int b, int *besterr)
 232{
 233	int err = abs(a - b);
 234
 235	if ((*besterr < 0) || (*besterr > err)) {
 236		*besterr = err;
 237		return 0;
 238	}
 239
 240	return 1;
 241}
 242
 243static const struct {
 244	u8	csr;
 245	u8	acr;
 246	u8	mr0;
 247	int	baud;
 248} baud_std[] = {
 249	{ 0,	ACR_BAUD0,	MR0_BAUD_NORMAL,	50, },
 250	{ 0,	ACR_BAUD1,	MR0_BAUD_NORMAL,	75, },
 251	{ 1,	ACR_BAUD0,	MR0_BAUD_NORMAL,	110, },
 252	{ 2,	ACR_BAUD0,	MR0_BAUD_NORMAL,	134, },
 253	{ 3,	ACR_BAUD1,	MR0_BAUD_NORMAL,	150, },
 254	{ 3,	ACR_BAUD0,	MR0_BAUD_NORMAL,	200, },
 255	{ 4,	ACR_BAUD0,	MR0_BAUD_NORMAL,	300, },
 256	{ 0,	ACR_BAUD1,	MR0_BAUD_EXT1,		450, },
 257	{ 1,	ACR_BAUD0,	MR0_BAUD_EXT2,		880, },
 258	{ 3,	ACR_BAUD1,	MR0_BAUD_EXT1,		900, },
 259	{ 5,	ACR_BAUD0,	MR0_BAUD_NORMAL,	600, },
 260	{ 7,	ACR_BAUD0,	MR0_BAUD_NORMAL,	1050, },
 261	{ 2,	ACR_BAUD0,	MR0_BAUD_EXT2,		1076, },
 262	{ 6,	ACR_BAUD0,	MR0_BAUD_NORMAL,	1200, },
 263	{ 10,	ACR_BAUD1,	MR0_BAUD_NORMAL,	1800, },
 264	{ 7,	ACR_BAUD1,	MR0_BAUD_NORMAL,	2000, },
 265	{ 8,	ACR_BAUD0,	MR0_BAUD_NORMAL,	2400, },
 266	{ 5,	ACR_BAUD1,	MR0_BAUD_EXT1,		3600, },
 267	{ 9,	ACR_BAUD0,	MR0_BAUD_NORMAL,	4800, },
 268	{ 10,	ACR_BAUD0,	MR0_BAUD_NORMAL,	7200, },
 269	{ 11,	ACR_BAUD0,	MR0_BAUD_NORMAL,	9600, },
 270	{ 8,	ACR_BAUD0,	MR0_BAUD_EXT1,		14400, },
 271	{ 12,	ACR_BAUD1,	MR0_BAUD_NORMAL,	19200, },
 272	{ 9,	ACR_BAUD0,	MR0_BAUD_EXT1,		28800, },
 273	{ 12,	ACR_BAUD0,	MR0_BAUD_NORMAL,	38400, },
 274	{ 11,	ACR_BAUD0,	MR0_BAUD_EXT1,		57600, },
 275	{ 12,	ACR_BAUD1,	MR0_BAUD_EXT1,		115200, },
 276	{ 12,	ACR_BAUD0,	MR0_BAUD_EXT1,		230400, },
 277	{ 0, 0, 0, 0 }
 278};
 279
 280static int sccnxp_set_baud(struct uart_port *port, int baud)
 281{
 282	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 283	int div_std, tmp_baud, bestbaud = baud, besterr = -1;
 284	struct sccnxp_chip *chip = s->chip;
 285	u8 i, acr = 0, csr = 0, mr0 = 0;
 286
 
 
 
 
 
 
 
 
 
 
 
 
 287	/* Find best baud from table */
 288	for (i = 0; baud_std[i].baud && besterr; i++) {
 289		if (baud_std[i].mr0 && !(chip->flags & SCCNXP_HAVE_MR0))
 290			continue;
 291		div_std = DIV_ROUND_CLOSEST(chip->freq_std, baud_std[i].baud);
 292		tmp_baud = DIV_ROUND_CLOSEST(port->uartclk, div_std);
 293		if (!sccnxp_update_best_err(baud, tmp_baud, &besterr)) {
 294			acr = baud_std[i].acr;
 295			csr = baud_std[i].csr;
 296			mr0 = baud_std[i].mr0;
 297			bestbaud = tmp_baud;
 298		}
 299	}
 300
 301	if (chip->flags & SCCNXP_HAVE_MR0) {
 302		/* Enable FIFO, set half level for TX */
 303		mr0 |= MR0_FIFO | MR0_TXLVL;
 304		/* Update MR0 */
 305		sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR0);
 306		sccnxp_port_write(port, SCCNXP_MR_REG, mr0);
 307	}
 308
 309	sccnxp_port_write(port, SCCNXP_ACR_REG, acr | ACR_TIMER_MODE);
 310	sccnxp_port_write(port, SCCNXP_CSR_REG, (csr << 4) | csr);
 311
 312	if (baud != bestbaud)
 313		dev_dbg(port->dev, "Baudrate desired: %i, calculated: %i\n",
 314			baud, bestbaud);
 315
 316	return bestbaud;
 317}
 318
 319static void sccnxp_enable_irq(struct uart_port *port, int mask)
 320{
 321	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 322
 323	s->imr |= mask << (port->line * 4);
 324	sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
 325}
 326
 327static void sccnxp_disable_irq(struct uart_port *port, int mask)
 328{
 329	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 330
 331	s->imr &= ~(mask << (port->line * 4));
 332	sccnxp_write(port, SCCNXP_IMR_REG, s->imr);
 333}
 334
 335static void sccnxp_set_bit(struct uart_port *port, int sig, int state)
 336{
 337	u8 bitmask;
 338	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 339
 340	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(sig)) {
 341		bitmask = 1 << MCTRL_OBIT(s->pdata.mctrl_cfg[port->line], sig);
 342		if (state)
 343			sccnxp_write(port, SCCNXP_SOP_REG, bitmask);
 344		else
 345			sccnxp_write(port, SCCNXP_ROP_REG, bitmask);
 346	}
 347}
 348
 349static void sccnxp_handle_rx(struct uart_port *port)
 350{
 351	u8 sr;
 352	unsigned int ch, flag;
 353
 354	for (;;) {
 355		sr = sccnxp_port_read(port, SCCNXP_SR_REG);
 356		if (!(sr & SR_RXRDY))
 357			break;
 358		sr &= SR_PE | SR_FE | SR_OVR | SR_BRK;
 359
 360		ch = sccnxp_port_read(port, SCCNXP_RHR_REG);
 361
 362		port->icount.rx++;
 363		flag = TTY_NORMAL;
 364
 365		if (unlikely(sr)) {
 366			if (sr & SR_BRK) {
 367				port->icount.brk++;
 368				sccnxp_port_write(port, SCCNXP_CR_REG,
 369						  CR_CMD_BREAK_RESET);
 370				if (uart_handle_break(port))
 371					continue;
 372			} else if (sr & SR_PE)
 373				port->icount.parity++;
 374			else if (sr & SR_FE)
 375				port->icount.frame++;
 376			else if (sr & SR_OVR) {
 377				port->icount.overrun++;
 378				sccnxp_port_write(port, SCCNXP_CR_REG,
 379						  CR_CMD_STATUS_RESET);
 380			}
 381
 382			sr &= port->read_status_mask;
 383			if (sr & SR_BRK)
 384				flag = TTY_BREAK;
 385			else if (sr & SR_PE)
 386				flag = TTY_PARITY;
 387			else if (sr & SR_FE)
 388				flag = TTY_FRAME;
 389			else if (sr & SR_OVR)
 390				flag = TTY_OVERRUN;
 391		}
 392
 393		if (uart_handle_sysrq_char(port, ch))
 394			continue;
 395
 396		if (sr & port->ignore_status_mask)
 397			continue;
 398
 399		uart_insert_char(port, sr, SR_OVR, ch, flag);
 400	}
 401
 402	tty_flip_buffer_push(&port->state->port);
 403}
 404
 405static void sccnxp_handle_tx(struct uart_port *port)
 406{
 407	u8 sr;
 408	struct circ_buf *xmit = &port->state->xmit;
 409	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 410
 411	if (unlikely(port->x_char)) {
 412		sccnxp_port_write(port, SCCNXP_THR_REG, port->x_char);
 413		port->icount.tx++;
 414		port->x_char = 0;
 415		return;
 416	}
 417
 418	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 419		/* Disable TX if FIFO is empty */
 420		if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXEMT) {
 421			sccnxp_disable_irq(port, IMR_TXRDY);
 422
 423			/* Set direction to input */
 424			if (s->chip->flags & SCCNXP_HAVE_IO)
 425				sccnxp_set_bit(port, DIR_OP, 0);
 426		}
 427		return;
 428	}
 429
 430	while (!uart_circ_empty(xmit)) {
 431		sr = sccnxp_port_read(port, SCCNXP_SR_REG);
 432		if (!(sr & SR_TXRDY))
 433			break;
 434
 435		sccnxp_port_write(port, SCCNXP_THR_REG, xmit->buf[xmit->tail]);
 436		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 437		port->icount.tx++;
 438	}
 439
 440	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 441		uart_write_wakeup(port);
 442}
 443
 444static void sccnxp_handle_events(struct sccnxp_port *s)
 445{
 446	int i;
 447	u8 isr;
 448
 449	do {
 450		isr = sccnxp_read(&s->port[0], SCCNXP_ISR_REG);
 451		isr &= s->imr;
 452		if (!isr)
 453			break;
 454
 455		for (i = 0; i < s->uart.nr; i++) {
 456			if (s->opened[i] && (isr & ISR_RXRDY(i)))
 457				sccnxp_handle_rx(&s->port[i]);
 458			if (s->opened[i] && (isr & ISR_TXRDY(i)))
 459				sccnxp_handle_tx(&s->port[i]);
 460		}
 461	} while (1);
 462}
 463
 464static void sccnxp_timer(struct timer_list *t)
 465{
 466	struct sccnxp_port *s = from_timer(s, t, timer);
 467	unsigned long flags;
 468
 469	spin_lock_irqsave(&s->lock, flags);
 470	sccnxp_handle_events(s);
 471	spin_unlock_irqrestore(&s->lock, flags);
 472
 473	mod_timer(&s->timer, jiffies + usecs_to_jiffies(s->pdata.poll_time_us));
 474}
 475
 476static irqreturn_t sccnxp_ist(int irq, void *dev_id)
 477{
 478	struct sccnxp_port *s = (struct sccnxp_port *)dev_id;
 479	unsigned long flags;
 480
 481	spin_lock_irqsave(&s->lock, flags);
 482	sccnxp_handle_events(s);
 483	spin_unlock_irqrestore(&s->lock, flags);
 484
 485	return IRQ_HANDLED;
 486}
 487
 488static void sccnxp_start_tx(struct uart_port *port)
 489{
 490	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 491	unsigned long flags;
 492
 493	spin_lock_irqsave(&s->lock, flags);
 494
 495	/* Set direction to output */
 496	if (s->chip->flags & SCCNXP_HAVE_IO)
 497		sccnxp_set_bit(port, DIR_OP, 1);
 498
 499	sccnxp_enable_irq(port, IMR_TXRDY);
 500
 501	spin_unlock_irqrestore(&s->lock, flags);
 502}
 503
 504static void sccnxp_stop_tx(struct uart_port *port)
 505{
 506	/* Do nothing */
 507}
 508
 509static void sccnxp_stop_rx(struct uart_port *port)
 510{
 511	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 512	unsigned long flags;
 513
 514	spin_lock_irqsave(&s->lock, flags);
 515	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE);
 516	spin_unlock_irqrestore(&s->lock, flags);
 517}
 518
 519static unsigned int sccnxp_tx_empty(struct uart_port *port)
 520{
 521	u8 val;
 522	unsigned long flags;
 523	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 524
 525	spin_lock_irqsave(&s->lock, flags);
 526	val = sccnxp_port_read(port, SCCNXP_SR_REG);
 527	spin_unlock_irqrestore(&s->lock, flags);
 528
 529	return (val & SR_TXEMT) ? TIOCSER_TEMT : 0;
 530}
 531
 532static void sccnxp_set_mctrl(struct uart_port *port, unsigned int mctrl)
 533{
 534	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 535	unsigned long flags;
 536
 537	if (!(s->chip->flags & SCCNXP_HAVE_IO))
 538		return;
 539
 540	spin_lock_irqsave(&s->lock, flags);
 541
 542	sccnxp_set_bit(port, DTR_OP, mctrl & TIOCM_DTR);
 543	sccnxp_set_bit(port, RTS_OP, mctrl & TIOCM_RTS);
 544
 545	spin_unlock_irqrestore(&s->lock, flags);
 546}
 547
 548static unsigned int sccnxp_get_mctrl(struct uart_port *port)
 549{
 550	u8 bitmask, ipr;
 551	unsigned long flags;
 552	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 553	unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
 554
 555	if (!(s->chip->flags & SCCNXP_HAVE_IO))
 556		return mctrl;
 557
 558	spin_lock_irqsave(&s->lock, flags);
 559
 560	ipr = ~sccnxp_read(port, SCCNXP_IPCR_REG);
 561
 562	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DSR_IP)) {
 563		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 564					  DSR_IP);
 565		mctrl &= ~TIOCM_DSR;
 566		mctrl |= (ipr & bitmask) ? TIOCM_DSR : 0;
 567	}
 568	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(CTS_IP)) {
 569		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 570					  CTS_IP);
 571		mctrl &= ~TIOCM_CTS;
 572		mctrl |= (ipr & bitmask) ? TIOCM_CTS : 0;
 573	}
 574	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(DCD_IP)) {
 575		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 576					  DCD_IP);
 577		mctrl &= ~TIOCM_CAR;
 578		mctrl |= (ipr & bitmask) ? TIOCM_CAR : 0;
 579	}
 580	if (s->pdata.mctrl_cfg[port->line] & MCTRL_MASK(RNG_IP)) {
 581		bitmask = 1 << MCTRL_IBIT(s->pdata.mctrl_cfg[port->line],
 582					  RNG_IP);
 583		mctrl &= ~TIOCM_RNG;
 584		mctrl |= (ipr & bitmask) ? TIOCM_RNG : 0;
 585	}
 586
 587	spin_unlock_irqrestore(&s->lock, flags);
 588
 589	return mctrl;
 590}
 591
 592static void sccnxp_break_ctl(struct uart_port *port, int break_state)
 593{
 594	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 595	unsigned long flags;
 596
 597	spin_lock_irqsave(&s->lock, flags);
 598	sccnxp_port_write(port, SCCNXP_CR_REG, break_state ?
 599			  CR_CMD_START_BREAK : CR_CMD_STOP_BREAK);
 600	spin_unlock_irqrestore(&s->lock, flags);
 601}
 602
 603static void sccnxp_set_termios(struct uart_port *port,
 604			       struct ktermios *termios, struct ktermios *old)
 
 605{
 606	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 607	unsigned long flags;
 608	u8 mr1, mr2;
 609	int baud;
 610
 611	spin_lock_irqsave(&s->lock, flags);
 612
 613	/* Mask termios capabilities we don't support */
 614	termios->c_cflag &= ~CMSPAR;
 615
 616	/* Disable RX & TX, reset break condition, status and FIFOs */
 617	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET |
 618					       CR_RX_DISABLE | CR_TX_DISABLE);
 619	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
 620	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
 621	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
 622
 623	/* Word size */
 624	switch (termios->c_cflag & CSIZE) {
 625	case CS5:
 626		mr1 = MR1_BITS_5;
 627		break;
 628	case CS6:
 629		mr1 = MR1_BITS_6;
 630		break;
 631	case CS7:
 632		mr1 = MR1_BITS_7;
 633		break;
 634	case CS8:
 635	default:
 636		mr1 = MR1_BITS_8;
 637		break;
 638	}
 639
 640	/* Parity */
 641	if (termios->c_cflag & PARENB) {
 642		if (termios->c_cflag & PARODD)
 643			mr1 |= MR1_PAR_ODD;
 644	} else
 645		mr1 |= MR1_PAR_NO;
 646
 647	/* Stop bits */
 648	mr2 = (termios->c_cflag & CSTOPB) ? MR2_STOP2 : MR2_STOP1;
 649
 650	/* Update desired format */
 651	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_MRPTR1);
 652	sccnxp_port_write(port, SCCNXP_MR_REG, mr1);
 653	sccnxp_port_write(port, SCCNXP_MR_REG, mr2);
 654
 655	/* Set read status mask */
 656	port->read_status_mask = SR_OVR;
 657	if (termios->c_iflag & INPCK)
 658		port->read_status_mask |= SR_PE | SR_FE;
 659	if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 660		port->read_status_mask |= SR_BRK;
 661
 662	/* Set status ignore mask */
 663	port->ignore_status_mask = 0;
 664	if (termios->c_iflag & IGNBRK)
 665		port->ignore_status_mask |= SR_BRK;
 666	if (termios->c_iflag & IGNPAR)
 667		port->ignore_status_mask |= SR_PE;
 668	if (!(termios->c_cflag & CREAD))
 669		port->ignore_status_mask |= SR_PE | SR_OVR | SR_FE | SR_BRK;
 670
 671	/* Setup baudrate */
 672	baud = uart_get_baud_rate(port, termios, old, 50,
 673				  (s->chip->flags & SCCNXP_HAVE_MR0) ?
 674				  230400 : 38400);
 675	baud = sccnxp_set_baud(port, baud);
 676
 677	/* Update timeout according to new baud rate */
 678	uart_update_timeout(port, termios->c_cflag, baud);
 679
 680	/* Report actual baudrate back to core */
 681	if (tty_termios_baud_rate(termios))
 682		tty_termios_encode_baud_rate(termios, baud, baud);
 683
 684	/* Enable RX & TX */
 685	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
 686
 687	spin_unlock_irqrestore(&s->lock, flags);
 688}
 689
 690static int sccnxp_startup(struct uart_port *port)
 691{
 692	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 693	unsigned long flags;
 694
 695	spin_lock_irqsave(&s->lock, flags);
 696
 697	if (s->chip->flags & SCCNXP_HAVE_IO) {
 698		/* Outputs are controlled manually */
 699		sccnxp_write(port, SCCNXP_OPCR_REG, 0);
 700	}
 701
 702	/* Reset break condition, status and FIFOs */
 703	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_RX_RESET);
 704	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_TX_RESET);
 705	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_STATUS_RESET);
 706	sccnxp_port_write(port, SCCNXP_CR_REG, CR_CMD_BREAK_RESET);
 707
 708	/* Enable RX & TX */
 709	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_ENABLE | CR_TX_ENABLE);
 710
 711	/* Enable RX interrupt */
 712	sccnxp_enable_irq(port, IMR_RXRDY);
 713
 714	s->opened[port->line] = 1;
 715
 716	spin_unlock_irqrestore(&s->lock, flags);
 717
 718	return 0;
 719}
 720
 721static void sccnxp_shutdown(struct uart_port *port)
 722{
 723	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 724	unsigned long flags;
 725
 726	spin_lock_irqsave(&s->lock, flags);
 727
 728	s->opened[port->line] = 0;
 729
 730	/* Disable interrupts */
 731	sccnxp_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
 732
 733	/* Disable TX & RX */
 734	sccnxp_port_write(port, SCCNXP_CR_REG, CR_RX_DISABLE | CR_TX_DISABLE);
 735
 736	/* Leave direction to input */
 737	if (s->chip->flags & SCCNXP_HAVE_IO)
 738		sccnxp_set_bit(port, DIR_OP, 0);
 739
 740	spin_unlock_irqrestore(&s->lock, flags);
 741}
 742
 743static const char *sccnxp_type(struct uart_port *port)
 744{
 745	struct sccnxp_port *s = dev_get_drvdata(port->dev);
 746
 747	return (port->type == PORT_SC26XX) ? s->chip->name : NULL;
 748}
 749
 750static void sccnxp_release_port(struct uart_port *port)
 751{
 752	/* Do nothing */
 753}
 754
 755static int sccnxp_request_port(struct uart_port *port)
 756{
 757	/* Do nothing */
 758	return 0;
 759}
 760
 761static void sccnxp_config_port(struct uart_port *port, int flags)
 762{
 763	if (flags & UART_CONFIG_TYPE)
 764		port->type = PORT_SC26XX;
 765}
 766
 767static int sccnxp_verify_port(struct uart_port *port, struct serial_struct *s)
 768{
 769	if ((s->type == PORT_UNKNOWN) || (s->type == PORT_SC26XX))
 770		return 0;
 771	if (s->irq == port->irq)
 772		return 0;
 773
 774	return -EINVAL;
 775}
 776
 777static const struct uart_ops sccnxp_ops = {
 778	.tx_empty	= sccnxp_tx_empty,
 779	.set_mctrl	= sccnxp_set_mctrl,
 780	.get_mctrl	= sccnxp_get_mctrl,
 781	.stop_tx	= sccnxp_stop_tx,
 782	.start_tx	= sccnxp_start_tx,
 783	.stop_rx	= sccnxp_stop_rx,
 784	.break_ctl	= sccnxp_break_ctl,
 785	.startup	= sccnxp_startup,
 786	.shutdown	= sccnxp_shutdown,
 787	.set_termios	= sccnxp_set_termios,
 788	.type		= sccnxp_type,
 789	.release_port	= sccnxp_release_port,
 790	.request_port	= sccnxp_request_port,
 791	.config_port	= sccnxp_config_port,
 792	.verify_port	= sccnxp_verify_port,
 793};
 794
 795#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
 796static void sccnxp_console_putchar(struct uart_port *port, int c)
 797{
 798	int tryes = 100000;
 799
 800	while (tryes--) {
 801		if (sccnxp_port_read(port, SCCNXP_SR_REG) & SR_TXRDY) {
 802			sccnxp_port_write(port, SCCNXP_THR_REG, c);
 803			break;
 804		}
 805		barrier();
 806	}
 807}
 808
 809static void sccnxp_console_write(struct console *co, const char *c, unsigned n)
 810{
 811	struct sccnxp_port *s = (struct sccnxp_port *)co->data;
 812	struct uart_port *port = &s->port[co->index];
 813	unsigned long flags;
 814
 815	spin_lock_irqsave(&s->lock, flags);
 816	uart_console_write(port, c, n, sccnxp_console_putchar);
 817	spin_unlock_irqrestore(&s->lock, flags);
 818}
 819
 820static int sccnxp_console_setup(struct console *co, char *options)
 821{
 822	struct sccnxp_port *s = (struct sccnxp_port *)co->data;
 823	struct uart_port *port = &s->port[(co->index > 0) ? co->index : 0];
 824	int baud = 9600, bits = 8, parity = 'n', flow = 'n';
 825
 826	if (options)
 827		uart_parse_options(options, &baud, &parity, &bits, &flow);
 828
 829	return uart_set_options(port, co, baud, parity, bits, flow);
 830}
 831#endif
 832
 833static const struct platform_device_id sccnxp_id_table[] = {
 834	{ .name = "sc2681",	.driver_data = (kernel_ulong_t)&sc2681, },
 835	{ .name = "sc2691",	.driver_data = (kernel_ulong_t)&sc2691, },
 836	{ .name = "sc2692",	.driver_data = (kernel_ulong_t)&sc2692, },
 837	{ .name = "sc2891",	.driver_data = (kernel_ulong_t)&sc2891, },
 838	{ .name = "sc2892",	.driver_data = (kernel_ulong_t)&sc2892, },
 839	{ .name = "sc28202",	.driver_data = (kernel_ulong_t)&sc28202, },
 840	{ .name = "sc68681",	.driver_data = (kernel_ulong_t)&sc68681, },
 841	{ .name = "sc68692",	.driver_data = (kernel_ulong_t)&sc68692, },
 842	{ }
 843};
 844MODULE_DEVICE_TABLE(platform, sccnxp_id_table);
 845
 846static int sccnxp_probe(struct platform_device *pdev)
 847{
 848	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 849	struct sccnxp_pdata *pdata = dev_get_platdata(&pdev->dev);
 
 850	int i, ret, uartclk;
 851	struct sccnxp_port *s;
 852	void __iomem *membase;
 853	struct clk *clk;
 854
 855	membase = devm_ioremap_resource(&pdev->dev, res);
 856	if (IS_ERR(membase))
 857		return PTR_ERR(membase);
 858
 859	s = devm_kzalloc(&pdev->dev, sizeof(struct sccnxp_port), GFP_KERNEL);
 860	if (!s) {
 861		dev_err(&pdev->dev, "Error allocating port structure\n");
 862		return -ENOMEM;
 863	}
 864	platform_set_drvdata(pdev, s);
 865
 866	spin_lock_init(&s->lock);
 867
 868	s->chip = (struct sccnxp_chip *)pdev->id_entry->driver_data;
 869
 870	s->regulator = devm_regulator_get(&pdev->dev, "vcc");
 871	if (!IS_ERR(s->regulator)) {
 872		ret = regulator_enable(s->regulator);
 873		if (ret) {
 874			dev_err(&pdev->dev,
 875				"Failed to enable regulator: %i\n", ret);
 876			return ret;
 877		}
 878	} else if (PTR_ERR(s->regulator) == -EPROBE_DEFER)
 879		return -EPROBE_DEFER;
 880
 881	clk = devm_clk_get(&pdev->dev, NULL);
 882	if (IS_ERR(clk)) {
 883		ret = PTR_ERR(clk);
 884		if (ret == -EPROBE_DEFER)
 885			goto err_out;
 886		uartclk = 0;
 887	} else {
 888		ret = clk_prepare_enable(clk);
 889		if (ret)
 890			goto err_out;
 891
 892		ret = devm_add_action_or_reset(&pdev->dev,
 893				(void(*)(void *))clk_disable_unprepare,
 894				clk);
 895		if (ret)
 896			goto err_out;
 897
 898		uartclk = clk_get_rate(clk);
 899	}
 900
 901	if (!uartclk) {
 902		dev_notice(&pdev->dev, "Using default clock frequency\n");
 903		uartclk = s->chip->freq_std;
 904	}
 905
 906	/* Check input frequency */
 907	if ((uartclk < s->chip->freq_min) || (uartclk > s->chip->freq_max)) {
 908		dev_err(&pdev->dev, "Frequency out of bounds\n");
 909		ret = -EINVAL;
 910		goto err_out;
 911	}
 912
 913	if (pdata)
 914		memcpy(&s->pdata, pdata, sizeof(struct sccnxp_pdata));
 915
 916	if (s->pdata.poll_time_us) {
 917		dev_info(&pdev->dev, "Using poll mode, resolution %u usecs\n",
 918			 s->pdata.poll_time_us);
 919		s->poll = 1;
 920	}
 921
 922	if (!s->poll) {
 923		s->irq = platform_get_irq(pdev, 0);
 924		if (s->irq < 0) {
 925			dev_err(&pdev->dev, "Missing irq resource data\n");
 926			ret = -ENXIO;
 927			goto err_out;
 928		}
 929	}
 930
 931	s->uart.owner		= THIS_MODULE;
 932	s->uart.dev_name	= "ttySC";
 933	s->uart.major		= SCCNXP_MAJOR;
 934	s->uart.minor		= SCCNXP_MINOR;
 935	s->uart.nr		= s->chip->nr;
 936#ifdef CONFIG_SERIAL_SCCNXP_CONSOLE
 937	s->uart.cons		= &s->console;
 938	s->uart.cons->device	= uart_console_device;
 939	s->uart.cons->write	= sccnxp_console_write;
 940	s->uart.cons->setup	= sccnxp_console_setup;
 941	s->uart.cons->flags	= CON_PRINTBUFFER;
 942	s->uart.cons->index	= -1;
 943	s->uart.cons->data	= s;
 944	strcpy(s->uart.cons->name, "ttySC");
 945#endif
 946	ret = uart_register_driver(&s->uart);
 947	if (ret) {
 948		dev_err(&pdev->dev, "Registering UART driver failed\n");
 949		goto err_out;
 950	}
 951
 952	for (i = 0; i < s->uart.nr; i++) {
 953		s->port[i].line		= i;
 954		s->port[i].dev		= &pdev->dev;
 955		s->port[i].irq		= s->irq;
 956		s->port[i].type		= PORT_SC26XX;
 957		s->port[i].fifosize	= s->chip->fifosize;
 958		s->port[i].flags	= UPF_SKIP_TEST | UPF_FIXED_TYPE;
 959		s->port[i].iotype	= UPIO_MEM;
 960		s->port[i].mapbase	= res->start;
 961		s->port[i].membase	= membase;
 962		s->port[i].regshift	= s->pdata.reg_shift;
 963		s->port[i].uartclk	= uartclk;
 964		s->port[i].ops		= &sccnxp_ops;
 
 965		uart_add_one_port(&s->uart, &s->port[i]);
 966		/* Set direction to input */
 967		if (s->chip->flags & SCCNXP_HAVE_IO)
 968			sccnxp_set_bit(&s->port[i], DIR_OP, 0);
 969	}
 970
 971	/* Disable interrupts */
 972	s->imr = 0;
 973	sccnxp_write(&s->port[0], SCCNXP_IMR_REG, 0);
 974
 975	if (!s->poll) {
 976		ret = devm_request_threaded_irq(&pdev->dev, s->irq, NULL,
 977						sccnxp_ist,
 978						IRQF_TRIGGER_FALLING |
 979						IRQF_ONESHOT,
 980						dev_name(&pdev->dev), s);
 981		if (!ret)
 982			return 0;
 983
 984		dev_err(&pdev->dev, "Unable to reguest IRQ %i\n", s->irq);
 985	} else {
 986		timer_setup(&s->timer, sccnxp_timer, 0);
 987		mod_timer(&s->timer, jiffies +
 988			  usecs_to_jiffies(s->pdata.poll_time_us));
 989		return 0;
 990	}
 991
 992	uart_unregister_driver(&s->uart);
 993err_out:
 994	if (!IS_ERR(s->regulator))
 995		regulator_disable(s->regulator);
 996
 997	return ret;
 998}
 999
1000static int sccnxp_remove(struct platform_device *pdev)
1001{
1002	int i;
1003	struct sccnxp_port *s = platform_get_drvdata(pdev);
1004
1005	if (!s->poll)
1006		devm_free_irq(&pdev->dev, s->irq, s);
1007	else
1008		del_timer_sync(&s->timer);
1009
1010	for (i = 0; i < s->uart.nr; i++)
1011		uart_remove_one_port(&s->uart, &s->port[i]);
1012
1013	uart_unregister_driver(&s->uart);
1014
1015	if (!IS_ERR(s->regulator))
1016		return regulator_disable(s->regulator);
1017
1018	return 0;
 
1019}
1020
1021static struct platform_driver sccnxp_uart_driver = {
1022	.driver = {
1023		.name	= SCCNXP_NAME,
1024	},
1025	.probe		= sccnxp_probe,
1026	.remove		= sccnxp_remove,
1027	.id_table	= sccnxp_id_table,
1028};
1029module_platform_driver(sccnxp_uart_driver);
1030
1031MODULE_LICENSE("GPL v2");
1032MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1033MODULE_DESCRIPTION("SCCNXP serial driver");