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1// SPDX-License-Identifier: GPL-2.0+
2// Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3// Copyright (C) 2008 Juergen Beisert
4
5#include <linux/bits.h>
6#include <linux/clk.h>
7#include <linux/completion.h>
8#include <linux/delay.h>
9#include <linux/dmaengine.h>
10#include <linux/dma-mapping.h>
11#include <linux/err.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/pinctrl/consumer.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20#include <linux/slab.h>
21#include <linux/spi/spi.h>
22#include <linux/types.h>
23#include <linux/of.h>
24#include <linux/property.h>
25
26#include <linux/dma/imx-dma.h>
27
28#define DRIVER_NAME "spi_imx"
29
30static bool use_dma = true;
31module_param(use_dma, bool, 0644);
32MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
33
34/* define polling limits */
35static unsigned int polling_limit_us = 30;
36module_param(polling_limit_us, uint, 0664);
37MODULE_PARM_DESC(polling_limit_us,
38 "time in us to run a transfer in polling mode\n");
39
40#define MXC_RPM_TIMEOUT 2000 /* 2000ms */
41
42#define MXC_CSPIRXDATA 0x00
43#define MXC_CSPITXDATA 0x04
44#define MXC_CSPICTRL 0x08
45#define MXC_CSPIINT 0x0c
46#define MXC_RESET 0x1c
47
48/* generic defines to abstract from the different register layouts */
49#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
50#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
51#define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
52
53/* The maximum bytes that a sdma BD can transfer. */
54#define MAX_SDMA_BD_BYTES (1 << 15)
55#define MX51_ECSPI_CTRL_MAX_BURST 512
56/* The maximum bytes that IMX53_ECSPI can transfer in target mode.*/
57#define MX53_MAX_TRANSFER_BYTES 512
58
59enum spi_imx_devtype {
60 IMX1_CSPI,
61 IMX21_CSPI,
62 IMX27_CSPI,
63 IMX31_CSPI,
64 IMX35_CSPI, /* CSPI on all i.mx except above */
65 IMX51_ECSPI, /* ECSPI on i.mx51 */
66 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
67};
68
69struct spi_imx_data;
70
71struct spi_imx_devtype_data {
72 void (*intctrl)(struct spi_imx_data *spi_imx, int enable);
73 int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg);
74 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi);
75 void (*trigger)(struct spi_imx_data *spi_imx);
76 int (*rx_available)(struct spi_imx_data *spi_imx);
77 void (*reset)(struct spi_imx_data *spi_imx);
78 void (*setup_wml)(struct spi_imx_data *spi_imx);
79 void (*disable)(struct spi_imx_data *spi_imx);
80 bool has_dmamode;
81 bool has_targetmode;
82 unsigned int fifo_size;
83 bool dynamic_burst;
84 /*
85 * ERR009165 fixed or not:
86 * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
87 */
88 bool tx_glitch_fixed;
89 enum spi_imx_devtype devtype;
90};
91
92struct spi_imx_data {
93 struct spi_controller *controller;
94 struct device *dev;
95
96 struct completion xfer_done;
97 void __iomem *base;
98 unsigned long base_phys;
99
100 struct clk *clk_per;
101 struct clk *clk_ipg;
102 unsigned long spi_clk;
103 unsigned int spi_bus_clk;
104
105 unsigned int bits_per_word;
106 unsigned int spi_drctl;
107
108 unsigned int count, remainder;
109 void (*tx)(struct spi_imx_data *spi_imx);
110 void (*rx)(struct spi_imx_data *spi_imx);
111 void *rx_buf;
112 const void *tx_buf;
113 unsigned int txfifo; /* number of words pushed in tx FIFO */
114 unsigned int dynamic_burst;
115 bool rx_only;
116
117 /* Target mode */
118 bool target_mode;
119 bool target_aborted;
120 unsigned int target_burst;
121
122 /* DMA */
123 bool usedma;
124 u32 wml;
125 struct completion dma_rx_completion;
126 struct completion dma_tx_completion;
127
128 const struct spi_imx_devtype_data *devtype_data;
129};
130
131static inline int is_imx27_cspi(struct spi_imx_data *d)
132{
133 return d->devtype_data->devtype == IMX27_CSPI;
134}
135
136static inline int is_imx35_cspi(struct spi_imx_data *d)
137{
138 return d->devtype_data->devtype == IMX35_CSPI;
139}
140
141static inline int is_imx51_ecspi(struct spi_imx_data *d)
142{
143 return d->devtype_data->devtype == IMX51_ECSPI;
144}
145
146static inline int is_imx53_ecspi(struct spi_imx_data *d)
147{
148 return d->devtype_data->devtype == IMX53_ECSPI;
149}
150
151#define MXC_SPI_BUF_RX(type) \
152static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
153{ \
154 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
155 \
156 if (spi_imx->rx_buf) { \
157 *(type *)spi_imx->rx_buf = val; \
158 spi_imx->rx_buf += sizeof(type); \
159 } \
160 \
161 spi_imx->remainder -= sizeof(type); \
162}
163
164#define MXC_SPI_BUF_TX(type) \
165static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
166{ \
167 type val = 0; \
168 \
169 if (spi_imx->tx_buf) { \
170 val = *(type *)spi_imx->tx_buf; \
171 spi_imx->tx_buf += sizeof(type); \
172 } \
173 \
174 spi_imx->count -= sizeof(type); \
175 \
176 writel(val, spi_imx->base + MXC_CSPITXDATA); \
177}
178
179MXC_SPI_BUF_RX(u8)
180MXC_SPI_BUF_TX(u8)
181MXC_SPI_BUF_RX(u16)
182MXC_SPI_BUF_TX(u16)
183MXC_SPI_BUF_RX(u32)
184MXC_SPI_BUF_TX(u32)
185
186/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
187 * (which is currently not the case in this driver)
188 */
189static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
190 256, 384, 512, 768, 1024};
191
192/* MX21, MX27 */
193static unsigned int spi_imx_clkdiv_1(unsigned int fin,
194 unsigned int fspi, unsigned int max, unsigned int *fres)
195{
196 int i;
197
198 for (i = 2; i < max; i++)
199 if (fspi * mxc_clkdivs[i] >= fin)
200 break;
201
202 *fres = fin / mxc_clkdivs[i];
203 return i;
204}
205
206/* MX1, MX31, MX35, MX51 CSPI */
207static unsigned int spi_imx_clkdiv_2(unsigned int fin,
208 unsigned int fspi, unsigned int *fres)
209{
210 int i, div = 4;
211
212 for (i = 0; i < 7; i++) {
213 if (fspi * div >= fin)
214 goto out;
215 div <<= 1;
216 }
217
218out:
219 *fres = fin / div;
220 return i;
221}
222
223static int spi_imx_bytes_per_word(const int bits_per_word)
224{
225 if (bits_per_word <= 8)
226 return 1;
227 else if (bits_per_word <= 16)
228 return 2;
229 else
230 return 4;
231}
232
233static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi,
234 struct spi_transfer *transfer)
235{
236 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
237
238 if (!use_dma || controller->fallback)
239 return false;
240
241 if (!controller->dma_rx)
242 return false;
243
244 if (spi_imx->target_mode)
245 return false;
246
247 if (transfer->len < spi_imx->devtype_data->fifo_size)
248 return false;
249
250 spi_imx->dynamic_burst = 0;
251
252 return true;
253}
254
255/*
256 * Note the number of natively supported chip selects for MX51 is 4. Some
257 * devices may have less actual SS pins but the register map supports 4. When
258 * using gpio chip selects the cs values passed into the macros below can go
259 * outside the range 0 - 3. We therefore need to limit the cs value to avoid
260 * corrupting bits outside the allocated locations.
261 *
262 * The simplest way to do this is to just mask the cs bits to 2 bits. This
263 * still allows all 4 native chip selects to work as well as gpio chip selects
264 * (which can use any of the 4 chip select configurations).
265 */
266
267#define MX51_ECSPI_CTRL 0x08
268#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
269#define MX51_ECSPI_CTRL_XCH (1 << 2)
270#define MX51_ECSPI_CTRL_SMC (1 << 3)
271#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
272#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
273#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
274#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
275#define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18)
276#define MX51_ECSPI_CTRL_BL_OFFSET 20
277#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
278
279#define MX51_ECSPI_CONFIG 0x0c
280#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0))
281#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4))
282#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8))
283#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12))
284#define MX51_ECSPI_CONFIG_DATACTL(cs) (1 << ((cs & 3) + 16))
285#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20))
286
287#define MX51_ECSPI_INT 0x10
288#define MX51_ECSPI_INT_TEEN (1 << 0)
289#define MX51_ECSPI_INT_RREN (1 << 3)
290#define MX51_ECSPI_INT_RDREN (1 << 4)
291
292#define MX51_ECSPI_DMA 0x14
293#define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
294#define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
295#define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
296
297#define MX51_ECSPI_DMA_TEDEN (1 << 7)
298#define MX51_ECSPI_DMA_RXDEN (1 << 23)
299#define MX51_ECSPI_DMA_RXTDEN (1 << 31)
300
301#define MX51_ECSPI_STAT 0x18
302#define MX51_ECSPI_STAT_RR (1 << 3)
303
304#define MX51_ECSPI_TESTREG 0x20
305#define MX51_ECSPI_TESTREG_LBC BIT(31)
306
307static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
308{
309 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
310
311 if (spi_imx->rx_buf) {
312#ifdef __LITTLE_ENDIAN
313 unsigned int bytes_per_word;
314
315 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
316 if (bytes_per_word == 1)
317 swab32s(&val);
318 else if (bytes_per_word == 2)
319 swahw32s(&val);
320#endif
321 *(u32 *)spi_imx->rx_buf = val;
322 spi_imx->rx_buf += sizeof(u32);
323 }
324
325 spi_imx->remainder -= sizeof(u32);
326}
327
328static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
329{
330 int unaligned;
331 u32 val;
332
333 unaligned = spi_imx->remainder % 4;
334
335 if (!unaligned) {
336 spi_imx_buf_rx_swap_u32(spi_imx);
337 return;
338 }
339
340 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
341 spi_imx_buf_rx_u16(spi_imx);
342 return;
343 }
344
345 val = readl(spi_imx->base + MXC_CSPIRXDATA);
346
347 while (unaligned--) {
348 if (spi_imx->rx_buf) {
349 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
350 spi_imx->rx_buf++;
351 }
352 spi_imx->remainder--;
353 }
354}
355
356static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
357{
358 u32 val = 0;
359#ifdef __LITTLE_ENDIAN
360 unsigned int bytes_per_word;
361#endif
362
363 if (spi_imx->tx_buf) {
364 val = *(u32 *)spi_imx->tx_buf;
365 spi_imx->tx_buf += sizeof(u32);
366 }
367
368 spi_imx->count -= sizeof(u32);
369#ifdef __LITTLE_ENDIAN
370 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
371
372 if (bytes_per_word == 1)
373 swab32s(&val);
374 else if (bytes_per_word == 2)
375 swahw32s(&val);
376#endif
377 writel(val, spi_imx->base + MXC_CSPITXDATA);
378}
379
380static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
381{
382 int unaligned;
383 u32 val = 0;
384
385 unaligned = spi_imx->count % 4;
386
387 if (!unaligned) {
388 spi_imx_buf_tx_swap_u32(spi_imx);
389 return;
390 }
391
392 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
393 spi_imx_buf_tx_u16(spi_imx);
394 return;
395 }
396
397 while (unaligned--) {
398 if (spi_imx->tx_buf) {
399 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
400 spi_imx->tx_buf++;
401 }
402 spi_imx->count--;
403 }
404
405 writel(val, spi_imx->base + MXC_CSPITXDATA);
406}
407
408static void mx53_ecspi_rx_target(struct spi_imx_data *spi_imx)
409{
410 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
411
412 if (spi_imx->rx_buf) {
413 int n_bytes = spi_imx->target_burst % sizeof(val);
414
415 if (!n_bytes)
416 n_bytes = sizeof(val);
417
418 memcpy(spi_imx->rx_buf,
419 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
420
421 spi_imx->rx_buf += n_bytes;
422 spi_imx->target_burst -= n_bytes;
423 }
424
425 spi_imx->remainder -= sizeof(u32);
426}
427
428static void mx53_ecspi_tx_target(struct spi_imx_data *spi_imx)
429{
430 u32 val = 0;
431 int n_bytes = spi_imx->count % sizeof(val);
432
433 if (!n_bytes)
434 n_bytes = sizeof(val);
435
436 if (spi_imx->tx_buf) {
437 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
438 spi_imx->tx_buf, n_bytes);
439 val = cpu_to_be32(val);
440 spi_imx->tx_buf += n_bytes;
441 }
442
443 spi_imx->count -= n_bytes;
444
445 writel(val, spi_imx->base + MXC_CSPITXDATA);
446}
447
448/* MX51 eCSPI */
449static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
450 unsigned int fspi, unsigned int *fres)
451{
452 /*
453 * there are two 4-bit dividers, the pre-divider divides by
454 * $pre, the post-divider by 2^$post
455 */
456 unsigned int pre, post;
457 unsigned int fin = spi_imx->spi_clk;
458
459 fspi = min(fspi, fin);
460
461 post = fls(fin) - fls(fspi);
462 if (fin > fspi << post)
463 post++;
464
465 /* now we have: (fin <= fspi << post) with post being minimal */
466
467 post = max(4U, post) - 4;
468 if (unlikely(post > 0xf)) {
469 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
470 fspi, fin);
471 return 0xff;
472 }
473
474 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
475
476 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
477 __func__, fin, fspi, post, pre);
478
479 /* Resulting frequency for the SCLK line. */
480 *fres = (fin / (pre + 1)) >> post;
481
482 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
483 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
484}
485
486static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
487{
488 unsigned int val = 0;
489
490 if (enable & MXC_INT_TE)
491 val |= MX51_ECSPI_INT_TEEN;
492
493 if (enable & MXC_INT_RR)
494 val |= MX51_ECSPI_INT_RREN;
495
496 if (enable & MXC_INT_RDR)
497 val |= MX51_ECSPI_INT_RDREN;
498
499 writel(val, spi_imx->base + MX51_ECSPI_INT);
500}
501
502static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
503{
504 u32 reg;
505
506 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
507 reg |= MX51_ECSPI_CTRL_XCH;
508 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
509}
510
511static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
512{
513 u32 ctrl;
514
515 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
516 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
517 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
518}
519
520static int mx51_ecspi_channel(const struct spi_device *spi)
521{
522 if (!spi_get_csgpiod(spi, 0))
523 return spi_get_chipselect(spi, 0);
524 return spi->controller->unused_native_cs;
525}
526
527static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
528 struct spi_message *msg)
529{
530 struct spi_device *spi = msg->spi;
531 struct spi_transfer *xfer;
532 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
533 u32 min_speed_hz = ~0U;
534 u32 testreg, delay;
535 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
536 u32 current_cfg = cfg;
537 int channel = mx51_ecspi_channel(spi);
538
539 /* set Host or Target mode */
540 if (spi_imx->target_mode)
541 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
542 else
543 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
544
545 /*
546 * Enable SPI_RDY handling (falling edge/level triggered).
547 */
548 if (spi->mode & SPI_READY)
549 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
550
551 /* set chip select to use */
552 ctrl |= MX51_ECSPI_CTRL_CS(channel);
553
554 /*
555 * The ctrl register must be written first, with the EN bit set other
556 * registers must not be written to.
557 */
558 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
559
560 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
561 if (spi->mode & SPI_LOOP)
562 testreg |= MX51_ECSPI_TESTREG_LBC;
563 else
564 testreg &= ~MX51_ECSPI_TESTREG_LBC;
565 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
566
567 /*
568 * eCSPI burst completion by Chip Select signal in Target mode
569 * is not functional for imx53 Soc, config SPI burst completed when
570 * BURST_LENGTH + 1 bits are received
571 */
572 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
573 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel);
574 else
575 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel);
576
577 if (spi->mode & SPI_CPOL) {
578 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel);
579 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel);
580 } else {
581 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel);
582 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel);
583 }
584
585 if (spi->mode & SPI_MOSI_IDLE_LOW)
586 cfg |= MX51_ECSPI_CONFIG_DATACTL(channel);
587 else
588 cfg &= ~MX51_ECSPI_CONFIG_DATACTL(channel);
589
590 if (spi->mode & SPI_CS_HIGH)
591 cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel);
592 else
593 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel);
594
595 if (cfg == current_cfg)
596 return 0;
597
598 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
599
600 /*
601 * Wait until the changes in the configuration register CONFIGREG
602 * propagate into the hardware. It takes exactly one tick of the
603 * SCLK clock, but we will wait two SCLK clock just to be sure. The
604 * effect of the delay it takes for the hardware to apply changes
605 * is noticable if the SCLK clock run very slow. In such a case, if
606 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
607 * be asserted before the SCLK polarity changes, which would disrupt
608 * the SPI communication as the device on the other end would consider
609 * the change of SCLK polarity as a clock tick already.
610 *
611 * Because spi_imx->spi_bus_clk is only set in prepare_message
612 * callback, iterate over all the transfers in spi_message, find the
613 * one with lowest bus frequency, and use that bus frequency for the
614 * delay calculation. In case all transfers have speed_hz == 0, then
615 * min_speed_hz is ~0 and the resulting delay is zero.
616 */
617 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
618 if (!xfer->speed_hz)
619 continue;
620 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
621 }
622
623 delay = (2 * 1000000) / min_speed_hz;
624 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */
625 udelay(delay);
626 else /* SCLK is _very_ slow */
627 usleep_range(delay, delay + 10);
628
629 return 0;
630}
631
632static void mx51_configure_cpha(struct spi_imx_data *spi_imx,
633 struct spi_device *spi)
634{
635 bool cpha = (spi->mode & SPI_CPHA);
636 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only;
637 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
638 int channel = mx51_ecspi_channel(spi);
639
640 /* Flip cpha logical value iff flip_cpha */
641 cpha ^= flip_cpha;
642
643 if (cpha)
644 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel);
645 else
646 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel);
647
648 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
649}
650
651static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
652 struct spi_device *spi)
653{
654 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
655 u32 clk;
656
657 /* Clear BL field and set the right value */
658 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
659 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
660 ctrl |= (spi_imx->target_burst * 8 - 1)
661 << MX51_ECSPI_CTRL_BL_OFFSET;
662 else {
663 if (spi_imx->usedma) {
664 ctrl |= (spi_imx->bits_per_word - 1)
665 << MX51_ECSPI_CTRL_BL_OFFSET;
666 } else {
667 if (spi_imx->count >= MX51_ECSPI_CTRL_MAX_BURST)
668 ctrl |= (MX51_ECSPI_CTRL_MAX_BURST * BITS_PER_BYTE - 1)
669 << MX51_ECSPI_CTRL_BL_OFFSET;
670 else
671 ctrl |= spi_imx->count / DIV_ROUND_UP(spi_imx->bits_per_word,
672 BITS_PER_BYTE) * spi_imx->bits_per_word
673 << MX51_ECSPI_CTRL_BL_OFFSET;
674 }
675 }
676
677 /* set clock speed */
678 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
679 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
680 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
681 spi_imx->spi_bus_clk = clk;
682
683 mx51_configure_cpha(spi_imx, spi);
684
685 /*
686 * ERR009165: work in XHC mode instead of SMC as PIO on the chips
687 * before i.mx6ul.
688 */
689 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
690 ctrl |= MX51_ECSPI_CTRL_SMC;
691 else
692 ctrl &= ~MX51_ECSPI_CTRL_SMC;
693
694 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
695
696 return 0;
697}
698
699static void mx51_setup_wml(struct spi_imx_data *spi_imx)
700{
701 u32 tx_wml = 0;
702
703 if (spi_imx->devtype_data->tx_glitch_fixed)
704 tx_wml = spi_imx->wml;
705 /*
706 * Configure the DMA register: setup the watermark
707 * and enable DMA request.
708 */
709 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
710 MX51_ECSPI_DMA_TX_WML(tx_wml) |
711 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
712 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
713 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
714}
715
716static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
717{
718 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
719}
720
721static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
722{
723 /* drain receive buffer */
724 while (mx51_ecspi_rx_available(spi_imx))
725 readl(spi_imx->base + MXC_CSPIRXDATA);
726}
727
728#define MX31_INTREG_TEEN (1 << 0)
729#define MX31_INTREG_RREN (1 << 3)
730
731#define MX31_CSPICTRL_ENABLE (1 << 0)
732#define MX31_CSPICTRL_HOST (1 << 1)
733#define MX31_CSPICTRL_XCH (1 << 2)
734#define MX31_CSPICTRL_SMC (1 << 3)
735#define MX31_CSPICTRL_POL (1 << 4)
736#define MX31_CSPICTRL_PHA (1 << 5)
737#define MX31_CSPICTRL_SSCTL (1 << 6)
738#define MX31_CSPICTRL_SSPOL (1 << 7)
739#define MX31_CSPICTRL_BC_SHIFT 8
740#define MX35_CSPICTRL_BL_SHIFT 20
741#define MX31_CSPICTRL_CS_SHIFT 24
742#define MX35_CSPICTRL_CS_SHIFT 12
743#define MX31_CSPICTRL_DR_SHIFT 16
744
745#define MX31_CSPI_DMAREG 0x10
746#define MX31_DMAREG_RH_DEN (1<<4)
747#define MX31_DMAREG_TH_DEN (1<<1)
748
749#define MX31_CSPISTATUS 0x14
750#define MX31_STATUS_RR (1 << 3)
751
752#define MX31_CSPI_TESTREG 0x1C
753#define MX31_TEST_LBC (1 << 14)
754
755/* These functions also work for the i.MX35, but be aware that
756 * the i.MX35 has a slightly different register layout for bits
757 * we do not use here.
758 */
759static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
760{
761 unsigned int val = 0;
762
763 if (enable & MXC_INT_TE)
764 val |= MX31_INTREG_TEEN;
765 if (enable & MXC_INT_RR)
766 val |= MX31_INTREG_RREN;
767
768 writel(val, spi_imx->base + MXC_CSPIINT);
769}
770
771static void mx31_trigger(struct spi_imx_data *spi_imx)
772{
773 unsigned int reg;
774
775 reg = readl(spi_imx->base + MXC_CSPICTRL);
776 reg |= MX31_CSPICTRL_XCH;
777 writel(reg, spi_imx->base + MXC_CSPICTRL);
778}
779
780static int mx31_prepare_message(struct spi_imx_data *spi_imx,
781 struct spi_message *msg)
782{
783 return 0;
784}
785
786static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
787 struct spi_device *spi)
788{
789 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_HOST;
790 unsigned int clk;
791
792 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
793 MX31_CSPICTRL_DR_SHIFT;
794 spi_imx->spi_bus_clk = clk;
795
796 if (is_imx35_cspi(spi_imx)) {
797 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
798 reg |= MX31_CSPICTRL_SSCTL;
799 } else {
800 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
801 }
802
803 if (spi->mode & SPI_CPHA)
804 reg |= MX31_CSPICTRL_PHA;
805 if (spi->mode & SPI_CPOL)
806 reg |= MX31_CSPICTRL_POL;
807 if (spi->mode & SPI_CS_HIGH)
808 reg |= MX31_CSPICTRL_SSPOL;
809 if (!spi_get_csgpiod(spi, 0))
810 reg |= (spi_get_chipselect(spi, 0)) <<
811 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
812 MX31_CSPICTRL_CS_SHIFT);
813
814 if (spi_imx->usedma)
815 reg |= MX31_CSPICTRL_SMC;
816
817 writel(reg, spi_imx->base + MXC_CSPICTRL);
818
819 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
820 if (spi->mode & SPI_LOOP)
821 reg |= MX31_TEST_LBC;
822 else
823 reg &= ~MX31_TEST_LBC;
824 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
825
826 if (spi_imx->usedma) {
827 /*
828 * configure DMA requests when RXFIFO is half full and
829 * when TXFIFO is half empty
830 */
831 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
832 spi_imx->base + MX31_CSPI_DMAREG);
833 }
834
835 return 0;
836}
837
838static int mx31_rx_available(struct spi_imx_data *spi_imx)
839{
840 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
841}
842
843static void mx31_reset(struct spi_imx_data *spi_imx)
844{
845 /* drain receive buffer */
846 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
847 readl(spi_imx->base + MXC_CSPIRXDATA);
848}
849
850#define MX21_INTREG_RR (1 << 4)
851#define MX21_INTREG_TEEN (1 << 9)
852#define MX21_INTREG_RREN (1 << 13)
853
854#define MX21_CSPICTRL_POL (1 << 5)
855#define MX21_CSPICTRL_PHA (1 << 6)
856#define MX21_CSPICTRL_SSPOL (1 << 8)
857#define MX21_CSPICTRL_XCH (1 << 9)
858#define MX21_CSPICTRL_ENABLE (1 << 10)
859#define MX21_CSPICTRL_HOST (1 << 11)
860#define MX21_CSPICTRL_DR_SHIFT 14
861#define MX21_CSPICTRL_CS_SHIFT 19
862
863static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
864{
865 unsigned int val = 0;
866
867 if (enable & MXC_INT_TE)
868 val |= MX21_INTREG_TEEN;
869 if (enable & MXC_INT_RR)
870 val |= MX21_INTREG_RREN;
871
872 writel(val, spi_imx->base + MXC_CSPIINT);
873}
874
875static void mx21_trigger(struct spi_imx_data *spi_imx)
876{
877 unsigned int reg;
878
879 reg = readl(spi_imx->base + MXC_CSPICTRL);
880 reg |= MX21_CSPICTRL_XCH;
881 writel(reg, spi_imx->base + MXC_CSPICTRL);
882}
883
884static int mx21_prepare_message(struct spi_imx_data *spi_imx,
885 struct spi_message *msg)
886{
887 return 0;
888}
889
890static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
891 struct spi_device *spi)
892{
893 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_HOST;
894 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
895 unsigned int clk;
896
897 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
898 << MX21_CSPICTRL_DR_SHIFT;
899 spi_imx->spi_bus_clk = clk;
900
901 reg |= spi_imx->bits_per_word - 1;
902
903 if (spi->mode & SPI_CPHA)
904 reg |= MX21_CSPICTRL_PHA;
905 if (spi->mode & SPI_CPOL)
906 reg |= MX21_CSPICTRL_POL;
907 if (spi->mode & SPI_CS_HIGH)
908 reg |= MX21_CSPICTRL_SSPOL;
909 if (!spi_get_csgpiod(spi, 0))
910 reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT;
911
912 writel(reg, spi_imx->base + MXC_CSPICTRL);
913
914 return 0;
915}
916
917static int mx21_rx_available(struct spi_imx_data *spi_imx)
918{
919 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
920}
921
922static void mx21_reset(struct spi_imx_data *spi_imx)
923{
924 writel(1, spi_imx->base + MXC_RESET);
925}
926
927#define MX1_INTREG_RR (1 << 3)
928#define MX1_INTREG_TEEN (1 << 8)
929#define MX1_INTREG_RREN (1 << 11)
930
931#define MX1_CSPICTRL_POL (1 << 4)
932#define MX1_CSPICTRL_PHA (1 << 5)
933#define MX1_CSPICTRL_XCH (1 << 8)
934#define MX1_CSPICTRL_ENABLE (1 << 9)
935#define MX1_CSPICTRL_HOST (1 << 10)
936#define MX1_CSPICTRL_DR_SHIFT 13
937
938static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
939{
940 unsigned int val = 0;
941
942 if (enable & MXC_INT_TE)
943 val |= MX1_INTREG_TEEN;
944 if (enable & MXC_INT_RR)
945 val |= MX1_INTREG_RREN;
946
947 writel(val, spi_imx->base + MXC_CSPIINT);
948}
949
950static void mx1_trigger(struct spi_imx_data *spi_imx)
951{
952 unsigned int reg;
953
954 reg = readl(spi_imx->base + MXC_CSPICTRL);
955 reg |= MX1_CSPICTRL_XCH;
956 writel(reg, spi_imx->base + MXC_CSPICTRL);
957}
958
959static int mx1_prepare_message(struct spi_imx_data *spi_imx,
960 struct spi_message *msg)
961{
962 return 0;
963}
964
965static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
966 struct spi_device *spi)
967{
968 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_HOST;
969 unsigned int clk;
970
971 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
972 MX1_CSPICTRL_DR_SHIFT;
973 spi_imx->spi_bus_clk = clk;
974
975 reg |= spi_imx->bits_per_word - 1;
976
977 if (spi->mode & SPI_CPHA)
978 reg |= MX1_CSPICTRL_PHA;
979 if (spi->mode & SPI_CPOL)
980 reg |= MX1_CSPICTRL_POL;
981
982 writel(reg, spi_imx->base + MXC_CSPICTRL);
983
984 return 0;
985}
986
987static int mx1_rx_available(struct spi_imx_data *spi_imx)
988{
989 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
990}
991
992static void mx1_reset(struct spi_imx_data *spi_imx)
993{
994 writel(1, spi_imx->base + MXC_RESET);
995}
996
997static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
998 .intctrl = mx1_intctrl,
999 .prepare_message = mx1_prepare_message,
1000 .prepare_transfer = mx1_prepare_transfer,
1001 .trigger = mx1_trigger,
1002 .rx_available = mx1_rx_available,
1003 .reset = mx1_reset,
1004 .fifo_size = 8,
1005 .has_dmamode = false,
1006 .dynamic_burst = false,
1007 .has_targetmode = false,
1008 .devtype = IMX1_CSPI,
1009};
1010
1011static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
1012 .intctrl = mx21_intctrl,
1013 .prepare_message = mx21_prepare_message,
1014 .prepare_transfer = mx21_prepare_transfer,
1015 .trigger = mx21_trigger,
1016 .rx_available = mx21_rx_available,
1017 .reset = mx21_reset,
1018 .fifo_size = 8,
1019 .has_dmamode = false,
1020 .dynamic_burst = false,
1021 .has_targetmode = false,
1022 .devtype = IMX21_CSPI,
1023};
1024
1025static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
1026 /* i.mx27 cspi shares the functions with i.mx21 one */
1027 .intctrl = mx21_intctrl,
1028 .prepare_message = mx21_prepare_message,
1029 .prepare_transfer = mx21_prepare_transfer,
1030 .trigger = mx21_trigger,
1031 .rx_available = mx21_rx_available,
1032 .reset = mx21_reset,
1033 .fifo_size = 8,
1034 .has_dmamode = false,
1035 .dynamic_burst = false,
1036 .has_targetmode = false,
1037 .devtype = IMX27_CSPI,
1038};
1039
1040static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
1041 .intctrl = mx31_intctrl,
1042 .prepare_message = mx31_prepare_message,
1043 .prepare_transfer = mx31_prepare_transfer,
1044 .trigger = mx31_trigger,
1045 .rx_available = mx31_rx_available,
1046 .reset = mx31_reset,
1047 .fifo_size = 8,
1048 .has_dmamode = false,
1049 .dynamic_burst = false,
1050 .has_targetmode = false,
1051 .devtype = IMX31_CSPI,
1052};
1053
1054static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
1055 /* i.mx35 and later cspi shares the functions with i.mx31 one */
1056 .intctrl = mx31_intctrl,
1057 .prepare_message = mx31_prepare_message,
1058 .prepare_transfer = mx31_prepare_transfer,
1059 .trigger = mx31_trigger,
1060 .rx_available = mx31_rx_available,
1061 .reset = mx31_reset,
1062 .fifo_size = 8,
1063 .has_dmamode = true,
1064 .dynamic_burst = false,
1065 .has_targetmode = false,
1066 .devtype = IMX35_CSPI,
1067};
1068
1069static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1070 .intctrl = mx51_ecspi_intctrl,
1071 .prepare_message = mx51_ecspi_prepare_message,
1072 .prepare_transfer = mx51_ecspi_prepare_transfer,
1073 .trigger = mx51_ecspi_trigger,
1074 .rx_available = mx51_ecspi_rx_available,
1075 .reset = mx51_ecspi_reset,
1076 .setup_wml = mx51_setup_wml,
1077 .fifo_size = 64,
1078 .has_dmamode = true,
1079 .dynamic_burst = true,
1080 .has_targetmode = true,
1081 .disable = mx51_ecspi_disable,
1082 .devtype = IMX51_ECSPI,
1083};
1084
1085static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1086 .intctrl = mx51_ecspi_intctrl,
1087 .prepare_message = mx51_ecspi_prepare_message,
1088 .prepare_transfer = mx51_ecspi_prepare_transfer,
1089 .trigger = mx51_ecspi_trigger,
1090 .rx_available = mx51_ecspi_rx_available,
1091 .reset = mx51_ecspi_reset,
1092 .fifo_size = 64,
1093 .has_dmamode = true,
1094 .has_targetmode = true,
1095 .disable = mx51_ecspi_disable,
1096 .devtype = IMX53_ECSPI,
1097};
1098
1099static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
1100 .intctrl = mx51_ecspi_intctrl,
1101 .prepare_message = mx51_ecspi_prepare_message,
1102 .prepare_transfer = mx51_ecspi_prepare_transfer,
1103 .trigger = mx51_ecspi_trigger,
1104 .rx_available = mx51_ecspi_rx_available,
1105 .reset = mx51_ecspi_reset,
1106 .setup_wml = mx51_setup_wml,
1107 .fifo_size = 64,
1108 .has_dmamode = true,
1109 .dynamic_burst = true,
1110 .has_targetmode = true,
1111 .tx_glitch_fixed = true,
1112 .disable = mx51_ecspi_disable,
1113 .devtype = IMX51_ECSPI,
1114};
1115
1116static const struct of_device_id spi_imx_dt_ids[] = {
1117 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1118 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1119 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1120 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1121 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1122 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1123 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1124 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1125 { /* sentinel */ }
1126};
1127MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1128
1129static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1130{
1131 u32 ctrl;
1132
1133 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1134 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1135 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1136 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1137}
1138
1139static void spi_imx_push(struct spi_imx_data *spi_imx)
1140{
1141 unsigned int burst_len;
1142
1143 /*
1144 * Reload the FIFO when the remaining bytes to be transferred in the
1145 * current burst is 0. This only applies when bits_per_word is a
1146 * multiple of 8.
1147 */
1148 if (!spi_imx->remainder) {
1149 if (spi_imx->dynamic_burst) {
1150
1151 /* We need to deal unaligned data first */
1152 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1153
1154 if (!burst_len)
1155 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1156
1157 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1158
1159 spi_imx->remainder = burst_len;
1160 } else {
1161 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1162 }
1163 }
1164
1165 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1166 if (!spi_imx->count)
1167 break;
1168 if (spi_imx->dynamic_burst &&
1169 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4))
1170 break;
1171 spi_imx->tx(spi_imx);
1172 spi_imx->txfifo++;
1173 }
1174
1175 if (!spi_imx->target_mode)
1176 spi_imx->devtype_data->trigger(spi_imx);
1177}
1178
1179static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1180{
1181 struct spi_imx_data *spi_imx = dev_id;
1182
1183 while (spi_imx->txfifo &&
1184 spi_imx->devtype_data->rx_available(spi_imx)) {
1185 spi_imx->rx(spi_imx);
1186 spi_imx->txfifo--;
1187 }
1188
1189 if (spi_imx->count) {
1190 spi_imx_push(spi_imx);
1191 return IRQ_HANDLED;
1192 }
1193
1194 if (spi_imx->txfifo) {
1195 /* No data left to push, but still waiting for rx data,
1196 * enable receive data available interrupt.
1197 */
1198 spi_imx->devtype_data->intctrl(
1199 spi_imx, MXC_INT_RR);
1200 return IRQ_HANDLED;
1201 }
1202
1203 spi_imx->devtype_data->intctrl(spi_imx, 0);
1204 complete(&spi_imx->xfer_done);
1205
1206 return IRQ_HANDLED;
1207}
1208
1209static int spi_imx_dma_configure(struct spi_controller *controller)
1210{
1211 int ret;
1212 enum dma_slave_buswidth buswidth;
1213 struct dma_slave_config rx = {}, tx = {};
1214 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1215
1216 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1217 case 4:
1218 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1219 break;
1220 case 2:
1221 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1222 break;
1223 case 1:
1224 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1225 break;
1226 default:
1227 return -EINVAL;
1228 }
1229
1230 tx.direction = DMA_MEM_TO_DEV;
1231 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1232 tx.dst_addr_width = buswidth;
1233 tx.dst_maxburst = spi_imx->wml;
1234 ret = dmaengine_slave_config(controller->dma_tx, &tx);
1235 if (ret) {
1236 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1237 return ret;
1238 }
1239
1240 rx.direction = DMA_DEV_TO_MEM;
1241 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1242 rx.src_addr_width = buswidth;
1243 rx.src_maxburst = spi_imx->wml;
1244 ret = dmaengine_slave_config(controller->dma_rx, &rx);
1245 if (ret) {
1246 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1247 return ret;
1248 }
1249
1250 return 0;
1251}
1252
1253static int spi_imx_setupxfer(struct spi_device *spi,
1254 struct spi_transfer *t)
1255{
1256 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1257
1258 if (!t)
1259 return 0;
1260
1261 if (!t->speed_hz) {
1262 if (!spi->max_speed_hz) {
1263 dev_err(&spi->dev, "no speed_hz provided!\n");
1264 return -EINVAL;
1265 }
1266 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1267 spi_imx->spi_bus_clk = spi->max_speed_hz;
1268 } else
1269 spi_imx->spi_bus_clk = t->speed_hz;
1270
1271 spi_imx->bits_per_word = t->bits_per_word;
1272 spi_imx->count = t->len;
1273
1274 /*
1275 * Initialize the functions for transfer. To transfer non byte-aligned
1276 * words, we have to use multiple word-size bursts, we can't use
1277 * dynamic_burst in that case.
1278 */
1279 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode &&
1280 !(spi->mode & SPI_CS_WORD) &&
1281 (spi_imx->bits_per_word == 8 ||
1282 spi_imx->bits_per_word == 16 ||
1283 spi_imx->bits_per_word == 32)) {
1284
1285 spi_imx->rx = spi_imx_buf_rx_swap;
1286 spi_imx->tx = spi_imx_buf_tx_swap;
1287 spi_imx->dynamic_burst = 1;
1288
1289 } else {
1290 if (spi_imx->bits_per_word <= 8) {
1291 spi_imx->rx = spi_imx_buf_rx_u8;
1292 spi_imx->tx = spi_imx_buf_tx_u8;
1293 } else if (spi_imx->bits_per_word <= 16) {
1294 spi_imx->rx = spi_imx_buf_rx_u16;
1295 spi_imx->tx = spi_imx_buf_tx_u16;
1296 } else {
1297 spi_imx->rx = spi_imx_buf_rx_u32;
1298 spi_imx->tx = spi_imx_buf_tx_u32;
1299 }
1300 spi_imx->dynamic_burst = 0;
1301 }
1302
1303 if (spi_imx_can_dma(spi_imx->controller, spi, t))
1304 spi_imx->usedma = true;
1305 else
1306 spi_imx->usedma = false;
1307
1308 spi_imx->rx_only = ((t->tx_buf == NULL)
1309 || (t->tx_buf == spi->controller->dummy_tx));
1310
1311 if (is_imx53_ecspi(spi_imx) && spi_imx->target_mode) {
1312 spi_imx->rx = mx53_ecspi_rx_target;
1313 spi_imx->tx = mx53_ecspi_tx_target;
1314 spi_imx->target_burst = t->len;
1315 }
1316
1317 spi_imx->devtype_data->prepare_transfer(spi_imx, spi);
1318
1319 return 0;
1320}
1321
1322static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1323{
1324 struct spi_controller *controller = spi_imx->controller;
1325
1326 if (controller->dma_rx) {
1327 dma_release_channel(controller->dma_rx);
1328 controller->dma_rx = NULL;
1329 }
1330
1331 if (controller->dma_tx) {
1332 dma_release_channel(controller->dma_tx);
1333 controller->dma_tx = NULL;
1334 }
1335}
1336
1337static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1338 struct spi_controller *controller)
1339{
1340 int ret;
1341
1342 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1343
1344 /* Prepare for TX DMA: */
1345 controller->dma_tx = dma_request_chan(dev, "tx");
1346 if (IS_ERR(controller->dma_tx)) {
1347 ret = PTR_ERR(controller->dma_tx);
1348 dev_err_probe(dev, ret, "can't get the TX DMA channel!\n");
1349 controller->dma_tx = NULL;
1350 goto err;
1351 }
1352
1353 /* Prepare for RX : */
1354 controller->dma_rx = dma_request_chan(dev, "rx");
1355 if (IS_ERR(controller->dma_rx)) {
1356 ret = PTR_ERR(controller->dma_rx);
1357 dev_err_probe(dev, ret, "can't get the RX DMA channel!\n");
1358 controller->dma_rx = NULL;
1359 goto err;
1360 }
1361
1362 init_completion(&spi_imx->dma_rx_completion);
1363 init_completion(&spi_imx->dma_tx_completion);
1364 controller->can_dma = spi_imx_can_dma;
1365 controller->max_dma_len = MAX_SDMA_BD_BYTES;
1366 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX |
1367 SPI_CONTROLLER_MUST_TX;
1368
1369 return 0;
1370err:
1371 spi_imx_sdma_exit(spi_imx);
1372 return ret;
1373}
1374
1375static void spi_imx_dma_rx_callback(void *cookie)
1376{
1377 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1378
1379 complete(&spi_imx->dma_rx_completion);
1380}
1381
1382static void spi_imx_dma_tx_callback(void *cookie)
1383{
1384 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1385
1386 complete(&spi_imx->dma_tx_completion);
1387}
1388
1389static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1390{
1391 unsigned long timeout = 0;
1392
1393 /* Time with actual data transfer and CS change delay related to HW */
1394 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1395
1396 /* Add extra second for scheduler related activities */
1397 timeout += 1;
1398
1399 /* Double calculated timeout */
1400 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1401}
1402
1403static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1404 struct spi_transfer *transfer)
1405{
1406 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1407 unsigned long transfer_timeout;
1408 unsigned long timeout;
1409 struct spi_controller *controller = spi_imx->controller;
1410 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1411 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1412 unsigned int bytes_per_word, i;
1413 int ret;
1414
1415 /* Get the right burst length from the last sg to ensure no tail data */
1416 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1417 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1418 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1419 break;
1420 }
1421 /* Use 1 as wml in case no available burst length got */
1422 if (i == 0)
1423 i = 1;
1424
1425 spi_imx->wml = i;
1426
1427 ret = spi_imx_dma_configure(controller);
1428 if (ret)
1429 goto dma_failure_no_start;
1430
1431 if (!spi_imx->devtype_data->setup_wml) {
1432 dev_err(spi_imx->dev, "No setup_wml()?\n");
1433 ret = -EINVAL;
1434 goto dma_failure_no_start;
1435 }
1436 spi_imx->devtype_data->setup_wml(spi_imx);
1437
1438 /*
1439 * The TX DMA setup starts the transfer, so make sure RX is configured
1440 * before TX.
1441 */
1442 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
1443 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1444 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1445 if (!desc_rx) {
1446 ret = -EINVAL;
1447 goto dma_failure_no_start;
1448 }
1449
1450 desc_rx->callback = spi_imx_dma_rx_callback;
1451 desc_rx->callback_param = (void *)spi_imx;
1452 dmaengine_submit(desc_rx);
1453 reinit_completion(&spi_imx->dma_rx_completion);
1454 dma_async_issue_pending(controller->dma_rx);
1455
1456 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
1457 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1458 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1459 if (!desc_tx) {
1460 dmaengine_terminate_all(controller->dma_tx);
1461 dmaengine_terminate_all(controller->dma_rx);
1462 return -EINVAL;
1463 }
1464
1465 desc_tx->callback = spi_imx_dma_tx_callback;
1466 desc_tx->callback_param = (void *)spi_imx;
1467 dmaengine_submit(desc_tx);
1468 reinit_completion(&spi_imx->dma_tx_completion);
1469 dma_async_issue_pending(controller->dma_tx);
1470
1471 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1472
1473 /* Wait SDMA to finish the data transfer.*/
1474 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1475 transfer_timeout);
1476 if (!timeout) {
1477 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1478 dmaengine_terminate_all(controller->dma_tx);
1479 dmaengine_terminate_all(controller->dma_rx);
1480 return -ETIMEDOUT;
1481 }
1482
1483 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1484 transfer_timeout);
1485 if (!timeout) {
1486 dev_err(&controller->dev, "I/O Error in DMA RX\n");
1487 spi_imx->devtype_data->reset(spi_imx);
1488 dmaengine_terminate_all(controller->dma_rx);
1489 return -ETIMEDOUT;
1490 }
1491
1492 return 0;
1493/* fallback to pio */
1494dma_failure_no_start:
1495 transfer->error |= SPI_TRANS_FAIL_NO_START;
1496 return ret;
1497}
1498
1499static int spi_imx_pio_transfer(struct spi_device *spi,
1500 struct spi_transfer *transfer)
1501{
1502 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1503 unsigned long transfer_timeout;
1504 unsigned long timeout;
1505
1506 spi_imx->tx_buf = transfer->tx_buf;
1507 spi_imx->rx_buf = transfer->rx_buf;
1508 spi_imx->count = transfer->len;
1509 spi_imx->txfifo = 0;
1510 spi_imx->remainder = 0;
1511
1512 reinit_completion(&spi_imx->xfer_done);
1513
1514 spi_imx_push(spi_imx);
1515
1516 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1517
1518 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1519
1520 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1521 transfer_timeout);
1522 if (!timeout) {
1523 dev_err(&spi->dev, "I/O Error in PIO\n");
1524 spi_imx->devtype_data->reset(spi_imx);
1525 return -ETIMEDOUT;
1526 }
1527
1528 return 0;
1529}
1530
1531static int spi_imx_poll_transfer(struct spi_device *spi,
1532 struct spi_transfer *transfer)
1533{
1534 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1535 unsigned long timeout;
1536
1537 spi_imx->tx_buf = transfer->tx_buf;
1538 spi_imx->rx_buf = transfer->rx_buf;
1539 spi_imx->count = transfer->len;
1540 spi_imx->txfifo = 0;
1541 spi_imx->remainder = 0;
1542
1543 /* fill in the fifo before timeout calculations if we are
1544 * interrupted here, then the data is getting transferred by
1545 * the HW while we are interrupted
1546 */
1547 spi_imx_push(spi_imx);
1548
1549 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies;
1550 while (spi_imx->txfifo) {
1551 /* RX */
1552 while (spi_imx->txfifo &&
1553 spi_imx->devtype_data->rx_available(spi_imx)) {
1554 spi_imx->rx(spi_imx);
1555 spi_imx->txfifo--;
1556 }
1557
1558 /* TX */
1559 if (spi_imx->count) {
1560 spi_imx_push(spi_imx);
1561 continue;
1562 }
1563
1564 if (spi_imx->txfifo &&
1565 time_after(jiffies, timeout)) {
1566
1567 dev_err_ratelimited(&spi->dev,
1568 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n",
1569 jiffies - timeout);
1570
1571 /* fall back to interrupt mode */
1572 return spi_imx_pio_transfer(spi, transfer);
1573 }
1574 }
1575
1576 return 0;
1577}
1578
1579static int spi_imx_pio_transfer_target(struct spi_device *spi,
1580 struct spi_transfer *transfer)
1581{
1582 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1583 int ret = 0;
1584
1585 if (is_imx53_ecspi(spi_imx) &&
1586 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1587 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1588 MX53_MAX_TRANSFER_BYTES);
1589 return -EMSGSIZE;
1590 }
1591
1592 spi_imx->tx_buf = transfer->tx_buf;
1593 spi_imx->rx_buf = transfer->rx_buf;
1594 spi_imx->count = transfer->len;
1595 spi_imx->txfifo = 0;
1596 spi_imx->remainder = 0;
1597
1598 reinit_completion(&spi_imx->xfer_done);
1599 spi_imx->target_aborted = false;
1600
1601 spi_imx_push(spi_imx);
1602
1603 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1604
1605 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1606 spi_imx->target_aborted) {
1607 dev_dbg(&spi->dev, "interrupted\n");
1608 ret = -EINTR;
1609 }
1610
1611 /* ecspi has a HW issue when works in Target mode,
1612 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1613 * ECSPI_TXDATA keeps shift out the last word data,
1614 * so we have to disable ECSPI when in target mode after the
1615 * transfer completes
1616 */
1617 if (spi_imx->devtype_data->disable)
1618 spi_imx->devtype_data->disable(spi_imx);
1619
1620 return ret;
1621}
1622
1623static int spi_imx_transfer_one(struct spi_controller *controller,
1624 struct spi_device *spi,
1625 struct spi_transfer *transfer)
1626{
1627 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1628 unsigned long hz_per_byte, byte_limit;
1629
1630 spi_imx_setupxfer(spi, transfer);
1631 transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1632
1633 /* flush rxfifo before transfer */
1634 while (spi_imx->devtype_data->rx_available(spi_imx))
1635 readl(spi_imx->base + MXC_CSPIRXDATA);
1636
1637 if (spi_imx->target_mode)
1638 return spi_imx_pio_transfer_target(spi, transfer);
1639
1640 /*
1641 * If we decided in spi_imx_can_dma() that we want to do a DMA
1642 * transfer, the SPI transfer has already been mapped, so we
1643 * have to do the DMA transfer here.
1644 */
1645 if (spi_imx->usedma)
1646 return spi_imx_dma_transfer(spi_imx, transfer);
1647 /*
1648 * Calculate the estimated time in us the transfer runs. Find
1649 * the number of Hz per byte per polling limit.
1650 */
1651 hz_per_byte = polling_limit_us ? ((8 + 4) * USEC_PER_SEC) / polling_limit_us : 0;
1652 byte_limit = hz_per_byte ? transfer->effective_speed_hz / hz_per_byte : 1;
1653
1654 /* run in polling mode for short transfers */
1655 if (transfer->len < byte_limit)
1656 return spi_imx_poll_transfer(spi, transfer);
1657
1658 return spi_imx_pio_transfer(spi, transfer);
1659}
1660
1661static int spi_imx_setup(struct spi_device *spi)
1662{
1663 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1664 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1665
1666 return 0;
1667}
1668
1669static void spi_imx_cleanup(struct spi_device *spi)
1670{
1671}
1672
1673static int
1674spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg)
1675{
1676 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1677 int ret;
1678
1679 ret = pm_runtime_resume_and_get(spi_imx->dev);
1680 if (ret < 0) {
1681 dev_err(spi_imx->dev, "failed to enable clock\n");
1682 return ret;
1683 }
1684
1685 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1686 if (ret) {
1687 pm_runtime_mark_last_busy(spi_imx->dev);
1688 pm_runtime_put_autosuspend(spi_imx->dev);
1689 }
1690
1691 return ret;
1692}
1693
1694static int
1695spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg)
1696{
1697 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1698
1699 pm_runtime_mark_last_busy(spi_imx->dev);
1700 pm_runtime_put_autosuspend(spi_imx->dev);
1701 return 0;
1702}
1703
1704static int spi_imx_target_abort(struct spi_controller *controller)
1705{
1706 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1707
1708 spi_imx->target_aborted = true;
1709 complete(&spi_imx->xfer_done);
1710
1711 return 0;
1712}
1713
1714static int spi_imx_probe(struct platform_device *pdev)
1715{
1716 struct device_node *np = pdev->dev.of_node;
1717 struct spi_controller *controller;
1718 struct spi_imx_data *spi_imx;
1719 struct resource *res;
1720 int ret, irq, spi_drctl;
1721 const struct spi_imx_devtype_data *devtype_data =
1722 of_device_get_match_data(&pdev->dev);
1723 bool target_mode;
1724 u32 val;
1725
1726 target_mode = devtype_data->has_targetmode &&
1727 of_property_read_bool(np, "spi-slave");
1728 if (target_mode)
1729 controller = spi_alloc_target(&pdev->dev,
1730 sizeof(struct spi_imx_data));
1731 else
1732 controller = spi_alloc_host(&pdev->dev,
1733 sizeof(struct spi_imx_data));
1734 if (!controller)
1735 return -ENOMEM;
1736
1737 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1738 if ((ret < 0) || (spi_drctl >= 0x3)) {
1739 /* '11' is reserved */
1740 spi_drctl = 0;
1741 }
1742
1743 platform_set_drvdata(pdev, controller);
1744
1745 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1746 controller->bus_num = np ? -1 : pdev->id;
1747 controller->use_gpio_descriptors = true;
1748
1749 spi_imx = spi_controller_get_devdata(controller);
1750 spi_imx->controller = controller;
1751 spi_imx->dev = &pdev->dev;
1752 spi_imx->target_mode = target_mode;
1753
1754 spi_imx->devtype_data = devtype_data;
1755
1756 /*
1757 * Get number of chip selects from device properties. This can be
1758 * coming from device tree or boardfiles, if it is not defined,
1759 * a default value of 3 chip selects will be used, as all the legacy
1760 * board files have <= 3 chip selects.
1761 */
1762 if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1763 controller->num_chipselect = val;
1764 else
1765 controller->num_chipselect = 3;
1766
1767 controller->transfer_one = spi_imx_transfer_one;
1768 controller->setup = spi_imx_setup;
1769 controller->cleanup = spi_imx_cleanup;
1770 controller->prepare_message = spi_imx_prepare_message;
1771 controller->unprepare_message = spi_imx_unprepare_message;
1772 controller->target_abort = spi_imx_target_abort;
1773 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS |
1774 SPI_MOSI_IDLE_LOW;
1775
1776 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1777 is_imx53_ecspi(spi_imx))
1778 controller->mode_bits |= SPI_LOOP | SPI_READY;
1779
1780 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx))
1781 controller->mode_bits |= SPI_RX_CPHA_FLIP;
1782
1783 if (is_imx51_ecspi(spi_imx) &&
1784 device_property_read_u32(&pdev->dev, "cs-gpios", NULL))
1785 /*
1786 * When using HW-CS implementing SPI_CS_WORD can be done by just
1787 * setting the burst length to the word size. This is
1788 * considerably faster than manually controlling the CS.
1789 */
1790 controller->mode_bits |= SPI_CS_WORD;
1791
1792 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) {
1793 controller->max_native_cs = 4;
1794 controller->flags |= SPI_CONTROLLER_GPIO_SS;
1795 }
1796
1797 spi_imx->spi_drctl = spi_drctl;
1798
1799 init_completion(&spi_imx->xfer_done);
1800
1801 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1802 if (IS_ERR(spi_imx->base)) {
1803 ret = PTR_ERR(spi_imx->base);
1804 goto out_controller_put;
1805 }
1806 spi_imx->base_phys = res->start;
1807
1808 irq = platform_get_irq(pdev, 0);
1809 if (irq < 0) {
1810 ret = irq;
1811 goto out_controller_put;
1812 }
1813
1814 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1815 dev_name(&pdev->dev), spi_imx);
1816 if (ret) {
1817 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1818 goto out_controller_put;
1819 }
1820
1821 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1822 if (IS_ERR(spi_imx->clk_ipg)) {
1823 ret = PTR_ERR(spi_imx->clk_ipg);
1824 goto out_controller_put;
1825 }
1826
1827 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1828 if (IS_ERR(spi_imx->clk_per)) {
1829 ret = PTR_ERR(spi_imx->clk_per);
1830 goto out_controller_put;
1831 }
1832
1833 ret = clk_prepare_enable(spi_imx->clk_per);
1834 if (ret)
1835 goto out_controller_put;
1836
1837 ret = clk_prepare_enable(spi_imx->clk_ipg);
1838 if (ret)
1839 goto out_put_per;
1840
1841 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1842 pm_runtime_use_autosuspend(spi_imx->dev);
1843 pm_runtime_get_noresume(spi_imx->dev);
1844 pm_runtime_set_active(spi_imx->dev);
1845 pm_runtime_enable(spi_imx->dev);
1846
1847 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1848 /*
1849 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1850 * if validated on other chips.
1851 */
1852 if (spi_imx->devtype_data->has_dmamode) {
1853 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller);
1854 if (ret == -EPROBE_DEFER)
1855 goto out_runtime_pm_put;
1856
1857 if (ret < 0)
1858 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1859 ret);
1860 }
1861
1862 spi_imx->devtype_data->reset(spi_imx);
1863
1864 spi_imx->devtype_data->intctrl(spi_imx, 0);
1865
1866 controller->dev.of_node = pdev->dev.of_node;
1867 ret = spi_register_controller(controller);
1868 if (ret) {
1869 dev_err_probe(&pdev->dev, ret, "register controller failed\n");
1870 goto out_register_controller;
1871 }
1872
1873 pm_runtime_mark_last_busy(spi_imx->dev);
1874 pm_runtime_put_autosuspend(spi_imx->dev);
1875
1876 return ret;
1877
1878out_register_controller:
1879 if (spi_imx->devtype_data->has_dmamode)
1880 spi_imx_sdma_exit(spi_imx);
1881out_runtime_pm_put:
1882 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1883 pm_runtime_set_suspended(&pdev->dev);
1884 pm_runtime_disable(spi_imx->dev);
1885
1886 clk_disable_unprepare(spi_imx->clk_ipg);
1887out_put_per:
1888 clk_disable_unprepare(spi_imx->clk_per);
1889out_controller_put:
1890 spi_controller_put(controller);
1891
1892 return ret;
1893}
1894
1895static void spi_imx_remove(struct platform_device *pdev)
1896{
1897 struct spi_controller *controller = platform_get_drvdata(pdev);
1898 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1899 int ret;
1900
1901 spi_unregister_controller(controller);
1902
1903 ret = pm_runtime_get_sync(spi_imx->dev);
1904 if (ret >= 0)
1905 writel(0, spi_imx->base + MXC_CSPICTRL);
1906 else
1907 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n");
1908
1909 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1910 pm_runtime_put_sync(spi_imx->dev);
1911 pm_runtime_disable(spi_imx->dev);
1912
1913 spi_imx_sdma_exit(spi_imx);
1914}
1915
1916static int __maybe_unused spi_imx_runtime_resume(struct device *dev)
1917{
1918 struct spi_controller *controller = dev_get_drvdata(dev);
1919 struct spi_imx_data *spi_imx;
1920 int ret;
1921
1922 spi_imx = spi_controller_get_devdata(controller);
1923
1924 ret = clk_prepare_enable(spi_imx->clk_per);
1925 if (ret)
1926 return ret;
1927
1928 ret = clk_prepare_enable(spi_imx->clk_ipg);
1929 if (ret) {
1930 clk_disable_unprepare(spi_imx->clk_per);
1931 return ret;
1932 }
1933
1934 return 0;
1935}
1936
1937static int __maybe_unused spi_imx_runtime_suspend(struct device *dev)
1938{
1939 struct spi_controller *controller = dev_get_drvdata(dev);
1940 struct spi_imx_data *spi_imx;
1941
1942 spi_imx = spi_controller_get_devdata(controller);
1943
1944 clk_disable_unprepare(spi_imx->clk_per);
1945 clk_disable_unprepare(spi_imx->clk_ipg);
1946
1947 return 0;
1948}
1949
1950static int __maybe_unused spi_imx_suspend(struct device *dev)
1951{
1952 pinctrl_pm_select_sleep_state(dev);
1953 return 0;
1954}
1955
1956static int __maybe_unused spi_imx_resume(struct device *dev)
1957{
1958 pinctrl_pm_select_default_state(dev);
1959 return 0;
1960}
1961
1962static const struct dev_pm_ops imx_spi_pm = {
1963 SET_RUNTIME_PM_OPS(spi_imx_runtime_suspend,
1964 spi_imx_runtime_resume, NULL)
1965 SET_SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
1966};
1967
1968static struct platform_driver spi_imx_driver = {
1969 .driver = {
1970 .name = DRIVER_NAME,
1971 .of_match_table = spi_imx_dt_ids,
1972 .pm = &imx_spi_pm,
1973 },
1974 .probe = spi_imx_probe,
1975 .remove_new = spi_imx_remove,
1976};
1977module_platform_driver(spi_imx_driver);
1978
1979MODULE_DESCRIPTION("i.MX SPI Controller driver");
1980MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1981MODULE_LICENSE("GPL");
1982MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/dmaengine.h>
25#include <linux/dma-mapping.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
34#include <linux/slab.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/spi_bitbang.h>
37#include <linux/types.h>
38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/of_gpio.h>
41
42#include <linux/platform_data/dma-imx.h>
43#include <linux/platform_data/spi-imx.h>
44
45#define DRIVER_NAME "spi_imx"
46
47#define MXC_CSPIRXDATA 0x00
48#define MXC_CSPITXDATA 0x04
49#define MXC_CSPICTRL 0x08
50#define MXC_CSPIINT 0x0c
51#define MXC_RESET 0x1c
52
53/* generic defines to abstract from the different register layouts */
54#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
56#define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
57
58/* The maximum bytes that a sdma BD can transfer.*/
59#define MAX_SDMA_BD_BYTES (1 << 15)
60#define MX51_ECSPI_CTRL_MAX_BURST 512
61/* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
62#define MX53_MAX_TRANSFER_BYTES 512
63
64enum spi_imx_devtype {
65 IMX1_CSPI,
66 IMX21_CSPI,
67 IMX27_CSPI,
68 IMX31_CSPI,
69 IMX35_CSPI, /* CSPI on all i.mx except above */
70 IMX51_ECSPI, /* ECSPI on i.mx51 */
71 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
72};
73
74struct spi_imx_data;
75
76struct spi_imx_devtype_data {
77 void (*intctrl)(struct spi_imx_data *, int);
78 int (*config)(struct spi_device *);
79 void (*trigger)(struct spi_imx_data *);
80 int (*rx_available)(struct spi_imx_data *);
81 void (*reset)(struct spi_imx_data *);
82 void (*disable)(struct spi_imx_data *);
83 bool has_dmamode;
84 bool has_slavemode;
85 unsigned int fifo_size;
86 bool dynamic_burst;
87 enum spi_imx_devtype devtype;
88};
89
90struct spi_imx_data {
91 struct spi_bitbang bitbang;
92 struct device *dev;
93
94 struct completion xfer_done;
95 void __iomem *base;
96 unsigned long base_phys;
97
98 struct clk *clk_per;
99 struct clk *clk_ipg;
100 unsigned long spi_clk;
101 unsigned int spi_bus_clk;
102
103 unsigned int speed_hz;
104 unsigned int bits_per_word;
105 unsigned int spi_drctl;
106
107 unsigned int count, remainder;
108 void (*tx)(struct spi_imx_data *);
109 void (*rx)(struct spi_imx_data *);
110 void *rx_buf;
111 const void *tx_buf;
112 unsigned int txfifo; /* number of words pushed in tx FIFO */
113 unsigned int dynamic_burst, read_u32;
114 unsigned int word_mask;
115
116 /* Slave mode */
117 bool slave_mode;
118 bool slave_aborted;
119 unsigned int slave_burst;
120
121 /* DMA */
122 bool usedma;
123 u32 wml;
124 struct completion dma_rx_completion;
125 struct completion dma_tx_completion;
126
127 const struct spi_imx_devtype_data *devtype_data;
128};
129
130static inline int is_imx27_cspi(struct spi_imx_data *d)
131{
132 return d->devtype_data->devtype == IMX27_CSPI;
133}
134
135static inline int is_imx35_cspi(struct spi_imx_data *d)
136{
137 return d->devtype_data->devtype == IMX35_CSPI;
138}
139
140static inline int is_imx51_ecspi(struct spi_imx_data *d)
141{
142 return d->devtype_data->devtype == IMX51_ECSPI;
143}
144
145static inline int is_imx53_ecspi(struct spi_imx_data *d)
146{
147 return d->devtype_data->devtype == IMX53_ECSPI;
148}
149
150#define MXC_SPI_BUF_RX(type) \
151static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
152{ \
153 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
154 \
155 if (spi_imx->rx_buf) { \
156 *(type *)spi_imx->rx_buf = val; \
157 spi_imx->rx_buf += sizeof(type); \
158 } \
159}
160
161#define MXC_SPI_BUF_TX(type) \
162static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
163{ \
164 type val = 0; \
165 \
166 if (spi_imx->tx_buf) { \
167 val = *(type *)spi_imx->tx_buf; \
168 spi_imx->tx_buf += sizeof(type); \
169 } \
170 \
171 spi_imx->count -= sizeof(type); \
172 \
173 writel(val, spi_imx->base + MXC_CSPITXDATA); \
174}
175
176MXC_SPI_BUF_RX(u8)
177MXC_SPI_BUF_TX(u8)
178MXC_SPI_BUF_RX(u16)
179MXC_SPI_BUF_TX(u16)
180MXC_SPI_BUF_RX(u32)
181MXC_SPI_BUF_TX(u32)
182
183/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
184 * (which is currently not the case in this driver)
185 */
186static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
187 256, 384, 512, 768, 1024};
188
189/* MX21, MX27 */
190static unsigned int spi_imx_clkdiv_1(unsigned int fin,
191 unsigned int fspi, unsigned int max, unsigned int *fres)
192{
193 int i;
194
195 for (i = 2; i < max; i++)
196 if (fspi * mxc_clkdivs[i] >= fin)
197 break;
198
199 *fres = fin / mxc_clkdivs[i];
200 return i;
201}
202
203/* MX1, MX31, MX35, MX51 CSPI */
204static unsigned int spi_imx_clkdiv_2(unsigned int fin,
205 unsigned int fspi, unsigned int *fres)
206{
207 int i, div = 4;
208
209 for (i = 0; i < 7; i++) {
210 if (fspi * div >= fin)
211 goto out;
212 div <<= 1;
213 }
214
215out:
216 *fres = fin / div;
217 return i;
218}
219
220static int spi_imx_bytes_per_word(const int bits_per_word)
221{
222 return DIV_ROUND_UP(bits_per_word, BITS_PER_BYTE);
223}
224
225static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
226 struct spi_transfer *transfer)
227{
228 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
229 unsigned int bytes_per_word, i;
230
231 if (!master->dma_rx)
232 return false;
233
234 if (spi_imx->slave_mode)
235 return false;
236
237 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
238
239 if (bytes_per_word != 1 && bytes_per_word != 2 && bytes_per_word != 4)
240 return false;
241
242 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
243 if (!(transfer->len % (i * bytes_per_word)))
244 break;
245 }
246
247 if (i == 0)
248 return false;
249
250 spi_imx->wml = i;
251 spi_imx->dynamic_burst = 0;
252
253 return true;
254}
255
256#define MX51_ECSPI_CTRL 0x08
257#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
258#define MX51_ECSPI_CTRL_XCH (1 << 2)
259#define MX51_ECSPI_CTRL_SMC (1 << 3)
260#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
261#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
262#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
263#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
264#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
265#define MX51_ECSPI_CTRL_BL_OFFSET 20
266#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
267
268#define MX51_ECSPI_CONFIG 0x0c
269#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
270#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
271#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
272#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
273#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
274
275#define MX51_ECSPI_INT 0x10
276#define MX51_ECSPI_INT_TEEN (1 << 0)
277#define MX51_ECSPI_INT_RREN (1 << 3)
278#define MX51_ECSPI_INT_RDREN (1 << 4)
279
280#define MX51_ECSPI_DMA 0x14
281#define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
282#define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
283#define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
284
285#define MX51_ECSPI_DMA_TEDEN (1 << 7)
286#define MX51_ECSPI_DMA_RXDEN (1 << 23)
287#define MX51_ECSPI_DMA_RXTDEN (1 << 31)
288
289#define MX51_ECSPI_STAT 0x18
290#define MX51_ECSPI_STAT_RR (1 << 3)
291
292#define MX51_ECSPI_TESTREG 0x20
293#define MX51_ECSPI_TESTREG_LBC BIT(31)
294
295static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
296{
297 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
298#ifdef __LITTLE_ENDIAN
299 unsigned int bytes_per_word;
300#endif
301
302 if (spi_imx->rx_buf) {
303#ifdef __LITTLE_ENDIAN
304 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
305 if (bytes_per_word == 1)
306 val = cpu_to_be32(val);
307 else if (bytes_per_word == 2)
308 val = (val << 16) | (val >> 16);
309#endif
310 val &= spi_imx->word_mask;
311 *(u32 *)spi_imx->rx_buf = val;
312 spi_imx->rx_buf += sizeof(u32);
313 }
314}
315
316static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
317{
318 unsigned int bytes_per_word;
319
320 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
321 if (spi_imx->read_u32) {
322 spi_imx_buf_rx_swap_u32(spi_imx);
323 return;
324 }
325
326 if (bytes_per_word == 1)
327 spi_imx_buf_rx_u8(spi_imx);
328 else if (bytes_per_word == 2)
329 spi_imx_buf_rx_u16(spi_imx);
330}
331
332static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
333{
334 u32 val = 0;
335#ifdef __LITTLE_ENDIAN
336 unsigned int bytes_per_word;
337#endif
338
339 if (spi_imx->tx_buf) {
340 val = *(u32 *)spi_imx->tx_buf;
341 val &= spi_imx->word_mask;
342 spi_imx->tx_buf += sizeof(u32);
343 }
344
345 spi_imx->count -= sizeof(u32);
346#ifdef __LITTLE_ENDIAN
347 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
348
349 if (bytes_per_word == 1)
350 val = cpu_to_be32(val);
351 else if (bytes_per_word == 2)
352 val = (val << 16) | (val >> 16);
353#endif
354 writel(val, spi_imx->base + MXC_CSPITXDATA);
355}
356
357static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
358{
359 u32 ctrl, val;
360 unsigned int bytes_per_word;
361
362 if (spi_imx->count == spi_imx->remainder) {
363 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
364 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
365 if (spi_imx->count > MX51_ECSPI_CTRL_MAX_BURST) {
366 spi_imx->remainder = spi_imx->count %
367 MX51_ECSPI_CTRL_MAX_BURST;
368 val = MX51_ECSPI_CTRL_MAX_BURST * 8 - 1;
369 } else if (spi_imx->count >= sizeof(u32)) {
370 spi_imx->remainder = spi_imx->count % sizeof(u32);
371 val = (spi_imx->count - spi_imx->remainder) * 8 - 1;
372 } else {
373 spi_imx->remainder = 0;
374 val = spi_imx->bits_per_word - 1;
375 spi_imx->read_u32 = 0;
376 }
377
378 ctrl |= (val << MX51_ECSPI_CTRL_BL_OFFSET);
379 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
380 }
381
382 if (spi_imx->count >= sizeof(u32)) {
383 spi_imx_buf_tx_swap_u32(spi_imx);
384 return;
385 }
386
387 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
388
389 if (bytes_per_word == 1)
390 spi_imx_buf_tx_u8(spi_imx);
391 else if (bytes_per_word == 2)
392 spi_imx_buf_tx_u16(spi_imx);
393}
394
395static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
396{
397 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
398
399 if (spi_imx->rx_buf) {
400 int n_bytes = spi_imx->slave_burst % sizeof(val);
401
402 if (!n_bytes)
403 n_bytes = sizeof(val);
404
405 memcpy(spi_imx->rx_buf,
406 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
407
408 spi_imx->rx_buf += n_bytes;
409 spi_imx->slave_burst -= n_bytes;
410 }
411}
412
413static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
414{
415 u32 val = 0;
416 int n_bytes = spi_imx->count % sizeof(val);
417
418 if (!n_bytes)
419 n_bytes = sizeof(val);
420
421 if (spi_imx->tx_buf) {
422 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
423 spi_imx->tx_buf, n_bytes);
424 val = cpu_to_be32(val);
425 spi_imx->tx_buf += n_bytes;
426 }
427
428 spi_imx->count -= n_bytes;
429
430 writel(val, spi_imx->base + MXC_CSPITXDATA);
431}
432
433/* MX51 eCSPI */
434static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
435 unsigned int fspi, unsigned int *fres)
436{
437 /*
438 * there are two 4-bit dividers, the pre-divider divides by
439 * $pre, the post-divider by 2^$post
440 */
441 unsigned int pre, post;
442 unsigned int fin = spi_imx->spi_clk;
443
444 if (unlikely(fspi > fin))
445 return 0;
446
447 post = fls(fin) - fls(fspi);
448 if (fin > fspi << post)
449 post++;
450
451 /* now we have: (fin <= fspi << post) with post being minimal */
452
453 post = max(4U, post) - 4;
454 if (unlikely(post > 0xf)) {
455 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
456 fspi, fin);
457 return 0xff;
458 }
459
460 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
461
462 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
463 __func__, fin, fspi, post, pre);
464
465 /* Resulting frequency for the SCLK line. */
466 *fres = (fin / (pre + 1)) >> post;
467
468 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
469 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
470}
471
472static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
473{
474 unsigned val = 0;
475
476 if (enable & MXC_INT_TE)
477 val |= MX51_ECSPI_INT_TEEN;
478
479 if (enable & MXC_INT_RR)
480 val |= MX51_ECSPI_INT_RREN;
481
482 if (enable & MXC_INT_RDR)
483 val |= MX51_ECSPI_INT_RDREN;
484
485 writel(val, spi_imx->base + MX51_ECSPI_INT);
486}
487
488static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
489{
490 u32 reg;
491
492 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
493 reg |= MX51_ECSPI_CTRL_XCH;
494 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
495}
496
497static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
498{
499 u32 ctrl;
500
501 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
502 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
503 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
504}
505
506static int mx51_ecspi_config(struct spi_device *spi)
507{
508 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
509 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
510 u32 clk = spi_imx->speed_hz, delay, reg;
511 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
512
513 /* set Master or Slave mode */
514 if (spi_imx->slave_mode)
515 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
516 else
517 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
518
519 /*
520 * Enable SPI_RDY handling (falling edge/level triggered).
521 */
522 if (spi->mode & SPI_READY)
523 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
524
525 /* set clock speed */
526 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
527 spi_imx->spi_bus_clk = clk;
528
529 /* set chip select to use */
530 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
531
532 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
533 ctrl |= (spi_imx->slave_burst * 8 - 1)
534 << MX51_ECSPI_CTRL_BL_OFFSET;
535 else
536 ctrl |= (spi_imx->bits_per_word - 1)
537 << MX51_ECSPI_CTRL_BL_OFFSET;
538
539 /*
540 * eCSPI burst completion by Chip Select signal in Slave mode
541 * is not functional for imx53 Soc, config SPI burst completed when
542 * BURST_LENGTH + 1 bits are received
543 */
544 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
545 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
546 else
547 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
548
549 if (spi->mode & SPI_CPHA)
550 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
551 else
552 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
553
554 if (spi->mode & SPI_CPOL) {
555 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
556 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
557 } else {
558 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
559 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
560 }
561 if (spi->mode & SPI_CS_HIGH)
562 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
563 else
564 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
565
566 if (spi_imx->usedma)
567 ctrl |= MX51_ECSPI_CTRL_SMC;
568
569 /* CTRL register always go first to bring out controller from reset */
570 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
571
572 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
573 if (spi->mode & SPI_LOOP)
574 reg |= MX51_ECSPI_TESTREG_LBC;
575 else
576 reg &= ~MX51_ECSPI_TESTREG_LBC;
577 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
578
579 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
580
581 /*
582 * Wait until the changes in the configuration register CONFIGREG
583 * propagate into the hardware. It takes exactly one tick of the
584 * SCLK clock, but we will wait two SCLK clock just to be sure. The
585 * effect of the delay it takes for the hardware to apply changes
586 * is noticable if the SCLK clock run very slow. In such a case, if
587 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
588 * be asserted before the SCLK polarity changes, which would disrupt
589 * the SPI communication as the device on the other end would consider
590 * the change of SCLK polarity as a clock tick already.
591 */
592 delay = (2 * 1000000) / clk;
593 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
594 udelay(delay);
595 else /* SCLK is _very_ slow */
596 usleep_range(delay, delay + 10);
597
598 /*
599 * Configure the DMA register: setup the watermark
600 * and enable DMA request.
601 */
602
603 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
604 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
605 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
606 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
607 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
608
609 return 0;
610}
611
612static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
613{
614 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
615}
616
617static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
618{
619 /* drain receive buffer */
620 while (mx51_ecspi_rx_available(spi_imx))
621 readl(spi_imx->base + MXC_CSPIRXDATA);
622}
623
624#define MX31_INTREG_TEEN (1 << 0)
625#define MX31_INTREG_RREN (1 << 3)
626
627#define MX31_CSPICTRL_ENABLE (1 << 0)
628#define MX31_CSPICTRL_MASTER (1 << 1)
629#define MX31_CSPICTRL_XCH (1 << 2)
630#define MX31_CSPICTRL_SMC (1 << 3)
631#define MX31_CSPICTRL_POL (1 << 4)
632#define MX31_CSPICTRL_PHA (1 << 5)
633#define MX31_CSPICTRL_SSCTL (1 << 6)
634#define MX31_CSPICTRL_SSPOL (1 << 7)
635#define MX31_CSPICTRL_BC_SHIFT 8
636#define MX35_CSPICTRL_BL_SHIFT 20
637#define MX31_CSPICTRL_CS_SHIFT 24
638#define MX35_CSPICTRL_CS_SHIFT 12
639#define MX31_CSPICTRL_DR_SHIFT 16
640
641#define MX31_CSPI_DMAREG 0x10
642#define MX31_DMAREG_RH_DEN (1<<4)
643#define MX31_DMAREG_TH_DEN (1<<1)
644
645#define MX31_CSPISTATUS 0x14
646#define MX31_STATUS_RR (1 << 3)
647
648#define MX31_CSPI_TESTREG 0x1C
649#define MX31_TEST_LBC (1 << 14)
650
651/* These functions also work for the i.MX35, but be aware that
652 * the i.MX35 has a slightly different register layout for bits
653 * we do not use here.
654 */
655static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
656{
657 unsigned int val = 0;
658
659 if (enable & MXC_INT_TE)
660 val |= MX31_INTREG_TEEN;
661 if (enable & MXC_INT_RR)
662 val |= MX31_INTREG_RREN;
663
664 writel(val, spi_imx->base + MXC_CSPIINT);
665}
666
667static void mx31_trigger(struct spi_imx_data *spi_imx)
668{
669 unsigned int reg;
670
671 reg = readl(spi_imx->base + MXC_CSPICTRL);
672 reg |= MX31_CSPICTRL_XCH;
673 writel(reg, spi_imx->base + MXC_CSPICTRL);
674}
675
676static int mx31_config(struct spi_device *spi)
677{
678 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
679 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
680 unsigned int clk;
681
682 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
683 MX31_CSPICTRL_DR_SHIFT;
684 spi_imx->spi_bus_clk = clk;
685
686 if (is_imx35_cspi(spi_imx)) {
687 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
688 reg |= MX31_CSPICTRL_SSCTL;
689 } else {
690 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
691 }
692
693 if (spi->mode & SPI_CPHA)
694 reg |= MX31_CSPICTRL_PHA;
695 if (spi->mode & SPI_CPOL)
696 reg |= MX31_CSPICTRL_POL;
697 if (spi->mode & SPI_CS_HIGH)
698 reg |= MX31_CSPICTRL_SSPOL;
699 if (!gpio_is_valid(spi->cs_gpio))
700 reg |= (spi->chip_select) <<
701 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
702 MX31_CSPICTRL_CS_SHIFT);
703
704 if (spi_imx->usedma)
705 reg |= MX31_CSPICTRL_SMC;
706
707 writel(reg, spi_imx->base + MXC_CSPICTRL);
708
709 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
710 if (spi->mode & SPI_LOOP)
711 reg |= MX31_TEST_LBC;
712 else
713 reg &= ~MX31_TEST_LBC;
714 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
715
716 if (spi_imx->usedma) {
717 /* configure DMA requests when RXFIFO is half full and
718 when TXFIFO is half empty */
719 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
720 spi_imx->base + MX31_CSPI_DMAREG);
721 }
722
723 return 0;
724}
725
726static int mx31_rx_available(struct spi_imx_data *spi_imx)
727{
728 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
729}
730
731static void mx31_reset(struct spi_imx_data *spi_imx)
732{
733 /* drain receive buffer */
734 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
735 readl(spi_imx->base + MXC_CSPIRXDATA);
736}
737
738#define MX21_INTREG_RR (1 << 4)
739#define MX21_INTREG_TEEN (1 << 9)
740#define MX21_INTREG_RREN (1 << 13)
741
742#define MX21_CSPICTRL_POL (1 << 5)
743#define MX21_CSPICTRL_PHA (1 << 6)
744#define MX21_CSPICTRL_SSPOL (1 << 8)
745#define MX21_CSPICTRL_XCH (1 << 9)
746#define MX21_CSPICTRL_ENABLE (1 << 10)
747#define MX21_CSPICTRL_MASTER (1 << 11)
748#define MX21_CSPICTRL_DR_SHIFT 14
749#define MX21_CSPICTRL_CS_SHIFT 19
750
751static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
752{
753 unsigned int val = 0;
754
755 if (enable & MXC_INT_TE)
756 val |= MX21_INTREG_TEEN;
757 if (enable & MXC_INT_RR)
758 val |= MX21_INTREG_RREN;
759
760 writel(val, spi_imx->base + MXC_CSPIINT);
761}
762
763static void mx21_trigger(struct spi_imx_data *spi_imx)
764{
765 unsigned int reg;
766
767 reg = readl(spi_imx->base + MXC_CSPICTRL);
768 reg |= MX21_CSPICTRL_XCH;
769 writel(reg, spi_imx->base + MXC_CSPICTRL);
770}
771
772static int mx21_config(struct spi_device *spi)
773{
774 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
775 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
776 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
777 unsigned int clk;
778
779 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk)
780 << MX21_CSPICTRL_DR_SHIFT;
781 spi_imx->spi_bus_clk = clk;
782
783 reg |= spi_imx->bits_per_word - 1;
784
785 if (spi->mode & SPI_CPHA)
786 reg |= MX21_CSPICTRL_PHA;
787 if (spi->mode & SPI_CPOL)
788 reg |= MX21_CSPICTRL_POL;
789 if (spi->mode & SPI_CS_HIGH)
790 reg |= MX21_CSPICTRL_SSPOL;
791 if (!gpio_is_valid(spi->cs_gpio))
792 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
793
794 writel(reg, spi_imx->base + MXC_CSPICTRL);
795
796 return 0;
797}
798
799static int mx21_rx_available(struct spi_imx_data *spi_imx)
800{
801 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
802}
803
804static void mx21_reset(struct spi_imx_data *spi_imx)
805{
806 writel(1, spi_imx->base + MXC_RESET);
807}
808
809#define MX1_INTREG_RR (1 << 3)
810#define MX1_INTREG_TEEN (1 << 8)
811#define MX1_INTREG_RREN (1 << 11)
812
813#define MX1_CSPICTRL_POL (1 << 4)
814#define MX1_CSPICTRL_PHA (1 << 5)
815#define MX1_CSPICTRL_XCH (1 << 8)
816#define MX1_CSPICTRL_ENABLE (1 << 9)
817#define MX1_CSPICTRL_MASTER (1 << 10)
818#define MX1_CSPICTRL_DR_SHIFT 13
819
820static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
821{
822 unsigned int val = 0;
823
824 if (enable & MXC_INT_TE)
825 val |= MX1_INTREG_TEEN;
826 if (enable & MXC_INT_RR)
827 val |= MX1_INTREG_RREN;
828
829 writel(val, spi_imx->base + MXC_CSPIINT);
830}
831
832static void mx1_trigger(struct spi_imx_data *spi_imx)
833{
834 unsigned int reg;
835
836 reg = readl(spi_imx->base + MXC_CSPICTRL);
837 reg |= MX1_CSPICTRL_XCH;
838 writel(reg, spi_imx->base + MXC_CSPICTRL);
839}
840
841static int mx1_config(struct spi_device *spi)
842{
843 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
844 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
845 unsigned int clk;
846
847 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
848 MX1_CSPICTRL_DR_SHIFT;
849 spi_imx->spi_bus_clk = clk;
850
851 reg |= spi_imx->bits_per_word - 1;
852
853 if (spi->mode & SPI_CPHA)
854 reg |= MX1_CSPICTRL_PHA;
855 if (spi->mode & SPI_CPOL)
856 reg |= MX1_CSPICTRL_POL;
857
858 writel(reg, spi_imx->base + MXC_CSPICTRL);
859
860 return 0;
861}
862
863static int mx1_rx_available(struct spi_imx_data *spi_imx)
864{
865 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
866}
867
868static void mx1_reset(struct spi_imx_data *spi_imx)
869{
870 writel(1, spi_imx->base + MXC_RESET);
871}
872
873static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
874 .intctrl = mx1_intctrl,
875 .config = mx1_config,
876 .trigger = mx1_trigger,
877 .rx_available = mx1_rx_available,
878 .reset = mx1_reset,
879 .fifo_size = 8,
880 .has_dmamode = false,
881 .dynamic_burst = false,
882 .has_slavemode = false,
883 .devtype = IMX1_CSPI,
884};
885
886static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
887 .intctrl = mx21_intctrl,
888 .config = mx21_config,
889 .trigger = mx21_trigger,
890 .rx_available = mx21_rx_available,
891 .reset = mx21_reset,
892 .fifo_size = 8,
893 .has_dmamode = false,
894 .dynamic_burst = false,
895 .has_slavemode = false,
896 .devtype = IMX21_CSPI,
897};
898
899static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
900 /* i.mx27 cspi shares the functions with i.mx21 one */
901 .intctrl = mx21_intctrl,
902 .config = mx21_config,
903 .trigger = mx21_trigger,
904 .rx_available = mx21_rx_available,
905 .reset = mx21_reset,
906 .fifo_size = 8,
907 .has_dmamode = false,
908 .dynamic_burst = false,
909 .has_slavemode = false,
910 .devtype = IMX27_CSPI,
911};
912
913static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
914 .intctrl = mx31_intctrl,
915 .config = mx31_config,
916 .trigger = mx31_trigger,
917 .rx_available = mx31_rx_available,
918 .reset = mx31_reset,
919 .fifo_size = 8,
920 .has_dmamode = false,
921 .dynamic_burst = false,
922 .has_slavemode = false,
923 .devtype = IMX31_CSPI,
924};
925
926static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
927 /* i.mx35 and later cspi shares the functions with i.mx31 one */
928 .intctrl = mx31_intctrl,
929 .config = mx31_config,
930 .trigger = mx31_trigger,
931 .rx_available = mx31_rx_available,
932 .reset = mx31_reset,
933 .fifo_size = 8,
934 .has_dmamode = true,
935 .dynamic_burst = false,
936 .has_slavemode = false,
937 .devtype = IMX35_CSPI,
938};
939
940static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
941 .intctrl = mx51_ecspi_intctrl,
942 .config = mx51_ecspi_config,
943 .trigger = mx51_ecspi_trigger,
944 .rx_available = mx51_ecspi_rx_available,
945 .reset = mx51_ecspi_reset,
946 .fifo_size = 64,
947 .has_dmamode = true,
948 .dynamic_burst = true,
949 .has_slavemode = true,
950 .disable = mx51_ecspi_disable,
951 .devtype = IMX51_ECSPI,
952};
953
954static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
955 .intctrl = mx51_ecspi_intctrl,
956 .config = mx51_ecspi_config,
957 .trigger = mx51_ecspi_trigger,
958 .rx_available = mx51_ecspi_rx_available,
959 .reset = mx51_ecspi_reset,
960 .fifo_size = 64,
961 .has_dmamode = true,
962 .has_slavemode = true,
963 .disable = mx51_ecspi_disable,
964 .devtype = IMX53_ECSPI,
965};
966
967static const struct platform_device_id spi_imx_devtype[] = {
968 {
969 .name = "imx1-cspi",
970 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
971 }, {
972 .name = "imx21-cspi",
973 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
974 }, {
975 .name = "imx27-cspi",
976 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
977 }, {
978 .name = "imx31-cspi",
979 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
980 }, {
981 .name = "imx35-cspi",
982 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
983 }, {
984 .name = "imx51-ecspi",
985 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
986 }, {
987 .name = "imx53-ecspi",
988 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
989 }, {
990 /* sentinel */
991 }
992};
993
994static const struct of_device_id spi_imx_dt_ids[] = {
995 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
996 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
997 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
998 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
999 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1000 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1001 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1002 { /* sentinel */ }
1003};
1004MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1005
1006static void spi_imx_chipselect(struct spi_device *spi, int is_active)
1007{
1008 int active = is_active != BITBANG_CS_INACTIVE;
1009 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
1010
1011 if (spi->mode & SPI_NO_CS)
1012 return;
1013
1014 if (!gpio_is_valid(spi->cs_gpio))
1015 return;
1016
1017 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1018}
1019
1020static void spi_imx_push(struct spi_imx_data *spi_imx)
1021{
1022 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1023 if (!spi_imx->count)
1024 break;
1025 if (spi_imx->txfifo && (spi_imx->count == spi_imx->remainder))
1026 break;
1027 spi_imx->tx(spi_imx);
1028 spi_imx->txfifo++;
1029 }
1030
1031 if (!spi_imx->slave_mode)
1032 spi_imx->devtype_data->trigger(spi_imx);
1033}
1034
1035static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1036{
1037 struct spi_imx_data *spi_imx = dev_id;
1038
1039 while (spi_imx->txfifo &&
1040 spi_imx->devtype_data->rx_available(spi_imx)) {
1041 spi_imx->rx(spi_imx);
1042 spi_imx->txfifo--;
1043 }
1044
1045 if (spi_imx->count) {
1046 spi_imx_push(spi_imx);
1047 return IRQ_HANDLED;
1048 }
1049
1050 if (spi_imx->txfifo) {
1051 /* No data left to push, but still waiting for rx data,
1052 * enable receive data available interrupt.
1053 */
1054 spi_imx->devtype_data->intctrl(
1055 spi_imx, MXC_INT_RR);
1056 return IRQ_HANDLED;
1057 }
1058
1059 spi_imx->devtype_data->intctrl(spi_imx, 0);
1060 complete(&spi_imx->xfer_done);
1061
1062 return IRQ_HANDLED;
1063}
1064
1065static int spi_imx_dma_configure(struct spi_master *master)
1066{
1067 int ret;
1068 enum dma_slave_buswidth buswidth;
1069 struct dma_slave_config rx = {}, tx = {};
1070 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1071
1072 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1073 case 4:
1074 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1075 break;
1076 case 2:
1077 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1078 break;
1079 case 1:
1080 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1081 break;
1082 default:
1083 return -EINVAL;
1084 }
1085
1086 tx.direction = DMA_MEM_TO_DEV;
1087 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1088 tx.dst_addr_width = buswidth;
1089 tx.dst_maxburst = spi_imx->wml;
1090 ret = dmaengine_slave_config(master->dma_tx, &tx);
1091 if (ret) {
1092 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1093 return ret;
1094 }
1095
1096 rx.direction = DMA_DEV_TO_MEM;
1097 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1098 rx.src_addr_width = buswidth;
1099 rx.src_maxburst = spi_imx->wml;
1100 ret = dmaengine_slave_config(master->dma_rx, &rx);
1101 if (ret) {
1102 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1103 return ret;
1104 }
1105
1106 return 0;
1107}
1108
1109static int spi_imx_setupxfer(struct spi_device *spi,
1110 struct spi_transfer *t)
1111{
1112 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1113 int ret;
1114
1115 if (!t)
1116 return 0;
1117
1118 spi_imx->bits_per_word = t->bits_per_word;
1119 spi_imx->speed_hz = t->speed_hz;
1120
1121 /* Initialize the functions for transfer */
1122 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode) {
1123 u32 mask;
1124
1125 spi_imx->dynamic_burst = 0;
1126 spi_imx->remainder = 0;
1127 spi_imx->read_u32 = 1;
1128
1129 mask = (1 << spi_imx->bits_per_word) - 1;
1130 spi_imx->rx = spi_imx_buf_rx_swap;
1131 spi_imx->tx = spi_imx_buf_tx_swap;
1132 spi_imx->dynamic_burst = 1;
1133 spi_imx->remainder = t->len;
1134
1135 if (spi_imx->bits_per_word <= 8)
1136 spi_imx->word_mask = mask << 24 | mask << 16
1137 | mask << 8 | mask;
1138 else if (spi_imx->bits_per_word <= 16)
1139 spi_imx->word_mask = mask << 16 | mask;
1140 else
1141 spi_imx->word_mask = mask;
1142 } else {
1143 if (spi_imx->bits_per_word <= 8) {
1144 spi_imx->rx = spi_imx_buf_rx_u8;
1145 spi_imx->tx = spi_imx_buf_tx_u8;
1146 } else if (spi_imx->bits_per_word <= 16) {
1147 spi_imx->rx = spi_imx_buf_rx_u16;
1148 spi_imx->tx = spi_imx_buf_tx_u16;
1149 } else {
1150 spi_imx->rx = spi_imx_buf_rx_u32;
1151 spi_imx->tx = spi_imx_buf_tx_u32;
1152 }
1153 }
1154
1155 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1156 spi_imx->usedma = 1;
1157 else
1158 spi_imx->usedma = 0;
1159
1160 if (spi_imx->usedma) {
1161 ret = spi_imx_dma_configure(spi->master);
1162 if (ret)
1163 return ret;
1164 }
1165
1166 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1167 spi_imx->rx = mx53_ecspi_rx_slave;
1168 spi_imx->tx = mx53_ecspi_tx_slave;
1169 spi_imx->slave_burst = t->len;
1170 }
1171
1172 spi_imx->devtype_data->config(spi);
1173
1174 return 0;
1175}
1176
1177static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1178{
1179 struct spi_master *master = spi_imx->bitbang.master;
1180
1181 if (master->dma_rx) {
1182 dma_release_channel(master->dma_rx);
1183 master->dma_rx = NULL;
1184 }
1185
1186 if (master->dma_tx) {
1187 dma_release_channel(master->dma_tx);
1188 master->dma_tx = NULL;
1189 }
1190}
1191
1192static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1193 struct spi_master *master)
1194{
1195 int ret;
1196
1197 /* use pio mode for i.mx6dl chip TKT238285 */
1198 if (of_machine_is_compatible("fsl,imx6dl"))
1199 return 0;
1200
1201 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1202
1203 /* Prepare for TX DMA: */
1204 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1205 if (IS_ERR(master->dma_tx)) {
1206 ret = PTR_ERR(master->dma_tx);
1207 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1208 master->dma_tx = NULL;
1209 goto err;
1210 }
1211
1212 /* Prepare for RX : */
1213 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1214 if (IS_ERR(master->dma_rx)) {
1215 ret = PTR_ERR(master->dma_rx);
1216 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1217 master->dma_rx = NULL;
1218 goto err;
1219 }
1220
1221 init_completion(&spi_imx->dma_rx_completion);
1222 init_completion(&spi_imx->dma_tx_completion);
1223 master->can_dma = spi_imx_can_dma;
1224 master->max_dma_len = MAX_SDMA_BD_BYTES;
1225 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1226 SPI_MASTER_MUST_TX;
1227
1228 return 0;
1229err:
1230 spi_imx_sdma_exit(spi_imx);
1231 return ret;
1232}
1233
1234static void spi_imx_dma_rx_callback(void *cookie)
1235{
1236 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1237
1238 complete(&spi_imx->dma_rx_completion);
1239}
1240
1241static void spi_imx_dma_tx_callback(void *cookie)
1242{
1243 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1244
1245 complete(&spi_imx->dma_tx_completion);
1246}
1247
1248static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1249{
1250 unsigned long timeout = 0;
1251
1252 /* Time with actual data transfer and CS change delay related to HW */
1253 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1254
1255 /* Add extra second for scheduler related activities */
1256 timeout += 1;
1257
1258 /* Double calculated timeout */
1259 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1260}
1261
1262static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1263 struct spi_transfer *transfer)
1264{
1265 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1266 unsigned long transfer_timeout;
1267 unsigned long timeout;
1268 struct spi_master *master = spi_imx->bitbang.master;
1269 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1270
1271 /*
1272 * The TX DMA setup starts the transfer, so make sure RX is configured
1273 * before TX.
1274 */
1275 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1276 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1277 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1278 if (!desc_rx)
1279 return -EINVAL;
1280
1281 desc_rx->callback = spi_imx_dma_rx_callback;
1282 desc_rx->callback_param = (void *)spi_imx;
1283 dmaengine_submit(desc_rx);
1284 reinit_completion(&spi_imx->dma_rx_completion);
1285 dma_async_issue_pending(master->dma_rx);
1286
1287 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1288 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1289 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1290 if (!desc_tx) {
1291 dmaengine_terminate_all(master->dma_tx);
1292 return -EINVAL;
1293 }
1294
1295 desc_tx->callback = spi_imx_dma_tx_callback;
1296 desc_tx->callback_param = (void *)spi_imx;
1297 dmaengine_submit(desc_tx);
1298 reinit_completion(&spi_imx->dma_tx_completion);
1299 dma_async_issue_pending(master->dma_tx);
1300
1301 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1302
1303 /* Wait SDMA to finish the data transfer.*/
1304 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1305 transfer_timeout);
1306 if (!timeout) {
1307 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1308 dmaengine_terminate_all(master->dma_tx);
1309 dmaengine_terminate_all(master->dma_rx);
1310 return -ETIMEDOUT;
1311 }
1312
1313 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1314 transfer_timeout);
1315 if (!timeout) {
1316 dev_err(&master->dev, "I/O Error in DMA RX\n");
1317 spi_imx->devtype_data->reset(spi_imx);
1318 dmaengine_terminate_all(master->dma_rx);
1319 return -ETIMEDOUT;
1320 }
1321
1322 return transfer->len;
1323}
1324
1325static int spi_imx_pio_transfer(struct spi_device *spi,
1326 struct spi_transfer *transfer)
1327{
1328 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1329 unsigned long transfer_timeout;
1330 unsigned long timeout;
1331
1332 spi_imx->tx_buf = transfer->tx_buf;
1333 spi_imx->rx_buf = transfer->rx_buf;
1334 spi_imx->count = transfer->len;
1335 spi_imx->txfifo = 0;
1336
1337 reinit_completion(&spi_imx->xfer_done);
1338
1339 spi_imx_push(spi_imx);
1340
1341 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1342
1343 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1344
1345 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1346 transfer_timeout);
1347 if (!timeout) {
1348 dev_err(&spi->dev, "I/O Error in PIO\n");
1349 spi_imx->devtype_data->reset(spi_imx);
1350 return -ETIMEDOUT;
1351 }
1352
1353 return transfer->len;
1354}
1355
1356static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1357 struct spi_transfer *transfer)
1358{
1359 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1360 int ret = transfer->len;
1361
1362 if (is_imx53_ecspi(spi_imx) &&
1363 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1364 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1365 MX53_MAX_TRANSFER_BYTES);
1366 return -EMSGSIZE;
1367 }
1368
1369 spi_imx->tx_buf = transfer->tx_buf;
1370 spi_imx->rx_buf = transfer->rx_buf;
1371 spi_imx->count = transfer->len;
1372 spi_imx->txfifo = 0;
1373
1374 reinit_completion(&spi_imx->xfer_done);
1375 spi_imx->slave_aborted = false;
1376
1377 spi_imx_push(spi_imx);
1378
1379 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1380
1381 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1382 spi_imx->slave_aborted) {
1383 dev_dbg(&spi->dev, "interrupted\n");
1384 ret = -EINTR;
1385 }
1386
1387 /* ecspi has a HW issue when works in Slave mode,
1388 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1389 * ECSPI_TXDATA keeps shift out the last word data,
1390 * so we have to disable ECSPI when in slave mode after the
1391 * transfer completes
1392 */
1393 if (spi_imx->devtype_data->disable)
1394 spi_imx->devtype_data->disable(spi_imx);
1395
1396 return ret;
1397}
1398
1399static int spi_imx_transfer(struct spi_device *spi,
1400 struct spi_transfer *transfer)
1401{
1402 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1403
1404 /* flush rxfifo before transfer */
1405 while (spi_imx->devtype_data->rx_available(spi_imx))
1406 spi_imx->rx(spi_imx);
1407
1408 if (spi_imx->slave_mode)
1409 return spi_imx_pio_transfer_slave(spi, transfer);
1410
1411 if (spi_imx->usedma)
1412 return spi_imx_dma_transfer(spi_imx, transfer);
1413 else
1414 return spi_imx_pio_transfer(spi, transfer);
1415}
1416
1417static int spi_imx_setup(struct spi_device *spi)
1418{
1419 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1420 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1421
1422 if (spi->mode & SPI_NO_CS)
1423 return 0;
1424
1425 if (gpio_is_valid(spi->cs_gpio))
1426 gpio_direction_output(spi->cs_gpio,
1427 spi->mode & SPI_CS_HIGH ? 0 : 1);
1428
1429 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1430
1431 return 0;
1432}
1433
1434static void spi_imx_cleanup(struct spi_device *spi)
1435{
1436}
1437
1438static int
1439spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1440{
1441 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1442 int ret;
1443
1444 ret = clk_enable(spi_imx->clk_per);
1445 if (ret)
1446 return ret;
1447
1448 ret = clk_enable(spi_imx->clk_ipg);
1449 if (ret) {
1450 clk_disable(spi_imx->clk_per);
1451 return ret;
1452 }
1453
1454 return 0;
1455}
1456
1457static int
1458spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1459{
1460 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1461
1462 clk_disable(spi_imx->clk_ipg);
1463 clk_disable(spi_imx->clk_per);
1464 return 0;
1465}
1466
1467static int spi_imx_slave_abort(struct spi_master *master)
1468{
1469 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1470
1471 spi_imx->slave_aborted = true;
1472 complete(&spi_imx->xfer_done);
1473
1474 return 0;
1475}
1476
1477static int spi_imx_probe(struct platform_device *pdev)
1478{
1479 struct device_node *np = pdev->dev.of_node;
1480 const struct of_device_id *of_id =
1481 of_match_device(spi_imx_dt_ids, &pdev->dev);
1482 struct spi_imx_master *mxc_platform_info =
1483 dev_get_platdata(&pdev->dev);
1484 struct spi_master *master;
1485 struct spi_imx_data *spi_imx;
1486 struct resource *res;
1487 int i, ret, irq, spi_drctl;
1488 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1489 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1490 bool slave_mode;
1491
1492 if (!np && !mxc_platform_info) {
1493 dev_err(&pdev->dev, "can't get the platform data\n");
1494 return -EINVAL;
1495 }
1496
1497 slave_mode = devtype_data->has_slavemode &&
1498 of_property_read_bool(np, "spi-slave");
1499 if (slave_mode)
1500 master = spi_alloc_slave(&pdev->dev,
1501 sizeof(struct spi_imx_data));
1502 else
1503 master = spi_alloc_master(&pdev->dev,
1504 sizeof(struct spi_imx_data));
1505 if (!master)
1506 return -ENOMEM;
1507
1508 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1509 if ((ret < 0) || (spi_drctl >= 0x3)) {
1510 /* '11' is reserved */
1511 spi_drctl = 0;
1512 }
1513
1514 platform_set_drvdata(pdev, master);
1515
1516 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1517 master->bus_num = np ? -1 : pdev->id;
1518
1519 spi_imx = spi_master_get_devdata(master);
1520 spi_imx->bitbang.master = master;
1521 spi_imx->dev = &pdev->dev;
1522 spi_imx->slave_mode = slave_mode;
1523
1524 spi_imx->devtype_data = devtype_data;
1525
1526 /* Get number of chip selects, either platform data or OF */
1527 if (mxc_platform_info) {
1528 master->num_chipselect = mxc_platform_info->num_chipselect;
1529 if (mxc_platform_info->chipselect) {
1530 master->cs_gpios = devm_kzalloc(&master->dev,
1531 sizeof(int) * master->num_chipselect, GFP_KERNEL);
1532 if (!master->cs_gpios)
1533 return -ENOMEM;
1534
1535 for (i = 0; i < master->num_chipselect; i++)
1536 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1537 }
1538 } else {
1539 u32 num_cs;
1540
1541 if (!of_property_read_u32(np, "num-cs", &num_cs))
1542 master->num_chipselect = num_cs;
1543 /* If not preset, default value of 1 is used */
1544 }
1545
1546 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1547 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1548 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1549 spi_imx->bitbang.master->setup = spi_imx_setup;
1550 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1551 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1552 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1553 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1554 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1555 | SPI_NO_CS;
1556 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1557 is_imx53_ecspi(spi_imx))
1558 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1559
1560 spi_imx->spi_drctl = spi_drctl;
1561
1562 init_completion(&spi_imx->xfer_done);
1563
1564 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1565 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1566 if (IS_ERR(spi_imx->base)) {
1567 ret = PTR_ERR(spi_imx->base);
1568 goto out_master_put;
1569 }
1570 spi_imx->base_phys = res->start;
1571
1572 irq = platform_get_irq(pdev, 0);
1573 if (irq < 0) {
1574 ret = irq;
1575 goto out_master_put;
1576 }
1577
1578 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1579 dev_name(&pdev->dev), spi_imx);
1580 if (ret) {
1581 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1582 goto out_master_put;
1583 }
1584
1585 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1586 if (IS_ERR(spi_imx->clk_ipg)) {
1587 ret = PTR_ERR(spi_imx->clk_ipg);
1588 goto out_master_put;
1589 }
1590
1591 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1592 if (IS_ERR(spi_imx->clk_per)) {
1593 ret = PTR_ERR(spi_imx->clk_per);
1594 goto out_master_put;
1595 }
1596
1597 ret = clk_prepare_enable(spi_imx->clk_per);
1598 if (ret)
1599 goto out_master_put;
1600
1601 ret = clk_prepare_enable(spi_imx->clk_ipg);
1602 if (ret)
1603 goto out_put_per;
1604
1605 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1606 /*
1607 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1608 * if validated on other chips.
1609 */
1610 if (spi_imx->devtype_data->has_dmamode) {
1611 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1612 if (ret == -EPROBE_DEFER)
1613 goto out_clk_put;
1614
1615 if (ret < 0)
1616 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1617 ret);
1618 }
1619
1620 spi_imx->devtype_data->reset(spi_imx);
1621
1622 spi_imx->devtype_data->intctrl(spi_imx, 0);
1623
1624 master->dev.of_node = pdev->dev.of_node;
1625 ret = spi_bitbang_start(&spi_imx->bitbang);
1626 if (ret) {
1627 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1628 goto out_clk_put;
1629 }
1630
1631 /* Request GPIO CS lines, if any */
1632 if (!spi_imx->slave_mode && master->cs_gpios) {
1633 for (i = 0; i < master->num_chipselect; i++) {
1634 if (!gpio_is_valid(master->cs_gpios[i]))
1635 continue;
1636
1637 ret = devm_gpio_request(&pdev->dev,
1638 master->cs_gpios[i],
1639 DRIVER_NAME);
1640 if (ret) {
1641 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1642 master->cs_gpios[i]);
1643 goto out_spi_bitbang;
1644 }
1645 }
1646 }
1647
1648 dev_info(&pdev->dev, "probed\n");
1649
1650 clk_disable(spi_imx->clk_ipg);
1651 clk_disable(spi_imx->clk_per);
1652 return ret;
1653
1654out_spi_bitbang:
1655 spi_bitbang_stop(&spi_imx->bitbang);
1656out_clk_put:
1657 clk_disable_unprepare(spi_imx->clk_ipg);
1658out_put_per:
1659 clk_disable_unprepare(spi_imx->clk_per);
1660out_master_put:
1661 spi_master_put(master);
1662
1663 return ret;
1664}
1665
1666static int spi_imx_remove(struct platform_device *pdev)
1667{
1668 struct spi_master *master = platform_get_drvdata(pdev);
1669 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1670 int ret;
1671
1672 spi_bitbang_stop(&spi_imx->bitbang);
1673
1674 ret = clk_enable(spi_imx->clk_per);
1675 if (ret)
1676 return ret;
1677
1678 ret = clk_enable(spi_imx->clk_ipg);
1679 if (ret) {
1680 clk_disable(spi_imx->clk_per);
1681 return ret;
1682 }
1683
1684 writel(0, spi_imx->base + MXC_CSPICTRL);
1685 clk_disable_unprepare(spi_imx->clk_ipg);
1686 clk_disable_unprepare(spi_imx->clk_per);
1687 spi_imx_sdma_exit(spi_imx);
1688 spi_master_put(master);
1689
1690 return 0;
1691}
1692
1693static struct platform_driver spi_imx_driver = {
1694 .driver = {
1695 .name = DRIVER_NAME,
1696 .of_match_table = spi_imx_dt_ids,
1697 },
1698 .id_table = spi_imx_devtype,
1699 .probe = spi_imx_probe,
1700 .remove = spi_imx_remove,
1701};
1702module_platform_driver(spi_imx_driver);
1703
1704MODULE_DESCRIPTION("SPI Controller driver");
1705MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1706MODULE_LICENSE("GPL");
1707MODULE_ALIAS("platform:" DRIVER_NAME);