Loading...
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 *
5 *
6 * Name: mpi2_ioc.h
7 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
8 * Creation Date: October 11, 2006
9 *
10 * mpi2_ioc.h Version: 02.00.37
11 *
12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13 * prefix are for use only on MPI v2.5 products, and must not be used
14 * with MPI v2.0 products. Unless otherwise noted, names beginning with
15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
16 *
17 * Version History
18 * ---------------
19 *
20 * Date Version Description
21 * -------- -------- ------------------------------------------------------
22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
23 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
24 * MaxTargets.
25 * Added TotalImageSize field to FWDownload Request.
26 * Added reserved words to FWUpload Request.
27 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
28 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
29 * request and replaced it with
30 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
31 * Replaced the MinReplyQueueDepth field of the IOCFacts
32 * reply with MaxReplyDescriptorPostQueueDepth.
33 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
34 * depth for the Reply Descriptor Post Queue.
35 * Added SASAddress field to Initiator Device Table
36 * Overflow Event data.
37 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
38 * for SAS Initiator Device Status Change Event data.
39 * Modified Reason Code defines for SAS Topology Change
40 * List Event data, including adding a bit for PHY Vacant
41 * status, and adding a mask for the Reason Code.
42 * Added define for
43 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
44 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
45 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
46 * the IOCFacts Reply.
47 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
48 * Moved MPI2_VERSION_UNION to mpi2.h.
49 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
50 * instead of enables, and added SASBroadcastPrimitiveMasks
51 * field.
52 * Added Log Entry Added Event and related structure.
53 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
54 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
55 * Added MaxVolumes and MaxPersistentEntries fields to
56 * IOCFacts reply.
57 * Added ProtocalFlags and IOCCapabilities fields to
58 * MPI2_FW_IMAGE_HEADER.
59 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
60 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
61 * a U16 (from a U32).
62 * Removed extra 's' from EventMasks name.
63 * 06-27-08 02.00.08 Fixed an offset in a comment.
64 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
65 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
66 * renamed MinReplyFrameSize to ReplyFrameSize.
67 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
68 * Added two new RAIDOperation values for Integrated RAID
69 * Operations Status Event data.
70 * Added four new IR Configuration Change List Event data
71 * ReasonCode values.
72 * Added two new ReasonCode defines for SAS Device Status
73 * Change Event data.
74 * Added three new DiscoveryStatus bits for the SAS
75 * Discovery event data.
76 * Added Multiplexing Status Change bit to the PhyStatus
77 * field of the SAS Topology Change List event data.
78 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
79 * BootFlags are now product-specific.
80 * Added defines for the indivdual signature bytes
81 * for MPI2_INIT_IMAGE_FOOTER.
82 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
83 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
84 * define.
85 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
86 * define.
87 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
88 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
89 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
90 * Added two new reason codes for SAS Device Status Change
91 * Event.
92 * Added new event: SAS PHY Counter.
93 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
94 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
95 * Added new product id family for 2208.
96 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
97 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
98 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
99 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
100 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
101 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
102 * Added Host Based Discovery Phy Event data.
103 * Added defines for ProductID Product field
104 * (MPI2_FW_HEADER_PID_).
105 * Modified values for SAS ProductID Family
106 * (MPI2_FW_HEADER_PID_FAMILY_).
107 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
108 * Added PowerManagementControl Request structures and
109 * defines.
110 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
111 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
112 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
113 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
114 * SASNotifyPrimitiveMasks field to
115 * MPI2_EVENT_NOTIFICATION_REQUEST.
116 * Added Temperature Threshold Event.
117 * Added Host Message Event.
118 * Added Send Host Message request and reply.
119 * 05-25-11 02.00.18 For Extended Image Header, added
120 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
121 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
122 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
123 * 08-24-11 02.00.19 Added PhysicalPort field to
124 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
125 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
126 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.
127 * 03-29-12 02.00.21 Added a product specific range to event values.
128 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
129 * Added ElapsedSeconds field to
130 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
131 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
132 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
133 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
134 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
135 * Added Encrypted Hash Extended Image.
136 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
137 * 11-18-14 02.00.25 Updated copyright information.
138 * 03-16-15 02.00.26 Updated for MPI v2.6.
139 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
140 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
141 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
142 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
143 * Added MPI26_CTRL_OP_SHUTDOWN.
144 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines.
145 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.
146 * Added ConigurationFlags field to IOCInit message to
147 * support NVMe SGL format control.
148 * Added PCIe SRIOV support.
149 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support.
150 * Added PCIe 4 16.0 GT/sec speec support.
151 * Removed AHCI support.
152 * Removed SOP support.
153 * 07-01-16 02.00.29 Added Archclass for 4008 product.
154 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED
155 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload
156 * Request Message.
157 * Added new defines for the ImageType field of FWUpload
158 * Request Message.
159 * Added new values for the RegionType field in the Layout
160 * Data sections of the FLASH Layout Extended Image Data.
161 * Added new defines for the ReasonCode field of
162 * Active Cable Exception Event.
163 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and
164 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.
165 * 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and
166 * MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.
167 * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.
168 * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related
169 * defines for the ReasonCode field.
170 * 06-13-17 02.00.33 Added MPI2_FW_DOWNLOAD_ITYPE_CPLD.
171 * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED
172 * to the ReasonCode field in PCIe Device Status Change
173 * Event Data.
174 * 07-22-18 02.00.35 Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC.
175 * Moved FW image definitions ionto new mpi2_image,h
176 * 08-14-18 02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
177 * 09-07-18 02.00.37 Added MPI26_EVENT_PCIE_TOPO_PI_16_LANES
178 * 10-02-19 02.00.38 Added MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE
179 * Added MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED
180 * Added MPI2_FW_DOWNLOAD_ITYPE_COREDUMP
181 * Added MPI2_FW_UPLOAD_ITYPE_COREDUMP
182 * --------------------------------------------------------------------------
183 */
184
185#ifndef MPI2_IOC_H
186#define MPI2_IOC_H
187
188/*****************************************************************************
189*
190* IOC Messages
191*
192*****************************************************************************/
193
194/****************************************************************************
195* IOCInit message
196****************************************************************************/
197
198/*IOCInit Request message */
199typedef struct _MPI2_IOC_INIT_REQUEST {
200 U8 WhoInit; /*0x00 */
201 U8 Reserved1; /*0x01 */
202 U8 ChainOffset; /*0x02 */
203 U8 Function; /*0x03 */
204 U16 Reserved2; /*0x04 */
205 U8 Reserved3; /*0x06 */
206 U8 MsgFlags; /*0x07 */
207 U8 VP_ID; /*0x08 */
208 U8 VF_ID; /*0x09 */
209 U16 Reserved4; /*0x0A */
210 U16 MsgVersion; /*0x0C */
211 U16 HeaderVersion; /*0x0E */
212 U32 Reserved5; /*0x10 */
213 U16 ConfigurationFlags; /* 0x14 */
214 U8 HostPageSize; /*0x16 */
215 U8 HostMSIxVectors; /*0x17 */
216 U16 Reserved8; /*0x18 */
217 U16 SystemRequestFrameSize; /*0x1A */
218 U16 ReplyDescriptorPostQueueDepth; /*0x1C */
219 U16 ReplyFreeQueueDepth; /*0x1E */
220 U32 SenseBufferAddressHigh; /*0x20 */
221 U32 SystemReplyAddressHigh; /*0x24 */
222 U64 SystemRequestFrameBaseAddress; /*0x28 */
223 U64 ReplyDescriptorPostQueueAddress; /*0x30 */
224 U64 ReplyFreeQueueAddress; /*0x38 */
225 U64 TimeStamp; /*0x40 */
226} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
227 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
228
229/*WhoInit values */
230#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
231#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
232#define MPI2_WHOINIT_ROM_BIOS (0x02)
233#define MPI2_WHOINIT_PCI_PEER (0x03)
234#define MPI2_WHOINIT_HOST_DRIVER (0x04)
235#define MPI2_WHOINIT_MANUFACTURER (0x05)
236
237/* MsgFlags */
238#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
239
240
241/*MsgVersion */
242#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
243#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
244#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
245#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
246
247/*HeaderVersion */
248#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
249#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
250#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
251#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
252
253/*ConfigurationFlags */
254#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)
255#define MPI26_IOCINIT_CFGFLAGS_COREDUMP_ENABLE (0x0002)
256
257/*minimum depth for a Reply Descriptor Post Queue */
258#define MPI2_RDPQ_DEPTH_MIN (16)
259
260/* Reply Descriptor Post Queue Array Entry */
261typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
262 U64 RDPQBaseAddress; /* 0x00 */
263 U32 Reserved1; /* 0x08 */
264 U32 Reserved2; /* 0x0C */
265} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
266*PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
267Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
268
269
270/*IOCInit Reply message */
271typedef struct _MPI2_IOC_INIT_REPLY {
272 U8 WhoInit; /*0x00 */
273 U8 Reserved1; /*0x01 */
274 U8 MsgLength; /*0x02 */
275 U8 Function; /*0x03 */
276 U16 Reserved2; /*0x04 */
277 U8 Reserved3; /*0x06 */
278 U8 MsgFlags; /*0x07 */
279 U8 VP_ID; /*0x08 */
280 U8 VF_ID; /*0x09 */
281 U16 Reserved4; /*0x0A */
282 U16 Reserved5; /*0x0C */
283 U16 IOCStatus; /*0x0E */
284 U32 IOCLogInfo; /*0x10 */
285} MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
286 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
287
288/****************************************************************************
289* IOCFacts message
290****************************************************************************/
291
292/*IOCFacts Request message */
293typedef struct _MPI2_IOC_FACTS_REQUEST {
294 U16 Reserved1; /*0x00 */
295 U8 ChainOffset; /*0x02 */
296 U8 Function; /*0x03 */
297 U16 Reserved2; /*0x04 */
298 U8 Reserved3; /*0x06 */
299 U8 MsgFlags; /*0x07 */
300 U8 VP_ID; /*0x08 */
301 U8 VF_ID; /*0x09 */
302 U16 Reserved4; /*0x0A */
303} MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
304 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
305
306/*IOCFacts Reply message */
307typedef struct _MPI2_IOC_FACTS_REPLY {
308 U16 MsgVersion; /*0x00 */
309 U8 MsgLength; /*0x02 */
310 U8 Function; /*0x03 */
311 U16 HeaderVersion; /*0x04 */
312 U8 IOCNumber; /*0x06 */
313 U8 MsgFlags; /*0x07 */
314 U8 VP_ID; /*0x08 */
315 U8 VF_ID; /*0x09 */
316 U16 Reserved1; /*0x0A */
317 U16 IOCExceptions; /*0x0C */
318 U16 IOCStatus; /*0x0E */
319 U32 IOCLogInfo; /*0x10 */
320 U8 MaxChainDepth; /*0x14 */
321 U8 WhoInit; /*0x15 */
322 U8 NumberOfPorts; /*0x16 */
323 U8 MaxMSIxVectors; /*0x17 */
324 U16 RequestCredit; /*0x18 */
325 U16 ProductID; /*0x1A */
326 U32 IOCCapabilities; /*0x1C */
327 MPI2_VERSION_UNION FWVersion; /*0x20 */
328 U16 IOCRequestFrameSize; /*0x24 */
329 U16 IOCMaxChainSegmentSize; /*0x26 */
330 U16 MaxInitiators; /*0x28 */
331 U16 MaxTargets; /*0x2A */
332 U16 MaxSasExpanders; /*0x2C */
333 U16 MaxEnclosures; /*0x2E */
334 U16 ProtocolFlags; /*0x30 */
335 U16 HighPriorityCredit; /*0x32 */
336 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */
337 U8 ReplyFrameSize; /*0x36 */
338 U8 MaxVolumes; /*0x37 */
339 U16 MaxDevHandle; /*0x38 */
340 U16 MaxPersistentEntries; /*0x3A */
341 U16 MinDevHandle; /*0x3C */
342 U8 CurrentHostPageSize; /* 0x3E */
343 U8 Reserved4; /* 0x3F */
344 U8 SGEModifierMask; /*0x40 */
345 U8 SGEModifierValue; /*0x41 */
346 U8 SGEModifierShift; /*0x42 */
347 U8 Reserved5; /*0x43 */
348} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
349 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
350
351/*MsgVersion */
352#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
353#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
354#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
355#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
356
357/*HeaderVersion */
358#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
359#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
360#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
361#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
362
363/*IOCExceptions */
364#define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400)
365#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
366#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
367
368#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
369#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
370#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
371#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
372#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
373
374#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
375#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
376#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
377#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
378#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
379
380/*defines for WhoInit field are after the IOCInit Request */
381
382/*ProductID field uses MPI2_FW_HEADER_PID_ */
383
384/*IOCCapabilities */
385#define MPI26_IOCFACTS_CAPABILITY_COREDUMP_ENABLED (0x00200000)
386#define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000)
387#define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)
388#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
389#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
390#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
391#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
392#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
393#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
394#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
395#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
396#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
397#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
398#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
399#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
400#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
401#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
402#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
403
404/*ProtocolFlags */
405#define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008)
406#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
407#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
408
409/****************************************************************************
410* PortFacts message
411****************************************************************************/
412
413/*PortFacts Request message */
414typedef struct _MPI2_PORT_FACTS_REQUEST {
415 U16 Reserved1; /*0x00 */
416 U8 ChainOffset; /*0x02 */
417 U8 Function; /*0x03 */
418 U16 Reserved2; /*0x04 */
419 U8 PortNumber; /*0x06 */
420 U8 MsgFlags; /*0x07 */
421 U8 VP_ID; /*0x08 */
422 U8 VF_ID; /*0x09 */
423 U16 Reserved3; /*0x0A */
424} MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
425 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
426
427/*PortFacts Reply message */
428typedef struct _MPI2_PORT_FACTS_REPLY {
429 U16 Reserved1; /*0x00 */
430 U8 MsgLength; /*0x02 */
431 U8 Function; /*0x03 */
432 U16 Reserved2; /*0x04 */
433 U8 PortNumber; /*0x06 */
434 U8 MsgFlags; /*0x07 */
435 U8 VP_ID; /*0x08 */
436 U8 VF_ID; /*0x09 */
437 U16 Reserved3; /*0x0A */
438 U16 Reserved4; /*0x0C */
439 U16 IOCStatus; /*0x0E */
440 U32 IOCLogInfo; /*0x10 */
441 U8 Reserved5; /*0x14 */
442 U8 PortType; /*0x15 */
443 U16 Reserved6; /*0x16 */
444 U16 MaxPostedCmdBuffers; /*0x18 */
445 U16 Reserved7; /*0x1A */
446} MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
447 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
448
449/*PortType values */
450#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
451#define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
452#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
453#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
454#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
455#define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40)
456
457
458/****************************************************************************
459* PortEnable message
460****************************************************************************/
461
462/*PortEnable Request message */
463typedef struct _MPI2_PORT_ENABLE_REQUEST {
464 U16 Reserved1; /*0x00 */
465 U8 ChainOffset; /*0x02 */
466 U8 Function; /*0x03 */
467 U8 Reserved2; /*0x04 */
468 U8 PortFlags; /*0x05 */
469 U8 Reserved3; /*0x06 */
470 U8 MsgFlags; /*0x07 */
471 U8 VP_ID; /*0x08 */
472 U8 VF_ID; /*0x09 */
473 U16 Reserved4; /*0x0A */
474} MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
475 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
476
477/*PortEnable Reply message */
478typedef struct _MPI2_PORT_ENABLE_REPLY {
479 U16 Reserved1; /*0x00 */
480 U8 MsgLength; /*0x02 */
481 U8 Function; /*0x03 */
482 U8 Reserved2; /*0x04 */
483 U8 PortFlags; /*0x05 */
484 U8 Reserved3; /*0x06 */
485 U8 MsgFlags; /*0x07 */
486 U8 VP_ID; /*0x08 */
487 U8 VF_ID; /*0x09 */
488 U16 Reserved4; /*0x0A */
489 U16 Reserved5; /*0x0C */
490 U16 IOCStatus; /*0x0E */
491 U32 IOCLogInfo; /*0x10 */
492} MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
493 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
494
495/****************************************************************************
496* EventNotification message
497****************************************************************************/
498
499/*EventNotification Request message */
500#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
501
502typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
503 U16 Reserved1; /*0x00 */
504 U8 ChainOffset; /*0x02 */
505 U8 Function; /*0x03 */
506 U16 Reserved2; /*0x04 */
507 U8 Reserved3; /*0x06 */
508 U8 MsgFlags; /*0x07 */
509 U8 VP_ID; /*0x08 */
510 U8 VF_ID; /*0x09 */
511 U16 Reserved4; /*0x0A */
512 U32 Reserved5; /*0x0C */
513 U32 Reserved6; /*0x10 */
514 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */
515 U16 SASBroadcastPrimitiveMasks; /*0x24 */
516 U16 SASNotifyPrimitiveMasks; /*0x26 */
517 U32 Reserved8; /*0x28 */
518} MPI2_EVENT_NOTIFICATION_REQUEST,
519 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
520 Mpi2EventNotificationRequest_t,
521 *pMpi2EventNotificationRequest_t;
522
523/*EventNotification Reply message */
524typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
525 U16 EventDataLength; /*0x00 */
526 U8 MsgLength; /*0x02 */
527 U8 Function; /*0x03 */
528 U16 Reserved1; /*0x04 */
529 U8 AckRequired; /*0x06 */
530 U8 MsgFlags; /*0x07 */
531 U8 VP_ID; /*0x08 */
532 U8 VF_ID; /*0x09 */
533 U16 Reserved2; /*0x0A */
534 U16 Reserved3; /*0x0C */
535 U16 IOCStatus; /*0x0E */
536 U32 IOCLogInfo; /*0x10 */
537 U16 Event; /*0x14 */
538 U16 Reserved4; /*0x16 */
539 U32 EventContext; /*0x18 */
540 U32 EventData[]; /*0x1C */
541} MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
542 Mpi2EventNotificationReply_t,
543 *pMpi2EventNotificationReply_t;
544
545/*AckRequired */
546#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
547#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
548
549/*Event */
550#define MPI2_EVENT_LOG_DATA (0x0001)
551#define MPI2_EVENT_STATE_CHANGE (0x0002)
552#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
553#define MPI2_EVENT_EVENT_CHANGE (0x000A)
554#define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */
555#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
556#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
557#define MPI2_EVENT_SAS_DISCOVERY (0x0016)
558#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
559#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
560#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
561#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
562#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
563#define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D)
564#define MPI2_EVENT_IR_VOLUME (0x001E)
565#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
566#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
567#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
568#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
569#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
570#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
571#define MPI2_EVENT_SAS_QUIESCE (0x0025)
572#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
573#define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
574#define MPI2_EVENT_HOST_MESSAGE (0x0028)
575#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
576#define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030)
577#define MPI2_EVENT_PCIE_ENUMERATION (0x0031)
578#define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032)
579#define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033)
580#define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034)
581#define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035)
582#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
583#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
584
585/*Log Entry Added Event data */
586
587/*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
588#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
589
590typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
591 U64 TimeStamp; /*0x00 */
592 U32 Reserved1; /*0x08 */
593 U16 LogSequence; /*0x0C */
594 U16 LogEntryQualifier; /*0x0E */
595 U8 VP_ID; /*0x10 */
596 U8 VF_ID; /*0x11 */
597 U16 Reserved2; /*0x12 */
598 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */
599} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
600 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
601 Mpi2EventDataLogEntryAdded_t,
602 *pMpi2EventDataLogEntryAdded_t;
603
604/*GPIO Interrupt Event data */
605
606typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
607 U8 GPIONum; /*0x00 */
608 U8 Reserved1; /*0x01 */
609 U16 Reserved2; /*0x02 */
610} MPI2_EVENT_DATA_GPIO_INTERRUPT,
611 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
612 Mpi2EventDataGpioInterrupt_t,
613 *pMpi2EventDataGpioInterrupt_t;
614
615/*Temperature Threshold Event data */
616
617typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
618 U16 Status; /*0x00 */
619 U8 SensorNum; /*0x02 */
620 U8 Reserved1; /*0x03 */
621 U16 CurrentTemperature; /*0x04 */
622 U16 Reserved2; /*0x06 */
623 U32 Reserved3; /*0x08 */
624 U32 Reserved4; /*0x0C */
625} MPI2_EVENT_DATA_TEMPERATURE,
626 *PTR_MPI2_EVENT_DATA_TEMPERATURE,
627 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
628
629/*Temperature Threshold Event data Status bits */
630#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
631#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
632#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
633#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
634
635/*Host Message Event data */
636
637typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
638 U8 SourceVF_ID; /*0x00 */
639 U8 Reserved1; /*0x01 */
640 U16 Reserved2; /*0x02 */
641 U32 Reserved3; /*0x04 */
642 U32 HostData[]; /*0x08 */
643} MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
644 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
645
646/*Power Performance Change Event data */
647
648typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
649 U8 CurrentPowerMode; /*0x00 */
650 U8 PreviousPowerMode; /*0x01 */
651 U16 Reserved1; /*0x02 */
652} MPI2_EVENT_DATA_POWER_PERF_CHANGE,
653 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
654 Mpi2EventDataPowerPerfChange_t,
655 *pMpi2EventDataPowerPerfChange_t;
656
657/*defines for CurrentPowerMode and PreviousPowerMode fields */
658#define MPI2_EVENT_PM_INIT_MASK (0xC0)
659#define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)
660#define MPI2_EVENT_PM_INIT_HOST (0x40)
661#define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)
662#define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)
663
664#define MPI2_EVENT_PM_MODE_MASK (0x07)
665#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
666#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
667#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
668#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
669#define MPI2_EVENT_PM_MODE_STANDBY (0x06)
670
671/* Active Cable Exception Event data */
672
673typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT {
674 U32 ActiveCablePowerRequirement; /* 0x00 */
675 U8 ReasonCode; /* 0x04 */
676 U8 ReceptacleID; /* 0x05 */
677 U16 Reserved1; /* 0x06 */
678} MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
679 *PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
680 Mpi25EventDataActiveCableExcept_t,
681 *pMpi25EventDataActiveCableExcept_t,
682 MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
683 *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
684 Mpi26EventDataActiveCableExcept_t,
685 *pMpi26EventDataActiveCableExcept_t;
686
687/*MPI2.5 defines for the ReasonCode field */
688#define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
689#define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01)
690#define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
691
692/* defines for ReasonCode field */
693#define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
694#define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01)
695#define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
696
697/*Hard Reset Received Event data */
698
699typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
700 U8 Reserved1; /*0x00 */
701 U8 Port; /*0x01 */
702 U16 Reserved2; /*0x02 */
703} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
704 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
705 Mpi2EventDataHardResetReceived_t,
706 *pMpi2EventDataHardResetReceived_t;
707
708/*Task Set Full Event data */
709/* this event is obsolete */
710
711typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
712 U16 DevHandle; /*0x00 */
713 U16 CurrentDepth; /*0x02 */
714} MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
715 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
716
717/*SAS Device Status Change Event data */
718
719typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
720 U16 TaskTag; /*0x00 */
721 U8 ReasonCode; /*0x02 */
722 U8 PhysicalPort; /*0x03 */
723 U8 ASC; /*0x04 */
724 U8 ASCQ; /*0x05 */
725 U16 DevHandle; /*0x06 */
726 U32 Reserved2; /*0x08 */
727 U64 SASAddress; /*0x0C */
728 U8 LUN[8]; /*0x14 */
729} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
730 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
731 Mpi2EventDataSasDeviceStatusChange_t,
732 *pMpi2EventDataSasDeviceStatusChange_t;
733
734/*SAS Device Status Change Event data ReasonCode values */
735#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
736#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
737#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
738#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
739#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
740#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
741#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
742#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
743#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
744#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
745#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
746#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
747#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
748
749/*Integrated RAID Operation Status Event data */
750
751typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
752 U16 VolDevHandle; /*0x00 */
753 U16 Reserved1; /*0x02 */
754 U8 RAIDOperation; /*0x04 */
755 U8 PercentComplete; /*0x05 */
756 U16 Reserved2; /*0x06 */
757 U32 ElapsedSeconds; /*0x08 */
758} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
759 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
760 Mpi2EventDataIrOperationStatus_t,
761 *pMpi2EventDataIrOperationStatus_t;
762
763/*Integrated RAID Operation Status Event data RAIDOperation values */
764#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
765#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
766#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
767#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
768#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
769
770/*Integrated RAID Volume Event data */
771
772typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
773 U16 VolDevHandle; /*0x00 */
774 U8 ReasonCode; /*0x02 */
775 U8 Reserved1; /*0x03 */
776 U32 NewValue; /*0x04 */
777 U32 PreviousValue; /*0x08 */
778} MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
779 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
780
781/*Integrated RAID Volume Event data ReasonCode values */
782#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
783#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
784#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
785
786/*Integrated RAID Physical Disk Event data */
787
788typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
789 U16 Reserved1; /*0x00 */
790 U8 ReasonCode; /*0x02 */
791 U8 PhysDiskNum; /*0x03 */
792 U16 PhysDiskDevHandle; /*0x04 */
793 U16 Reserved2; /*0x06 */
794 U16 Slot; /*0x08 */
795 U16 EnclosureHandle; /*0x0A */
796 U32 NewValue; /*0x0C */
797 U32 PreviousValue; /*0x10 */
798} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
799 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
800 Mpi2EventDataIrPhysicalDisk_t,
801 *pMpi2EventDataIrPhysicalDisk_t;
802
803/*Integrated RAID Physical Disk Event data ReasonCode values */
804#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
805#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
806#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
807
808/*Integrated RAID Configuration Change List Event data */
809
810/*
811 *Host code (drivers, BIOS, utilities, etc.) should check NumElements at
812 *runtime before using ConfigElement[].
813 */
814
815typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
816 U16 ElementFlags; /*0x00 */
817 U16 VolDevHandle; /*0x02 */
818 U8 ReasonCode; /*0x04 */
819 U8 PhysDiskNum; /*0x05 */
820 U16 PhysDiskDevHandle; /*0x06 */
821} MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
822 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
823
824/*IR Configuration Change List Event data ElementFlags values */
825#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
826#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
827#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
828#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
829
830/*IR Configuration Change List Event data ReasonCode values */
831#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
832#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
833#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
834#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
835#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
836#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
837#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
838#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
839#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
840
841typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
842 U8 NumElements; /*0x00 */
843 U8 Reserved1; /*0x01 */
844 U8 Reserved2; /*0x02 */
845 U8 ConfigNum; /*0x03 */
846 U32 Flags; /*0x04 */
847 MPI2_EVENT_IR_CONFIG_ELEMENT
848 ConfigElement[];/*0x08 */
849} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
850 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
851 Mpi2EventDataIrConfigChangeList_t,
852 *pMpi2EventDataIrConfigChangeList_t;
853
854/*IR Configuration Change List Event data Flags values */
855#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
856
857/*SAS Discovery Event data */
858
859typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
860 U8 Flags; /*0x00 */
861 U8 ReasonCode; /*0x01 */
862 U8 PhysicalPort; /*0x02 */
863 U8 Reserved1; /*0x03 */
864 U32 DiscoveryStatus; /*0x04 */
865} MPI2_EVENT_DATA_SAS_DISCOVERY,
866 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
867 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
868
869/*SAS Discovery Event data Flags values */
870#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
871#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
872
873/*SAS Discovery Event data ReasonCode values */
874#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
875#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
876
877/*SAS Discovery Event data DiscoveryStatus values */
878#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
879#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
880#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
881#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
882#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
883#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
884#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
885#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
886#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
887#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
888#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
889#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
890#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
891#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
892#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
893#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
894#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
895#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
896#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
897#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
898
899/*SAS Broadcast Primitive Event data */
900
901typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
902 U8 PhyNum; /*0x00 */
903 U8 Port; /*0x01 */
904 U8 PortWidth; /*0x02 */
905 U8 Primitive; /*0x03 */
906} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
907 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
908 Mpi2EventDataSasBroadcastPrimitive_t,
909 *pMpi2EventDataSasBroadcastPrimitive_t;
910
911/*defines for the Primitive field */
912#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
913#define MPI2_EVENT_PRIMITIVE_SES (0x02)
914#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
915#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
916#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
917#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
918#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
919#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
920
921/*SAS Notify Primitive Event data */
922
923typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
924 U8 PhyNum; /*0x00 */
925 U8 Port; /*0x01 */
926 U8 Reserved1; /*0x02 */
927 U8 Primitive; /*0x03 */
928} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
929 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
930 Mpi2EventDataSasNotifyPrimitive_t,
931 *pMpi2EventDataSasNotifyPrimitive_t;
932
933/*defines for the Primitive field */
934#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
935#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
936#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
937#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
938
939/*SAS Initiator Device Status Change Event data */
940
941typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
942 U8 ReasonCode; /*0x00 */
943 U8 PhysicalPort; /*0x01 */
944 U16 DevHandle; /*0x02 */
945 U64 SASAddress; /*0x04 */
946} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
947 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
948 Mpi2EventDataSasInitDevStatusChange_t,
949 *pMpi2EventDataSasInitDevStatusChange_t;
950
951/*SAS Initiator Device Status Change event ReasonCode values */
952#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
953#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
954
955/*SAS Initiator Device Table Overflow Event data */
956
957typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
958 U16 MaxInit; /*0x00 */
959 U16 CurrentInit; /*0x02 */
960 U64 SASAddress; /*0x04 */
961} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
962 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
963 Mpi2EventDataSasInitTableOverflow_t,
964 *pMpi2EventDataSasInitTableOverflow_t;
965
966/*SAS Topology Change List Event data */
967
968/*
969 *Host code (drivers, BIOS, utilities, etc.) should check NumEntries at
970 *runtime before using PHY[].
971 */
972
973typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
974 U16 AttachedDevHandle; /*0x00 */
975 U8 LinkRate; /*0x02 */
976 U8 PhyStatus; /*0x03 */
977} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
978 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
979
980typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
981 U16 EnclosureHandle; /*0x00 */
982 U16 ExpanderDevHandle; /*0x02 */
983 U8 NumPhys; /*0x04 */
984 U8 Reserved1; /*0x05 */
985 U16 Reserved2; /*0x06 */
986 U8 NumEntries; /*0x08 */
987 U8 StartPhyNum; /*0x09 */
988 U8 ExpStatus; /*0x0A */
989 U8 PhysicalPort; /*0x0B */
990 MPI2_EVENT_SAS_TOPO_PHY_ENTRY
991 PHY[]; /*0x0C */
992} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
993 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
994 Mpi2EventDataSasTopologyChangeList_t,
995 *pMpi2EventDataSasTopologyChangeList_t;
996
997/*values for the ExpStatus field */
998#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
999#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
1000#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
1001#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
1002#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
1003
1004/*defines for the LinkRate field */
1005#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
1006#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
1007#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
1008#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
1009
1010#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
1011#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
1012#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
1013#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
1014#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
1015#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
1016#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
1017#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
1018#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
1019#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
1020#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
1021#define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C)
1022
1023/*values for the PhyStatus field */
1024#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
1025#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
1026/*values for the PhyStatus ReasonCode sub-field */
1027#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
1028#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
1029#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
1030#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
1031#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
1032#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
1033
1034/*SAS Enclosure Device Status Change Event data */
1035
1036typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
1037 U16 EnclosureHandle; /*0x00 */
1038 U8 ReasonCode; /*0x02 */
1039 U8 PhysicalPort; /*0x03 */
1040 U64 EnclosureLogicalID; /*0x04 */
1041 U16 NumSlots; /*0x0C */
1042 U16 StartSlot; /*0x0E */
1043 U32 PhyBits; /*0x10 */
1044} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1045 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1046 Mpi2EventDataSasEnclDevStatusChange_t,
1047 *pMpi2EventDataSasEnclDevStatusChange_t,
1048 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1049 *PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1050 Mpi26EventDataEnclDevStatusChange_t,
1051 *pMpi26EventDataEnclDevStatusChange_t;
1052
1053/*SAS Enclosure Device Status Change event ReasonCode values */
1054#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
1055#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
1056
1057/*Enclosure Device Status Change event ReasonCode values */
1058#define MPI26_EVENT_ENCL_RC_ADDED (0x01)
1059#define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02)
1060
1061
1062typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR {
1063 U16 DevHandle; /*0x00 */
1064 U8 ReasonCode; /*0x02 */
1065 U8 PhysicalPort; /*0x03 */
1066 U32 Reserved1[2]; /*0x04 */
1067 U64 SASAddress; /*0x0C */
1068 U32 Reserved2[2]; /*0x14 */
1069} MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1070 *PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1071 Mpi25EventDataSasDeviceDiscoveryError_t,
1072 *pMpi25EventDataSasDeviceDiscoveryError_t;
1073
1074/*SAS Device Discovery Error Event data ReasonCode values */
1075#define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01)
1076#define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02)
1077
1078/*SAS PHY Counter Event data */
1079
1080typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
1081 U64 TimeStamp; /*0x00 */
1082 U32 Reserved1; /*0x08 */
1083 U8 PhyEventCode; /*0x0C */
1084 U8 PhyNum; /*0x0D */
1085 U16 Reserved2; /*0x0E */
1086 U32 PhyEventInfo; /*0x10 */
1087 U8 CounterType; /*0x14 */
1088 U8 ThresholdWindow; /*0x15 */
1089 U8 TimeUnits; /*0x16 */
1090 U8 Reserved3; /*0x17 */
1091 U32 EventThreshold; /*0x18 */
1092 U16 ThresholdFlags; /*0x1C */
1093 U16 Reserved4; /*0x1E */
1094} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1095 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1096 Mpi2EventDataSasPhyCounter_t,
1097 *pMpi2EventDataSasPhyCounter_t;
1098
1099/*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
1100 *for the PhyEventCode field */
1101
1102/*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
1103 *for the CounterType field */
1104
1105/*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
1106 *for the TimeUnits field */
1107
1108/*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
1109 *for the ThresholdFlags field */
1110
1111/*SAS Quiesce Event data */
1112
1113typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1114 U8 ReasonCode; /*0x00 */
1115 U8 Reserved1; /*0x01 */
1116 U16 Reserved2; /*0x02 */
1117 U32 Reserved3; /*0x04 */
1118} MPI2_EVENT_DATA_SAS_QUIESCE,
1119 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1120 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
1121
1122/*SAS Quiesce Event data ReasonCode values */
1123#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
1124#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
1125
1126/*Host Based Discovery Phy Event data */
1127
1128typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1129 U8 Flags; /*0x00 */
1130 U8 NegotiatedLinkRate; /*0x01 */
1131 U8 PhyNum; /*0x02 */
1132 U8 PhysicalPort; /*0x03 */
1133 U32 Reserved1; /*0x04 */
1134 U8 InitialFrame[28]; /*0x08 */
1135} MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1136 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1137
1138/*values for the Flags field */
1139#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1140#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1141
1142/*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1143 *for the NegotiatedLinkRate field */
1144
1145typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1146 MPI2_EVENT_HBD_PHY_SAS Sas;
1147} MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1148 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1149
1150typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1151 U8 DescriptorType; /*0x00 */
1152 U8 Reserved1; /*0x01 */
1153 U16 Reserved2; /*0x02 */
1154 U32 Reserved3; /*0x04 */
1155 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */
1156} MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1157 Mpi2EventDataHbdPhy_t,
1158 *pMpi2EventDataMpi2EventDataHbdPhy_t;
1159
1160/*values for the DescriptorType field */
1161#define MPI2_EVENT_HBD_DT_SAS (0x01)
1162
1163
1164/*PCIe Device Status Change Event data (MPI v2.6 and later) */
1165
1166typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE {
1167 U16 TaskTag; /*0x00 */
1168 U8 ReasonCode; /*0x02 */
1169 U8 PhysicalPort; /*0x03 */
1170 U8 ASC; /*0x04 */
1171 U8 ASCQ; /*0x05 */
1172 U16 DevHandle; /*0x06 */
1173 U32 Reserved2; /*0x08 */
1174 U64 WWID; /*0x0C */
1175 U8 LUN[8]; /*0x14 */
1176} MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1177 *PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1178 Mpi26EventDataPCIeDeviceStatusChange_t,
1179 *pMpi26EventDataPCIeDeviceStatusChange_t;
1180
1181/*PCIe Device Status Change Event data ReasonCode values */
1182#define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05)
1183#define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07)
1184#define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
1185#define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
1186#define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
1187#define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
1188#define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
1189#define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
1190#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
1191#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
1192#define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10)
1193#define MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED (0x11)
1194
1195
1196/*PCIe Enumeration Event data (MPI v2.6 and later) */
1197
1198typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION {
1199 U8 Flags; /*0x00 */
1200 U8 ReasonCode; /*0x01 */
1201 U8 PhysicalPort; /*0x02 */
1202 U8 Reserved1; /*0x03 */
1203 U32 EnumerationStatus; /*0x04 */
1204} MPI26_EVENT_DATA_PCIE_ENUMERATION,
1205 *PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,
1206 Mpi26EventDataPCIeEnumeration_t,
1207 *pMpi26EventDataPCIeEnumeration_t;
1208
1209/*PCIe Enumeration Event data Flags values */
1210#define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02)
1211#define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01)
1212
1213/*PCIe Enumeration Event data ReasonCode values */
1214#define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01)
1215#define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
1216
1217/*PCIe Enumeration Event data EnumerationStatus values */
1218#define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
1219#define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
1220#define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
1221
1222
1223/*PCIe Topology Change List Event data (MPI v2.6 and later) */
1224
1225/*
1226 *Host code (drivers, BIOS, utilities, etc.) should check NumEntries at
1227 *runtime before using PortEntry[].
1228 */
1229
1230typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY {
1231 U16 AttachedDevHandle; /*0x00 */
1232 U8 PortStatus; /*0x02 */
1233 U8 Reserved1; /*0x03 */
1234 U8 CurrentPortInfo; /*0x04 */
1235 U8 Reserved2; /*0x05 */
1236 U8 PreviousPortInfo; /*0x06 */
1237 U8 Reserved3; /*0x07 */
1238} MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1239 *PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1240 Mpi26EventPCIeTopoPortEntry_t,
1241 *pMpi26EventPCIeTopoPortEntry_t;
1242
1243/*PCIe Topology Change List Event data PortStatus values */
1244#define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01)
1245#define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
1246#define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
1247#define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
1248#define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
1249
1250/*PCIe Topology Change List Event data defines for CurrentPortInfo and
1251 *PreviousPortInfo
1252 */
1253#define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0)
1254#define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
1255#define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10)
1256#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20)
1257#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30)
1258#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40)
1259#define MPI26_EVENT_PCIE_TOPO_PI_16_LANES (0x50)
1260
1261#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F)
1262#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
1263#define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
1264#define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
1265#define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
1266#define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
1267#define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
1268
1269typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST {
1270 U16 EnclosureHandle; /*0x00 */
1271 U16 SwitchDevHandle; /*0x02 */
1272 U8 NumPorts; /*0x04 */
1273 U8 Reserved1; /*0x05 */
1274 U16 Reserved2; /*0x06 */
1275 U8 NumEntries; /*0x08 */
1276 U8 StartPortNum; /*0x09 */
1277 U8 SwitchStatus; /*0x0A */
1278 U8 PhysicalPort; /*0x0B */
1279 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
1280 PortEntry[]; /*0x0C */
1281} MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1282 *PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1283 Mpi26EventDataPCIeTopologyChangeList_t,
1284 *pMpi26EventDataPCIeTopologyChangeList_t;
1285
1286/*PCIe Topology Change List Event data SwitchStatus values */
1287#define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
1288#define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01)
1289#define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
1290#define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
1291#define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
1292
1293/*PCIe Link Counter Event data (MPI v2.6 and later) */
1294
1295typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER {
1296 U64 TimeStamp; /*0x00 */
1297 U32 Reserved1; /*0x08 */
1298 U8 LinkEventCode; /*0x0C */
1299 U8 LinkNum; /*0x0D */
1300 U16 Reserved2; /*0x0E */
1301 U32 LinkEventInfo; /*0x10 */
1302 U8 CounterType; /*0x14 */
1303 U8 ThresholdWindow; /*0x15 */
1304 U8 TimeUnits; /*0x16 */
1305 U8 Reserved3; /*0x17 */
1306 U32 EventThreshold; /*0x18 */
1307 U16 ThresholdFlags; /*0x1C */
1308 U16 Reserved4; /*0x1E */
1309} MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1310 *PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1311 Mpi26EventDataPcieLinkCounter_t, *pMpi26EventDataPcieLinkCounter_t;
1312
1313
1314/*use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode
1315 *field
1316 */
1317
1318/*use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType
1319 *field
1320 */
1321
1322/*use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits
1323 *field
1324 */
1325
1326/*use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags
1327 *field
1328 */
1329
1330/****************************************************************************
1331* EventAck message
1332****************************************************************************/
1333
1334/*EventAck Request message */
1335typedef struct _MPI2_EVENT_ACK_REQUEST {
1336 U16 Reserved1; /*0x00 */
1337 U8 ChainOffset; /*0x02 */
1338 U8 Function; /*0x03 */
1339 U16 Reserved2; /*0x04 */
1340 U8 Reserved3; /*0x06 */
1341 U8 MsgFlags; /*0x07 */
1342 U8 VP_ID; /*0x08 */
1343 U8 VF_ID; /*0x09 */
1344 U16 Reserved4; /*0x0A */
1345 U16 Event; /*0x0C */
1346 U16 Reserved5; /*0x0E */
1347 U32 EventContext; /*0x10 */
1348} MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1349 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1350
1351/*EventAck Reply message */
1352typedef struct _MPI2_EVENT_ACK_REPLY {
1353 U16 Reserved1; /*0x00 */
1354 U8 MsgLength; /*0x02 */
1355 U8 Function; /*0x03 */
1356 U16 Reserved2; /*0x04 */
1357 U8 Reserved3; /*0x06 */
1358 U8 MsgFlags; /*0x07 */
1359 U8 VP_ID; /*0x08 */
1360 U8 VF_ID; /*0x09 */
1361 U16 Reserved4; /*0x0A */
1362 U16 Reserved5; /*0x0C */
1363 U16 IOCStatus; /*0x0E */
1364 U32 IOCLogInfo; /*0x10 */
1365} MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1366 Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1367
1368/****************************************************************************
1369* SendHostMessage message
1370****************************************************************************/
1371
1372/*SendHostMessage Request message */
1373typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1374 U16 HostDataLength; /*0x00 */
1375 U8 ChainOffset; /*0x02 */
1376 U8 Function; /*0x03 */
1377 U16 Reserved1; /*0x04 */
1378 U8 Reserved2; /*0x06 */
1379 U8 MsgFlags; /*0x07 */
1380 U8 VP_ID; /*0x08 */
1381 U8 VF_ID; /*0x09 */
1382 U16 Reserved3; /*0x0A */
1383 U8 Reserved4; /*0x0C */
1384 U8 DestVF_ID; /*0x0D */
1385 U16 Reserved5; /*0x0E */
1386 U32 Reserved6; /*0x10 */
1387 U32 Reserved7; /*0x14 */
1388 U32 Reserved8; /*0x18 */
1389 U32 Reserved9; /*0x1C */
1390 U32 Reserved10; /*0x20 */
1391 U32 HostData[]; /*0x24 */
1392} MPI2_SEND_HOST_MESSAGE_REQUEST,
1393 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1394 Mpi2SendHostMessageRequest_t,
1395 *pMpi2SendHostMessageRequest_t;
1396
1397/*SendHostMessage Reply message */
1398typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1399 U16 HostDataLength; /*0x00 */
1400 U8 MsgLength; /*0x02 */
1401 U8 Function; /*0x03 */
1402 U16 Reserved1; /*0x04 */
1403 U8 Reserved2; /*0x06 */
1404 U8 MsgFlags; /*0x07 */
1405 U8 VP_ID; /*0x08 */
1406 U8 VF_ID; /*0x09 */
1407 U16 Reserved3; /*0x0A */
1408 U16 Reserved4; /*0x0C */
1409 U16 IOCStatus; /*0x0E */
1410 U32 IOCLogInfo; /*0x10 */
1411} MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1412 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1413
1414/****************************************************************************
1415* FWDownload message
1416****************************************************************************/
1417
1418/*MPI v2.0 FWDownload Request message */
1419typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1420 U8 ImageType; /*0x00 */
1421 U8 Reserved1; /*0x01 */
1422 U8 ChainOffset; /*0x02 */
1423 U8 Function; /*0x03 */
1424 U16 Reserved2; /*0x04 */
1425 U8 Reserved3; /*0x06 */
1426 U8 MsgFlags; /*0x07 */
1427 U8 VP_ID; /*0x08 */
1428 U8 VF_ID; /*0x09 */
1429 U16 Reserved4; /*0x0A */
1430 U32 TotalImageSize; /*0x0C */
1431 U32 Reserved5; /*0x10 */
1432 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1433} MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1434 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1435
1436#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1437
1438#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1439#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1440#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1441#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1442#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1443#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1444#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1445#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1446#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C)
1447#define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D)
1448#define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E)
1449#define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F)
1450#define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10)
1451#define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11)
1452#define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12)
1453#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13)
1454#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14)
1455/*MPI v2.6 and newer */
1456#define MPI2_FW_DOWNLOAD_ITYPE_CPLD (0x15)
1457#define MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
1458#define MPI2_FW_DOWNLOAD_ITYPE_COREDUMP (0x17)
1459#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1460
1461/*MPI v2.0 FWDownload TransactionContext Element */
1462typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1463 U8 Reserved1; /*0x00 */
1464 U8 ContextSize; /*0x01 */
1465 U8 DetailsLength; /*0x02 */
1466 U8 Flags; /*0x03 */
1467 U32 Reserved2; /*0x04 */
1468 U32 ImageOffset; /*0x08 */
1469 U32 ImageSize; /*0x0C */
1470} MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1471 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1472
1473/*MPI v2.5 FWDownload Request message */
1474typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1475 U8 ImageType; /*0x00 */
1476 U8 Reserved1; /*0x01 */
1477 U8 ChainOffset; /*0x02 */
1478 U8 Function; /*0x03 */
1479 U16 Reserved2; /*0x04 */
1480 U8 Reserved3; /*0x06 */
1481 U8 MsgFlags; /*0x07 */
1482 U8 VP_ID; /*0x08 */
1483 U8 VF_ID; /*0x09 */
1484 U16 Reserved4; /*0x0A */
1485 U32 TotalImageSize; /*0x0C */
1486 U32 Reserved5; /*0x10 */
1487 U32 Reserved6; /*0x14 */
1488 U32 ImageOffset; /*0x18 */
1489 U32 ImageSize; /*0x1C */
1490 MPI25_SGE_IO_UNION SGL; /*0x20 */
1491} MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1492 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1493
1494/*FWDownload Reply message */
1495typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1496 U8 ImageType; /*0x00 */
1497 U8 Reserved1; /*0x01 */
1498 U8 MsgLength; /*0x02 */
1499 U8 Function; /*0x03 */
1500 U16 Reserved2; /*0x04 */
1501 U8 Reserved3; /*0x06 */
1502 U8 MsgFlags; /*0x07 */
1503 U8 VP_ID; /*0x08 */
1504 U8 VF_ID; /*0x09 */
1505 U16 Reserved4; /*0x0A */
1506 U16 Reserved5; /*0x0C */
1507 U16 IOCStatus; /*0x0E */
1508 U32 IOCLogInfo; /*0x10 */
1509} MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1510 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1511
1512/****************************************************************************
1513* FWUpload message
1514****************************************************************************/
1515
1516/*MPI v2.0 FWUpload Request message */
1517typedef struct _MPI2_FW_UPLOAD_REQUEST {
1518 U8 ImageType; /*0x00 */
1519 U8 Reserved1; /*0x01 */
1520 U8 ChainOffset; /*0x02 */
1521 U8 Function; /*0x03 */
1522 U16 Reserved2; /*0x04 */
1523 U8 Reserved3; /*0x06 */
1524 U8 MsgFlags; /*0x07 */
1525 U8 VP_ID; /*0x08 */
1526 U8 VF_ID; /*0x09 */
1527 U16 Reserved4; /*0x0A */
1528 U32 Reserved5; /*0x0C */
1529 U32 Reserved6; /*0x10 */
1530 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1531} MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1532 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1533
1534#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1535#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1536#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1537#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1538#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1539#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1540#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1541#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1542#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1543#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1544#define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)
1545#define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E)
1546#define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F)
1547#define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10)
1548#define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11)
1549#define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12)
1550#define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13)
1551#define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14)
1552
1553
1554/*MPI v2.0 FWUpload TransactionContext Element */
1555typedef struct _MPI2_FW_UPLOAD_TCSGE {
1556 U8 Reserved1; /*0x00 */
1557 U8 ContextSize; /*0x01 */
1558 U8 DetailsLength; /*0x02 */
1559 U8 Flags; /*0x03 */
1560 U32 Reserved2; /*0x04 */
1561 U32 ImageOffset; /*0x08 */
1562 U32 ImageSize; /*0x0C */
1563} MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1564 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1565
1566/*MPI v2.5 FWUpload Request message */
1567typedef struct _MPI25_FW_UPLOAD_REQUEST {
1568 U8 ImageType; /*0x00 */
1569 U8 Reserved1; /*0x01 */
1570 U8 ChainOffset; /*0x02 */
1571 U8 Function; /*0x03 */
1572 U16 Reserved2; /*0x04 */
1573 U8 Reserved3; /*0x06 */
1574 U8 MsgFlags; /*0x07 */
1575 U8 VP_ID; /*0x08 */
1576 U8 VF_ID; /*0x09 */
1577 U16 Reserved4; /*0x0A */
1578 U32 Reserved5; /*0x0C */
1579 U32 Reserved6; /*0x10 */
1580 U32 Reserved7; /*0x14 */
1581 U32 ImageOffset; /*0x18 */
1582 U32 ImageSize; /*0x1C */
1583 MPI25_SGE_IO_UNION SGL; /*0x20 */
1584} MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1585 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1586
1587/*FWUpload Reply message */
1588typedef struct _MPI2_FW_UPLOAD_REPLY {
1589 U8 ImageType; /*0x00 */
1590 U8 Reserved1; /*0x01 */
1591 U8 MsgLength; /*0x02 */
1592 U8 Function; /*0x03 */
1593 U16 Reserved2; /*0x04 */
1594 U8 Reserved3; /*0x06 */
1595 U8 MsgFlags; /*0x07 */
1596 U8 VP_ID; /*0x08 */
1597 U8 VF_ID; /*0x09 */
1598 U16 Reserved4; /*0x0A */
1599 U16 Reserved5; /*0x0C */
1600 U16 IOCStatus; /*0x0E */
1601 U32 IOCLogInfo; /*0x10 */
1602 U32 ActualImageSize; /*0x14 */
1603} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1604 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1605
1606
1607/****************************************************************************
1608* PowerManagementControl message
1609****************************************************************************/
1610
1611/*PowerManagementControl Request message */
1612typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1613 U8 Feature; /*0x00 */
1614 U8 Reserved1; /*0x01 */
1615 U8 ChainOffset; /*0x02 */
1616 U8 Function; /*0x03 */
1617 U16 Reserved2; /*0x04 */
1618 U8 Reserved3; /*0x06 */
1619 U8 MsgFlags; /*0x07 */
1620 U8 VP_ID; /*0x08 */
1621 U8 VF_ID; /*0x09 */
1622 U16 Reserved4; /*0x0A */
1623 U8 Parameter1; /*0x0C */
1624 U8 Parameter2; /*0x0D */
1625 U8 Parameter3; /*0x0E */
1626 U8 Parameter4; /*0x0F */
1627 U32 Reserved5; /*0x10 */
1628 U32 Reserved6; /*0x14 */
1629} MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1630 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1631
1632/*defines for the Feature field */
1633#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1634#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1635#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */
1636#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1637#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05)
1638#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1639#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1640
1641/*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1642/*Parameter1 contains a PHY number */
1643/*Parameter2 indicates power condition action using these defines */
1644#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1645#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1646#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1647/*Parameter3 and Parameter4 are reserved */
1648
1649/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1650 * Feature */
1651/*Parameter1 contains SAS port width modulation group number */
1652/*Parameter2 indicates IOC action using these defines */
1653#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1654#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1655#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1656/*Parameter3 indicates desired modulation level using these defines */
1657#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1658#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1659#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1660#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1661/*Parameter4 is reserved */
1662
1663/*this next set (_PCIE_LINK) is obsolete */
1664/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1665/*Parameter1 indicates desired PCIe link speed using these defines */
1666#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */
1667#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */
1668#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */
1669/*Parameter2 indicates desired PCIe link width using these defines */
1670#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */
1671#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */
1672#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */
1673#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */
1674/*Parameter3 and Parameter4 are reserved */
1675
1676/*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1677/*Parameter1 indicates desired IOC hardware clock speed using these defines */
1678#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1679#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1680#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1681#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1682/*Parameter2, Parameter3, and Parameter4 are reserved */
1683
1684/*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1685/*Parameter1 indicates host action regarding global power management mode */
1686#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)
1687#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)
1688#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)
1689/*Parameter2 indicates the requested global power management mode */
1690#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)
1691#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)
1692#define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)
1693/*Parameter3 and Parameter4 are reserved */
1694
1695/*PowerManagementControl Reply message */
1696typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1697 U8 Feature; /*0x00 */
1698 U8 Reserved1; /*0x01 */
1699 U8 MsgLength; /*0x02 */
1700 U8 Function; /*0x03 */
1701 U16 Reserved2; /*0x04 */
1702 U8 Reserved3; /*0x06 */
1703 U8 MsgFlags; /*0x07 */
1704 U8 VP_ID; /*0x08 */
1705 U8 VF_ID; /*0x09 */
1706 U16 Reserved4; /*0x0A */
1707 U16 Reserved5; /*0x0C */
1708 U16 IOCStatus; /*0x0E */
1709 U32 IOCLogInfo; /*0x10 */
1710} MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1711 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
1712
1713/****************************************************************************
1714* IO Unit Control messages (MPI v2.6 and later only.)
1715****************************************************************************/
1716
1717/* IO Unit Control Request Message */
1718typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {
1719 U8 Operation; /* 0x00 */
1720 U8 Reserved1; /* 0x01 */
1721 U8 ChainOffset; /* 0x02 */
1722 U8 Function; /* 0x03 */
1723 U16 DevHandle; /* 0x04 */
1724 U8 IOCParameter; /* 0x06 */
1725 U8 MsgFlags; /* 0x07 */
1726 U8 VP_ID; /* 0x08 */
1727 U8 VF_ID; /* 0x09 */
1728 U16 Reserved3; /* 0x0A */
1729 U16 Reserved4; /* 0x0C */
1730 U8 PhyNum; /* 0x0E */
1731 U8 PrimFlags; /* 0x0F */
1732 U32 Primitive; /* 0x10 */
1733 U8 LookupMethod; /* 0x14 */
1734 U8 Reserved5; /* 0x15 */
1735 U16 SlotNumber; /* 0x16 */
1736 U64 LookupAddress; /* 0x18 */
1737 U32 IOCParameterValue; /* 0x20 */
1738 U32 Reserved7; /* 0x24 */
1739 U32 Reserved8; /* 0x28 */
1740} MPI26_IOUNIT_CONTROL_REQUEST,
1741 *PTR_MPI26_IOUNIT_CONTROL_REQUEST,
1742 Mpi26IoUnitControlRequest_t,
1743 *pMpi26IoUnitControlRequest_t;
1744
1745/* values for the Operation field */
1746#define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02)
1747#define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06)
1748#define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07)
1749#define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08)
1750#define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09)
1751#define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A)
1752#define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B)
1753#define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D)
1754#define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E)
1755#define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F)
1756#define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10)
1757#define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11)
1758#define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12)
1759#define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13)
1760#define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14)
1761#define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15)
1762#define MPI26_CTRL_OP_SHUTDOWN (0x16)
1763#define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)
1764#define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)
1765#define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)
1766#define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A)
1767#define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B)
1768#define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)
1769
1770/* values for the PrimFlags field */
1771#define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08)
1772#define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02)
1773#define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01)
1774
1775/* values for the LookupMethod field */
1776#define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
1777#define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
1778#define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
1779
1780
1781/* IO Unit Control Reply Message */
1782typedef struct _MPI26_IOUNIT_CONTROL_REPLY {
1783 U8 Operation; /* 0x00 */
1784 U8 Reserved1; /* 0x01 */
1785 U8 MsgLength; /* 0x02 */
1786 U8 Function; /* 0x03 */
1787 U16 DevHandle; /* 0x04 */
1788 U8 IOCParameter; /* 0x06 */
1789 U8 MsgFlags; /* 0x07 */
1790 U8 VP_ID; /* 0x08 */
1791 U8 VF_ID; /* 0x09 */
1792 U16 Reserved3; /* 0x0A */
1793 U16 Reserved4; /* 0x0C */
1794 U16 IOCStatus; /* 0x0E */
1795 U32 IOCLogInfo; /* 0x10 */
1796} MPI26_IOUNIT_CONTROL_REPLY,
1797 *PTR_MPI26_IOUNIT_CONTROL_REPLY,
1798 Mpi26IoUnitControlReply_t,
1799 *pMpi26IoUnitControlReply_t;
1800
1801
1802#endif
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2000-2015 Avago Technologies. All rights reserved.
4 *
5 *
6 * Name: mpi2_ioc.h
7 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
8 * Creation Date: October 11, 2006
9 *
10 * mpi2_ioc.h Version: 02.00.32
11 *
12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13 * prefix are for use only on MPI v2.5 products, and must not be used
14 * with MPI v2.0 products. Unless otherwise noted, names beginning with
15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
16 *
17 * Version History
18 * ---------------
19 *
20 * Date Version Description
21 * -------- -------- ------------------------------------------------------
22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
23 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
24 * MaxTargets.
25 * Added TotalImageSize field to FWDownload Request.
26 * Added reserved words to FWUpload Request.
27 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
28 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
29 * request and replaced it with
30 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
31 * Replaced the MinReplyQueueDepth field of the IOCFacts
32 * reply with MaxReplyDescriptorPostQueueDepth.
33 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
34 * depth for the Reply Descriptor Post Queue.
35 * Added SASAddress field to Initiator Device Table
36 * Overflow Event data.
37 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
38 * for SAS Initiator Device Status Change Event data.
39 * Modified Reason Code defines for SAS Topology Change
40 * List Event data, including adding a bit for PHY Vacant
41 * status, and adding a mask for the Reason Code.
42 * Added define for
43 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
44 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
45 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
46 * the IOCFacts Reply.
47 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
48 * Moved MPI2_VERSION_UNION to mpi2.h.
49 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
50 * instead of enables, and added SASBroadcastPrimitiveMasks
51 * field.
52 * Added Log Entry Added Event and related structure.
53 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
54 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
55 * Added MaxVolumes and MaxPersistentEntries fields to
56 * IOCFacts reply.
57 * Added ProtocalFlags and IOCCapabilities fields to
58 * MPI2_FW_IMAGE_HEADER.
59 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
60 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
61 * a U16 (from a U32).
62 * Removed extra 's' from EventMasks name.
63 * 06-27-08 02.00.08 Fixed an offset in a comment.
64 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
65 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
66 * renamed MinReplyFrameSize to ReplyFrameSize.
67 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
68 * Added two new RAIDOperation values for Integrated RAID
69 * Operations Status Event data.
70 * Added four new IR Configuration Change List Event data
71 * ReasonCode values.
72 * Added two new ReasonCode defines for SAS Device Status
73 * Change Event data.
74 * Added three new DiscoveryStatus bits for the SAS
75 * Discovery event data.
76 * Added Multiplexing Status Change bit to the PhyStatus
77 * field of the SAS Topology Change List event data.
78 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
79 * BootFlags are now product-specific.
80 * Added defines for the indivdual signature bytes
81 * for MPI2_INIT_IMAGE_FOOTER.
82 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
83 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
84 * define.
85 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
86 * define.
87 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
88 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
89 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
90 * Added two new reason codes for SAS Device Status Change
91 * Event.
92 * Added new event: SAS PHY Counter.
93 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
94 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
95 * Added new product id family for 2208.
96 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
97 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
98 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
99 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
100 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
101 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
102 * Added Host Based Discovery Phy Event data.
103 * Added defines for ProductID Product field
104 * (MPI2_FW_HEADER_PID_).
105 * Modified values for SAS ProductID Family
106 * (MPI2_FW_HEADER_PID_FAMILY_).
107 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
108 * Added PowerManagementControl Request structures and
109 * defines.
110 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
111 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
112 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
113 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
114 * SASNotifyPrimitiveMasks field to
115 * MPI2_EVENT_NOTIFICATION_REQUEST.
116 * Added Temperature Threshold Event.
117 * Added Host Message Event.
118 * Added Send Host Message request and reply.
119 * 05-25-11 02.00.18 For Extended Image Header, added
120 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
121 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
122 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
123 * 08-24-11 02.00.19 Added PhysicalPort field to
124 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
125 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
126 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.
127 * 03-29-12 02.00.21 Added a product specific range to event values.
128 * 07-26-12 02.00.22 Added MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE.
129 * Added ElapsedSeconds field to
130 * MPI2_EVENT_DATA_IR_OPERATION_STATUS.
131 * 08-19-13 02.00.23 For IOCInit, added MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE
132 * and MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY.
133 * Added MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE.
134 * Added MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY.
135 * Added Encrypted Hash Extended Image.
136 * 12-05-13 02.00.24 Added MPI25_HASH_IMAGE_TYPE_BIOS.
137 * 11-18-14 02.00.25 Updated copyright information.
138 * 03-16-15 02.00.26 Updated for MPI v2.6.
139 * Added MPI2_EVENT_ACTIVE_CABLE_EXCEPTION and
140 * MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT.
141 * Added MPI26_FW_HEADER_PID_FAMILY_3324_SAS and
142 * MPI26_FW_HEADER_PID_FAMILY_3516_SAS.
143 * Added MPI26_CTRL_OP_SHUTDOWN.
144 * 08-25-15 02.00.27 Added IC ARCH Class based signature defines.
145 * Added MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED event.
146 * Added ConigurationFlags field to IOCInit message to
147 * support NVMe SGL format control.
148 * Added PCIe SRIOV support.
149 * 02-17-16 02.00.28 Added SAS 4 22.5 gbs speed support.
150 * Added PCIe 4 16.0 GT/sec speec support.
151 * Removed AHCI support.
152 * Removed SOP support.
153 * 07-01-16 02.00.29 Added Archclass for 4008 product.
154 * Added IOCException MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED
155 * 08-23-16 02.00.30 Added new defines for the ImageType field of FWDownload
156 * Request Message.
157 * Added new defines for the ImageType field of FWUpload
158 * Request Message.
159 * Added new values for the RegionType field in the Layout
160 * Data sections of the FLASH Layout Extended Image Data.
161 * Added new defines for the ReasonCode field of
162 * Active Cable Exception Event.
163 * Added MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE and
164 * MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE.
165 * 11-23-16 02.00.31 Added MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR and
166 * MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR.
167 * 02-02-17 02.00.32 Added MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP.
168 * Added MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT and related
169 * defines for the ReasonCode field.
170 * --------------------------------------------------------------------------
171 */
172
173#ifndef MPI2_IOC_H
174#define MPI2_IOC_H
175
176/*****************************************************************************
177*
178* IOC Messages
179*
180*****************************************************************************/
181
182/****************************************************************************
183* IOCInit message
184****************************************************************************/
185
186/*IOCInit Request message */
187typedef struct _MPI2_IOC_INIT_REQUEST {
188 U8 WhoInit; /*0x00 */
189 U8 Reserved1; /*0x01 */
190 U8 ChainOffset; /*0x02 */
191 U8 Function; /*0x03 */
192 U16 Reserved2; /*0x04 */
193 U8 Reserved3; /*0x06 */
194 U8 MsgFlags; /*0x07 */
195 U8 VP_ID; /*0x08 */
196 U8 VF_ID; /*0x09 */
197 U16 Reserved4; /*0x0A */
198 U16 MsgVersion; /*0x0C */
199 U16 HeaderVersion; /*0x0E */
200 U32 Reserved5; /*0x10 */
201 U16 ConfigurationFlags; /* 0x14 */
202 U8 HostPageSize; /*0x16 */
203 U8 HostMSIxVectors; /*0x17 */
204 U16 Reserved8; /*0x18 */
205 U16 SystemRequestFrameSize; /*0x1A */
206 U16 ReplyDescriptorPostQueueDepth; /*0x1C */
207 U16 ReplyFreeQueueDepth; /*0x1E */
208 U32 SenseBufferAddressHigh; /*0x20 */
209 U32 SystemReplyAddressHigh; /*0x24 */
210 U64 SystemRequestFrameBaseAddress; /*0x28 */
211 U64 ReplyDescriptorPostQueueAddress; /*0x30 */
212 U64 ReplyFreeQueueAddress; /*0x38 */
213 U64 TimeStamp; /*0x40 */
214} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
215 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
216
217/*WhoInit values */
218#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
219#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
220#define MPI2_WHOINIT_ROM_BIOS (0x02)
221#define MPI2_WHOINIT_PCI_PEER (0x03)
222#define MPI2_WHOINIT_HOST_DRIVER (0x04)
223#define MPI2_WHOINIT_MANUFACTURER (0x05)
224
225/* MsgFlags */
226#define MPI2_IOCINIT_MSGFLAG_RDPQ_ARRAY_MODE (0x01)
227
228
229/*MsgVersion */
230#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
231#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
232#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
233#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
234
235/*HeaderVersion */
236#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
237#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
238#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
239#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
240
241/*ConfigurationFlags */
242#define MPI26_IOCINIT_CFGFLAGS_NVME_SGL_FORMAT (0x0001)
243
244/*minimum depth for a Reply Descriptor Post Queue */
245#define MPI2_RDPQ_DEPTH_MIN (16)
246
247/* Reply Descriptor Post Queue Array Entry */
248typedef struct _MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
249 U64 RDPQBaseAddress; /* 0x00 */
250 U32 Reserved1; /* 0x08 */
251 U32 Reserved2; /* 0x0C */
252} MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
253*PTR_MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY,
254Mpi2IOCInitRDPQArrayEntry, *pMpi2IOCInitRDPQArrayEntry;
255
256
257/*IOCInit Reply message */
258typedef struct _MPI2_IOC_INIT_REPLY {
259 U8 WhoInit; /*0x00 */
260 U8 Reserved1; /*0x01 */
261 U8 MsgLength; /*0x02 */
262 U8 Function; /*0x03 */
263 U16 Reserved2; /*0x04 */
264 U8 Reserved3; /*0x06 */
265 U8 MsgFlags; /*0x07 */
266 U8 VP_ID; /*0x08 */
267 U8 VF_ID; /*0x09 */
268 U16 Reserved4; /*0x0A */
269 U16 Reserved5; /*0x0C */
270 U16 IOCStatus; /*0x0E */
271 U32 IOCLogInfo; /*0x10 */
272} MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
273 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
274
275/****************************************************************************
276* IOCFacts message
277****************************************************************************/
278
279/*IOCFacts Request message */
280typedef struct _MPI2_IOC_FACTS_REQUEST {
281 U16 Reserved1; /*0x00 */
282 U8 ChainOffset; /*0x02 */
283 U8 Function; /*0x03 */
284 U16 Reserved2; /*0x04 */
285 U8 Reserved3; /*0x06 */
286 U8 MsgFlags; /*0x07 */
287 U8 VP_ID; /*0x08 */
288 U8 VF_ID; /*0x09 */
289 U16 Reserved4; /*0x0A */
290} MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
291 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
292
293/*IOCFacts Reply message */
294typedef struct _MPI2_IOC_FACTS_REPLY {
295 U16 MsgVersion; /*0x00 */
296 U8 MsgLength; /*0x02 */
297 U8 Function; /*0x03 */
298 U16 HeaderVersion; /*0x04 */
299 U8 IOCNumber; /*0x06 */
300 U8 MsgFlags; /*0x07 */
301 U8 VP_ID; /*0x08 */
302 U8 VF_ID; /*0x09 */
303 U16 Reserved1; /*0x0A */
304 U16 IOCExceptions; /*0x0C */
305 U16 IOCStatus; /*0x0E */
306 U32 IOCLogInfo; /*0x10 */
307 U8 MaxChainDepth; /*0x14 */
308 U8 WhoInit; /*0x15 */
309 U8 NumberOfPorts; /*0x16 */
310 U8 MaxMSIxVectors; /*0x17 */
311 U16 RequestCredit; /*0x18 */
312 U16 ProductID; /*0x1A */
313 U32 IOCCapabilities; /*0x1C */
314 MPI2_VERSION_UNION FWVersion; /*0x20 */
315 U16 IOCRequestFrameSize; /*0x24 */
316 U16 IOCMaxChainSegmentSize; /*0x26 */
317 U16 MaxInitiators; /*0x28 */
318 U16 MaxTargets; /*0x2A */
319 U16 MaxSasExpanders; /*0x2C */
320 U16 MaxEnclosures; /*0x2E */
321 U16 ProtocolFlags; /*0x30 */
322 U16 HighPriorityCredit; /*0x32 */
323 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */
324 U8 ReplyFrameSize; /*0x36 */
325 U8 MaxVolumes; /*0x37 */
326 U16 MaxDevHandle; /*0x38 */
327 U16 MaxPersistentEntries; /*0x3A */
328 U16 MinDevHandle; /*0x3C */
329 U8 CurrentHostPageSize; /* 0x3E */
330 U8 Reserved4; /* 0x3F */
331 U8 SGEModifierMask; /*0x40 */
332 U8 SGEModifierValue; /*0x41 */
333 U8 SGEModifierShift; /*0x42 */
334 U8 Reserved5; /*0x43 */
335} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
336 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
337
338/*MsgVersion */
339#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
340#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
341#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
342#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
343
344/*HeaderVersion */
345#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
346#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
347#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
348#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
349
350/*IOCExceptions */
351#define MPI2_IOCFACTS_EXCEPT_PCIE_DISABLED (0x0400)
352#define MPI2_IOCFACTS_EXCEPT_PARTIAL_MEMORY_FAILURE (0x0200)
353#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
354
355#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
356#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
357#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
358#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
359#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
360
361#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
362#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
363#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
364#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
365#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
366
367/*defines for WhoInit field are after the IOCInit Request */
368
369/*ProductID field uses MPI2_FW_HEADER_PID_ */
370
371/*IOCCapabilities */
372#define MPI26_IOCFACTS_CAPABILITY_PCIE_SRIOV (0x00100000)
373#define MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ (0x00080000)
374#define MPI2_IOCFACTS_CAPABILITY_RDPQ_ARRAY_CAPABLE (0x00040000)
375#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
376#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
377#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
378#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
379#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
380#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
381#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
382#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
383#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
384#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
385#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
386#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
387#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
388#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
389
390/*ProtocolFlags */
391#define MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES (0x0008)
392#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
393#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
394
395/****************************************************************************
396* PortFacts message
397****************************************************************************/
398
399/*PortFacts Request message */
400typedef struct _MPI2_PORT_FACTS_REQUEST {
401 U16 Reserved1; /*0x00 */
402 U8 ChainOffset; /*0x02 */
403 U8 Function; /*0x03 */
404 U16 Reserved2; /*0x04 */
405 U8 PortNumber; /*0x06 */
406 U8 MsgFlags; /*0x07 */
407 U8 VP_ID; /*0x08 */
408 U8 VF_ID; /*0x09 */
409 U16 Reserved3; /*0x0A */
410} MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
411 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
412
413/*PortFacts Reply message */
414typedef struct _MPI2_PORT_FACTS_REPLY {
415 U16 Reserved1; /*0x00 */
416 U8 MsgLength; /*0x02 */
417 U8 Function; /*0x03 */
418 U16 Reserved2; /*0x04 */
419 U8 PortNumber; /*0x06 */
420 U8 MsgFlags; /*0x07 */
421 U8 VP_ID; /*0x08 */
422 U8 VF_ID; /*0x09 */
423 U16 Reserved3; /*0x0A */
424 U16 Reserved4; /*0x0C */
425 U16 IOCStatus; /*0x0E */
426 U32 IOCLogInfo; /*0x10 */
427 U8 Reserved5; /*0x14 */
428 U8 PortType; /*0x15 */
429 U16 Reserved6; /*0x16 */
430 U16 MaxPostedCmdBuffers; /*0x18 */
431 U16 Reserved7; /*0x1A */
432} MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
433 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
434
435/*PortType values */
436#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
437#define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
438#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
439#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
440#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
441#define MPI2_PORTFACTS_PORTTYPE_TRI_MODE (0x40)
442
443
444/****************************************************************************
445* PortEnable message
446****************************************************************************/
447
448/*PortEnable Request message */
449typedef struct _MPI2_PORT_ENABLE_REQUEST {
450 U16 Reserved1; /*0x00 */
451 U8 ChainOffset; /*0x02 */
452 U8 Function; /*0x03 */
453 U8 Reserved2; /*0x04 */
454 U8 PortFlags; /*0x05 */
455 U8 Reserved3; /*0x06 */
456 U8 MsgFlags; /*0x07 */
457 U8 VP_ID; /*0x08 */
458 U8 VF_ID; /*0x09 */
459 U16 Reserved4; /*0x0A */
460} MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
461 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
462
463/*PortEnable Reply message */
464typedef struct _MPI2_PORT_ENABLE_REPLY {
465 U16 Reserved1; /*0x00 */
466 U8 MsgLength; /*0x02 */
467 U8 Function; /*0x03 */
468 U8 Reserved2; /*0x04 */
469 U8 PortFlags; /*0x05 */
470 U8 Reserved3; /*0x06 */
471 U8 MsgFlags; /*0x07 */
472 U8 VP_ID; /*0x08 */
473 U8 VF_ID; /*0x09 */
474 U16 Reserved4; /*0x0A */
475 U16 Reserved5; /*0x0C */
476 U16 IOCStatus; /*0x0E */
477 U32 IOCLogInfo; /*0x10 */
478} MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
479 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
480
481/****************************************************************************
482* EventNotification message
483****************************************************************************/
484
485/*EventNotification Request message */
486#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
487
488typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
489 U16 Reserved1; /*0x00 */
490 U8 ChainOffset; /*0x02 */
491 U8 Function; /*0x03 */
492 U16 Reserved2; /*0x04 */
493 U8 Reserved3; /*0x06 */
494 U8 MsgFlags; /*0x07 */
495 U8 VP_ID; /*0x08 */
496 U8 VF_ID; /*0x09 */
497 U16 Reserved4; /*0x0A */
498 U32 Reserved5; /*0x0C */
499 U32 Reserved6; /*0x10 */
500 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */
501 U16 SASBroadcastPrimitiveMasks; /*0x24 */
502 U16 SASNotifyPrimitiveMasks; /*0x26 */
503 U32 Reserved8; /*0x28 */
504} MPI2_EVENT_NOTIFICATION_REQUEST,
505 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
506 Mpi2EventNotificationRequest_t,
507 *pMpi2EventNotificationRequest_t;
508
509/*EventNotification Reply message */
510typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
511 U16 EventDataLength; /*0x00 */
512 U8 MsgLength; /*0x02 */
513 U8 Function; /*0x03 */
514 U16 Reserved1; /*0x04 */
515 U8 AckRequired; /*0x06 */
516 U8 MsgFlags; /*0x07 */
517 U8 VP_ID; /*0x08 */
518 U8 VF_ID; /*0x09 */
519 U16 Reserved2; /*0x0A */
520 U16 Reserved3; /*0x0C */
521 U16 IOCStatus; /*0x0E */
522 U32 IOCLogInfo; /*0x10 */
523 U16 Event; /*0x14 */
524 U16 Reserved4; /*0x16 */
525 U32 EventContext; /*0x18 */
526 U32 EventData[1]; /*0x1C */
527} MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
528 Mpi2EventNotificationReply_t,
529 *pMpi2EventNotificationReply_t;
530
531/*AckRequired */
532#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
533#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
534
535/*Event */
536#define MPI2_EVENT_LOG_DATA (0x0001)
537#define MPI2_EVENT_STATE_CHANGE (0x0002)
538#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
539#define MPI2_EVENT_EVENT_CHANGE (0x000A)
540#define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */
541#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
542#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
543#define MPI2_EVENT_SAS_DISCOVERY (0x0016)
544#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
545#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
546#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
547#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
548#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
549#define MPI2_EVENT_ENCL_DEVICE_STATUS_CHANGE (0x001D)
550#define MPI2_EVENT_IR_VOLUME (0x001E)
551#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
552#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
553#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
554#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
555#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
556#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
557#define MPI2_EVENT_SAS_QUIESCE (0x0025)
558#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
559#define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
560#define MPI2_EVENT_HOST_MESSAGE (0x0028)
561#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
562#define MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE (0x0030)
563#define MPI2_EVENT_PCIE_ENUMERATION (0x0031)
564#define MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST (0x0032)
565#define MPI2_EVENT_PCIE_LINK_COUNTER (0x0033)
566#define MPI2_EVENT_ACTIVE_CABLE_EXCEPTION (0x0034)
567#define MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR (0x0035)
568#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
569#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
570
571/*Log Entry Added Event data */
572
573/*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
574#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
575
576typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
577 U64 TimeStamp; /*0x00 */
578 U32 Reserved1; /*0x08 */
579 U16 LogSequence; /*0x0C */
580 U16 LogEntryQualifier; /*0x0E */
581 U8 VP_ID; /*0x10 */
582 U8 VF_ID; /*0x11 */
583 U16 Reserved2; /*0x12 */
584 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */
585} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
586 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
587 Mpi2EventDataLogEntryAdded_t,
588 *pMpi2EventDataLogEntryAdded_t;
589
590/*GPIO Interrupt Event data */
591
592typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
593 U8 GPIONum; /*0x00 */
594 U8 Reserved1; /*0x01 */
595 U16 Reserved2; /*0x02 */
596} MPI2_EVENT_DATA_GPIO_INTERRUPT,
597 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
598 Mpi2EventDataGpioInterrupt_t,
599 *pMpi2EventDataGpioInterrupt_t;
600
601/*Temperature Threshold Event data */
602
603typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
604 U16 Status; /*0x00 */
605 U8 SensorNum; /*0x02 */
606 U8 Reserved1; /*0x03 */
607 U16 CurrentTemperature; /*0x04 */
608 U16 Reserved2; /*0x06 */
609 U32 Reserved3; /*0x08 */
610 U32 Reserved4; /*0x0C */
611} MPI2_EVENT_DATA_TEMPERATURE,
612 *PTR_MPI2_EVENT_DATA_TEMPERATURE,
613 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
614
615/*Temperature Threshold Event data Status bits */
616#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
617#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
618#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
619#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
620
621/*Host Message Event data */
622
623typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
624 U8 SourceVF_ID; /*0x00 */
625 U8 Reserved1; /*0x01 */
626 U16 Reserved2; /*0x02 */
627 U32 Reserved3; /*0x04 */
628 U32 HostData[1]; /*0x08 */
629} MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
630 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
631
632/*Power Performance Change Event data */
633
634typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
635 U8 CurrentPowerMode; /*0x00 */
636 U8 PreviousPowerMode; /*0x01 */
637 U16 Reserved1; /*0x02 */
638} MPI2_EVENT_DATA_POWER_PERF_CHANGE,
639 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
640 Mpi2EventDataPowerPerfChange_t,
641 *pMpi2EventDataPowerPerfChange_t;
642
643/*defines for CurrentPowerMode and PreviousPowerMode fields */
644#define MPI2_EVENT_PM_INIT_MASK (0xC0)
645#define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)
646#define MPI2_EVENT_PM_INIT_HOST (0x40)
647#define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)
648#define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)
649
650#define MPI2_EVENT_PM_MODE_MASK (0x07)
651#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
652#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
653#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
654#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
655#define MPI2_EVENT_PM_MODE_STANDBY (0x06)
656
657/* Active Cable Exception Event data */
658
659typedef struct _MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT {
660 U32 ActiveCablePowerRequirement; /* 0x00 */
661 U8 ReasonCode; /* 0x04 */
662 U8 ReceptacleID; /* 0x05 */
663 U16 Reserved1; /* 0x06 */
664} MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
665 *PTR_MPI25_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
666 Mpi25EventDataActiveCableExcept_t,
667 *pMpi25EventDataActiveCableExcept_t,
668 MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
669 *PTR_MPI26_EVENT_DATA_ACTIVE_CABLE_EXCEPT,
670 Mpi26EventDataActiveCableExcept_t,
671 *pMpi26EventDataActiveCableExcept_t;
672
673/*MPI2.5 defines for the ReasonCode field */
674#define MPI25_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
675#define MPI25_EVENT_ACTIVE_CABLE_PRESENT (0x01)
676#define MPI25_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
677
678/* defines for ReasonCode field */
679#define MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER (0x00)
680#define MPI26_EVENT_ACTIVE_CABLE_PRESENT (0x01)
681#define MPI26_EVENT_ACTIVE_CABLE_DEGRADED (0x02)
682
683/*Hard Reset Received Event data */
684
685typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
686 U8 Reserved1; /*0x00 */
687 U8 Port; /*0x01 */
688 U16 Reserved2; /*0x02 */
689} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
690 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
691 Mpi2EventDataHardResetReceived_t,
692 *pMpi2EventDataHardResetReceived_t;
693
694/*Task Set Full Event data */
695/* this event is obsolete */
696
697typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
698 U16 DevHandle; /*0x00 */
699 U16 CurrentDepth; /*0x02 */
700} MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
701 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
702
703/*SAS Device Status Change Event data */
704
705typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
706 U16 TaskTag; /*0x00 */
707 U8 ReasonCode; /*0x02 */
708 U8 PhysicalPort; /*0x03 */
709 U8 ASC; /*0x04 */
710 U8 ASCQ; /*0x05 */
711 U16 DevHandle; /*0x06 */
712 U32 Reserved2; /*0x08 */
713 U64 SASAddress; /*0x0C */
714 U8 LUN[8]; /*0x14 */
715} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
716 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
717 Mpi2EventDataSasDeviceStatusChange_t,
718 *pMpi2EventDataSasDeviceStatusChange_t;
719
720/*SAS Device Status Change Event data ReasonCode values */
721#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
722#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
723#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
724#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
725#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
726#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
727#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
728#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
729#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
730#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
731#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
732#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
733#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
734
735/*Integrated RAID Operation Status Event data */
736
737typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
738 U16 VolDevHandle; /*0x00 */
739 U16 Reserved1; /*0x02 */
740 U8 RAIDOperation; /*0x04 */
741 U8 PercentComplete; /*0x05 */
742 U16 Reserved2; /*0x06 */
743 U32 ElapsedSeconds; /*0x08 */
744} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
745 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
746 Mpi2EventDataIrOperationStatus_t,
747 *pMpi2EventDataIrOperationStatus_t;
748
749/*Integrated RAID Operation Status Event data RAIDOperation values */
750#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
751#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
752#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
753#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
754#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
755
756/*Integrated RAID Volume Event data */
757
758typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
759 U16 VolDevHandle; /*0x00 */
760 U8 ReasonCode; /*0x02 */
761 U8 Reserved1; /*0x03 */
762 U32 NewValue; /*0x04 */
763 U32 PreviousValue; /*0x08 */
764} MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
765 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
766
767/*Integrated RAID Volume Event data ReasonCode values */
768#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
769#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
770#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
771
772/*Integrated RAID Physical Disk Event data */
773
774typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
775 U16 Reserved1; /*0x00 */
776 U8 ReasonCode; /*0x02 */
777 U8 PhysDiskNum; /*0x03 */
778 U16 PhysDiskDevHandle; /*0x04 */
779 U16 Reserved2; /*0x06 */
780 U16 Slot; /*0x08 */
781 U16 EnclosureHandle; /*0x0A */
782 U32 NewValue; /*0x0C */
783 U32 PreviousValue; /*0x10 */
784} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
785 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
786 Mpi2EventDataIrPhysicalDisk_t,
787 *pMpi2EventDataIrPhysicalDisk_t;
788
789/*Integrated RAID Physical Disk Event data ReasonCode values */
790#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
791#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
792#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
793
794/*Integrated RAID Configuration Change List Event data */
795
796/*
797 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
798 *one and check NumElements at runtime.
799 */
800#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
801#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
802#endif
803
804typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
805 U16 ElementFlags; /*0x00 */
806 U16 VolDevHandle; /*0x02 */
807 U8 ReasonCode; /*0x04 */
808 U8 PhysDiskNum; /*0x05 */
809 U16 PhysDiskDevHandle; /*0x06 */
810} MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
811 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
812
813/*IR Configuration Change List Event data ElementFlags values */
814#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
815#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
816#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
817#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
818
819/*IR Configuration Change List Event data ReasonCode values */
820#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
821#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
822#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
823#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
824#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
825#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
826#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
827#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
828#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
829
830typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
831 U8 NumElements; /*0x00 */
832 U8 Reserved1; /*0x01 */
833 U8 Reserved2; /*0x02 */
834 U8 ConfigNum; /*0x03 */
835 U32 Flags; /*0x04 */
836 MPI2_EVENT_IR_CONFIG_ELEMENT
837 ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
838} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
839 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
840 Mpi2EventDataIrConfigChangeList_t,
841 *pMpi2EventDataIrConfigChangeList_t;
842
843/*IR Configuration Change List Event data Flags values */
844#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
845
846/*SAS Discovery Event data */
847
848typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
849 U8 Flags; /*0x00 */
850 U8 ReasonCode; /*0x01 */
851 U8 PhysicalPort; /*0x02 */
852 U8 Reserved1; /*0x03 */
853 U32 DiscoveryStatus; /*0x04 */
854} MPI2_EVENT_DATA_SAS_DISCOVERY,
855 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
856 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
857
858/*SAS Discovery Event data Flags values */
859#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
860#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
861
862/*SAS Discovery Event data ReasonCode values */
863#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
864#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
865
866/*SAS Discovery Event data DiscoveryStatus values */
867#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
868#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
869#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
870#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
871#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
872#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
873#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
874#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
875#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
876#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
877#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
878#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
879#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
880#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
881#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
882#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
883#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
884#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
885#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
886#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
887
888/*SAS Broadcast Primitive Event data */
889
890typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
891 U8 PhyNum; /*0x00 */
892 U8 Port; /*0x01 */
893 U8 PortWidth; /*0x02 */
894 U8 Primitive; /*0x03 */
895} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
896 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
897 Mpi2EventDataSasBroadcastPrimitive_t,
898 *pMpi2EventDataSasBroadcastPrimitive_t;
899
900/*defines for the Primitive field */
901#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
902#define MPI2_EVENT_PRIMITIVE_SES (0x02)
903#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
904#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
905#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
906#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
907#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
908#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
909
910/*SAS Notify Primitive Event data */
911
912typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
913 U8 PhyNum; /*0x00 */
914 U8 Port; /*0x01 */
915 U8 Reserved1; /*0x02 */
916 U8 Primitive; /*0x03 */
917} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
918 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
919 Mpi2EventDataSasNotifyPrimitive_t,
920 *pMpi2EventDataSasNotifyPrimitive_t;
921
922/*defines for the Primitive field */
923#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
924#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
925#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
926#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
927
928/*SAS Initiator Device Status Change Event data */
929
930typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
931 U8 ReasonCode; /*0x00 */
932 U8 PhysicalPort; /*0x01 */
933 U16 DevHandle; /*0x02 */
934 U64 SASAddress; /*0x04 */
935} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
936 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
937 Mpi2EventDataSasInitDevStatusChange_t,
938 *pMpi2EventDataSasInitDevStatusChange_t;
939
940/*SAS Initiator Device Status Change event ReasonCode values */
941#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
942#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
943
944/*SAS Initiator Device Table Overflow Event data */
945
946typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
947 U16 MaxInit; /*0x00 */
948 U16 CurrentInit; /*0x02 */
949 U64 SASAddress; /*0x04 */
950} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
951 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
952 Mpi2EventDataSasInitTableOverflow_t,
953 *pMpi2EventDataSasInitTableOverflow_t;
954
955/*SAS Topology Change List Event data */
956
957/*
958 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
959 *one and check NumEntries at runtime.
960 */
961#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
962#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
963#endif
964
965typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
966 U16 AttachedDevHandle; /*0x00 */
967 U8 LinkRate; /*0x02 */
968 U8 PhyStatus; /*0x03 */
969} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
970 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
971
972typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
973 U16 EnclosureHandle; /*0x00 */
974 U16 ExpanderDevHandle; /*0x02 */
975 U8 NumPhys; /*0x04 */
976 U8 Reserved1; /*0x05 */
977 U16 Reserved2; /*0x06 */
978 U8 NumEntries; /*0x08 */
979 U8 StartPhyNum; /*0x09 */
980 U8 ExpStatus; /*0x0A */
981 U8 PhysicalPort; /*0x0B */
982 MPI2_EVENT_SAS_TOPO_PHY_ENTRY
983 PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */
984} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
985 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
986 Mpi2EventDataSasTopologyChangeList_t,
987 *pMpi2EventDataSasTopologyChangeList_t;
988
989/*values for the ExpStatus field */
990#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
991#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
992#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
993#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
994#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
995
996/*defines for the LinkRate field */
997#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
998#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
999#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
1000#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
1001
1002#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
1003#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
1004#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
1005#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
1006#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
1007#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
1008#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
1009#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
1010#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
1011#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
1012#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
1013#define MPI26_EVENT_SAS_TOPO_LR_RATE_22_5 (0x0C)
1014
1015/*values for the PhyStatus field */
1016#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
1017#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
1018/*values for the PhyStatus ReasonCode sub-field */
1019#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
1020#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
1021#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
1022#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
1023#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
1024#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
1025
1026/*SAS Enclosure Device Status Change Event data */
1027
1028typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
1029 U16 EnclosureHandle; /*0x00 */
1030 U8 ReasonCode; /*0x02 */
1031 U8 PhysicalPort; /*0x03 */
1032 U64 EnclosureLogicalID; /*0x04 */
1033 U16 NumSlots; /*0x0C */
1034 U16 StartSlot; /*0x0E */
1035 U32 PhyBits; /*0x10 */
1036} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1037 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
1038 Mpi2EventDataSasEnclDevStatusChange_t,
1039 *pMpi2EventDataSasEnclDevStatusChange_t,
1040 MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1041 *PTR_MPI26_EVENT_DATA_ENCL_DEV_STATUS_CHANGE,
1042 Mpi26EventDataEnclDevStatusChange_t,
1043 *pMpi26EventDataEnclDevStatusChange_t;
1044
1045/*SAS Enclosure Device Status Change event ReasonCode values */
1046#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
1047#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
1048
1049/*Enclosure Device Status Change event ReasonCode values */
1050#define MPI26_EVENT_ENCL_RC_ADDED (0x01)
1051#define MPI26_EVENT_ENCL_RC_NOT_RESPONDING (0x02)
1052
1053
1054typedef struct _MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR {
1055 U16 DevHandle; /*0x00 */
1056 U8 ReasonCode; /*0x02 */
1057 U8 PhysicalPort; /*0x03 */
1058 U32 Reserved1[2]; /*0x04 */
1059 U64 SASAddress; /*0x0C */
1060 U32 Reserved2[2]; /*0x14 */
1061} MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1062 *PTR_MPI25_EVENT_DATA_SAS_DEVICE_DISCOVERY_ERROR,
1063 Mpi25EventDataSasDeviceDiscoveryError_t,
1064 *pMpi25EventDataSasDeviceDiscoveryError_t;
1065
1066/*SAS Device Discovery Error Event data ReasonCode values */
1067#define MPI25_EVENT_SAS_DISC_ERR_SMP_FAILED (0x01)
1068#define MPI25_EVENT_SAS_DISC_ERR_SMP_TIMEOUT (0x02)
1069
1070/*SAS PHY Counter Event data */
1071
1072typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
1073 U64 TimeStamp; /*0x00 */
1074 U32 Reserved1; /*0x08 */
1075 U8 PhyEventCode; /*0x0C */
1076 U8 PhyNum; /*0x0D */
1077 U16 Reserved2; /*0x0E */
1078 U32 PhyEventInfo; /*0x10 */
1079 U8 CounterType; /*0x14 */
1080 U8 ThresholdWindow; /*0x15 */
1081 U8 TimeUnits; /*0x16 */
1082 U8 Reserved3; /*0x17 */
1083 U32 EventThreshold; /*0x18 */
1084 U16 ThresholdFlags; /*0x1C */
1085 U16 Reserved4; /*0x1E */
1086} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1087 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
1088 Mpi2EventDataSasPhyCounter_t,
1089 *pMpi2EventDataSasPhyCounter_t;
1090
1091/*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
1092 *for the PhyEventCode field */
1093
1094/*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
1095 *for the CounterType field */
1096
1097/*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
1098 *for the TimeUnits field */
1099
1100/*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
1101 *for the ThresholdFlags field */
1102
1103/*SAS Quiesce Event data */
1104
1105typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
1106 U8 ReasonCode; /*0x00 */
1107 U8 Reserved1; /*0x01 */
1108 U16 Reserved2; /*0x02 */
1109 U32 Reserved3; /*0x04 */
1110} MPI2_EVENT_DATA_SAS_QUIESCE,
1111 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
1112 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
1113
1114/*SAS Quiesce Event data ReasonCode values */
1115#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
1116#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
1117
1118/*Host Based Discovery Phy Event data */
1119
1120typedef struct _MPI2_EVENT_HBD_PHY_SAS {
1121 U8 Flags; /*0x00 */
1122 U8 NegotiatedLinkRate; /*0x01 */
1123 U8 PhyNum; /*0x02 */
1124 U8 PhysicalPort; /*0x03 */
1125 U32 Reserved1; /*0x04 */
1126 U8 InitialFrame[28]; /*0x08 */
1127} MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
1128 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
1129
1130/*values for the Flags field */
1131#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1132#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1133
1134/*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1135 *for the NegotiatedLinkRate field */
1136
1137typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1138 MPI2_EVENT_HBD_PHY_SAS Sas;
1139} MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1140 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1141
1142typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1143 U8 DescriptorType; /*0x00 */
1144 U8 Reserved1; /*0x01 */
1145 U16 Reserved2; /*0x02 */
1146 U32 Reserved3; /*0x04 */
1147 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */
1148} MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1149 Mpi2EventDataHbdPhy_t,
1150 *pMpi2EventDataMpi2EventDataHbdPhy_t;
1151
1152/*values for the DescriptorType field */
1153#define MPI2_EVENT_HBD_DT_SAS (0x01)
1154
1155
1156/*PCIe Device Status Change Event data (MPI v2.6 and later) */
1157
1158typedef struct _MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE {
1159 U16 TaskTag; /*0x00 */
1160 U8 ReasonCode; /*0x02 */
1161 U8 PhysicalPort; /*0x03 */
1162 U8 ASC; /*0x04 */
1163 U8 ASCQ; /*0x05 */
1164 U16 DevHandle; /*0x06 */
1165 U32 Reserved2; /*0x08 */
1166 U64 WWID; /*0x0C */
1167 U8 LUN[8]; /*0x14 */
1168} MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1169 *PTR_MPI26_EVENT_DATA_PCIE_DEVICE_STATUS_CHANGE,
1170 Mpi26EventDataPCIeDeviceStatusChange_t,
1171 *pMpi26EventDataPCIeDeviceStatusChange_t;
1172
1173/*PCIe Device Status Change Event data ReasonCode values */
1174#define MPI26_EVENT_PCIDEV_STAT_RC_SMART_DATA (0x05)
1175#define MPI26_EVENT_PCIDEV_STAT_RC_UNSUPPORTED (0x07)
1176#define MPI26_EVENT_PCIDEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
1177#define MPI26_EVENT_PCIDEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
1178#define MPI26_EVENT_PCIDEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
1179#define MPI26_EVENT_PCIDEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
1180#define MPI26_EVENT_PCIDEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
1181#define MPI26_EVENT_PCIDEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
1182#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
1183#define MPI26_EVENT_PCIDEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
1184#define MPI26_EVENT_PCIDEV_STAT_RC_DEV_INIT_FAILURE (0x10)
1185
1186
1187/*PCIe Enumeration Event data (MPI v2.6 and later) */
1188
1189typedef struct _MPI26_EVENT_DATA_PCIE_ENUMERATION {
1190 U8 Flags; /*0x00 */
1191 U8 ReasonCode; /*0x01 */
1192 U8 PhysicalPort; /*0x02 */
1193 U8 Reserved1; /*0x03 */
1194 U32 EnumerationStatus; /*0x04 */
1195} MPI26_EVENT_DATA_PCIE_ENUMERATION,
1196 *PTR_MPI26_EVENT_DATA_PCIE_ENUMERATION,
1197 Mpi26EventDataPCIeEnumeration_t,
1198 *pMpi26EventDataPCIeEnumeration_t;
1199
1200/*PCIe Enumeration Event data Flags values */
1201#define MPI26_EVENT_PCIE_ENUM_DEVICE_CHANGE (0x02)
1202#define MPI26_EVENT_PCIE_ENUM_IN_PROGRESS (0x01)
1203
1204/*PCIe Enumeration Event data ReasonCode values */
1205#define MPI26_EVENT_PCIE_ENUM_RC_STARTED (0x01)
1206#define MPI26_EVENT_PCIE_ENUM_RC_COMPLETED (0x02)
1207
1208/*PCIe Enumeration Event data EnumerationStatus values */
1209#define MPI26_EVENT_PCIE_ENUM_ES_MAX_SWITCHES_EXCEED (0x40000000)
1210#define MPI26_EVENT_PCIE_ENUM_ES_MAX_DEVICES_EXCEED (0x20000000)
1211#define MPI26_EVENT_PCIE_ENUM_ES_RESOURCES_EXHAUSTED (0x10000000)
1212
1213
1214/*PCIe Topology Change List Event data (MPI v2.6 and later) */
1215
1216/*
1217 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1218 *one and check NumEntries at runtime.
1219 */
1220#ifndef MPI26_EVENT_PCIE_TOPO_PORT_COUNT
1221#define MPI26_EVENT_PCIE_TOPO_PORT_COUNT (1)
1222#endif
1223
1224typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY {
1225 U16 AttachedDevHandle; /*0x00 */
1226 U8 PortStatus; /*0x02 */
1227 U8 Reserved1; /*0x03 */
1228 U8 CurrentPortInfo; /*0x04 */
1229 U8 Reserved2; /*0x05 */
1230 U8 PreviousPortInfo; /*0x06 */
1231 U8 Reserved3; /*0x07 */
1232} MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1233 *PTR_MPI26_EVENT_PCIE_TOPO_PORT_ENTRY,
1234 Mpi26EventPCIeTopoPortEntry_t,
1235 *pMpi26EventPCIeTopoPortEntry_t;
1236
1237/*PCIe Topology Change List Event data PortStatus values */
1238#define MPI26_EVENT_PCIE_TOPO_PS_DEV_ADDED (0x01)
1239#define MPI26_EVENT_PCIE_TOPO_PS_NOT_RESPONDING (0x02)
1240#define MPI26_EVENT_PCIE_TOPO_PS_PORT_CHANGED (0x03)
1241#define MPI26_EVENT_PCIE_TOPO_PS_NO_CHANGE (0x04)
1242#define MPI26_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING (0x05)
1243
1244/*PCIe Topology Change List Event data defines for CurrentPortInfo and
1245 *PreviousPortInfo
1246 */
1247#define MPI26_EVENT_PCIE_TOPO_PI_LANE_MASK (0xF0)
1248#define MPI26_EVENT_PCIE_TOPO_PI_LANES_UNKNOWN (0x00)
1249#define MPI26_EVENT_PCIE_TOPO_PI_1_LANE (0x10)
1250#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20)
1251#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30)
1252#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40)
1253
1254#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F)
1255#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
1256#define MPI26_EVENT_PCIE_TOPO_PI_RATE_DISABLED (0x01)
1257#define MPI26_EVENT_PCIE_TOPO_PI_RATE_2_5 (0x02)
1258#define MPI26_EVENT_PCIE_TOPO_PI_RATE_5_0 (0x03)
1259#define MPI26_EVENT_PCIE_TOPO_PI_RATE_8_0 (0x04)
1260#define MPI26_EVENT_PCIE_TOPO_PI_RATE_16_0 (0x05)
1261
1262typedef struct _MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST {
1263 U16 EnclosureHandle; /*0x00 */
1264 U16 SwitchDevHandle; /*0x02 */
1265 U8 NumPorts; /*0x04 */
1266 U8 Reserved1; /*0x05 */
1267 U16 Reserved2; /*0x06 */
1268 U8 NumEntries; /*0x08 */
1269 U8 StartPortNum; /*0x09 */
1270 U8 SwitchStatus; /*0x0A */
1271 U8 PhysicalPort; /*0x0B */
1272 MPI26_EVENT_PCIE_TOPO_PORT_ENTRY
1273 PortEntry[MPI26_EVENT_PCIE_TOPO_PORT_COUNT]; /*0x0C */
1274} MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1275 *PTR_MPI26_EVENT_DATA_PCIE_TOPOLOGY_CHANGE_LIST,
1276 Mpi26EventDataPCIeTopologyChangeList_t,
1277 *pMpi26EventDataPCIeTopologyChangeList_t;
1278
1279/*PCIe Topology Change List Event data SwitchStatus values */
1280#define MPI26_EVENT_PCIE_TOPO_SS_NO_PCIE_SWITCH (0x00)
1281#define MPI26_EVENT_PCIE_TOPO_SS_ADDED (0x01)
1282#define MPI26_EVENT_PCIE_TOPO_SS_NOT_RESPONDING (0x02)
1283#define MPI26_EVENT_PCIE_TOPO_SS_RESPONDING (0x03)
1284#define MPI26_EVENT_PCIE_TOPO_SS_DELAY_NOT_RESPONDING (0x04)
1285
1286/*PCIe Link Counter Event data (MPI v2.6 and later) */
1287
1288typedef struct _MPI26_EVENT_DATA_PCIE_LINK_COUNTER {
1289 U64 TimeStamp; /*0x00 */
1290 U32 Reserved1; /*0x08 */
1291 U8 LinkEventCode; /*0x0C */
1292 U8 LinkNum; /*0x0D */
1293 U16 Reserved2; /*0x0E */
1294 U32 LinkEventInfo; /*0x10 */
1295 U8 CounterType; /*0x14 */
1296 U8 ThresholdWindow; /*0x15 */
1297 U8 TimeUnits; /*0x16 */
1298 U8 Reserved3; /*0x17 */
1299 U32 EventThreshold; /*0x18 */
1300 U16 ThresholdFlags; /*0x1C */
1301 U16 Reserved4; /*0x1E */
1302} MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1303 *PTR_MPI26_EVENT_DATA_PCIE_LINK_COUNTER,
1304 Mpi26EventDataPcieLinkCounter_t, *pMpi26EventDataPcieLinkCounter_t;
1305
1306
1307/*use MPI26_PCIELINK3_EVTCODE_ values from mpi2_cnfg.h for the LinkEventCode
1308 *field
1309 */
1310
1311/*use MPI26_PCIELINK3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType
1312 *field
1313 */
1314
1315/*use MPI26_PCIELINK3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits
1316 *field
1317 */
1318
1319/*use MPI26_PCIELINK3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags
1320 *field
1321 */
1322
1323/****************************************************************************
1324* EventAck message
1325****************************************************************************/
1326
1327/*EventAck Request message */
1328typedef struct _MPI2_EVENT_ACK_REQUEST {
1329 U16 Reserved1; /*0x00 */
1330 U8 ChainOffset; /*0x02 */
1331 U8 Function; /*0x03 */
1332 U16 Reserved2; /*0x04 */
1333 U8 Reserved3; /*0x06 */
1334 U8 MsgFlags; /*0x07 */
1335 U8 VP_ID; /*0x08 */
1336 U8 VF_ID; /*0x09 */
1337 U16 Reserved4; /*0x0A */
1338 U16 Event; /*0x0C */
1339 U16 Reserved5; /*0x0E */
1340 U32 EventContext; /*0x10 */
1341} MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1342 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1343
1344/*EventAck Reply message */
1345typedef struct _MPI2_EVENT_ACK_REPLY {
1346 U16 Reserved1; /*0x00 */
1347 U8 MsgLength; /*0x02 */
1348 U8 Function; /*0x03 */
1349 U16 Reserved2; /*0x04 */
1350 U8 Reserved3; /*0x06 */
1351 U8 MsgFlags; /*0x07 */
1352 U8 VP_ID; /*0x08 */
1353 U8 VF_ID; /*0x09 */
1354 U16 Reserved4; /*0x0A */
1355 U16 Reserved5; /*0x0C */
1356 U16 IOCStatus; /*0x0E */
1357 U32 IOCLogInfo; /*0x10 */
1358} MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1359 Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1360
1361/****************************************************************************
1362* SendHostMessage message
1363****************************************************************************/
1364
1365/*SendHostMessage Request message */
1366typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1367 U16 HostDataLength; /*0x00 */
1368 U8 ChainOffset; /*0x02 */
1369 U8 Function; /*0x03 */
1370 U16 Reserved1; /*0x04 */
1371 U8 Reserved2; /*0x06 */
1372 U8 MsgFlags; /*0x07 */
1373 U8 VP_ID; /*0x08 */
1374 U8 VF_ID; /*0x09 */
1375 U16 Reserved3; /*0x0A */
1376 U8 Reserved4; /*0x0C */
1377 U8 DestVF_ID; /*0x0D */
1378 U16 Reserved5; /*0x0E */
1379 U32 Reserved6; /*0x10 */
1380 U32 Reserved7; /*0x14 */
1381 U32 Reserved8; /*0x18 */
1382 U32 Reserved9; /*0x1C */
1383 U32 Reserved10; /*0x20 */
1384 U32 HostData[1]; /*0x24 */
1385} MPI2_SEND_HOST_MESSAGE_REQUEST,
1386 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1387 Mpi2SendHostMessageRequest_t,
1388 *pMpi2SendHostMessageRequest_t;
1389
1390/*SendHostMessage Reply message */
1391typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1392 U16 HostDataLength; /*0x00 */
1393 U8 MsgLength; /*0x02 */
1394 U8 Function; /*0x03 */
1395 U16 Reserved1; /*0x04 */
1396 U8 Reserved2; /*0x06 */
1397 U8 MsgFlags; /*0x07 */
1398 U8 VP_ID; /*0x08 */
1399 U8 VF_ID; /*0x09 */
1400 U16 Reserved3; /*0x0A */
1401 U16 Reserved4; /*0x0C */
1402 U16 IOCStatus; /*0x0E */
1403 U32 IOCLogInfo; /*0x10 */
1404} MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1405 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1406
1407/****************************************************************************
1408* FWDownload message
1409****************************************************************************/
1410
1411/*MPI v2.0 FWDownload Request message */
1412typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1413 U8 ImageType; /*0x00 */
1414 U8 Reserved1; /*0x01 */
1415 U8 ChainOffset; /*0x02 */
1416 U8 Function; /*0x03 */
1417 U16 Reserved2; /*0x04 */
1418 U8 Reserved3; /*0x06 */
1419 U8 MsgFlags; /*0x07 */
1420 U8 VP_ID; /*0x08 */
1421 U8 VF_ID; /*0x09 */
1422 U16 Reserved4; /*0x0A */
1423 U32 TotalImageSize; /*0x0C */
1424 U32 Reserved5; /*0x10 */
1425 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1426} MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1427 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1428
1429#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1430
1431#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1432#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1433#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1434#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1435#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1436#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1437#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1438#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1439#define MPI2_FW_DOWNLOAD_ITYPE_PUBLIC_KEY (0x0C)
1440#define MPI2_FW_DOWNLOAD_ITYPE_CBB_BACKUP (0x0D)
1441#define MPI2_FW_DOWNLOAD_ITYPE_SBR (0x0E)
1442#define MPI2_FW_DOWNLOAD_ITYPE_SBR_BACKUP (0x0F)
1443#define MPI2_FW_DOWNLOAD_ITYPE_HIIM (0x10)
1444#define MPI2_FW_DOWNLOAD_ITYPE_HIIA (0x11)
1445#define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12)
1446#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13)
1447#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14)
1448#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1449
1450/*MPI v2.0 FWDownload TransactionContext Element */
1451typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1452 U8 Reserved1; /*0x00 */
1453 U8 ContextSize; /*0x01 */
1454 U8 DetailsLength; /*0x02 */
1455 U8 Flags; /*0x03 */
1456 U32 Reserved2; /*0x04 */
1457 U32 ImageOffset; /*0x08 */
1458 U32 ImageSize; /*0x0C */
1459} MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1460 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1461
1462/*MPI v2.5 FWDownload Request message */
1463typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1464 U8 ImageType; /*0x00 */
1465 U8 Reserved1; /*0x01 */
1466 U8 ChainOffset; /*0x02 */
1467 U8 Function; /*0x03 */
1468 U16 Reserved2; /*0x04 */
1469 U8 Reserved3; /*0x06 */
1470 U8 MsgFlags; /*0x07 */
1471 U8 VP_ID; /*0x08 */
1472 U8 VF_ID; /*0x09 */
1473 U16 Reserved4; /*0x0A */
1474 U32 TotalImageSize; /*0x0C */
1475 U32 Reserved5; /*0x10 */
1476 U32 Reserved6; /*0x14 */
1477 U32 ImageOffset; /*0x18 */
1478 U32 ImageSize; /*0x1C */
1479 MPI25_SGE_IO_UNION SGL; /*0x20 */
1480} MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1481 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1482
1483/*FWDownload Reply message */
1484typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1485 U8 ImageType; /*0x00 */
1486 U8 Reserved1; /*0x01 */
1487 U8 MsgLength; /*0x02 */
1488 U8 Function; /*0x03 */
1489 U16 Reserved2; /*0x04 */
1490 U8 Reserved3; /*0x06 */
1491 U8 MsgFlags; /*0x07 */
1492 U8 VP_ID; /*0x08 */
1493 U8 VF_ID; /*0x09 */
1494 U16 Reserved4; /*0x0A */
1495 U16 Reserved5; /*0x0C */
1496 U16 IOCStatus; /*0x0E */
1497 U32 IOCLogInfo; /*0x10 */
1498} MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1499 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1500
1501/****************************************************************************
1502* FWUpload message
1503****************************************************************************/
1504
1505/*MPI v2.0 FWUpload Request message */
1506typedef struct _MPI2_FW_UPLOAD_REQUEST {
1507 U8 ImageType; /*0x00 */
1508 U8 Reserved1; /*0x01 */
1509 U8 ChainOffset; /*0x02 */
1510 U8 Function; /*0x03 */
1511 U16 Reserved2; /*0x04 */
1512 U8 Reserved3; /*0x06 */
1513 U8 MsgFlags; /*0x07 */
1514 U8 VP_ID; /*0x08 */
1515 U8 VF_ID; /*0x09 */
1516 U16 Reserved4; /*0x0A */
1517 U32 Reserved5; /*0x0C */
1518 U32 Reserved6; /*0x10 */
1519 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1520} MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1521 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1522
1523#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1524#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1525#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1526#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1527#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1528#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1529#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1530#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1531#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1532#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1533#define MPI2_FW_UPLOAD_ITYPE_CBB_BACKUP (0x0D)
1534#define MPI2_FW_UPLOAD_ITYPE_SBR (0x0E)
1535#define MPI2_FW_UPLOAD_ITYPE_SBR_BACKUP (0x0F)
1536#define MPI2_FW_UPLOAD_ITYPE_HIIM (0x10)
1537#define MPI2_FW_UPLOAD_ITYPE_HIIA (0x11)
1538#define MPI2_FW_UPLOAD_ITYPE_CTLR (0x12)
1539#define MPI2_FW_UPLOAD_ITYPE_IMR_FIRMWARE (0x13)
1540#define MPI2_FW_UPLOAD_ITYPE_MR_NVDATA (0x14)
1541
1542
1543/*MPI v2.0 FWUpload TransactionContext Element */
1544typedef struct _MPI2_FW_UPLOAD_TCSGE {
1545 U8 Reserved1; /*0x00 */
1546 U8 ContextSize; /*0x01 */
1547 U8 DetailsLength; /*0x02 */
1548 U8 Flags; /*0x03 */
1549 U32 Reserved2; /*0x04 */
1550 U32 ImageOffset; /*0x08 */
1551 U32 ImageSize; /*0x0C */
1552} MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1553 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1554
1555/*MPI v2.5 FWUpload Request message */
1556typedef struct _MPI25_FW_UPLOAD_REQUEST {
1557 U8 ImageType; /*0x00 */
1558 U8 Reserved1; /*0x01 */
1559 U8 ChainOffset; /*0x02 */
1560 U8 Function; /*0x03 */
1561 U16 Reserved2; /*0x04 */
1562 U8 Reserved3; /*0x06 */
1563 U8 MsgFlags; /*0x07 */
1564 U8 VP_ID; /*0x08 */
1565 U8 VF_ID; /*0x09 */
1566 U16 Reserved4; /*0x0A */
1567 U32 Reserved5; /*0x0C */
1568 U32 Reserved6; /*0x10 */
1569 U32 Reserved7; /*0x14 */
1570 U32 ImageOffset; /*0x18 */
1571 U32 ImageSize; /*0x1C */
1572 MPI25_SGE_IO_UNION SGL; /*0x20 */
1573} MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1574 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1575
1576/*FWUpload Reply message */
1577typedef struct _MPI2_FW_UPLOAD_REPLY {
1578 U8 ImageType; /*0x00 */
1579 U8 Reserved1; /*0x01 */
1580 U8 MsgLength; /*0x02 */
1581 U8 Function; /*0x03 */
1582 U16 Reserved2; /*0x04 */
1583 U8 Reserved3; /*0x06 */
1584 U8 MsgFlags; /*0x07 */
1585 U8 VP_ID; /*0x08 */
1586 U8 VF_ID; /*0x09 */
1587 U16 Reserved4; /*0x0A */
1588 U16 Reserved5; /*0x0C */
1589 U16 IOCStatus; /*0x0E */
1590 U32 IOCLogInfo; /*0x10 */
1591 U32 ActualImageSize; /*0x14 */
1592} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1593 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1594
1595/*FW Image Header */
1596typedef struct _MPI2_FW_IMAGE_HEADER {
1597 U32 Signature; /*0x00 */
1598 U32 Signature0; /*0x04 */
1599 U32 Signature1; /*0x08 */
1600 U32 Signature2; /*0x0C */
1601 MPI2_VERSION_UNION MPIVersion; /*0x10 */
1602 MPI2_VERSION_UNION FWVersion; /*0x14 */
1603 MPI2_VERSION_UNION NVDATAVersion; /*0x18 */
1604 MPI2_VERSION_UNION PackageVersion; /*0x1C */
1605 U16 VendorID; /*0x20 */
1606 U16 ProductID; /*0x22 */
1607 U16 ProtocolFlags; /*0x24 */
1608 U16 Reserved26; /*0x26 */
1609 U32 IOCCapabilities; /*0x28 */
1610 U32 ImageSize; /*0x2C */
1611 U32 NextImageHeaderOffset; /*0x30 */
1612 U32 Checksum; /*0x34 */
1613 U32 Reserved38; /*0x38 */
1614 U32 Reserved3C; /*0x3C */
1615 U32 Reserved40; /*0x40 */
1616 U32 Reserved44; /*0x44 */
1617 U32 Reserved48; /*0x48 */
1618 U32 Reserved4C; /*0x4C */
1619 U32 Reserved50; /*0x50 */
1620 U32 Reserved54; /*0x54 */
1621 U32 Reserved58; /*0x58 */
1622 U32 Reserved5C; /*0x5C */
1623 U32 BootFlags; /*0x60 */
1624 U32 FirmwareVersionNameWhat; /*0x64 */
1625 U8 FirmwareVersionName[32]; /*0x68 */
1626 U32 VendorNameWhat; /*0x88 */
1627 U8 VendorName[32]; /*0x8C */
1628 U32 PackageNameWhat; /*0x88 */
1629 U8 PackageName[32]; /*0x8C */
1630 U32 ReservedD0; /*0xD0 */
1631 U32 ReservedD4; /*0xD4 */
1632 U32 ReservedD8; /*0xD8 */
1633 U32 ReservedDC; /*0xDC */
1634 U32 ReservedE0; /*0xE0 */
1635 U32 ReservedE4; /*0xE4 */
1636 U32 ReservedE8; /*0xE8 */
1637 U32 ReservedEC; /*0xEC */
1638 U32 ReservedF0; /*0xF0 */
1639 U32 ReservedF4; /*0xF4 */
1640 U32 ReservedF8; /*0xF8 */
1641 U32 ReservedFC; /*0xFC */
1642} MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1643 Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1644
1645/*Signature field */
1646#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1647#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1648#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1649#define MPI26_FW_HEADER_SIGNATURE (0xEB000000)
1650
1651/*Signature0 field */
1652#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1653#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1654/* Last byte is defined by architecture */
1655#define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500)
1656#define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A)
1657#define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00)
1658#define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01)
1659/* legacy (0x5AEAA55A) */
1660#define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02)
1661#define MPI26_FW_HEADER_SIGNATURE0 \
1662 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0)
1663#define MPI26_FW_HEADER_SIGNATURE0_3516 \
1664 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1)
1665#define MPI26_FW_HEADER_SIGNATURE0_4008 \
1666 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3)
1667
1668/*Signature1 field */
1669#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1670#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1671#define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5)
1672
1673/*Signature2 field */
1674#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1675#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1676#define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA)
1677
1678/*defines for using the ProductID field */
1679#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1680#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1681
1682#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1683#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1684#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1685#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1686
1687#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1688/*SAS ProductID Family bits */
1689#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1690#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1691#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1692#define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028)
1693#define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031)
1694
1695/*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1696
1697/*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1698
1699#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1700#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1701#define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60)
1702#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1703
1704#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1705
1706#define MPI2_FW_HEADER_SIZE (0x100)
1707
1708/*Extended Image Header */
1709typedef struct _MPI2_EXT_IMAGE_HEADER {
1710 U8 ImageType; /*0x00 */
1711 U8 Reserved1; /*0x01 */
1712 U16 Reserved2; /*0x02 */
1713 U32 Checksum; /*0x04 */
1714 U32 ImageSize; /*0x08 */
1715 U32 NextImageHeaderOffset; /*0x0C */
1716 U32 PackageVersion; /*0x10 */
1717 U32 Reserved3; /*0x14 */
1718 U32 Reserved4; /*0x18 */
1719 U32 Reserved5; /*0x1C */
1720 U8 IdentifyString[32]; /*0x20 */
1721} MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1722 Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1723
1724/*useful offsets */
1725#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1726#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1727#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1728
1729#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1730
1731/*defines for the ImageType field */
1732#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1733#define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1734#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1735#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1736#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1737#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1738#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1739#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1740#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09)
1741#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1742#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1743
1744#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1745
1746/*FLASH Layout Extended Image Data */
1747
1748/*
1749 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1750 *one and check RegionsPerLayout at runtime.
1751 */
1752#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1753#define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1754#endif
1755
1756/*
1757 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1758 *one and check NumberOfLayouts at runtime.
1759 */
1760#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1761#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1762#endif
1763
1764typedef struct _MPI2_FLASH_REGION {
1765 U8 RegionType; /*0x00 */
1766 U8 Reserved1; /*0x01 */
1767 U16 Reserved2; /*0x02 */
1768 U32 RegionOffset; /*0x04 */
1769 U32 RegionSize; /*0x08 */
1770 U32 Reserved3; /*0x0C */
1771} MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1772 Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1773
1774typedef struct _MPI2_FLASH_LAYOUT {
1775 U32 FlashSize; /*0x00 */
1776 U32 Reserved1; /*0x04 */
1777 U32 Reserved2; /*0x08 */
1778 U32 Reserved3; /*0x0C */
1779 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
1780} MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1781 Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1782
1783typedef struct _MPI2_FLASH_LAYOUT_DATA {
1784 U8 ImageRevision; /*0x00 */
1785 U8 Reserved1; /*0x01 */
1786 U8 SizeOfRegion; /*0x02 */
1787 U8 Reserved2; /*0x03 */
1788 U16 NumberOfLayouts; /*0x04 */
1789 U16 RegionsPerLayout; /*0x06 */
1790 U16 MinimumSectorAlignment; /*0x08 */
1791 U16 Reserved3; /*0x0A */
1792 U32 Reserved4; /*0x0C */
1793 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
1794} MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1795 Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1796
1797/*defines for the RegionType field */
1798#define MPI2_FLASH_REGION_UNUSED (0x00)
1799#define MPI2_FLASH_REGION_FIRMWARE (0x01)
1800#define MPI2_FLASH_REGION_BIOS (0x02)
1801#define MPI2_FLASH_REGION_NVDATA (0x03)
1802#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1803#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1804#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1805#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1806#define MPI2_FLASH_REGION_MEGARAID (0x09)
1807#define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A)
1808#define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK)
1809#define MPI2_FLASH_REGION_CBB_BACKUP (0x0D)
1810#define MPI2_FLASH_REGION_SBR (0x0E)
1811#define MPI2_FLASH_REGION_SBR_BACKUP (0x0F)
1812#define MPI2_FLASH_REGION_HIIM (0x10)
1813#define MPI2_FLASH_REGION_HIIA (0x11)
1814#define MPI2_FLASH_REGION_CTLR (0x12)
1815#define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13)
1816#define MPI2_FLASH_REGION_MR_NVDATA (0x14)
1817
1818/*ImageRevision */
1819#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1820
1821/*Supported Devices Extended Image Data */
1822
1823/*
1824 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1825 *one and check NumberOfDevices at runtime.
1826 */
1827#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1828#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1829#endif
1830
1831typedef struct _MPI2_SUPPORTED_DEVICE {
1832 U16 DeviceID; /*0x00 */
1833 U16 VendorID; /*0x02 */
1834 U16 DeviceIDMask; /*0x04 */
1835 U16 Reserved1; /*0x06 */
1836 U8 LowPCIRev; /*0x08 */
1837 U8 HighPCIRev; /*0x09 */
1838 U16 Reserved2; /*0x0A */
1839 U32 Reserved3; /*0x0C */
1840} MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1841 Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1842
1843typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1844 U8 ImageRevision; /*0x00 */
1845 U8 Reserved1; /*0x01 */
1846 U8 NumberOfDevices; /*0x02 */
1847 U8 Reserved2; /*0x03 */
1848 U32 Reserved3; /*0x04 */
1849 MPI2_SUPPORTED_DEVICE
1850 SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1851} MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1852 Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1853
1854/*ImageRevision */
1855#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1856
1857/*Init Extended Image Data */
1858
1859typedef struct _MPI2_INIT_IMAGE_FOOTER {
1860 U32 BootFlags; /*0x00 */
1861 U32 ImageSize; /*0x04 */
1862 U32 Signature0; /*0x08 */
1863 U32 Signature1; /*0x0C */
1864 U32 Signature2; /*0x10 */
1865 U32 ResetVector; /*0x14 */
1866} MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1867 Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1868
1869/*defines for the BootFlags field */
1870#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1871
1872/*defines for the ImageSize field */
1873#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1874
1875/*defines for the Signature0 field */
1876#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1877#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1878
1879/*defines for the Signature1 field */
1880#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1881#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1882
1883/*defines for the Signature2 field */
1884#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1885#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1886
1887/*Signature fields as individual bytes */
1888#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1889#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1890#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1891#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1892
1893#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1894#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1895#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1896#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1897
1898#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1899#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1900#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1901#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1902
1903/*defines for the ResetVector field */
1904#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1905
1906
1907/* Encrypted Hash Extended Image Data */
1908
1909typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1910 U8 HashImageType; /* 0x00 */
1911 U8 HashAlgorithm; /* 0x01 */
1912 U8 EncryptionAlgorithm; /* 0x02 */
1913 U8 Reserved1; /* 0x03 */
1914 U32 Reserved2; /* 0x04 */
1915 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */
1916} MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1917Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t;
1918
1919/* values for HashImageType */
1920#define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00)
1921#define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01)
1922#define MPI25_HASH_IMAGE_TYPE_BIOS (0x02)
1923
1924/* values for HashAlgorithm */
1925#define MPI25_HASH_ALGORITHM_UNUSED (0x00)
1926#define MPI25_HASH_ALGORITHM_SHA256 (0x01)
1927
1928/* values for EncryptionAlgorithm */
1929#define MPI25_ENCRYPTION_ALG_UNUSED (0x00)
1930#define MPI25_ENCRYPTION_ALG_RSA256 (0x01)
1931
1932typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1933 U8 ImageVersion; /* 0x00 */
1934 U8 NumHash; /* 0x01 */
1935 U16 Reserved1; /* 0x02 */
1936 U32 Reserved2; /* 0x04 */
1937 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */
1938} MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA,
1939Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t;
1940
1941
1942/****************************************************************************
1943* PowerManagementControl message
1944****************************************************************************/
1945
1946/*PowerManagementControl Request message */
1947typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1948 U8 Feature; /*0x00 */
1949 U8 Reserved1; /*0x01 */
1950 U8 ChainOffset; /*0x02 */
1951 U8 Function; /*0x03 */
1952 U16 Reserved2; /*0x04 */
1953 U8 Reserved3; /*0x06 */
1954 U8 MsgFlags; /*0x07 */
1955 U8 VP_ID; /*0x08 */
1956 U8 VF_ID; /*0x09 */
1957 U16 Reserved4; /*0x0A */
1958 U8 Parameter1; /*0x0C */
1959 U8 Parameter2; /*0x0D */
1960 U8 Parameter3; /*0x0E */
1961 U8 Parameter4; /*0x0F */
1962 U32 Reserved5; /*0x10 */
1963 U32 Reserved6; /*0x14 */
1964} MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1965 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1966
1967/*defines for the Feature field */
1968#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1969#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1970#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */
1971#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1972#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05)
1973#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1974#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1975
1976/*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1977/*Parameter1 contains a PHY number */
1978/*Parameter2 indicates power condition action using these defines */
1979#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1980#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1981#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1982/*Parameter3 and Parameter4 are reserved */
1983
1984/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1985 * Feature */
1986/*Parameter1 contains SAS port width modulation group number */
1987/*Parameter2 indicates IOC action using these defines */
1988#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1989#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1990#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1991/*Parameter3 indicates desired modulation level using these defines */
1992#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1993#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1994#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1995#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1996/*Parameter4 is reserved */
1997
1998/*this next set (_PCIE_LINK) is obsolete */
1999/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
2000/*Parameter1 indicates desired PCIe link speed using these defines */
2001#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */
2002#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */
2003#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */
2004/*Parameter2 indicates desired PCIe link width using these defines */
2005#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */
2006#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */
2007#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */
2008#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */
2009/*Parameter3 and Parameter4 are reserved */
2010
2011/*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
2012/*Parameter1 indicates desired IOC hardware clock speed using these defines */
2013#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
2014#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
2015#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
2016#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
2017/*Parameter2, Parameter3, and Parameter4 are reserved */
2018
2019/*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
2020/*Parameter1 indicates host action regarding global power management mode */
2021#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)
2022#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)
2023#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)
2024/*Parameter2 indicates the requested global power management mode */
2025#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)
2026#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)
2027#define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)
2028/*Parameter3 and Parameter4 are reserved */
2029
2030/*PowerManagementControl Reply message */
2031typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
2032 U8 Feature; /*0x00 */
2033 U8 Reserved1; /*0x01 */
2034 U8 MsgLength; /*0x02 */
2035 U8 Function; /*0x03 */
2036 U16 Reserved2; /*0x04 */
2037 U8 Reserved3; /*0x06 */
2038 U8 MsgFlags; /*0x07 */
2039 U8 VP_ID; /*0x08 */
2040 U8 VF_ID; /*0x09 */
2041 U16 Reserved4; /*0x0A */
2042 U16 Reserved5; /*0x0C */
2043 U16 IOCStatus; /*0x0E */
2044 U32 IOCLogInfo; /*0x10 */
2045} MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
2046 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
2047
2048/****************************************************************************
2049* IO Unit Control messages (MPI v2.6 and later only.)
2050****************************************************************************/
2051
2052/* IO Unit Control Request Message */
2053typedef struct _MPI26_IOUNIT_CONTROL_REQUEST {
2054 U8 Operation; /* 0x00 */
2055 U8 Reserved1; /* 0x01 */
2056 U8 ChainOffset; /* 0x02 */
2057 U8 Function; /* 0x03 */
2058 U16 DevHandle; /* 0x04 */
2059 U8 IOCParameter; /* 0x06 */
2060 U8 MsgFlags; /* 0x07 */
2061 U8 VP_ID; /* 0x08 */
2062 U8 VF_ID; /* 0x09 */
2063 U16 Reserved3; /* 0x0A */
2064 U16 Reserved4; /* 0x0C */
2065 U8 PhyNum; /* 0x0E */
2066 U8 PrimFlags; /* 0x0F */
2067 U32 Primitive; /* 0x10 */
2068 U8 LookupMethod; /* 0x14 */
2069 U8 Reserved5; /* 0x15 */
2070 U16 SlotNumber; /* 0x16 */
2071 U64 LookupAddress; /* 0x18 */
2072 U32 IOCParameterValue; /* 0x20 */
2073 U32 Reserved7; /* 0x24 */
2074 U32 Reserved8; /* 0x28 */
2075} MPI26_IOUNIT_CONTROL_REQUEST,
2076 *PTR_MPI26_IOUNIT_CONTROL_REQUEST,
2077 Mpi26IoUnitControlRequest_t,
2078 *pMpi26IoUnitControlRequest_t;
2079
2080/* values for the Operation field */
2081#define MPI26_CTRL_OP_CLEAR_ALL_PERSISTENT (0x02)
2082#define MPI26_CTRL_OP_SAS_PHY_LINK_RESET (0x06)
2083#define MPI26_CTRL_OP_SAS_PHY_HARD_RESET (0x07)
2084#define MPI26_CTRL_OP_PHY_CLEAR_ERROR_LOG (0x08)
2085#define MPI26_CTRL_OP_LINK_CLEAR_ERROR_LOG (0x09)
2086#define MPI26_CTRL_OP_SAS_SEND_PRIMITIVE (0x0A)
2087#define MPI26_CTRL_OP_FORCE_FULL_DISCOVERY (0x0B)
2088#define MPI26_CTRL_OP_REMOVE_DEVICE (0x0D)
2089#define MPI26_CTRL_OP_LOOKUP_MAPPING (0x0E)
2090#define MPI26_CTRL_OP_SET_IOC_PARAMETER (0x0F)
2091#define MPI26_CTRL_OP_ENABLE_FP_DEVICE (0x10)
2092#define MPI26_CTRL_OP_DISABLE_FP_DEVICE (0x11)
2093#define MPI26_CTRL_OP_ENABLE_FP_ALL (0x12)
2094#define MPI26_CTRL_OP_DISABLE_FP_ALL (0x13)
2095#define MPI26_CTRL_OP_DEV_ENABLE_NCQ (0x14)
2096#define MPI26_CTRL_OP_DEV_DISABLE_NCQ (0x15)
2097#define MPI26_CTRL_OP_SHUTDOWN (0x16)
2098#define MPI26_CTRL_OP_DEV_ENABLE_PERSIST_CONNECTION (0x17)
2099#define MPI26_CTRL_OP_DEV_DISABLE_PERSIST_CONNECTION (0x18)
2100#define MPI26_CTRL_OP_DEV_CLOSE_PERSIST_CONNECTION (0x19)
2101#define MPI26_CTRL_OP_ENABLE_NVME_SGL_FORMAT (0x1A)
2102#define MPI26_CTRL_OP_DISABLE_NVME_SGL_FORMAT (0x1B)
2103#define MPI26_CTRL_OP_PRODUCT_SPECIFIC_MIN (0x80)
2104
2105/* values for the PrimFlags field */
2106#define MPI26_CTRL_PRIMFLAGS_SINGLE (0x08)
2107#define MPI26_CTRL_PRIMFLAGS_TRIPLE (0x02)
2108#define MPI26_CTRL_PRIMFLAGS_REDUNDANT (0x01)
2109
2110/* values for the LookupMethod field */
2111#define MPI26_CTRL_LOOKUP_METHOD_WWID_ADDRESS (0x01)
2112#define MPI26_CTRL_LOOKUP_METHOD_ENCLOSURE_SLOT (0x02)
2113#define MPI26_CTRL_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
2114
2115
2116/* IO Unit Control Reply Message */
2117typedef struct _MPI26_IOUNIT_CONTROL_REPLY {
2118 U8 Operation; /* 0x00 */
2119 U8 Reserved1; /* 0x01 */
2120 U8 MsgLength; /* 0x02 */
2121 U8 Function; /* 0x03 */
2122 U16 DevHandle; /* 0x04 */
2123 U8 IOCParameter; /* 0x06 */
2124 U8 MsgFlags; /* 0x07 */
2125 U8 VP_ID; /* 0x08 */
2126 U8 VF_ID; /* 0x09 */
2127 U16 Reserved3; /* 0x0A */
2128 U16 Reserved4; /* 0x0C */
2129 U16 IOCStatus; /* 0x0E */
2130 U32 IOCLogInfo; /* 0x10 */
2131} MPI26_IOUNIT_CONTROL_REPLY,
2132 *PTR_MPI26_IOUNIT_CONTROL_REPLY,
2133 Mpi26IoUnitControlReply_t,
2134 *pMpi26IoUnitControlReply_t;
2135
2136
2137#endif