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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
4 * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
5 * Copyright (c) 2012 NeilBrown <neilb@suse.de>
6 * Heavily based on earlier code which is:
7 * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
8 *
9 * Also based on pwm-samsung.c
10 *
11 * Description:
12 * This file is the core OMAP support for the generic, Linux
13 * PWM driver / controller, using the OMAP's dual-mode timers
14 * with a timer counter that goes up. When it overflows it gets
15 * reloaded with the load value and the pwm output goes up.
16 * When counter matches with match register, the output goes down.
17 * Reference Manual: https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
18 *
19 * Limitations:
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
23 * we cannot prevent in software that the output might produce
24 * a period with mixed settings. Especially when period/duty_cyle
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
26 * can get updated as below based on the current timer counter:
27 * - period for current cycle = current_period + new period
28 * - duty_cycle for current period = current period + new duty_cycle.
29 * - PWM OMAP DM timer cannot change the polarity when pwm is active. When
30 * user requests a change in polarity when in active state:
31 * - PWM is stopped abruptly(without completing the current cycle)
32 * - Polarity is changed
33 * - A fresh cycle is started.
34 */
35
36#include <linux/clk.h>
37#include <linux/err.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/of.h>
41#include <linux/of_platform.h>
42#include <clocksource/timer-ti-dm.h>
43#include <linux/platform_data/dmtimer-omap.h>
44#include <linux/platform_device.h>
45#include <linux/pm_runtime.h>
46#include <linux/pwm.h>
47#include <linux/slab.h>
48#include <linux/time.h>
49
50#define DM_TIMER_LOAD_MIN 0xfffffffe
51#define DM_TIMER_MAX 0xffffffff
52
53/**
54 * struct pwm_omap_dmtimer_chip - Structure representing a pwm chip
55 * corresponding to omap dmtimer.
56 * @chip: PWM chip structure representing PWM controller
57 * @dm_timer: Pointer to omap dm timer.
58 * @pdata: Pointer to omap dm timer ops.
59 * @dm_timer_pdev: Pointer to omap dm timer platform device
60 */
61struct pwm_omap_dmtimer_chip {
62 struct pwm_chip chip;
63 /* Mutex to protect pwm apply state */
64 struct omap_dm_timer *dm_timer;
65 const struct omap_dm_timer_ops *pdata;
66 struct platform_device *dm_timer_pdev;
67};
68
69static inline struct pwm_omap_dmtimer_chip *
70to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
71{
72 return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
73}
74
75/**
76 * pwm_omap_dmtimer_get_clock_cycles() - Get clock cycles in a time frame
77 * @clk_rate: pwm timer clock rate
78 * @ns: time frame in nano seconds.
79 *
80 * Return number of clock cycles in a given period(ins ns).
81 */
82static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
83{
84 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
85}
86
87/**
88 * pwm_omap_dmtimer_start() - Start the pwm omap dm timer in pwm mode
89 * @omap: Pointer to pwm omap dm timer chip
90 */
91static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
92{
93 /*
94 * According to OMAP 4 TRM section 22.2.4.10 the counter should be
95 * started at 0xFFFFFFFE when overflow and match is used to ensure
96 * that the PWM line is toggled on the first event.
97 *
98 * Note that omap_dm_timer_enable/disable is for register access and
99 * not the timer counter itself.
100 */
101 omap->pdata->enable(omap->dm_timer);
102 omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
103 omap->pdata->disable(omap->dm_timer);
104
105 omap->pdata->start(omap->dm_timer);
106}
107
108/**
109 * pwm_omap_dmtimer_is_enabled() - Detect if the pwm is enabled.
110 * @omap: Pointer to pwm omap dm timer chip
111 *
112 * Return true if pwm is enabled else false.
113 */
114static bool pwm_omap_dmtimer_is_enabled(struct pwm_omap_dmtimer_chip *omap)
115{
116 u32 status;
117
118 status = omap->pdata->get_pwm_status(omap->dm_timer);
119
120 return !!(status & OMAP_TIMER_CTRL_ST);
121}
122
123/**
124 * pwm_omap_dmtimer_polarity() - Detect the polarity of pwm.
125 * @omap: Pointer to pwm omap dm timer chip
126 *
127 * Return the polarity of pwm.
128 */
129static int pwm_omap_dmtimer_polarity(struct pwm_omap_dmtimer_chip *omap)
130{
131 u32 status;
132
133 status = omap->pdata->get_pwm_status(omap->dm_timer);
134
135 return !!(status & OMAP_TIMER_CTRL_SCPWM);
136}
137
138/**
139 * pwm_omap_dmtimer_config() - Update the configuration of pwm omap dm timer
140 * @chip: Pointer to PWM controller
141 * @pwm: Pointer to PWM channel
142 * @duty_ns: New duty cycle in nano seconds
143 * @period_ns: New period in nano seconds
144 *
145 * Return 0 if successfully changed the period/duty_cycle else appropriate
146 * error.
147 */
148static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
149 struct pwm_device *pwm,
150 int duty_ns, int period_ns)
151{
152 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
153 u32 period_cycles, duty_cycles;
154 u32 load_value, match_value;
155 unsigned long clk_rate;
156 struct clk *fclk;
157
158 dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
159 duty_ns, period_ns);
160
161 if (duty_ns == pwm_get_duty_cycle(pwm) &&
162 period_ns == pwm_get_period(pwm))
163 return 0;
164
165 fclk = omap->pdata->get_fclk(omap->dm_timer);
166 if (!fclk) {
167 dev_err(chip->dev, "invalid pmtimer fclk\n");
168 return -EINVAL;
169 }
170
171 clk_rate = clk_get_rate(fclk);
172 if (!clk_rate) {
173 dev_err(chip->dev, "invalid pmtimer fclk rate\n");
174 return -EINVAL;
175 }
176
177 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
178
179 /*
180 * Calculate the appropriate load and match values based on the
181 * specified period and duty cycle. The load value determines the
182 * period time and the match value determines the duty time.
183 *
184 * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
185 * Similarly, the active time lasts (match_value-load_value+1) cycles.
186 * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
187 * clock cycles.
188 *
189 * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
190 *
191 * References:
192 * OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
193 * AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
194 */
195 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
196 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
197
198 if (period_cycles < 2) {
199 dev_info(chip->dev,
200 "period %d ns too short for clock rate %lu Hz\n",
201 period_ns, clk_rate);
202 return -EINVAL;
203 }
204
205 if (duty_cycles < 1) {
206 dev_dbg(chip->dev,
207 "duty cycle %d ns is too short for clock rate %lu Hz\n",
208 duty_ns, clk_rate);
209 dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
210 duty_cycles = 1;
211 } else if (duty_cycles >= period_cycles) {
212 dev_dbg(chip->dev,
213 "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
214 duty_ns, period_ns, clk_rate);
215 dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
216 duty_cycles = period_cycles - 1;
217 }
218
219 dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
220 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
221 clk_rate),
222 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
223 clk_rate));
224
225 load_value = (DM_TIMER_MAX - period_cycles) + 1;
226 match_value = load_value + duty_cycles - 1;
227
228 omap->pdata->set_load(omap->dm_timer, load_value);
229 omap->pdata->set_match(omap->dm_timer, true, match_value);
230
231 dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
232 load_value, load_value, match_value, match_value);
233
234 return 0;
235}
236
237/**
238 * pwm_omap_dmtimer_set_polarity() - Changes the polarity of the pwm dm timer.
239 * @chip: Pointer to PWM controller
240 * @pwm: Pointer to PWM channel
241 * @polarity: New pwm polarity to be set
242 */
243static void pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
244 struct pwm_device *pwm,
245 enum pwm_polarity polarity)
246{
247 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
248 bool enabled;
249
250 /* Disable the PWM before changing the polarity. */
251 enabled = pwm_omap_dmtimer_is_enabled(omap);
252 if (enabled)
253 omap->pdata->stop(omap->dm_timer);
254
255 omap->pdata->set_pwm(omap->dm_timer,
256 polarity == PWM_POLARITY_INVERSED,
257 true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
258 true);
259
260 if (enabled)
261 pwm_omap_dmtimer_start(omap);
262}
263
264/**
265 * pwm_omap_dmtimer_apply() - Changes the state of the pwm omap dm timer.
266 * @chip: Pointer to PWM controller
267 * @pwm: Pointer to PWM channel
268 * @state: New state to apply
269 *
270 * Return 0 if successfully changed the state else appropriate error.
271 */
272static int pwm_omap_dmtimer_apply(struct pwm_chip *chip,
273 struct pwm_device *pwm,
274 const struct pwm_state *state)
275{
276 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
277 int ret;
278
279 if (pwm_omap_dmtimer_is_enabled(omap) && !state->enabled) {
280 omap->pdata->stop(omap->dm_timer);
281 return 0;
282 }
283
284 if (pwm_omap_dmtimer_polarity(omap) != state->polarity)
285 pwm_omap_dmtimer_set_polarity(chip, pwm, state->polarity);
286
287 ret = pwm_omap_dmtimer_config(chip, pwm, state->duty_cycle,
288 state->period);
289 if (ret)
290 return ret;
291
292 if (!pwm_omap_dmtimer_is_enabled(omap) && state->enabled) {
293 omap->pdata->set_pwm(omap->dm_timer,
294 state->polarity == PWM_POLARITY_INVERSED,
295 true,
296 OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
297 true);
298 pwm_omap_dmtimer_start(omap);
299 }
300
301 return 0;
302}
303
304static const struct pwm_ops pwm_omap_dmtimer_ops = {
305 .apply = pwm_omap_dmtimer_apply,
306};
307
308static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
309{
310 struct device_node *np = pdev->dev.of_node;
311 struct dmtimer_platform_data *timer_pdata;
312 const struct omap_dm_timer_ops *pdata;
313 struct platform_device *timer_pdev;
314 struct pwm_omap_dmtimer_chip *omap;
315 struct omap_dm_timer *dm_timer;
316 struct device_node *timer;
317 int ret = 0;
318 u32 v;
319
320 timer = of_parse_phandle(np, "ti,timers", 0);
321 if (!timer)
322 return -ENODEV;
323
324 timer_pdev = of_find_device_by_node(timer);
325 if (!timer_pdev) {
326 dev_err(&pdev->dev, "Unable to find Timer pdev\n");
327 ret = -ENODEV;
328 goto err_find_timer_pdev;
329 }
330
331 timer_pdata = dev_get_platdata(&timer_pdev->dev);
332 if (!timer_pdata) {
333 dev_dbg(&pdev->dev,
334 "dmtimer pdata structure NULL, deferring probe\n");
335 ret = -EPROBE_DEFER;
336 goto err_platdata;
337 }
338
339 pdata = timer_pdata->timer_ops;
340
341 if (!pdata || !pdata->request_by_node ||
342 !pdata->free ||
343 !pdata->enable ||
344 !pdata->disable ||
345 !pdata->get_fclk ||
346 !pdata->start ||
347 !pdata->stop ||
348 !pdata->set_load ||
349 !pdata->set_match ||
350 !pdata->set_pwm ||
351 !pdata->get_pwm_status ||
352 !pdata->set_prescaler ||
353 !pdata->write_counter) {
354 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
355 ret = -EINVAL;
356 goto err_platdata;
357 }
358
359 if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
360 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
361 ret = -ENODEV;
362 goto err_timer_property;
363 }
364
365 dm_timer = pdata->request_by_node(timer);
366 if (!dm_timer) {
367 ret = -EPROBE_DEFER;
368 goto err_request_timer;
369 }
370
371 omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
372 if (!omap) {
373 ret = -ENOMEM;
374 goto err_alloc_omap;
375 }
376
377 omap->pdata = pdata;
378 omap->dm_timer = dm_timer;
379 omap->dm_timer_pdev = timer_pdev;
380
381 /*
382 * Ensure that the timer is stopped before we allow PWM core to call
383 * pwm_enable.
384 */
385 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
386 omap->pdata->stop(omap->dm_timer);
387
388 if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
389 omap->pdata->set_prescaler(omap->dm_timer, v);
390
391 /* setup dmtimer clock source */
392 if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
393 omap->pdata->set_source(omap->dm_timer, v);
394
395 omap->chip.dev = &pdev->dev;
396 omap->chip.ops = &pwm_omap_dmtimer_ops;
397 omap->chip.npwm = 1;
398
399 ret = pwmchip_add(&omap->chip);
400 if (ret < 0) {
401 dev_err(&pdev->dev, "failed to register PWM\n");
402 goto err_pwmchip_add;
403 }
404
405 of_node_put(timer);
406
407 platform_set_drvdata(pdev, omap);
408
409 return 0;
410
411err_pwmchip_add:
412
413 /*
414 * *omap is allocated using devm_kzalloc,
415 * so no free necessary here
416 */
417err_alloc_omap:
418
419 pdata->free(dm_timer);
420err_request_timer:
421
422err_timer_property:
423err_platdata:
424
425 put_device(&timer_pdev->dev);
426err_find_timer_pdev:
427
428 of_node_put(timer);
429
430 return ret;
431}
432
433static void pwm_omap_dmtimer_remove(struct platform_device *pdev)
434{
435 struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
436
437 pwmchip_remove(&omap->chip);
438
439 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
440 omap->pdata->stop(omap->dm_timer);
441
442 omap->pdata->free(omap->dm_timer);
443
444 put_device(&omap->dm_timer_pdev->dev);
445}
446
447static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
448 {.compatible = "ti,omap-dmtimer-pwm"},
449 {}
450};
451MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
452
453static struct platform_driver pwm_omap_dmtimer_driver = {
454 .driver = {
455 .name = "omap-dmtimer-pwm",
456 .of_match_table = pwm_omap_dmtimer_of_match,
457 },
458 .probe = pwm_omap_dmtimer_probe,
459 .remove_new = pwm_omap_dmtimer_remove,
460};
461module_platform_driver(pwm_omap_dmtimer_driver);
462
463MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
464MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
465MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
466MODULE_LICENSE("GPL v2");
467MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");
1/*
2 * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
3 * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
4 * Copyright (c) 2012 NeilBrown <neilb@suse.de>
5 * Heavily based on earlier code which is:
6 * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
7 *
8 * Also based on pwm-samsung.c
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * Description:
15 * This file is the core OMAP support for the generic, Linux
16 * PWM driver / controller, using the OMAP's dual-mode timers.
17 */
18
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/mutex.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/platform_data/dmtimer-omap.h>
27#include <linux/platform_data/pwm_omap_dmtimer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/pwm.h>
31#include <linux/slab.h>
32#include <linux/time.h>
33
34#define DM_TIMER_LOAD_MIN 0xfffffffe
35#define DM_TIMER_MAX 0xffffffff
36
37struct pwm_omap_dmtimer_chip {
38 struct pwm_chip chip;
39 struct mutex mutex;
40 pwm_omap_dmtimer *dm_timer;
41 const struct omap_dm_timer_ops *pdata;
42 struct platform_device *dm_timer_pdev;
43};
44
45static inline struct pwm_omap_dmtimer_chip *
46to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
47{
48 return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
49}
50
51static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
52{
53 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
54}
55
56static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
57{
58 /*
59 * According to OMAP 4 TRM section 22.2.4.10 the counter should be
60 * started at 0xFFFFFFFE when overflow and match is used to ensure
61 * that the PWM line is toggled on the first event.
62 *
63 * Note that omap_dm_timer_enable/disable is for register access and
64 * not the timer counter itself.
65 */
66 omap->pdata->enable(omap->dm_timer);
67 omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
68 omap->pdata->disable(omap->dm_timer);
69
70 omap->pdata->start(omap->dm_timer);
71}
72
73static int pwm_omap_dmtimer_enable(struct pwm_chip *chip,
74 struct pwm_device *pwm)
75{
76 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
77
78 mutex_lock(&omap->mutex);
79 pwm_omap_dmtimer_start(omap);
80 mutex_unlock(&omap->mutex);
81
82 return 0;
83}
84
85static void pwm_omap_dmtimer_disable(struct pwm_chip *chip,
86 struct pwm_device *pwm)
87{
88 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
89
90 mutex_lock(&omap->mutex);
91 omap->pdata->stop(omap->dm_timer);
92 mutex_unlock(&omap->mutex);
93}
94
95static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
96 struct pwm_device *pwm,
97 int duty_ns, int period_ns)
98{
99 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
100 u32 period_cycles, duty_cycles;
101 u32 load_value, match_value;
102 struct clk *fclk;
103 unsigned long clk_rate;
104 bool timer_active;
105
106 dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
107 duty_ns, period_ns);
108
109 mutex_lock(&omap->mutex);
110 if (duty_ns == pwm_get_duty_cycle(pwm) &&
111 period_ns == pwm_get_period(pwm)) {
112 /* No change - don't cause any transients. */
113 mutex_unlock(&omap->mutex);
114 return 0;
115 }
116
117 fclk = omap->pdata->get_fclk(omap->dm_timer);
118 if (!fclk) {
119 dev_err(chip->dev, "invalid pmtimer fclk\n");
120 goto err_einval;
121 }
122
123 clk_rate = clk_get_rate(fclk);
124 if (!clk_rate) {
125 dev_err(chip->dev, "invalid pmtimer fclk rate\n");
126 goto err_einval;
127 }
128
129 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
130
131 /*
132 * Calculate the appropriate load and match values based on the
133 * specified period and duty cycle. The load value determines the
134 * period time and the match value determines the duty time.
135 *
136 * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
137 * Similarly, the active time lasts (match_value-load_value+1) cycles.
138 * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
139 * clock cycles.
140 *
141 * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
142 *
143 * References:
144 * OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
145 * AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
146 */
147 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
148 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
149
150 if (period_cycles < 2) {
151 dev_info(chip->dev,
152 "period %d ns too short for clock rate %lu Hz\n",
153 period_ns, clk_rate);
154 goto err_einval;
155 }
156
157 if (duty_cycles < 1) {
158 dev_dbg(chip->dev,
159 "duty cycle %d ns is too short for clock rate %lu Hz\n",
160 duty_ns, clk_rate);
161 dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
162 duty_cycles = 1;
163 } else if (duty_cycles >= period_cycles) {
164 dev_dbg(chip->dev,
165 "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
166 duty_ns, period_ns, clk_rate);
167 dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
168 duty_cycles = period_cycles - 1;
169 }
170
171 dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
172 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
173 clk_rate),
174 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
175 clk_rate));
176
177 load_value = (DM_TIMER_MAX - period_cycles) + 1;
178 match_value = load_value + duty_cycles - 1;
179
180 /*
181 * We MUST stop the associated dual-mode timer before attempting to
182 * write its registers, but calls to omap_dm_timer_start/stop must
183 * be balanced so check if timer is active before calling timer_stop.
184 */
185 timer_active = pm_runtime_active(&omap->dm_timer_pdev->dev);
186 if (timer_active)
187 omap->pdata->stop(omap->dm_timer);
188
189 omap->pdata->set_load(omap->dm_timer, true, load_value);
190 omap->pdata->set_match(omap->dm_timer, true, match_value);
191
192 dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
193 load_value, load_value, match_value, match_value);
194
195 omap->pdata->set_pwm(omap->dm_timer,
196 pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED,
197 true,
198 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
199
200 /* If config was called while timer was running it must be reenabled. */
201 if (timer_active)
202 pwm_omap_dmtimer_start(omap);
203
204 mutex_unlock(&omap->mutex);
205
206 return 0;
207
208err_einval:
209 mutex_unlock(&omap->mutex);
210
211 return -EINVAL;
212}
213
214static int pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
215 struct pwm_device *pwm,
216 enum pwm_polarity polarity)
217{
218 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
219
220 /*
221 * PWM core will not call set_polarity while PWM is enabled so it's
222 * safe to reconfigure the timer here without stopping it first.
223 */
224 mutex_lock(&omap->mutex);
225 omap->pdata->set_pwm(omap->dm_timer,
226 polarity == PWM_POLARITY_INVERSED,
227 true,
228 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
229 mutex_unlock(&omap->mutex);
230
231 return 0;
232}
233
234static const struct pwm_ops pwm_omap_dmtimer_ops = {
235 .enable = pwm_omap_dmtimer_enable,
236 .disable = pwm_omap_dmtimer_disable,
237 .config = pwm_omap_dmtimer_config,
238 .set_polarity = pwm_omap_dmtimer_set_polarity,
239 .owner = THIS_MODULE,
240};
241
242static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
243{
244 struct device_node *np = pdev->dev.of_node;
245 struct device_node *timer;
246 struct platform_device *timer_pdev;
247 struct pwm_omap_dmtimer_chip *omap;
248 struct dmtimer_platform_data *timer_pdata;
249 const struct omap_dm_timer_ops *pdata;
250 pwm_omap_dmtimer *dm_timer;
251 u32 v;
252 int ret = 0;
253
254 timer = of_parse_phandle(np, "ti,timers", 0);
255 if (!timer)
256 return -ENODEV;
257
258 timer_pdev = of_find_device_by_node(timer);
259 if (!timer_pdev) {
260 dev_err(&pdev->dev, "Unable to find Timer pdev\n");
261 ret = -ENODEV;
262 goto put;
263 }
264
265 timer_pdata = dev_get_platdata(&timer_pdev->dev);
266 if (!timer_pdata) {
267 dev_err(&pdev->dev, "dmtimer pdata structure NULL\n");
268 ret = -EINVAL;
269 goto put;
270 }
271
272 pdata = timer_pdata->timer_ops;
273
274 if (!pdata || !pdata->request_by_node ||
275 !pdata->free ||
276 !pdata->enable ||
277 !pdata->disable ||
278 !pdata->get_fclk ||
279 !pdata->start ||
280 !pdata->stop ||
281 !pdata->set_load ||
282 !pdata->set_match ||
283 !pdata->set_pwm ||
284 !pdata->set_prescaler ||
285 !pdata->write_counter) {
286 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
287 ret = -EINVAL;
288 goto put;
289 }
290
291 if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
292 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
293 ret = -ENODEV;
294 goto put;
295 }
296
297 dm_timer = pdata->request_by_node(timer);
298 if (!dm_timer) {
299 ret = -EPROBE_DEFER;
300 goto put;
301 }
302
303put:
304 of_node_put(timer);
305 if (ret < 0)
306 return ret;
307
308 omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
309 if (!omap) {
310 pdata->free(dm_timer);
311 return -ENOMEM;
312 }
313
314 omap->pdata = pdata;
315 omap->dm_timer = dm_timer;
316 omap->dm_timer_pdev = timer_pdev;
317
318 /*
319 * Ensure that the timer is stopped before we allow PWM core to call
320 * pwm_enable.
321 */
322 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
323 omap->pdata->stop(omap->dm_timer);
324
325 if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
326 omap->pdata->set_prescaler(omap->dm_timer, v);
327
328 /* setup dmtimer clock source */
329 if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
330 omap->pdata->set_source(omap->dm_timer, v);
331
332 omap->chip.dev = &pdev->dev;
333 omap->chip.ops = &pwm_omap_dmtimer_ops;
334 omap->chip.base = -1;
335 omap->chip.npwm = 1;
336 omap->chip.of_xlate = of_pwm_xlate_with_flags;
337 omap->chip.of_pwm_n_cells = 3;
338
339 mutex_init(&omap->mutex);
340
341 ret = pwmchip_add(&omap->chip);
342 if (ret < 0) {
343 dev_err(&pdev->dev, "failed to register PWM\n");
344 omap->pdata->free(omap->dm_timer);
345 return ret;
346 }
347
348 platform_set_drvdata(pdev, omap);
349
350 return 0;
351}
352
353static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
354{
355 struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
356
357 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
358 omap->pdata->stop(omap->dm_timer);
359
360 omap->pdata->free(omap->dm_timer);
361
362 mutex_destroy(&omap->mutex);
363
364 return pwmchip_remove(&omap->chip);
365}
366
367static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
368 {.compatible = "ti,omap-dmtimer-pwm"},
369 {}
370};
371MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
372
373static struct platform_driver pwm_omap_dmtimer_driver = {
374 .driver = {
375 .name = "omap-dmtimer-pwm",
376 .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
377 },
378 .probe = pwm_omap_dmtimer_probe,
379 .remove = pwm_omap_dmtimer_remove,
380};
381module_platform_driver(pwm_omap_dmtimer_driver);
382
383MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
384MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
385MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
386MODULE_LICENSE("GPL v2");
387MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");