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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include "e1000.h"
5#include <linux/ethtool.h>
6
7static s32 e1000_wait_autoneg(struct e1000_hw *hw);
8static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
9 u16 *data, bool read, bool page_set);
10static u32 e1000_get_phy_addr_for_hv_page(u32 page);
11static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
12 u16 *data, bool read);
13
14/* Cable length tables */
15static const u16 e1000_m88_cable_length_table[] = {
16 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
17};
18
19#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
20 ARRAY_SIZE(e1000_m88_cable_length_table)
21
22static const u16 e1000_igp_2_cable_length_table[] = {
23 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
24 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
25 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
26 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
27 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
28 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
29 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
30 124
31};
32
33#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
34 ARRAY_SIZE(e1000_igp_2_cable_length_table)
35
36/**
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
38 * @hw: pointer to the HW structure
39 *
40 * Read the PHY management control register and check whether a PHY reset
41 * is blocked. If a reset is not blocked return 0, otherwise
42 * return E1000_BLK_PHY_RESET (12).
43 **/
44s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
45{
46 u32 manc;
47
48 manc = er32(MANC);
49
50 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
51}
52
53/**
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
55 * @hw: pointer to the HW structure
56 *
57 * Reads the PHY registers and stores the PHY ID and possibly the PHY
58 * revision in the hardware structure.
59 **/
60s32 e1000e_get_phy_id(struct e1000_hw *hw)
61{
62 struct e1000_phy_info *phy = &hw->phy;
63 s32 ret_val = 0;
64 u16 phy_id;
65 u16 retry_count = 0;
66
67 if (!phy->ops.read_reg)
68 return 0;
69
70 while (retry_count < 2) {
71 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
72 if (ret_val)
73 return ret_val;
74
75 phy->id = (u32)(phy_id << 16);
76 usleep_range(20, 40);
77 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
78 if (ret_val)
79 return ret_val;
80
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
82 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
83
84 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
85 return 0;
86
87 retry_count++;
88 }
89
90 return 0;
91}
92
93/**
94 * e1000e_phy_reset_dsp - Reset PHY DSP
95 * @hw: pointer to the HW structure
96 *
97 * Reset the digital signal processor.
98 **/
99s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
100{
101 s32 ret_val;
102
103 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
104 if (ret_val)
105 return ret_val;
106
107 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
108}
109
110/**
111 * e1000e_read_phy_reg_mdic - Read MDI control register
112 * @hw: pointer to the HW structure
113 * @offset: register offset to be read
114 * @data: pointer to the read data
115 *
116 * Reads the MDI control register in the PHY at offset and stores the
117 * information read to data.
118 **/
119s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
120{
121 struct e1000_phy_info *phy = &hw->phy;
122 u32 i, mdic = 0;
123
124 if (offset > MAX_PHY_REG_ADDRESS) {
125 e_dbg("PHY Address %d is out of range\n", offset);
126 return -E1000_ERR_PARAM;
127 }
128
129 /* Set up Op-code, Phy Address, and register offset in the MDI
130 * Control register. The MAC will take care of interfacing with the
131 * PHY to retrieve the desired data.
132 */
133 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
134 (phy->addr << E1000_MDIC_PHY_SHIFT) |
135 (E1000_MDIC_OP_READ));
136
137 ew32(MDIC, mdic);
138
139 /* Poll the ready bit to see if the MDI read completed
140 * Increasing the time out as testing showed failures with
141 * the lower time out
142 */
143 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
144 udelay(50);
145 mdic = er32(MDIC);
146 if (mdic & E1000_MDIC_READY)
147 break;
148 }
149 if (!(mdic & E1000_MDIC_READY)) {
150 e_dbg("MDI Read PHY Reg Address %d did not complete\n", offset);
151 return -E1000_ERR_PHY;
152 }
153 if (mdic & E1000_MDIC_ERROR) {
154 e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
155 return -E1000_ERR_PHY;
156 }
157 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
158 e_dbg("MDI Read offset error - requested %d, returned %d\n",
159 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
160 return -E1000_ERR_PHY;
161 }
162 *data = (u16)mdic;
163
164 /* Allow some time after each MDIC transaction to avoid
165 * reading duplicate data in the next MDIC transaction.
166 */
167 if (hw->mac.type == e1000_pch2lan)
168 udelay(100);
169 return 0;
170}
171
172/**
173 * e1000e_write_phy_reg_mdic - Write MDI control register
174 * @hw: pointer to the HW structure
175 * @offset: register offset to write to
176 * @data: data to write to register at offset
177 *
178 * Writes data to MDI control register in the PHY at offset.
179 **/
180s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
181{
182 struct e1000_phy_info *phy = &hw->phy;
183 u32 i, mdic = 0;
184
185 if (offset > MAX_PHY_REG_ADDRESS) {
186 e_dbg("PHY Address %d is out of range\n", offset);
187 return -E1000_ERR_PARAM;
188 }
189
190 /* Set up Op-code, Phy Address, and register offset in the MDI
191 * Control register. The MAC will take care of interfacing with the
192 * PHY to retrieve the desired data.
193 */
194 mdic = (((u32)data) |
195 (offset << E1000_MDIC_REG_SHIFT) |
196 (phy->addr << E1000_MDIC_PHY_SHIFT) |
197 (E1000_MDIC_OP_WRITE));
198
199 ew32(MDIC, mdic);
200
201 /* Poll the ready bit to see if the MDI read completed
202 * Increasing the time out as testing showed failures with
203 * the lower time out
204 */
205 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
206 udelay(50);
207 mdic = er32(MDIC);
208 if (mdic & E1000_MDIC_READY)
209 break;
210 }
211 if (!(mdic & E1000_MDIC_READY)) {
212 e_dbg("MDI Write PHY Reg Address %d did not complete\n", offset);
213 return -E1000_ERR_PHY;
214 }
215 if (mdic & E1000_MDIC_ERROR) {
216 e_dbg("MDI Write PHY Red Address %d Error\n", offset);
217 return -E1000_ERR_PHY;
218 }
219 if (FIELD_GET(E1000_MDIC_REG_MASK, mdic) != offset) {
220 e_dbg("MDI Write offset error - requested %d, returned %d\n",
221 offset, FIELD_GET(E1000_MDIC_REG_MASK, mdic));
222 return -E1000_ERR_PHY;
223 }
224
225 /* Allow some time after each MDIC transaction to avoid
226 * reading duplicate data in the next MDIC transaction.
227 */
228 if (hw->mac.type == e1000_pch2lan)
229 udelay(100);
230
231 return 0;
232}
233
234/**
235 * e1000e_read_phy_reg_m88 - Read m88 PHY register
236 * @hw: pointer to the HW structure
237 * @offset: register offset to be read
238 * @data: pointer to the read data
239 *
240 * Acquires semaphore, if necessary, then reads the PHY register at offset
241 * and storing the retrieved information in data. Release any acquired
242 * semaphores before exiting.
243 **/
244s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
245{
246 s32 ret_val;
247
248 ret_val = hw->phy.ops.acquire(hw);
249 if (ret_val)
250 return ret_val;
251
252 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
253 data);
254
255 hw->phy.ops.release(hw);
256
257 return ret_val;
258}
259
260/**
261 * e1000e_write_phy_reg_m88 - Write m88 PHY register
262 * @hw: pointer to the HW structure
263 * @offset: register offset to write to
264 * @data: data to write at register offset
265 *
266 * Acquires semaphore, if necessary, then writes the data to PHY register
267 * at the offset. Release any acquired semaphores before exiting.
268 **/
269s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
270{
271 s32 ret_val;
272
273 ret_val = hw->phy.ops.acquire(hw);
274 if (ret_val)
275 return ret_val;
276
277 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
278 data);
279
280 hw->phy.ops.release(hw);
281
282 return ret_val;
283}
284
285/**
286 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
287 * @hw: pointer to the HW structure
288 * @page: page to set (shifted left when necessary)
289 *
290 * Sets PHY page required for PHY register access. Assumes semaphore is
291 * already acquired. Note, this function sets phy.addr to 1 so the caller
292 * must set it appropriately (if necessary) after this function returns.
293 **/
294s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
295{
296 e_dbg("Setting page 0x%x\n", page);
297
298 hw->phy.addr = 1;
299
300 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
301}
302
303/**
304 * __e1000e_read_phy_reg_igp - Read igp PHY register
305 * @hw: pointer to the HW structure
306 * @offset: register offset to be read
307 * @data: pointer to the read data
308 * @locked: semaphore has already been acquired or not
309 *
310 * Acquires semaphore, if necessary, then reads the PHY register at offset
311 * and stores the retrieved information in data. Release any acquired
312 * semaphores before exiting.
313 **/
314static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
315 bool locked)
316{
317 s32 ret_val = 0;
318
319 if (!locked) {
320 if (!hw->phy.ops.acquire)
321 return 0;
322
323 ret_val = hw->phy.ops.acquire(hw);
324 if (ret_val)
325 return ret_val;
326 }
327
328 if (offset > MAX_PHY_MULTI_PAGE_REG)
329 ret_val = e1000e_write_phy_reg_mdic(hw,
330 IGP01E1000_PHY_PAGE_SELECT,
331 (u16)offset);
332 if (!ret_val)
333 ret_val = e1000e_read_phy_reg_mdic(hw,
334 MAX_PHY_REG_ADDRESS & offset,
335 data);
336 if (!locked)
337 hw->phy.ops.release(hw);
338
339 return ret_val;
340}
341
342/**
343 * e1000e_read_phy_reg_igp - Read igp PHY register
344 * @hw: pointer to the HW structure
345 * @offset: register offset to be read
346 * @data: pointer to the read data
347 *
348 * Acquires semaphore then reads the PHY register at offset and stores the
349 * retrieved information in data.
350 * Release the acquired semaphore before exiting.
351 **/
352s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
353{
354 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
355}
356
357/**
358 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
359 * @hw: pointer to the HW structure
360 * @offset: register offset to be read
361 * @data: pointer to the read data
362 *
363 * Reads the PHY register at offset and stores the retrieved information
364 * in data. Assumes semaphore already acquired.
365 **/
366s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
367{
368 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
369}
370
371/**
372 * __e1000e_write_phy_reg_igp - Write igp PHY register
373 * @hw: pointer to the HW structure
374 * @offset: register offset to write to
375 * @data: data to write at register offset
376 * @locked: semaphore has already been acquired or not
377 *
378 * Acquires semaphore, if necessary, then writes the data to PHY register
379 * at the offset. Release any acquired semaphores before exiting.
380 **/
381static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
382 bool locked)
383{
384 s32 ret_val = 0;
385
386 if (!locked) {
387 if (!hw->phy.ops.acquire)
388 return 0;
389
390 ret_val = hw->phy.ops.acquire(hw);
391 if (ret_val)
392 return ret_val;
393 }
394
395 if (offset > MAX_PHY_MULTI_PAGE_REG)
396 ret_val = e1000e_write_phy_reg_mdic(hw,
397 IGP01E1000_PHY_PAGE_SELECT,
398 (u16)offset);
399 if (!ret_val)
400 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
401 offset, data);
402 if (!locked)
403 hw->phy.ops.release(hw);
404
405 return ret_val;
406}
407
408/**
409 * e1000e_write_phy_reg_igp - Write igp PHY register
410 * @hw: pointer to the HW structure
411 * @offset: register offset to write to
412 * @data: data to write at register offset
413 *
414 * Acquires semaphore then writes the data to PHY register
415 * at the offset. Release any acquired semaphores before exiting.
416 **/
417s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
418{
419 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
420}
421
422/**
423 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
424 * @hw: pointer to the HW structure
425 * @offset: register offset to write to
426 * @data: data to write at register offset
427 *
428 * Writes the data to PHY register at the offset.
429 * Assumes semaphore already acquired.
430 **/
431s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
432{
433 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
434}
435
436/**
437 * __e1000_read_kmrn_reg - Read kumeran register
438 * @hw: pointer to the HW structure
439 * @offset: register offset to be read
440 * @data: pointer to the read data
441 * @locked: semaphore has already been acquired or not
442 *
443 * Acquires semaphore, if necessary. Then reads the PHY register at offset
444 * using the kumeran interface. The information retrieved is stored in data.
445 * Release any acquired semaphores before exiting.
446 **/
447static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
448 bool locked)
449{
450 u32 kmrnctrlsta;
451
452 if (!locked) {
453 s32 ret_val = 0;
454
455 if (!hw->phy.ops.acquire)
456 return 0;
457
458 ret_val = hw->phy.ops.acquire(hw);
459 if (ret_val)
460 return ret_val;
461 }
462
463 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) |
464 E1000_KMRNCTRLSTA_REN;
465 ew32(KMRNCTRLSTA, kmrnctrlsta);
466 e1e_flush();
467
468 udelay(2);
469
470 kmrnctrlsta = er32(KMRNCTRLSTA);
471 *data = (u16)kmrnctrlsta;
472
473 if (!locked)
474 hw->phy.ops.release(hw);
475
476 return 0;
477}
478
479/**
480 * e1000e_read_kmrn_reg - Read kumeran register
481 * @hw: pointer to the HW structure
482 * @offset: register offset to be read
483 * @data: pointer to the read data
484 *
485 * Acquires semaphore then reads the PHY register at offset using the
486 * kumeran interface. The information retrieved is stored in data.
487 * Release the acquired semaphore before exiting.
488 **/
489s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
490{
491 return __e1000_read_kmrn_reg(hw, offset, data, false);
492}
493
494/**
495 * e1000e_read_kmrn_reg_locked - Read kumeran register
496 * @hw: pointer to the HW structure
497 * @offset: register offset to be read
498 * @data: pointer to the read data
499 *
500 * Reads the PHY register at offset using the kumeran interface. The
501 * information retrieved is stored in data.
502 * Assumes semaphore already acquired.
503 **/
504s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
505{
506 return __e1000_read_kmrn_reg(hw, offset, data, true);
507}
508
509/**
510 * __e1000_write_kmrn_reg - Write kumeran register
511 * @hw: pointer to the HW structure
512 * @offset: register offset to write to
513 * @data: data to write at register offset
514 * @locked: semaphore has already been acquired or not
515 *
516 * Acquires semaphore, if necessary. Then write the data to PHY register
517 * at the offset using the kumeran interface. Release any acquired semaphores
518 * before exiting.
519 **/
520static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
521 bool locked)
522{
523 u32 kmrnctrlsta;
524
525 if (!locked) {
526 s32 ret_val = 0;
527
528 if (!hw->phy.ops.acquire)
529 return 0;
530
531 ret_val = hw->phy.ops.acquire(hw);
532 if (ret_val)
533 return ret_val;
534 }
535
536 kmrnctrlsta = FIELD_PREP(E1000_KMRNCTRLSTA_OFFSET, offset) | data;
537 ew32(KMRNCTRLSTA, kmrnctrlsta);
538 e1e_flush();
539
540 udelay(2);
541
542 if (!locked)
543 hw->phy.ops.release(hw);
544
545 return 0;
546}
547
548/**
549 * e1000e_write_kmrn_reg - Write kumeran register
550 * @hw: pointer to the HW structure
551 * @offset: register offset to write to
552 * @data: data to write at register offset
553 *
554 * Acquires semaphore then writes the data to the PHY register at the offset
555 * using the kumeran interface. Release the acquired semaphore before exiting.
556 **/
557s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
558{
559 return __e1000_write_kmrn_reg(hw, offset, data, false);
560}
561
562/**
563 * e1000e_write_kmrn_reg_locked - Write kumeran register
564 * @hw: pointer to the HW structure
565 * @offset: register offset to write to
566 * @data: data to write at register offset
567 *
568 * Write the data to PHY register at the offset using the kumeran interface.
569 * Assumes semaphore already acquired.
570 **/
571s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
572{
573 return __e1000_write_kmrn_reg(hw, offset, data, true);
574}
575
576/**
577 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
578 * @hw: pointer to the HW structure
579 *
580 * Sets up Master/slave mode
581 **/
582static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
583{
584 s32 ret_val;
585 u16 phy_data;
586
587 /* Resolve Master/Slave mode */
588 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
589 if (ret_val)
590 return ret_val;
591
592 /* load defaults for future use */
593 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
594 ((phy_data & CTL1000_AS_MASTER) ?
595 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
596
597 switch (hw->phy.ms_type) {
598 case e1000_ms_force_master:
599 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
600 break;
601 case e1000_ms_force_slave:
602 phy_data |= CTL1000_ENABLE_MASTER;
603 phy_data &= ~(CTL1000_AS_MASTER);
604 break;
605 case e1000_ms_auto:
606 phy_data &= ~CTL1000_ENABLE_MASTER;
607 fallthrough;
608 default:
609 break;
610 }
611
612 return e1e_wphy(hw, MII_CTRL1000, phy_data);
613}
614
615/**
616 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
617 * @hw: pointer to the HW structure
618 *
619 * Sets up Carrier-sense on Transmit and downshift values.
620 **/
621s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
622{
623 s32 ret_val;
624 u16 phy_data;
625
626 /* Enable CRS on Tx. This must be set for half-duplex operation. */
627 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
628 if (ret_val)
629 return ret_val;
630
631 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
632
633 /* Enable downshift */
634 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
635
636 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
637 if (ret_val)
638 return ret_val;
639
640 /* Set MDI/MDIX mode */
641 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
642 if (ret_val)
643 return ret_val;
644 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
645 /* Options:
646 * 0 - Auto (default)
647 * 1 - MDI mode
648 * 2 - MDI-X mode
649 */
650 switch (hw->phy.mdix) {
651 case 1:
652 break;
653 case 2:
654 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
655 break;
656 case 0:
657 default:
658 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
659 break;
660 }
661 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
662 if (ret_val)
663 return ret_val;
664
665 return e1000_set_master_slave_mode(hw);
666}
667
668/**
669 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
670 * @hw: pointer to the HW structure
671 *
672 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
673 * and downshift values are set also.
674 **/
675s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
676{
677 struct e1000_phy_info *phy = &hw->phy;
678 s32 ret_val;
679 u16 phy_data;
680
681 /* Enable CRS on Tx. This must be set for half-duplex operation. */
682 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
683 if (ret_val)
684 return ret_val;
685
686 /* For BM PHY this bit is downshift enable */
687 if (phy->type != e1000_phy_bm)
688 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
689
690 /* Options:
691 * MDI/MDI-X = 0 (default)
692 * 0 - Auto for all speeds
693 * 1 - MDI mode
694 * 2 - MDI-X mode
695 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
696 */
697 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
698
699 switch (phy->mdix) {
700 case 1:
701 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
702 break;
703 case 2:
704 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
705 break;
706 case 3:
707 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
708 break;
709 case 0:
710 default:
711 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
712 break;
713 }
714
715 /* Options:
716 * disable_polarity_correction = 0 (default)
717 * Automatic Correction for Reversed Cable Polarity
718 * 0 - Disabled
719 * 1 - Enabled
720 */
721 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
722 if (phy->disable_polarity_correction)
723 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
724
725 /* Enable downshift on BM (disabled by default) */
726 if (phy->type == e1000_phy_bm) {
727 /* For 82574/82583, first disable then enable downshift */
728 if (phy->id == BME1000_E_PHY_ID_R2) {
729 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
730 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
731 phy_data);
732 if (ret_val)
733 return ret_val;
734 /* Commit the changes. */
735 ret_val = phy->ops.commit(hw);
736 if (ret_val) {
737 e_dbg("Error committing the PHY changes\n");
738 return ret_val;
739 }
740 }
741
742 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
743 }
744
745 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
746 if (ret_val)
747 return ret_val;
748
749 if ((phy->type == e1000_phy_m88) &&
750 (phy->revision < E1000_REVISION_4) &&
751 (phy->id != BME1000_E_PHY_ID_R2)) {
752 /* Force TX_CLK in the Extended PHY Specific Control Register
753 * to 25MHz clock.
754 */
755 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
756 if (ret_val)
757 return ret_val;
758
759 phy_data |= M88E1000_EPSCR_TX_CLK_25;
760
761 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
762 /* 82573L PHY - set the downshift counter to 5x. */
763 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
764 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
765 } else {
766 /* Configure Master and Slave downshift values */
767 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
768 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
769 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
770 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
771 }
772 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
773 if (ret_val)
774 return ret_val;
775 }
776
777 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
778 /* Set PHY page 0, register 29 to 0x0003 */
779 ret_val = e1e_wphy(hw, 29, 0x0003);
780 if (ret_val)
781 return ret_val;
782
783 /* Set PHY page 0, register 30 to 0x0000 */
784 ret_val = e1e_wphy(hw, 30, 0x0000);
785 if (ret_val)
786 return ret_val;
787 }
788
789 /* Commit the changes. */
790 if (phy->ops.commit) {
791 ret_val = phy->ops.commit(hw);
792 if (ret_val) {
793 e_dbg("Error committing the PHY changes\n");
794 return ret_val;
795 }
796 }
797
798 if (phy->type == e1000_phy_82578) {
799 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
800 if (ret_val)
801 return ret_val;
802
803 /* 82578 PHY - set the downshift count to 1x. */
804 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
805 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
806 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
807 if (ret_val)
808 return ret_val;
809 }
810
811 return 0;
812}
813
814/**
815 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
816 * @hw: pointer to the HW structure
817 *
818 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
819 * igp PHY's.
820 **/
821s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
822{
823 struct e1000_phy_info *phy = &hw->phy;
824 s32 ret_val;
825 u16 data;
826
827 ret_val = e1000_phy_hw_reset(hw);
828 if (ret_val) {
829 e_dbg("Error resetting the PHY.\n");
830 return ret_val;
831 }
832
833 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
834 * timeout issues when LFS is enabled.
835 */
836 msleep(100);
837
838 /* disable lplu d0 during driver init */
839 if (hw->phy.ops.set_d0_lplu_state) {
840 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
841 if (ret_val) {
842 e_dbg("Error Disabling LPLU D0\n");
843 return ret_val;
844 }
845 }
846 /* Configure mdi-mdix settings */
847 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
848 if (ret_val)
849 return ret_val;
850
851 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
852
853 switch (phy->mdix) {
854 case 1:
855 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
856 break;
857 case 2:
858 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
859 break;
860 case 0:
861 default:
862 data |= IGP01E1000_PSCR_AUTO_MDIX;
863 break;
864 }
865 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
866 if (ret_val)
867 return ret_val;
868
869 /* set auto-master slave resolution settings */
870 if (hw->mac.autoneg) {
871 /* when autonegotiation advertisement is only 1000Mbps then we
872 * should disable SmartSpeed and enable Auto MasterSlave
873 * resolution as hardware default.
874 */
875 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
876 /* Disable SmartSpeed */
877 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
878 &data);
879 if (ret_val)
880 return ret_val;
881
882 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
883 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
884 data);
885 if (ret_val)
886 return ret_val;
887
888 /* Set auto Master/Slave resolution process */
889 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
890 if (ret_val)
891 return ret_val;
892
893 data &= ~CTL1000_ENABLE_MASTER;
894 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
895 if (ret_val)
896 return ret_val;
897 }
898
899 ret_val = e1000_set_master_slave_mode(hw);
900 }
901
902 return ret_val;
903}
904
905/**
906 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
907 * @hw: pointer to the HW structure
908 *
909 * Reads the MII auto-neg advertisement register and/or the 1000T control
910 * register and if the PHY is already setup for auto-negotiation, then
911 * return successful. Otherwise, setup advertisement and flow control to
912 * the appropriate values for the wanted auto-negotiation.
913 **/
914static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
915{
916 struct e1000_phy_info *phy = &hw->phy;
917 s32 ret_val;
918 u16 mii_autoneg_adv_reg;
919 u16 mii_1000t_ctrl_reg = 0;
920
921 phy->autoneg_advertised &= phy->autoneg_mask;
922
923 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
924 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
925 if (ret_val)
926 return ret_val;
927
928 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
929 /* Read the MII 1000Base-T Control Register (Address 9). */
930 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
931 if (ret_val)
932 return ret_val;
933 }
934
935 /* Need to parse both autoneg_advertised and fc and set up
936 * the appropriate PHY registers. First we will parse for
937 * autoneg_advertised software override. Since we can advertise
938 * a plethora of combinations, we need to check each bit
939 * individually.
940 */
941
942 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
943 * Advertisement Register (Address 4) and the 1000 mb speed bits in
944 * the 1000Base-T Control Register (Address 9).
945 */
946 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
947 ADVERTISE_100HALF |
948 ADVERTISE_10FULL | ADVERTISE_10HALF);
949 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
950
951 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
952
953 /* Do we want to advertise 10 Mb Half Duplex? */
954 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
955 e_dbg("Advertise 10mb Half duplex\n");
956 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
957 }
958
959 /* Do we want to advertise 10 Mb Full Duplex? */
960 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
961 e_dbg("Advertise 10mb Full duplex\n");
962 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
963 }
964
965 /* Do we want to advertise 100 Mb Half Duplex? */
966 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
967 e_dbg("Advertise 100mb Half duplex\n");
968 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
969 }
970
971 /* Do we want to advertise 100 Mb Full Duplex? */
972 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
973 e_dbg("Advertise 100mb Full duplex\n");
974 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
975 }
976
977 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
978 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
979 e_dbg("Advertise 1000mb Half duplex request denied!\n");
980
981 /* Do we want to advertise 1000 Mb Full Duplex? */
982 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
983 e_dbg("Advertise 1000mb Full duplex\n");
984 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
985 }
986
987 /* Check for a software override of the flow control settings, and
988 * setup the PHY advertisement registers accordingly. If
989 * auto-negotiation is enabled, then software will have to set the
990 * "PAUSE" bits to the correct value in the Auto-Negotiation
991 * Advertisement Register (MII_ADVERTISE) and re-start auto-
992 * negotiation.
993 *
994 * The possible values of the "fc" parameter are:
995 * 0: Flow control is completely disabled
996 * 1: Rx flow control is enabled (we can receive pause frames
997 * but not send pause frames).
998 * 2: Tx flow control is enabled (we can send pause frames
999 * but we do not support receiving pause frames).
1000 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1001 * other: No software override. The flow control configuration
1002 * in the EEPROM is used.
1003 */
1004 switch (hw->fc.current_mode) {
1005 case e1000_fc_none:
1006 /* Flow control (Rx & Tx) is completely disabled by a
1007 * software over-ride.
1008 */
1009 mii_autoneg_adv_reg &=
1010 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1011 phy->autoneg_advertised &=
1012 ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1013 break;
1014 case e1000_fc_rx_pause:
1015 /* Rx Flow control is enabled, and Tx Flow control is
1016 * disabled, by a software over-ride.
1017 *
1018 * Since there really isn't a way to advertise that we are
1019 * capable of Rx Pause ONLY, we will advertise that we
1020 * support both symmetric and asymmetric Rx PAUSE. Later
1021 * (in e1000e_config_fc_after_link_up) we will disable the
1022 * hw's ability to send PAUSE frames.
1023 */
1024 mii_autoneg_adv_reg |=
1025 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1026 phy->autoneg_advertised |=
1027 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1028 break;
1029 case e1000_fc_tx_pause:
1030 /* Tx Flow control is enabled, and Rx Flow control is
1031 * disabled, by a software over-ride.
1032 */
1033 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1034 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1035 phy->autoneg_advertised |= ADVERTISED_Asym_Pause;
1036 phy->autoneg_advertised &= ~ADVERTISED_Pause;
1037 break;
1038 case e1000_fc_full:
1039 /* Flow control (both Rx and Tx) is enabled by a software
1040 * over-ride.
1041 */
1042 mii_autoneg_adv_reg |=
1043 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1044 phy->autoneg_advertised |=
1045 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
1046 break;
1047 default:
1048 e_dbg("Flow control param set incorrectly\n");
1049 return -E1000_ERR_CONFIG;
1050 }
1051
1052 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1053 if (ret_val)
1054 return ret_val;
1055
1056 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1057
1058 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1059 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1060
1061 return ret_val;
1062}
1063
1064/**
1065 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1066 * @hw: pointer to the HW structure
1067 *
1068 * Performs initial bounds checking on autoneg advertisement parameter, then
1069 * configure to advertise the full capability. Setup the PHY to autoneg
1070 * and restart the negotiation process between the link partner. If
1071 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1072 **/
1073static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1074{
1075 struct e1000_phy_info *phy = &hw->phy;
1076 s32 ret_val;
1077 u16 phy_ctrl;
1078
1079 /* Perform some bounds checking on the autoneg advertisement
1080 * parameter.
1081 */
1082 phy->autoneg_advertised &= phy->autoneg_mask;
1083
1084 /* If autoneg_advertised is zero, we assume it was not defaulted
1085 * by the calling code so we set to advertise full capability.
1086 */
1087 if (!phy->autoneg_advertised)
1088 phy->autoneg_advertised = phy->autoneg_mask;
1089
1090 e_dbg("Reconfiguring auto-neg advertisement params\n");
1091 ret_val = e1000_phy_setup_autoneg(hw);
1092 if (ret_val) {
1093 e_dbg("Error Setting up Auto-Negotiation\n");
1094 return ret_val;
1095 }
1096 e_dbg("Restarting Auto-Neg\n");
1097
1098 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1099 * the Auto Neg Restart bit in the PHY control register.
1100 */
1101 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1102 if (ret_val)
1103 return ret_val;
1104
1105 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1106 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1107 if (ret_val)
1108 return ret_val;
1109
1110 /* Does the user want to wait for Auto-Neg to complete here, or
1111 * check at a later time (for example, callback routine).
1112 */
1113 if (phy->autoneg_wait_to_complete) {
1114 ret_val = e1000_wait_autoneg(hw);
1115 if (ret_val) {
1116 e_dbg("Error while waiting for autoneg to complete\n");
1117 return ret_val;
1118 }
1119 }
1120
1121 hw->mac.get_link_status = true;
1122
1123 return ret_val;
1124}
1125
1126/**
1127 * e1000e_setup_copper_link - Configure copper link settings
1128 * @hw: pointer to the HW structure
1129 *
1130 * Calls the appropriate function to configure the link for auto-neg or forced
1131 * speed and duplex. Then we check for link, once link is established calls
1132 * to configure collision distance and flow control are called. If link is
1133 * not established, we return -E1000_ERR_PHY (-2).
1134 **/
1135s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1136{
1137 s32 ret_val;
1138 bool link;
1139
1140 if (hw->mac.autoneg) {
1141 /* Setup autoneg and flow control advertisement and perform
1142 * autonegotiation.
1143 */
1144 ret_val = e1000_copper_link_autoneg(hw);
1145 if (ret_val)
1146 return ret_val;
1147 } else {
1148 /* PHY will be set to 10H, 10F, 100H or 100F
1149 * depending on user settings.
1150 */
1151 e_dbg("Forcing Speed and Duplex\n");
1152 ret_val = hw->phy.ops.force_speed_duplex(hw);
1153 if (ret_val) {
1154 e_dbg("Error Forcing Speed and Duplex\n");
1155 return ret_val;
1156 }
1157 }
1158
1159 /* Check link status. Wait up to 100 microseconds for link to become
1160 * valid.
1161 */
1162 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1163 &link);
1164 if (ret_val)
1165 return ret_val;
1166
1167 if (link) {
1168 e_dbg("Valid link established!!!\n");
1169 hw->mac.ops.config_collision_dist(hw);
1170 ret_val = e1000e_config_fc_after_link_up(hw);
1171 } else {
1172 e_dbg("Unable to establish link!!!\n");
1173 }
1174
1175 return ret_val;
1176}
1177
1178/**
1179 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1180 * @hw: pointer to the HW structure
1181 *
1182 * Calls the PHY setup function to force speed and duplex. Clears the
1183 * auto-crossover to force MDI manually. Waits for link and returns
1184 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1185 **/
1186s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1187{
1188 struct e1000_phy_info *phy = &hw->phy;
1189 s32 ret_val;
1190 u16 phy_data;
1191 bool link;
1192
1193 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1194 if (ret_val)
1195 return ret_val;
1196
1197 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1198
1199 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1200 if (ret_val)
1201 return ret_val;
1202
1203 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1204 * forced whenever speed and duplex are forced.
1205 */
1206 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1207 if (ret_val)
1208 return ret_val;
1209
1210 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1211 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1212
1213 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1214 if (ret_val)
1215 return ret_val;
1216
1217 e_dbg("IGP PSCR: %X\n", phy_data);
1218
1219 udelay(1);
1220
1221 if (phy->autoneg_wait_to_complete) {
1222 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1223
1224 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1225 100000, &link);
1226 if (ret_val)
1227 return ret_val;
1228
1229 if (!link)
1230 e_dbg("Link taking longer than expected.\n");
1231
1232 /* Try once more */
1233 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1234 100000, &link);
1235 }
1236
1237 return ret_val;
1238}
1239
1240/**
1241 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1242 * @hw: pointer to the HW structure
1243 *
1244 * Calls the PHY setup function to force speed and duplex. Clears the
1245 * auto-crossover to force MDI manually. Resets the PHY to commit the
1246 * changes. If time expires while waiting for link up, we reset the DSP.
1247 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1248 * successful completion, else return corresponding error code.
1249 **/
1250s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1251{
1252 struct e1000_phy_info *phy = &hw->phy;
1253 s32 ret_val;
1254 u16 phy_data;
1255 bool link;
1256
1257 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1258 * forced whenever speed and duplex are forced.
1259 */
1260 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1261 if (ret_val)
1262 return ret_val;
1263
1264 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1265 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1266 if (ret_val)
1267 return ret_val;
1268
1269 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1270
1271 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1272 if (ret_val)
1273 return ret_val;
1274
1275 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1276
1277 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1278 if (ret_val)
1279 return ret_val;
1280
1281 /* Reset the phy to commit changes. */
1282 if (hw->phy.ops.commit) {
1283 ret_val = hw->phy.ops.commit(hw);
1284 if (ret_val)
1285 return ret_val;
1286 }
1287
1288 if (phy->autoneg_wait_to_complete) {
1289 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1290
1291 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1292 100000, &link);
1293 if (ret_val)
1294 return ret_val;
1295
1296 if (!link) {
1297 if (hw->phy.type != e1000_phy_m88) {
1298 e_dbg("Link taking longer than expected.\n");
1299 } else {
1300 /* We didn't get link.
1301 * Reset the DSP and cross our fingers.
1302 */
1303 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1304 0x001d);
1305 if (ret_val)
1306 return ret_val;
1307 ret_val = e1000e_phy_reset_dsp(hw);
1308 if (ret_val)
1309 return ret_val;
1310 }
1311 }
1312
1313 /* Try once more */
1314 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1315 100000, &link);
1316 if (ret_val)
1317 return ret_val;
1318 }
1319
1320 if (hw->phy.type != e1000_phy_m88)
1321 return 0;
1322
1323 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1324 if (ret_val)
1325 return ret_val;
1326
1327 /* Resetting the phy means we need to re-force TX_CLK in the
1328 * Extended PHY Specific Control Register to 25MHz clock from
1329 * the reset value of 2.5MHz.
1330 */
1331 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1332 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1333 if (ret_val)
1334 return ret_val;
1335
1336 /* In addition, we must re-enable CRS on Tx for both half and full
1337 * duplex.
1338 */
1339 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1340 if (ret_val)
1341 return ret_val;
1342
1343 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1344 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1345
1346 return ret_val;
1347}
1348
1349/**
1350 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1351 * @hw: pointer to the HW structure
1352 *
1353 * Forces the speed and duplex settings of the PHY.
1354 * This is a function pointer entry point only called by
1355 * PHY setup routines.
1356 **/
1357s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1358{
1359 struct e1000_phy_info *phy = &hw->phy;
1360 s32 ret_val;
1361 u16 data;
1362 bool link;
1363
1364 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1365 if (ret_val)
1366 return ret_val;
1367
1368 e1000e_phy_force_speed_duplex_setup(hw, &data);
1369
1370 ret_val = e1e_wphy(hw, MII_BMCR, data);
1371 if (ret_val)
1372 return ret_val;
1373
1374 /* Disable MDI-X support for 10/100 */
1375 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1376 if (ret_val)
1377 return ret_val;
1378
1379 data &= ~IFE_PMC_AUTO_MDIX;
1380 data &= ~IFE_PMC_FORCE_MDIX;
1381
1382 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1383 if (ret_val)
1384 return ret_val;
1385
1386 e_dbg("IFE PMC: %X\n", data);
1387
1388 udelay(1);
1389
1390 if (phy->autoneg_wait_to_complete) {
1391 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1392
1393 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1394 100000, &link);
1395 if (ret_val)
1396 return ret_val;
1397
1398 if (!link)
1399 e_dbg("Link taking longer than expected.\n");
1400
1401 /* Try once more */
1402 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1403 100000, &link);
1404 if (ret_val)
1405 return ret_val;
1406 }
1407
1408 return 0;
1409}
1410
1411/**
1412 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1413 * @hw: pointer to the HW structure
1414 * @phy_ctrl: pointer to current value of MII_BMCR
1415 *
1416 * Forces speed and duplex on the PHY by doing the following: disable flow
1417 * control, force speed/duplex on the MAC, disable auto speed detection,
1418 * disable auto-negotiation, configure duplex, configure speed, configure
1419 * the collision distance, write configuration to CTRL register. The
1420 * caller must write to the MII_BMCR register for these settings to
1421 * take affect.
1422 **/
1423void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1424{
1425 struct e1000_mac_info *mac = &hw->mac;
1426 u32 ctrl;
1427
1428 /* Turn off flow control when forcing speed/duplex */
1429 hw->fc.current_mode = e1000_fc_none;
1430
1431 /* Force speed/duplex on the mac */
1432 ctrl = er32(CTRL);
1433 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1434 ctrl &= ~E1000_CTRL_SPD_SEL;
1435
1436 /* Disable Auto Speed Detection */
1437 ctrl &= ~E1000_CTRL_ASDE;
1438
1439 /* Disable autoneg on the phy */
1440 *phy_ctrl &= ~BMCR_ANENABLE;
1441
1442 /* Forcing Full or Half Duplex? */
1443 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1444 ctrl &= ~E1000_CTRL_FD;
1445 *phy_ctrl &= ~BMCR_FULLDPLX;
1446 e_dbg("Half Duplex\n");
1447 } else {
1448 ctrl |= E1000_CTRL_FD;
1449 *phy_ctrl |= BMCR_FULLDPLX;
1450 e_dbg("Full Duplex\n");
1451 }
1452
1453 /* Forcing 10mb or 100mb? */
1454 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1455 ctrl |= E1000_CTRL_SPD_100;
1456 *phy_ctrl |= BMCR_SPEED100;
1457 *phy_ctrl &= ~BMCR_SPEED1000;
1458 e_dbg("Forcing 100mb\n");
1459 } else {
1460 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1461 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1462 e_dbg("Forcing 10mb\n");
1463 }
1464
1465 hw->mac.ops.config_collision_dist(hw);
1466
1467 ew32(CTRL, ctrl);
1468}
1469
1470/**
1471 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1472 * @hw: pointer to the HW structure
1473 * @active: boolean used to enable/disable lplu
1474 *
1475 * Success returns 0, Failure returns 1
1476 *
1477 * The low power link up (lplu) state is set to the power management level D3
1478 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1479 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1480 * is used during Dx states where the power conservation is most important.
1481 * During driver activity, SmartSpeed should be enabled so performance is
1482 * maintained.
1483 **/
1484s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1485{
1486 struct e1000_phy_info *phy = &hw->phy;
1487 s32 ret_val;
1488 u16 data;
1489
1490 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1491 if (ret_val)
1492 return ret_val;
1493
1494 if (!active) {
1495 data &= ~IGP02E1000_PM_D3_LPLU;
1496 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1497 if (ret_val)
1498 return ret_val;
1499 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1500 * during Dx states where the power conservation is most
1501 * important. During driver activity we should enable
1502 * SmartSpeed, so performance is maintained.
1503 */
1504 if (phy->smart_speed == e1000_smart_speed_on) {
1505 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1506 &data);
1507 if (ret_val)
1508 return ret_val;
1509
1510 data |= IGP01E1000_PSCFR_SMART_SPEED;
1511 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1512 data);
1513 if (ret_val)
1514 return ret_val;
1515 } else if (phy->smart_speed == e1000_smart_speed_off) {
1516 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1517 &data);
1518 if (ret_val)
1519 return ret_val;
1520
1521 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1522 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1523 data);
1524 if (ret_val)
1525 return ret_val;
1526 }
1527 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1528 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1529 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1530 data |= IGP02E1000_PM_D3_LPLU;
1531 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1532 if (ret_val)
1533 return ret_val;
1534
1535 /* When LPLU is enabled, we should disable SmartSpeed */
1536 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1537 if (ret_val)
1538 return ret_val;
1539
1540 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1541 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1542 }
1543
1544 return ret_val;
1545}
1546
1547/**
1548 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1549 * @hw: pointer to the HW structure
1550 *
1551 * Success returns 0, Failure returns 1
1552 *
1553 * A downshift is detected by querying the PHY link health.
1554 **/
1555s32 e1000e_check_downshift(struct e1000_hw *hw)
1556{
1557 struct e1000_phy_info *phy = &hw->phy;
1558 s32 ret_val;
1559 u16 phy_data, offset, mask;
1560
1561 switch (phy->type) {
1562 case e1000_phy_m88:
1563 case e1000_phy_gg82563:
1564 case e1000_phy_bm:
1565 case e1000_phy_82578:
1566 offset = M88E1000_PHY_SPEC_STATUS;
1567 mask = M88E1000_PSSR_DOWNSHIFT;
1568 break;
1569 case e1000_phy_igp_2:
1570 case e1000_phy_igp_3:
1571 offset = IGP01E1000_PHY_LINK_HEALTH;
1572 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1573 break;
1574 default:
1575 /* speed downshift not supported */
1576 phy->speed_downgraded = false;
1577 return 0;
1578 }
1579
1580 ret_val = e1e_rphy(hw, offset, &phy_data);
1581
1582 if (!ret_val)
1583 phy->speed_downgraded = !!(phy_data & mask);
1584
1585 return ret_val;
1586}
1587
1588/**
1589 * e1000_check_polarity_m88 - Checks the polarity.
1590 * @hw: pointer to the HW structure
1591 *
1592 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1593 *
1594 * Polarity is determined based on the PHY specific status register.
1595 **/
1596s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1597{
1598 struct e1000_phy_info *phy = &hw->phy;
1599 s32 ret_val;
1600 u16 data;
1601
1602 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1603
1604 if (!ret_val)
1605 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1606 ? e1000_rev_polarity_reversed
1607 : e1000_rev_polarity_normal);
1608
1609 return ret_val;
1610}
1611
1612/**
1613 * e1000_check_polarity_igp - Checks the polarity.
1614 * @hw: pointer to the HW structure
1615 *
1616 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1617 *
1618 * Polarity is determined based on the PHY port status register, and the
1619 * current speed (since there is no polarity at 100Mbps).
1620 **/
1621s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1622{
1623 struct e1000_phy_info *phy = &hw->phy;
1624 s32 ret_val;
1625 u16 data, offset, mask;
1626
1627 /* Polarity is determined based on the speed of
1628 * our connection.
1629 */
1630 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1631 if (ret_val)
1632 return ret_val;
1633
1634 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1635 IGP01E1000_PSSR_SPEED_1000MBPS) {
1636 offset = IGP01E1000_PHY_PCS_INIT_REG;
1637 mask = IGP01E1000_PHY_POLARITY_MASK;
1638 } else {
1639 /* This really only applies to 10Mbps since
1640 * there is no polarity for 100Mbps (always 0).
1641 */
1642 offset = IGP01E1000_PHY_PORT_STATUS;
1643 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1644 }
1645
1646 ret_val = e1e_rphy(hw, offset, &data);
1647
1648 if (!ret_val)
1649 phy->cable_polarity = ((data & mask)
1650 ? e1000_rev_polarity_reversed
1651 : e1000_rev_polarity_normal);
1652
1653 return ret_val;
1654}
1655
1656/**
1657 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1658 * @hw: pointer to the HW structure
1659 *
1660 * Polarity is determined on the polarity reversal feature being enabled.
1661 **/
1662s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1663{
1664 struct e1000_phy_info *phy = &hw->phy;
1665 s32 ret_val;
1666 u16 phy_data, offset, mask;
1667
1668 /* Polarity is determined based on the reversal feature being enabled.
1669 */
1670 if (phy->polarity_correction) {
1671 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1672 mask = IFE_PESC_POLARITY_REVERSED;
1673 } else {
1674 offset = IFE_PHY_SPECIAL_CONTROL;
1675 mask = IFE_PSC_FORCE_POLARITY;
1676 }
1677
1678 ret_val = e1e_rphy(hw, offset, &phy_data);
1679
1680 if (!ret_val)
1681 phy->cable_polarity = ((phy_data & mask)
1682 ? e1000_rev_polarity_reversed
1683 : e1000_rev_polarity_normal);
1684
1685 return ret_val;
1686}
1687
1688/**
1689 * e1000_wait_autoneg - Wait for auto-neg completion
1690 * @hw: pointer to the HW structure
1691 *
1692 * Waits for auto-negotiation to complete or for the auto-negotiation time
1693 * limit to expire, which ever happens first.
1694 **/
1695static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1696{
1697 s32 ret_val = 0;
1698 u16 i, phy_status;
1699
1700 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1701 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1702 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1703 if (ret_val)
1704 break;
1705 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1706 if (ret_val)
1707 break;
1708 if (phy_status & BMSR_ANEGCOMPLETE)
1709 break;
1710 msleep(100);
1711 }
1712
1713 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1714 * has completed.
1715 */
1716 return ret_val;
1717}
1718
1719/**
1720 * e1000e_phy_has_link_generic - Polls PHY for link
1721 * @hw: pointer to the HW structure
1722 * @iterations: number of times to poll for link
1723 * @usec_interval: delay between polling attempts
1724 * @success: pointer to whether polling was successful or not
1725 *
1726 * Polls the PHY status register for link, 'iterations' number of times.
1727 **/
1728s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1729 u32 usec_interval, bool *success)
1730{
1731 s32 ret_val = 0;
1732 u16 i, phy_status;
1733
1734 *success = false;
1735 for (i = 0; i < iterations; i++) {
1736 /* Some PHYs require the MII_BMSR register to be read
1737 * twice due to the link bit being sticky. No harm doing
1738 * it across the board.
1739 */
1740 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1741 if (ret_val) {
1742 /* If the first read fails, another entity may have
1743 * ownership of the resources, wait and try again to
1744 * see if they have relinquished the resources yet.
1745 */
1746 if (usec_interval >= 1000)
1747 msleep(usec_interval / 1000);
1748 else
1749 udelay(usec_interval);
1750 }
1751 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1752 if (ret_val)
1753 break;
1754 if (phy_status & BMSR_LSTATUS) {
1755 *success = true;
1756 break;
1757 }
1758 if (usec_interval >= 1000)
1759 msleep(usec_interval / 1000);
1760 else
1761 udelay(usec_interval);
1762 }
1763
1764 return ret_val;
1765}
1766
1767/**
1768 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1769 * @hw: pointer to the HW structure
1770 *
1771 * Reads the PHY specific status register to retrieve the cable length
1772 * information. The cable length is determined by averaging the minimum and
1773 * maximum values to get the "average" cable length. The m88 PHY has four
1774 * possible cable length values, which are:
1775 * Register Value Cable Length
1776 * 0 < 50 meters
1777 * 1 50 - 80 meters
1778 * 2 80 - 110 meters
1779 * 3 110 - 140 meters
1780 * 4 > 140 meters
1781 **/
1782s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1783{
1784 struct e1000_phy_info *phy = &hw->phy;
1785 s32 ret_val;
1786 u16 phy_data, index;
1787
1788 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1789 if (ret_val)
1790 return ret_val;
1791
1792 index = FIELD_GET(M88E1000_PSSR_CABLE_LENGTH, phy_data);
1793
1794 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1795 return -E1000_ERR_PHY;
1796
1797 phy->min_cable_length = e1000_m88_cable_length_table[index];
1798 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1799
1800 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1801
1802 return 0;
1803}
1804
1805/**
1806 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1807 * @hw: pointer to the HW structure
1808 *
1809 * The automatic gain control (agc) normalizes the amplitude of the
1810 * received signal, adjusting for the attenuation produced by the
1811 * cable. By reading the AGC registers, which represent the
1812 * combination of coarse and fine gain value, the value can be put
1813 * into a lookup table to obtain the approximate cable length
1814 * for each channel.
1815 **/
1816s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1817{
1818 struct e1000_phy_info *phy = &hw->phy;
1819 s32 ret_val;
1820 u16 phy_data, i, agc_value = 0;
1821 u16 cur_agc_index, max_agc_index = 0;
1822 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1823 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1824 IGP02E1000_PHY_AGC_A,
1825 IGP02E1000_PHY_AGC_B,
1826 IGP02E1000_PHY_AGC_C,
1827 IGP02E1000_PHY_AGC_D
1828 };
1829
1830 /* Read the AGC registers for all channels */
1831 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1832 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1833 if (ret_val)
1834 return ret_val;
1835
1836 /* Getting bits 15:9, which represent the combination of
1837 * coarse and fine gain values. The result is a number
1838 * that can be put into the lookup table to obtain the
1839 * approximate cable length.
1840 */
1841 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1842 IGP02E1000_AGC_LENGTH_MASK);
1843
1844 /* Array index bound check. */
1845 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1846 (cur_agc_index == 0))
1847 return -E1000_ERR_PHY;
1848
1849 /* Remove min & max AGC values from calculation. */
1850 if (e1000_igp_2_cable_length_table[min_agc_index] >
1851 e1000_igp_2_cable_length_table[cur_agc_index])
1852 min_agc_index = cur_agc_index;
1853 if (e1000_igp_2_cable_length_table[max_agc_index] <
1854 e1000_igp_2_cable_length_table[cur_agc_index])
1855 max_agc_index = cur_agc_index;
1856
1857 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1858 }
1859
1860 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1861 e1000_igp_2_cable_length_table[max_agc_index]);
1862 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1863
1864 /* Calculate cable length with the error range of +/- 10 meters. */
1865 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1866 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1867 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1868
1869 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1870
1871 return 0;
1872}
1873
1874/**
1875 * e1000e_get_phy_info_m88 - Retrieve PHY information
1876 * @hw: pointer to the HW structure
1877 *
1878 * Valid for only copper links. Read the PHY status register (sticky read)
1879 * to verify that link is up. Read the PHY special control register to
1880 * determine the polarity and 10base-T extended distance. Read the PHY
1881 * special status register to determine MDI/MDIx and current speed. If
1882 * speed is 1000, then determine cable length, local and remote receiver.
1883 **/
1884s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1885{
1886 struct e1000_phy_info *phy = &hw->phy;
1887 s32 ret_val;
1888 u16 phy_data;
1889 bool link;
1890
1891 if (phy->media_type != e1000_media_type_copper) {
1892 e_dbg("Phy info is only valid for copper media\n");
1893 return -E1000_ERR_CONFIG;
1894 }
1895
1896 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1897 if (ret_val)
1898 return ret_val;
1899
1900 if (!link) {
1901 e_dbg("Phy info is only valid if link is up\n");
1902 return -E1000_ERR_CONFIG;
1903 }
1904
1905 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1906 if (ret_val)
1907 return ret_val;
1908
1909 phy->polarity_correction = !!(phy_data &
1910 M88E1000_PSCR_POLARITY_REVERSAL);
1911
1912 ret_val = e1000_check_polarity_m88(hw);
1913 if (ret_val)
1914 return ret_val;
1915
1916 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1917 if (ret_val)
1918 return ret_val;
1919
1920 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1921
1922 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1923 ret_val = hw->phy.ops.get_cable_length(hw);
1924 if (ret_val)
1925 return ret_val;
1926
1927 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1928 if (ret_val)
1929 return ret_val;
1930
1931 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1932 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1933
1934 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1935 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1936 } else {
1937 /* Set values to "undefined" */
1938 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1939 phy->local_rx = e1000_1000t_rx_status_undefined;
1940 phy->remote_rx = e1000_1000t_rx_status_undefined;
1941 }
1942
1943 return ret_val;
1944}
1945
1946/**
1947 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1948 * @hw: pointer to the HW structure
1949 *
1950 * Read PHY status to determine if link is up. If link is up, then
1951 * set/determine 10base-T extended distance and polarity correction. Read
1952 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1953 * determine on the cable length, local and remote receiver.
1954 **/
1955s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1956{
1957 struct e1000_phy_info *phy = &hw->phy;
1958 s32 ret_val;
1959 u16 data;
1960 bool link;
1961
1962 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1963 if (ret_val)
1964 return ret_val;
1965
1966 if (!link) {
1967 e_dbg("Phy info is only valid if link is up\n");
1968 return -E1000_ERR_CONFIG;
1969 }
1970
1971 phy->polarity_correction = true;
1972
1973 ret_val = e1000_check_polarity_igp(hw);
1974 if (ret_val)
1975 return ret_val;
1976
1977 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1978 if (ret_val)
1979 return ret_val;
1980
1981 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1982
1983 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1984 IGP01E1000_PSSR_SPEED_1000MBPS) {
1985 ret_val = phy->ops.get_cable_length(hw);
1986 if (ret_val)
1987 return ret_val;
1988
1989 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
1990 if (ret_val)
1991 return ret_val;
1992
1993 phy->local_rx = (data & LPA_1000LOCALRXOK)
1994 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1995
1996 phy->remote_rx = (data & LPA_1000REMRXOK)
1997 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1998 } else {
1999 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2000 phy->local_rx = e1000_1000t_rx_status_undefined;
2001 phy->remote_rx = e1000_1000t_rx_status_undefined;
2002 }
2003
2004 return ret_val;
2005}
2006
2007/**
2008 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2009 * @hw: pointer to the HW structure
2010 *
2011 * Populates "phy" structure with various feature states.
2012 **/
2013s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2014{
2015 struct e1000_phy_info *phy = &hw->phy;
2016 s32 ret_val;
2017 u16 data;
2018 bool link;
2019
2020 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2021 if (ret_val)
2022 return ret_val;
2023
2024 if (!link) {
2025 e_dbg("Phy info is only valid if link is up\n");
2026 return -E1000_ERR_CONFIG;
2027 }
2028
2029 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2030 if (ret_val)
2031 return ret_val;
2032 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2033
2034 if (phy->polarity_correction) {
2035 ret_val = e1000_check_polarity_ife(hw);
2036 if (ret_val)
2037 return ret_val;
2038 } else {
2039 /* Polarity is forced */
2040 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2041 ? e1000_rev_polarity_reversed
2042 : e1000_rev_polarity_normal);
2043 }
2044
2045 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2046 if (ret_val)
2047 return ret_val;
2048
2049 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2050
2051 /* The following parameters are undefined for 10/100 operation. */
2052 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2053 phy->local_rx = e1000_1000t_rx_status_undefined;
2054 phy->remote_rx = e1000_1000t_rx_status_undefined;
2055
2056 return 0;
2057}
2058
2059/**
2060 * e1000e_phy_sw_reset - PHY software reset
2061 * @hw: pointer to the HW structure
2062 *
2063 * Does a software reset of the PHY by reading the PHY control register and
2064 * setting/write the control register reset bit to the PHY.
2065 **/
2066s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2067{
2068 s32 ret_val;
2069 u16 phy_ctrl;
2070
2071 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2072 if (ret_val)
2073 return ret_val;
2074
2075 phy_ctrl |= BMCR_RESET;
2076 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2077 if (ret_val)
2078 return ret_val;
2079
2080 udelay(1);
2081
2082 return ret_val;
2083}
2084
2085/**
2086 * e1000e_phy_hw_reset_generic - PHY hardware reset
2087 * @hw: pointer to the HW structure
2088 *
2089 * Verify the reset block is not blocking us from resetting. Acquire
2090 * semaphore (if necessary) and read/set/write the device control reset
2091 * bit in the PHY. Wait the appropriate delay time for the device to
2092 * reset and release the semaphore (if necessary).
2093 **/
2094s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2095{
2096 struct e1000_phy_info *phy = &hw->phy;
2097 s32 ret_val;
2098 u32 ctrl;
2099
2100 if (phy->ops.check_reset_block) {
2101 ret_val = phy->ops.check_reset_block(hw);
2102 if (ret_val)
2103 return 0;
2104 }
2105
2106 ret_val = phy->ops.acquire(hw);
2107 if (ret_val)
2108 return ret_val;
2109
2110 ctrl = er32(CTRL);
2111 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2112 e1e_flush();
2113
2114 udelay(phy->reset_delay_us);
2115
2116 ew32(CTRL, ctrl);
2117 e1e_flush();
2118
2119 usleep_range(150, 300);
2120
2121 phy->ops.release(hw);
2122
2123 return phy->ops.get_cfg_done(hw);
2124}
2125
2126/**
2127 * e1000e_get_cfg_done_generic - Generic configuration done
2128 * @hw: pointer to the HW structure
2129 *
2130 * Generic function to wait 10 milli-seconds for configuration to complete
2131 * and return success.
2132 **/
2133s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2134{
2135 mdelay(10);
2136
2137 return 0;
2138}
2139
2140/**
2141 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2142 * @hw: pointer to the HW structure
2143 *
2144 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2145 **/
2146s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2147{
2148 e_dbg("Running IGP 3 PHY init script\n");
2149
2150 /* PHY init IGP 3 */
2151 /* Enable rise/fall, 10-mode work in class-A */
2152 e1e_wphy(hw, 0x2F5B, 0x9018);
2153 /* Remove all caps from Replica path filter */
2154 e1e_wphy(hw, 0x2F52, 0x0000);
2155 /* Bias trimming for ADC, AFE and Driver (Default) */
2156 e1e_wphy(hw, 0x2FB1, 0x8B24);
2157 /* Increase Hybrid poly bias */
2158 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2159 /* Add 4% to Tx amplitude in Gig mode */
2160 e1e_wphy(hw, 0x2010, 0x10B0);
2161 /* Disable trimming (TTT) */
2162 e1e_wphy(hw, 0x2011, 0x0000);
2163 /* Poly DC correction to 94.6% + 2% for all channels */
2164 e1e_wphy(hw, 0x20DD, 0x249A);
2165 /* ABS DC correction to 95.9% */
2166 e1e_wphy(hw, 0x20DE, 0x00D3);
2167 /* BG temp curve trim */
2168 e1e_wphy(hw, 0x28B4, 0x04CE);
2169 /* Increasing ADC OPAMP stage 1 currents to max */
2170 e1e_wphy(hw, 0x2F70, 0x29E4);
2171 /* Force 1000 ( required for enabling PHY regs configuration) */
2172 e1e_wphy(hw, 0x0000, 0x0140);
2173 /* Set upd_freq to 6 */
2174 e1e_wphy(hw, 0x1F30, 0x1606);
2175 /* Disable NPDFE */
2176 e1e_wphy(hw, 0x1F31, 0xB814);
2177 /* Disable adaptive fixed FFE (Default) */
2178 e1e_wphy(hw, 0x1F35, 0x002A);
2179 /* Enable FFE hysteresis */
2180 e1e_wphy(hw, 0x1F3E, 0x0067);
2181 /* Fixed FFE for short cable lengths */
2182 e1e_wphy(hw, 0x1F54, 0x0065);
2183 /* Fixed FFE for medium cable lengths */
2184 e1e_wphy(hw, 0x1F55, 0x002A);
2185 /* Fixed FFE for long cable lengths */
2186 e1e_wphy(hw, 0x1F56, 0x002A);
2187 /* Enable Adaptive Clip Threshold */
2188 e1e_wphy(hw, 0x1F72, 0x3FB0);
2189 /* AHT reset limit to 1 */
2190 e1e_wphy(hw, 0x1F76, 0xC0FF);
2191 /* Set AHT master delay to 127 msec */
2192 e1e_wphy(hw, 0x1F77, 0x1DEC);
2193 /* Set scan bits for AHT */
2194 e1e_wphy(hw, 0x1F78, 0xF9EF);
2195 /* Set AHT Preset bits */
2196 e1e_wphy(hw, 0x1F79, 0x0210);
2197 /* Change integ_factor of channel A to 3 */
2198 e1e_wphy(hw, 0x1895, 0x0003);
2199 /* Change prop_factor of channels BCD to 8 */
2200 e1e_wphy(hw, 0x1796, 0x0008);
2201 /* Change cg_icount + enable integbp for channels BCD */
2202 e1e_wphy(hw, 0x1798, 0xD008);
2203 /* Change cg_icount + enable integbp + change prop_factor_master
2204 * to 8 for channel A
2205 */
2206 e1e_wphy(hw, 0x1898, 0xD918);
2207 /* Disable AHT in Slave mode on channel A */
2208 e1e_wphy(hw, 0x187A, 0x0800);
2209 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2210 * Enable SPD+B2B
2211 */
2212 e1e_wphy(hw, 0x0019, 0x008D);
2213 /* Enable restart AN on an1000_dis change */
2214 e1e_wphy(hw, 0x001B, 0x2080);
2215 /* Enable wh_fifo read clock in 10/100 modes */
2216 e1e_wphy(hw, 0x0014, 0x0045);
2217 /* Restart AN, Speed selection is 1000 */
2218 e1e_wphy(hw, 0x0000, 0x1340);
2219
2220 return 0;
2221}
2222
2223/**
2224 * e1000e_get_phy_type_from_id - Get PHY type from id
2225 * @phy_id: phy_id read from the phy
2226 *
2227 * Returns the phy type from the id.
2228 **/
2229enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2230{
2231 enum e1000_phy_type phy_type = e1000_phy_unknown;
2232
2233 switch (phy_id) {
2234 case M88E1000_I_PHY_ID:
2235 case M88E1000_E_PHY_ID:
2236 case M88E1111_I_PHY_ID:
2237 case M88E1011_I_PHY_ID:
2238 phy_type = e1000_phy_m88;
2239 break;
2240 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2241 phy_type = e1000_phy_igp_2;
2242 break;
2243 case GG82563_E_PHY_ID:
2244 phy_type = e1000_phy_gg82563;
2245 break;
2246 case IGP03E1000_E_PHY_ID:
2247 phy_type = e1000_phy_igp_3;
2248 break;
2249 case IFE_E_PHY_ID:
2250 case IFE_PLUS_E_PHY_ID:
2251 case IFE_C_E_PHY_ID:
2252 phy_type = e1000_phy_ife;
2253 break;
2254 case BME1000_E_PHY_ID:
2255 case BME1000_E_PHY_ID_R2:
2256 phy_type = e1000_phy_bm;
2257 break;
2258 case I82578_E_PHY_ID:
2259 phy_type = e1000_phy_82578;
2260 break;
2261 case I82577_E_PHY_ID:
2262 phy_type = e1000_phy_82577;
2263 break;
2264 case I82579_E_PHY_ID:
2265 phy_type = e1000_phy_82579;
2266 break;
2267 case I217_E_PHY_ID:
2268 phy_type = e1000_phy_i217;
2269 break;
2270 default:
2271 phy_type = e1000_phy_unknown;
2272 break;
2273 }
2274 return phy_type;
2275}
2276
2277/**
2278 * e1000e_determine_phy_address - Determines PHY address.
2279 * @hw: pointer to the HW structure
2280 *
2281 * This uses a trial and error method to loop through possible PHY
2282 * addresses. It tests each by reading the PHY ID registers and
2283 * checking for a match.
2284 **/
2285s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2286{
2287 u32 phy_addr = 0;
2288 u32 i;
2289 enum e1000_phy_type phy_type = e1000_phy_unknown;
2290
2291 hw->phy.id = phy_type;
2292
2293 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2294 hw->phy.addr = phy_addr;
2295 i = 0;
2296
2297 do {
2298 e1000e_get_phy_id(hw);
2299 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2300
2301 /* If phy_type is valid, break - we found our
2302 * PHY address
2303 */
2304 if (phy_type != e1000_phy_unknown)
2305 return 0;
2306
2307 usleep_range(1000, 2000);
2308 i++;
2309 } while (i < 10);
2310 }
2311
2312 return -E1000_ERR_PHY_TYPE;
2313}
2314
2315/**
2316 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2317 * @page: page to access
2318 * @reg: register to check
2319 *
2320 * Returns the phy address for the page requested.
2321 **/
2322static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2323{
2324 u32 phy_addr = 2;
2325
2326 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2327 phy_addr = 1;
2328
2329 return phy_addr;
2330}
2331
2332/**
2333 * e1000e_write_phy_reg_bm - Write BM PHY register
2334 * @hw: pointer to the HW structure
2335 * @offset: register offset to write to
2336 * @data: data to write at register offset
2337 *
2338 * Acquires semaphore, if necessary, then writes the data to PHY register
2339 * at the offset. Release any acquired semaphores before exiting.
2340 **/
2341s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2342{
2343 s32 ret_val;
2344 u32 page = offset >> IGP_PAGE_SHIFT;
2345
2346 ret_val = hw->phy.ops.acquire(hw);
2347 if (ret_val)
2348 return ret_val;
2349
2350 /* Page 800 works differently than the rest so it has its own func */
2351 if (page == BM_WUC_PAGE) {
2352 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2353 false, false);
2354 goto release;
2355 }
2356
2357 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2358
2359 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2360 u32 page_shift, page_select;
2361
2362 /* Page select is register 31 for phy address 1 and 22 for
2363 * phy address 2 and 3. Page select is shifted only for
2364 * phy address 1.
2365 */
2366 if (hw->phy.addr == 1) {
2367 page_shift = IGP_PAGE_SHIFT;
2368 page_select = IGP01E1000_PHY_PAGE_SELECT;
2369 } else {
2370 page_shift = 0;
2371 page_select = BM_PHY_PAGE_SELECT;
2372 }
2373
2374 /* Page is shifted left, PHY expects (page x 32) */
2375 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2376 (page << page_shift));
2377 if (ret_val)
2378 goto release;
2379 }
2380
2381 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2382 data);
2383
2384release:
2385 hw->phy.ops.release(hw);
2386 return ret_val;
2387}
2388
2389/**
2390 * e1000e_read_phy_reg_bm - Read BM PHY register
2391 * @hw: pointer to the HW structure
2392 * @offset: register offset to be read
2393 * @data: pointer to the read data
2394 *
2395 * Acquires semaphore, if necessary, then reads the PHY register at offset
2396 * and storing the retrieved information in data. Release any acquired
2397 * semaphores before exiting.
2398 **/
2399s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2400{
2401 s32 ret_val;
2402 u32 page = offset >> IGP_PAGE_SHIFT;
2403
2404 ret_val = hw->phy.ops.acquire(hw);
2405 if (ret_val)
2406 return ret_val;
2407
2408 /* Page 800 works differently than the rest so it has its own func */
2409 if (page == BM_WUC_PAGE) {
2410 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2411 true, false);
2412 goto release;
2413 }
2414
2415 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2416
2417 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2418 u32 page_shift, page_select;
2419
2420 /* Page select is register 31 for phy address 1 and 22 for
2421 * phy address 2 and 3. Page select is shifted only for
2422 * phy address 1.
2423 */
2424 if (hw->phy.addr == 1) {
2425 page_shift = IGP_PAGE_SHIFT;
2426 page_select = IGP01E1000_PHY_PAGE_SELECT;
2427 } else {
2428 page_shift = 0;
2429 page_select = BM_PHY_PAGE_SELECT;
2430 }
2431
2432 /* Page is shifted left, PHY expects (page x 32) */
2433 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2434 (page << page_shift));
2435 if (ret_val)
2436 goto release;
2437 }
2438
2439 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2440 data);
2441release:
2442 hw->phy.ops.release(hw);
2443 return ret_val;
2444}
2445
2446/**
2447 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2448 * @hw: pointer to the HW structure
2449 * @offset: register offset to be read
2450 * @data: pointer to the read data
2451 *
2452 * Acquires semaphore, if necessary, then reads the PHY register at offset
2453 * and storing the retrieved information in data. Release any acquired
2454 * semaphores before exiting.
2455 **/
2456s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2457{
2458 s32 ret_val;
2459 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2460
2461 ret_val = hw->phy.ops.acquire(hw);
2462 if (ret_val)
2463 return ret_val;
2464
2465 /* Page 800 works differently than the rest so it has its own func */
2466 if (page == BM_WUC_PAGE) {
2467 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2468 true, false);
2469 goto release;
2470 }
2471
2472 hw->phy.addr = 1;
2473
2474 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2475 /* Page is shifted left, PHY expects (page x 32) */
2476 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2477 page);
2478
2479 if (ret_val)
2480 goto release;
2481 }
2482
2483 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2484 data);
2485release:
2486 hw->phy.ops.release(hw);
2487 return ret_val;
2488}
2489
2490/**
2491 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2492 * @hw: pointer to the HW structure
2493 * @offset: register offset to write to
2494 * @data: data to write at register offset
2495 *
2496 * Acquires semaphore, if necessary, then writes the data to PHY register
2497 * at the offset. Release any acquired semaphores before exiting.
2498 **/
2499s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2500{
2501 s32 ret_val;
2502 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2503
2504 ret_val = hw->phy.ops.acquire(hw);
2505 if (ret_val)
2506 return ret_val;
2507
2508 /* Page 800 works differently than the rest so it has its own func */
2509 if (page == BM_WUC_PAGE) {
2510 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2511 false, false);
2512 goto release;
2513 }
2514
2515 hw->phy.addr = 1;
2516
2517 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2518 /* Page is shifted left, PHY expects (page x 32) */
2519 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2520 page);
2521
2522 if (ret_val)
2523 goto release;
2524 }
2525
2526 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2527 data);
2528
2529release:
2530 hw->phy.ops.release(hw);
2531 return ret_val;
2532}
2533
2534/**
2535 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2536 * @hw: pointer to the HW structure
2537 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2538 *
2539 * Assumes semaphore already acquired and phy_reg points to a valid memory
2540 * address to store contents of the BM_WUC_ENABLE_REG register.
2541 **/
2542s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2543{
2544 s32 ret_val;
2545 u16 temp;
2546
2547 /* All page select, port ctrl and wakeup registers use phy address 1 */
2548 hw->phy.addr = 1;
2549
2550 /* Select Port Control Registers page */
2551 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2552 if (ret_val) {
2553 e_dbg("Could not set Port Control page\n");
2554 return ret_val;
2555 }
2556
2557 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2558 if (ret_val) {
2559 e_dbg("Could not read PHY register %d.%d\n",
2560 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2561 return ret_val;
2562 }
2563
2564 /* Enable both PHY wakeup mode and Wakeup register page writes.
2565 * Prevent a power state change by disabling ME and Host PHY wakeup.
2566 */
2567 temp = *phy_reg;
2568 temp |= BM_WUC_ENABLE_BIT;
2569 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2570
2571 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2572 if (ret_val) {
2573 e_dbg("Could not write PHY register %d.%d\n",
2574 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2575 return ret_val;
2576 }
2577
2578 /* Select Host Wakeup Registers page - caller now able to write
2579 * registers on the Wakeup registers page
2580 */
2581 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2582}
2583
2584/**
2585 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2586 * @hw: pointer to the HW structure
2587 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2588 *
2589 * Restore BM_WUC_ENABLE_REG to its original value.
2590 *
2591 * Assumes semaphore already acquired and *phy_reg is the contents of the
2592 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2593 * caller.
2594 **/
2595s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2596{
2597 s32 ret_val;
2598
2599 /* Select Port Control Registers page */
2600 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2601 if (ret_val) {
2602 e_dbg("Could not set Port Control page\n");
2603 return ret_val;
2604 }
2605
2606 /* Restore 769.17 to its original value */
2607 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2608 if (ret_val)
2609 e_dbg("Could not restore PHY register %d.%d\n",
2610 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2611
2612 return ret_val;
2613}
2614
2615/**
2616 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2617 * @hw: pointer to the HW structure
2618 * @offset: register offset to be read or written
2619 * @data: pointer to the data to read or write
2620 * @read: determines if operation is read or write
2621 * @page_set: BM_WUC_PAGE already set and access enabled
2622 *
2623 * Read the PHY register at offset and store the retrieved information in
2624 * data, or write data to PHY register at offset. Note the procedure to
2625 * access the PHY wakeup registers is different than reading the other PHY
2626 * registers. It works as such:
2627 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2628 * 2) Set page to 800 for host (801 if we were manageability)
2629 * 3) Write the address using the address opcode (0x11)
2630 * 4) Read or write the data using the data opcode (0x12)
2631 * 5) Restore 769.17.2 to its original value
2632 *
2633 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2634 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2635 *
2636 * Assumes semaphore is already acquired. When page_set==true, assumes
2637 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2638 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2639 **/
2640static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2641 u16 *data, bool read, bool page_set)
2642{
2643 s32 ret_val;
2644 u16 reg = BM_PHY_REG_NUM(offset);
2645 u16 page = BM_PHY_REG_PAGE(offset);
2646 u16 phy_reg = 0;
2647
2648 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2649 if ((hw->mac.type == e1000_pchlan) &&
2650 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2651 e_dbg("Attempting to access page %d while gig enabled.\n",
2652 page);
2653
2654 if (!page_set) {
2655 /* Enable access to PHY wakeup registers */
2656 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2657 if (ret_val) {
2658 e_dbg("Could not enable PHY wakeup reg access\n");
2659 return ret_val;
2660 }
2661 }
2662
2663 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2664
2665 /* Write the Wakeup register page offset value using opcode 0x11 */
2666 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2667 if (ret_val) {
2668 e_dbg("Could not write address opcode to page %d\n", page);
2669 return ret_val;
2670 }
2671
2672 if (read) {
2673 /* Read the Wakeup register page value using opcode 0x12 */
2674 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2675 data);
2676 } else {
2677 /* Write the Wakeup register page value using opcode 0x12 */
2678 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2679 *data);
2680 }
2681
2682 if (ret_val) {
2683 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2684 return ret_val;
2685 }
2686
2687 if (!page_set)
2688 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2689
2690 return ret_val;
2691}
2692
2693/**
2694 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2695 * @hw: pointer to the HW structure
2696 *
2697 * In the case of a PHY power down to save power, or to turn off link during a
2698 * driver unload, or wake on lan is not enabled, restore the link to previous
2699 * settings.
2700 **/
2701void e1000_power_up_phy_copper(struct e1000_hw *hw)
2702{
2703 u16 mii_reg = 0;
2704 int ret;
2705
2706 /* The PHY will retain its settings across a power down/up cycle */
2707 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2708 if (ret) {
2709 e_dbg("Error reading PHY register\n");
2710 return;
2711 }
2712 mii_reg &= ~BMCR_PDOWN;
2713 e1e_wphy(hw, MII_BMCR, mii_reg);
2714}
2715
2716/**
2717 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2718 * @hw: pointer to the HW structure
2719 *
2720 * In the case of a PHY power down to save power, or to turn off link during a
2721 * driver unload, or wake on lan is not enabled, restore the link to previous
2722 * settings.
2723 **/
2724void e1000_power_down_phy_copper(struct e1000_hw *hw)
2725{
2726 u16 mii_reg = 0;
2727 int ret;
2728
2729 /* The PHY will retain its settings across a power down/up cycle */
2730 ret = e1e_rphy(hw, MII_BMCR, &mii_reg);
2731 if (ret) {
2732 e_dbg("Error reading PHY register\n");
2733 return;
2734 }
2735 mii_reg |= BMCR_PDOWN;
2736 e1e_wphy(hw, MII_BMCR, mii_reg);
2737 usleep_range(1000, 2000);
2738}
2739
2740/**
2741 * __e1000_read_phy_reg_hv - Read HV PHY register
2742 * @hw: pointer to the HW structure
2743 * @offset: register offset to be read
2744 * @data: pointer to the read data
2745 * @locked: semaphore has already been acquired or not
2746 * @page_set: BM_WUC_PAGE already set and access enabled
2747 *
2748 * Acquires semaphore, if necessary, then reads the PHY register at offset
2749 * and stores the retrieved information in data. Release any acquired
2750 * semaphore before exiting.
2751 **/
2752static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2753 bool locked, bool page_set)
2754{
2755 s32 ret_val;
2756 u16 page = BM_PHY_REG_PAGE(offset);
2757 u16 reg = BM_PHY_REG_NUM(offset);
2758 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2759
2760 if (!locked) {
2761 ret_val = hw->phy.ops.acquire(hw);
2762 if (ret_val)
2763 return ret_val;
2764 }
2765
2766 /* Page 800 works differently than the rest so it has its own func */
2767 if (page == BM_WUC_PAGE) {
2768 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2769 true, page_set);
2770 goto out;
2771 }
2772
2773 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2774 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2775 data, true);
2776 goto out;
2777 }
2778
2779 if (!page_set) {
2780 if (page == HV_INTC_FC_PAGE_START)
2781 page = 0;
2782
2783 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2784 /* Page is shifted left, PHY expects (page x 32) */
2785 ret_val = e1000_set_page_igp(hw,
2786 (page << IGP_PAGE_SHIFT));
2787
2788 hw->phy.addr = phy_addr;
2789
2790 if (ret_val)
2791 goto out;
2792 }
2793 }
2794
2795 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2796 page << IGP_PAGE_SHIFT, reg);
2797
2798 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2799out:
2800 if (!locked)
2801 hw->phy.ops.release(hw);
2802
2803 return ret_val;
2804}
2805
2806/**
2807 * e1000_read_phy_reg_hv - Read HV PHY register
2808 * @hw: pointer to the HW structure
2809 * @offset: register offset to be read
2810 * @data: pointer to the read data
2811 *
2812 * Acquires semaphore then reads the PHY register at offset and stores
2813 * the retrieved information in data. Release the acquired semaphore
2814 * before exiting.
2815 **/
2816s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2817{
2818 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2819}
2820
2821/**
2822 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2823 * @hw: pointer to the HW structure
2824 * @offset: register offset to be read
2825 * @data: pointer to the read data
2826 *
2827 * Reads the PHY register at offset and stores the retrieved information
2828 * in data. Assumes semaphore already acquired.
2829 **/
2830s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2831{
2832 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2833}
2834
2835/**
2836 * e1000_read_phy_reg_page_hv - Read HV PHY register
2837 * @hw: pointer to the HW structure
2838 * @offset: register offset to write to
2839 * @data: data to write at register offset
2840 *
2841 * Reads the PHY register at offset and stores the retrieved information
2842 * in data. Assumes semaphore already acquired and page already set.
2843 **/
2844s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2845{
2846 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2847}
2848
2849/**
2850 * __e1000_write_phy_reg_hv - Write HV PHY register
2851 * @hw: pointer to the HW structure
2852 * @offset: register offset to write to
2853 * @data: data to write at register offset
2854 * @locked: semaphore has already been acquired or not
2855 * @page_set: BM_WUC_PAGE already set and access enabled
2856 *
2857 * Acquires semaphore, if necessary, then writes the data to PHY register
2858 * at the offset. Release any acquired semaphores before exiting.
2859 **/
2860static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2861 bool locked, bool page_set)
2862{
2863 s32 ret_val;
2864 u16 page = BM_PHY_REG_PAGE(offset);
2865 u16 reg = BM_PHY_REG_NUM(offset);
2866 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2867
2868 if (!locked) {
2869 ret_val = hw->phy.ops.acquire(hw);
2870 if (ret_val)
2871 return ret_val;
2872 }
2873
2874 /* Page 800 works differently than the rest so it has its own func */
2875 if (page == BM_WUC_PAGE) {
2876 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2877 false, page_set);
2878 goto out;
2879 }
2880
2881 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2882 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2883 &data, false);
2884 goto out;
2885 }
2886
2887 if (!page_set) {
2888 if (page == HV_INTC_FC_PAGE_START)
2889 page = 0;
2890
2891 /* Workaround MDIO accesses being disabled after entering IEEE
2892 * Power Down (when bit 11 of the PHY Control register is set)
2893 */
2894 if ((hw->phy.type == e1000_phy_82578) &&
2895 (hw->phy.revision >= 1) &&
2896 (hw->phy.addr == 2) &&
2897 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2898 u16 data2 = 0x7EFF;
2899
2900 ret_val = e1000_access_phy_debug_regs_hv(hw,
2901 BIT(6) | 0x3,
2902 &data2, false);
2903 if (ret_val)
2904 goto out;
2905 }
2906
2907 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2908 /* Page is shifted left, PHY expects (page x 32) */
2909 ret_val = e1000_set_page_igp(hw,
2910 (page << IGP_PAGE_SHIFT));
2911
2912 hw->phy.addr = phy_addr;
2913
2914 if (ret_val)
2915 goto out;
2916 }
2917 }
2918
2919 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2920 page << IGP_PAGE_SHIFT, reg);
2921
2922 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2923 data);
2924
2925out:
2926 if (!locked)
2927 hw->phy.ops.release(hw);
2928
2929 return ret_val;
2930}
2931
2932/**
2933 * e1000_write_phy_reg_hv - Write HV PHY register
2934 * @hw: pointer to the HW structure
2935 * @offset: register offset to write to
2936 * @data: data to write at register offset
2937 *
2938 * Acquires semaphore then writes the data to PHY register at the offset.
2939 * Release the acquired semaphores before exiting.
2940 **/
2941s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2942{
2943 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2944}
2945
2946/**
2947 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2948 * @hw: pointer to the HW structure
2949 * @offset: register offset to write to
2950 * @data: data to write at register offset
2951 *
2952 * Writes the data to PHY register at the offset. Assumes semaphore
2953 * already acquired.
2954 **/
2955s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2956{
2957 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2958}
2959
2960/**
2961 * e1000_write_phy_reg_page_hv - Write HV PHY register
2962 * @hw: pointer to the HW structure
2963 * @offset: register offset to write to
2964 * @data: data to write at register offset
2965 *
2966 * Writes the data to PHY register at the offset. Assumes semaphore
2967 * already acquired and page already set.
2968 **/
2969s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2970{
2971 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2972}
2973
2974/**
2975 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2976 * @page: page to be accessed
2977 **/
2978static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2979{
2980 u32 phy_addr = 2;
2981
2982 if (page >= HV_INTC_FC_PAGE_START)
2983 phy_addr = 1;
2984
2985 return phy_addr;
2986}
2987
2988/**
2989 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2990 * @hw: pointer to the HW structure
2991 * @offset: register offset to be read or written
2992 * @data: pointer to the data to be read or written
2993 * @read: determines if operation is read or write
2994 *
2995 * Reads the PHY register at offset and stores the retrieved information
2996 * in data. Assumes semaphore already acquired. Note that the procedure
2997 * to access these regs uses the address port and data port to read/write.
2998 * These accesses done with PHY address 2 and without using pages.
2999 **/
3000static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3001 u16 *data, bool read)
3002{
3003 s32 ret_val;
3004 u32 addr_reg;
3005 u32 data_reg;
3006
3007 /* This takes care of the difference with desktop vs mobile phy */
3008 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3009 I82578_ADDR_REG : I82577_ADDR_REG);
3010 data_reg = addr_reg + 1;
3011
3012 /* All operations in this function are phy address 2 */
3013 hw->phy.addr = 2;
3014
3015 /* masking with 0x3F to remove the page from offset */
3016 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3017 if (ret_val) {
3018 e_dbg("Could not write the Address Offset port register\n");
3019 return ret_val;
3020 }
3021
3022 /* Read or write the data value next */
3023 if (read)
3024 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3025 else
3026 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3027
3028 if (ret_val)
3029 e_dbg("Could not access the Data port register\n");
3030
3031 return ret_val;
3032}
3033
3034/**
3035 * e1000_link_stall_workaround_hv - Si workaround
3036 * @hw: pointer to the HW structure
3037 *
3038 * This function works around a Si bug where the link partner can get
3039 * a link up indication before the PHY does. If small packets are sent
3040 * by the link partner they can be placed in the packet buffer without
3041 * being properly accounted for by the PHY and will stall preventing
3042 * further packets from being received. The workaround is to clear the
3043 * packet buffer after the PHY detects link up.
3044 **/
3045s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3046{
3047 s32 ret_val = 0;
3048 u16 data;
3049
3050 if (hw->phy.type != e1000_phy_82578)
3051 return 0;
3052
3053 /* Do not apply workaround if in PHY loopback bit 14 set */
3054 ret_val = e1e_rphy(hw, MII_BMCR, &data);
3055 if (ret_val) {
3056 e_dbg("Error reading PHY register\n");
3057 return ret_val;
3058 }
3059 if (data & BMCR_LOOPBACK)
3060 return 0;
3061
3062 /* check if link is up and at 1Gbps */
3063 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3064 if (ret_val)
3065 return ret_val;
3066
3067 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3068 BM_CS_STATUS_SPEED_MASK);
3069
3070 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3071 BM_CS_STATUS_SPEED_1000))
3072 return 0;
3073
3074 msleep(200);
3075
3076 /* flush the packets in the fifo buffer */
3077 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3078 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3079 HV_MUX_DATA_CTRL_FORCE_SPEED));
3080 if (ret_val)
3081 return ret_val;
3082
3083 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3084}
3085
3086/**
3087 * e1000_check_polarity_82577 - Checks the polarity.
3088 * @hw: pointer to the HW structure
3089 *
3090 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3091 *
3092 * Polarity is determined based on the PHY specific status register.
3093 **/
3094s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3095{
3096 struct e1000_phy_info *phy = &hw->phy;
3097 s32 ret_val;
3098 u16 data;
3099
3100 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3101
3102 if (!ret_val)
3103 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3104 ? e1000_rev_polarity_reversed
3105 : e1000_rev_polarity_normal);
3106
3107 return ret_val;
3108}
3109
3110/**
3111 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3112 * @hw: pointer to the HW structure
3113 *
3114 * Calls the PHY setup function to force speed and duplex.
3115 **/
3116s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3117{
3118 struct e1000_phy_info *phy = &hw->phy;
3119 s32 ret_val;
3120 u16 phy_data;
3121 bool link;
3122
3123 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3124 if (ret_val)
3125 return ret_val;
3126
3127 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3128
3129 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3130 if (ret_val)
3131 return ret_val;
3132
3133 udelay(1);
3134
3135 if (phy->autoneg_wait_to_complete) {
3136 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3137
3138 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3139 100000, &link);
3140 if (ret_val)
3141 return ret_val;
3142
3143 if (!link)
3144 e_dbg("Link taking longer than expected.\n");
3145
3146 /* Try once more */
3147 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3148 100000, &link);
3149 }
3150
3151 return ret_val;
3152}
3153
3154/**
3155 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3156 * @hw: pointer to the HW structure
3157 *
3158 * Read PHY status to determine if link is up. If link is up, then
3159 * set/determine 10base-T extended distance and polarity correction. Read
3160 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3161 * determine on the cable length, local and remote receiver.
3162 **/
3163s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3164{
3165 struct e1000_phy_info *phy = &hw->phy;
3166 s32 ret_val;
3167 u16 data;
3168 bool link;
3169
3170 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3171 if (ret_val)
3172 return ret_val;
3173
3174 if (!link) {
3175 e_dbg("Phy info is only valid if link is up\n");
3176 return -E1000_ERR_CONFIG;
3177 }
3178
3179 phy->polarity_correction = true;
3180
3181 ret_val = e1000_check_polarity_82577(hw);
3182 if (ret_val)
3183 return ret_val;
3184
3185 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3186 if (ret_val)
3187 return ret_val;
3188
3189 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3190
3191 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3192 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3193 ret_val = hw->phy.ops.get_cable_length(hw);
3194 if (ret_val)
3195 return ret_val;
3196
3197 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3198 if (ret_val)
3199 return ret_val;
3200
3201 phy->local_rx = (data & LPA_1000LOCALRXOK)
3202 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3203
3204 phy->remote_rx = (data & LPA_1000REMRXOK)
3205 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3206 } else {
3207 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3208 phy->local_rx = e1000_1000t_rx_status_undefined;
3209 phy->remote_rx = e1000_1000t_rx_status_undefined;
3210 }
3211
3212 return 0;
3213}
3214
3215/**
3216 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3217 * @hw: pointer to the HW structure
3218 *
3219 * Reads the diagnostic status register and verifies result is valid before
3220 * placing it in the phy_cable_length field.
3221 **/
3222s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3223{
3224 struct e1000_phy_info *phy = &hw->phy;
3225 s32 ret_val;
3226 u16 phy_data, length;
3227
3228 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3229 if (ret_val)
3230 return ret_val;
3231
3232 length = FIELD_GET(I82577_DSTATUS_CABLE_LENGTH, phy_data);
3233
3234 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3235 return -E1000_ERR_PHY;
3236
3237 phy->cable_length = length;
3238
3239 return 0;
3240}
1// SPDX-License-Identifier: GPL-2.0
2/* Intel PRO/1000 Linux driver
3 * Copyright(c) 1999 - 2015 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in
15 * the file called "COPYING".
16 *
17 * Contact Information:
18 * Linux NICS <linux.nics@intel.com>
19 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
20 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
21 */
22
23#include "e1000.h"
24
25static s32 e1000_wait_autoneg(struct e1000_hw *hw);
26static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
27 u16 *data, bool read, bool page_set);
28static u32 e1000_get_phy_addr_for_hv_page(u32 page);
29static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
30 u16 *data, bool read);
31
32/* Cable length tables */
33static const u16 e1000_m88_cable_length_table[] = {
34 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED
35};
36
37#define M88E1000_CABLE_LENGTH_TABLE_SIZE \
38 ARRAY_SIZE(e1000_m88_cable_length_table)
39
40static const u16 e1000_igp_2_cable_length_table[] = {
41 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
42 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
43 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
44 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
45 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
46 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
47 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
48 124
49};
50
51#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
52 ARRAY_SIZE(e1000_igp_2_cable_length_table)
53
54/**
55 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
56 * @hw: pointer to the HW structure
57 *
58 * Read the PHY management control register and check whether a PHY reset
59 * is blocked. If a reset is not blocked return 0, otherwise
60 * return E1000_BLK_PHY_RESET (12).
61 **/
62s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
63{
64 u32 manc;
65
66 manc = er32(MANC);
67
68 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? E1000_BLK_PHY_RESET : 0;
69}
70
71/**
72 * e1000e_get_phy_id - Retrieve the PHY ID and revision
73 * @hw: pointer to the HW structure
74 *
75 * Reads the PHY registers and stores the PHY ID and possibly the PHY
76 * revision in the hardware structure.
77 **/
78s32 e1000e_get_phy_id(struct e1000_hw *hw)
79{
80 struct e1000_phy_info *phy = &hw->phy;
81 s32 ret_val = 0;
82 u16 phy_id;
83 u16 retry_count = 0;
84
85 if (!phy->ops.read_reg)
86 return 0;
87
88 while (retry_count < 2) {
89 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
90 if (ret_val)
91 return ret_val;
92
93 phy->id = (u32)(phy_id << 16);
94 usleep_range(20, 40);
95 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
96 if (ret_val)
97 return ret_val;
98
99 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
100 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
101
102 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
103 return 0;
104
105 retry_count++;
106 }
107
108 return 0;
109}
110
111/**
112 * e1000e_phy_reset_dsp - Reset PHY DSP
113 * @hw: pointer to the HW structure
114 *
115 * Reset the digital signal processor.
116 **/
117s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
118{
119 s32 ret_val;
120
121 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
122 if (ret_val)
123 return ret_val;
124
125 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
126}
127
128/**
129 * e1000e_read_phy_reg_mdic - Read MDI control register
130 * @hw: pointer to the HW structure
131 * @offset: register offset to be read
132 * @data: pointer to the read data
133 *
134 * Reads the MDI control register in the PHY at offset and stores the
135 * information read to data.
136 **/
137s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
138{
139 struct e1000_phy_info *phy = &hw->phy;
140 u32 i, mdic = 0;
141
142 if (offset > MAX_PHY_REG_ADDRESS) {
143 e_dbg("PHY Address %d is out of range\n", offset);
144 return -E1000_ERR_PARAM;
145 }
146
147 /* Set up Op-code, Phy Address, and register offset in the MDI
148 * Control register. The MAC will take care of interfacing with the
149 * PHY to retrieve the desired data.
150 */
151 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
152 (phy->addr << E1000_MDIC_PHY_SHIFT) |
153 (E1000_MDIC_OP_READ));
154
155 ew32(MDIC, mdic);
156
157 /* Poll the ready bit to see if the MDI read completed
158 * Increasing the time out as testing showed failures with
159 * the lower time out
160 */
161 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
162 udelay(50);
163 mdic = er32(MDIC);
164 if (mdic & E1000_MDIC_READY)
165 break;
166 }
167 if (!(mdic & E1000_MDIC_READY)) {
168 e_dbg("MDI Read did not complete\n");
169 return -E1000_ERR_PHY;
170 }
171 if (mdic & E1000_MDIC_ERROR) {
172 e_dbg("MDI Error\n");
173 return -E1000_ERR_PHY;
174 }
175 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
176 e_dbg("MDI Read offset error - requested %d, returned %d\n",
177 offset,
178 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
179 return -E1000_ERR_PHY;
180 }
181 *data = (u16)mdic;
182
183 /* Allow some time after each MDIC transaction to avoid
184 * reading duplicate data in the next MDIC transaction.
185 */
186 if (hw->mac.type == e1000_pch2lan)
187 udelay(100);
188
189 return 0;
190}
191
192/**
193 * e1000e_write_phy_reg_mdic - Write MDI control register
194 * @hw: pointer to the HW structure
195 * @offset: register offset to write to
196 * @data: data to write to register at offset
197 *
198 * Writes data to MDI control register in the PHY at offset.
199 **/
200s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
201{
202 struct e1000_phy_info *phy = &hw->phy;
203 u32 i, mdic = 0;
204
205 if (offset > MAX_PHY_REG_ADDRESS) {
206 e_dbg("PHY Address %d is out of range\n", offset);
207 return -E1000_ERR_PARAM;
208 }
209
210 /* Set up Op-code, Phy Address, and register offset in the MDI
211 * Control register. The MAC will take care of interfacing with the
212 * PHY to retrieve the desired data.
213 */
214 mdic = (((u32)data) |
215 (offset << E1000_MDIC_REG_SHIFT) |
216 (phy->addr << E1000_MDIC_PHY_SHIFT) |
217 (E1000_MDIC_OP_WRITE));
218
219 ew32(MDIC, mdic);
220
221 /* Poll the ready bit to see if the MDI read completed
222 * Increasing the time out as testing showed failures with
223 * the lower time out
224 */
225 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
226 udelay(50);
227 mdic = er32(MDIC);
228 if (mdic & E1000_MDIC_READY)
229 break;
230 }
231 if (!(mdic & E1000_MDIC_READY)) {
232 e_dbg("MDI Write did not complete\n");
233 return -E1000_ERR_PHY;
234 }
235 if (mdic & E1000_MDIC_ERROR) {
236 e_dbg("MDI Error\n");
237 return -E1000_ERR_PHY;
238 }
239 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
240 e_dbg("MDI Write offset error - requested %d, returned %d\n",
241 offset,
242 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT);
243 return -E1000_ERR_PHY;
244 }
245
246 /* Allow some time after each MDIC transaction to avoid
247 * reading duplicate data in the next MDIC transaction.
248 */
249 if (hw->mac.type == e1000_pch2lan)
250 udelay(100);
251
252 return 0;
253}
254
255/**
256 * e1000e_read_phy_reg_m88 - Read m88 PHY register
257 * @hw: pointer to the HW structure
258 * @offset: register offset to be read
259 * @data: pointer to the read data
260 *
261 * Acquires semaphore, if necessary, then reads the PHY register at offset
262 * and storing the retrieved information in data. Release any acquired
263 * semaphores before exiting.
264 **/
265s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
266{
267 s32 ret_val;
268
269 ret_val = hw->phy.ops.acquire(hw);
270 if (ret_val)
271 return ret_val;
272
273 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
274 data);
275
276 hw->phy.ops.release(hw);
277
278 return ret_val;
279}
280
281/**
282 * e1000e_write_phy_reg_m88 - Write m88 PHY register
283 * @hw: pointer to the HW structure
284 * @offset: register offset to write to
285 * @data: data to write at register offset
286 *
287 * Acquires semaphore, if necessary, then writes the data to PHY register
288 * at the offset. Release any acquired semaphores before exiting.
289 **/
290s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
291{
292 s32 ret_val;
293
294 ret_val = hw->phy.ops.acquire(hw);
295 if (ret_val)
296 return ret_val;
297
298 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
299 data);
300
301 hw->phy.ops.release(hw);
302
303 return ret_val;
304}
305
306/**
307 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
308 * @hw: pointer to the HW structure
309 * @page: page to set (shifted left when necessary)
310 *
311 * Sets PHY page required for PHY register access. Assumes semaphore is
312 * already acquired. Note, this function sets phy.addr to 1 so the caller
313 * must set it appropriately (if necessary) after this function returns.
314 **/
315s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
316{
317 e_dbg("Setting page 0x%x\n", page);
318
319 hw->phy.addr = 1;
320
321 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
322}
323
324/**
325 * __e1000e_read_phy_reg_igp - Read igp PHY register
326 * @hw: pointer to the HW structure
327 * @offset: register offset to be read
328 * @data: pointer to the read data
329 * @locked: semaphore has already been acquired or not
330 *
331 * Acquires semaphore, if necessary, then reads the PHY register at offset
332 * and stores the retrieved information in data. Release any acquired
333 * semaphores before exiting.
334 **/
335static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
336 bool locked)
337{
338 s32 ret_val = 0;
339
340 if (!locked) {
341 if (!hw->phy.ops.acquire)
342 return 0;
343
344 ret_val = hw->phy.ops.acquire(hw);
345 if (ret_val)
346 return ret_val;
347 }
348
349 if (offset > MAX_PHY_MULTI_PAGE_REG)
350 ret_val = e1000e_write_phy_reg_mdic(hw,
351 IGP01E1000_PHY_PAGE_SELECT,
352 (u16)offset);
353 if (!ret_val)
354 ret_val = e1000e_read_phy_reg_mdic(hw,
355 MAX_PHY_REG_ADDRESS & offset,
356 data);
357 if (!locked)
358 hw->phy.ops.release(hw);
359
360 return ret_val;
361}
362
363/**
364 * e1000e_read_phy_reg_igp - Read igp PHY register
365 * @hw: pointer to the HW structure
366 * @offset: register offset to be read
367 * @data: pointer to the read data
368 *
369 * Acquires semaphore then reads the PHY register at offset and stores the
370 * retrieved information in data.
371 * Release the acquired semaphore before exiting.
372 **/
373s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
374{
375 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
376}
377
378/**
379 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
380 * @hw: pointer to the HW structure
381 * @offset: register offset to be read
382 * @data: pointer to the read data
383 *
384 * Reads the PHY register at offset and stores the retrieved information
385 * in data. Assumes semaphore already acquired.
386 **/
387s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
388{
389 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
390}
391
392/**
393 * e1000e_write_phy_reg_igp - Write igp PHY register
394 * @hw: pointer to the HW structure
395 * @offset: register offset to write to
396 * @data: data to write at register offset
397 * @locked: semaphore has already been acquired or not
398 *
399 * Acquires semaphore, if necessary, then writes the data to PHY register
400 * at the offset. Release any acquired semaphores before exiting.
401 **/
402static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
403 bool locked)
404{
405 s32 ret_val = 0;
406
407 if (!locked) {
408 if (!hw->phy.ops.acquire)
409 return 0;
410
411 ret_val = hw->phy.ops.acquire(hw);
412 if (ret_val)
413 return ret_val;
414 }
415
416 if (offset > MAX_PHY_MULTI_PAGE_REG)
417 ret_val = e1000e_write_phy_reg_mdic(hw,
418 IGP01E1000_PHY_PAGE_SELECT,
419 (u16)offset);
420 if (!ret_val)
421 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
422 offset, data);
423 if (!locked)
424 hw->phy.ops.release(hw);
425
426 return ret_val;
427}
428
429/**
430 * e1000e_write_phy_reg_igp - Write igp PHY register
431 * @hw: pointer to the HW structure
432 * @offset: register offset to write to
433 * @data: data to write at register offset
434 *
435 * Acquires semaphore then writes the data to PHY register
436 * at the offset. Release any acquired semaphores before exiting.
437 **/
438s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
439{
440 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
441}
442
443/**
444 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
445 * @hw: pointer to the HW structure
446 * @offset: register offset to write to
447 * @data: data to write at register offset
448 *
449 * Writes the data to PHY register at the offset.
450 * Assumes semaphore already acquired.
451 **/
452s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
453{
454 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
455}
456
457/**
458 * __e1000_read_kmrn_reg - Read kumeran register
459 * @hw: pointer to the HW structure
460 * @offset: register offset to be read
461 * @data: pointer to the read data
462 * @locked: semaphore has already been acquired or not
463 *
464 * Acquires semaphore, if necessary. Then reads the PHY register at offset
465 * using the kumeran interface. The information retrieved is stored in data.
466 * Release any acquired semaphores before exiting.
467 **/
468static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
469 bool locked)
470{
471 u32 kmrnctrlsta;
472
473 if (!locked) {
474 s32 ret_val = 0;
475
476 if (!hw->phy.ops.acquire)
477 return 0;
478
479 ret_val = hw->phy.ops.acquire(hw);
480 if (ret_val)
481 return ret_val;
482 }
483
484 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
485 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
486 ew32(KMRNCTRLSTA, kmrnctrlsta);
487 e1e_flush();
488
489 udelay(2);
490
491 kmrnctrlsta = er32(KMRNCTRLSTA);
492 *data = (u16)kmrnctrlsta;
493
494 if (!locked)
495 hw->phy.ops.release(hw);
496
497 return 0;
498}
499
500/**
501 * e1000e_read_kmrn_reg - Read kumeran register
502 * @hw: pointer to the HW structure
503 * @offset: register offset to be read
504 * @data: pointer to the read data
505 *
506 * Acquires semaphore then reads the PHY register at offset using the
507 * kumeran interface. The information retrieved is stored in data.
508 * Release the acquired semaphore before exiting.
509 **/
510s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
511{
512 return __e1000_read_kmrn_reg(hw, offset, data, false);
513}
514
515/**
516 * e1000e_read_kmrn_reg_locked - Read kumeran register
517 * @hw: pointer to the HW structure
518 * @offset: register offset to be read
519 * @data: pointer to the read data
520 *
521 * Reads the PHY register at offset using the kumeran interface. The
522 * information retrieved is stored in data.
523 * Assumes semaphore already acquired.
524 **/
525s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
526{
527 return __e1000_read_kmrn_reg(hw, offset, data, true);
528}
529
530/**
531 * __e1000_write_kmrn_reg - Write kumeran register
532 * @hw: pointer to the HW structure
533 * @offset: register offset to write to
534 * @data: data to write at register offset
535 * @locked: semaphore has already been acquired or not
536 *
537 * Acquires semaphore, if necessary. Then write the data to PHY register
538 * at the offset using the kumeran interface. Release any acquired semaphores
539 * before exiting.
540 **/
541static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
542 bool locked)
543{
544 u32 kmrnctrlsta;
545
546 if (!locked) {
547 s32 ret_val = 0;
548
549 if (!hw->phy.ops.acquire)
550 return 0;
551
552 ret_val = hw->phy.ops.acquire(hw);
553 if (ret_val)
554 return ret_val;
555 }
556
557 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
558 E1000_KMRNCTRLSTA_OFFSET) | data;
559 ew32(KMRNCTRLSTA, kmrnctrlsta);
560 e1e_flush();
561
562 udelay(2);
563
564 if (!locked)
565 hw->phy.ops.release(hw);
566
567 return 0;
568}
569
570/**
571 * e1000e_write_kmrn_reg - Write kumeran register
572 * @hw: pointer to the HW structure
573 * @offset: register offset to write to
574 * @data: data to write at register offset
575 *
576 * Acquires semaphore then writes the data to the PHY register at the offset
577 * using the kumeran interface. Release the acquired semaphore before exiting.
578 **/
579s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
580{
581 return __e1000_write_kmrn_reg(hw, offset, data, false);
582}
583
584/**
585 * e1000e_write_kmrn_reg_locked - Write kumeran register
586 * @hw: pointer to the HW structure
587 * @offset: register offset to write to
588 * @data: data to write at register offset
589 *
590 * Write the data to PHY register at the offset using the kumeran interface.
591 * Assumes semaphore already acquired.
592 **/
593s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
594{
595 return __e1000_write_kmrn_reg(hw, offset, data, true);
596}
597
598/**
599 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode
600 * @hw: pointer to the HW structure
601 *
602 * Sets up Master/slave mode
603 **/
604static s32 e1000_set_master_slave_mode(struct e1000_hw *hw)
605{
606 s32 ret_val;
607 u16 phy_data;
608
609 /* Resolve Master/Slave mode */
610 ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data);
611 if (ret_val)
612 return ret_val;
613
614 /* load defaults for future use */
615 hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ?
616 ((phy_data & CTL1000_AS_MASTER) ?
617 e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto;
618
619 switch (hw->phy.ms_type) {
620 case e1000_ms_force_master:
621 phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
622 break;
623 case e1000_ms_force_slave:
624 phy_data |= CTL1000_ENABLE_MASTER;
625 phy_data &= ~(CTL1000_AS_MASTER);
626 break;
627 case e1000_ms_auto:
628 phy_data &= ~CTL1000_ENABLE_MASTER;
629 /* fall-through */
630 default:
631 break;
632 }
633
634 return e1e_wphy(hw, MII_CTRL1000, phy_data);
635}
636
637/**
638 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
639 * @hw: pointer to the HW structure
640 *
641 * Sets up Carrier-sense on Transmit and downshift values.
642 **/
643s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
644{
645 s32 ret_val;
646 u16 phy_data;
647
648 /* Enable CRS on Tx. This must be set for half-duplex operation. */
649 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
650 if (ret_val)
651 return ret_val;
652
653 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
654
655 /* Enable downshift */
656 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
657
658 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
659 if (ret_val)
660 return ret_val;
661
662 /* Set MDI/MDIX mode */
663 ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data);
664 if (ret_val)
665 return ret_val;
666 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
667 /* Options:
668 * 0 - Auto (default)
669 * 1 - MDI mode
670 * 2 - MDI-X mode
671 */
672 switch (hw->phy.mdix) {
673 case 1:
674 break;
675 case 2:
676 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
677 break;
678 case 0:
679 default:
680 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
681 break;
682 }
683 ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data);
684 if (ret_val)
685 return ret_val;
686
687 return e1000_set_master_slave_mode(hw);
688}
689
690/**
691 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
692 * @hw: pointer to the HW structure
693 *
694 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
695 * and downshift values are set also.
696 **/
697s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
698{
699 struct e1000_phy_info *phy = &hw->phy;
700 s32 ret_val;
701 u16 phy_data;
702
703 /* Enable CRS on Tx. This must be set for half-duplex operation. */
704 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
705 if (ret_val)
706 return ret_val;
707
708 /* For BM PHY this bit is downshift enable */
709 if (phy->type != e1000_phy_bm)
710 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
711
712 /* Options:
713 * MDI/MDI-X = 0 (default)
714 * 0 - Auto for all speeds
715 * 1 - MDI mode
716 * 2 - MDI-X mode
717 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
718 */
719 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
720
721 switch (phy->mdix) {
722 case 1:
723 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
724 break;
725 case 2:
726 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
727 break;
728 case 3:
729 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
730 break;
731 case 0:
732 default:
733 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
734 break;
735 }
736
737 /* Options:
738 * disable_polarity_correction = 0 (default)
739 * Automatic Correction for Reversed Cable Polarity
740 * 0 - Disabled
741 * 1 - Enabled
742 */
743 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
744 if (phy->disable_polarity_correction)
745 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
746
747 /* Enable downshift on BM (disabled by default) */
748 if (phy->type == e1000_phy_bm) {
749 /* For 82574/82583, first disable then enable downshift */
750 if (phy->id == BME1000_E_PHY_ID_R2) {
751 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT;
752 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL,
753 phy_data);
754 if (ret_val)
755 return ret_val;
756 /* Commit the changes. */
757 ret_val = phy->ops.commit(hw);
758 if (ret_val) {
759 e_dbg("Error committing the PHY changes\n");
760 return ret_val;
761 }
762 }
763
764 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
765 }
766
767 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
768 if (ret_val)
769 return ret_val;
770
771 if ((phy->type == e1000_phy_m88) &&
772 (phy->revision < E1000_REVISION_4) &&
773 (phy->id != BME1000_E_PHY_ID_R2)) {
774 /* Force TX_CLK in the Extended PHY Specific Control Register
775 * to 25MHz clock.
776 */
777 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
778 if (ret_val)
779 return ret_val;
780
781 phy_data |= M88E1000_EPSCR_TX_CLK_25;
782
783 if ((phy->revision == 2) && (phy->id == M88E1111_I_PHY_ID)) {
784 /* 82573L PHY - set the downshift counter to 5x. */
785 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
786 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
787 } else {
788 /* Configure Master and Slave downshift values */
789 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
790 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
791 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
792 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
793 }
794 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
795 if (ret_val)
796 return ret_val;
797 }
798
799 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
800 /* Set PHY page 0, register 29 to 0x0003 */
801 ret_val = e1e_wphy(hw, 29, 0x0003);
802 if (ret_val)
803 return ret_val;
804
805 /* Set PHY page 0, register 30 to 0x0000 */
806 ret_val = e1e_wphy(hw, 30, 0x0000);
807 if (ret_val)
808 return ret_val;
809 }
810
811 /* Commit the changes. */
812 if (phy->ops.commit) {
813 ret_val = phy->ops.commit(hw);
814 if (ret_val) {
815 e_dbg("Error committing the PHY changes\n");
816 return ret_val;
817 }
818 }
819
820 if (phy->type == e1000_phy_82578) {
821 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
822 if (ret_val)
823 return ret_val;
824
825 /* 82578 PHY - set the downshift count to 1x. */
826 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
827 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
828 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
829 if (ret_val)
830 return ret_val;
831 }
832
833 return 0;
834}
835
836/**
837 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
838 * @hw: pointer to the HW structure
839 *
840 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
841 * igp PHY's.
842 **/
843s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
844{
845 struct e1000_phy_info *phy = &hw->phy;
846 s32 ret_val;
847 u16 data;
848
849 ret_val = e1000_phy_hw_reset(hw);
850 if (ret_val) {
851 e_dbg("Error resetting the PHY.\n");
852 return ret_val;
853 }
854
855 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
856 * timeout issues when LFS is enabled.
857 */
858 msleep(100);
859
860 /* disable lplu d0 during driver init */
861 if (hw->phy.ops.set_d0_lplu_state) {
862 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
863 if (ret_val) {
864 e_dbg("Error Disabling LPLU D0\n");
865 return ret_val;
866 }
867 }
868 /* Configure mdi-mdix settings */
869 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
870 if (ret_val)
871 return ret_val;
872
873 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
874
875 switch (phy->mdix) {
876 case 1:
877 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
878 break;
879 case 2:
880 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
881 break;
882 case 0:
883 default:
884 data |= IGP01E1000_PSCR_AUTO_MDIX;
885 break;
886 }
887 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
888 if (ret_val)
889 return ret_val;
890
891 /* set auto-master slave resolution settings */
892 if (hw->mac.autoneg) {
893 /* when autonegotiation advertisement is only 1000Mbps then we
894 * should disable SmartSpeed and enable Auto MasterSlave
895 * resolution as hardware default.
896 */
897 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
898 /* Disable SmartSpeed */
899 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
900 &data);
901 if (ret_val)
902 return ret_val;
903
904 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
905 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
906 data);
907 if (ret_val)
908 return ret_val;
909
910 /* Set auto Master/Slave resolution process */
911 ret_val = e1e_rphy(hw, MII_CTRL1000, &data);
912 if (ret_val)
913 return ret_val;
914
915 data &= ~CTL1000_ENABLE_MASTER;
916 ret_val = e1e_wphy(hw, MII_CTRL1000, data);
917 if (ret_val)
918 return ret_val;
919 }
920
921 ret_val = e1000_set_master_slave_mode(hw);
922 }
923
924 return ret_val;
925}
926
927/**
928 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
929 * @hw: pointer to the HW structure
930 *
931 * Reads the MII auto-neg advertisement register and/or the 1000T control
932 * register and if the PHY is already setup for auto-negotiation, then
933 * return successful. Otherwise, setup advertisement and flow control to
934 * the appropriate values for the wanted auto-negotiation.
935 **/
936static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
937{
938 struct e1000_phy_info *phy = &hw->phy;
939 s32 ret_val;
940 u16 mii_autoneg_adv_reg;
941 u16 mii_1000t_ctrl_reg = 0;
942
943 phy->autoneg_advertised &= phy->autoneg_mask;
944
945 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
946 ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg);
947 if (ret_val)
948 return ret_val;
949
950 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
951 /* Read the MII 1000Base-T Control Register (Address 9). */
952 ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg);
953 if (ret_val)
954 return ret_val;
955 }
956
957 /* Need to parse both autoneg_advertised and fc and set up
958 * the appropriate PHY registers. First we will parse for
959 * autoneg_advertised software override. Since we can advertise
960 * a plethora of combinations, we need to check each bit
961 * individually.
962 */
963
964 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
965 * Advertisement Register (Address 4) and the 1000 mb speed bits in
966 * the 1000Base-T Control Register (Address 9).
967 */
968 mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL |
969 ADVERTISE_100HALF |
970 ADVERTISE_10FULL | ADVERTISE_10HALF);
971 mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
972
973 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
974
975 /* Do we want to advertise 10 Mb Half Duplex? */
976 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
977 e_dbg("Advertise 10mb Half duplex\n");
978 mii_autoneg_adv_reg |= ADVERTISE_10HALF;
979 }
980
981 /* Do we want to advertise 10 Mb Full Duplex? */
982 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
983 e_dbg("Advertise 10mb Full duplex\n");
984 mii_autoneg_adv_reg |= ADVERTISE_10FULL;
985 }
986
987 /* Do we want to advertise 100 Mb Half Duplex? */
988 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
989 e_dbg("Advertise 100mb Half duplex\n");
990 mii_autoneg_adv_reg |= ADVERTISE_100HALF;
991 }
992
993 /* Do we want to advertise 100 Mb Full Duplex? */
994 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
995 e_dbg("Advertise 100mb Full duplex\n");
996 mii_autoneg_adv_reg |= ADVERTISE_100FULL;
997 }
998
999 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1000 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1001 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1002
1003 /* Do we want to advertise 1000 Mb Full Duplex? */
1004 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1005 e_dbg("Advertise 1000mb Full duplex\n");
1006 mii_1000t_ctrl_reg |= ADVERTISE_1000FULL;
1007 }
1008
1009 /* Check for a software override of the flow control settings, and
1010 * setup the PHY advertisement registers accordingly. If
1011 * auto-negotiation is enabled, then software will have to set the
1012 * "PAUSE" bits to the correct value in the Auto-Negotiation
1013 * Advertisement Register (MII_ADVERTISE) and re-start auto-
1014 * negotiation.
1015 *
1016 * The possible values of the "fc" parameter are:
1017 * 0: Flow control is completely disabled
1018 * 1: Rx flow control is enabled (we can receive pause frames
1019 * but not send pause frames).
1020 * 2: Tx flow control is enabled (we can send pause frames
1021 * but we do not support receiving pause frames).
1022 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1023 * other: No software override. The flow control configuration
1024 * in the EEPROM is used.
1025 */
1026 switch (hw->fc.current_mode) {
1027 case e1000_fc_none:
1028 /* Flow control (Rx & Tx) is completely disabled by a
1029 * software over-ride.
1030 */
1031 mii_autoneg_adv_reg &=
1032 ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1033 break;
1034 case e1000_fc_rx_pause:
1035 /* Rx Flow control is enabled, and Tx Flow control is
1036 * disabled, by a software over-ride.
1037 *
1038 * Since there really isn't a way to advertise that we are
1039 * capable of Rx Pause ONLY, we will advertise that we
1040 * support both symmetric and asymmetric Rx PAUSE. Later
1041 * (in e1000e_config_fc_after_link_up) we will disable the
1042 * hw's ability to send PAUSE frames.
1043 */
1044 mii_autoneg_adv_reg |=
1045 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1046 break;
1047 case e1000_fc_tx_pause:
1048 /* Tx Flow control is enabled, and Rx Flow control is
1049 * disabled, by a software over-ride.
1050 */
1051 mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM;
1052 mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP;
1053 break;
1054 case e1000_fc_full:
1055 /* Flow control (both Rx and Tx) is enabled by a software
1056 * over-ride.
1057 */
1058 mii_autoneg_adv_reg |=
1059 (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1060 break;
1061 default:
1062 e_dbg("Flow control param set incorrectly\n");
1063 return -E1000_ERR_CONFIG;
1064 }
1065
1066 ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1067 if (ret_val)
1068 return ret_val;
1069
1070 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1071
1072 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1073 ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg);
1074
1075 return ret_val;
1076}
1077
1078/**
1079 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1080 * @hw: pointer to the HW structure
1081 *
1082 * Performs initial bounds checking on autoneg advertisement parameter, then
1083 * configure to advertise the full capability. Setup the PHY to autoneg
1084 * and restart the negotiation process between the link partner. If
1085 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1086 **/
1087static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1088{
1089 struct e1000_phy_info *phy = &hw->phy;
1090 s32 ret_val;
1091 u16 phy_ctrl;
1092
1093 /* Perform some bounds checking on the autoneg advertisement
1094 * parameter.
1095 */
1096 phy->autoneg_advertised &= phy->autoneg_mask;
1097
1098 /* If autoneg_advertised is zero, we assume it was not defaulted
1099 * by the calling code so we set to advertise full capability.
1100 */
1101 if (!phy->autoneg_advertised)
1102 phy->autoneg_advertised = phy->autoneg_mask;
1103
1104 e_dbg("Reconfiguring auto-neg advertisement params\n");
1105 ret_val = e1000_phy_setup_autoneg(hw);
1106 if (ret_val) {
1107 e_dbg("Error Setting up Auto-Negotiation\n");
1108 return ret_val;
1109 }
1110 e_dbg("Restarting Auto-Neg\n");
1111
1112 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1113 * the Auto Neg Restart bit in the PHY control register.
1114 */
1115 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
1116 if (ret_val)
1117 return ret_val;
1118
1119 phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART);
1120 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
1121 if (ret_val)
1122 return ret_val;
1123
1124 /* Does the user want to wait for Auto-Neg to complete here, or
1125 * check at a later time (for example, callback routine).
1126 */
1127 if (phy->autoneg_wait_to_complete) {
1128 ret_val = e1000_wait_autoneg(hw);
1129 if (ret_val) {
1130 e_dbg("Error while waiting for autoneg to complete\n");
1131 return ret_val;
1132 }
1133 }
1134
1135 hw->mac.get_link_status = true;
1136
1137 return ret_val;
1138}
1139
1140/**
1141 * e1000e_setup_copper_link - Configure copper link settings
1142 * @hw: pointer to the HW structure
1143 *
1144 * Calls the appropriate function to configure the link for auto-neg or forced
1145 * speed and duplex. Then we check for link, once link is established calls
1146 * to configure collision distance and flow control are called. If link is
1147 * not established, we return -E1000_ERR_PHY (-2).
1148 **/
1149s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1150{
1151 s32 ret_val;
1152 bool link;
1153
1154 if (hw->mac.autoneg) {
1155 /* Setup autoneg and flow control advertisement and perform
1156 * autonegotiation.
1157 */
1158 ret_val = e1000_copper_link_autoneg(hw);
1159 if (ret_val)
1160 return ret_val;
1161 } else {
1162 /* PHY will be set to 10H, 10F, 100H or 100F
1163 * depending on user settings.
1164 */
1165 e_dbg("Forcing Speed and Duplex\n");
1166 ret_val = hw->phy.ops.force_speed_duplex(hw);
1167 if (ret_val) {
1168 e_dbg("Error Forcing Speed and Duplex\n");
1169 return ret_val;
1170 }
1171 }
1172
1173 /* Check link status. Wait up to 100 microseconds for link to become
1174 * valid.
1175 */
1176 ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1177 &link);
1178 if (ret_val)
1179 return ret_val;
1180
1181 if (link) {
1182 e_dbg("Valid link established!!!\n");
1183 hw->mac.ops.config_collision_dist(hw);
1184 ret_val = e1000e_config_fc_after_link_up(hw);
1185 } else {
1186 e_dbg("Unable to establish link!!!\n");
1187 }
1188
1189 return ret_val;
1190}
1191
1192/**
1193 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1194 * @hw: pointer to the HW structure
1195 *
1196 * Calls the PHY setup function to force speed and duplex. Clears the
1197 * auto-crossover to force MDI manually. Waits for link and returns
1198 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1199 **/
1200s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1201{
1202 struct e1000_phy_info *phy = &hw->phy;
1203 s32 ret_val;
1204 u16 phy_data;
1205 bool link;
1206
1207 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1208 if (ret_val)
1209 return ret_val;
1210
1211 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1212
1213 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1214 if (ret_val)
1215 return ret_val;
1216
1217 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1218 * forced whenever speed and duplex are forced.
1219 */
1220 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1221 if (ret_val)
1222 return ret_val;
1223
1224 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1225 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1226
1227 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1228 if (ret_val)
1229 return ret_val;
1230
1231 e_dbg("IGP PSCR: %X\n", phy_data);
1232
1233 udelay(1);
1234
1235 if (phy->autoneg_wait_to_complete) {
1236 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1237
1238 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1239 100000, &link);
1240 if (ret_val)
1241 return ret_val;
1242
1243 if (!link)
1244 e_dbg("Link taking longer than expected.\n");
1245
1246 /* Try once more */
1247 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1248 100000, &link);
1249 }
1250
1251 return ret_val;
1252}
1253
1254/**
1255 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1256 * @hw: pointer to the HW structure
1257 *
1258 * Calls the PHY setup function to force speed and duplex. Clears the
1259 * auto-crossover to force MDI manually. Resets the PHY to commit the
1260 * changes. If time expires while waiting for link up, we reset the DSP.
1261 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1262 * successful completion, else return corresponding error code.
1263 **/
1264s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1265{
1266 struct e1000_phy_info *phy = &hw->phy;
1267 s32 ret_val;
1268 u16 phy_data;
1269 bool link;
1270
1271 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1272 * forced whenever speed and duplex are forced.
1273 */
1274 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1275 if (ret_val)
1276 return ret_val;
1277
1278 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1279 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1280 if (ret_val)
1281 return ret_val;
1282
1283 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1284
1285 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
1286 if (ret_val)
1287 return ret_val;
1288
1289 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1290
1291 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
1292 if (ret_val)
1293 return ret_val;
1294
1295 /* Reset the phy to commit changes. */
1296 if (hw->phy.ops.commit) {
1297 ret_val = hw->phy.ops.commit(hw);
1298 if (ret_val)
1299 return ret_val;
1300 }
1301
1302 if (phy->autoneg_wait_to_complete) {
1303 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1304
1305 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1306 100000, &link);
1307 if (ret_val)
1308 return ret_val;
1309
1310 if (!link) {
1311 if (hw->phy.type != e1000_phy_m88) {
1312 e_dbg("Link taking longer than expected.\n");
1313 } else {
1314 /* We didn't get link.
1315 * Reset the DSP and cross our fingers.
1316 */
1317 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1318 0x001d);
1319 if (ret_val)
1320 return ret_val;
1321 ret_val = e1000e_phy_reset_dsp(hw);
1322 if (ret_val)
1323 return ret_val;
1324 }
1325 }
1326
1327 /* Try once more */
1328 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1329 100000, &link);
1330 if (ret_val)
1331 return ret_val;
1332 }
1333
1334 if (hw->phy.type != e1000_phy_m88)
1335 return 0;
1336
1337 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1338 if (ret_val)
1339 return ret_val;
1340
1341 /* Resetting the phy means we need to re-force TX_CLK in the
1342 * Extended PHY Specific Control Register to 25MHz clock from
1343 * the reset value of 2.5MHz.
1344 */
1345 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1346 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1347 if (ret_val)
1348 return ret_val;
1349
1350 /* In addition, we must re-enable CRS on Tx for both half and full
1351 * duplex.
1352 */
1353 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1354 if (ret_val)
1355 return ret_val;
1356
1357 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1358 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1359
1360 return ret_val;
1361}
1362
1363/**
1364 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1365 * @hw: pointer to the HW structure
1366 *
1367 * Forces the speed and duplex settings of the PHY.
1368 * This is a function pointer entry point only called by
1369 * PHY setup routines.
1370 **/
1371s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1372{
1373 struct e1000_phy_info *phy = &hw->phy;
1374 s32 ret_val;
1375 u16 data;
1376 bool link;
1377
1378 ret_val = e1e_rphy(hw, MII_BMCR, &data);
1379 if (ret_val)
1380 return ret_val;
1381
1382 e1000e_phy_force_speed_duplex_setup(hw, &data);
1383
1384 ret_val = e1e_wphy(hw, MII_BMCR, data);
1385 if (ret_val)
1386 return ret_val;
1387
1388 /* Disable MDI-X support for 10/100 */
1389 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1390 if (ret_val)
1391 return ret_val;
1392
1393 data &= ~IFE_PMC_AUTO_MDIX;
1394 data &= ~IFE_PMC_FORCE_MDIX;
1395
1396 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1397 if (ret_val)
1398 return ret_val;
1399
1400 e_dbg("IFE PMC: %X\n", data);
1401
1402 udelay(1);
1403
1404 if (phy->autoneg_wait_to_complete) {
1405 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1406
1407 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1408 100000, &link);
1409 if (ret_val)
1410 return ret_val;
1411
1412 if (!link)
1413 e_dbg("Link taking longer than expected.\n");
1414
1415 /* Try once more */
1416 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1417 100000, &link);
1418 if (ret_val)
1419 return ret_val;
1420 }
1421
1422 return 0;
1423}
1424
1425/**
1426 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1427 * @hw: pointer to the HW structure
1428 * @phy_ctrl: pointer to current value of MII_BMCR
1429 *
1430 * Forces speed and duplex on the PHY by doing the following: disable flow
1431 * control, force speed/duplex on the MAC, disable auto speed detection,
1432 * disable auto-negotiation, configure duplex, configure speed, configure
1433 * the collision distance, write configuration to CTRL register. The
1434 * caller must write to the MII_BMCR register for these settings to
1435 * take affect.
1436 **/
1437void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1438{
1439 struct e1000_mac_info *mac = &hw->mac;
1440 u32 ctrl;
1441
1442 /* Turn off flow control when forcing speed/duplex */
1443 hw->fc.current_mode = e1000_fc_none;
1444
1445 /* Force speed/duplex on the mac */
1446 ctrl = er32(CTRL);
1447 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1448 ctrl &= ~E1000_CTRL_SPD_SEL;
1449
1450 /* Disable Auto Speed Detection */
1451 ctrl &= ~E1000_CTRL_ASDE;
1452
1453 /* Disable autoneg on the phy */
1454 *phy_ctrl &= ~BMCR_ANENABLE;
1455
1456 /* Forcing Full or Half Duplex? */
1457 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1458 ctrl &= ~E1000_CTRL_FD;
1459 *phy_ctrl &= ~BMCR_FULLDPLX;
1460 e_dbg("Half Duplex\n");
1461 } else {
1462 ctrl |= E1000_CTRL_FD;
1463 *phy_ctrl |= BMCR_FULLDPLX;
1464 e_dbg("Full Duplex\n");
1465 }
1466
1467 /* Forcing 10mb or 100mb? */
1468 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1469 ctrl |= E1000_CTRL_SPD_100;
1470 *phy_ctrl |= BMCR_SPEED100;
1471 *phy_ctrl &= ~BMCR_SPEED1000;
1472 e_dbg("Forcing 100mb\n");
1473 } else {
1474 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1475 *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100);
1476 e_dbg("Forcing 10mb\n");
1477 }
1478
1479 hw->mac.ops.config_collision_dist(hw);
1480
1481 ew32(CTRL, ctrl);
1482}
1483
1484/**
1485 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1486 * @hw: pointer to the HW structure
1487 * @active: boolean used to enable/disable lplu
1488 *
1489 * Success returns 0, Failure returns 1
1490 *
1491 * The low power link up (lplu) state is set to the power management level D3
1492 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1493 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1494 * is used during Dx states where the power conservation is most important.
1495 * During driver activity, SmartSpeed should be enabled so performance is
1496 * maintained.
1497 **/
1498s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1499{
1500 struct e1000_phy_info *phy = &hw->phy;
1501 s32 ret_val;
1502 u16 data;
1503
1504 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1505 if (ret_val)
1506 return ret_val;
1507
1508 if (!active) {
1509 data &= ~IGP02E1000_PM_D3_LPLU;
1510 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1511 if (ret_val)
1512 return ret_val;
1513 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1514 * during Dx states where the power conservation is most
1515 * important. During driver activity we should enable
1516 * SmartSpeed, so performance is maintained.
1517 */
1518 if (phy->smart_speed == e1000_smart_speed_on) {
1519 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1520 &data);
1521 if (ret_val)
1522 return ret_val;
1523
1524 data |= IGP01E1000_PSCFR_SMART_SPEED;
1525 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1526 data);
1527 if (ret_val)
1528 return ret_val;
1529 } else if (phy->smart_speed == e1000_smart_speed_off) {
1530 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1531 &data);
1532 if (ret_val)
1533 return ret_val;
1534
1535 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1536 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1537 data);
1538 if (ret_val)
1539 return ret_val;
1540 }
1541 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1542 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1543 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1544 data |= IGP02E1000_PM_D3_LPLU;
1545 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1546 if (ret_val)
1547 return ret_val;
1548
1549 /* When LPLU is enabled, we should disable SmartSpeed */
1550 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1551 if (ret_val)
1552 return ret_val;
1553
1554 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1555 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1556 }
1557
1558 return ret_val;
1559}
1560
1561/**
1562 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1563 * @hw: pointer to the HW structure
1564 *
1565 * Success returns 0, Failure returns 1
1566 *
1567 * A downshift is detected by querying the PHY link health.
1568 **/
1569s32 e1000e_check_downshift(struct e1000_hw *hw)
1570{
1571 struct e1000_phy_info *phy = &hw->phy;
1572 s32 ret_val;
1573 u16 phy_data, offset, mask;
1574
1575 switch (phy->type) {
1576 case e1000_phy_m88:
1577 case e1000_phy_gg82563:
1578 case e1000_phy_bm:
1579 case e1000_phy_82578:
1580 offset = M88E1000_PHY_SPEC_STATUS;
1581 mask = M88E1000_PSSR_DOWNSHIFT;
1582 break;
1583 case e1000_phy_igp_2:
1584 case e1000_phy_igp_3:
1585 offset = IGP01E1000_PHY_LINK_HEALTH;
1586 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1587 break;
1588 default:
1589 /* speed downshift not supported */
1590 phy->speed_downgraded = false;
1591 return 0;
1592 }
1593
1594 ret_val = e1e_rphy(hw, offset, &phy_data);
1595
1596 if (!ret_val)
1597 phy->speed_downgraded = !!(phy_data & mask);
1598
1599 return ret_val;
1600}
1601
1602/**
1603 * e1000_check_polarity_m88 - Checks the polarity.
1604 * @hw: pointer to the HW structure
1605 *
1606 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1607 *
1608 * Polarity is determined based on the PHY specific status register.
1609 **/
1610s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1611{
1612 struct e1000_phy_info *phy = &hw->phy;
1613 s32 ret_val;
1614 u16 data;
1615
1616 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1617
1618 if (!ret_val)
1619 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY)
1620 ? e1000_rev_polarity_reversed
1621 : e1000_rev_polarity_normal);
1622
1623 return ret_val;
1624}
1625
1626/**
1627 * e1000_check_polarity_igp - Checks the polarity.
1628 * @hw: pointer to the HW structure
1629 *
1630 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1631 *
1632 * Polarity is determined based on the PHY port status register, and the
1633 * current speed (since there is no polarity at 100Mbps).
1634 **/
1635s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1636{
1637 struct e1000_phy_info *phy = &hw->phy;
1638 s32 ret_val;
1639 u16 data, offset, mask;
1640
1641 /* Polarity is determined based on the speed of
1642 * our connection.
1643 */
1644 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1645 if (ret_val)
1646 return ret_val;
1647
1648 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1649 IGP01E1000_PSSR_SPEED_1000MBPS) {
1650 offset = IGP01E1000_PHY_PCS_INIT_REG;
1651 mask = IGP01E1000_PHY_POLARITY_MASK;
1652 } else {
1653 /* This really only applies to 10Mbps since
1654 * there is no polarity for 100Mbps (always 0).
1655 */
1656 offset = IGP01E1000_PHY_PORT_STATUS;
1657 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1658 }
1659
1660 ret_val = e1e_rphy(hw, offset, &data);
1661
1662 if (!ret_val)
1663 phy->cable_polarity = ((data & mask)
1664 ? e1000_rev_polarity_reversed
1665 : e1000_rev_polarity_normal);
1666
1667 return ret_val;
1668}
1669
1670/**
1671 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1672 * @hw: pointer to the HW structure
1673 *
1674 * Polarity is determined on the polarity reversal feature being enabled.
1675 **/
1676s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1677{
1678 struct e1000_phy_info *phy = &hw->phy;
1679 s32 ret_val;
1680 u16 phy_data, offset, mask;
1681
1682 /* Polarity is determined based on the reversal feature being enabled.
1683 */
1684 if (phy->polarity_correction) {
1685 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1686 mask = IFE_PESC_POLARITY_REVERSED;
1687 } else {
1688 offset = IFE_PHY_SPECIAL_CONTROL;
1689 mask = IFE_PSC_FORCE_POLARITY;
1690 }
1691
1692 ret_val = e1e_rphy(hw, offset, &phy_data);
1693
1694 if (!ret_val)
1695 phy->cable_polarity = ((phy_data & mask)
1696 ? e1000_rev_polarity_reversed
1697 : e1000_rev_polarity_normal);
1698
1699 return ret_val;
1700}
1701
1702/**
1703 * e1000_wait_autoneg - Wait for auto-neg completion
1704 * @hw: pointer to the HW structure
1705 *
1706 * Waits for auto-negotiation to complete or for the auto-negotiation time
1707 * limit to expire, which ever happens first.
1708 **/
1709static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1710{
1711 s32 ret_val = 0;
1712 u16 i, phy_status;
1713
1714 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1715 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1716 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1717 if (ret_val)
1718 break;
1719 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1720 if (ret_val)
1721 break;
1722 if (phy_status & BMSR_ANEGCOMPLETE)
1723 break;
1724 msleep(100);
1725 }
1726
1727 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1728 * has completed.
1729 */
1730 return ret_val;
1731}
1732
1733/**
1734 * e1000e_phy_has_link_generic - Polls PHY for link
1735 * @hw: pointer to the HW structure
1736 * @iterations: number of times to poll for link
1737 * @usec_interval: delay between polling attempts
1738 * @success: pointer to whether polling was successful or not
1739 *
1740 * Polls the PHY status register for link, 'iterations' number of times.
1741 **/
1742s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1743 u32 usec_interval, bool *success)
1744{
1745 s32 ret_val = 0;
1746 u16 i, phy_status;
1747
1748 *success = false;
1749 for (i = 0; i < iterations; i++) {
1750 /* Some PHYs require the MII_BMSR register to be read
1751 * twice due to the link bit being sticky. No harm doing
1752 * it across the board.
1753 */
1754 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1755 if (ret_val) {
1756 /* If the first read fails, another entity may have
1757 * ownership of the resources, wait and try again to
1758 * see if they have relinquished the resources yet.
1759 */
1760 if (usec_interval >= 1000)
1761 msleep(usec_interval / 1000);
1762 else
1763 udelay(usec_interval);
1764 }
1765 ret_val = e1e_rphy(hw, MII_BMSR, &phy_status);
1766 if (ret_val)
1767 break;
1768 if (phy_status & BMSR_LSTATUS) {
1769 *success = true;
1770 break;
1771 }
1772 if (usec_interval >= 1000)
1773 msleep(usec_interval / 1000);
1774 else
1775 udelay(usec_interval);
1776 }
1777
1778 return ret_val;
1779}
1780
1781/**
1782 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1783 * @hw: pointer to the HW structure
1784 *
1785 * Reads the PHY specific status register to retrieve the cable length
1786 * information. The cable length is determined by averaging the minimum and
1787 * maximum values to get the "average" cable length. The m88 PHY has four
1788 * possible cable length values, which are:
1789 * Register Value Cable Length
1790 * 0 < 50 meters
1791 * 1 50 - 80 meters
1792 * 2 80 - 110 meters
1793 * 3 110 - 140 meters
1794 * 4 > 140 meters
1795 **/
1796s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1797{
1798 struct e1000_phy_info *phy = &hw->phy;
1799 s32 ret_val;
1800 u16 phy_data, index;
1801
1802 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1803 if (ret_val)
1804 return ret_val;
1805
1806 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1807 M88E1000_PSSR_CABLE_LENGTH_SHIFT);
1808
1809 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1)
1810 return -E1000_ERR_PHY;
1811
1812 phy->min_cable_length = e1000_m88_cable_length_table[index];
1813 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1814
1815 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1816
1817 return 0;
1818}
1819
1820/**
1821 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1822 * @hw: pointer to the HW structure
1823 *
1824 * The automatic gain control (agc) normalizes the amplitude of the
1825 * received signal, adjusting for the attenuation produced by the
1826 * cable. By reading the AGC registers, which represent the
1827 * combination of coarse and fine gain value, the value can be put
1828 * into a lookup table to obtain the approximate cable length
1829 * for each channel.
1830 **/
1831s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1832{
1833 struct e1000_phy_info *phy = &hw->phy;
1834 s32 ret_val;
1835 u16 phy_data, i, agc_value = 0;
1836 u16 cur_agc_index, max_agc_index = 0;
1837 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1838 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1839 IGP02E1000_PHY_AGC_A,
1840 IGP02E1000_PHY_AGC_B,
1841 IGP02E1000_PHY_AGC_C,
1842 IGP02E1000_PHY_AGC_D
1843 };
1844
1845 /* Read the AGC registers for all channels */
1846 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1847 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1848 if (ret_val)
1849 return ret_val;
1850
1851 /* Getting bits 15:9, which represent the combination of
1852 * coarse and fine gain values. The result is a number
1853 * that can be put into the lookup table to obtain the
1854 * approximate cable length.
1855 */
1856 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1857 IGP02E1000_AGC_LENGTH_MASK);
1858
1859 /* Array index bound check. */
1860 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1861 (cur_agc_index == 0))
1862 return -E1000_ERR_PHY;
1863
1864 /* Remove min & max AGC values from calculation. */
1865 if (e1000_igp_2_cable_length_table[min_agc_index] >
1866 e1000_igp_2_cable_length_table[cur_agc_index])
1867 min_agc_index = cur_agc_index;
1868 if (e1000_igp_2_cable_length_table[max_agc_index] <
1869 e1000_igp_2_cable_length_table[cur_agc_index])
1870 max_agc_index = cur_agc_index;
1871
1872 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1873 }
1874
1875 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1876 e1000_igp_2_cable_length_table[max_agc_index]);
1877 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1878
1879 /* Calculate cable length with the error range of +/- 10 meters. */
1880 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1881 (agc_value - IGP02E1000_AGC_RANGE) : 0);
1882 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1883
1884 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1885
1886 return 0;
1887}
1888
1889/**
1890 * e1000e_get_phy_info_m88 - Retrieve PHY information
1891 * @hw: pointer to the HW structure
1892 *
1893 * Valid for only copper links. Read the PHY status register (sticky read)
1894 * to verify that link is up. Read the PHY special control register to
1895 * determine the polarity and 10base-T extended distance. Read the PHY
1896 * special status register to determine MDI/MDIx and current speed. If
1897 * speed is 1000, then determine cable length, local and remote receiver.
1898 **/
1899s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1900{
1901 struct e1000_phy_info *phy = &hw->phy;
1902 s32 ret_val;
1903 u16 phy_data;
1904 bool link;
1905
1906 if (phy->media_type != e1000_media_type_copper) {
1907 e_dbg("Phy info is only valid for copper media\n");
1908 return -E1000_ERR_CONFIG;
1909 }
1910
1911 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1912 if (ret_val)
1913 return ret_val;
1914
1915 if (!link) {
1916 e_dbg("Phy info is only valid if link is up\n");
1917 return -E1000_ERR_CONFIG;
1918 }
1919
1920 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1921 if (ret_val)
1922 return ret_val;
1923
1924 phy->polarity_correction = !!(phy_data &
1925 M88E1000_PSCR_POLARITY_REVERSAL);
1926
1927 ret_val = e1000_check_polarity_m88(hw);
1928 if (ret_val)
1929 return ret_val;
1930
1931 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1932 if (ret_val)
1933 return ret_val;
1934
1935 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX);
1936
1937 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1938 ret_val = hw->phy.ops.get_cable_length(hw);
1939 if (ret_val)
1940 return ret_val;
1941
1942 ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data);
1943 if (ret_val)
1944 return ret_val;
1945
1946 phy->local_rx = (phy_data & LPA_1000LOCALRXOK)
1947 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1948
1949 phy->remote_rx = (phy_data & LPA_1000REMRXOK)
1950 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
1951 } else {
1952 /* Set values to "undefined" */
1953 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1954 phy->local_rx = e1000_1000t_rx_status_undefined;
1955 phy->remote_rx = e1000_1000t_rx_status_undefined;
1956 }
1957
1958 return ret_val;
1959}
1960
1961/**
1962 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1963 * @hw: pointer to the HW structure
1964 *
1965 * Read PHY status to determine if link is up. If link is up, then
1966 * set/determine 10base-T extended distance and polarity correction. Read
1967 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1968 * determine on the cable length, local and remote receiver.
1969 **/
1970s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1971{
1972 struct e1000_phy_info *phy = &hw->phy;
1973 s32 ret_val;
1974 u16 data;
1975 bool link;
1976
1977 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1978 if (ret_val)
1979 return ret_val;
1980
1981 if (!link) {
1982 e_dbg("Phy info is only valid if link is up\n");
1983 return -E1000_ERR_CONFIG;
1984 }
1985
1986 phy->polarity_correction = true;
1987
1988 ret_val = e1000_check_polarity_igp(hw);
1989 if (ret_val)
1990 return ret_val;
1991
1992 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1993 if (ret_val)
1994 return ret_val;
1995
1996 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX);
1997
1998 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1999 IGP01E1000_PSSR_SPEED_1000MBPS) {
2000 ret_val = phy->ops.get_cable_length(hw);
2001 if (ret_val)
2002 return ret_val;
2003
2004 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
2005 if (ret_val)
2006 return ret_val;
2007
2008 phy->local_rx = (data & LPA_1000LOCALRXOK)
2009 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2010
2011 phy->remote_rx = (data & LPA_1000REMRXOK)
2012 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
2013 } else {
2014 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2015 phy->local_rx = e1000_1000t_rx_status_undefined;
2016 phy->remote_rx = e1000_1000t_rx_status_undefined;
2017 }
2018
2019 return ret_val;
2020}
2021
2022/**
2023 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2024 * @hw: pointer to the HW structure
2025 *
2026 * Populates "phy" structure with various feature states.
2027 **/
2028s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2029{
2030 struct e1000_phy_info *phy = &hw->phy;
2031 s32 ret_val;
2032 u16 data;
2033 bool link;
2034
2035 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2036 if (ret_val)
2037 return ret_val;
2038
2039 if (!link) {
2040 e_dbg("Phy info is only valid if link is up\n");
2041 return -E1000_ERR_CONFIG;
2042 }
2043
2044 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2045 if (ret_val)
2046 return ret_val;
2047 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2048
2049 if (phy->polarity_correction) {
2050 ret_val = e1000_check_polarity_ife(hw);
2051 if (ret_val)
2052 return ret_val;
2053 } else {
2054 /* Polarity is forced */
2055 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2056 ? e1000_rev_polarity_reversed
2057 : e1000_rev_polarity_normal);
2058 }
2059
2060 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2061 if (ret_val)
2062 return ret_val;
2063
2064 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2065
2066 /* The following parameters are undefined for 10/100 operation. */
2067 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2068 phy->local_rx = e1000_1000t_rx_status_undefined;
2069 phy->remote_rx = e1000_1000t_rx_status_undefined;
2070
2071 return 0;
2072}
2073
2074/**
2075 * e1000e_phy_sw_reset - PHY software reset
2076 * @hw: pointer to the HW structure
2077 *
2078 * Does a software reset of the PHY by reading the PHY control register and
2079 * setting/write the control register reset bit to the PHY.
2080 **/
2081s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2082{
2083 s32 ret_val;
2084 u16 phy_ctrl;
2085
2086 ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl);
2087 if (ret_val)
2088 return ret_val;
2089
2090 phy_ctrl |= BMCR_RESET;
2091 ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl);
2092 if (ret_val)
2093 return ret_val;
2094
2095 udelay(1);
2096
2097 return ret_val;
2098}
2099
2100/**
2101 * e1000e_phy_hw_reset_generic - PHY hardware reset
2102 * @hw: pointer to the HW structure
2103 *
2104 * Verify the reset block is not blocking us from resetting. Acquire
2105 * semaphore (if necessary) and read/set/write the device control reset
2106 * bit in the PHY. Wait the appropriate delay time for the device to
2107 * reset and release the semaphore (if necessary).
2108 **/
2109s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2110{
2111 struct e1000_phy_info *phy = &hw->phy;
2112 s32 ret_val;
2113 u32 ctrl;
2114
2115 if (phy->ops.check_reset_block) {
2116 ret_val = phy->ops.check_reset_block(hw);
2117 if (ret_val)
2118 return 0;
2119 }
2120
2121 ret_val = phy->ops.acquire(hw);
2122 if (ret_val)
2123 return ret_val;
2124
2125 ctrl = er32(CTRL);
2126 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2127 e1e_flush();
2128
2129 udelay(phy->reset_delay_us);
2130
2131 ew32(CTRL, ctrl);
2132 e1e_flush();
2133
2134 usleep_range(150, 300);
2135
2136 phy->ops.release(hw);
2137
2138 return phy->ops.get_cfg_done(hw);
2139}
2140
2141/**
2142 * e1000e_get_cfg_done_generic - Generic configuration done
2143 * @hw: pointer to the HW structure
2144 *
2145 * Generic function to wait 10 milli-seconds for configuration to complete
2146 * and return success.
2147 **/
2148s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw)
2149{
2150 mdelay(10);
2151
2152 return 0;
2153}
2154
2155/**
2156 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2157 * @hw: pointer to the HW structure
2158 *
2159 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2160 **/
2161s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2162{
2163 e_dbg("Running IGP 3 PHY init script\n");
2164
2165 /* PHY init IGP 3 */
2166 /* Enable rise/fall, 10-mode work in class-A */
2167 e1e_wphy(hw, 0x2F5B, 0x9018);
2168 /* Remove all caps from Replica path filter */
2169 e1e_wphy(hw, 0x2F52, 0x0000);
2170 /* Bias trimming for ADC, AFE and Driver (Default) */
2171 e1e_wphy(hw, 0x2FB1, 0x8B24);
2172 /* Increase Hybrid poly bias */
2173 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2174 /* Add 4% to Tx amplitude in Gig mode */
2175 e1e_wphy(hw, 0x2010, 0x10B0);
2176 /* Disable trimming (TTT) */
2177 e1e_wphy(hw, 0x2011, 0x0000);
2178 /* Poly DC correction to 94.6% + 2% for all channels */
2179 e1e_wphy(hw, 0x20DD, 0x249A);
2180 /* ABS DC correction to 95.9% */
2181 e1e_wphy(hw, 0x20DE, 0x00D3);
2182 /* BG temp curve trim */
2183 e1e_wphy(hw, 0x28B4, 0x04CE);
2184 /* Increasing ADC OPAMP stage 1 currents to max */
2185 e1e_wphy(hw, 0x2F70, 0x29E4);
2186 /* Force 1000 ( required for enabling PHY regs configuration) */
2187 e1e_wphy(hw, 0x0000, 0x0140);
2188 /* Set upd_freq to 6 */
2189 e1e_wphy(hw, 0x1F30, 0x1606);
2190 /* Disable NPDFE */
2191 e1e_wphy(hw, 0x1F31, 0xB814);
2192 /* Disable adaptive fixed FFE (Default) */
2193 e1e_wphy(hw, 0x1F35, 0x002A);
2194 /* Enable FFE hysteresis */
2195 e1e_wphy(hw, 0x1F3E, 0x0067);
2196 /* Fixed FFE for short cable lengths */
2197 e1e_wphy(hw, 0x1F54, 0x0065);
2198 /* Fixed FFE for medium cable lengths */
2199 e1e_wphy(hw, 0x1F55, 0x002A);
2200 /* Fixed FFE for long cable lengths */
2201 e1e_wphy(hw, 0x1F56, 0x002A);
2202 /* Enable Adaptive Clip Threshold */
2203 e1e_wphy(hw, 0x1F72, 0x3FB0);
2204 /* AHT reset limit to 1 */
2205 e1e_wphy(hw, 0x1F76, 0xC0FF);
2206 /* Set AHT master delay to 127 msec */
2207 e1e_wphy(hw, 0x1F77, 0x1DEC);
2208 /* Set scan bits for AHT */
2209 e1e_wphy(hw, 0x1F78, 0xF9EF);
2210 /* Set AHT Preset bits */
2211 e1e_wphy(hw, 0x1F79, 0x0210);
2212 /* Change integ_factor of channel A to 3 */
2213 e1e_wphy(hw, 0x1895, 0x0003);
2214 /* Change prop_factor of channels BCD to 8 */
2215 e1e_wphy(hw, 0x1796, 0x0008);
2216 /* Change cg_icount + enable integbp for channels BCD */
2217 e1e_wphy(hw, 0x1798, 0xD008);
2218 /* Change cg_icount + enable integbp + change prop_factor_master
2219 * to 8 for channel A
2220 */
2221 e1e_wphy(hw, 0x1898, 0xD918);
2222 /* Disable AHT in Slave mode on channel A */
2223 e1e_wphy(hw, 0x187A, 0x0800);
2224 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2225 * Enable SPD+B2B
2226 */
2227 e1e_wphy(hw, 0x0019, 0x008D);
2228 /* Enable restart AN on an1000_dis change */
2229 e1e_wphy(hw, 0x001B, 0x2080);
2230 /* Enable wh_fifo read clock in 10/100 modes */
2231 e1e_wphy(hw, 0x0014, 0x0045);
2232 /* Restart AN, Speed selection is 1000 */
2233 e1e_wphy(hw, 0x0000, 0x1340);
2234
2235 return 0;
2236}
2237
2238/**
2239 * e1000e_get_phy_type_from_id - Get PHY type from id
2240 * @phy_id: phy_id read from the phy
2241 *
2242 * Returns the phy type from the id.
2243 **/
2244enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2245{
2246 enum e1000_phy_type phy_type = e1000_phy_unknown;
2247
2248 switch (phy_id) {
2249 case M88E1000_I_PHY_ID:
2250 case M88E1000_E_PHY_ID:
2251 case M88E1111_I_PHY_ID:
2252 case M88E1011_I_PHY_ID:
2253 phy_type = e1000_phy_m88;
2254 break;
2255 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2256 phy_type = e1000_phy_igp_2;
2257 break;
2258 case GG82563_E_PHY_ID:
2259 phy_type = e1000_phy_gg82563;
2260 break;
2261 case IGP03E1000_E_PHY_ID:
2262 phy_type = e1000_phy_igp_3;
2263 break;
2264 case IFE_E_PHY_ID:
2265 case IFE_PLUS_E_PHY_ID:
2266 case IFE_C_E_PHY_ID:
2267 phy_type = e1000_phy_ife;
2268 break;
2269 case BME1000_E_PHY_ID:
2270 case BME1000_E_PHY_ID_R2:
2271 phy_type = e1000_phy_bm;
2272 break;
2273 case I82578_E_PHY_ID:
2274 phy_type = e1000_phy_82578;
2275 break;
2276 case I82577_E_PHY_ID:
2277 phy_type = e1000_phy_82577;
2278 break;
2279 case I82579_E_PHY_ID:
2280 phy_type = e1000_phy_82579;
2281 break;
2282 case I217_E_PHY_ID:
2283 phy_type = e1000_phy_i217;
2284 break;
2285 default:
2286 phy_type = e1000_phy_unknown;
2287 break;
2288 }
2289 return phy_type;
2290}
2291
2292/**
2293 * e1000e_determine_phy_address - Determines PHY address.
2294 * @hw: pointer to the HW structure
2295 *
2296 * This uses a trial and error method to loop through possible PHY
2297 * addresses. It tests each by reading the PHY ID registers and
2298 * checking for a match.
2299 **/
2300s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2301{
2302 u32 phy_addr = 0;
2303 u32 i;
2304 enum e1000_phy_type phy_type = e1000_phy_unknown;
2305
2306 hw->phy.id = phy_type;
2307
2308 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2309 hw->phy.addr = phy_addr;
2310 i = 0;
2311
2312 do {
2313 e1000e_get_phy_id(hw);
2314 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2315
2316 /* If phy_type is valid, break - we found our
2317 * PHY address
2318 */
2319 if (phy_type != e1000_phy_unknown)
2320 return 0;
2321
2322 usleep_range(1000, 2000);
2323 i++;
2324 } while (i < 10);
2325 }
2326
2327 return -E1000_ERR_PHY_TYPE;
2328}
2329
2330/**
2331 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2332 * @page: page to access
2333 *
2334 * Returns the phy address for the page requested.
2335 **/
2336static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2337{
2338 u32 phy_addr = 2;
2339
2340 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2341 phy_addr = 1;
2342
2343 return phy_addr;
2344}
2345
2346/**
2347 * e1000e_write_phy_reg_bm - Write BM PHY register
2348 * @hw: pointer to the HW structure
2349 * @offset: register offset to write to
2350 * @data: data to write at register offset
2351 *
2352 * Acquires semaphore, if necessary, then writes the data to PHY register
2353 * at the offset. Release any acquired semaphores before exiting.
2354 **/
2355s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2356{
2357 s32 ret_val;
2358 u32 page = offset >> IGP_PAGE_SHIFT;
2359
2360 ret_val = hw->phy.ops.acquire(hw);
2361 if (ret_val)
2362 return ret_val;
2363
2364 /* Page 800 works differently than the rest so it has its own func */
2365 if (page == BM_WUC_PAGE) {
2366 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2367 false, false);
2368 goto release;
2369 }
2370
2371 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2372
2373 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2374 u32 page_shift, page_select;
2375
2376 /* Page select is register 31 for phy address 1 and 22 for
2377 * phy address 2 and 3. Page select is shifted only for
2378 * phy address 1.
2379 */
2380 if (hw->phy.addr == 1) {
2381 page_shift = IGP_PAGE_SHIFT;
2382 page_select = IGP01E1000_PHY_PAGE_SELECT;
2383 } else {
2384 page_shift = 0;
2385 page_select = BM_PHY_PAGE_SELECT;
2386 }
2387
2388 /* Page is shifted left, PHY expects (page x 32) */
2389 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2390 (page << page_shift));
2391 if (ret_val)
2392 goto release;
2393 }
2394
2395 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2396 data);
2397
2398release:
2399 hw->phy.ops.release(hw);
2400 return ret_val;
2401}
2402
2403/**
2404 * e1000e_read_phy_reg_bm - Read BM PHY register
2405 * @hw: pointer to the HW structure
2406 * @offset: register offset to be read
2407 * @data: pointer to the read data
2408 *
2409 * Acquires semaphore, if necessary, then reads the PHY register at offset
2410 * and storing the retrieved information in data. Release any acquired
2411 * semaphores before exiting.
2412 **/
2413s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2414{
2415 s32 ret_val;
2416 u32 page = offset >> IGP_PAGE_SHIFT;
2417
2418 ret_val = hw->phy.ops.acquire(hw);
2419 if (ret_val)
2420 return ret_val;
2421
2422 /* Page 800 works differently than the rest so it has its own func */
2423 if (page == BM_WUC_PAGE) {
2424 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2425 true, false);
2426 goto release;
2427 }
2428
2429 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2430
2431 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2432 u32 page_shift, page_select;
2433
2434 /* Page select is register 31 for phy address 1 and 22 for
2435 * phy address 2 and 3. Page select is shifted only for
2436 * phy address 1.
2437 */
2438 if (hw->phy.addr == 1) {
2439 page_shift = IGP_PAGE_SHIFT;
2440 page_select = IGP01E1000_PHY_PAGE_SELECT;
2441 } else {
2442 page_shift = 0;
2443 page_select = BM_PHY_PAGE_SELECT;
2444 }
2445
2446 /* Page is shifted left, PHY expects (page x 32) */
2447 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2448 (page << page_shift));
2449 if (ret_val)
2450 goto release;
2451 }
2452
2453 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2454 data);
2455release:
2456 hw->phy.ops.release(hw);
2457 return ret_val;
2458}
2459
2460/**
2461 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2462 * @hw: pointer to the HW structure
2463 * @offset: register offset to be read
2464 * @data: pointer to the read data
2465 *
2466 * Acquires semaphore, if necessary, then reads the PHY register at offset
2467 * and storing the retrieved information in data. Release any acquired
2468 * semaphores before exiting.
2469 **/
2470s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2471{
2472 s32 ret_val;
2473 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2474
2475 ret_val = hw->phy.ops.acquire(hw);
2476 if (ret_val)
2477 return ret_val;
2478
2479 /* Page 800 works differently than the rest so it has its own func */
2480 if (page == BM_WUC_PAGE) {
2481 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2482 true, false);
2483 goto release;
2484 }
2485
2486 hw->phy.addr = 1;
2487
2488 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2489 /* Page is shifted left, PHY expects (page x 32) */
2490 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2491 page);
2492
2493 if (ret_val)
2494 goto release;
2495 }
2496
2497 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2498 data);
2499release:
2500 hw->phy.ops.release(hw);
2501 return ret_val;
2502}
2503
2504/**
2505 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2506 * @hw: pointer to the HW structure
2507 * @offset: register offset to write to
2508 * @data: data to write at register offset
2509 *
2510 * Acquires semaphore, if necessary, then writes the data to PHY register
2511 * at the offset. Release any acquired semaphores before exiting.
2512 **/
2513s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2514{
2515 s32 ret_val;
2516 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2517
2518 ret_val = hw->phy.ops.acquire(hw);
2519 if (ret_val)
2520 return ret_val;
2521
2522 /* Page 800 works differently than the rest so it has its own func */
2523 if (page == BM_WUC_PAGE) {
2524 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2525 false, false);
2526 goto release;
2527 }
2528
2529 hw->phy.addr = 1;
2530
2531 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2532 /* Page is shifted left, PHY expects (page x 32) */
2533 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2534 page);
2535
2536 if (ret_val)
2537 goto release;
2538 }
2539
2540 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2541 data);
2542
2543release:
2544 hw->phy.ops.release(hw);
2545 return ret_val;
2546}
2547
2548/**
2549 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2550 * @hw: pointer to the HW structure
2551 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2552 *
2553 * Assumes semaphore already acquired and phy_reg points to a valid memory
2554 * address to store contents of the BM_WUC_ENABLE_REG register.
2555 **/
2556s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2557{
2558 s32 ret_val;
2559 u16 temp;
2560
2561 /* All page select, port ctrl and wakeup registers use phy address 1 */
2562 hw->phy.addr = 1;
2563
2564 /* Select Port Control Registers page */
2565 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2566 if (ret_val) {
2567 e_dbg("Could not set Port Control page\n");
2568 return ret_val;
2569 }
2570
2571 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2572 if (ret_val) {
2573 e_dbg("Could not read PHY register %d.%d\n",
2574 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2575 return ret_val;
2576 }
2577
2578 /* Enable both PHY wakeup mode and Wakeup register page writes.
2579 * Prevent a power state change by disabling ME and Host PHY wakeup.
2580 */
2581 temp = *phy_reg;
2582 temp |= BM_WUC_ENABLE_BIT;
2583 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2584
2585 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2586 if (ret_val) {
2587 e_dbg("Could not write PHY register %d.%d\n",
2588 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2589 return ret_val;
2590 }
2591
2592 /* Select Host Wakeup Registers page - caller now able to write
2593 * registers on the Wakeup registers page
2594 */
2595 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2596}
2597
2598/**
2599 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2600 * @hw: pointer to the HW structure
2601 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2602 *
2603 * Restore BM_WUC_ENABLE_REG to its original value.
2604 *
2605 * Assumes semaphore already acquired and *phy_reg is the contents of the
2606 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2607 * caller.
2608 **/
2609s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2610{
2611 s32 ret_val;
2612
2613 /* Select Port Control Registers page */
2614 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2615 if (ret_val) {
2616 e_dbg("Could not set Port Control page\n");
2617 return ret_val;
2618 }
2619
2620 /* Restore 769.17 to its original value */
2621 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2622 if (ret_val)
2623 e_dbg("Could not restore PHY register %d.%d\n",
2624 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2625
2626 return ret_val;
2627}
2628
2629/**
2630 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2631 * @hw: pointer to the HW structure
2632 * @offset: register offset to be read or written
2633 * @data: pointer to the data to read or write
2634 * @read: determines if operation is read or write
2635 * @page_set: BM_WUC_PAGE already set and access enabled
2636 *
2637 * Read the PHY register at offset and store the retrieved information in
2638 * data, or write data to PHY register at offset. Note the procedure to
2639 * access the PHY wakeup registers is different than reading the other PHY
2640 * registers. It works as such:
2641 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2642 * 2) Set page to 800 for host (801 if we were manageability)
2643 * 3) Write the address using the address opcode (0x11)
2644 * 4) Read or write the data using the data opcode (0x12)
2645 * 5) Restore 769.17.2 to its original value
2646 *
2647 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2648 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2649 *
2650 * Assumes semaphore is already acquired. When page_set==true, assumes
2651 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2652 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2653 **/
2654static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2655 u16 *data, bool read, bool page_set)
2656{
2657 s32 ret_val;
2658 u16 reg = BM_PHY_REG_NUM(offset);
2659 u16 page = BM_PHY_REG_PAGE(offset);
2660 u16 phy_reg = 0;
2661
2662 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2663 if ((hw->mac.type == e1000_pchlan) &&
2664 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2665 e_dbg("Attempting to access page %d while gig enabled.\n",
2666 page);
2667
2668 if (!page_set) {
2669 /* Enable access to PHY wakeup registers */
2670 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2671 if (ret_val) {
2672 e_dbg("Could not enable PHY wakeup reg access\n");
2673 return ret_val;
2674 }
2675 }
2676
2677 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2678
2679 /* Write the Wakeup register page offset value using opcode 0x11 */
2680 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2681 if (ret_val) {
2682 e_dbg("Could not write address opcode to page %d\n", page);
2683 return ret_val;
2684 }
2685
2686 if (read) {
2687 /* Read the Wakeup register page value using opcode 0x12 */
2688 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2689 data);
2690 } else {
2691 /* Write the Wakeup register page value using opcode 0x12 */
2692 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2693 *data);
2694 }
2695
2696 if (ret_val) {
2697 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2698 return ret_val;
2699 }
2700
2701 if (!page_set)
2702 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2703
2704 return ret_val;
2705}
2706
2707/**
2708 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2709 * @hw: pointer to the HW structure
2710 *
2711 * In the case of a PHY power down to save power, or to turn off link during a
2712 * driver unload, or wake on lan is not enabled, restore the link to previous
2713 * settings.
2714 **/
2715void e1000_power_up_phy_copper(struct e1000_hw *hw)
2716{
2717 u16 mii_reg = 0;
2718
2719 /* The PHY will retain its settings across a power down/up cycle */
2720 e1e_rphy(hw, MII_BMCR, &mii_reg);
2721 mii_reg &= ~BMCR_PDOWN;
2722 e1e_wphy(hw, MII_BMCR, mii_reg);
2723}
2724
2725/**
2726 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2727 * @hw: pointer to the HW structure
2728 *
2729 * In the case of a PHY power down to save power, or to turn off link during a
2730 * driver unload, or wake on lan is not enabled, restore the link to previous
2731 * settings.
2732 **/
2733void e1000_power_down_phy_copper(struct e1000_hw *hw)
2734{
2735 u16 mii_reg = 0;
2736
2737 /* The PHY will retain its settings across a power down/up cycle */
2738 e1e_rphy(hw, MII_BMCR, &mii_reg);
2739 mii_reg |= BMCR_PDOWN;
2740 e1e_wphy(hw, MII_BMCR, mii_reg);
2741 usleep_range(1000, 2000);
2742}
2743
2744/**
2745 * __e1000_read_phy_reg_hv - Read HV PHY register
2746 * @hw: pointer to the HW structure
2747 * @offset: register offset to be read
2748 * @data: pointer to the read data
2749 * @locked: semaphore has already been acquired or not
2750 *
2751 * Acquires semaphore, if necessary, then reads the PHY register at offset
2752 * and stores the retrieved information in data. Release any acquired
2753 * semaphore before exiting.
2754 **/
2755static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2756 bool locked, bool page_set)
2757{
2758 s32 ret_val;
2759 u16 page = BM_PHY_REG_PAGE(offset);
2760 u16 reg = BM_PHY_REG_NUM(offset);
2761 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2762
2763 if (!locked) {
2764 ret_val = hw->phy.ops.acquire(hw);
2765 if (ret_val)
2766 return ret_val;
2767 }
2768
2769 /* Page 800 works differently than the rest so it has its own func */
2770 if (page == BM_WUC_PAGE) {
2771 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2772 true, page_set);
2773 goto out;
2774 }
2775
2776 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2777 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2778 data, true);
2779 goto out;
2780 }
2781
2782 if (!page_set) {
2783 if (page == HV_INTC_FC_PAGE_START)
2784 page = 0;
2785
2786 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2787 /* Page is shifted left, PHY expects (page x 32) */
2788 ret_val = e1000_set_page_igp(hw,
2789 (page << IGP_PAGE_SHIFT));
2790
2791 hw->phy.addr = phy_addr;
2792
2793 if (ret_val)
2794 goto out;
2795 }
2796 }
2797
2798 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2799 page << IGP_PAGE_SHIFT, reg);
2800
2801 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, data);
2802out:
2803 if (!locked)
2804 hw->phy.ops.release(hw);
2805
2806 return ret_val;
2807}
2808
2809/**
2810 * e1000_read_phy_reg_hv - Read HV PHY register
2811 * @hw: pointer to the HW structure
2812 * @offset: register offset to be read
2813 * @data: pointer to the read data
2814 *
2815 * Acquires semaphore then reads the PHY register at offset and stores
2816 * the retrieved information in data. Release the acquired semaphore
2817 * before exiting.
2818 **/
2819s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2820{
2821 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2822}
2823
2824/**
2825 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2826 * @hw: pointer to the HW structure
2827 * @offset: register offset to be read
2828 * @data: pointer to the read data
2829 *
2830 * Reads the PHY register at offset and stores the retrieved information
2831 * in data. Assumes semaphore already acquired.
2832 **/
2833s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2834{
2835 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2836}
2837
2838/**
2839 * e1000_read_phy_reg_page_hv - Read HV PHY register
2840 * @hw: pointer to the HW structure
2841 * @offset: register offset to write to
2842 * @data: data to write at register offset
2843 *
2844 * Reads the PHY register at offset and stores the retrieved information
2845 * in data. Assumes semaphore already acquired and page already set.
2846 **/
2847s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2848{
2849 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2850}
2851
2852/**
2853 * __e1000_write_phy_reg_hv - Write HV PHY register
2854 * @hw: pointer to the HW structure
2855 * @offset: register offset to write to
2856 * @data: data to write at register offset
2857 * @locked: semaphore has already been acquired or not
2858 *
2859 * Acquires semaphore, if necessary, then writes the data to PHY register
2860 * at the offset. Release any acquired semaphores before exiting.
2861 **/
2862static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2863 bool locked, bool page_set)
2864{
2865 s32 ret_val;
2866 u16 page = BM_PHY_REG_PAGE(offset);
2867 u16 reg = BM_PHY_REG_NUM(offset);
2868 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2869
2870 if (!locked) {
2871 ret_val = hw->phy.ops.acquire(hw);
2872 if (ret_val)
2873 return ret_val;
2874 }
2875
2876 /* Page 800 works differently than the rest so it has its own func */
2877 if (page == BM_WUC_PAGE) {
2878 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2879 false, page_set);
2880 goto out;
2881 }
2882
2883 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2884 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2885 &data, false);
2886 goto out;
2887 }
2888
2889 if (!page_set) {
2890 if (page == HV_INTC_FC_PAGE_START)
2891 page = 0;
2892
2893 /* Workaround MDIO accesses being disabled after entering IEEE
2894 * Power Down (when bit 11 of the PHY Control register is set)
2895 */
2896 if ((hw->phy.type == e1000_phy_82578) &&
2897 (hw->phy.revision >= 1) &&
2898 (hw->phy.addr == 2) &&
2899 !(MAX_PHY_REG_ADDRESS & reg) && (data & BIT(11))) {
2900 u16 data2 = 0x7EFF;
2901
2902 ret_val = e1000_access_phy_debug_regs_hv(hw,
2903 BIT(6) | 0x3,
2904 &data2, false);
2905 if (ret_val)
2906 goto out;
2907 }
2908
2909 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2910 /* Page is shifted left, PHY expects (page x 32) */
2911 ret_val = e1000_set_page_igp(hw,
2912 (page << IGP_PAGE_SHIFT));
2913
2914 hw->phy.addr = phy_addr;
2915
2916 if (ret_val)
2917 goto out;
2918 }
2919 }
2920
2921 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2922 page << IGP_PAGE_SHIFT, reg);
2923
2924 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2925 data);
2926
2927out:
2928 if (!locked)
2929 hw->phy.ops.release(hw);
2930
2931 return ret_val;
2932}
2933
2934/**
2935 * e1000_write_phy_reg_hv - Write HV PHY register
2936 * @hw: pointer to the HW structure
2937 * @offset: register offset to write to
2938 * @data: data to write at register offset
2939 *
2940 * Acquires semaphore then writes the data to PHY register at the offset.
2941 * Release the acquired semaphores before exiting.
2942 **/
2943s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
2944{
2945 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
2946}
2947
2948/**
2949 * e1000_write_phy_reg_hv_locked - Write HV PHY register
2950 * @hw: pointer to the HW structure
2951 * @offset: register offset to write to
2952 * @data: data to write at register offset
2953 *
2954 * Writes the data to PHY register at the offset. Assumes semaphore
2955 * already acquired.
2956 **/
2957s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
2958{
2959 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
2960}
2961
2962/**
2963 * e1000_write_phy_reg_page_hv - Write HV PHY register
2964 * @hw: pointer to the HW structure
2965 * @offset: register offset to write to
2966 * @data: data to write at register offset
2967 *
2968 * Writes the data to PHY register at the offset. Assumes semaphore
2969 * already acquired and page already set.
2970 **/
2971s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
2972{
2973 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
2974}
2975
2976/**
2977 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
2978 * @page: page to be accessed
2979 **/
2980static u32 e1000_get_phy_addr_for_hv_page(u32 page)
2981{
2982 u32 phy_addr = 2;
2983
2984 if (page >= HV_INTC_FC_PAGE_START)
2985 phy_addr = 1;
2986
2987 return phy_addr;
2988}
2989
2990/**
2991 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
2992 * @hw: pointer to the HW structure
2993 * @offset: register offset to be read or written
2994 * @data: pointer to the data to be read or written
2995 * @read: determines if operation is read or write
2996 *
2997 * Reads the PHY register at offset and stores the retreived information
2998 * in data. Assumes semaphore already acquired. Note that the procedure
2999 * to access these regs uses the address port and data port to read/write.
3000 * These accesses done with PHY address 2 and without using pages.
3001 **/
3002static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3003 u16 *data, bool read)
3004{
3005 s32 ret_val;
3006 u32 addr_reg;
3007 u32 data_reg;
3008
3009 /* This takes care of the difference with desktop vs mobile phy */
3010 addr_reg = ((hw->phy.type == e1000_phy_82578) ?
3011 I82578_ADDR_REG : I82577_ADDR_REG);
3012 data_reg = addr_reg + 1;
3013
3014 /* All operations in this function are phy address 2 */
3015 hw->phy.addr = 2;
3016
3017 /* masking with 0x3F to remove the page from offset */
3018 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3019 if (ret_val) {
3020 e_dbg("Could not write the Address Offset port register\n");
3021 return ret_val;
3022 }
3023
3024 /* Read or write the data value next */
3025 if (read)
3026 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3027 else
3028 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3029
3030 if (ret_val)
3031 e_dbg("Could not access the Data port register\n");
3032
3033 return ret_val;
3034}
3035
3036/**
3037 * e1000_link_stall_workaround_hv - Si workaround
3038 * @hw: pointer to the HW structure
3039 *
3040 * This function works around a Si bug where the link partner can get
3041 * a link up indication before the PHY does. If small packets are sent
3042 * by the link partner they can be placed in the packet buffer without
3043 * being properly accounted for by the PHY and will stall preventing
3044 * further packets from being received. The workaround is to clear the
3045 * packet buffer after the PHY detects link up.
3046 **/
3047s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3048{
3049 s32 ret_val = 0;
3050 u16 data;
3051
3052 if (hw->phy.type != e1000_phy_82578)
3053 return 0;
3054
3055 /* Do not apply workaround if in PHY loopback bit 14 set */
3056 e1e_rphy(hw, MII_BMCR, &data);
3057 if (data & BMCR_LOOPBACK)
3058 return 0;
3059
3060 /* check if link is up and at 1Gbps */
3061 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3062 if (ret_val)
3063 return ret_val;
3064
3065 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3066 BM_CS_STATUS_SPEED_MASK);
3067
3068 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3069 BM_CS_STATUS_SPEED_1000))
3070 return 0;
3071
3072 msleep(200);
3073
3074 /* flush the packets in the fifo buffer */
3075 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL,
3076 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3077 HV_MUX_DATA_CTRL_FORCE_SPEED));
3078 if (ret_val)
3079 return ret_val;
3080
3081 return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3082}
3083
3084/**
3085 * e1000_check_polarity_82577 - Checks the polarity.
3086 * @hw: pointer to the HW structure
3087 *
3088 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3089 *
3090 * Polarity is determined based on the PHY specific status register.
3091 **/
3092s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3093{
3094 struct e1000_phy_info *phy = &hw->phy;
3095 s32 ret_val;
3096 u16 data;
3097
3098 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3099
3100 if (!ret_val)
3101 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3102 ? e1000_rev_polarity_reversed
3103 : e1000_rev_polarity_normal);
3104
3105 return ret_val;
3106}
3107
3108/**
3109 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3110 * @hw: pointer to the HW structure
3111 *
3112 * Calls the PHY setup function to force speed and duplex.
3113 **/
3114s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3115{
3116 struct e1000_phy_info *phy = &hw->phy;
3117 s32 ret_val;
3118 u16 phy_data;
3119 bool link;
3120
3121 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
3122 if (ret_val)
3123 return ret_val;
3124
3125 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3126
3127 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
3128 if (ret_val)
3129 return ret_val;
3130
3131 udelay(1);
3132
3133 if (phy->autoneg_wait_to_complete) {
3134 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3135
3136 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3137 100000, &link);
3138 if (ret_val)
3139 return ret_val;
3140
3141 if (!link)
3142 e_dbg("Link taking longer than expected.\n");
3143
3144 /* Try once more */
3145 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3146 100000, &link);
3147 }
3148
3149 return ret_val;
3150}
3151
3152/**
3153 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3154 * @hw: pointer to the HW structure
3155 *
3156 * Read PHY status to determine if link is up. If link is up, then
3157 * set/determine 10base-T extended distance and polarity correction. Read
3158 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3159 * determine on the cable length, local and remote receiver.
3160 **/
3161s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3162{
3163 struct e1000_phy_info *phy = &hw->phy;
3164 s32 ret_val;
3165 u16 data;
3166 bool link;
3167
3168 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3169 if (ret_val)
3170 return ret_val;
3171
3172 if (!link) {
3173 e_dbg("Phy info is only valid if link is up\n");
3174 return -E1000_ERR_CONFIG;
3175 }
3176
3177 phy->polarity_correction = true;
3178
3179 ret_val = e1000_check_polarity_82577(hw);
3180 if (ret_val)
3181 return ret_val;
3182
3183 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3184 if (ret_val)
3185 return ret_val;
3186
3187 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
3188
3189 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3190 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3191 ret_val = hw->phy.ops.get_cable_length(hw);
3192 if (ret_val)
3193 return ret_val;
3194
3195 ret_val = e1e_rphy(hw, MII_STAT1000, &data);
3196 if (ret_val)
3197 return ret_val;
3198
3199 phy->local_rx = (data & LPA_1000LOCALRXOK)
3200 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3201
3202 phy->remote_rx = (data & LPA_1000REMRXOK)
3203 ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
3204 } else {
3205 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3206 phy->local_rx = e1000_1000t_rx_status_undefined;
3207 phy->remote_rx = e1000_1000t_rx_status_undefined;
3208 }
3209
3210 return 0;
3211}
3212
3213/**
3214 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3215 * @hw: pointer to the HW structure
3216 *
3217 * Reads the diagnostic status register and verifies result is valid before
3218 * placing it in the phy_cable_length field.
3219 **/
3220s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3221{
3222 struct e1000_phy_info *phy = &hw->phy;
3223 s32 ret_val;
3224 u16 phy_data, length;
3225
3226 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3227 if (ret_val)
3228 return ret_val;
3229
3230 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3231 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
3232
3233 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3234 return -E1000_ERR_PHY;
3235
3236 phy->cable_length = length;
3237
3238 return 0;
3239}